Power device having reverse-voltage protection

Abstract: In power integrated circuits having both control circuit components and at least one power device, the circuit components are typically isolated from the power device by placing them in separate "wells" of opposite conductivity type to that of the underlying substrate. However, when these power integrated circuits are used in applications (such as automotive electronics) where supply voltage can be inadvertently reversed, large and potentially damaging currents can flow through the circuit components. In order to prevent such large reverse currents from flowing, an additional p-n junction is incorporated within the circuit "well", thus preventing undesirably large reverse current flow. However, introduction of this addition p-n junction creates a vertical transistor within the device, thus creating another potentially damaging current path and also creating potential reverse breakdown voltage problems. In order to alleviate these problems, a reverse voltage protection circuit employing two series-connected MOS switching transistors is used to shunt current away from the base of the vertical transistor. Additionally, the effectiveness of this reverse voltage protection circuit can be improved by the addition of an integrated bias circuit that serves to generate a gate bias voltage that further enhances the breakdown characteristics of the circuit.

Description: The invention is in the field of power devices, and relates specifically to techniques for providing reverse-voltage protection for power integrated circuit (PIC) devices. As noted in "Reverse-Voltage Protection Methods for CMOS Circuits", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February, 1989, it is known to introduce an n+ diffusion into a p-type well in order to create a p-n junction with the appropriate polarity to block excessive current when a reverse-polarity voltage is applied to an integrated circuit. However, it is noted in that publication that this approach has the disadvantage that the additional n+ diffusion forms the emitter of a parasitic vertical bipolar transistor, thus resulting in functional problems during normal operation. For this reason, this approach to the reverse-voltage protection problem was indicated to have been dropped. Various other prior-art reverse-voltage protection circuits, taking different approaches to the problem, are shown in U.S. Patent No. 4,857,985 and European Patent Application No. 0360991. Another approach to reverse-voltage protection, as discussed in the previously-cited IEEE publication, is to diffuse a region into the substrate to form the desired p-n blocking junction. However, this approach also introduces an undesirable parasitic transistor, and in any case this technique cannot be used in VDMOS power integrated circuits because the substrate in such circuits is typically tied to the maximum supply voltage. Yet another known technique for providing reverse-voltage protection is to provide the blocking p-n junction as an external diode, but this approach is clearly undesirable as it requires an extra external component, with the attendant disadvantages of extra cost, space and complexity. A final drawback of existing reverse-voltage protection circuits is that such circuits are not ideally adapted to high power, moderately high voltage operating conditions, such as those typically encountered in automotive operation, where the PIC must survive a reverse voltage of at least 12 volts and operate under forward voltage conditions as high as 35 volts. It is therefore an object of the present invention to provide a power device with a reverse-voltage protection circuit which is fully integrated, which avoids undesirable parasitic-transistor effects, and which can be simply and effectively implemented using conventional technology. It is a further object of the invention to provide a reverse-voltage protection circuit capable of operating in a high-power and moderately high voltage environment without breakdown. In accordance with the invention, these objects are achieved by providing a power integrated circuit device as defined in claim 1. Further embodiments are defined in dependent claims 2-5. Protection is provided by an integrated p-n junction, and in which the undesirable effects of the vertical parasitic transistor created by this junction are minimized by a pair of insulated gate field effect transistors connected in such a manner as to actively shunt current away from the base of the parasitic transistor, thus minimizing its affect on device operation. For operation at relatively high power and moderate voltage levels, the reverse-voltage protection circuit of the invention may further include a bias-voltage generating circuit which enables the reverse-voltage protection circuit to operate at higher voltage levels than would otherwise be possible without incurring breakdown. The reverse-voltage protection circuit is implemented in a power device having a substrate of a first conductivity type, a first, surface-adjoining semiconductor region of a second conductivity type opposite to the first, with at least one low-power circuit element being provided in the first well. A second surface-adjoining semiconductor region of the second conductivity type is provided in the substrate and spaced apart from the first semiconductor region, with at least one power transistor such as a VDMOS transistor being provided in the second semiconductor region. Other types of power transistors that can be used in the device include bipolar transistors, LDMOS transistors, IGBT devices and intelligent power switches. Depending on the particular type of power transistor used, the transistor may be provided either fully or partly in the second semiconductor zone, in accordance with well-known prior art techniques. This circuit configuration provides a power integrated circuit with a reverse-voltage protection circuit and a bias-voltage generating circuit which is fully integrated, simple, compact and efficient in construction, and capable of operating at relatively high power and voltage levels. Fig. 1a is a simplified cross-sectional view of a prior-art power integrated circuit; Fig. 1b is a simplified schematic drawing of the power integrated circuit shown in Fig. 1a; Fig. 2a is a simplified schematic drawing of a prior-art reverse-voltage protection scheme for a portion of the power integrated circuit of Figs. 1a and 1b; Fig. 2b is a simplified circuit diagram of an equivalent circuit for the circuit shown in Fig. 2a; Fig. 3a is a simplified schematic diagram of a voltage protection circuit in accordance with the invention, Fig. 3b is a simplified cross-sectional view of part of a power integrated circuit incorporating the reverse-voltage protection circuit of Fig. 3a; Fig. 4a is a simplified circuit diagram of the reverse-voltage protection circuit of Fig. 3a incorporating a bias-voltage generating circuit in accordance with the invention; and Fig. 4b is a simplified cross-sectional view of a power integrated circuit incorporating the circuit configuration of Fig. 4a. In the drawing, semiconductor zones and regions of like conductivity type are generally shown hatched in the same direction. Additionally, like reference numerals are generally used to identify like regions in different figures of the drawing. Furthermore, it should be noted that the figures are not drawn to scale, and that, in particular, dimensions in the vertical direction have been exaggerated for improved clarity. Fig. 1a of the drawing shows a simplified cross-sectional view of a power integrated circuit (PIC) device 10 of the general type having a substrate 100 of a first conductivity type (herein n-type) a first, surface-adjoining semiconductor region in the form of well 102 of a second conductivity type opposite to the first (herein p-type) and containing various low-power circuits, and a second, surface-adjoining semiconductor region in the form of well 104, also of p-type conductivity, and spaced apart from the first semiconductor region 102, with at least one power transistor (here a VDMOS transistor) being provided at least partly in well 104. The particular nature and configuration of the low-power circuits and the power transistor are not shown in Fig. 1a, as their precise configuration is not critical to the invention. A contact region 106 of p+ conductivity type is provided in semiconductor region 102 for coupling the circuits within that semiconductor region to a power supply terminal (ground) and a similar region 108 is provided in well 104 for coupling the power transistor to ground through a resistor R L . Finally, a contact region 110 is provided on the lower surface of the substrate 10 for connecting the substrate directly to a power supply terminal (V cc ). The p-n junctions between p-type semiconductor regions 102 and 104, respectively, and the n-type substrate 100 are shown schematically by diodes D 2 and D 1 . A simplified schematic diagram of the device of Fig. 1a is shown in Fig. 1b. During normal operation, a positive voltage (typically in the range of 8 to 35 volts) is connected directly to the V cc terminal at the substrate, so that the diodes D 1 and D 2 are reverse biased to prevent unwanted and possibly damaging the current flow through the substrate-well junctions. However, during a reverse-voltage condition, as might typically occur due to an improper connection of battery cables in an automobile, a negative voltage will be applied to the substrate, and diodes D 1 and D 2 will become forward biased, thus permitting current flow as indicated schematically by arrows I 1 and I 2 in Fig. 1b. Although the current through diode D 1 (from the power transistor well) is limited by load resistor R L , the current I 2 (through the circuit well 102) is not limited. Accordingly, large and potentially damaging currents can flow through this circuit path in the event of inadvertent reverse voltage application. One known technique for overcoming this problem is shown in Fig. 2a, where the p-type well 102, instead of being connected directly to ground as in Figs. 1a and 1b, is instead coupled to ground through a p-n junction, shown schematically in Fig. 2a as diode D 3 . Such a diode may be simply formed by providing an n-type zone 112 in the p-type well 102 as shown in Fig. 3b (to be described in further detail hereinafter). However, the disadvantage of this prior-art approach, as noted in the previously-cited IEEE publication, is that the two resulting back-to-back diodes D 2 and D 3 , formed by n-type substrate 100, p-type well 102 and n-type zone 112, form a vertical parasitic transistor shown schematically in Fig. 2b as transistor Q 1 . The introduction of the n-type zone 112 creates two problems. First, current flowing into p-type well 102 is amplified by transistor Q 1 , causing large leakage currents from V cc to ground, which can damage the device. Second, the reverse breakdown voltage of the junction between well 102 and zone 112 is typically fairly low (about 7 volts), and thus not sufficient to sustain the level of reverse voltage protection needed in many applications. In order to provide reverse-voltage protection in PIC devices while at the same time overcoming the disadvantages mentioned above, a circuit such as that shown in Fig. 3a may be used. In this circuit, two series-connected MOS switching transistor, M 1 and M 2 , are connected across the two power supply terminals, with their common intermediate connection being connected to the base of vertical parasitic bipolar transistor Q 1 . In order to relate the schematic diagram of Fig. 3a to the simplified partial cross-sectional view of Fig. 3b, reference numerals designating the three semiconductor regions 112, 102 and 100, forming, respectively, the emitter, base and collector of the transistor Q 1 , are shown in Fig. 3a. In order to automatically shunt current to ground (and therefore away from the base of transistor Q 1 ) the gate electrodes of MOS transistors M 1 and M 2 are connected to V cc and ground, respectively. Thus, under normal (forward voltage) conditions, V cc will be above ground potential, M 2 will be "off' and M 1 will be "on" to provide a relatively low impedance path for shunting current to ground and away from the base of transistor Q 1 . Under reverse-voltage conditions, V cc will be below ground potential, transistor M 1 will be "off' and transistor M 2 will be "on", thus again shunting current away from the base of transistor Q 1 and reducing the adverse effects of the parasitic transistor. By shunting current away from the base of transistor Q 1 its beta is effectively reduced, thereby reducing its collector current and minimizing its impact on circuit operation. The circuit configuration shown in Fig. 3a is capable of reducing the beta of transistor Q 1 by a factor of between about 3 and 10, thus providing a substantial improvement in circuit performance. A physical implementation of the circuit of Fig. 3a is shown in the simplified cross-sectional view of Fig. 3b. In Fig. 3b, the MOS transistors M 1 and M 2 are implemented by highly-doped n-type surface-adjoining zones 112, 114, 116 and 118, which form the source and drain regions of the two transistors. Gate electrodes for transistors M 1 and M 2 are shown in simplified fashion by electrodes 120 and 122, with the two transistors being connected together in series, and to well 102, by highly-doped p-type zone 126 and connection conductor 128. While the circuit shown in Figs. 3a and 3b provides basic reverse-voltage protection, PIC operation at moderately high voltages, such as the typical reverse voltage of -12 volts and typical forward voltage peaks of up to 35 volts encountered in automotive electronics will create a number of problems. More particularly, at forward voltages above about 15 volts, transistor M 2 will be susceptible to drain-to-source breakdown, while the junction between zone 112 and p-type well 102 will be in danger of breakdown at reverse voltage levels above about 7 volts. Additionally, at forward voltages of about 35 volts or higher there is a danger of gate-to-source breakdown in MOS transistor M 1 . In order to overcome these additional problems, related to increased operating and reverse voltage levels, a further embodiment of the invention incorporates a bias-voltage generating circuit used in combination with the reverse-voltage protection circuit previously described. This circuit, shown in Fig. 4a, incorporates the reverse-voltage protection circuit of Fig. 3a in its lower portion and a bias-voltage generating circuit in its upper portion. In the simplified cross-sectional view of Fig. 4b, an implementation of the circuit of Fig. 4a is shown in which the bias-voltage generating circuit is fabricated in a p-type surface-adjoining well adjacent to (but spaced apart from) the well containing the reverse-voltage protection circuit. In the embodiment shown in Fig. 4a, the reverse-voltage protection circuit in the lower portion of the Figure is similar to the circuit shown in Fig. 3a, except that the gate electrode of transistor M 1 , instead of being connected directly to V cc , is instead connected to a terminal V G of the bias-voltage generating circuit. In the bias-voltage generating circuit, bipolar transistor Q 2 represents the vertical parasitic transistor formed in like manner to that of transistor Q 1 , but in p-type well 202 of Fig. 4b. This circuit includes two further MOS transistors, M 3 and M 4 , connected in series between the power supply terminals (V cc and ground), with the common junction between the two series-connected MOS transistors being connected to the base of the parasitic vertical transistor Q 2 . In order to generate the bias voltage, a resistor R B is connected from V cc to bias voltage terminal V G . The bias-voltage generating circuit is completed by a zener diode D Z connected from terminal V G to the base of transistor Q 2 , which corresponds to the p-type well 202. The bias voltage terminal V G is connected to the gate terminals of transistors M 1 and M 3 to provide a bias voltage for these transistors with the zener diode D Z being fabricated in such a manner as to provide a zener bias voltage of about 15 volts. By connecting the gates of transistors M 1 and M 3 to the bias voltage terminal V G of the bias-voltage generating circuit, gate-to-source breakdown in these transistors will be avoided at higher values of V cc . When V cc is less than the zener voltage (here about 15 volts) the voltage at terminal V G is substantially equal to V cc for optimum performance, but when V cc exceeds the zener voltage, V G is clamped to the zener voltage by zener diode D Z , so that the risk of gate-to-source breakdown in transistors M 1 and M 3 is avoided. Fig. 4b shows a simplified cross-sectional view of a structure in accordance with the circuit of Fig. 4a which offers additional protection against component breakdown at higher operating voltages. In Fig. 4b, transistors M 3 and M 4 are configured in the same manner as transistors M 1 and M 2 , and corresponding structural features have accordingly been given reference numerals with the last two digits corresponding to the analogous features of transistors M 1 and M 2 . Transistors M 1 -M 4 in Fig. 4b also correspond to the configuration of transistors M 1 and M 2 as previously described with reference to Fig. 3b (and so will not be further described), with one important exception. In Fig. 4b, the highly-doped n-type zones 112 and 118 have been replaced by similar zones 112a and 118a in p-type well 102 (and zones 212a and 218a in p-type well 202) which are surrounded by less highly-doped n-type drift regions 112b and 118b (212b and 218b in p-type well 202). The purpose of these added drift regions in Fig. 4b is to raise the drain-to-source breakdown voltage of MOS transistor M 2 and increase the collector-to-base breakdown voltage of bipolar transistor Q 1 . In an alternative configuration, p-type wells 102 and 202 may be integrally formed as a single well. This alternative is illustrated by the dashed line 232 in Fig. 4b, which represents the contour of a single well. In this case the surface-adjoining region 234 above the dashed line 232, instead of being n-type, would be homogenous with the p-type wells 102 and 202. If a single well is used, a further simplification can be achieved by using only a single pair of MOS transistors as shown in Fig. 3a, since there is now only a single vertical bipolar parasitic transistor, again as shown in Fig. 3a. In Fig. 4b, zener diode D Z is implemented by adding a highly-doped n-type zone 230, and power supply voltage V cc is supplied to zones 118a and 218a of MOS transistors M 2 and M 4 by a conductor 200. Finally, the resistor R B is shown for simplicity in this embodiment as an externally-provided component, but it may also be integrated into the PIC. Thus, by the use of a bias-voltage generating circuit as shown in Fig. 4a in a structure containing additional drift regions as shown in Fig. 4b, a device configuration is achieved which overcomes all of the previously-mentioned problems associated with relatively high voltage operation of the reverse-voltage protection circuit.

Claims: A power integrated circuit device (10) having a semiconductor substrate (100) of a first conductivity type, a first, surface-adjoining semiconductor well (102) of a second conductivity type opposite to the first conductivity type, at least one low-power circuit element being provided in said first semiconductor well (102), a second, surface-adjoining semiconductor well (104) of said second conductivity type and spaced apart from said first semiconductor well (102), at least one power transistor being provided at least partly in said second semiconductor well (104) with a first power supply terminal electrically connected to the second semiconductor well (104) and a second power supply terminal electrically connected to the substrate, characterized in that said power integrated circuit device (10) comprises a reverse-voltage protection circuit electrically connected to the first and second power supply terminals, said protection circuit comprises: a first insulated gate field effect transistor (M1) having a channel region between first (112) and second (114) surface-adjoining semiconductor regions of the first conductivity type located in the first well, and a gate terminal electrically connected to said second power supply terminal; said first region (112) forming a p-n junction with the first well and being electrically connected to the first power supply terminal, said p-n junction and a further p-n junction between said first well (102) and said substrate (100) together forming a bipolar transistor (Q1) having said first well (102) as a base region, the substrate (100) as a collector region and the first region (112) as an emitter region; and a second insulated gate field effect transistor (M2) having a channel region between third (118) and fourth (116) surface-adjoining semiconductor regions of the first conductivity type located in the first well, and a gate terminal electrically connected to said first power supply terminal; wherein the third region is electrically connected to the second power supply terminal, and the second region is electrically connected to the first well such that the first insulated gate field effect transistor is for providing a main current path between said base and said first region, wherein the fourth region is electrically connected to the first well such that the second insulated gate field effect transistor is for providing a main current path between said base region and said third region. A device (10) as in Claim 1, wherein the gate terminal of said first insulated gate field effect transistor (M1) is connected directly to said second supply terminal. A device (10) as in Claim 1, further comprising a third surface-adjoining semiconductor well (202) of said second conductivity type and spaced apart from said first well and second well (102, 104), a bias-voltage generating circuit at least partly formed in said third semiconductor well (202) and comprising a third insulated gate field effect transistor (M3), a fourth insulated gate field effect transistor (M4), a resistor R B , and a zener diode D z , fifth and sixth regions (212, 218) of said first conductivity type in said third semiconductor well (202) for coupling said third semiconductor well (202) to said first and second power supply terminals, respectively, said fifth region (212), said third well (202) and said substrate (100) together forming a further bipolar transistor (Q2), said third well (202) forming the base region of said further bipolar transistor, said resistor R B being electrically connected from said second power supply terminal to a bias voltage terminal, said zener diode D z being electrically connected from said bias voltage terminal to said third well (202), said third insulated gate field effect transistor (M3) having a gate terminal and a channel region between said third well (202) and said fifth region (212), where this fifth region (212) is electrically connected to the first power supply, said fourth insulated gate field effect transistor (M4) having a gate terminal and a channel region between said third well (202) and said sixth region (218), where the sixth region (218) is electrically connected to the second power supply terminal, the gate terminal of said fourth insulated gate field effect transistor (M4) being electrically connected to said first power supply terminal, and the gate terminals of said first and third insulated gate field effect transistors (M1, M3) being electrically connected to said bias voltage terminal. A device (10) as in Claim 3, wherein each of said fifth and sixth regions (212, 218) of said first conductivity type in said third semiconductor well (202) and wherein each of said first region (112) and third region (118) of said first conductivity type in said first well (102) comprise a surface-adjoining drift region (212b, 218b, 112b, 118b) with a surface-adjoining region (212a, 218a, 112a, 118a) provided therein, said surface-adjoining region (212a, 218a, 112a, 118a) being more highly doped than said surface-adjoining drift region (212b, 218b, 112b, 118b). A device (10) as in Claim 3 or 4, wherein said first and third surface-adjoining wells (102, 202) are integrally formed as a single semiconductor well (232) containing said at least one low-power circuit and at least part of said bias voltage generating circuit.

Inventors: WONG STEPHEN, WONG, STEPHEN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21, H02H11