Charge transfer device equipped with charge signal detector improved in sensitivity as well as in voltage amplification

Abstract: A charge coupled device transfers a charge packet to a floating diffusion region (16) for producing voltage variation therein, and the voltage variation is relayed to an output terminal (OUT) by means of a driving unit (17) implemented by a plurality of source follower circuits (17a/ 17b/ 17c) coupled in cascade, wherein each of the second to final source follower circuits (17b/ 17c) is implemented by a series combination of an enhancement type driving transistor (Q173/ Q175) and an enhancement type load transistor (Q174/ Q176), and the enhancement type load transistor changes the channel conductance thereof complementary to the enhancement type driving transistor under the control of a control unit (18) so as to improve the dynamic range of the output signal thereof without sacrifice of the sensitivity of the floating diffusion region.

Description: FIELD OF THE INVENTION This invention relates to an image sensor and, more particularly, to a charge signal detecting circuit incorporated in the image sensor. DESCRIPTION OF THE RELATED ART A typical example of the charge signal detecting circuit is disclosed by Eiji Oda et. al. in "A 1920 (H) x 1035(V) Pixel High-Definition CCD Image Sensor", IEEE Journal of Solid State Circuits, vol. 24, No. 3, 1989, pages 711 to 717, and the prior art charge detecting circuit is shown in Fig. 1 of the drawings. Referring to Fig. 1, a charge transfer device is fabricated on a single semiconductor chip 1, and the charge transfer device comprises a charge transfer region 2a defined in the semiconductor substrate 1. The charge transfer region 2a forms a shift register 2 together with a plurality of transfer electrodes 1b sequentially applied with a transfer clock signal CLt, and an output electrode 1c is provided between the final stage of the shift register 2 and a floating gate region 3. The shift register 2 is contiguous to the floating diffusion region 3 in the presence of the output signal CLout, and the floating diffusion region 3 is electrically isolated from the semiconductor substrate 1 by means of a p-n junction 4 reversely biased. The floating diffusion region 3 is further coupled with a depletion type field effect transistor 5, and the depletion type field effect transistor 5 is responsive to a reset signal CLr for equalizing the floating diffusion region 3 with a reset voltage level Vrd. The floating diffusion region 3 is further coupled with a driver circuit 6, and the driver circuit 6 comprises three stages of source follower circuits 6a, 6b and 6c coupled in cascade. Each of the source follower circuits 6a to 6c is implemented by a series combination of a driving transistor 6aa and a load transistor 6ab, and the source follower circuits 6a to 6c decrease the output impedance for high speed operation. The driving transistor 6aa of the source follower circuit 6a is gated by the floating diffusion region 3, and the driving transistors 6aa of the source follower circuits 6b and 6c are coupled with the common drain nodes of the previous stages. The common drain node of the source follower circuit 6c is coupled with an output node OUT, and voltage variation due to a charge signal transferred to the floating diffusion region 3 is increased at the output node OUT. The prior art charge transfer device thus arranged behaves as follows. Fig. 2 shows the waveforms of the transfer clock signal CLt, the waveform of the reset signal CLr and the voltage variation in the floating diffusion region 3. Assuming now that the shift register 2 conveys a charge signal or a charge packet, the reset signal CLr is lifted to a high voltage level at time t1, and the depletion type field effect transistor 5 conducts the source of the reset voltage level Vrd to the floating diffusion region 3. For this reason, the floating diffusion region 3 reaches the reset voltage level Vrd by time t2. However, the reset signal CLr is recovered to a low voltage level at time t3, and the floating diffusion region 3 enters a floating state by time t4. Since the output signal CLout has already allowed the output electrode 2c to form a conductive channel to the floating diffusion region 3, the transfer clock signal CLt decayed to the low voltage level allows the shift register 2 to sweep the charge signal into the floating diffusion region 3, and the charge signal thus swept into the floating diffusion region 3 is causative of voltage variation indicated by dVp. The voltage variation at the floating diffusion region 3 is relayed through the source follower circuits 6a to 6c, and an output signal is produced at the output node OUT. The voltage variation dVp is given as follows. dVp = dQ / Ct where dQ is the electric charge of the charge signal, and Ct is the total capacitance coupled with the floating diffusion region 3. The capacitance at the p-n junction 4, the parasitic capacitance at the gate electrode of the driving transistor 6aa of the first emitter follower circuit 6a and the parasitic capacitance of wiring between the floating diffusion region 3 and the driving transistor 6aa form the total capacitance Ct. As will be understood from Equation 1, the smaller the total capacitance Ct is, the larger the voltage variation dVp is. In other words, if the total capacitance Ct is decreased, the floating diffusion region 3 is improved in sensitivity. In general, the parasitic capacitance of the driving transistor 6aa is proportional to the dimensions of the gate electrode or the transistor size, and, for this reason, the driving transistor 6aa of the source follower circuit 6a is implemented by a field effect transistor as small as possible. However, a small sized field effect transistor is also small in current driving capability. In fact, the driving transistor 6aa of the source follower circuit 6a has the ratio of the channel width to the channel length W/L of about 5 micron/4 micron, and, for this reason, the prior art driving circuit 6 is implemented by a multi-stage source follower configuration. However, a problem is encountered in the prior art charge transfer device in voltage amplification. In detail, the source follower circuits 6a to 6c are as small in voltage amplification as 0.85 to 0.90, and only 70 per cent of the voltage variation dVp is transferred to the output node OUT. Of course, if the driving circuit 6 is implemented by only a single stage of source follower circuit, most of the voltage variation is transferred to the output node OUT, and the dynamic range of the output signal is improved. However, this approach encounters another problem in sensitivity of the floating diffusion region 3, because the driving transistor large enough to drive the load at high-speed deteriorates the sensitivity due to large parasitic capacitance coupled to the gate electrode thereof. Thus, there is a trade-off between the sensitivity of the floating diffusion region 3 and the dynamic range of the output signal. SUMMARY OF THE INVENTION It is therefore an important object of the present invention provide a charge transfer device which is large in sensitivity without sacrifice of dynamic range of an output signal. To accomplish the object, the present invention proposes to gate a load transistor complementary to an associated driving transistor. In accordance with the present invention, there is provided a charge transfer device comprising a) a charge transfer line for transferring a charge packet to a final stage thereof, b) a floating diffusion region electrically connectable with the final stage, and allowing a voltage level thereat to vary with the charge packet, c) a driving unit coupled between the floating diffusion region and an output terminal, and implemented by a plurality of source follower circuits coupled in cascade, a first a source follower circuit with a first output node serving as an initial stage of the driving unit being gated by the floating diffusion region and being implemented by a series combination of a first driving transistor, said first output node and a first load transistor coupled between a first source of power voltage level and a second source of power voltage level, the others of the plurality of source follower circuits being respectively implemented by series combinations of other driving transistors, other output nodes and other load transistors coupled between said first source of power voltage level and said second source of power voltage level, each of the output nodes of the plurality of source follower circuits being coupled with a gate electrode of the driving transistor of the next stage or said output terminal, and d) a control signal producing means operative to produce a control signal, and supplying the control signal to gate electrodes of said other load transistors of the others of the plurality of source follower circuits, the control signal allowing said load transistors to change channel conductances thereof in complementary manner with respect to those of the associated other driving transistors. BRIEF DESCRIPTION OF THE DRAWINGS The feature and advantages of the charge transfer device according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram showing the arrangement of the prior art charge transfer device; Fig. 2 is a graph showing the waveforms of essential signals produced in the prior art charge transfer device: Fig. 3 is a circuit diagram showing the circuit arrangement of a charge transfer device according to the present invention; Fig. 4 is a circuit diagram showing a source follower circuit used for evaluation of characteristics; Fig. 5 is a graph showing characteristics of a source follower circuit shown in Fig. 4 Fig. 6 is a graph showing the waveforms at essential nodes in the charge transfer device shown in Fig. 3, and Fig. 7 is a circuit diagram showing the arrangement of another charge transfer device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring to Fig. 3 of the drawings, an image sensor is fabricated on a single semiconductor chip 11, and largely comprises a photo-electric converting region 12, a charge transfer unit 13, and a transfer gate 14 periodically interconnecting the photo-electric converting region 12 and the charge transfer unit 13. The transfer electrode is responsive to a transfer signal TG, and charge packets are periodically read out from the photo-electric converting region 12 to the shift register 15. The charge transfer device comprises a shift register 15, a floating diffusion region 16 associated with a reset transistor 16a, a driving unit 17 coupled between the floating diffusion region 16 and an output terminal OUT, and a control unit 18 provided in association with the driving unit 17. The shift register 15 comprises a charge transfer region 15a formed in the semiconductor substrate 11, and a plurality of transfer gate electrodes 15b opposite to the charge transfer region 15a through a thin gate oxide film (not shown), and a multi-phase transferring clock signal CLt is sequentially supplied to the transfer gate electrodes 15b for conveying the charge packets towards the final stage thereof. An output electrode 15c is further provided over that area between the final stage and the floating diffusion region 16, and is responsive to an output signal CLout for providing a conductive channel therebetween. The floating diffusion region 16 is formed in the semiconductor substrate 11, and is defined by a p-n junction 16b reversely biased. The reset transistor 16a is implemented by a depletion type field effect transistor coupled between a source of resetting voltage level Vrd and the floating diffusion region 16. The driving unit 17 is implemented by a plurality of source follower circuits 17a, 17b and 17c coupled in cascade. The source follower circuit 17a serves as a first stage of the driving unit 17, and is implemented by a series combination of an enhancement type driving transistor Q171, an output node N1 and a depletion type load transistor Q172 coupled between a source of power voltage level Vod and a ground voltage line. The enhancement type driving transistor Q171 is gated by the floating diffusion region 16, and voltage variation in the floating diffusion region 16 is relayed to the output node N1 thereof. The second source follower circuit 17b is implemented by a series combination of an enhancement type driving transistor Q173, an output node N2 and an enhancement type load transistor Q174 coupled between the source of power voltage level Vod and the ground voltage line, and the enhancement type driving transistor Q173 is gated by the output node N1. Similarly, the final source follower circuit 17c is implemented by a series combination of an enhancement type driving transistor Q175, an output node N3 and an enhancement type load transistor Q176 coupled between the source of power voltage level Vod and the ground voltage line, and the enhancement type driving transistor Q175 is gated by the output node N2. The output node N3 is coupled with the output terminal OUT. Thus, the source follower circuits 17a to 17c are coupled in cascade, and the voltage variation in the floating diffusion region 16 is sequentially relayed to the output terminal OUT. The driving transistor Q171 of the first source follower circuit 17a is small enough to maintain the sensitivity of the floating diffusion region 16, and, accordingly, the voltage variation in the floating diffusion region 16 is not less than that of the prior art charge transfer device. The control unit 18 largely comprises a constant voltage source 18a, a level shift circuit 18b and an inverting circuit 18c, and the inverting circuit 18c controls the channel conductances of the enhancement type load transistors Q174 and Q176 by the aid of the constant voltage source 18a and the level shift circuit 18b. In detail, the constant voltage source 18a is implemented by a series combination of an enhancement type load transistor Q177, an output node N4 and a depletion type load transistor Q178 coupled between the source of power voltage level Vod and the ground voltage line, and the gate electrodes of the two load transistors Q177 and Q178 are respectively coupled with the source nodes thereof. Then, a first predetermined constant voltage level lower than the power voltage level Vod is produced at the output node N4. The level shift circuit 18b is implemented by a series combination of an enhancement type first shifting transistor Q179, an output node N5 and an enhancement type second shifting transistor Q180 coupled between the source of power voltage level Vod and the ground voltage line. The enhancement type first shifting transistor Q179 is gated by the output node N1 of the source follower circuit 17a, and the enhancement type second shifting transistor Q180 is gated by the output node N5. The channel conductances of the enhancement type first and second shifting transistors Q179 and Q180 thus arranged are complementarily varied, and the voltage level at the output node N1 is level-shifted to the output node N5. The inverting circuit 18c is implemented by a series combination of an enhancement type load transistor Q181, an output node N6 and an enhancement type third shifting transistor Q182 coupled between the source of power voltage level Vod and the ground voltage line, and the first predetermined constant voltage level at the output node N4 is supplied to the gate electrode of the enhancement type load transistor Q181. Since the enhancement type third shifting transistor Q182 is gated by the output node N5 of the level shift circuit 18b, the inverting circuit 18c produces an control signal CTL with voltage level complementarily varied with respect to the voltage level at the output node N5. The control signal CTL is supplied to the gate electrodes of the enhancement type load transistors Q174 and Q176. Since the voltage level of the control signal CTL is complementarily varied with respect to the voltage level at the node N5, the control signal CTL is of a complementary signal of the output signal of the source follower circuit 17a, and the enhancement type load transistors Q174 and Q176 change the channel conductances thereof in a complementary manner to those of the enhancement type driving transistors Q173 and Q175, respectively. This results in improvement of the dynamic range of the output signal at the output terminal OUT. Fig. 4 shows a source follower circuit implemented by two n-channel enhancement type field effect transistors QA and QB coupled in series, and an input voltage signal IN is supplied to the gate electrode of the enhancement type field effect transistor QA. The gate electrode of the enhancement type field effect transistor QB is supplied with a bias voltage level Vb, and an output voltage signal EX is produced at the common drain node of the two enhancement type field effect transistors QA and QB. Using the source follower circuit shown in Fig. 4, the input voltage-to-output voltage characteristics of the source follower circuit are plotted in Fig. 5. Plots PLA are indicative of the input voltage-to-output voltage characteristics of the source follower circuit in case where the bias voltage Vb is about 2 volts. If the bias voltage Vb is increased to about 3 volts, the input voltage-to-output voltage characteristics trace plots PLB. When the input voltage-to-output voltage characteristics trace plots PLA, the source follower circuit has a gain G of about 0.9. If the bias voltage is increased to about 3.0 volts, the offset voltage is lowered, because much current passes through the enhancement type field effect transistor QB. However, the gain G still remains at 0.9. The present inventor noticed the gain G increasing along dash lines PLC when the bias voltage Vb was decreased from 3 volts to 2 volts. If the bias voltage Vb is decreased between the input voltage signal IN at 10 volts and the input voltage signal IN at 11 volts, the source follower circuit achieves the gain of about 1.5. The present inventor applied the principle described in conjunction with Figs. 4 and 5 to the driving unit 17, and the bias voltage of the load transistors Q174 and Q176 is varied by means of the control unit 18 in complementary manner with respect to the voltage levels applied to the gate electrodes of the driving transistors Q173 and Q175. The circuit behavior of the charge transfer device implementing the first embodiment is hereinbelow described with reference to Fig. 6 of the drawings. In Fig. 6, Plots N1, N2, N3, N5 and N6 are respectively indicative of voltage variations at the output nodes N1, N2, N3, N5 and N6. Assuming now that the voltage level Vp in the floating diffusion region 16 is increased by dVp, the source follower circuit 17a increases the voltage level at the output node N1 by dV1 which is about 90 per cent of the voltage variation dVp at the floating diffusion region 16. Since the voltage variation dV1 is relayed to the level shift circuit 18b, the level shift signal at the output node N5 is increased by dV5, and the inverting circuit 18c decreases the control signal CTL by dV6. The enhancement type driving transistor Q173 increases the channel conductance thereof together with the voltage level at the output node N1, and the enhancement type load transistor Q174 decreases the channel conductance with the control signal CTL decreased by the inverting circuit 18c. Therefore, the source follower circuit 17b increases the gain more than unit as described hereinbefore. In a similar manner, the enhancement type driving transistor Q175 increases the channel conductance thereof together with the output node N2, and the control signal CTL causes the enhancement type load transistor to decrease the channel conductance thereof. Therefore, the source follower circuit 17c also increases the gain greater than 1. Thus, the source follower circuits 17b and 17c increase the respective gains, and the driving unit 17 improves the dynamic range of the output signal at the output terminal OUT. As will be understood from the foregoing description, the source follower circuits 17b and 17c increase the respective gains by virtue of the control signal CTL produced by the control unit 18, and the dynamic range of the output signal is surely improved without sacrifice of the sensitivity of the floating diffusion region 16. Second Embodiment Turning to Fig. 7 of the drawings, another charge transfer device embodying the present invention is illustrated. The charge transfer device implementing the second embodiment is similar to the first embodiment except for a driving unit 27 and a control unit 28, and the other components are labeled with the same references used for the first embodiment. The driving unit 27 is implemented by two source follower circuits 27a and 27b coupled in cascade, and the source follower circuits 27a and 27b are respectively similar in arrangement to the source follower circuits 17a and 17c. The control unit 28 comprises a constant voltage source 28a and an inverting circuit 28b which are similar in circuit arrangement to the constant voltage source 18a and the inverting circuit 18c, respectively. For this reason, component transistors and nodes of those circuits 27a, 27b, 28a and 28c are designated by the same references denoting the corresponding transistors and nodes of the first embodiment without any detailed description. In the second embodiment, a level-shift circuit is deleted from the control unit 28, and the enhancement type shifting transistor Q182 is directly gated by the output node N1 of the source follower circuit 27a. The charge transfer device implementing the second embodiment behaves similar to the first embodiment, and no further description is hereinbelow incorporated for the sake of simplicity. Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made within the scope of the claims.

Claims: A charge transfer device comprising a) a charge transfer line (15) for transferring a charge packet to a final stage thereof, b) a floating diffusion region (16) electrically connectable with said final stage, and allowing a voltage level thereat to vary with said charge packet, and c) a driving unit (17; 27) coupled between said floating diffusion region (16) and an output terminal (OUT), and implemented by a plurality of source follower circuits (17a/ 17b/ 17c; 27a/ 27b) coupled in cascade, a first source follower circuit (17a; 27a) with a first output node (N1) serving as an initial stage of said driving unit (17; 27) being gated by said floating diffusion region (16) and being implemented by a series combination of a first driving transistor (Q 171), said first output node (N1) and a first load transistor (Q 172) coupled between a first source of power voltage level (Vod) and a second source of power voltage level, the others (17b/ 17c; 27b) of said plurality of source follower circuits being respectively implemented by series combinations of other driving transistors (Q173/ Q175), other output nodes (N2/ N3) and other load transistors (Q174/ Q176) coupled between said first source of power voltage level (Vod) and said second source of power voltage level, each of said output nodes (N1/ N2/ N3) of said plurality of source follower circuits (17a/ 17b/ 17c; 27a/ 27b) being coupled with a gate electrode of said driving transistor (Q173/ Q175) of the next stage or said output terminal (OUT), characterized by d) a control signal producing means (18; 28) operative to produce a control signal (CTL), and supplying said control signal to gate electrodes of said other load transistors (Q174/ Q176) of the others of said plurality of source follower circuits (17b/ 17c; 27b), said control signal (CTL) allowing said other load transistors (Q174/ Q176) to change channel conductances thereof in complementary manner with respect to those of said associated other driving transistors (Q173/ Q175). A charge transfer device as set forth in claim 1, in which said other driving transistors (Q173/ Q175) and said other load transistors (Q174/ Q176) of the others of said plurality of source follower circuits (17b/ 17c; 27b) are of an enhancement type. A charge transfer device as set forth in claim 2, in which said control unit (18) comprises a constant voltage source (18a) coupled between said first source of power voltage level (Vod) and said second source of power voltage level for producing a predetermined constant voltage level, a level shift circuit (18b) coupled between said first source of power voltage level (Vod) and said second source of power voltage level, and operative to produce a level-shift signal on the basis of an output signal of said first stage (17a) of said driving unit (17), and an inverting circuit (18c) implemented by a series combination of a load transistor (Q181), an output node (N6) and a shifting transistor (Q182) coupled between said first source of power voltage level and said second source of power voltage level, said load transistor (Q181) of said inverting circuit being gated by said predetermined constant voltage level, said shifting transistor (Q182) being gated by said level-shift signal. A charge transfer device as set forth in claim 3, in which said constant voltage source (18a) is implemented by a series combination of two load transistors (Q177/ Q178) coupled between said first source of power voltage level and said second source of power voltage level, said two load transistors (Q177/ Q178) having respective gate electrodes coupled with said first source of power voltage level and said second source of power voltage level, respectively. A charge transfer device as set forth in claim 3, in which said level shift circuit (18b) is implemented by a series combination of two shifting transistors (Q179/ Q180) coupled between said first source of power voltage level and said second source of power voltage level, one (Q179) of said two shifting transistors having a gate electrode supplied with said output signal of said first stage (17a), the other (Q180) of said two shifting transistors having a gate electrode supplied with said level-shift signal. A charge transfer device as set forth in claim 2, in which said charge transfer device is incorporated in an image sensor. A charge transfer device as set forth in claim 2, in which said control unit (28) comprises a constant voltage source (28a) coupled between said first source of power voltage level (Vod) and said second source of power voltage level for producing a predetermined constant voltage level, and an inverting circuit (28b) implemented by a series combination of a load transistor (Q181), an output node (N6) and a shifting transistor (Q182) coupled between said first source of power voltage level (Vod) and said second source of power voltage level, said load transistor (Q181) of said inverting circuit (28b) being gated by said predetermined constant voltage level, a gate electrode of said shifting transistor (Q182) being supplied with an output signal of said first stage (27a) of said driving unit (27). A charge transfer device as set forth in claim 7, in which said constant voltage source (28a) is implemented by a series combination of two load transistors (Q177/ Q178) coupled between said first source of power voltage level (Vod) and said second source of power voltage level, said two load transistors (Q177/ Q178) having respective gate electrodes coupled with said first source of power voltage level (Vod) and said second source of power voltage level, respectively.

Inventors: MIWADA KAZUO, MIWADA, KAZUO, MIWADA, KAZUO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G11C19
IPC codes: H01L21, H04N5, G11C27, H01L29, G11C19, H03F3