Interface circuit for data transfer

Abstract: An interface circuit capable of performing an exact data transfer between two devices operated by asynchronous two clocks of the same frequency even when the clock contains a jitter, including three-stage latches coupled by a cascade connection and a control circuit to output a one-shot pulse when one external clock and one internal clock are input. The first latch latches input data by the external clock, the second latch latches the data output from the first latch by the pulse of the control circuit, and the third latch latches the data output from the second latch by the internal clock and outputs the data. The input data are output from the third latch in the input order without a continuous or repeated output of the same data or an omission or deletion of the output data.

Description: BACKGROUND OF THE INVENTION The present invention relates to an interface circuit, and more particularly to an interface circuit for performing data input and output between two devices operated by asynchronous two clocks such as internal and external clocks having the same frequency. Description of the Related Arts In Fig. 1, there is shown a conventional input interface circuit for generally performing a data input by an external clock and a data output by an internal clock, which is comprised of a first latch 5 for latching input data by the external clock and a second latch 6 of a master/slave type for latching the data output from the first latch 5 by the internal clock. As described above, in almost all conventional input interface circuits, the data input in synchronism with the external clock are output in synchronism with the internal clock. In this case, when the external clock and the internal clock are overlapped with each other, the master/slave latch as the second latch 6 is used so that the data input to the first latch 5 may not be directly leaked out to the output of the second latch 6. Next, the operation of the conventional input interface circuit described above will now be described in connection with Fig. 2. First, the input data A are latched in the first latch 5 by the external clock. Then, the data A output from the first latch 5 are latched in the second latch 6 by the internal clock, and the second latch 6 outputs the data A. Next, the input data B are latched in the first latch 5 by the external clock. Then, the data B output from the first latch 5 are latched in the second latch 6 by the internal clock, and the second latch 6 outputs the data B. As described above, in the conventional input interface circuit shown in Fig. 1, the input data are consecutively latched from the first latch 5 to the second latch 6, and the data are output from the second latch 6. Hence, even when the external clock contains a jitter of the corresponding internal clock at the previous period, the input data can be successively output from the second latch 6 in synchronism with the internal clock. However, in the conventional input interface circuit shown in Fig. 1, the following problems arise. That is, in case that the external clock contains the jitter with respect to the internal clock, as shown in Fig. 3, when two internal clocks are input to the second latch 6 while no external clock is input to the first latch 5, the second latch 6 latches the data A output from the first latch 5 before the input data A latched in the first latch 5 are renewed to the input data B, and thus the same data A are continuously output from the second latch 6. Further, when two external clocks are input to the first latch 6 while two internal clocks are input to the second latch 6, the input data C are renewed to the input data D in the first latch 5 before the input data C latched in the first latch 5 are not latched in the second latch 6 yet, and then the data D latched in the first latch 5 are latched in the second latch 6. Accordingly, the second latch 6 can not output the data C. That is, in this case, an omission or deletion occurs in the output data with respect to the input data. Patent abstracts of Japan, Vol. 10, No. 20 (E-376) [2077], and JP-A-60180240 disclose a circuit according to the preamble of claim 1. The circuit is a phase correcting circuit including a delay circuit, a pair of latch circuits and a latch signal forming circuit. The latch signal forming circuit is implemented for a comparison between a data clock and a system clock to output an inverted signal of those clocks which is selected in accordance with the result of the comparison. US-A-4935942 discloses a data sampling architecture for sampling incoming asynchronous data pulses and providing synchronous output pulses having a constant pulse width. SUMMARY OF THE INVENTION It is therefore an object of the invention to provide an interface circuit in view of the aforementioned problems of the prior art which is capable of performing an exact data transfer between two devices operated by two asynchronous clocks without any disadvantages such as an omission or deletion of data, a continuous or repeated output of the same data and the like even when the two asynchronous clocks having the same frequency contain a jitter. This object is achieved by an interface circuit as defined in claim 1; the dependent claims are related to further developments of the invention. According to the present invention, the first latch means latches the input data by the first clock signal, the second latch means latches the data output from the first latch means by the pulse generated from the control circuit means by the second clock signal, the third latch means latches the data output from the second latch means by the next second clock signal and outputs the data. As described above, the first, second and third latch means successively latch the data and the third latch means outputs the data. Further, even when the next first clock signal is not input within the period of the second clock signal by a presence of a jitter in the first clock signal after the first clock signal is input, the pulse is output from the control circuit means at the time when the next first clock signal is input, and the second latch means latches the data output from the first latch means. Hence, the second latch means can exactly latch the input data in the input order, and the third latch means can latch the data output from the second latch means by the next second clock signal and outputs the data. Therefore, the input data are output from the interface circuit in the input order, and the continuous or repeated output of the same data and the omission or deletion of the output data can not be caused. BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the present invention will become more apparent from the consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional input interface circuit; Fig. 2 is a timing chart exhibiting an operation of the input interface circuit shown in Fig. 1; Fig. 3 is a timing chart exhibiting an operation of the input interface circuit shown in Fig. 1 when an external clock contains a jitter; Fig. 4 is a block diagram of one embodiment of an input interface circuit according to the present invention; Fig. 5 is a timing chart exhibiting an operation of the input interface circuit shown in Fig. 4; and Fig. 6 is a block diagram of one embodiment of an output interface circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference characters designate like or corresponding parts throughout the views and thus the repeated description thereof can be omitted for brevity, there is shown in Fig. 4 one embodiment of an input interface circuit according to the present invention. As shown in Fig. 4, the input interface circuit comprises a first latch 1 for latching input data by an external clock, a second latch 2 for latching the data output from the first latch 1 by an output signal of a control circuit 4, and a third latch 3 for latching the data output from the second latch 2 by an internal clock. In this embodiment, the input and output terminals of the adjacent two of the first, second and third latches 1, 2 and 3 are coupled with each other by a cascade connection. The control circuit 4 outputs a one-shot pulse within the period of the internal clock whenever one external clock and one internal clock are input. Fig. 5 shows one example of a timing chart of an operation of the interface circuit shown in Fig. 4. The operation of the interface circuit described above will now be described in detail with reference to Fig. 5. First, the input data A are latched in the first latch 1 by the external clock, and the data A output from the first latch 1 are latched in the second latch 2 by the output signal of the control circuit 4. Then, when the internal clock is input to the third latch 3, the data A output from the second latch 2 are latched in the third latch 3, and the third latch 3 outputs the data A. At this time, since the next external clock is already input to the first latch 1, the input data B are latched in the first latch 1. Then, the second latch 2 latches the data B output from the first latch 1 by the output signal of the control circuit 4, and the third latch 3 latches the data B output from the second latch 2 by the next internal clock and outputs the data B. Now, the case where the external clock contains a jitter with respect to the internal clock will be described. First, as shown at a period between the second and third pulses of the internal clock in Fig. 5, when two internal clocks (the second and third pulses) are continuously input to the third latch 3 and the control circuit 4 after the external clock (the second pulse) is input to the first latch 1 and the control circuit 4, the first latch 1 already latched the input data B by the external clock (the second pulse) and the second latch 2 latches the data B output from the first latch 1 by the output signal (the second pulse) generated by the control circuit 4 when the internal clock (the second pulse) is input to the control circuit 4. Hence, after the data A are output from the third latch 3 by the internal clock (the second pulse), the internal clock (the third pulse) is further input to the third latch 3, and the third latch 3 can latch the data B output from the second latch 2 and outputs the data B. Next, as shown at a period between the third and fourth pulses of the external clock in Fig. 5, when two external clocks (the third and fourth pulses) are continuously input to the first latch 1 and the control circuit 4 after the internal clock (the third pulse) is input to the third latch 3 and the control circuit 4, the first latch 1 latches the input data C by the external clock (the third pulse) and the second latch 2 latches the data C output from the first latch 1 by the output signal (the third pulse) of the control circuit 4. Further, when the external clock (the fourth pulse) is input to the first latch 1 and the control circuit 4, the first latch 1 latches the input data D, and then the second latch 2 latches the data D output from the first latch 1 by the output signal (the fourth pulse) generated by the control circuit 4 when the internal clock (the fourth pulse) is input to the control circuit 4. Hence, after the data C are output from the third latch 3 by the internal clock (the fourth pulse), the third latch 3 can latch the data D output from the second latch 2 by the internal clock (the fifth pulse) and outputs the data D. As described above, in this embodiment, even when the external clock contains the jitter of the corresponding internal clock at the previous or following period, the input data can be successively latched in the first, second and third latches 1, 2 and 3, and thus the data can be output in the input order. Hence, the same data can not be continuously or repeatedly output from the input interface circuit, and no omission or deletion occurs in the output data with respect to the input data. In Fig. 6, there is shown one embodiment of an output interface circuit according to the present invention. As shown in Fig. 6, the output interface circuit comprises a first latch 7 for latching output data by an internal clock, a second latch 8 for latching the data output from the first latch 7 by an output signal of a control circuit 10, and a third latch 9 for latching the data output from the second latch 8 by an external clock. In this embodiment, the input and output terminals of the adjacent two of the first, second and third latches 7, 8 and 9 are coupled with each other by a cascade connection. The control circuit 10 outputs a one-shot pulse within the period of the external clock whenever one external clock and one internal clock are input. In this embodiment, by replacing the internal clock with the external clock in the input interface circuit described above, an output interface circuit can be obtained. The operation of this output interface circuit can be performed in the same manner as the input interface circuit. Hence, the input data latched in the first latch 7 by the internal clock can be consecutively latched in the second latch 8 and the third latch 9, and the third latch 9 outputs the data. In this case, a continuous or repeated output of the same data from the output interface circuit, and an occurrence of an omission or deletion of the output data with respect to the input data can be prevented in the same manner as the input interface circuit. As described above, according to the present invention, in the three-stage cascade connection latches, the control circuit controls so that the second latch may latch the data latched in the first latch before the first latch latches the next data and similarly the third latch may latch the data latched in the second latch before the second latch latches the next data so as to output the data in the input order, without outputting the continuous or repeated same data and occurring the omission or deletion of the output data with respect to the input data. Hence, in the interface circuit according to the present invention, even when the external clock contains the jitter of the corresponding internal clock at the previous or following period, an exact data transfer can be performed, and an malfunction due to the jitter can be prevented. While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope of the present invention as defined by the claims.

Claims: An interface circuit for a data transfer from a first device having a first clock signal (EXTERNAL CLOCK; INTERNAL CLOCK) for an operation thereof to a second device having a second clock signal (INTERNAL CLOCK; EXTERNAL CLOCK) for an operation thereof, the first and second signals being asynchronous to each other and identical in frequency to each other, said interface circuit including: first circuit means (1; 7), responsive to the first clock signal, to temporarily hold therein an input data (DATA IN) from the first device to the interface circuit; second circuit means (2; 8), responsive to a one-shot pulse, to latch therein the data as it is output from the first circuit means (1; 7); third circuit means (3, 9), responsive to the second clock signal, to latch therein the data as it is output from the second circuit means (2; 8), the third circuit means (3; 9) being operative to output to the second device the latched data therein as an output data (OUT DATA) of the interface circuit in synchronism with the second clock signal; and fourth circuit means (4; 10) for generating the one-shot pulse in response to a combination of the first and second clock signals, said interface circuit being characterized by: the first circuit means (1, 7) being latch means operative to latch therein the input data (DATA IN; DATA IN) to the interface circuit in response to the first clock signal; and the fourth circuit means (4; 10) being operative to output the one-shot pulse within a period of the second clock signal, whenever an n-th pulse of said first clock signal and an n-th pulse of said second clock signal are both input thereto, where n is an arbitrary integer, so that the input data from the first device to the interface circuit is output to the second device as the output data thereof irrespective of a jitter between the first clock signal and the second clock signal. The interface circuit as claimed in claim 1, wherein the interface circuit is an output interface circuit of the first device, and the first and second clock signals are internal and external clock signals, respectively, of the first device. The interface circuit as claimed in claim 1, wherein the interface circuit is an input interface circuit of the second device, and the first and second clock signals are external and internal clock signals, respectively, of the second device.

Inventors: MATSUMOTO YOSHIMI, MATSUMOTO, YOSHIMI, Matsumoto, Yoshimi, c/o NEC IC Microcomp.Syst.Ltd.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H04L7
IPC codes: H04L7, H04L13, G06F13