An output circuit

Abstract: An output circuit for driving a load connected to an output terminal in accordance with an input signal input to an input terminal, comprises : a first output buffer (6B) wihch operates when activated; a second output buffer (5B) which is connected in parallel to the first output buffer and which , when activated, operates with driving ability higher than the first output buffer; and means (control) for activating the second output buffer for a predetermined period when the input signal is input and, after the period, for activating the first output buffer.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an output circuit for driving a load connected thereto. An output circuit is placed at an output stage of a circuit, such as a memory integrated circuit (IC), and propagates a signal input therefrom out to a load connected to the output circuit. Therefore, a high-speed output circuit with little power consumption and high reliability is in great demand. Description of the Related Art Fig. 1 is a block diagram of a memory IC with a conventional output circuit. An address latch 1a latches an incoming memory address signal to address and read one of a plurality of memory cells constituting a memory cell array 2a. An output data latch 3a latches data read from the cell addressed. An output circuit 4a, which is an output buffer (or buffer amplifier) of low driving ability, outputs the data latched in the output data latch 3a out to (i.e., drive) a load connected thereto. The output circuit 4a may be an output buffer of high driving ability. However, an output buffer of high driving ability flows a large current to drive the load fast and, therefore, consumes a large power and is subject to a damage from a "bus fight". A bus fight is a phenomenon where two signals from output circuits collide and interfere with each other temporarily on a data bus. For the above reasons, an output buffer of low driving ability is usually used for an output circuit to avoid the above-mentioned ill effects of the output buffer of high driving ability. Fig. 2 is a timing chart illustrating an operation of the output circuit in Fig. 1. The address signal An is latched in the address latch 1a at the leading edge of the first clock pulse to address data in the memory cell array 2a. Data read from the memory cell addressed is output via the output circuit 4a as an data-out (Dn) signal. As shown in the Figure, the data-out signal is blunt and unsteady at its leading and trailing edges and, eventually, making propagation delay time (i.e., memory access time T) long. Hereinafter, the access time T is defined, as shown in Fig. 2, as a period from the leading edge of the next clock pulse until the data-out signal becomes steady. The data-out signal becomes blunt and unsteady at the leading and trailing edges because an output buffer of the low driving ability requires time to charge and discharge stray capacitance, for example, connected to the output buffer. Thus, a problem is that the output circuit of the related art, which is made of an output buffer of low driving ability, provides large memory access time T (or propagation delay time) and, therefore decreases processing speeds of a memory device and other logical circuits using such output circuit. There is known from document US-A-4 820 942 an output buffer circuit having two parallel buffers of different characteristics. Document US-A-4 604 731 discloses an output buffer circuit with two parallel connected buffers driven in alternation. SUMMARY OF THE INVENTION It is an object of the present invention to provide an output circuit which is high-speed and less power-consuming. It is another object of the present invention to provide an output circuit which is reliable and trouble-free despite a bus fight. To achieve the above and other objects, the present invention provides a first output buffer, a second output buffer, and activation means. According to the invention defined in claim 1, there is provided an output circuit for driving a load connected to an output terminal thereof in accordance with an input signal to an input terminal thereof. According to another aspect of the invention, defined in claim 3, there is provided a synchronous type memory device employing the output drive circuit defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a memory IC with a conventional output circuit; Fig. 2 is a timing chart illustrating an operation of the output circuit in Fig. 1; Fig. 3 is a block diagram of an output circuit illustrating the principle of the present invention; Fig. 4 is a timing chart illustrating the principle of the present invention; Fig. 5 is a detailed output circuit embodying the present invention; Fig. 6 is a timing chart illustrating an operation of the output circuit shown in Fig. 5; Fig. 7 is a block diagram of a memory device including an output circuit embodying the present invention; and Fig. 8 is a timing chart showing an operation of a memory device embodying the present invention. Throughout the above-mentioned drawings, identical reference numerals are used to designate the same or similar component parts DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 3 is a block diagram of an output circuit illustrating the principle of the present invention. The output circuit is comprised of an output buffer 5B of high driving ability and an output buffer 6B of low driving ability, connected in parallel to each other. A control signal is input to the output buffers 5B and 6B to selectively activate either one of the buffers. A data-in signal is input to the output buffers 5B and 6B, amplified in the output buffer selected by the control signal and output therefrom as a data-out signal. Fig. 4 is a timing chart illustrating the principle of the present invention, which shows a waveform of the data-in, control and the data-out signals to/from the output circuit shown in Fig. 3. Part (a) shows a waveform when the output buffer 6B is selectively activated by the low-active control signal with the signal level low. The waveform of the data-out signal becomes blunt at the leading and trailing edges, eventually increasing propagation delay time as in the prior art. Part (b) shows a waveform when the output buffer 5B is selectively activated by the control signal with the signal level high. Since the output buffer 5B drives the loads connected thereto with a large current, the waveform of the data-out signal provides a sharp rise and fall, thus decreasing propagation delay time. Afterward, when the control signal goes low, the output buffer 6B is activated in turn as shown in part (c), where the output buffer 6B holds the data-out signal level established by the output buffer 5B, while consuming less power than the output buffer 5B. Therefore, the output circuit is free from a damage even when a bus fight occurs at the trailing edge of the data-out signal. Fig. 5 is a detailed output circuit embodying the present invention. Fig. 6 is a timing chart illustrating an operation of the output circuit shown in Fig. 5. The output buffer 6B of low driving ability is comprised of a pair of n-channel MOS transistors Tr1 and Tr2 connected in series, which have larger ohmic resistance and, therefore, are less power-consuming and free from a damage from a bus fight. The output buffer 5B of high driving ability is comprised of a pair of n-channel MOS transistors Tr3 and Tr4 connected in series, which have small ohmic resistance to allow a large current to flow through. A pair of n-channel MOS transistors Tr7 and Tr8 connected in series constitute an inverter. A pair of n-channel MOS transistors Tr5 and Tr6 each act as a gate for activating the output buffer 5B when the control signal is high. (The control signal is input only to the output buffer 5B here because it has practically the same effect as input to both output buffers 5B and 6B, as explained later.) As is apparent from Fig. 5, transistors Tr1-Tr8 are connected in such a way that only one transistor of each pair conducts at a time. When the control signal goes high, depending on the data-in signal being high or low, either transistor Tr5 or Tr6 conducts, then either transistor Tr3 or Tr4 conducts and, as a result, a high or low level is output as the data-out signal, respectively. For example, when the control signal goes high with the data-in signal high, the transistors Tr5 and then Tr3 conduct, a current flows outward from the power source Vcc of the output buffer 5B through Tr3, and a high level is output as the data-out signal. When the control signal goes high with the data-in signal low, the transistors Tr6 and then Tr4 conduct, a current flows from the outside into the ground of the output buffer 5B through Tr4, and a low level is output as the data-out signal. Thus, when the control signal is high, the output buffer 5B of high driving ability is activated to drive the loads including stray capacitance and, therefore, the data-in signal is propagated fast as the data-out signal (shown by the heavy lines in Fig. 6). When the control signal goes low, the transistors Tr5 and Tr6, and then the transistors Tr3 and Tr4 are cut off. In the meantime, depending on the data-in signal being high or low (independently of the control signal), either transistor Tr1 or Tr2 of the output buffer 6B conducts, and a high or low level is output as the data-out signal, respectively. For example, when the data-in signal is high, the transistor Tr1 conducts, a current flows outward from the power source Vcc of the output buffer 6B through Tr1, and a high level is output as the data-out signal. When the data-in signal is low, the transistor Tr2 conducts, a current flows from the outside into the ground of the output buffer 6B through Tr2, and a low level is output as the data-out signal. Thus, once the level of the data-out signal is established by the output buffer 5B of high driving ability, the level is maintained by the output buffer 6B of low driving ability with less power consumption even after the control signal goes low (shown by the fine lines following the heavy ones in Fig. 6). This is because the output buffer 6B need only supply energy required for holding the level. Fig. 7 is a block diagram of a memory device including an output circuit embodying the present invention. For a synchronous-type SRAM including an STRAM (self-timed static RAM) and a static RAM (SRAM) with a built-in address latch, which inputs a clock signal for internal control, the clock signal can be used for the above-mentioned control signal for activating the output buffer 5B. A synchronous-type SRAM chip is given here as an example of the memory device. For easy understanding, only two chips (chips 1 and 2) are given, each including an address latch 11 (21), a memory cell array 12 (22), an output data latch 13 (23) and an output circuit 14 (24). The output circuit 14 (24) includes an output buffer 15 (25) of high driving ability and an output buffer 16 (26) of low driving ability. When low, a low-active chip select signal *CS (mark * represents negation) selects either one of the two memory chips. A memory address signal is input to both chips and latched in the address latch 11 (21) to address and read one of a plurality of memory cells constituting the memory cell array 12 (22). Data read from the cell addressed by the the address latch 11 (21) is latched in the output data latch 13 (23) and then output through the output circuit 14 (24). The outputs of the output circuits 14 and 24 are wire-ORed to form a data bus. Fig. 8 is a timing chart showing an operation of a memory device embodying the present invention. (1) When the chip select signal *CS for the chip 1 (represented as *CS #1) goes low, the incoming memory address signal is latched in the address latch 11 at the leading edge of the clock signal and a memory read operation is started on the memory cell array 12. (2) Subsequently, when the *CS #2 goes low, the memory address signal is latched in the address latch 21 at the leading edge of the clock signal and a memory read operation is started on the memory cell array 22. (3) About one clock cycle later, data read from the chip 1 is latched in the output data latch 13 and the data-out signal (represented as data #1) is output via the output circuit 14 onto the data bus. The data #1 is output via the output buffer 15 of high driving ability while the clock signal is high (shown by a heavy line), and via the output buffer 16 of low driving ability while the clock signal is low (shown by a fine line). (4) Another one clock cycle later when *CS #1 is high, the output circuit 14 disables the output (or put the output in a three state) at the leading edge of the clock pulse. (5) For chip 2, as is the case with chip 1, data #2 is latched in the output data latch 23 and output via the output circuit 24 onto the data bus. The data #2 is output via the output buffer 25 of high driving ability while the clock signal is high (shown by a heavy line), and via the output buffer 26 of low driving ability while the clock signal is low (shown by a fine line). (6) Thus, in the period shown as (6), data #1 and data #2 collide with each other on the data bus, causing a bus fight. However, the bus fight does not cause a damage to the output circuits 14 and 24 because, in this case, the output buffers 16 and 25, each being of low driving ability and high driving ability respectively, are activated together, however, the output buffers 15 and 25, both being of high driving ability, are never activated simultaneously. The largest possible current occurs when data #1 and data #2 are logical 1 (high) and logical 0 (low), respectively. That is, referring to Figs. 5 and 7, the largest current flows from the chip-2 power source Vcc into the chip-1 ground through the chip-2 transistor Tr3, data bus and chip-1 transistor Tr2. That is, assuming that the power source Vcc is plus 5 volts, the ohmic resistance of a transistor (e.g., Tr3) for an output buffer of high driving ability is 5 ohms and that of a transistor (e.g., Tr2) for an output buffer of low driving ability is 95 ohms, only a 50 milli-ampere of current flows through the transistors, without causing a damage to the transistors. Whereas, if a bus fight is caused by two output buffers of high driving ability, a heavy current may flow from a power source Vcc into a ground through two transistors of the respective output buffers, because a transistor used for an output buffer of high driving ability has inherently small ohmic resistance to allow a large current to flow. That is, assuming that the ohmic resistance of a transistor for an output buffer of high driving ability is 5 ohms, a current as large as about 500 milli-amperes may flow through the transistors, causing a damage to the transistors. As is apparent by the above description, an output circuit of the present invention drives the loads first by an output buffer of high driving ability to establish an output level fast and then by that of low driving ability to maintain the level, allowing a high-speed propagation of a signal with less power consumption and without being damaged by a bus fight.

Claims: An output circuit for driving a load connected to an output terminal thereof in accordance with an input signal, including positive logic and negative logic signals, applied to an input terminal thereof, said output circuit comprising : a first output buffer (6B) which is operatively connected to the input and the output terminals, operates when activated and comprises first and second transistors (Tr1, Tr2) connected in series between first and second power sources (Vcc) with a midpoint between said first and said second transistors as an output thereof, said first and said second transistors being responsive to the positive-logic and the negative-logic input signals, respectively; a second output buffer (5B) which is connected in parallel to said first output buffer and, when activated, operates with driving capacity higher than that of said first output buffer, said second buffer including third and fourth transistors (Tr3, Tr4) connected in series between the first and the second power sources (Vcc) with a midpoint between said third and fourth transistors as an output thereof, said third and said fourth transistors each having ohmic resistance smaller than said first and said second transistors; and activation means for activating said second output buffer for a predetermined time period when the input signal is input, and for activating said first output buffer after said predetermined time period wherein said activation means for activating said second output buffer inputs a clock signal and includes fifth and sixth transistors (Tr5, Tr6), said fifth transistor (Tr5) being responsive to the clock signal and the positive-logic input signal and said sixth transistor (Tr6) being responsive to the clock signal and the negative-logic input signal. An output circuit according to claim 1, said third and fourth transistors being responsive to said fifth and said sixth transistors (Tr5, Tr6) respectively. A synchronous-type memory device having input means for receiving a clock signal and comprising an output circuit according to claim 1 or 2 for driving a load connected to an output thereof in accordance with an input signal input to an input terminal thereof, wherein said activation means of said output circuit operate in accordance with a signal level of said clock signal being high or low.

Inventors: MATSUI NORIYUKI, MATSUI, NORIYUKI, Matsui, Noriyuki, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11C7
IPC codes: G11C7, H03K19, G11C11, H03K17