Process for manufacturing MOS-type integrated circuits comprising LOCOS isolation regions

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.

Description: The present invention relates to a process for manufacturing MOS-type integrated circuits. The need for forming large numbers of electrically connected devices on the same substrate requires that the devices be located physically as close together as possible, while at the same time operating independently in the same way as discrete components. For this purpose, special insulating techniques have been devised for minimizing the space required for ensuring correct insulation of adjacent devices, and so enabling a high degree of integration. Reducing the size of each device, in fact, provides for reducing the total area of the integrated circuit, thus enabling a larger number of circuits to be formed on the same wafer, and a substantial reduction in circuit cost. One technique widely used for NMOS, PMOS and CMOS circuits is the LOCOS (LOCal Oxidation of Silicon) technique, which consists in defining the active areas by depositing a layer of nitride; implanting channel stoppers in predetermined regions of the substrate through a mask; and growing the field oxide regions in the portions which are not covered by the nitride layer. The major plus features of the LOCOS technique are: simplicity; the possibility of implanting channel stoppers automatically aligned with the active regions (as required for micrometric and submicrometric technology); and precise definition of the active areas. An example of the LOCOS insulating technique will be described with reference to Fig.s 1-4, which show the formation of an N and P type transistor and EPROM memory cell of an N-well CMOS device. Fig.1 shows an intermediate structure produced by forming N-wells in a P type substrate; growing an oxide layer ("pad oxide"); depositing a layer of nitride; and simultaneously defining the N and P type active areas by masking and subsequently etching the nitride layer. The Fig.1 structure therefore comprises a substrate 1 housing an N-well 2 and selectively covered (in the portions defining the active areas of the finished integrated circuit) with an oxide layer 3, a nitride layer 4, and a resist masking layer 5. At this point, a second masking operation is performed for protecting the N type regions prior to implanting the channel stoppers, and which consists in covering the N-well region with a resist mask 6 (Fig.2), followed by high-energy boron implantation as shown by arrows 7. Implantation and diffusion of the boron ions inside the substrate results in the formation of P + type channel stoppers 8 inside the unmasked portions of the substrate, as shown in Fig.2, at which point, resist layers 6 and 5 are removed, and, via field oxidation, field oxide regions 10 are formed, with intrusion of the oxide beneath the nitride layer along the edge of the active areas (thus forming the so-called "field beak"), as shown in Fig.3. In the example shown, the process continues by removing nitride layer 4; growing a gate oxide layer; depositing and doping (via phosphorus or POCl 3 implantation) a first polysilicon layer; defining said first polysilicon layer in the memory matrix region and the parts of the circuit featuring UPROM (Unerasable Programmable Read Only Memory) cells requiring said first layer for forming the floating gates; growing and removing an oxide layer in the cell-free circuit regions; and depositing a second polysilicon layer using the Double Short Circuited Polysilicon technique whereby the second silicon layer contacts the first in the cell-free circuit regions, and is separated from it in the cell regions by the intermediate oxide layer. The above phases result in the formation of the intermediate structure shown in Fig.4, which presents substrate 1; well 2; field oxide regions 10; channel stoppers 8; gate oxide layer 13; first polysilicon layer 14; intermediate oxide layer 15; and second polysilicon layer 16. For the sake of simplicity, layers 14 and 16 in Fig.4 are also illustrated separately in the circuit region (to the left) where in actual fact they would merge to form the transistor gates. In the LOCOS technique described, high-energy implantation as shown by arrows 7 in Fig.2 provides for raising the turn-on threshold voltage of the parasitic transistors formed by the interconnecting lines over the field oxide regions, and which, in the event of an overly thin field oxide region or insufficient doping of the substrate, may result in inversion of the conductivity of the silicon region underlying the field oxide region, thus reducing or even jeopardizing the electric performance of the finished integrated circuit. As the threshold voltage of the parasitic transistors, however, increases in proportion to doping ion concentration, the above phenomenon is prevented by increasing the doping concentration at the silicon-field-oxide interface, so that the threshold voltage of the parasitic transistors is greater than the maximum operating voltage of the integrated circuit. For this purpose, ions of the same type as the substrate (in this case, boron) are high-energy implanted for ensuring correct isolation and preventing segregation of the doping agent in the oxide during field oxidation. Whereas the threshold voltage of the parasitic transistors increases, the breakdown voltage of the junction formed between the channel stopper and the active areas decreases alongside an increase in doping ion concentration. Moreover, the presence of said junction also creates a parasitic capacitance, due to the depletion region, which is directly proportional to channel stopper concentration close to the active areas. Such conflicting requirements therefore involve a tradeoff, which currently consists in so dosing the channel stopper that the threshold voltage of the parasitic transistor and the breakdown voltage of the junction exceed the maximum voltage of any one part of the device. As already stated, in the LOCOS technique, formation of the channel stoppers beneath the field oxide regions entails an additional masking stage for preventing the N-well regions from also being doped. Though widely used, the LOCOS technique is therefore susceptible to improvement as regards the number of masking stages involved, which substantially affect both manufacturing and finished circuit cost, as well as regards the electric characteristics of the device in terms of the threshold voltage of the parasitic transistor. JP-A-59 178 746 discloses a process for producing MOS-type integrated circuits comprising the steps of: depositing a first layer of semiconductive polycrystalline material on said substrate; selectively removing the first layer of semiconductive polycrystalline material and part of the substrate using a shaping mask; and selectively implanting ions of a selected type of conductivity in the substrate for forming inversion preventing layers (channel stoppers). Then, field insulation regions are grown over the inversion preventing layers and the first layer of polycrystalline material is further shaped through an own mask to form the gate electrode. The article published on IEDM 1983, 5-7 December 1983, p. 526-529 titled "An N-Well CMOS with Self-Aligned Channel Stops" describes a manufacturing method comprising the steps of forming field insulating regions in the substrate, forming and shaping a metal layer having opening over the field insulating regions; implanting boron ions through the field insulating regions for forming channel stoppers. EP-A-0 428 283 discloses a method for local oxidation including performing a field implant through the field insulating regions to enhance isolation for N-channel devices. US-A-4 663 645 discloses a method for manufacturing semiconductor devices including conventional forming of a field insulating film and P-type channel stopper regions therebelow and following conventional steps for shaping a first polysilicon layer to form the floating gate regions of the cells using an own mask and forming the control gate and the gate of transistors from a second polysilicon layer. EP-A-0 206 929 describes a method for manufacturing an EPROM cell and a transistor. It is an object of the present invention to provide an improved manufacturing process designed to reduce the number of masking stages involved in forming the channel stoppers, without jeopardizing, indeed, while at the sane time preferably improving, the electric characteristics of the finished device. According to the present invention, there is provided a process for manufacturing MOS integrated circuits, as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Fig.s 1 to 4 show cross sections of a silicon wafer at four different stages of the known LOCOS process, for forming two complementary transistors and a memory cell; Fig.s 5 to 11 show cross sections of a silicon wafer at different stages in the formation of the Fig. 1-4 components according to the present invention. In the following description, reference is made solely to Fig.s 5 to 11, the elements of which, similar to those of Fig.s 1 to 4, are indicated using the same numbering system. Fig.5 shows a cross section of a silicon wafer consisting of a substrate 1 housing an N-well 2 and on which extend a silicon oxide layer 3 and a nitride layer 4. The Fig.5 structure is masked using known photolithographic techniques, for obtaining the active area mask including resist portions 5 extending over the required field oxide regions; and the exposed portions of nitride layer 4 and oxide layer 3 are removed to produce the Fig.6 structure identical to that of Fig.1. Unlike the known LOCOS process described previously, immediately following removal of resist layer 5, thick-oxide field insulating regions 10 are grown, with nitride layers 4 being slightly distorted by intrusion (in known manner) of the oxide along the edge of the active areas, to produce the structure shown in Fig.7. At this point, nitride layer 4 and oxide layer 3 are removed; a gate oxide layer 13 is grown; and a first polysilicon layer 14 is deposited and subsequently doped by implanting phosphorus or POCl 3 in known manner, to produce the Fig.8 structure wherein layer 13, which merges with oxide 10 in the field insulating regions, is shown solely in the active areas. First polysilicon layer 14 is then defined by means of a masking and chemical etching operation, to produce the Fig.9 structure. As can be seen, the resist mask 20 used for defining layer 14 differs from that of the known LOCOS technique in that, in addition to exposing the portions of layer 14 surrounding the memory cell region (to the right) and the UPROM cell region (not shown), it also exposes layer 14 over the field insulating regions 10 formed in the P type substrate, i.e. the regions in which the channel stoppers are to be formed. Subsequently, after removing the exposed portions of polysilicon layer 14, boron ions are implanted as shown by arrows 21 in Fig.10. This is performed in high-energy manner, to penetrate the full thickness of field oxide layer 10 (typically 500-700 nm (5000-7000 Å)), and results in the formation of small boron ion layers 8' underlying field insulating regions 10 and forming P + type channel stoppers after diffusion. Following implantation of layers 8', photoresist mask 20 used for defining first polysilicon layer 14 and implanting channel stoppers 8' is removed; an oxide layer 15 is grown for insulating the polysilicon layers; oxide layer 15 is removed selectively, by masking, from the circuit component portions; and a second polysilicon layer 16 is deposited, to produce the structure shown in Fig.11. The next stages in the process consist in forming the various components in and on the substrate, according to the circuit and technique in question, and more specifically, in doping second polysilicon layer 16; defining the transistor gates; implanting the transistor source and drain regions; and, finally, protecting and interconnecting the devices. In other words, in the described process first polysilicon layer 14 and the photoresist mask 20 employed for defining the same protect the active areas and N-well regions at the channel stopper implantation stage, thus eliminating the need for an additional mask and so reducing the total number of masking stages for producing the circuit. The advantages of the described process will be clear from the foregoing description. In particular, besides eliminating one masking stage, as described above, and so reducing production time and cost, the process according to the present invention also provides for improved electric performance by enabling implantation of the channel stoppers at a slightly greater distance from the active areas as compared with the known LOCOS technique wherein the stoppers are selfaligned. Moreover, the doping ions implanted subsequent to field oxidation are not involved in the field oxidation itself and in the oxidation necessary to form the gate oxide layer 13, and, by virtue of not being subjected to the relative heat processes, diffuse to a lesser degree, thus further reducing doping ion concentration close to the active areas and, consequently, increasing breakdown voltage and reducing parasitic capacitance, with no reduction in the turn-on threshold of the parasitic transistors.

Claims: A process for producing MOS-type integrated circuits including N and P channel MOS devices formed in substrate portions (1, 2) of opposite conductivity and memory cell devices having two layers of semiconductive material separated by field insulating regions, the process comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) of semiconductive material; depositing a first layer (14) of semiconductive polycrystalline material on said substrate (1); and said field insulting regions (10); shaping said first layer (14) of semiconductive polycrystalline material using a floating gate shaping mask (20), said shaping mask (20) having openings over field insulating regions (10) housed in first portions (1) of said substrate having a first conductivity type; said mask (20) covering second portions (2) of said substrate having a second conductivity type; thereafter, selectively implanting (21) ions of a selected type of conductivity in said substrate (1) through said predetermined field insulating regions (10) using said floating gate shaping mask, for forming channel stopper regions (8') beneath said predetermined field insulating regions (10); subsequently, removing said shaping mask (20) and depositing an electrically insulating layer (15); selectively removing said electrically insulating layer from the transistor device portions; depositing a second layer (16) of semiconductive polycrystalline material, said second layer (16) being in direct electrical contact with said first layer (14) at said transistor device portions; and shaping transistor gate regions and cell control gate regions of said devices. A process as claimed in Claim 1, characterized in that said selective implantation step (21) is a high-energy implantation step. A process as claimed in one of Claims 1 or 2, characterized in that said substrate (1) has said selected conductivity type. A process as claimed in one or more of the foregoing Claims, characterized in that said selected type of conductivity is a P type, and said ions comprise boron.

Inventors: CEREDA MANLIO SERGIO, GINAMI GIANCARLO, LAURIN ENRICO, RAVAGLIA ANDREA, CEREDA, MANLIO SERGIO, GINAMI, GIANCARLO, LAURIN, ENRICO, RAVAGLIA, ANDREA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21