Current offset type sense amplifier

Abstract: A modulated-current offset-type or currentunbalance, offset-type sense amplifier for reading programmable memory cells employs loads identical to each other and a differential input pair of transistors of the differential amplifier are "cross-coupled" with said identical loads to realize a latch structure for storing an extracted data. The circuit utilizes three timing signals for sequentially modifying the configuration of the circuit and defining the following phases: start of a new reading cycle, pre-charging of capacitances associated with bit lines, and equalization of output nodes and line potentials, discrimination phase, reading and storing of the extracted data. Different embodiments employing different reference systems are described.

Description: Technical Field The present invention relates to a circuit for reading the information stored in a cell of a programmable static memory, e.g., a ROM or EPROM type memory, according to a differential sensing system employing a sense amplifier and an output latch circuit for storing an extracted (read) data. Background of the Invention Along with a constantly increasing packing density of integrated semiconductor devices, the reduction of the size of the single cells of static memory arrays, the attendant decrease of the operating current levels and the consequent magnified influence of parasitic electric factors of the integrated structures impose the use of a reading circuitry having an enhanced precision and reliability while ensuring a high speed. The use of differential sense amplifiers attempts to treat the effects due to "process spread", temperature and supply voltage variations as common mode contributions. Moreover modulated-current offset type as well as current unbalance type sense amplifier attempts to free the sensing behavior from the maximum value that the supply voltage may reach, besides simplifying the dimensioning of transistors which form the sense amplifier in respect to the alternative load unbalance system. Usually the required control of the output common mode of the high gain differential sense amplifier is conveniently implemented by using an output latch wherein the extracted (read) data may be stored. The article: "A High-Speed Parallel Sensing Architecture for Multi-Megabit Flash E 2 PROM's" by Kazuo Kobayashi, et al., IEEE Journal of Solid-State Circuits, February 25, 1990, No. 1, New York, discloses a self-timed dynamic sensing circuit for high-speed and stable sensing wherein the differential amplifier acts as a column latch. The article: "A 1-Mbit CMOS EPROM with Enhanced Verification" by Roberto Gastaldi, et al., IEEE Journal of Solid-State Circuits, October 23, 1998, No. 5, New York, pages 1150-1156, discloses a high-speed EPROM memory wherein the sense circuitry uses an offset current to shift the sense point in order to require a higher threshold shift during verification. A sense amplifier with these characteristics is relatively complex and remains sensitive to noise. Summary of the Invention A main objective of the present invention is to provide an improved sense amplifier of the so-called modulated-current offset type or of the current offset type, having a simplified circuit layout and employing a reduced number of components while having an enhanced immunity to noise, a high speed and a high reliability. It is a further objective of the invention to provide a sense amplifier for a programmable memory having cross-coupled loads which also constitute a latch circuit for storing the extracted data, thus performing both amplification and output data storage functions. Basically, in the sense amplifier's circuit of this invention, the same identical load elements of the two branches or lines of the input network of the differential sense amplifier also constitute the loads of a differential input transistor pair of the amplifier and are cross-coupled whereby they form together with the same differential input transistor pair a latch circuit for storing the output data. The different features and advantages of the circuit object of the present invention will become clear from the following description of several preferred embodiments and reference to the attached drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of a sense amplifier of the modulated-current offset type, according to a first embodiment of the invention. Figure 2 is a timing diagram of the circuit of Figure 1 during a reading cycle. Figure 3 is a diagram of the operation characteristics of the sense amplifier of Figure 1. Figure 4 is a circuit diagram of a sense amplifier the current unbalance type, according to an alternative embodiment of the present invention. Figure 5 is a diagram of the circuit of Figure 4 during a reading cycle. Figure 6 is a diagram of the operation characteristics of the sense amplifier of Figure 4. Figure 7 is a circuit diagram of another embodiment of a current offset type sense amplifier according to the invention. Figure 8 is a timing diagram of the circuit of Figure 7 during a reading cycle. Figure 9 is a diagram of the operation characteristics of the current offset type sense amplifier of Figure 7. Detailed Description of the Invention A first embodiment of the circuit of the invention, of a modulated-current offset type, is shown in Figure 1. In the bottom half of the circuit diagram is shown in a schematic manner the organization of a memory matrix, organized in rows (word lines) and columns (bit lines) of cells. From the "matrix side", the different columns (MATRIX BIT LINE) may be individually selected through a multiplexer driven by the bus COL.SELECT. A reference bit line, BLr (REFERENCE BIT LINE), contains virgin memory cells which act as reference elements for determining the state of the programmable cells of the bit lines of the memory matrix. The top portion of the diagram shows a reading circuit made in accordance with the invention, which employs a single stage differential amplifier formed by a pair of input transistors T DM and T DR and by a current generator TS, which may be enabled or disabled. The respective load elements, which in the example shown are two p-channel transistors, T LM and T LR , are cross-coupled in order to form, together with the same input transistors of the differential amplifier: T DM and T DR , also a latch circuit for storing the output data which is represented by the signal present on the output nodes OUTM and OUTR of the reading circuit. Significantly, the same loads T LM and T LR of the output latch also constitute the loads of the reference branch and of the branch containing the selected matrix cell to be read, of an input network of the differential sense amplifier, respectively. In the example shown, these branches are represented by the reference line BLr and by the selected matrix side bit line BLm. The two lines of the input network of the differential sense amplifier are precharged, in preparation of an actual reading step, through the switches T PM and T PR , respectively, which momentarily connect the respective line to the supply for a preestablished time interval in order to charge the capacitances associated with the two input lines of the differential sense amplifier. Two NOR gates, CM and CR, respectively, which may be formed by a cascode circuit, may be utilized for setting the point of operation of the sense amplifier by controlling a fast precharge of the two lines of the input network through the respective switches T PM and T PR and simultaneously the capacitive decoupling of the input lines from the output nodes of the sense amplifier: OUTM and OUTR, by means of the pass transistors T CM and T CR . To an input node of each of said NOR gates, a first timing signal Φ EN is applied, which is also applied to a control terminal of the current generator TS which enables the sense amplifier. A first switch T EC permits to equalize the output node of the two cascode circuits CM and CR during the precharge step of the input lines and a second switch T ES permits to equalize the input lines during the precharge step. A second timing signal Φ PC is applied to the control terminals of both equalization switches T EC and T ES . Eventually this second timing signal Φ PC determines the start of a reading phase at the end of the precharging phase of the lines, by interrupting the respective equalization paths, that is by opening the switches T EC and T ES . The switch T EL , connected between the two output nodes of the reading circuit, maintains in a state of substantial equalization the load elements T LM and T LR of the reading circuit until the conclusive valutation phase of a reading cycle is reached, that is when the switch T EL is opened by the respective timing signal Φ EQ , in order to permit a full evolution of a difference of potential between the output nodes OUTM and OUTR. The operation of the circuit of Figure 1 is as follows. The form of the various signals of the circuit during a complete reading cycle, as described above, is shown in the diagram of Figure 2. The rest condition of the reading circuit, which is characterized by nil power consumption, is determined by the three timing signals: Φ EN , Φ PC and Φ EQ , all at a high logic level ("1") and represents the natural condition from which any new reading cycle begins and to which the system returns after having extracted the data. In this rest condition, the output nodes of the two NOR gates, CM and CR, are forced to ground potential by Φ EN being high. The output nodes OUTM and OUTR are at logically opposed levels: "1" and "0" or vice-versa, in conformity with the last extracted data stored by the circuit. No power consumption is possible because of the action of Φ EN , on the cascodes CM and CR and moreover the other timing signal Φ EQ , maintained at a logic high level, interrupts any possible path between the supply node and ground (VCC-GND). A new reading cycle begins with the switching from "1" to "0" of the control signals Φ EN and Φ EQ , which free the cascodes CM and CR, thus permitting them to drive a fast pre-charge of the capacitances of the reference line BLr and of the selected matrix's bit line BLm until the design working point of the sense amplifier is attained. At the same time, various nodes in the system equalize at various levels: for example at the level shown in Figure 2 for OUTM and OUTR nodes; at the level shown for the output nodes of the two cascodes circuits, CM and CR; and at the level shown for the bit lines BLr and BLm. The circuit elements are sized and designed such that at the end of the fast pre-charge period, the OUTM and OUTR nodes, duly equalized, take a potential which is apt to provide, through the loads TLM and TLR, the sum of the currents drawn by the selected cells of the matrix line and of the reference line. As soon as propagation of any control signal within the circuit may be assumed as completed, this first step of the reading cycle is terminated by the switching from "1" to "0" of the control signal Φ PC so as to initiate a preevaluation or discrimination phase of the state of the selected cells which will produce only relatively small potential variations at the OUTM and OUTR nodes and at the output nodes of the NOR gates (cascodes) CM and CR, but in an extremely small period of time, by virtue of the design freedom offered by the circuit of the invention to size the components of the input network so as to effectively minimize any undue shift of potential of the bit lines BLm and Blr during this critical discrimination phase. The evaluation step is completed by the switching from "0" to "1" of the control signal Φ EQ which occurs soon after said switching of the control signal Φ PC . When this event takes place, the small difference of potential present at the OUTM and OUTR nodes rapidly evolves firstly toward the asymptotes VCC-(VBL-VBR) and subsequently toward the asymptotes VCC-GND upon the switching back from "0" to "1" of the control signal Φ EN , which takes place immediately after the switching of the control signal Φ EQ . This sequence of events, beside digitalizing and storing the extracted data, resets automatically the system to the rest condition characterized by a nil power consumption. Of course, the events described above take place in a short period of time, the entire cycle occurring in less than a second, thus achieving an extremely short reading time. The current drawn by the system, after the pre-charge phase is terminated, is totally provided through the loads T LM and T LR in order to concentrate through the load elements the entire current signal of the system. The peculiar cross-coupled connection of the loads T LM and T LR confers to the sense amplifier a positive feedback which enhances the amplifying capacities without the need of further amplifying stages. The load elements T LM and T LR and the differential input transistor pair: T DM and T DR , in the last phase of the reading cycle are so configured as to form a latch circuit, capable of storing the extracted data beside effectively suppressing any common mode disturbance, thus making the sense amplifier exceptionally immune to noise and to other possible causes of instability. The reference system of the sense amplifier of Figure 1 for discriminating the state of a selected matrix's cell (virgin or programmed) utilizes a MOS transistor T OF , which is functionally associated to the selected matrix's line. The transistor T OF is a current modulating transistor functionally connected to the bit line to be read. The transistor T OF is sized and designed to be capable of generating under any condition of supply voltage a current equal to half the current drawn by a virgin cell, and can be designed in accordance with an offsetting technique commonly referred to as "modulated-current" offsetting, which is well known to a skilled technician. Within the circuit: Ivm is the current drawn by a matrix's virgin cell; Ivr is the current drawn by a reference virgin cell; Ipm is the current drawn by a matrix's programmed cell; Iv is the current drawn by a generic virgin cell; and Iof is the offset current; and the circuits are designed such that: Ivm = Ivr = Iv Iof = Iv/2 (offset current) Ipm = 0 The following system of current inequalities affords discrimination: Ivm + Iof > Ivr for a selected virgin cell; Ipm + Iof < Ivr for a selected programmed cell; Iv + Iv/2 > Iv for a selected virgin cell; and 0 + Iv/2 < Iv for a selected programmed cell. The curves which characterize the above inequalities are shown in the diagram of Figure 3. Among the main advantages of the sense amplifier of the invention the following may be cited: i) use of a reduced number of components and of amplifying stages by performing also the function of storing the extracted data within the structure of the differential sense amplifier; ii) the only power dissipating structures are the cascode circuits which form the two NOR gates which are disabled during the evaluation step; iii) the load elements are an integral part both of the sense amplifier as well as of the output latch associated therewith; this enhances immunity to noise during and after a reading cycle; iv) an immediate decoupling of the large capacitances of bit lines and of the multiplexer (i.e., the structure which performs the selection of the path to a selected matrix's cell to be read) during the critical discrimination step is ensured by the circuit, thus enhancing speed and reliability; v) good sensitivity and speed by virtue of the cross-coupled connection of the loads; vi) the circuit has lesser design restraints than known circuits and remains operative also in presence of large variations of current levels by preventing undesired saturation conditions; vii) the circuit is intrinsically suitable to operate in memory devices which require rather high bias levels of the lines. An alternative embodiment of the circuit of the invention is depicted in Figure 4. In this alternative embodiment there is not a current modulating transistor functionally connected to the bit line to be read as in the previously described example, by contrast the current unbalance condition is implemented in a different manner as will be described later. Structurally the reading circuit is substantially similar to the circuit shown in Figure 1, as confirmed by utilizing the same symbols for identifying the various functionally similar components of the two circuits. Differently from the circuit of Figure 1, a second connection path to the supply rail is arranged both for the reference bit line BLr and the selected matrix's bit line Blm during the fast precharging step of a reading cycle. This additional path is controlled by the switch T CR ' in the case of the reference bit line BLr and by a second switch T PC functionally in series with the switch T CM ' and driven by the timing signal Φ PC , for the case of the selected matrix's bit line BLm. Moreover a p-channel transistor, T LM ' and T LR ', respectively, is connected as a load element in each of said two additional connection paths to the supply rail of the reference line and of the selected line, respectively. Differently from known current offset circuits which normally utilize a load transistor (T CR ) of double the size of the other (dual) load transistor (T LM ) and which therefore exclude symmetry of the two branches of the input network of the sense amplifier, the addition of these two additional connection paths to the supply permits maintaining a virtually perfect symmetry of the size of transistors which makes possible the operation of the circuit also as an output latch. The operation of the reading circuit of Figure 4 is as follows: The form of the various signals of the circuit of Figure 4 during a complete reading cycle, as now described, is shown in the diagram of Figure 5. The rest condition of the reading circuit, which is characterized by nil power consumption, is determined by the three timing signals: Φ EN , Φ PC and Φ EQ , all at a high logic level ("1") and represents the natural condition from which any new reading cycle begins and to which the system returns after having extracted the data. In this rest condition, the output nodes of the two NOR gates, CM and CR, are forced to ground potential by Φ EN . The output nodes OUTM and OUTR are at logically opposed levels: "1" and "0" or vice-versa, in conformity with the last extracted data stored by the circuit. No power consumption is possible because of the action of Φ EN , on the cascodes CM and CR and moreover the other timing signal Φ EQ , maintained at a logic high level, interrupts any possible path between the supply node and ground (VCC-GND). A new reading cycle begins with the switching from "1" to "0" of the control signals Φ EN and Φ EQ which free the cascodes CM and CR, thus permitting them to drive a fast precharge of the capacitances of the reference line BLr and of the selected matrix's bit line BLm until the design working point of the sense amplifier is attained. At the same time various nodes in the system equalize at various levels, for example at the load's level shown in Figure 5 for OUTM and OUTR nodes; at the level shown for the output nodes of the two cascodes circuits, CM and CR; and at the level shown for the bit lines BLr and BLm. At the end of the fast pre-charge period, the OUTM and OUTR nodes, duly equalized, take a potential which is apt to provide, through the loads T LM , T LR and T LM ', T LR ', the sum of the currents drawn by the selected cells of the matrix line and of the reference line. As soon as propagation of any control signal within the circuit may be assumed as completed, this first step of the reading cycle is terminated by the switching from "1" to "0" of the control signal Φ PC which interrupts the additional connection path of the selected matrix's bit line to the supply and the equalization paths between the output nodes of the two cascodes CM and CR and the two lines Blm and Blr so as to initiate a preevaluation phase of the state of the selected cells which will produce only relatively small potential variations at the OUTM and OUTR nodes and at the output nodes of the NOR gates (cascodes) CM and CR, but in an extremely small period of time, by virtue of the design freedom offered by the circuit of the invention to size the components of the input network so as to effectively minimize any undue shift of potential of the bit lines: BLm and Blr during this discrimination phase. The evaluation step is completed by the switching from "0" to "1" of the control signal Φ EQ which occurs soon after said switching of the control signal Φ PC . When this event takes place, the small difference of potential present at the OUTM and OUTR nodes rapidly evolves firstly toward the asymptotes VCC-(VBL-VBR) and subsequently toward the asymptotes VCC-GND upon the switching back from "0" to "1" of the control signal Φ EN , which takes place immediately after the switching of the control signal Φ EQ . This sequence of events, besides digitalizing and storing the extracted data, resets automatically the system to the rest condition characterized by a nil power consumption. Of course, the events described above take place in a short period of time thus achieving an extremely short reading time. The current drawn by the system, after the initial pre-charge phase and the discrimination phase is terminated, is provided through the loads T LM and T LR in order to concentrate through the load elements of the sense amplifier the entire current signal of the system. The peculiar cross-coupled connection of the loads T LM and T LR confers to the sense amplifier a positive feedback which enhances the amplifying capacities without the need of further amplifying stages. The load elements T LM and T LR and the differential input transistor pair: T DM and T DR , in the last phase of the reading cycle are so configured as to form a latch circuit, capable of storing the extracted data beside effectively suppressing any common mode disturbance, thus making the sense amplifier exceptionally immune to noise and to other possible causes of instability. The reference system of the sense circuit of Figure 4 is different from that of the circuit of Figure 1. In order to permit to the sense amplifier to discriminate the state of a selected matrix's cell (virgin or programmed), a current unbalance at the loads level, which on the other hand must remain virtually identical in order to permit a correct operation of the circuit also as an output latch, is implemented by opening the switch T PC thus interrupting, at the end of the fast precharging phase, the additional current contribution of the secondary or additional precharge path through the matrix's bit line selected for reading, which is controlled by the switch T CM ' and which is provided with a load T LM '. Within the circuit of Figure 4: Ivm is the current drawn by a matrix's virgin cell Ivr is the current drawn by a reference virgin cell Ipm is the current drawn by a programmed matrix's cell Iv is the current drawn by a generic virgin cell Ilm is the current drawn by the load on the matrix side T LM Ilr is the current drawn by the load on the reference side T LR Ilr' is the current drawn by the unbalancing load T LR ' on the reference side Icm is the current through the pass-transistor T CM Icr is the current through the pass-transistor T CR Icr' is the current through the pass-transistor T CR ' and: Ivm = Ivr = Iv Ipm = 0 Ivm = Icmv Ivp = Icmp Ivr = Icr + Icr' Icr = Icr' Icr = Ivr/2 The following system of inequalities affords discrimination: Icmv > Icr for a selected virgin cell; Icmp < Icr for a selected programmed cell; Ivm > Ivr/2 for a selected virgin cell; Ipm < Ivr/2 for a selected programmed cell; Iv > Iv/2 for a selected virgin cell; and 0 < Iv/2 for a selected programmed cell. The curves which characterize the above inequalities are shown in the diagram of Figure 6. Also in the case of the alternative embodiment of Figure 4, the sense circuit of the invention offers the same advantages of the circuit of Figure 1. A current offset type embodiment of the sense circuit of the invention, may also be realized in a simpler form than that of Figure 7. In this further embodiment, the current offsetting elements in the two branches of the input network of the sense amplifier are constituted by the transistors T PC and T PM on the matrix side and by the transistor T PR on the reference side. The operation of the reading circuit of Fig. 7 is substantially similar to that of the circuit of Fig. 4 , as will be evident to any skilled technician. Therefore a further reiteration of a detailed description of the operation of the circuit would appear largely superfluous. Also in this alternative embodiment the ability of discriminating the state of a selected cell (virgin or programmed), is achieved by means of a current offset through the load elements T LM and T LR , which, on the other hand, must continued to be rigorously identical both dimensionally as well as geometrically, in order to permit a correct functioning of the latch structure. Such a current offsetting is realized by placing in an OFF condition the T PC MOS transistor thus interrupting in this way, at the end of the precharge phase, the additional current contribution provided by the additional connection path to the supply through the T PC and T PM transistors of the line of the input network relative to the matrix's cell selected for ready. The reference system of the sense amplifier circuit of Fig. 7 is the following. Given: Ivm current drawn by a matrix's virgin cell Ivr current drawn by a reference virgin cell Ipm current drawn by a programmed matrix's cell Iv current drawn by a generic virgin cell Ilm current drawn by the load on the matrix side T LM Ilr current drawn by the load on the reference side T LR Icm current through the pass-transistor T CM Icr current through the pass-transistor T CR Ipr current through the pass-transistor T PR and: Ivm = Ivr = Iv Ipm = 0 Icm = Ivm = Iv current through the pass-transistor TCM with a virgin cell selected Icm = Ipm = 0 current through the pass-transistor TCM with a programmed cell selected Ipr = Icr which implies TCR = TPR from where: Ivr = Icr + Ipr Ivr = 2Icr = Icmv Ivr = 2Ipr = Icmv The following system of disequations affords discrimination: Icmv > Icr selected virgin cell Icmp < Icr selected programmed cell Ivm > Ivr/2 selected virgin cell Ipm < Ivr/2 selected programmed cell Iv > Iv/2 selected virgin cell 0 < Iv/2 selected programmed cell The form of the relevant signals, during a complete reading cycle, is shown in the diagram of Fig. 8 and the characteristics of the discriminating system are shown in the diagram of Fig. 9. Also the sense amplifier's circuit of Fig. 7 offers substantially the same advantages of the circuits of the preceding embodiments.

Claims: A current offset type differential sense amplifier comprising a pair of input transistors (T DM , T DR ) of a first conduction type each having first and second current terminals and a control terminal, said control terminals being cross-coupled to the respective first current terminal of the other input transistor, the respective control terminals constituting a first input node and a second input node connectable to a first line (REFERENCE BITLINE) containing at least a reference cell (T VR1 , T VR2 ) and a second line containing a selected memory cell (T VM , T PM ), respectively, each input node being operatively connected to a supply rail through an essentially identical load transistor (T LM , T LR ) of a second conduction type said load transistors being essentially identical, and a biasing current generator (T S ) functionally connected between said second current terminal of each of said input transistors (T DM , T DR ) and a ground node and having a control terminal to which a second timing signal (Ø EN ) is applied, said load transistors (T LM , T LR ) having their control terminals cross-coupled to said input nodes of the amplifier and connected to a respective output node (OUTM, OUTR); a reset switch (T EL ) being connected across said output nodes and having a control terminal to which a first timing signal (Ø EQ ) is applied; said load transistors (T LM , T LR ) constituting the loads of said pair of input transistors (T DM , T DR ) of said differential sense amplifier during a discrimination phase of a reading cycle and forming together with said input transistor (T DM , T DR ) a latch for storing an extracted data during a last phase of a reading cycle. A sense amplifier according to claim 1, further comprising electrical paths functionally connecting each of said lines to said supply rail and to the respective input node, said paths being controlled by at least a pair of switches, a connecting switch (T PM , T PR ) between the supply rail and the respective line and a decoupling switch (T CM , T CR ) between the respective input node and the line; each pair of switches (T PM -T CM , T CR - PR ) being driven by a control gate circuit (CM, CR) having an output node connected to control terminals of said switches, a first input node connected to the respective line, and a second input terminal to which said second timing signal (Ø EN ), is fed; a first equalizing switch (T ES ), functionally connected between said two lines and a second equalizing switch (T EC ), functionally connected between the output nodes of said control gate circuits (CM, CR), driven by a third timing signal (Ø PC ); an evaluation phase of a reading cycle being initiated upon the opening of said two equalizing switches (T ES , T EC ). A sense amplifier according to claim 2, wherein said control gate circuit (CM, CR) is a NOR gate. A sense amplifier according to claim 3, wherein said NOR gate is a cascode circuit. A sense amplifier according to claim 2, wherein a current generator (T OF ) capable of generating a current equal to half the current which is drawn by a virgin memory cell forces an offsetting current through the line (MATRIX BIT LINE) containing the selected memory cell to be read. A sense amplifier according to claim 2, further comprising secondary electrical path functionally connecting each of said lines to the supply rail, each of said secondary paths being provided with an identical load (T LM ', T LR ') and being controlled by means of a switch (T CM ', T CR '), driven by the respective control gate circuit (CM, CR), connected between the load (T LM ', T LR ') and the respective line (MATRIX BIT LINE, REFERENCE BIT LINE) ; the secondary electrical path connecting the line containing the selected memory cell to be read having a second switch (T pc ), driven by said third timing signal (Ø PC ) for determining a current offset condition between the two lines at the end of a precharge phase of a reading cycle. A sense amplifier according to claim 1, wherein said loads (T LM , T LR , T LM ', T LR ') and said reset switch (T EL ) are p-channel transistors. A sense amplifier according to claim 5, wherein said identical loads (T LM ', T LR ') of said secondary electrical paths are also identical to the cross-coupled loads (T LM , T LR ) of said differential sense amplifier and output storage latch. A sense amplifier according to claim 1 comprising: a memory bit line sense node and a reference bit line sense node; said input transistors (T DM , T DR ) cross coupled and having the gate of a first transistor (T DR ) and the drain of the other transistor (T DM ) coupled to the memory bit line sense node and the gate of said other transistor (T DM ) and the drain of the first transistor (T DR ) coupled to the reference bit line sense node; said two identical load transistors (T LM , T LR ), coupled between a selected supply voltage potential and the memory bit line sense node and the reference bit line sense node, respectively, their gates being cross-coupled to the respective reference bit line sense node and the memory bit line sense node, respectively; and a clocked transistor (T EL ) forming said reset switch and shortcircuiting the gates of the two identical load transistor (T LM , T LR ) when the clocked transistor (T EL ) is clocked to be conductive and isolating the gates of the identical load transistors from each other when is clocked to be nonconductive. The sense amplifier of claim 9, further including: a pair of pass transistors (T CM , T CR ), each coupled between the memory bit line and the memory bit line sense node and the reference bit line and reference bit line sense node; and a pair of NOR gates (CM, CR) each having one of their inputs clocked and the other input connected to the memory bit line and the reference bit line, respectively, and each having their outputs connected to the gate of the respective one of the pair of said pass transistors (T CM , T CR ), respectively. The sense amplifier according to claim 10, further including: a pair of precharge switching transistors (T PM , T PR ) connected from a selected single voltage potential to the memory bit line and reference bit line, respectively, and each having their gate coupled to the output of the respective NOR gates (CM, CR) so that their state of being conductive or nonconductive is controlled by the output of said respective NOR gates. The sense amplifier according to claim 11, further including: a second pair of precharge switching transistors (T CM ', T CR ') coupled to the memory bit line and reference bit, respectively, and having their gates coupled to the outputs of the respective NOR gates (CM, CR).

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: G11C7
IPC codes: G11C16, G11C7, G11C11, G11C17