CCD image sensor

Abstract: A CCD imager includes at least one four-phase vertical shift register having first, second, third and fourth transfer electrodes (G₁ to G₄). In order to prevent nonuniform distribution of smear charge and other unwanted charge, and for improving the quality of a picture, means are provided for making the potential well under each first electrode (G₁) deeper than the potential wells under the second, third and fourth electrodes (G₂ to G₄). Preferably, a N-type semiconductor region (6) is formed under each first electrode (G₁) by ion implantation.

Description: BACKGROUND OF THE INVENTION The present invention relates to a solid-state imager in accordance with the precharacterizing part of claim 1. Such a solid state imager is known from US-A-4656518. The present invention further relates to a method of producing a CCD imager. In general, a four-phase CCD solid-state imager has at least one photosensitive imaging section, and one ore more shift registers having four clock input terminals connected with a driver circuit 21 (shown in Fig. 8) by four clock lines. Field readout operations of such a CCD solid-state imager is performed as shown in Figs. 5A-6B. During a readout period, readout pulses (of 15V) are applied, respectively, to first transfer electrodes G1 for receiving a first drive pulse signal V1, and third transfer electrodes G3 for receiving a third drive pulse signal V3. In the odd field, as shown in Figs. 5A and 5B, signal charge packets are transferred from photosensitive elements Sn, Sn+1, Sn+2, Sn+3, ... to corresponding potential wells which are formed independently under the first and third transfer electrodes G1 and G3. Thereafter, the potential barrier under each second transfer electrode G2 is lowered to create a wide potential well extending continuously under the first, second and third electrodes G1, G2 and G3 of each stage. Thus, one continuous potential well is formed for each of pairs (Sn, Sn+1,), (Sn+2, Sn+3), ... . Therefore, the signal charge of the nth photosensitive element Sn of the nth row is mixed with the signal charge of the (n+1)st photosensitive element Sn+1 of the (n+1)st row in the corresponding continuous wide potential well. The next continuous potential well serves for mixing the signal charge packets of the next pair (Sn+2, Sn+3). In this way, the signal charge of each photosensitive element is mixed with the signal charge of the mate of the pair. In these figures, signal charge is shown by parallel oblique lines. In the even field, the photosensitive elements are paired to form pairs (Sn+1, Sn+2), (Sn+3, Sn+4), ... . First, signal charge packets of the photosensitive elements are transferred to respective independent potential wells formed under the the first and third transfer electrodes G 1 and G 3 . Then, lowering the potential barrier of each fourth transfer electrode G 4 creates a continuous wide potential well extending continuously under the third, fourth and first electrodes G 3 , G 4 and G 1 . Therefore, the continuous wide potential wells function to mix the signal charge packets of the (n+1)st row and (n+2)nd row, the signal charge packets of the (n+3)rd row and (n+4)th row, and so on. Unwanted charge, such as smear charge and dark signal charge, generated in the vertical shift registers are also transferred in the same manner as explained above for the signal charge. Figs. 7 and 8 show the clock pulse waveforms for the vertical registers and profiles of potential in the odd field. Figs. 9 and 10 shows the clock pulse waveforms and potential profiles in the even field. In these figures, unwanted charge including smear charge and dark signal charge is shown by parallel oblique lines. In the odd field, the unwanted charge packet stored under the first and second transfer electrodes G 1 and G 2 of a given electrode set (the first electrode set, for example) at an instant t 0 is shifted to the right as viewed in Fig. 8, and this unwanted charge packet exists in the location under the first and second electrodes G 1 and G 2 of the next electrode set (the second set, for example) at an instant t 8 , as shown in Fig. 8. At this instant t 8 (t=t 8 ), the first and second drive pulse signals V1 and V2 are held at the high level (0 V), and the third and fourth drive pulse signals V3 and V4 are at the low level (-9 V). At the next instant t 9 , the third drive pulse signal V3 has switched to the high level, and therefore, the unwanted charge is accumulated under the first, second and third electrodes G 1 , G 2 and G 3 . At the next instant t 10 , the second drive pulse signal V 2 is at the low level, and therefore, the unwanted charge is divided into a first portion under the first electrode G 1 and a second portion under the third electrode G 3 . At an instant t 11 , the second drive pulse signal V 2 has switched again to the high level, and the unwanted charge is transfer and accumulated again under the first, second and third transfer electrodes G 1 , G 2 and G 3 . During the readout period T after the instant t 10 , a readout pulse p (15 V) is applied to each of the first and third transfer electrodes G 1 and G 3 . Therefore, signal charge packets of the sensing elements are transferred to the associated vertical shift register, and accumulated in the respective storage sites under the first, second and third electrodes G 1 , G 2 and G 3 at t 11 . The storage levels of the signal charge are shown by one dot chain lines in Fig. 8. In the even field, as shown in Figs. 9 and 10, unwanted charge such as smear charge is shifted during an interval between t 0 and t 8 , from the location under the first and second transfer electrodes G 1 and G 2 of the first electrode set, for example, to the location under the first and second transfer electrodes G 1 and G 2 of the second electrode set, as in the odd field. Then, the third drive pulse signal V 3 is switched to the high level, so that, at an instant t 9 , the first, second and third drive pulses signals V 1 , V 2 and V 3 are high and the fourth drive pulse signal V 4 is low as shown in Fig. 9. Therefore, the unwanted charge is accumulated at t 9 under the first, second and third transfer electrodes G 1 , G 2 and G 3 of each set. At an instant t 10 , because of the most recent fall of the second drive pulse signal V 2 to the lower level between t 9 and t 10 in Fig. 9, the unwanted charge is divided into a first portion under the first transfer electrode G 1 and a second portion under the third transfer electrode G 3 , by a potential barrier formed under each second transfer electrode G 2 . At an instant t 11 , the fourth drive pulse signal V 4 has risen to the high level, and the unwanted charge is accumulated under the third, fourth and first transfer electrodes G 3 , G 4 and G 1 . During the readout period T between t 10 and t 11 , the readout pulses p are applied to the first and third transfer electrode G 1 and G 3 as shown in Fig. 9, so that signal charge packets are taken out from the sensing elements and accumulated at the instant t 11 under the third, fourth and first electrodes G 3 , G 4 and G 1 , as shown by one dot chain lines in Fig. 10. In the conventional CCD imager, however, nonuniform distribution of unwanted non-signal charge in the even field causes noise in reproduced picture imagery. As shown in Fig. 10, the unwanted charge residing in each temporary storage site at t 9 is divided into two portions at t 10 due to a potential barrier formed under each second transfer electrode G 2 with the second drive pulse signal V 2 at the lower level. In this case, the allotment is not uniform but differs in different locations. The ratio between two portions into which an unwanted charge packet is divided is affected by irregularity in pattern and fabricating process. In the example shown in Fig. 10, each unwanted charge packet existing at t 9 is split at t 10 in two unequal parts, and the ratio of one part to the other is 4:6 in one packet, and 8:2 in the next packet. At the instant t 11 , a potential well is formed under each fourth transfer electrode G 4 by the fourth pulse signal switched to the high level while the potential barrier under each second transfer electrode G 2 still remains. Therefore, the unwanted charge remains nonuniformly distributed among a plurality of wide potential wells of a threefold width (as schematically shown in Fig. 10) formed, respectively, under a plurality of three consecutive electrode sets of the third, forth and first transfer electrodes G 3 , G 4 and G 1 . The signal charge from the sensing elements is accumulated in the threefold wide potential wells among which the unwanted charges are nonuniformly distributed. As a result, the level of accumulated charge differs from bit to bit in the vertical register. In the example shown in Fig. 10, the amount of accumulation is great in one potential well W 2 while the neighboring potential wells W 1 and W 3 on both sides are filled only to lower levels. Because of this irregularity, the quality of pictures is significantly degraded by unseemly noises (black-and-white point defects) N appearing, in a picture 11 as shown in Fig. 11, in positional relation in the vertical direction with an image of a bright object A. In the odd field, on the other hand, the uneven distribution of the non-signal charge appearing at the instant t10 in Fig. 8 is only temporary one which disappears shortly and causes no defects in the reproduced picture. At the next instant t11 in Fig. 8, the same potential well is formed as at the instant t9 under each neighboring group of the first, second and third transfer electrodes G1, G2 and G3. Therefore, the distribution of the unwanted charges is restored to the uniform state existing at the instant t9. The solid-state imager known from US-A-4 656 518 comprises a four-phase vertical shift register receiving first to fourth four-phase driving signals for first to fourth transfer electrodes. From Fig. 1 and the corresponding text in columns 5 and 6 it appears that the vertical shift register is connected with the imaging sections so that signal charge packets are transferred from the imaging section to the vertical shift register by applying a readout voltage to transfer electrodes 1-A and 3-A. Column 6 of US-A-4 656 518 describes that the potential energy profile shown in Fig. 1, in particular the potential energy profile shown in Fig. 1(b) is achieved by applying respectively adapted clock pulse signals to each of the first to fourth transfer electrodes 1-A to 4-A so that the signal charges 1+2, 3+4, 5+6 and 7+8 are respectively accumulated under each of said first transfer electrodes 1-A and that the odd-numbered charge packets 1, 3, 5, 7, 9 descriptive of sinqle line vertical resolution image elements merge with the next higher and even-numbered charge packets during transitional clocking and that the resulting charge packets have only two lines vertical resolution. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a solid-state imager which can prevent non uniform distribution of charge and improve the quality of reproduced pictures. According to a first aspect of the present invention a solid-state imager comprising: a photosensitive imaging section; first, second, third and fourth input terminals for receiving respectively first, second, third and fourth four-phase drive pulse signals; and a four-phase vertical shift register comprising a plurality of electrode sets each of which consists of a first transfer electrode connected with said first input terminal, a second transfer electrode connected with said second input terminal, a third transfer electrode connected with said third input terminal and a fourth transfer electrode connected with said fourth input terminal, each of said first, second, third and fourth transfer electrodes being regularly arranged on an insulating layer which is formed on a top surface of an N-type top layer forming a buried channel extending on an underlying P-type semiconductor substrate layer, said vertical shift register being connected with said imaging section so that signal charge packets are transferred from the imaging section to the vertical shift register by applying a readout voltage to each of said first and third transfer electrodes, is characterized in that said substrate further comprises N + -type regions respectively formed under each of said first transfer electrodes, said N + -type regions having an impurity concentration which is higher under each first transfer electrode than under any of the second, third and fourth transfer electrodes to make the potential well under said first transfer electrode deeper than any of the potential wells under said second, third and fourth transfer electrodes (claim 1). Depending claim 2 is specifying an advantageous development thereof. According to a second aspect, the present invention provides a method of producing a CCD imager comprising the steps of forming an N-type top layer on an underlying P-type semiconductor substrate layer, forming a plurality of electrode sets each of which consists of first, second, third and fourth transfer electrodes, each of said transfer electrodes being formed on an insulating layer on a top surface of said N-type top layer, which thus forms a buried channel extending on said underlying P-type substrate layer, said first, second, third and fourth transfer electrodes being regularly arranged to form a four-phase vertical CCD shift register, each of said first electrodes comprising a lower portion formed on said insulating layer, a first upper portion formed on a neighboring one of said fourth electrodes through an insulating film and a second upper portion formed on a neighboring one of said second electrodes through an insulating film, each of said third electrodes comprising a lower portion formed on said insulating layer, a first upper portion formed on a neighboring one of said second electrodes through an insulating film and a second upper portion formed on a neighboring one of said fourth electrodes through an insulating film; and forming an N + -type region under each of said first transfer electrodes, said N + -type regions having an impurity concentration which is higher under each first transfer electrode than under any of the second, third and fourth transfer electrodes for making a potential well under each of said first transfer electrodes deeper than any of the potential wells under said second, third and fourth transfer electrodes (claim 3). Depending claims 4 to 6 are respectively specifying an advantageous development thereof. This solid-state imager according to the present invention can accumulate unwanted charge such as smear charge in the deeper potential well under the first transfer electrode, and prevent the unwanted charge from moving from under the first transfer electrode to next storage sites under the second and third transfer electrodes. In this way, this solid-state imager can prevent the unwanted charge from being divided into two unequal parts, by temporarily trapping the unwanted charge under the first transfer electrode. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic sectional view showing a main portion (a vertical shift register and its transfer stage) of a CCD solid-state imager according to one embodiment of the present invention. Fig. 1B is a view showing a potential profile in the vertical shift register shown in Fig. 1A with all the transfer electrodes G 1 , G 2 , G 3 and G 4 held at the same potential. Figs. 2A and 2B are cross sectional views showing one process for fabricating the structure shown in Fig. 1A. Fig. 3 is a schematic view showing operations of the vertical shift register shown in Fig. 1A in the even field. Figs. 4A and 4B are sectional views showing a process for fabricating a modification of the structure shown in Fig. 1A. Fig. 4C is a view showing a potential profile in the vertical shift register shown in Fig. 4B with the first and second transfer electrodes G 1 and G 2 at a high level potential, and the third and fourth transfer electrodes G 3 and G 4 at a low level potential. Figs. 5A and 5B are schematic sectional view and schematic plan view of a vertical shift register in the odd field of a field readout mode. Figs. 6A and 6B are schematic sectional view and schematic plan view of a vertical shift register in the even field of the field readout mode. Fig. 7 is a time chart showing sequentially clocked vertical drive pulses V 1 , V 2 , V 3 and V 4 in the odd field in a conventional example. Fig. 8 is a schematic view showing operations of a conventional vertical shift register in the odd field. Fig. 9 is a time chart showing the vertical drive pulses in the even field. Fig. 10 is a schematic view showing operation of the conventional vertical shift register in the even field. Fig. 11 is a schematic view showing point defects in a picture produced by the conventional imager. DETAILED DESCRIPTION OF THE INVENTION Figs. 1A-4 show one embodiment of the present invention. A CCD imager according to this embodiment has vertical shift registers one of which is shown in Fig. 1A. This example employs a P-type substrate 1. In the section of Fig. 1A, an N-type diffusion layer 2 is formed on the P-type underlying layer of the substrate 1. The imager has a plurality of electrodes sets each of which consists of first, second, third and fourth transfer electrodes G 1 , G 2 , G 3 and G 4 . Each of the transfer electrodes G 1 , G 2 , G 3 and G 4 is formed on a gate insulating layer 3 which is in turn formed on the top surface of the N-type layer 2. In this example, the second and fourth transfer electrodes G 2 and G 4 are formed by a first (lower) polycrystalline silicon layer, and the first and third transfer electrodes G 1 and G 3 are formed by a second (upper) polycrystalline silicon layer. These transfer electrodes G 1 , G 2 , G 3 and G 4 are regularly arrayed (as shown in Fig. 3) in the vertical direction (the y direction in Fig. 1A) to form each of the vertical shift registers with the N-type top layer 2. The first transfer electrodes G 1 are all connected to an first clock input terminal for receiving a first drive pulse signal V 1 from a driver circuit (or driving means) 21 (shown in Fig. 8). The second transfer electrodes G 2 are all connected to a second clock input terminal for receiving a second drive pulse signal V 2 of the driver circuit 21. There are further provided a third clock input terminal, connected with all the third transfer electrodes G 3 , for receiving a third drive pulse signal V 3 , and a fourth clock input terminal, connected with all the fourth transfer electrodes G 4 , for receiving a fourth drive pulse signal V 4 . In this embodiment, there is further formed, under each first transfer electrode G 1 , a region 6 for forming a potential step ph shown in Fig. 1B by making the impurity concentration higher under each first electrode G 1 than under any of the second, third and fourth electrodes G 2 , G 3 and G 4 . In this embodiment, the region 6 is a highly doped N + -type region extending into the N-type top layer 2 from the top surface of the N-type layer 2. When the same voltage is applied to all the electrodes G 1 , G 2 , G 3 and G 4 , the potential is made higher only under the first electrodes G1, as shown in Fig. 1B, than the potential under the second, third and fourth electrodes G 2 , G 3 and G 4 . Figs. 2A and 2B show one fabricating process for the structure shown in Fig. 1A. As shown in Fig. 2A, the N-type top layer 2 used as the vertical shift register is first formed on the P-type silicon substrate 1. Then, the gate insulating film 3 of SiO2 is formed, on the top surface of the semiconductor substrate, by thermal oxidation. Thereafter, as shown in Fig. 2B, the second and fourth electrodes G 2 and G 4 are formed by depositing and patterning the first polysilicon layer. Then, the highly doped N + -type regions 6 are formed in the N top layer 2 by a step of ion implantation introducing the N-type impurities such as phosphorus (P) or arsenic (As), using a mask 5 having windows 4 opened at positions at which the first electrodes G 1 are to be formed. Then, as shown in Fig. 1A, the first and third transfer electrodes G 1 and G 3 are formed by patterning the second polysilicon layer. In this way, the impurity concentration can be made higher only under the first electrodes G 1 . The impurity concentration is substantially uniform in the N top layer 2 along the y direction under the second, third and fourth transfer electrodes G 2 , G 3 and G 4 . The CCD imager according to this embodiment of the invention is operated as shown in Fig. 3. The vertical shift register shown in Fig. 1A is clocked in the even field by the four drive pulse signals shown in Fig. 9 In Fig. 9, clock timings in an interval between t 0 ∼t 8 are determined according to an ordinary four-phase clock timing schedule for line shift (vertical scanning). The period T is a readout period for transferring signal charge from the sensing elements of the photosensitive imaging section to the vertical shift registers. At an initial instant t 0 shown in Figs. 3 and 9, the first and second drive pulse signals V 1 and V 2 are in the high level, and the third and fourth drive pulse signals V 3 and V 4 are in the low level. This state is an initial state of the vertical transfer. In this state, a continuous potential well is formed under each neighboring pair of the first and second transfer electrodes G 1 and G 2 held at the high level. In this state, unwanted non-signal charge such as smear charge and dark signal charge is accumulated in the potential step ph formed under each of the first transfer electrodes G 1 , as shown in Fig. 3. The unwanted charge is shown by parallel oblique lines in Fig. 3. At the first point t 1 in time, the third drive pulse signal V 3 is in the high level together with the first and second drive signals V 1 and V 2 , and therefore the potential well under each neighboring pair of the first and second electrodes G 1 and G 2 extends under the next third electrode G 3 . However, the unwanted charge is still held in the potential step ph under each first electrode G 1 . At the second point t 2 in time, the first drive pulse signal V 1 is switched to the low level, and lowers the potential under each first electrode G 1 . Therefore, the unwanted charge is transferred in the vertical shift direction, and stored under the second and third electrodes G 2 and G 3 . At the instant t 3 , the fourth drive signal V 4 is held in the high level together with the second and third signals V 2 and V 3 , and the unwanted charge is stored in the potential well formed under each neighboring group of the second, third and fourth electrodes G 2 , G 3 and G 4 . At the instant t 4 , the second drive pulse signal V 2 has been switched to the low level, and a potential barrier is formed under each second transfer electrode G 2 . Therefore, the unwanted charge is stored under each neighboring pair of the third and fourth electrodes G 3 and G 4 . At the instant t 5 , the potential is made higher again under each first electrode G 1 by the first drive pulse signal V 1 switched to the high level, and therefore, the unwanted charge is collected again in the potential step ph beneath each first electrode G 1 . At the instant t 6 , a potential barrier is formed under each third electrode G 3 with the third drive pulse signal V 3 in the low level. Nevertheless, the unwanted charge is still held in the potential step ph under each first electrode G 1 . At the instant t 7 , a potential well is formed under each second electrode G 2 by a rise of the second drive pulse signal V 2 to the high level. The unwanted charge yet remains in the potential step ph under each first electrode G 1 . At the instant t 8 , the fourth drive pulse signal V 4 is in the low level, and a potential barrier is formed under each fourth electrode G 4 . The unwanted charge is still in the potential steps ph. At the instant t 9 , the third drive pulse signal V 3 switched to the high level forms potential wells under the third electrodes G 3 . At the ninth instant t 9 , there are formed a plurality of threefold wide stepped potential wells each of which is formed under a neighboring group of the first, second and third transfer electrodes G 1 , G 2 and G 3 . Each of these stepped wells is deeper only under the first electrode G1, and slightly shallower under the second and third transfer electrodes G 2 and G 3 . Therefore, the unwanted charge is still trapped under the first transfer electrode G 1 . At the instant t 10 , potential barriers are formed under the second electrodes G 2 with the second drive pulse signal V 2 in the low level. In this case, the unwanted charge in each potential step ph is not divided into two portions, but all of the unwanted charge is persistently confined in each potential step ph. In the case of the conventional device, the formation of a potential barrier appearing under each second electrode at the instant t 10 causes uneven distribution of the unwanted charge as shown in Fig. 10. In the vertical shift register according to this embodiment of the invention, by contrast, the potential steps ph prevent nonuniform redistribution of the unwanted charge by holding the unwanted charges under the first electrodes G 1 . At the instant t 11 , although potential wells are formed under the fourth electrodes G 4 with the fourth signal V 4 in the high level, the unwanted charge is invariably held in the potential steps ph under the first electrodes G 1 . During the readout period T between t 10 and t 11 , signal charge packets are transferred from the sensing elements to the vertical shift register by the readout pulses applied to the first and third electrodes G 1 and G 3 , and accumulated in the potential wells under neighboring groups of the third, fourth and first electrodes G 3 , G 4 and G 1 , as shown by one dot chain lines in Fig. 3. Thereafter, the signal charge packets are transferred sequentially to a horizontal shift register under the control of the four-phase drive pulses V 1 ∼V 4 of proper phases, together with the unwanted charge. Fig. 4A shows a variation of the embodiment, in which the highly doped N + -type region 6 is formed only partially under each first electrode G 1 . In the example shown in Fig. 4A, the highly doped N + -type region 6 is formed by ion implantation only under the right half of each first electrode G 1 . As shown in Fig. 4A, a mask 5 is aligned to protect the silicon surface under the left halves of the first electrodes G 1 against the implanted ions. The original doping level of the N-type layer 2 is held unchanged under the left halves of the first electrodes as well as under the second, third and fourth electrodes G2, G3 and G4, as shown in Fig. 4B. When the high level potential is applied to the first and second electrodes G 1 and G 2 and the low level potential is applied to the third and fourth electrodes G 3 and G 4 , then a potential step ph is formed only in a portion corresponding to each highly doped region 6, as shown in Fig. 4C. Therefore, this structure can not only accumulate unwanted charge packets but also improve the vertical transfer efficiency of signal charge packets. In the examples shown in Figs. 1A and 4A, the highly doped regions 6 are used as a means for creating the potential steps ph under the first transfer electrodes G 1 . In this way, the CCD imagers according to the present invention can prevent nonuniform distribution of smear charge, and prevent defects in reproduced pictures.

Claims: A solid-state imager comprising: a photosensitive imaging section; first, second, third and fourth input terminals for receiving respectively first, second, third and fourth four-phase drive pulse signals (V 1 , V 2 , V 3 , V 4 ); and a four-phase vertical shift register comprising a plurality of electrode sets each of which consists of a first transfer electrode (G1) connected with said first input terminal, a second transfer electrode (G2) connected with said second input terminal, a third transfer electrode (G3) connected with said third input terminal and a fourth transfer electrode (G4) connected with said fourth input terminal, each of said first, second, third and fourth transfer electrodes (G1-G4) being regularly arranged on an insulating layer (3) which is formed on a top surface of an N-type toplayer (2) forming a buried channel extending on an underlying P-type semiconductor substrate layer (1), said vertical shift register being connected with said imaging section so that signal charge packets are transferred from the imaging section to the vertical shift register by applying a readout voltage (P) to each of said first and third transfer electrodes, characterized in that said substrate (1) further comprises N + -type regions (6) respectively formed under each of said first transfer electrodes (G1), said N + -type regions (6) having an impurity concentration which is higher under each first transfer electrode (G1) than under any of the second, third and fourth transfer electrodes (G2, G3, G4) to make the potential well under said first transfer electrode (G1) deeper than any of the potential wells under said second, third and fourth transfer electrodes (G2, G3, G4). The solid-state imager according to claim 1, wherein each of said first and third drive pulse signals (V 1 , V 3 ) assumes one of three different values (H, L, P). A method of producing a CCD imager comprising the steps of forming an N-type top layer (2) on an underlying P-type semiconductor substrate (1) layer, forming a plurality of electrode sets each of which consists of first, second, third and fourth transfer electrodes (G1, G2, G3, G4), each of said transfer electrodes being formed on an insulating layer (3) on a top surface of said N-type top layer (2) which thus forms a buried channel extending on said underlying P-type substrate layer (1), said first, second, third and fourth transfer electrodes (G1-G4) being regularly arranged to form a four-phase vertical CCD shift register, each of said first electrodes (G1) comprising a lower portion formed on said insulating layer (3), a first upper portion formed on a neighboring one of said fourth electrodes (G4) through an insulating film and a second upper portion formed on a neighboring one of said second electrodes (G2) through an insulating film, each of said third electrodes (G3) comprising a lower portion formed on said insulating layer (3), a first upper portion formed on a neighboring one of said second electrodes (G2) through an insulating film and a second upper portion formed on a neighboring one of said fourth electrodes (G4) through an insulating film; and forming an N + -type region (6) under each of said first transfer electrodes (G1), said N + -type regions (6) having an impurity concentration which is higher under each first transfer electrode (G1) than under any of the second, third and fourth transfer electrodes (G2, G3, G4) for making a potential well under each of said first transfer electrodes (G1) deeper than any of the potential wells under said second, third and fourth transfer electrodes (G2, G3, G4). The method according to claim 3, wherein said N + -type region (6) forming said potential well under each of said first transfer electrodes (G1) is formed by N-type ion implantation with anN-type dopant of phosphorus. The method according to claim 3, wherein said N + -type region (6) forming said potential well under each of said first transfer electrodes (G1) is formed by N-type ion implantation with an N-type dopant of arsenic. The method according to one of the claims 3 to 5, wherein said N + -type regions (6) forming said potential wells under each of said first transfer electrodes (G1) are respectively formed only partially under said first transfer electrodes (G1).

Inventors: KATO NAOKI, KATO, NAOKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H01L27
IPC codes: H01L27, H04N5, H04N3