THIN FILM TRANSISTOR HAVING A TRIPLE LAYER DIELECTRIC GATE INSULATOR, METHOD OF FABRICATING SUCH A THIN FILM TRANSISTOR AND AN ACTIVE MATRIX DISPLAY HAVING A PLURALITY OF SUCH THIN FILM TRANSISTORS

Abstract: In an active matrix display having a plurality of thin film transistors for selectively enabling and disabling pixels of the display, the improvement comprising a gate insulator for each of said thin film transistors having triple layer dielectric.

Description: T h in film transistor having a triple layer dielectric αate insula tor, method of fabricating such a thin film transistor an d an active matrix display having a plurality of such thin film tran ¬ sistors. Field of the Invention This invention relates in general to gate insulators 5 in thin film transistors (TFTs) , and more particularly to a triple layer dielectric for use as the TFT gate insulator in an active matrix liquid crystal display (AMLCD) . Background of the Invention 10 Active matrix liquid crystal displays (AMLCDs) are finding increasing application in the fields of avionics, computer monitors, television, etc. As the commercial viability of AMLCDs increases due to reduced fabrication costs, better viewing angle, etc., it is expected that 15 AMLCDs will increasingly replace well known CRT technology for such applications as television and computer terminal monitors since the AMLCD has significant advantages over CRT technology in terms of power consumption, weight and volume. 20 A TFT-based AMLCD typically comprises top and bottom polarizers and a TFT plate containing a matrix of transistors for selectively enabling and disabling associated LCD pixels. The gate dielectric in an active matrix display must 25 provide high breakdown voltage between the gate and data lines as well as adequate transconductance of the TFT switching device. The integrity of the gate dielectric is especially important for electro-optic display media such as electroluminescent films and NCAP (nematic 30 curvilinear aligned phase) materials, since these may require operating voltages approaching or exceeding 100V Traditionally, the gate insulating layer of a TFT comprises a single or double layer of appropriate dielectric material such a Si 3 N 4 , Sio 2 , SiO x N γ , Ta 2 0 5 , 35 or A1 2 0 3 . Summary of the Invention According to the present invention a triple layer SUBSTITUTE SHEET dielectric is provided for use as the TFT gate insulation in an active matrix display. The use of a triple layer dielectric in the form of a stacked film offers unique advantages over single layer dielectrics for electro-optic display media because of the high reliability and high dielectric strength provided by the triple layer dielectric in very large scale integrated circuits. According to an aspect of the invention, there is provided in an active matrix display having a plurality of thin film transistors for selectively enabling and disabling pixels of said display, the improvement comprising a gate insulator for each of said thin film transistors having a triple layer dielectric. Brief Description of the Drawings A description of the preferred embodiment is provided herein below with reference to the following drawings, in which: Figures la, lb and lc show successive steps in the fabrication process of a TFT with triple layer gate dielectric according to the preferred embodiment of the present invention; Figure 2 is a cross-sectional view of a capacitor structure fabricated for break-down field measurements between single layer and triple layer dielectrics; Figures 3 and 4 show breakdown field distributions for Si0 2 and triple layer insulation of Figure 2 with aluminum and chromium electrodes, respectively; Figure 5 shows drain current as a function of gate voltage for CdSe TFTs with Si0 2 and triple layer gate insulation; Figure 6 shows the drain current characteristics of a CdSe TFT at high drain voltage, for a TFT having triple layer gate insulation in accordance with the present invention; Figure 7 shows drain current as a function of gate SUBSTITUTE SHEET voltage for a further test CdSe TFT with Si0 2 and triple layer gate insulation in accordance with the present invention; and Figure 8 shows the time dependence of the drain current after switching from the OFF to ON state for CdSe TFTs with Si0 2 and ONO gate insulation. Detailed Description of the Preferred Embodiment Turning to Figures la, lb and lc illustrating the fabrication steps according to the present invention, a layer of chromium (Cr) is deposited on a Corning 7059 glass substrate 13, and patterned to form gate electrode 14. A 5000 A film of triple layer dielectric, serving as the gate insulator 15, is then deposited, followed by a 500 A layer of the evaporated CdSe semiconductor. After annealing, the semiconductor layer 16 is patterned and then passivated with a SiO x layer 17. Following this, indium tin oxide (ITO) is deposited and patterned to form the pixel output pad 18. The final two steps in the fabrication process are to open up contact vias 19a and 20a in the passivation oxide, deposit the source/drain metal, and pattern the metal to form the source and drain electrodes 19 and 20. The contact vias are formed by a dry etch process using reactive gasses. Since conductivity properties of the semiconductor are disturbed when the semiconductor is uncovered as a result of the reactive ion etch, a sputter etch is performed, according to the present invention, to etch away contaminated areas. A final anneal is then performed to ensure good oh ic contact between the semiconductor 16 and the source and drain electrodes 19 and 20. The gate insulation 15 is fabricated as a triple layer comprising the two oxide layers 4 and 5, and an intermediate dielectric layer 6. The insulation layer 15, as sub-divided into layers 4, 5, and 6 was characterized by total thickness of 500 nanometres, divided roughly evenly in thickness for each SUBSTITUTE SHEET of the layers 4, 5 and 6. However, for PECVD, the dielectric layer 6 may be of reduced thickness relative to oxide layers 4 and 5, in order to yield a slightly co pressive stress, as discussed below in greater detail. According to one embodiment of the invention, the layers 4, 6 and 5 are fabricated as Si0 2 /Si 3 N 4 /Si0 2 . According to another embodiment of the invention, the layers are formed as Si0 2 /Al 2 0 3 /Si0 2 . According to yet another embodiment of the invention, the layers are formed as Si0 2 /Ta 2 0 5 /Si0 2 . Furthermore, it is contemplated that nonstoichiometric films may be utilized wherein the oxide and dielectric layers may be designated as SiO x , A10 x , SiN x , TaO x , etc. A layer of semiconductor material 16 is deposited on the gate insulation layer in the usual manner. Metallic source and drain electrodes 19 and 20 are then deposited so as to contact the semiconductor layer. An additional pixel pad connector 18 may be deposited so as to contact the source electrode 20 where the TFT is to be used in an AMLCD. Finally, a transparent alignment layer 21 is deposited so as to overly the entire structure. According to the preferred embodiment, the triple layer gate insulation 15 was deposited by plasma enhanced chemical vapor deposition (PECVD) , although other fabrication techniques may be used.. The films 4, 5 and 6 are preferably deposited at 300°C to a combined total thickness which is sufficient for high voltage operation. As discussed in greater detail below, the triple layer gate insulation of the present invention is characterized by a much higher dielectric strength than the prior art single layer of Si0 2 , and provides similar transconductance in a TFT device. In order to conduct breakdown field measurements for the triple layer dielectric of the present invention, the capacitor structure of Figure 2 was fabricated. More particularly, two capacitors were fabricated - one to measure the breakdown characteristics of a single layer SUBSTITUTE SHEET oxide, and a second capacitor fabricated to test the breakdown characteristics of the triple layer dielectric of the present invention. The Si0 2 layers were deposited using gas phase combinations of SiH 4 , He, N 2 0. The SiN x films were deposited in the same reactor using SiH 4 , He, NH 3 and N 2 . The deposition system utilized a capacitively coupled parallel plate design with 13.56 megahertz as the excitation frequency. Substrates were placed on the grounded lower electrode, and the deposition rate was 8.5 nm/min for Si0 2 and 2.3 nm/min for SiN x . The resulting structure of Figure 2 shows a glass substrate 20, onto which a "layer under test" 21 of either Si0 2 according to the first test capacitor, or ONO according to the second test capacitor, was deposited. The dielectric layer 21 was 150 n thick in the case of the first capacitor utilizing Si0 2 , and was 60/60/60 nm thick with ONO used for the second test capacitor. These thicknesses resulted in the same capacitance per unit area for both device types and resulted in the same oxide field for a given applied voltage. Electrodes 22 and 23 were deposited covering a device area of 0.012 cm 2 and were composed in one instance of sputtered Al and in another instance of sputtered Cr. Aluminum contacts 24 and 25 were deposited on the electrodes 22 and 23, respectively, and the completed capacitors received an anneal (not shown) in the usual manner. Where the electrodes 22 and 23 are fabricated as Al, then the additional contact deposition 24 and 25 may be omitted and the electrode 23 deposited to a greater thickness. As discussed in greater detail below, the average ramp rate during break down testing was lV/s. In order to examine the characteristics of the triple layer dielectric of the present invention, films were deposited for ellipsometry, stress and FT-IR measurements. These films were deposited on Si wafers which were polished on both sides. All samples received SUBSTITUTE SHEET a 45 minute anneal in N 2 ambient 400°C. The stress was determined by measuring the change of wafer curvature resulting from the film deposition and anneal. Infrared absorption spectra were obtained using a Nicolette™ 5 DXC spectrometer with a resolution of 16 cm "1 . An Si wafer identical to the sample substrates was used as a reference. Table I summarizes the results of the ellipsometry and stress measurements for the deposited films. The index of refraction (at 633 nm) of the Si0 2 was higher than that of thermally grown oxide, suggesting that the films were oxygen deficient or had some nitrogen content. Thus it is possible that the film grown was in fact a form of siliconoxynitride (SiO x N γ ) , although much closer to silicon dioxide than to silicon nitride. It has been found that by varying the values of X and Y a continuous variation is possible between silicon oxide and silicon nitride. The results of Table 1 show that the stress was compressive in the Si0 2 and tensile in the SiN x . When the two materials were combined in an ONO structure, a net tensile stress of relatively low magnitude was obtained. By reducing the relative thickness of the nitride layer, further reduction in the tensile stress and even slightly compressive ONO films were obtained. Table I. Ellipsometry and stress measurements. Target Ellipsometry Film Thickness Thickness Index of Stress (nm) (nm) Refraction (MPa) Si0 2 150 145 1.513 -89 SiN x 70 69 1.899 210 ONO 60/60/60 33 Returning to the capacitor structure of Figure 2 , SUBSTITUTE SHEET for metal-insulator-metal (MIM) capacitors with aluminum electrodes, the dielectric breakdown events were spatially localized and self-healing. Consequently, up to four breakdown events were recorded for each device. A total of 40 devices were tested for each device type, giving 160 breakdown events. The resulting breakdown field distributions are shown in Figure 3. For the ONO film, the field was calculated using the effective oxide thickness with the ONO film (ie. the thickness required to give the same capacitance per unit area as given when the entire layer is Si0 2 ) , with the mean breakdown field being 4.3 MV/cm for Si0 2 and 7.8 MV/cm for ONO. The dielectric breakdown events for capacitors with Cr electrodes were qualitatively different from those with Al electrodes in a number of respects. First of all, most of the breakdown events with the Cr electrodes were not self-healing. This resulted in a requirement to test more devices in order to record the same number of breakdown events. Also, it was discovered that if a series resistor was not used in the driving circuit, the damaged region would propagate from the initial breakdown point. In some cases, the damage would consume the entire the area of the capacitor. A chemical reaction between the chromium, silicon dioxide and ambient air was likely responsible for this effect. Finally, a much larger proportion of the breakdown events were initiated where the top metal crossed over the bottom metal edge. In an actual display panel, such events could be avoided by improving the slope of the bottom metal edge, or by adding field oxide to the gate insulation at these edges. Figure 4 shows the breakdown field distributions for the capacitors with chromium electrodes. The breakdown events were more broadly distributed, which is consistent with defect-related breakdown. However, the dielectric strength was again improved with the ONO film, with the mean breakdown field being 4.35 MV/cm for Si0 2 and 8.7 MV/cm for ONO. su: f U i ___> ET Figure 5 shows the drain current as a function of gate voltage for a CdSe TFT with single layer Si0 2 gate insulation compared to the ONO gate insulation 15 of the TFT transistor according to the present invention (Figure 1) . Both insulation types exhibited the same capacitance per unit area, with an equivalent oxide thickness of 150 nanometres. The transistors were 25 μm long and 36 μm wide. Good switching characteristics were obtained for both device types. However, the ONO curve rises a little more quickly in the subthreshold region and is characterized by a slightly higher ON current. Figure 6 shows the drain current characteristics of the CdSe TFT structure of Figure l , at high drain voltage. The device was 60 μm long, 36 μm wide and had ONO gate insulation 15 with layer thicknesses 200/100/200 nm. The device had good transistor characteristics up to a drain voltage of 200 volts, which was the maximum limit of the test apparatus. For very thin ONO films, charge trapping in the nitride layer can produce a reversible threshold voltage shift [S.K. Lee, J.H. Chen, Y.H. Ku, D.L. Kwong, B.Y. Nguyen and K.W. Tseng, Solid State Electron 3JL, 1501 (1988)]. This effect is greatly reduced by providing a thick ONO film in accordance with the invention, whereby the tunneling current is greatly reduced. Further testing has been undertaken to compare the properties of thin film transistor with Si0 2 and ONO gate and to determine whether the D.C. drift was degraded by the presence of the nitride layer. For the thickness range considered, the nitride layer was found to have no effect on the D.C. drift, and the subthreshold swing was improved with the ONO films. Figure 7 shows the drain current as a function of gate voltage for two further CdSe thin film transistors under test, one with 440 nm thick Si0 2 gate insulation, and the other with 180/130/180 nm think ONO gate insulation. The capacitance per unit area was SUBSTITUTE SHEE ' approximately the same (within 10%) for both insulator types. The devices were fabricated as described in detail above, and had dimensions 40 x 36 μm (lxw) . The drain current of the ONO device rose more quickly in the subthreshold region and reached a higher ON current. The subthreshold swing near I D = 1 nA averaged 1.31 V/decade for Si0 2 devices and 0.83 V/decade for ONO devices. Figure 8 shows the normalized drain current as a function of time after switching from the OFF to ON state. For high drain voltage, the initial current exceeded 100 μA for both device types (slightly more for ONO) . The curves were quite similar for both device types, indicating that the nitride layer in the ONO films does not degrade the drift. The integrity of the gate dielectric is an important consideration for the display media such as electroluminescent films and NCAP (nematic curvilinear aligned phase) materials, which require high operating voltage. The present invention provides for high dielectric strength ONO films being substituted for single layer Si0 2 without degrading the transconductance or drift of CdSe thin film transistors. The subthreshold swing is in fact improved with the ONO films of the present invention. In summary according to the present invention, ONO gate dielectrics as deposited by PECVD have been found to exhibit lower stress and greater dielectric strength than single layer Si0 2 . These improvements were obtained without sacrificing the transconductance of the switching device. In an active matrix display, the ONO films permit higher voltage operation and provide greater versatility in the choice of display media than is possible with single layer Si0 2 gate insulation. Other embodiments and variations of the invention are possible. For example, the TFT with triple-layer dielectric of the present invention may be used in various types of display media other than AMLCDs, such as SUBSTITUTE SHEET NCAP materials, electroluminescent films, etc. Furthermore, the TFT of the present invention may be of any suitable structure (eg. non inverted design, or provided with bottom contacts) . All such variations and modifications are believed to be within the sphere and scope of the claims appended hereto. SUBSTITUTE SHEET

Claims: THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OF PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS: 1. In an active matrix display having a plurality of thin film transistors for selectively enabling and disabling pixels of said display, the improvement comprising a gate insulator for each of said thin film transistors having triple layer dielectric. 2. The improvement of claim 1, wherein said triple layer dielectric further comprises a pair of SiO x films and an SiN x film therebetween. 3. The improvement of claim 1, wherein said triple layer dielectric further comprises a pair of SiO x films and an A10 x film therebetween. 4. The improvement of claim 1, wherein said triple layer dielectric further comprises a pair of SiO x films and a TaO x film therebetween. 5. A thin film transistor, comprising: a) a glass substrate; b) a gate electrode deposited on said substrate; c) a gate insulator layer having triple layer dielectric deposited on said electrode so as to overly said gate electrode; d) a thin film semiconductor channel layer deposited on said gate insulator layer and substantially aligned with said gate electrode; e) an alignment layer deposited on said gate insulator layer so as to overly said thin film semiconductor channel layer; and f) a pair of source and drain electrodes deposited on said alignment layer and extending through a portion of said alignment layer for contacting said SHEE semiconductor channel layer. 6. The thin film transistor of claim 5, wherein said triple layer dielectric further comprises a pair of SiO x films and an SiN x film therebetween. 7. The thin film transistor of claim 5, wherein said triple layer dielectric further comprises a pair of SiO x films and an A10 x film therebetween. 8. The thin film transistor of claim 5, wherein said triple layer dielectric further comprises a pair of SiO x films and an TaO x film therebetween. 9. The thin film transistor of claim 5, wherein said gate electrode is fabricated from chromium. 10. The thin film transistor of claim 5, wherein said thin film semiconductor channel layer is fabricated from CdSe. 11. The thin film transistor of claim 5, further comprising a pixel output pad intermediate respective portions of said alignment layer and said drain electrode. 12. A method of fabricating a thin film transistor, comprising the steps of: a) providing a substrate; b) depositing a gate electrode on said substrate; c) depositing a gate insulator layer having triple layer dielectric on said substrate so as to overly said gate electrode; d) depositing a thin film semiconductor channel layer on said gate insulator layer so as to be substantially aligned with said gate electrode; su; I U f SHEET e) depositing an alignment layer on said gate insulator layer so as to overly said thin film semiconductor channel layer; and f) depositing a pair of source and drain terminals on said alignment layer and extending through said alignment layer so as to contact said semiconductor channel layer. SUBSTITUTE SHEET

Inventors: WAECHTER DAVID, WAECHTER, DAVID
Applicants: LITTON SYSTEMS CANADA, WAECHTER DAVID, LITTON SYSTEMS CANADA LIMITED, WAECHTER, DAVID
Application year: 1992
Main classification: H01L29
IPC codes: H01L21, H01L29