Repeater station wherein input frame data are accessible

Abstract: A repeater station comprises an RFD frame synchronization circuit (32), an AND gate (34), and an IFD frame synchronization circuit (36). The RFD frame synchronization circuit (32) outputs a frame synchronization signal indicating the timing of an auxiliary signal by performing frame synchronization with regard to the RFD. The AND gate (34) inhibits clock signals during periods of the auxiliary signals and allows the clock signals to pass through during the other periods. The IFD frame synchronization circuit (36) performs frame synchronization of the RFD with regard to the IFD by carrying out frame synchronization operation in accordance with the clock signals output from the AND gate (34). The IFD are accessible in the above simple construction.

Description: The present invention relates to a repeater station for relaying transmission signals, preferably with amplification and/or shaping ot the transmission signals in a radio transmission system. More particularly, the present invention is concerned with the repeater station adapted to a digital multiplex radio transmission system wherein radio frame data constructed by inserting auxiliary signals for radio transmission into input frame data including multiple signals are transmitted and relayed. In a general digital multiplex radio transmission system, RFD (Radio Frame Data) are constructed in sending end by inserting auxiliary signals into IFD (Input Frame Data) which are multiple signals conforming to a prescribed frame form. The RFD are modulated in a modulator and then transmitted from a transmitter. The auxiliary signals include a frame synchronization signal for frame synchronization of the RFD, an error-correcting code for detecting and correcting errors in radio transmission, and a signal of a digital service channel, etc. In receiving end, the signal received in a receiver is demodulated in a demodulator and the auxiliary signals are removed to reproduce the IFD. Necessary number of repeater stations are located between the sending end and the receiving end. In the repeater station, received signal is demodulated into a baseband signal. The baseband signal is shaped by synchronizing with a clock signal ticking time of the baseband signal and the shaped baseband signal is again modulated and then transmitted. If the auxiliary signal must be read/written in the repeater station, frame synchronization with regard to the RFD is performed to give access to the auxiliary signal. As mentioned above, in the general digital multiplex radio transmission system, it is enough for operations of the repeater station that frame synchronization with regard to the RFD is possible. However, there is a special case where information included in the IFD must be accessible. The case is, for example, where signals conforming to a frame form prescribed in an NNI (Network Node Interface) in an ISDN (Integrated Services Digital Network) are transmitted. A data frame conforming to an SDH (Synchronous Digital Hierarchy) as the NNI includes an SOH (Section OverHead) area containing network management information. The network management information includes information for watching repeater stations. Accordingly, also in the repeater station, the SOH must be accessible, that is, the IFD must be accessible in the repeater station relaying the SDH frames. Nevertheless, access to the IFD is not easy in the repeater station, because the RFD is generally constructed in asynchronism with the frame form of the IFD and therefore the IFD does not become accessible only by frame-synchronizing with the RFD. This problem may be overcome if the RFD is constructed by inserting the auxiliary signals in synchronism with the frame form of the IFD. Then, the IFD becomes accessible only by frame-synchronizing with the RFD. However, this solution raises another problem that a degree of freedom in design of the frame form of the RFD is lowered. If the ratio of the auxiliary bits, especially, the ratio of the error correcting code inserted to construct the RFD is higher, capability of error correction is higher but the transmission rate must be elevated and therefore the bandwidth occupied in the radio frequency becomes large. For this reason, an appropriate frame form of the RFD must be designed in accordance with the quality of the radio transmission path by trading off both factors. Thus, the fact that the degree of freedom in design of the RFD is lowered is unfavorable. The IFD may also become accessible in a construction where the auxiliary signals are removed after frame synchronization with the RFD; the transmission rate is altered using an elastic memory to obtain the IFD, and then frame synchronization with the IFD is performed, in the repeater station, as is usually done in the receiving end. But this construction is complex and requires large size circuits. Reference is made to JP 61 094 426 and its Patent Abstract of Japan, vol. 10, No. 272 (E-437). This reference, with particular reference to Fig. 2(a) thereof discloses a repeater which relays a signal having a frame format in which bit portions of surplus bits (AUX) relative to Frame bits (F) are fixed. It is an object of the present invention to provide a repeater station having a simple construction and enabling access of information contained in an original frame form of data even if a transmission frame constructed in asynchronism with the original frame form is relayed. In accordance with the present invention, there is provided a repeater station for relaying a series of first information signals obtained by demodulation of a received signal and constructed by inserting first auxiliary signals in accordance with a first frame form into a series of second information signals including second auxiliary signals conforming to a second frame form, comprising: first frame synchronisation means to which the first information signals and a clock signal ticking time of the first information signals are input for outputting first timing signals indicating the timing of the first auxiliary signals by operating in accordance with the clock signal, gate means to which the clock signal and the first timing signals are input for inhibiting the clock signal at the timing of the first auxiliary signals and for allowing the clock signal to pass through otherwise, and second frame synchronisation means to which the first information signals and the clock signal passing through the gate means are input for outputting second timing signals indicating the timing of the second auxiliary signals included in the first information signals by operating in accordance with the clock signal passing through the gate means. The invention will be better understood by referring, by way of example, to the accompanying drawings, in which:- Figure 1 is a schematic block diagram of a digital multiplex radio transmission system according to an embodiment of the present invention; Figure 2A is a diagram showing a schematic frame form of a SDH frame as an IFD; Figure 2B is a diagram showing schematic frame form of an RFD; Figure 3 is a block diagram showing more detailed construction of the IFD access circuit 24 of Fig. 1; Figures 4A to 4D are waveform diagrams for explaining an operation of the circuit 24 of Fig. 1; Figure 5 is a block diagram showing a more detailed construction of the RFD frame synchronization circuit 32 of Fig. 3. Figure 6 is a circuit diagram showing a more detailed construction of the SOH separation circuit 38 of Fig. 3; and Figure 7 is a circuit diagram showing a more detailed construction cf the SOH insertion circuit 40 of Fig. 3. Figure 1 is a schematic block diagram of a digital multiplex radio transmission system including repeater station according to an embodiment of the present invention. In Fig. 1, a transmitting station 10, the repeater station 12 and a receiving station 14 are shown. In the transmitting station 10, an auxiliary signal S is inserted into IFD (Input Frame Data) having a frame form of SDH (Synchronous Digital Hierarchy) frame according to a frame form of RFD (Radio Frame Data), to form RFD, in an auxiliary signal inserting circuit 16. The RFD is modulated and transmitted from the transmitter 18. The repeater station 12 includes a receiver 20 for receiving the signal and for demodulating the received signal to output a baseband signal, a waveform shaping circuit 22 for shaping the baseband signal by synchronizing with a clock signal ticking time of the baseband signal, an IFD access circuit 24 (described later in detail), and a transmitter 26. In the receiving station 14, the signal is received and demodulated in a receiver 28 to reproduce the RFD at baseband. In an auxiliary signal separating circuit 30, the auxiliary signal S is separated and the transmitting rate is altered to reproduce the IFD. Figure 2A shows a schematic frame form of the SDH frame prescribed as NNI of ISDN. In the SDH frame, a Row consists of a hatched SOH (Section OverHead) and a payload section P, and the nine Row constitutes a frame. When IFD having a frame form shown in Fig. 2A is radio-transmitted, auxiliary signals S are inserted in accordance with a prescribed frame form of RFD as shown in Fig. 2B. As shown in Figs. 2A and 2B, the auxiliary signals S are inserted into the IFD in asynchronism with the frame form of the IFD. Figure 3 is a block diagram showing a more detailed construction of the IFD access circuit 24 of Fig. 1. An RFD frame synchronization circuit 32 operates according to a clock signal ticking time of the baseband signal. In the circuit 32, frame synchronization of the input signal is done with regard to frame form of RFD. After the frame synchronization has been established, the circuit 32 outputs a synchronization signal in each timing of the auxiliary signal included in the RFD. The signal output from the circuit 32 is input to one input of an AND gate 34, and the clock signal is input to another input of the AND gate 34. Therefore, each time the signal indicating the timing of the auxiliary signal is output from the circuit 32, the AND gate 34 is closed to inhibit the clock signal. Thus, the clock signal output from the AND gate 34 ticks time of RFD except for the auxiliary signals, that is, only time corresponding to IFD included in the RFD. In an IFD frame synchronization circuit 36, frame synchronization of an input signal is performed with regard to a frame form of IFD. Since the RFD and the clock signal ticking time of the IFD signal are input to the circuit 36, the circuit 36 performs the frame synchronization operation according to the clock signal ticking time of the IFD, as if the RFD input were the IFD. Thus, the IFD frame synchronization circuit 36 can output a signal indicating the timing of the SOH included in the IFD. An SOH separation circuit 38 reads out the SOH from the RFD according to the output signal of the circuit 36. An SOH insertion circuit 40 writes the SOH on the RFD. Figures 4A to 4D are waveform diagrams showing waveforms in lines denoted by a to d in Fig. 3, respectively. Referring to Fig. 4A, the RFD is constructed by inserting the auxiliary signal S into the IFD constituted by the SOH and the payload section P. Fig. 4B shows the original clock signal. As shown in Fig. 4C; the signal output from the RFD frame synchronization circuit 32 becomes L level only during the period of the auxiliary signal S. The clock signal is inhibited during this period by the AND gate 34, as shown in Fig. 4D. Therefore, the operation of the IFD frame synchronization circuit 36 is interrupted during this period and is continued during the other periods according to the clock signal, and thus the circuit 36 can perform a frame synchronization operation as if the IFD were input though the RFD is input in reality. Figure 5 is a block diagram showing a more detailed construction of the RFD frame synchronization circuit 32 of Fig. 3. The RFD are compared in a data comparison unit 42 with a frame synchronization pattern generated in a frame synchronization pattern generation unit 44 constructed so as to cyclically generate the frame synchronization pattern operating in accordance with the input clock signal. The comparison results are given to a synchronism protection unit 46. The synchronism protection unit 46 lets a clock inhibition unit 48 inhibit the clock signal to pass through if coincidence is not detected in the data comparison unit 42, and releases the clock inhibition unit 48 from inhibition of a clock signal if coincidence is detected in the data comparison unit 42. If the coincidence is successively detected during a predetermined period, the synchronism protection unit 46 enters a synchronism establishment mode where the clock inhibition unit 48 permits the clock signal to pass through until the mode is released. If disagreement is successively detected during a predetermined period, the synchronism protection unit 46 regards it as pulling out of synchronism, and the synchronism establishment mode is released. Accordingly, during the synchronism establishment mode, the frame synchronization pattern generation unit 44 and a synchronization pulse generation unit 50 operating in synchronism with the frame synchronization pattern generation unit 44 are successively supplied with the clock signal to renew their operation steps. Therefore, during this mode, the frame synchronization pattern generation unit 44 cyclically outputs the frame synchronization pattern to the data comparison unit 42 in accordance with the frame form of the RFD, and the synchronization pulse generation unit 50 cyclically outputs a frame synchronization pulse, i.e., a signal indicating the timing of the auxiliary signals, in accordance with the frame form of the RFD. The IFD frame synchronization circuit 36 has a construction essentially similar to that of the RFD frame synchronization circuit 32, except that the frame synchronization pattern generation unit 44 and the synchronization pulse generation unit 50 operate in accordance with the frame form of the IFD and the synchronization pulse generation unit 50 outputs a signal indicating the timing of the SOH, as the frame synchronization pulse. Figure 6 is a circuit diagram of the SOH separation circuit 38 of Fig. 3. The RFD are input to one input of an AND gate 52, and the synchronization pulses indicating the timing of the SOH output from the IFD frame synchronization circuit 36, are input to another input of the AND gate 52. Therefore, the SOH is separately obtained in an output of the AND gate 52. Figure 7 is a circuit diagram of the SOH insertion circuit 40 of Fig. 3. The SOH is stamped out by the synchronization pulses output from the IFD frame synchronization circuit 36 in an AND gate 54. The RFD except for the SOH are stamped out in an AND gate 56 by an inverted synchronization pulses made in an inverter 58. Output signals of the AND gates 54 and 56 are input to an OR gate 60. The renewed RFD are obtained in an output of the AND gate 60. Although the aforementioned embodiment is described with regard to the case where signals conforming to the frame form prescribed in NNI of ISDN are radio-transmitted; the present invention is obviously applicable to a radio or line transmission system for transmitting general digital multiplex signals. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A repeater station for relaying a series of first information signals obtained by demodulation of a received signal and constructed by inserting first auxiliary signals in accordance with a first frame form into a series of second information signals including second auxiliary signals conforming to a second frame form, comprising: first frame synchronisation means (32) to which the first information signals and a clock signal ticking time of the first information signals are input for outputting first timing signals indicating the timing of the first auxiliary signals by operating in accordance with the clock signal; gate means (34) to which the clock signal and the first timing signals are input for inhibiting the clock signal at the timing of the first auxiliary signals and for allowing the clock signal to pass through otherwise, and second frame synchronisation means (36) to which the first information signals and the clock signal passing through the gate means are input for outputting second timing signals indicating the timing of the second auxiliary signals included in the first information signals by operating in accordance with the clock signal passing through the gate means. A repeater station as claimed in claim 1, further comprising: information separating means (38) to which the first information signals and the second timing signals are input for reading-out the second auxiliary signals from the first information signals, and information insertion means (40) to which the first information signals and the second timing signals, are input for inserting the second auxiliary signals on the first information signals. A repeater station as claimed in claim 1 or 2, wherein the first frame synchronization means include: a clock inhibition unit (48) for inhibiting the clock signal or allowing the clock signal to pass through; a frame synchronization pattern generation unit (44) for cyclically generating a frame synchronization pattern conforming to the first frame form, operating in accordance with the clock signal from the clock inhibition unit; a data comparison unit (42) for comparing the first information signals with the frame synchronization pattern; a synchronism protection unit (46) for letting the clock inhibition unit inhibit the clock signal if coincidence is not detected in the data comparison unit, for letting the clock inhibition unit to allow the clock signal to pass through if coincidence is detected in the data comparison unit, and for letting the clock inhibition unit to continue allowing the clock signal to pass through after coincidence is successively detected during a predetermined period in the data comparison unit until disagreement is successively detected during a predetermined period in the data comparison unit, and a synchronization pulse generation unit (50) operating in synchronism with the synchronization pattern generation unit for outputting the first timing signals. A repeater station as claimed in claim 1, 2 or 3, wherein the second frame synchronization means include: a clock inhibition unit for inhibiting the clock signals or allowing the clock signal to pass through; a frame synchronization pattern generation unit for cyclically generating a frame synchronization pattern conforming to the second frame form, operating in accordance with the clock signal from the clock inhibition unit; a data comparison unit for comparing the first information signals with the frame synchronization pattern; a synchronism protection unit, for letting the clock inhibition unit inhibit the clock signals if coincidence is not detected in the data comparison unit, for letting the clock inhibition unit to allow the clock signal to pass through if coincidence is detected in the data comparison unit, and for letting the clock inhibition unit to continue allowing the clock signal to pass through after coincidence is successively detected during a predetermined period in the data comparison unit until disagreement is successively detected during a predetermined period in the data comparison unit, and a synchronization pulse generation unit operating in synchronism with the synchronization pattern generation unit for outputting the second timing signals. A repeater station as claimed in any of preceding claims, wherein the second frame form is a frame form conforming to Synchronous Digital Hierarchy in Integrated Services Digital Network.

Inventors: SUZUKI EIJI, SUZUKI, EIJI, SUZUKI, EIJI, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H04J3
IPC codes: H04J3, H04Q11