Image transmission method, and apparatus therefor

Abstract: The secrecy of data transmitted by an image transmission apparatus can be maintained by performing encoding or decoding in conformity with identification information specifying the apparatus. The image transmission apparatus, which is for dynamically converting the image data accumulated in a memory into an arithmetic code and then transmitting the code, is so adapted that, on the sending side, an initializing table for the purpose of encoding is read out of an initializing ROM based upon an ID specifying the apparatus, and a CODEC 107 performs encoding based upon the table. The encoded data is transmitted via a CCU and is decoded on the receiving side in the same manner as encoding was performed on the sending side. As a result, the secrecy of the contents of the communication can be maintained.

Description: This invention relates to an image transmission method and apparatus, in which input image data is compressed and the compressed image data is transmitted. More particularly the invention relates to an image transmission method and apparatus in which enciphering is performed in addition to compression, to maintain confidentiality. In the prior art, for example, a dynamic arithmetic encoding method has been proposed as an encoding method for encoding a black-and-white binary image. This encoding system involves predicting whether a pixel is "0" or "1", performing arithmetic dynamically depending upon whether the prediction is correct or erroneous, and then encoding. The JBIG standard is such a system. With this dynamic arithmetic encoding method, however, a drawback is that absolutely no consideration is given to enciphering data when the encoded data is transmitted, and therefore the confidentiality of the contents of a communication cannot be maintained. The drawback also exists in other encoding systems, for example, ADCT (Adaptive Discrete Cosine Transform). The present invention is defined in the appended claims and combines encryption with compression encoding by providing an image transmission apparatus comprising: compression encoding means for compressing input image data by a compression process to reduce an amount of data to be transmitted; and characterised by initialising means for setting a parameter of said compression process on the basis of identification information (ID) which specifies an apparatus said identification information being known to both the encoding and decoding apparatus, such that said compression encoding means also effects encrypting so as to improve the confidentiality of the data, by compressing using said parameter. In a preferred embodiment, the initialising means includes memory means for storing a plurality of initialising tables selected in dependence upon the identification information, and selecting means for selecting an initialising table stored by the memory means, wherein initialisation of a predicted-state memory for encoding is performed by the initialising table selected by the selecting means. Another object of the invention is to provide an efficient image data transmission method. Further object of this invention is to provide a simple structure of an image encoding or decoding apparatus. Still further object of this invention is to provide an image encoding or decoding apparatus easy to operate for an operator. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating the construction of an ordinary image transmission apparatus; Fig. 2 is a block diagram illustrating the construction of the encoder within a CODEC shown in Fig. 1; Fig. 3 is a block diagram illustrating the construction of a predicting unit shown in Fig. 2; Fig. 4 is a block diagram illustrating the construction of an arithmetic encoder shown in Fig. 2; Figs. 5 through 14 are flowcharts illustrating the encoding processing of the encoder shown in Fig. 2; Fig. 15 is a block diagram illustrating the construction of a decoder within the CODEC shown in Fig. 1; Fig. 16 is a block diagram illustrating the construction of an arithmetic decoder shown in Fig. 15; Figs. 17 through 23 are flowcharts illustrating the decoding processing of the encoder shown in Fig. 15; Fig. 24 is a diagram showing a value of P with respect to an index 1; Fig. 25 is a block diagram illustrating the construction of an image transmission apparatus according to an embodiment; Fig. 26 is a block diagram illustrating the construction of the encoder in a first embodiment; Fig. 27 is a circuit diagram of an ID switch shown in Fig. 26; Fig. 28 is a flowchart illustrating the operation of encoding in the first embodiment; Fig. 29 is a block diagram illustrating the construction of a decoder in the first embodiment; Fig. 30 is a flowchart illustrating the operation of decoding in the first embodiment; Fig. 31 is a block diagram illustrating the construction of the encoder in a second embodiment; Fig. 32 is a flowchart illustrating the operation of encoding in the second embodiment; Fig. 33 is a block diagram illustrating the construction of a decoder in the second embodiment; Fig. 34 is a flowchart illustrating the operation of decoding in the second embodiment; Fig. 35 is a block diagram illustrating the construction of the encoder in a third embodiment; Fig. 36 is a flowchart illustrating the operation of encoding in the third embodiment; Fig. 37 is a block diagram illustrating the construction of a decoder in the third embodiment; Fig. 38 is a flowchart illustrating the operation of decoding in the third embodiment; Fig. 39 is a block diagram illustrating the construction of the encoder in a fourth embodiment; Fig. 40 is a flowchart illustrating the operation of encoding in the fourth embodiment; Fig. 41 is a block diagram illustrating the construction of a decoder in the fourth embodiment; Fig. 42 is a flowchart illustrating the operation of decoding in the fourth embodiment; Fig. 43 is a block diagram illustrating the construction of the encoder in a fifth embodiment; Fig. 44 is a flowchart illustrating the operation of encoding in the fifth embodiment; Fig. 45 is a block diagram illustrating the construction of a decoder in the fifth embodiment; Fig. 46 is a flowchart illustrating the operation of decoding in the fifth embodiment; Fig. 47 is a block diagram illustrating the construction of the encoder in a sixth embodiment; Fig. 48 is a flowchart illustrating the operation of encoding in the sixth embodiment; Fig. 49 is a block diagram illustrating the construction of a decoder in the sixth embodiment; Fig. 50 is a flowchart illustrating the operation of decoding in the sixth embodiment; Fig. 51 is a block diagram illustrating the construction of the encoder in a seventh embodiment; Fig. 52 is a flowchart illustrating the operation of encoding in the seventh embodiment; Fig. 53 is a block diagram illustrating the construction of a decoder in the seventh embodiment; Fig. 54 is a flowchart illustrating the operation of decoding in the seventh embodiment; Fig. 55 is a block diagram illustrating the construction of the encoder in an eighth embodiment; Fig. 56 is a flowchart illustrating the operation of encoding in the eighth embodiment; Fig. 57 is a block diagram illustrating the construction of a decoder in the eighth embodiment; Fig. 58 is a flowchart illustrating the operation of decoding in the eighth embodiment; and Figs. 59 - 66 are flowcharts illustrating the operation of encoding and decoding in other embodiments of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. First, a dynamic arithmetic encoding method will be described in detail. Fig. 1 is a block diagram illustrating an example of an ordinary image transmitting apparatus which employs a dynamic arithmetic encoding method. The apparatus includes a main CPU 101 which carries out overall control of the other blocks, an operation panel 102 at which the user controls the image transmission apparatus, a program memory 103, such as a ROM, storing various programs executed by the main CPU 101, and a user memory 104, such as a RAM, in which data registered by the user, such as numbers for abbreviated dialing, is stored. The apparatus further includes a scanner/printer 105 for reading in or printing out an image, an image processor 106 which executes binarization processing or the like, a CODEC 107 which performs encoding or decoding by means of dynamic arithmetic encoding, a CCU 109 which controls interfacing with a line, an image memory 110, such as a hard disk or RAM, for memory stored transmission and memory reception, and a line 111, such as a public telephone line or leased line. Fig. 2 is a block diagram of a dynamic arithmetic encoder included in the CODEC 107 mentioned above. As shown in Fig. 2, the dynamic arithmetic encoder includes a predicting unit 114 for referring to pixels peripheral to a pixel an, and a predicted-status memory (RAM) 115 which, based upon peripheral-pixel values S 11-0 outputted by the predicting unit 114, stores an index 1, which indicates the states of these values, and a superiority symbol MPS. Also provided are an initializing unit 113 for clearing the predicted-state memory 115 to "0" by an initialization operation, an arithmetic-parameter ROM 116 which outputs the probability P of an inferiority symbol according to the index 1 outputted by the predicted-status memory 115, an arithmetic encoder 117 for performing arithmetic encoding dynamically from the probability P delivered by the arithmetic-parameter ROM 116, the superiority symbol MPS from the predicted-state memory 115, and the value Xn of the pixel of interest from the predicting unit 114, and an updating unit 118 for updating the index 1 of the predicted-state memory 115 in accordance with whether the superiority symbol MPS and the value Xn of the pixel of interest agree or not. Fig. 3 is a block diagram illustrating the predicting unit 114 shown in Fig. 2. The predicting unit 114 includes FIFOs 123 for four lines, a predicting template 124 for outputting Xn as the pixel of interest and values of 12 ∼ 1 in Fig. 3 and the values of S 11-0 . Fig. 4 is a block diagram illustrating the construction of the arithmetic encoder 117 shown in Fig. 2. The arithmetic encoder 117 includes a subtractor 125, multipliers 126, a selector 127, latches 128, a comparator 129, a code output unit 130, an adder 131 and an exclusive-OR (EX-OR) gate 132. The encoding operation performed by the above-mentioned components will now be described in accordance with the flowcharts of Figs. 5 through 14. When there is a request to begin encoding, the predicted-state memory 115 is cleared to "0" and initialization is performed at step S14, after which an encoding subroutine shown in Fig. 6 is called at step S3. In the encoding subroutine, a feinit subroutine shown in Fig. 7 is called at step S15. At a step S20 of the feinit subroutine in Fig. 7, a register C, a buffer B and a counter SC are cleared to "0", and a register A, a flag STFLG and CT are set to "FFFF", "1" and "11", respectively. The program returns from the subroutine of Fig. 7 to Fig. 6, where the pixel of interest Xn is read out at step S16. Then, in order for encoding to be carried out, a fencode subroutine shown in Fig. 8 is called at step S17. In the fencode subroutine, first the index 1 and the superiority symbol MPS are read out of the predicted-state memory 115 and an arithmetic parameter P (the probability of the inferiority symbol) is decided at step S21. Next, at step S22, the data A in register A is multiplied by the arithmetic parameter P to give A1, and then A1 is subtracted from A to give A0. Then, at step S23, it is determined whether the pixel of interest Xn and the superiority symbol MPS are equal. If they are equal (i.e., if there is agreement with the prediction), then A0 is substituted into the register A at step S24. Next, it is determined at step S25 whether the MSB (most significant bit) of A is "0" or not. If it is "0", then the index 1 is updated at step S26 in accordance with a table NMPS. This is followed by step S27, at which a RENORME subroutine shown in Fig. 10 is called. When processing ends, the program returns from this subroutine. If Xn and MPS are found not to agree at step S23, A0 is added to the data in register C, whereby C is updated, and A1 is substituted into register A at step S28 in Fig. 9. It is determined at step S29 whether the status of a switch corresponding to the index 1 is "1" or not. If the switch status is "1", the superiority symbol MPS is reversed at step S30 and then the index 1 is updated in accordance with table NLPS at step S31. This is followed by step S32, at which the RENORME subroutine shown in Fig. 10 is called and the processing of this subroutine is ended. In the RENORME subroutine of Fig. 10, it is determined at step S33 whether the MSB of register A is "0" or not. If it is "0", the register C is shifted to the left and the counter CT is decremented at step S34. It is then determined at step S35 whether CT is "0" or not. If it is "0", then a BYTEOUT subroutine shown in Fig. 11 is called at step S36. The foregoing processing is repeated and, when the MSB of A becomes "1", the program returns from this subroutine. In the BYTEOUT subroutine of Fig. 11, the 19th to 28th bits of the register C are extracted and stored in a temp register at step S37, and it is determined at step S38 whether temp is "FF"X. If it is greater (i.e., if there is a carry to the 27th bit), the value of a buffer register is incremented and an OUTPUT subroutine shown in Fig. 13 is called at step S39. In the OUTPUT subroutine of Fig. 13, it is determined at step S50 whether a flag STFLG is "1" or not. If it is "1", then STFLG is made "0" at step S51 and the program returns from this subroutine. It should be noted that since the initial value of register C enters only in the initial OUTPUT processing, the above-described processing is for invalidating this. In a case where STFLG is "0" (that is, from the second time onward), one byte of data is externally outputted (to a file or line) at step S52. Following step S51 or S52, the program returns from this subroutine. It is determined at step S40 in Fig. 11 whether the counter SC is positive (> 0). If the answer is YES, then, at step S41, the counter SC is decremented, the above-mentioned OUTPUT subroutine is called and SC-number of "00"X outputs are delivered. When SC becomes "0", the eight lower-order bits of temp are written in the buffer B at step S42. If temp is found to be equal to or less than "FF"X at step S38, "FF"X is checked at step S43 in Fig. 12 and, if temp is equal to "FF"X, then SC is incremented at step S48. However, if temp is less than "FF"X, the OUTPUT subroutine is called and SC-number of "FF"X outputs are delivered (steps S45, S46) through processing similar to that of steps S40, S41 described above. The eight lower-order bits of temp are written in buffer B at step S47, the outputted bits are cleared in register C, and "8" is set in CT at step S49, after which the program returns from this subroutine. By virtue of the foregoing processing, the processing of steps S16, S17 shown in Fig. 6 is repeated until all pixels are processed (step S18). When processing of the final pixel has ended, a feflush subroutine shown in Fig. 14 is called at step S19. In the feflush subroutine of Fig. 14, the final output of a code remaining in the register C is made. First, 16 bits higher-order bits are extracted from the results of the calculation (C+A-1) and stored in temp at step S53, and temp is compared with C at step S54. If the result is that temp is less than C (indicating a carry), "8000"X is added to temp and the result is substituted into C at step S55. If the answer at step S54 is NO, then C is substituted into temp at step S56. Next, C is shifted CT bits to the left at step S57, and it is determined at step S58 whether C is greater than "7FFFFFF"X. If it is greater, then "1" is added to buffer B and the above-described OUTPUT subroutine is called at step S59. Then, at steps S60, S61, SC-number of "00"X outputs are delivered. If C is less than "7FFFFFF", the buffer contents are outputted at step S62, and "FF"X outputs are delivered at steps S60, S61 in the manner set forth above. Finally, the 19th to 11th bits of register C are outputted at step S65, and the program returns from this routine. Thus, encoding is performed by repeating the processing of steps S14, S3 in Fig. 5 until the processing of the last page ends (YES at step S4). Fig. 15 is a block diagram illustrating the construction of a dynamic arithmetic decoder included in the CODEC 107 of Fig. 1. The dynamic arithmetic decoder includes a line memory 120 for holding four lines of decoded results, a predicted-state memory (RAM) 115 for storing an index, which is based upon peripheral-pixel values S 11-0 outputted by the line memory 120, and which indicate the states of these values. Also provided are an initializing unit 113 for clearing the predicted-state memory 115 to "0" by an initialization operation, an arithmetic-parameter ROM 116 which outputs the probability P of an inferiority symbol according to the index 1 outputted by the predicted-status memory 115, an arithmetic decoder 119 for performing arithmetic decoding dynamically using upon the probability P delivered by the arithmetic-parameter ROM 116, the superiority symbol MPS, and a code word CR, and an updating unit 118 for updating the index 1 of the predicted-state memory 115 in accordance with whether the superiority symbol MPS and the code word CR agree or not. Fig. 16 is a block diagram showing the construction of the arithmetic decoder 119 shown in Fig. 15. The arithmetic decoder 119 includes subtractors 125, multipliers 126, selectors 127, latches 128, comparators 129, a code output unit 130, an exclusive-OR (EX-OR) gate 132, and a code input unit. The decoding operation performed by the above-mentioned components will now be described in accordance with the flowcharts of Figs. 17 through 23. When there is a request to begin decoding, the predicted-state memory 115 is cleared to "0" and initialization is performed at step S14, after which a DECODE subroutine shown in Fig. 18 is called at step S5. In the DECODE subroutine, a fdinit subroutine shown in Fig. 19 is called at step S71. At a step S74 of the fdinit subroutine in Fig. 19, 24 bits from the beginning of the code are inputted to the 24 higher-order bits of the register C by a BYTEIN routine shown in Fig. 23, and "FFFF"X is set in the register A at step S74. The program returns to Fig. 18 from this subroutine. A fdecode subroutine shown in Fig. 20 is called at step S72 in Fig. 18. In the fdecode subroutine, first the index 1, the superiority symbol MPS and the arithmetic parameter (the probability of the inferiority symbol) P are read out of the memories 115, 116 at step S75. Next, at step S76, the data A in register A is multiplied by P to give A1, and then A1 is subtracted from A to give A0. Then, at step S77, the eight higher-order bits of C and the value of A0 are compared. If A0 is smaller, a decoded value X'n is decoded as the value of the MPS and the value of A0 is substituted into the register A at step S78. It is them determined at step S79 whether the MSB of the register A is "0". If the MSB is "0", the index 1 is updated in accordance with the table NMPS a RENORMD subroutine illustrated in Fig. 21 is called at step S80. In the RENORMD subroutine of Fig. 21, it is determined at step S82 whether the counter CT is "0". If the answer is YES, the BYTEIN subroutine shown in Fig. 23 is called at step S83. Next, the registers A and C are each shifted to the left and CT is decremented at step S84. The foregoing processing is executed until the MSB of register A becomes "1" at step S85. If the eight higher-order bits of register C are found to be larger than A0 at step S77, then decoding is performed on the assumption that the prediction is erroneous. Therefore, the program proceeds to step S81, at which 1-MPS is substituted into X'n, A0 is subtracted from the eight higher-order bits of the register C, and A1 is substituted into A. Further, in order to update the index 1, a SUP subroutine shown in Fig. 22 is called. In the SUP subroutine of Fig. 22, it is determined at step S86 whether the status of the switch corresponding to the index 1 is "1" or not. If the switch status is "1", the superiority symbol MPS is reversed at step S87 and then the value of the index 1 is updated in accordance with table NLPS at step S88. This is followed by step S89. When normalization processing ends, the program returns from this subroutine, and the program returns to Fig. 18 from the subroutine of Fig. 20. The above-described processing is repeated until the final pixel is decoded (step S73). The program then returns to Fig. 17. Thus, decoding is performed by repeating the processing of steps S14, S5 in Fig. 17 until the processing of the last page ends (YES at step S4). Next, an image transmission apparatus which performs encoding or decoding in conformity with identification information specifying the apparatus, and which maintains the secrecy of the transmitted data, will be described with reference to the related drawings. Fig. 25 is a block diagram illustrating an image transmitting apparatus which employs a dynamic arithmetic encoding method according to this embodiment. The apparatus includes the main CPU 101 which carries out overall control of the other blocks, the operation panel 102 at which the user controls the image transmission apparatus, the program memory 103, such as a ROM, storing programs executed by the main CPU 101, and the user memory 104, such as a RAM, in which data registered by the user, such as numbers for abbreviated dialing, is stored. The apparatus further includes the scanner/printer 105 for reading in or printing out an image, the image processor 106 which executes binarization processing or the like, the CODEC 107 which performs encoding or decoding by means of dynamic arithmetic encoding, an initializing table (ROM) storing various tables for initializing a predicted-state memory included within the CODEC 107, the CCU 109 which controls interfacing with the line, the image memory 110, such as a hard disk or RAM, for memory stored transmission or memory reception, and the line 111, such as a public telephone line or leased line. <First Embodiment> Fig. 26 is a block diagram illustrating the construction of the encoder in a first embodiment. As shown in Fig. 2, the encoder includes the predicting unit 114 for referring to pixels peripheral to a pixel Xn, and a predicted-status memory (RAM) 115 which, based upon peripheral-pixel values S 11-0 outputted by the predicting unit 114, stores an index 1, which indicates the states of these values, and a superiority symbol MPS. Also provided are an initializing unit 113 for initializing the predicted-state memory 115, initializing table ROMs 108 storing a plurality of initialization tables for performing initialization, and an ID switch 112 for setting the ID of the apparatus. Fig. 27 illustrates the specific circuit construction. Further, there are provided the arithmetic-parameter ROM 116 which outputs the probability P of an inferiority symbol according to the index 1 outputted by the predicted-status memory 115, the arithmetic encoder 117 for performing arithmetic encoding dynamically using the probability P delivered by the arithmetic-parameter ROM 116, the superiority symbol MPS, and the value Xn of the pixel of interest, and the updating unit 118 for updating the index 1 of the predicted-state memory 115 in accordance with whether the superiority symbol MPS and the value Xn of the pixel of interest agree or not. The encoding operation performed by the above-mentioned components according to this embodiment will now be described in accordance with the flowchart of Fig. 28. When there is a request to begin encoding, the values of the initializing table selected by an output from the four-bit ID switch 112 are read out at step S1, and the values are written in the predicted-state memory 115 at step S2. This is followed by step S3, at which the ENCODE subroutine of Fig. 6 is called and the above-described encoding of one page is performed. Thereafter, the processing of step S3 is repeated without performing the initialization of the predicted-state memory 115. When the processing of the final page ends at step S4, encoding is terminated. When the encoded data is transmitted to line 111, a cipher identification code is appended to the header, after which the resulting encoded data is transmitted. Fig. 29 is a block diagram showing the decoder according to the first embodiment. The decoder includes the line memory 120 for holding four lines of decoded results, the predicted-state memory 115 for storing an index, which is based upon peripheral-pixel values S 11-0 outputted by the line memory 120, and which indicates the states of these values. Also provided are the initializing unit 113 for initializing the predicted-state memory 115, the initializing table ROMs 108 storing a plurality of initialization tables for performing initialization, and the ID switch 112 for setting the ID of the apparatus. Fig. 27 illustrates the specific circuit construction. Further, there are provided the arithmetic-parameter ROM 116 which outputs the probability P of an inferiority symbol according to the index 1 outputted by the predicted-status memory 115, the arithmetic decoder 119 for performing arithmetic decoding dynamically using the probability P delivered by the arithmetic-parameter ROM 116, the superiority symbol MPS, and the code word CR, and the updating unit 118 for updating the index 1 of the predicted-state memory 115 in accordance with whether the superiority symbol MPS and the code word CR agree or not. The decoding operation performed by the above-mentioned components according to the first embodiment will now be described in accordance with the flowchart of Fig. 30. When it is determined that the header of the received data has the aforementioned cipher identification code appended thereto, the values of the initializing table selected by an output from the four-bit ID switch 112 are read out at step S1, and the values are written in the predicted-state memory 115 at step S2. This is followed by step S3, at which the DECODE subroutine of Fig. 18 is called and the above-described decoding of one page is performed. Thereafter, the processing of step S5 is repeated without performing the initialization of the predicted-state memory 115. When the processing of the final page ends at step S4, decoding is terminated. <Second Embodiment> Fig. 31 is a block diagram showing the encoder according to a second embodiment of the invention. Instead of relying upon the ID switch 112 of the first embodiment, this embodiment employs the user memory 104 from which the ID of the destination of the transmission is read out. Fig. 32 is a flowchart illustrating the operation of encoding according to the second embodiment. When there is a request to begin encoding, the ID of the other party's apparatus registered in advance by the user is read out at step S6, the values of the initializing table selected by the read ID are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. As in the first embodiment, the processing of step S3 is repeated without performing the initialization of the predicted-state memory 115. When the processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. Fig. 33 is a block diagram showing a decoder according to the second embodiment of the invention. Instead of relying upon the ID switch 112 of the first embodiment, this embodiment employs the user memory 104 from which the ID of the transmitting apparatus is read out. Fig. 34 is a flowchart illustrating the operation of decoding according to the second embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the transmitting party's apparatus registered in advance by the user is read out at step S6, the values of the initializing table selected by the read ID are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the first embodiment, the processing of step S5 is repeated without performing the initialization of the predicted-state memory 115. When the processing of the final page ends at step S4, decoding is terminated. <Third Embodiment> Fig. 35 is a block diagram showing the encoder according to a third embodiment of the invention. In the first embodiment, the initialization of the predicted-state memory 115 is performed by TS (a transformation-start signal). In this embodiment, on the other hand, the initialization of the predicted-state memory 115 is performed by PS (a page-start signal). Fig. 36 is a flowchart illustrating the operation of encoding according to the third embodiment. When there is a request to begin encoding, the values of the initializing table selected by an output from the four-bit ID switch 112 are read out at step S1, and the values are written in the predicted-state memory 115 at step S2. This is followed by step S3, at which the ENCODE subroutine of Fig. 6 is called and the encoding of one page is performed. Thereafter, the processing of steps S1 through S3 is repeated. When the processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the resulting encoded data is transmitted. Fig. 37 is a block diagram showing a decoder according to the third embodiment of the invention. In the first embodiment, the initialization of the predicted-state memory 115 is performed by TS. In this embodiment, on the other hand, the initialization of the predicted-state memory 115 is performed by PS. Fig. 38 is a flowchart illustrating the operation of decoding according to the third embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the values of the initializing table selected by the output of the ID switch 112 are read out at step S1, and the values are written in the predicted-state memory 115 at step S2. Next, the DECODE subroutine shown in Fig. 18 is called and the decoding of one page is performed at step S5. Thereafter, the processing of steps S1, S2 and S5 is repeated. When the processing of the final page ends at step S4, decoding is terminated. <Fourth Embodiment> Fig. 39 is a block diagram showing the encoder according to a fourth embodiment of the invention. Instead of relying upon the ID switch 112 of the third embodiment, this embodiment employs the user memory 104 from which the ID of the destination of the transmission is read out. Fig. 40 is a flowchart illustrating the operation of encoding according to the fourth embodiment. When there is a request to begin encoding, the ID of the other party's apparatus registered in advance by the user is read out at step S6, the values of the initializing table selected by the read ID are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the third embodiment, the processing of steps S6, S7, S2 and S3 is repeated. When the processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. Fig. 41 is a block diagram showing a decoder according to the fourth embodiment of the invention. As in the encoder described above, the ID of the transmitting party's apparatus is read out of the user memory 104 rather than from the ID switch 112. Fig. 42 is a flowchart illustrating the operation of decoding according to the fourth embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the transmitting party's apparatus registered in advance by the user is read out at step S6, the values of the initializing table selected by the read ID are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the third embodiment, the processing of steps S6, S7, S2, S5 is repeated. When the processing of the final page ends at step S4, decoding is terminated. <Fifth Embodiment> Fig. 43 is a block diagram of the encoder according to a fifth embodiment of the invention. In the third embodiment described above, each page is initialized by the same table. In this embodiment, on the other hand, the arrangement is such that the ID is changed hypothetically by a counter every page. Fig. 44 is a flowchart showing the operation of encoding according to the fifth embodiment. When there is a request to begin encoding, the value from the ID switch is read out at step S8, the values of the initializing table based upon this value are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. This is followed by step S3, at which the ENCODE subroutine of Fig. 6 is called and the encoding of one page is performed. If the page is not the last page, the value of the ID is counted up hypothetically at step S9 by the counter 121. Steps S7, S2, S3 and S9 are repeated, as in the aforementioned manner. When the processing of the last page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the resulting encoded data is transmitted. Fig. 45 is a block diagram of a decoder according to a fifth embodiment of the invention. As in the manner of the above-described encoder, the ID is changed hypothetically by a counter every page. Fig. 46 is a flowchart showing the operation of decoding according to the fifth embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the value from the ID switch 112 is read out at step S9, the values of the initializing table based upon this value are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. Thereafter, steps S7, S2, S5 and S9 are repeated as in the aforementioned manner. When the processing of the last page ends at step S4, decoding is terminated. <Sixth Embodiment> Fig. 47 is a block diagram showing the encoder according to a sixth embodiment of the invention. Instead of relying upon the ID switch 112 of the fifth embodiment, this embodiment employs the user memory 104 from which the ID of the destination of the transmission is read out. Fig. 48 is a flowchart illustrating the operation of encoding according to the sixth embodiment. When there is a request to begin encoding, the ID of the other party's apparatus registered in advance by the user is read out at step S6, the values of the initializing table selected by the read ID are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the fifth embodiment, the processing of steps S7, S2, S3 and S9 is repeated. When the processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. Fig. 49 is a block diagram showing a decoder according to the sixth embodiment of the invention. Instead of relying upon the ID switch 112, this embodiment employs the user memory 104 from which the ID of the destination of the transmission is read out, as in the manner of the encoder described above. Fig. 50 is a flowchart illustrating the operation of decoding according to the sixth embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the transmitting party's apparatus registered in advance by the user is read out at step S6, the values of the initializing table selected by the read ID are read out at step S7, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the fifth embodiment, the processing of steps S7, S2, S5, S9 is repeated. When the processing of the final page ends at step S4, decoding is terminated. <Seventh Embodiment> Fig. 51 is a block diagram of the encoder according to a seventh embodiment of the present invention. In the fifth embodiment described above, the ID is changed by a counter page by page. In this embodiment, on the other hand, the arrangement is such that the initializing table 108 is changed by the values of a random-number sequence. Fig. 52 is a flowchart illustrating the encoding operation according to the seventh embodiment. When there is a request to begin encoding, the value of the ID switch 112 is read out at step S8 and a random-number sequence is generated at step S10 with this value serving as the source. The values of the initializing table based upon the random number are read out at step S11, and the values are written in the predicted-state memory 115 at step S2. Next, the ENCODE subroutine shown in Fig. 6 is called and the encoding of one page is performed at step S3. If the page is not the last page, the next random number is read out at step S12 in order to update the value of the random number. The processing of steps S11, S2, S3 and S12 is repeated as in the aforementioned manner. When the processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. Fig. 53 is a block diagram of a decoder according to a seventh embodiment of the present invention. In the seventh embodiment described above, the value of the random number is updated and changed every page, as in the manner of the above-described encoder. Fig. 54 is a flowchart illustrating the decoding operation according to the seventh embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the value from the ID switch 112 is read out at step S8 and a random-number sequence is generated at step S10 with this value serving as the source. The values of the initializing table based upon this random number value are read out at step S11, and the values are written in the predicted-state memory 115 at step S2. Next, the DECODE subroutine shown in Fig. 18 is called and the decoding of one page is performed at step S5. Thereafter, the processing of steps S11, S2, S5 and S12 is repeated. When the processing of the final page ends at step S4, decoding is terminated. <Eighth Embodiment> Fig. 55 is a block diagram showing the encoder according to an eighth embodiment of the invention. Instead of relying upon the ID switch 112 of the seventh embodiment, this embodiment employs the user memory 104 from which the ID of the destination of the transmission is read out. Fig. 56 is a flowchart illustrating the operation of encoding according to the eighth embodiment. When there is a request to begin encoding, the ID of the other party's apparatus registered in advance by the user is read out at step S6 and a random-number sequence is generated at step S10 with the ID serving as the source. The values of the initializing table based upon the random number are read out at step S11, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the seventh embodiment, the processing of steps S11, S2, S3 and S12 is repeated. When the processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. Fig. 57 is a block diagram showing a decoder according to the eighth embodiment of the invention. Instead of relying upon the ID switch 112, this embodiment employs the user memory 104 from which the ID of the destination of the transmission is read out, as in the manner of the encoder described above. Fig. 58 is a flowchart illustrating the operation of decoding according to the eighth embodiment. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the transmitting party's apparatus registered in advance by the user is read out at step S6 and a random-number sequence is generated at step S10 with this ID serving as the source. The values of the initializing table based upon the random number are read out at step S11, and the values are written in the predicted-state memory 115 at step S2. Thereafter, as in the seventh embodiment, the processing of steps S11, S2, S5, S12 is repeated. When the processing of the final page ends at step S4, decoding is terminated. Thus, in accordance with the embodiments described above, an image transmission apparatus for transmitting and receiving images using dynamic arithmetic encoding is provided with a plurality of initializing tables, and one of these tables is selected based upon an ID registered in advance. On the transmitting side, a predicted-state memory within the encoder is initialized at the beginning of communication or at the beginning of each page and, after enciphered encoding is carried out, a signal to the effect that enciphered encoding has been performed is appended, after which the transmission is made. On the receiving side, it is determined whether the signal indicative of enciphering has been appended. If the signal is identified, then, in a manner similar to that on the transmitting side, a predicted-state memory within a decoder is initialized by an initializing table selected based upon the ID, and decoding is carried out. If the IDs of the transmitting and receiving sides do not agree, received image data can no longer be decoded correctly, and therefore the confidentiality of the contents of the communication can be maintained. <Other Embodiments> Other embodiments of the present invention will now be described with reference to the related drawings. In the second, fourth, sixth and eighth embodiments, the ID of the other party's apparatus is read out of the user memory 104 instead of the ID switch 112. A case in which the ID of the apparatus is read will now be described as another embodiment of the invention. The operation of encoding corresponding to the second embodiment will now be described in accordance with the flowchart shown in Fig. 59. When there is a request to begin encoding, the four-bit ID of the apparatus set by the user at the time of registration is read out at step S13, the values of the initializing table selected by this ID are read out at step S7, and these values are written in the predicted-state memory 115 at step S2. Thereafter, as in the second embodiment, the processing of step S3 is repeated without initializing the predicted-state memory 115. When processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. The operation of decoding corresponding to the second embodiment will now be described in accordance with the flowchart of Fig 60. When it is determined that the header of the received data has the cipher identification code appended thereto, the four-bit ID of the apparatus set by the user at the time of registration is read out at step S13, the values of the initializing table selected by this ID are read out at step S7, and these values are written in the predicted-state memory 115 at step S2. Thereafter, as in the second embodiment, the processing of step S5 is repeated without initializing the predicted-state memory 115. When processing of the final page ends at step S4, decoding is terminated. The operation of encoding corresponding to the fourth embodiment will now be described in accordance with the flowchart shown in Fig. 61. When there is a request to begin encoding, the ID of the apparatus set by the user at the time of registration is read out at step S13, the values of the initializing table selected by this ID are read out at step S7, and these values are written in the predicted-state memory 115 at step S2. Thereafter, as in the fourth embodiment, the processing of steps S13, S7, S2 and S3 is repeated. When processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. The operation of decoding corresponding to the fourth embodiment will now be described in accordance with the flowchart of Fig 62. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the apparatus set by the user at the time of registration is read out at step S13, the values of the initializing table selected by this ID are read out at step S7, and these values are written in the predicted-state memory 115 at step S2. Thereafter, as in the fourth embodiment, the processing of steps S13, S7, S2, S5 is repeated. When processing of the final page ends at step S4, decoding is terminated. The operation of encoding corresponding to the sixth embodiment will now be described in accordance with the flowchart shown in Fig. 63. When there is a request to begin encoding, the ID of the apparatus set by the user at the time of registration is read out at step S13, the values of the initializing table selected by this ID are read out at step S7, and these values are written in the predicted-state memory 115 at step S2. Thereafter, as in the sixth embodiment, the processing of steps S7, S2, S3 and S9 is repeated. When processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. The operation of decoding corresponding to the sixth embodiment will now be described in accordance with the flowchart of Fig 64. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the apparatus set by the user at the time of registration is read out at step S13, the values of the initializing table selected by this ID are read out at step S7, and these values are written in the predicted-state memory 115 at step S2. Thereafter, as in the sixth embodiment, the processing of steps S7, S2, S5, S9 is repeated. When processing of the final page ends at step S4, decoding is terminated. The operation of encoding corresponding to the eighth embodiment will now be described in accordance with the flowchart shown in Fig. 65. When there is a request to begin encoding, the ID of the apparatus set by the user at the time of registration is read out at step S13 and a random-number sequence is generated at step S10. Thereafter, as in the eighth embodiment, the processing of steps S11, S2, S3 and S12 is repeated. When processing of the final page ends at step S4, encoding is terminated. At the time of transmission, a cipher identification code is appended to the header, after which the encoded data is transmitted. The operation of decoding corresponding to the eighth embodiment will now be described in accordance with the flowchart of Fig 66. When it is determined that the header of the received data has the cipher identification code appended thereto, the ID of the apparatus set by the user at the time of registration is read out at step S13 and a random-number sequence is generated at step S10 with this ID serving as the source. Thereafter, as in the eighth embodiment, the processing of steps S11, S2, S5, S12 is repeated. When processing of the final page ends at step S4, decoding is terminated. Though ROMs and RAMs are mentioned as the memories in the embodiments, this does not impose a limitation upon the invention. For example, a RAM or a hard disk may be used in place of a ROM. Further, though the ID in the embodiments is a four-bit numerical value, this does not impose a limitation upon the invention. For example, the ID may be a numerical value of another number of bits or a character. Thus, in accordance with the embodiments described above, the confidentiality of transmitted data can be maintained by encoding or decoding the data in dependence upon identification apparatus specifying the apparatus. As many apparently widely different embodiments of the present invention can be made without departing from the scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: An image transmission apparatus comprising: compression encoding means (107, 117) for compressing input image data by a compression process to reduce an amount of data to be transmitted; and characterised by initialising means (113) for setting a parameter of said compression process on the basis of identification information (ID) which specifies an apparatus said identification information (ID) being known also to a specific decoding apparatus, such that said compression encoding means also effects encrypting so as to improve the confidentiality of the data, by compressing using said parameter. The apparatus according to claim 1, wherein information which indicates 'that the image data is encoded based upon the parameter initialised in dependence upon the identification information is appended to the encoded data for transmission. The apparatus according to claim 1 or 2, wherein said initialising means includes: memory means (108) for storing a plurality of initialising tables selected in dependence upon the identification information; and selecting means (112) for selecting an initialising table stored by said memory means; wherein a predicted-state memory for encoding is initialised by the initialising table selected by said selecting means. The apparatus according to claim 3, wherein initialising of said predicted-state memory is carried out at the beginning of one communication. The apparatus according to claim 3 or 4, wherein initialisation of said predicted-state memory is carried out every page. The apparatus according to claim 5, wherein said selecting means selects an initialising table every page based upon the identification information. The apparatus according to claim 6, wherein said selecting means selects an initialising table in accordance with identification information changed by a counter every page. The apparatus according to claim 6, wherein said selecting means selects an initialising table in accordance with a random number generated based upon the identification information. An image transmission method comprising: compressing (S3) input image data by a compression process to reduce an amount of data to be transmitted; and characterised by initially setting (S1) a parameter of said compression process on the basis of identification information which specifies an apparatus said identification information (ID) being known also to a specific decoding apparatus, such that said compression process using said parameter also effects encrypting so as to improve the confidentiality of the data. The method according to claim 9, further comprising appending to the compressed image data information which indicates that the image data is encoded based upon the parameter initialised in dependence upon the identification information. The method according to claim 9 or 10, wherein said setting step includes selecting one of a plurality of initialising tables in dependence upon the identification information, and initialising a predicted-state memory for encoding by the initialising table selected. An image receiving apparatus comprising: decoding means (107, 119) for decoding compressed received image data by a decompression process; and characterised by initialising means (113) for setting a parameter of said decompression process on the basis of identification information (ID) which specifies an apparatus said identification information (ID) being known also to a specific encoding apparatus, such that said decompression process effects decoding and decryption of the received data, thereby improving the confidentiality of the data. The apparatus according to claim 12, wherein said initialising means includes: memory means (108) for storing a plurality of initialising tables selected in dependence upon the identification information; and selecting means for selecting an initialising table stored by said memory means; wherein a predicted-state memory (115) for encoding is initialised by the initialising table selected by said selecting means. The apparatus according to claim 13, wherein initialisation of said predicted-state memory is carried out at the beginning of one communication. The apparatus according to claim 13, wherein initialisation of said predicted-state memory is carried out every page. The apparatus according to claim 15, wherein said selecting means selects an initialising table every page based upon the identification information. The apparatus according to claim 16, wherein said selecting means selects an initialising table in accordance with identification information changed by a counter every page. The apparatus according to claim 16, wherein said selecting means selects an initialising table in accordance with a random number generated based upon the identification information. An image receiving method comprising: decoding (S5) compressed received image data by a decompression process; and characterised by initially setting (S1) a parameter of said decompression process on the basis of identification information which specifies an apparatus said identification information (ID) being known also to a specific encoding apparatus, such that said decompression process effects decoding and decryption of the received data, thereby improving the confidentiality of the data. The method according to claim 19, wherein said setting step includes selecting one of a plurality of initialising tables in dependence upon the identification information, and initialising a predicted-state memory for decoding by the initialising table selected. A facsimile communication apparatus (101-110), comprising a transmission apparatus according to any of claims 1 to 8 and a receiving apparatus according to any of claims 12 to 18.

Inventors: NAKANISHI HIROYUKI, NAKANISHI, HIROYUKI, NAKANISHI, HIROYUKI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N1
IPC codes: H03M7, G06T9, H04N1, H04K1, H04L9