Transistor spacer structure

Abstract: A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate (16) is formed over a portion of a substrate. A dielectric layer (18) is formed over the integrated circuit and an oxide layer (22) is formed over the dielectric layer (18). The oxide layer is patterned and etched to form sidewall oxide spacers (24) on each side of the gate (16) and over a portion of the dielectric layer (18). The dielectric layer (18) not covered by the sidewall oxide spacers (24) is then removed.

Description: The present invention relates generally to semiconductor integrated circuits, and more specifically to a transistor spacer endpoint structure. In MOS technology, the gate of a transistor is the part of the device that controls the operation of the device. The formation of the gate has thus been of prime importance in maintaining the integrity and performance of the device. The typical gate of the transistor is formed from a doped polysilicon layer overlying a gate oxide layer. Lightly doped drain (LDD) regions are formed by implanting a dopant into the substrate adjacent to the gate. The implantation forms lightly doped, very shallow source/drain regions. A low temperature oxide (LTO) is formed over the surface of the wafer and anisotropically etched away. The oxide on the sidewalls of the polysilicon and gate oxide remains after this etch step to form sidewall spacers. More heavily doped source/drain regions are implanted into the substrate adjacent to the edge of the sidewall spacers. The gate does not overlap the more heavily doped source/drain regions. The uniformity of the etched LTO to form the sidewall spacers is critical to the transistor performance for devices in the submicron feature sizes. Etching of the LTO must be carefully controlled to achieve a precise endpoint. Overetching of the LTO is a standard technique to insure complete removal of the oxide over the heavily implanted source/drain regions. This overetching technique of the LTO, however, creates problems. Thicker field oxide regions which separate the active areas must be initially grown. As the LTO is etched to form the sidewall spacers, a portion of the field oxide is also etched away. Initially, forming thicker field oxide regions, however, forms longer birds beaks and causes greater physical stress to the substrate from the larger volume of field oxide. The additional stress leads to lattice strain and defects in the substrate. Additionally, variations of the overetch process can change the drive current of the transistor, thus directly impacting transistor performance. One way to insure that device performance is maintained after overetching the LTO to form sidewall oxide spacers is to form a layer between the LTO and the field oxide region. Placing a spacer etch stop under the LTO which forms the spacers will prevent overetching the field oxide region and control the precise etch endpoint. It would therefore be desirable to provide a method which produces a reliable transistor having the desired sidewall oxide spacer structure using an etch stop layer under the spacer oxide layer. It would further be desirable for such technique to be easily adapted for use with standard integrated circuit fabrication process flows without increasing the complexity of the process. IBM Technical Disclosure Bulletin, Vol. 24, No 2, July 1981, pages 1293-1295 discloses a portion of a semiconductor integrated circuit comprising a substrate, a gate dielectric layer over a portion of the substrate and a gate electrode formed from a conductive material over the gate dielectric layer. A metal oxide layer is disposed over the sides of the gate electrode and over a portion of the substrate adjacent to the gate electrode, but spaced from the gate electrode and the substrate via a silicon dioxide layer. Sidewall oxide spacers are disposed on the metal oxide layer. This document is used to form the preamble of the appended claim 1. IEEE "Electron Device Letters", Vol. 10 November 1989, No 11, pages 487-489 discloses a substrate, a gate dielectric layer over a portion of the substrate and a gate electrode formed from a conductive material over the gate dielectric layer. A silicon nitride layer is disposed on the sides of the gate electrode and a portion of the substrate adjacent to the gate electrode, the silicon nitride layer being spaced from the gate electrode and substrate via a thermal oxide layer. Sidewall oxide spacers are disposed on the silicon nitride layer. According to the present invention there is provided a structure consisting of a portion of a semiconductor integrated circuit, comprising a substrate, a gate oxide layer over a portion of the substrate, a gate electrode, formed from a conductive material, over the gate oxide layer; a metal oxide layer over the sides of the gate electrode and over a portion of the substrate adjacent to the gate electrode and sidewall oxide spacers on the metal oxide layer adjacent to the sidewalls of the gate electrode, characterised in that the metal oxide layer is on the sides of the gate electrode whereby the metal oxide layer is in direct contact with the conductive material forming the gate electrode. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. Referring to Figure 1, an integrated circuit is to be formed on a silicon substrate 10. A field oxide region 12 is generally made in an area on the substrate as known in the art to separate active areas. A transistor gate is formed over a portion of the substrate 10. The gate electrode 16, preferably a doped polysilicon, is formed over a gate oxide 14 as known in the art. A dielectric layer 18 is deposited over the integrated circuit as known in the art to a depth of between approximately 5 to 200 nm (50 to 2000 angstroms). Layer 18 is a metal oxide layer such as aluminum oxide, titanium oxide or tantalum oxide. Layer 18, however, may be any dielectric which can be selectively etched over oxide. Lightly doped drain (LDD) regions 20 may be formed in the substrate adjacent to the gate 16 either before or after the dielectric layer 18 is formed. The LDD regions 20 are formed by implanting a dopant such as phosphorus for N-type regions. This implant forms lightly doped, very shallow source/drain regions. An oxide layer 22 is next formed over the dielectric layer 18 as known in the art. Referring to Figure 2, oxide layer 22 is patterned and etched to form sidewall oxide spacers 24 adjacent to the sides of the gate 16 and on top of a portion of the dielectric layer 18. The oxide layer 22 is selectively etched, typically by a plasma etch, using the dielectric layer 18 as an etch stop. The dielectric layer will prevent any overetching, required to remove all of the oxide from the area where the LDD implant is made, from attacking the field oxide region. Thus, a thicker field oxide region is not required at the beginning of the process to accommodate a loss of a portion of the field oxide during overetch of the spacer oxide. Transistor performance can be maintained because the overetch will not attack the field oxide or the silicon substrate where the implants are made. Referring to Figure 3, The dielectric layer 18 is removed by a wet or dry etch process as known in the art. The dielectric is selectively etched to prevent any loss of the oxide sidewall spacers 24. A second implant is performed either before or after the dielectric layer is removed to form source/drain regions 26. This implant is a large dose of dopant such as arsenic or antimony forming N + regions adjacent to the sidewall oxide spacers 24. The sidewall oxide spacers act as a mask to insure that the heavy second implant only reaches the edges of the oxide spacers. As will be appreciated by those skilled in the art, p-channel transistors can also be made by the above described process. As will be appreciated by those skilled in the art, the process steps described above can be used with nearly any conventional process flow.

Claims: A structure consisting of a portion of a semiconductor integrated circuit, comprising: a substrate (10); a gate oxide layer (14) over a portion of the substrate; a gate electrode (16), formed from a conductive material, over the gate oxide layer (14); a metal oxide layer (18) over the sides of the gate electrode and over a portion (20) of the substrate adjacent to the gate electrode; and sidewall oxide spacers (24) on the metal oxide layer (18) adjacent to the sidewalls of the gate electrode (16), characterised in that the metal oxide layer (18) is on the sides of the gate electrode (16) whereby the metal oxide layer (18) is in direct contact with the conductive material (16) forming the gate electrode. The structure of claim 1, wherein the metal oxide layer (18) comprises aluminum oxide. The structure of claim 1, wherein the metal oxide layer (18) comprises titanium oxide. The structure of claim 1, wherein the metal oxide layer (18) comprises tantalum oxide. The structure of any preceding claim, wherein the metal oxide layer (18) is in direct contact with the substrate in the portion (20) adjacent the gate electrode.

Inventors: BRYANT FRANK RANDOLPH, CHEN FUSEN E, DIXIT GIRISH ANANT, BRYANT, FRANK RANDOLPH, CHEN, FUSEN E., DIXIT, GIRISH ANANT
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS, INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L29