QUASI RADIX-16 PROCESSOR AND METHOD

Abstract: A Quasi Radix-16 Butterfly comprises a radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.

Description: ΌESCRIPTION QUASI RADIX-16 PROCESSOR AND METHOD Background of the Invention 1. Field of the Invention The present invention relates to a LSI butterfl processor and method for high performance Fast Fourier Transform (FFT) processors. 2. Description of Related Art With the present state of the art in VLSI technology, the speed of VLSI computing structures is typically limited by the data bandwidth of a VLSI array processor and not by silicon circuits. The data bandwidth directly related to the number of input and output (I/O) pins. The level of integration has reached a point where, due to limited I/O bandwidth, it is not possible to achiev 100% execution hardware utilization without increasing the number of I/O pins significantly. In such a situation, th design of VLSI processors should aim for minimization of t undesirable effects of limited I/O bandwidth while preserv the tremendous advantages of large computation arrays. Early integrated FFT processors were based on a radix-2 "butterfly" as illustrated in Figure la, to keep t amount of hardware required on a single chip to a minimum. "butterfly" is a set of arithmetic operations commonly use in digital signal processing. Recently, due to a vancinα technology, several radix-4 butterfly-based processors ha been disclosed. These processors are a logical evolutiona advance from racix-2 processors that takes advantage of a higher level of integration and thus more silicon area. E radix-4 butterfly requires four data inputs, three 'twiddl inputs (i.e. angular velocity information), and four date outputs, as shown in Figure lb. A typical multi-cycle radix-4 butterfly processor includes one complex data inpu port, one complex twiddle port and one complex data output port, where each port can be 32 to 48 bits wide in such fi point processors. Thus, for a radix-4 butterfly processor there is already a large number of I/O pins. Also, it is difficult to conceive of a radix-8 butterfly processor because there is a tremendous increase in the amount of hardware required for a radix-8 butterfly processor as compared with a- radix-4 butterfly processor. The term "butterfly" processor is used herein to conveniently designate the circuit module, described in detail later herein, which includes a plurality of fan-in inputs and a plurality of fan-out outputs in the schematic representatio It is desirable to compute Fast Fourier transform (FFTs) using as high a radix as possible to alleviate the I bandwidth problem in VLSI FFT processors. The use of highe radices is even more desirable for FFT processors designed handle exceptionally large FFT sizes e.g., 15 million data-point FFT. The I/O bandwidth problem in high performance FFT processors is illustrated in the tirr.inc diagrams of Figures 2a and 2b. Let Tio be the I/O cycle time and Teu be the execution unit pipeline cycle time. a dual radix-2 butterfly, four I/O cycles are performed t fetch the data (Al, Bl, A2, B2), as shown in Figure 2a. datapath then performs two butterfly operations (1,2) on fetched data in two cycles. If Tio is equal to Teu then datapath cannot be kept busy continuously and is I/O boun indicated by the blank cycles in the datapath timing wave of Figure 2a. As indicated in Figure 2a, to make the datapath execution bound, 4xTio ■= 2xTeu i.e., the I/O cyc time should have to be one-half the execution pipeline cy time. Figure 2b illustrates the same situation for s rad butterfly. Here again four I/O cycles are required to fe the data for a single radix-4 butterfly. If it is assume that the datapath can execute a radix-4 butterfly every t cycles, then once again Tio would have to be (1/2) Teu to make the datapath execution bound. This then is the I/O bandwidth problem in high performance pipelined FFT processors with a limited number of I/O ports, specificall three complex ports (namely, an input port, a twiddle port and an output port as indicated in Figure 2). Summary of the Invention In accordance with the illustrated embodiment of the present invention, racix-lS butterfly hardware is implemented using a multi-cycle radix-4 butterfIv-besed circui-t module that uses relatively fewer I/O pins and vet relieves the I/O bandwidth problem to achieve significant higher throughput compared with a conventional raαιx-4 butterfly implementation. This invention, henceforth referred to as the Quasi Radix-16 (QR16) butterfly process includes a radix-4 butterfly processor and on-board memory with some minor external memory addressing changes from a conventional radix-4 butterfly processor. The QR16 perfor a quasi radix-16 butterfly in two columns of four redix-4 butterfly operations as illustrated in Figure lc . On-chip cache memory is included to store data outputs of the firs column of radix-4 butterflies for use as data inputs in th radix-4 butterfly operations of the second column to implement high-speed processing that is maximally execution-bound, as illustrated in Figure 2c. Brief Description of the Drawings Figure la is a simplified diagram of a convention radix-2 butterfly operation; Figure lb is a simplified diagram of a convention radix-4 butterfly operation; Figure lc is a simplified diagram of one embodime of a quasi radix-15 butterfly operation according to the present invention; Figures 2a-c are timing diagrams for the associat radix-n butterfly processors that illustrate input/cutout bandwidth and execution limitations; Figure 3a is a simplified schematic diagram of preferred embodiment of the quasi radix-16 butterfly hard implementation according to the present invention; Figure 3b is a simplified chart illustrating da flow in a quasi radix-16 butterfly processor according to present invention; Figures 4a and 4b are pictorial representations the processing sequences for a conventional radix-4 proce and the quasi radix-16 processor of the present invention - Figure 5 is a timing diagram illustrating the impact of data dependencies in a datapath on the processi speed attributable to the quasi radix-15 processor of the present invention; Figure 6 is a chart illustrating the data processing for maximum execution utilization of a quasi radix-16 processor according to the present invention; Figure 7a is a simplified diagram illustrating deta flow through an interleaved quasi-radix-16 scheme as illustrated in Figure 7b, according to the present invent Figure 7b is a simplified schematic diagram illustrating an interleaved quasi radix-16 butterfly operation with multiple twiddle inputs for operation as illustrated in Figure 4b according to the present inventi Figure 7c is a chart illustrating the address orientations of twiddle inputs within on-chip memory in hexadecimal notation; Figure 8 is a simplified diagram for performing N-point Fest Fourier Transform with a quasi radix-16 butterfly of the present invention illustrating the generi notation; Figure 9 is a block schematic diagram of the preferred embodiment of the circuit module radix-4 process for operation in the quasi radix-16 processor according to the present invention; Figure 10 is a schematic diagram of the memory a addressing circuitry essocieted with the quesi-radix 15 processo ; Figures lie and lib are charts illustrating the input memory storage scheme for data inputs; Figures 12a-c are charts illustrating the coefficient memory storage scheme for twiddle input data; Figures 13a and 13b are " charts illustrating the cache memory storage scheme; and Figures I4a-c are cherts illustrating the output data memory scheme. Description of the Preferred Embodiment In general, a Fourier transform of data points representing a complex function includes an ascending serie c ~erms, each including a coefficient and an angular velocirv (or ecuencv) acto τ* where each * "eτ?_ o~ * -»ι— complex function av include real and imaoinarv Quantities, -s - r -r D 0 ÷ D-i X W χ ÷ D 2 x V. 2 ÷ D 3 x W 3 (Ξ Thus, the higher-order terms of the complex function, in general case, require four multiplications of the real a imaginary components per term, where D p is data and n i "twiddle" input such that D n = a÷jb ( W n = c÷jd ( D n x W n = (a÷jb) (c÷j ) = axe ÷ axjd ÷ cxjb ÷ jbxj (E Radix-4 processing performs four multiplications per ter twelve multiplications for these higher-order terms D- j _ x through D 3 x 3 . The data inputs D n and the twiddle inp W p are supplied at separate inputs for processing in sel sequence, as later described herein. Referring now to Figure lc, there is shown the quasi radix-15 butterfly which includes two columns of f radix-4 butterflies each (A to D and E to H) , as shown i Figure lc. The QRI5 processor uses on-chip cache memory, later described herein, to store the 16 data outputs of first column butterfly operations, for use in the second column butterfly operations. Figures 3a, 9 and 10 illus the hardware implementation of QR16 processor around a radix-4 butterfly execution unit. As can be seen from t figures, the QR16 processor is implemented by adding a limited amount of on-boerd memory S, 11, 13, 15 to a radi butterfiv processor chip. 8 Each QRlδ butterfly requires 15 input dare pcinrs (D0-DI5) and 15 twiddle factors (wl-wl5) as shown in Figure lc, which takes 15 fetch cycles with 2 complex data input ports i.e., input data and twiddle inputs. Internally, eig 5 radix-4 butterfly operations (A to H in Figure lc) are required. The first column uses the same data ordering as 15-point radix-4 fast-Fourier transform (FFT) and all butterflies (A to D) have three common twiddles i.e., wl, w and w3. The second column of butterflies E through H requi 10 digit reversed data ordering and 12 unique twiddles i.e., to w!5. Without the QR15 butterfly, a 15 point radix-4 FFT would required 32 (2x16) data inputs, 24 (2x12) twiddle inputs, end 32 (2x16) date outputs, since the first column results would have to be stored in off-chip memory and be 5 brought in again on-chip to complete the second column. With the QR15 butterfly scheme of the present invention, it is possible to achieve as much as twice the throughput of a conventional radix-4 butterfly based processor. The higher throughput is achieved by maximizing 0 the utilization of the datapath, as shown in Figure 2c. It should be noted in Figure 2c that each data fetch and cutout store e.g., Al* and Al*' respectively, actually takes four input/output (I/O) cycles. The 15 data points (Al *-* , 31', Cl and DI" *" ! brought on-chio are passed twice thrc c rhe -, r Psass 1-1 and Pass 1-2) before being stored ir. Thus, for QR15 processor cf the preser.r i - 7ι η ι ς D " n; " r- .--. T=-:■ 7. — 1 ~ - '—. ____. datapath is continuously busy, thus indicating en ideal I balanced environment. Referring now to Figure 4, the chart illustrate the difference between a radix-4 butterfly sequence and a QR16 butterfly sequence for IK data points of a fast-Four transform. Figure 4a shows the sequence of butterfly operations for a IK point FFT using only radix-4 butterflies. Each shaded rectangle in Figure 4 represent one radix 4 butterfly operation. All the butterflies of single column are processed before the next column of butterflies are processed. Thus, a IK point FFT can be performed in five columns by five radix-4 passes (1024 = 4x4x4x4x4) as shown in Figure 4a. In contrast, a IK poin FFT can be performed in three columns by two QRlδ butterf passes end one radix-4 pass (1024 = 16x16x4) as. shown in Figure 4b. In Figure 4b, the QR16 butterfly is shown as dashed line enclosing 8 radix-4 butterflies arranged in 2 columns. In Figure 4b, processing also proceeds column b column except only three columns are needed because of th higher radix used in the first two columns. The QRlδ butterfly essentially allows two radix-4 columns to be processed at a time before the next stage. The QR16 processor advantageously includes on chip cache memory 15 storing real and imaginary data needed for processing the radix-4 columns in the QRI5 butterfly. The present invention advantageously uses on chip memory to rearrange radix-4 butterflies to exploit data localit y to increase speed of computation. In addition to cache memory, input ana output memories are included, as shown in Figure 3a. QR16 embodiment of the present invention includes an inher 'pipeline' latency problem, when implemented on a pipeline radix-4 datapath. In accordance with this invention, this latency can be eliminated by interleaving the QRlδ computations of two 16-point data blocks in the pipelined datapath, as later described herein. Table 1, below, illustrates the increases in processing speed that are achieved using the QR15 of the present invention, especial when operated in radix-15 mode only. Table 1 Assuming: Tio = Ten = 20ns The Ouasi-raάix 15 Butterfl y Implementation Referring now to Figure 3a and 10, in order to implement QR15 using a radix-4 module 7, a limited amount c on-board memory has to be included with this module on the seme circuit chip. Memory structures 3, 11, 13 are placed tne mpuc ana output or t cacepatn. _n memory 15 is also required. For complex d or width should allow for real and ima arv Geι_ Ϊ compo nts OU' J I _ Ϊ — mo r ies x 17 - ~~ . - ~ ~ =e. s ' for data buffering while the cache memory 15 is used to store the intermediate results of column 1 of the QRI5 butterfly processing, as illustrated in Figure lc. Figur shows the basic data flow through the memories and the datapath. A more detailed version will be discussed late herein. Input data points are stored in the input memory and the twiddles are stored in the coefficient memory 9. Then, the datapath operates on this data to accomplish th first column of QRlδ butterfly processing. The results o the first column butterflies are stored in the cache memo 15 and once all the butterflies of column 1 are complete, cache memory 15 is read to perform the second column butterflies. The final results of the second column of a QR16 butterfly are stored in the output memory 13 for transfer to off-chip memory. Typically, multiple stage pipelined data paths used to implement high performance FFT processors, e.g., pipeline stage for the multiplier section, a pipeline sta for the adder section, a pipeline stage for the ALU secti and the like. In the QR16 butterfly of the present invention, there exists a data dependency between the fir column and the second column of butterfly processing. Th results of all first column butterflies must be available before ' the second column calculations can begin, i.e. , -wi reference to Figure lc, the results of butterfly D must b stored in the cache memory 15 prior to the execution of butterfly Ξ. This data dependency becomes an acute probl in pipelined data paths where the results of a particular operation are not available until a specified number of cl cycles later due to the latency of the datapath pipeline. the QRlδ, this would impose a certain number of dead (or no-op) cycles into the pipeline after the last butterfly o the first column (butterfly D) and before the first butter of the second column (butterfly E) to avoid this date dependency. This data dependency can be understood cleerly f the timing diagram of Figure 5 which shows nine timing patterns corresponding to the memory read and write functi and the execution unit, where each of these waveforms is defined below: (a) Input Memory Write - Input data from I/O pins written in Input Data Memory 11; (b) Coeff Memory Write - Twiddle data from I/O pi written to Coefficient Memory 9; (c) Coeff Memory Read - Input data transfer to Execution Unit 7; (d) Input memory read - Input data transfer to Execution Unit 7; (e) Execute - Execution Unit activity; (f) Cache Write - Execution unit result data written to Cache Memory 15; (g) Cache Read - Cache data transfer to Execution Unit 7; (h) Output Memory Write - Execution unit result data written to Output Data Memory 13; an (i) Output Memory Read - Output data read to I/ pins . Referring now to the graph of Figure 5, A and B refer to two different QR16 butterfly data blocks. Al an refer to the first and second columns of the A block respectively. Similarly, Bl and B2 refer to the first an second columns of the B block, as illustrated in Figure 7 In the timing waveforms of Figure 5, the shaded areas on waveform indicate no activity for that function for the specified duration, whereas unshaded areas indicate processing activity. The timing diagram in Figure 5 assumes Teu = Ti i.e., pipeline cycle time is equal to I/O cycle time. Fi the input data- for block A is written to the input memory this takes sixteen (Tio or Teu) cycles to bring in the sixteen data points of block A and is shown on the Input Memory Write pattern (a) . Similarly, the twiddles for bl A are also written to the coefficient memory 9 in sixteen cycles. Note that the Coeff Memory Write (b) is delayed by eight cycles with respect to the Input Memory Write (a This situation arises because the Coeff Memory Read Al on empties three memory locations. As will be shown later, twiddle sequencing requires retransmission of three twidd for the first column butterflies. Therefore, to keep the input 11 and coefficient 5 Memory of the same depth, the Coeff Memory Write (b) is delayed 16 by eight cycles with respect to the Input Memory Write (a) . Two cycles prior t the completion of Input Memory Write (a), the execution un 7 accesses the input data memory 11 (Input Memory Read (d) and the coefficient memory 9 (Coeff Memory Read (c) ) to ge the data for the first column butterflies of block A. Not that the read process only takes eight cycles 16 since the read bandwidth is twice the write bandwidth for these memories 9, 11, as later described. Therefore, two cycles are required to fetch the data for one radix-4 butterfly f the memories 9, 11. Kence, the execution unit activity ca begin two cycles after the Coeff (c) and Input (d) Memory Read, as shown on the Execute waveform (e) . Each column o QR16 butterfly requires that eight cycles be initiated sin there are four butterflies in each column. Note that the transitions shown on the Execute waveform (e) only indicat the beginning " of a new column of butterflies and not the total execution "time of a column through the pipeline. Th radix-4 datapath on which the QR16 of the present inventio is implemented has an execution latency of six cycles 18. Therefore, the results of Al start getting written into th cache memory six cycles 18 after the execution (Al) is begun. The Cache Read (A1/A2) (g) is initiated as soon as all the results of Al are available. The twiddles for colu 2 are accessed at the seme time (Coeff Memory Read A2) (c) from the Coefficient Memory 9. Execution for column 2, i.e A2 can be started two cycles later. Six cycles 20 after start of A2 execution, the results of these computations begin to be written (h) into the output memory 13, end t data in the output memory 13 can be read (i) to the I/O (Output Memory Read) . For the output memory 13, the wri bandwidth is twice the read bandwidth, as described late herein, and thus the results of a column of butterflies written in eight cycles and read in sixteen cycles. The sequence of operations described above is repeated for b B and every other block thereafter. It should be noted, however, that the shaded areas in the Execute timing wav (e) indicate dead time periods 22 attributable to this da dependency in the processing through the QR16. Specifica for this datapeth, e dead time period 24 consisting of se Teu (or Tio) cycles would be introduced into the pipeline between the Al and A2 execution. However, in accordance with the present inventi this latency can be eliminated by interleaving the QR16 computations of two 16-point blocks in the datapeth. To accomplish this, twice as large on-board memories are use store two 16-point data blocks on-chip at the same time, illustrated in the timing diegrem of Figure 5 which shows timing diagram for two interleaved QR16 butterfly computa ions. The timing waveforms shown in Figure 5 hav the same definitions as in Figure 5, and A and 3 again re to two QP.15 butterfly data blocks. The input data for th two Q 15 butterfly data blocks (A and B) is written (a) t 1G the input data memory 11 sequentially, and this takes 32 (2x15) cycles. However, twiddle data for both block A an is written (b) to the coefficient memory 9 in a scrambled fashion, which will be explained later, and is agεin dela 25 by sixteen cycles with respect to the Input Memory Wri (a) . Once the input data for a pair of QRlδ blocks is available in the input data memory 11, the execution unit reads the input data memory 11 to start the first column block A computations (e) (Al) . As soon as the data for t last butterfly of Al has been read, the first column of b B computations are initiated. The sequence of operations just described for interleaved QR16 butterflies is illustrated in Figure 7a, and a more detailed version of computation is illustrated in Figure 7b. It should be no in Figure 6 that as soon as Bl computations are complete, results of Al are already available for fetching from the cache memory 15 to compute A2. As this computation is completed, the results of 31 are already available in the cache memory 15 for computing B2. Finally, this process c be repeated for the next pair of QR16 data blocks, and so on. This interleaving scheme in accordance with the prese invention requires 32 storage locations in all the on-boar memories 9, 11, 13 and 15. As can be seen from the Execut timing waveform (e) in Figure 6, there are now no no-op or shaded areas 28 on this waveform, thus indicating a continuously busy datapath. Figure 7c shows the twiddle o coefficient sequence for this interleaved scheme, as explained below in detail later herein in connection with the addressing for the coefficient memory 9. Having defined the basic memory requirements fo QR16 and- having discussed the interleaved QRlδ scheme, th details of each of the on-board memories will now be described. The cache memory 15 is a conventional double-buffered structure or dual-port memory to allow concurrent read/write for the pipelined datapath. As indicated in Figure 6, to keep the datapath pipeline continuously busy with the interleaving scheme, the cache memory 15 must be written with the results of Bl and at t same time the results of Al need to be read. The cache memory 15 is preferably comprised of four banks 24 bits w and 16 words deep. Therefore, the cache memory 15 may ha 32 complex data words (48 bits) locations or 64 real data word (24 bits) locations. The word width is governed directly by the data in the datapath on which the QRlδ is implemented. The cache memory 15 must be able to supply accept two complex words every clock cycle. The cache me addressing can be accomplished for example, by a four-bit counter and a few multiplexers (mux) . Some conventional counter and mux logic supports sequential data ordering as well as conventional digit-reversed data ordering. As mentioned above, the results of the first column of a QR16 butterfly are stored in digit-reversed order and read in sequential order for the second column calcula ions. Input date memory 11 and output data memory 13 placed at the input and output of the datapath, respectiv are of conventional design and used for data buffering an concurrent read/write operation. Both the input and outp memories 11, 13 are also four banks 24 bits wide and 16 w deep having 32 complex data words (48 bits) locations or 6 real data word (24 bits) locations. The memory buffering structures are used here for the reasons that there is a speed gap between slow I/O and a fast datapath, and that there is a need for convenient simultaneous read/write operations. On the proposed datapath, a radix-4 butterfly can be executed every two pipeline cycles. This implies t two data quantities must be supplied every pipeline cycle data per cycle x 2 cycles = 4 data values per radix-4 butterfly) if the data and twiddle have separated dedicate I/O ports. However, it is generally not possible to suppl two data values every cycle with just one data and one twiddle port if the I/O cycle time is the same as the pipeline cycle time. This is the speed gap that exists wh is eliminated by using memory structures 9, 11, 13 at the input end output of the datapath. The timing shown in Figu 5 assumes one common clock between I/O and execution unit i order to minimize the complexity of the control structure, with a common clock, it becomes necessary to have the read bandwidth of the input memory 11 be twice the write bandwid and vice versa for the output memory 13. The timing shown therefore avoids boundary conditions in the memories for ea of implementation. Even if different clocks are used for the I/O and the datapath, the use of memory structures at input and output eases the interface problem between exter circuitry and the internal datapath. In addition to the input and output memories 11, 13, there is also a coefficient memory 9 which is used for storing the twiddle data, as shown in Figure 3a. The coefficient memory 9 is preferably comprised of four banks bits wide and 20 words deep. Thus, the coefficient memory may have 40 complex data words (48 bits) locations or 80 r data word (24 bits) locations. However, only 30 locations are used to store two sets of 15 twiddles corresponding to the pair of QR16 data blocks resident in the input memory for the interleaving scheme. The coefficient memory 9 structure is otherwise similar to the input and output memories 11, 13 ' previously described. The coefficient mem 9 also has a read bandwidth twice that of the write bandwidth, and is of conventional configuration for supporting non-sequential read addressing. It should be noted that three twiddle factors, Wl, W2 , and W3, are shar across all radix-4 butterflies in the first column of data block A, as shown in Figure 7b. For the second column butterflies of data block A, 12 unique twiddles, W4 to W15 are read from the coefficient memory 9 sequentially. In t interleaving scheme according to the present invention as illustrated in Figure 7c, Wl to W3 are read 4 times for th first column calculation of data block A (Al) and then W15 W1S are read 4 times for the first column calculation of data block B (Bl) . Then W4 to W15 are read sequentially f second column calculations of data block A (A2) and W19 to W30 are read similarly for second column calculations of da block A (A2) and W19 and W30 are read sequentially for seco column of data block B (B2) . The required read sequence fo the twiddles in the interleaving scheme of the present invention is shown more clearly in Figure 7c which indicate the address locations of the twiddle inputs (numbered in hexadecimal notation) . The coefficient memory 9 only supports read-retransmission from the required locations, a the combined sequence between the first 15 and the second 1 twiddles is supported by an external address generator 21, illustrated in Figure 10. In the QR16 according to the present invention, t levels of address generation are required. First, a given size FFT must be composed of QR16 blocks and the appropriat number of passes of radix-16, radix-4 and radix-2 must be calculated. The equations for data and twiddle sequencing perform an N point FFT by QR16 are shown in Figure 8. The data and twiddle addressing at this block level, where a pa of 16-point data blocks are brought from external memory (MEM) 32, 34 and 36, is done by an off-chip conventional address generator (AG) 21, 23, 25, as shown in Figure 10. previously described, the external AG 21, 23, 25 must combin the twiddles of two QRlδ blocks in the manner shown in Figur 7c. At the second level, the address generation is required within the pair of data blocks and this, as previously discussed, is handled on-chip by conventional addressing circuitry associated with each on-board memory 9, 11, 13 15. Referring now to Figure 9, there is shown a schematic diagram of processor circuitry according to the present invention for operation in the quasi-radix-16 embodiment. This circuitry and the datapath therethrough accomplish a radix-4 complex butterfly every two cycles us 6 multipliers 27, 29, 31, 33, 35 and 37, and with 3 stages adders 39-42, 44-47 and 49-52, to permit a 16-cycle QR16 butterfly processing of data and twiddles applied to input registers 53-66. The data bandwidth required by this datapath for the QR16 butterfly is achieved by doubling th read/write bandwidth of the on-board memories. Thus, on e execution cycle, the on-board memories can supply/accept t sets of two complex numbers. Thus, with reference to the 1, above, the date for processing successively higher-orde terms is arranged generally from left to right in that the data inputs are supplied via data registers 53, 54, the D-- data inputs are supplied via data registers 55, 56, the D 2 data inputs are supplied via data registers 57, 58 end the data inputs are supplied via data registers 59, 60. Similarly, the W-, twiddle inputs are supplied via data registers 61, 62, the W2 twiddle inputs ere .supplied via d registers 63, 54, and the W3 twiddle inputs are supplied v data registers £5, 55. The groups of multiplexers 57, 68 63 , 70 and 71, 72 are cross connected to facilitate the complex cross-product multiplication in the respective multipliers during alternate cycles to yield products that are stored in registers 74-81. The initial products are arithmetically combined in adder/subtractor units 39-42 an stored in the registers 82-85. The outputs of registers 82-85 again combined in a second stage of adder/subtractor units 44-47 and stored in data registers 87-94. The data registers 87-94 is supplied via multiplexers 95-96 to the arithmetic logic units 49-52. Registers 98-102 are couple to receive and store the results from the arithmetic logic units 49-52. The outputs of these registers 98-102 are coupled to a data formatter multiplexer 104 that organizes the data from the registers for output to the memories in desired 24 or 48 bit format. Thus, the complex data for is processed in multipliers 27, 29 during first and second cycles, the complex data for D 2 * 2 is processed in multipli 31, 33 during first and second cycles, end the complex data for D 3 W 3 is processed in multipliers 35, 37 during first a second cycles. Ultimately, the processed complex outputs (say, from first column processing appeer at outputs 106, 1 for DO in one cycle, and at outputs 108, 109 for D-j in the one cycle, and appear at outputs 105, 107 for D2 in the second cycle, and et outputs 108, 109 for D-. in the second cycle. ith the eid of cache memory 15 on-chip, these outputs from first-column processing are stored to provide the data inputs for second-column processing according to t quasi radix-16, as previously described. This circuit al supports radix-2 and radix-4 butterfly processing operations. A radix-2 butterfly can be done in a single cycle in this circuitry, but I/O only supplies half of th required data in one cycle, which therefore limits the radix-2 processing to 2 cycles. Radix-4 butterfly proces can be executed in 2 cycles, but for the same reason, it takes 4 cycles to read the data. In this circuitry, the butterfly is the only operation that achieves 100% execut utilization, as shown in Figure 6. More specifically, th QR16 according to the present invention is most efficient the FFT size is an integral power of 16, for example 256 x 16), 4K (15 x 16 x 16), as illustrated in Table 1 above but is also capable of speeding up the computation by 30 50% for other FFT sizes. Assuming a 20 nanoseconds I/O r and a 40 nanoseconds radix-4 butterfly, the QR16 accordin the present invention performs a IK FFT in 61.4 microseco compared with 102.4 microseconds if only radix-4 butterfl passes were used on the same circuitry. Performance improvements due to the QR16 according to the present invention for other FFT sizes are also tabulated in Table above. Referring now to Figures 11-14, there is shown pictorial representation of the prefe red memory sto age scheme for the coefficient, input, output and cache memor 9, 11, 13 and 15. Each of the memories 9, 11, 13 and 15 comprise a left bank of complex memories (A÷jB) and a rig bank of complex memories (C÷jD) . The memories 9, 11, 13 15 preferably have 20 row addresses designated in the top of each chart. Therefore, at each address one word may b written the left bank and another word may be written in t 5 right bank of complex memory. The charts of Figures 11-14 detail the write and read sequences for words written the respective memories. For example, as shown in Figure 11, write sequence for Radix 2, 4 or 16 (a) in the input data memory II writes word 0 at the left bank (A÷j3) of address 10 word 1 at the right bank (C÷jD) of address 0, and word 2 a the left bank (A÷jB) of address 1. Words 3-lf are similar written according to the write sequence indicated in Figur lie. Exemplary schemes for reading and writing data in th memories 9, 11, 13 and 15 are shown in remaining charts of 15 Figures 11-14. The data is preferably retrieved and store in the memories 9, 11, 13 and 15 with address sequences ordered linearly or in some form of reverse addressing. As noted above, the data in the Coefficient Memory 9, may be ordered in a scrambled fashion to permit 100% use of the 20 execution unit 7 as described above with reference to Figur "> -.

Claims: CLAIMS 25 1. A processor for performing fast Fourier transforms, said processor comprising: an input memory having inputs and outputs for storing data; an output memory having inputs and outputs for storing data; a cache memory having inputs and outputs for storing data; a coefficient memory having inputs and outputs storing data; and an execution unit having inputs and outputs for performing logical and arithmetic operations on real and imaginary numbers, the outputs of said execution unit cou to the inputs of the output memory and the cache memory, t inputs of said execution unit coupled to the outputs of t input memory, the outputs of the coefficient memory and t outputs of the cache memory. 2. The processor of claim 1, wherein the input memory, the output memory, the cache memory and the coefficient memory are 32 words deep. 3. The processor of claim 1, wherein the cache memory can supply and accept two words every clock cycle. 4. The processor of claim 1, wherein the input memory and the coefficient memory have a read bandwidth tw the write bandwidth, and the output memory has a write bandwidth twice the read bandwidth. 5. The processor of claim 1, wherein the execution further comprises: a plurality of input registers having inputs and output for storing data; a plurality of multipliers having inputs and outputs for performing cross product multiplication, the inputs of said plurality of multipliers coupled to the outputs of said registers; a plurality of arithmetic logic units having an inputs and outputs for performing logical and arithmetic operations on the data input, the inputs of said first stage coupled to the outputs of the arithmetic logic units; and a multiplexer having inputs and outputs for formatting the data input, the inputs of said multiplexer coupled to the outputs of the plurality of multiplexers. 6. The processor of claim 5, wherein plurality o arithmetic logic units comprise: a first stage of arithmetic logic units having an inputs and outputs for generating the sum or difference of data input, the inputs of said first stage coupled to the outputs of the multipliers; a second stage of arithmetic logic units having an inputs and outputs for generating sums and differences, the inputs of said second stage coupled to the outputs of the first stage; and a third stage of arithmetic logic units having an inputs and outputs for performing logical and arithmetic operations, the inputs of said third stage coupled to the outputs of the second stage. 7. The processor of claim 1, wherein the input memory, the output memory, the cache memory, the coefficie memory and the execution unit art constructed on a single chip . 8. The processor of claim 1, wherein the execution unit is a radix-4 processor. 9. The processor of claim 1, wherein the execution unit, input memory, output memory, cache memory coefficient memory are constructed on a single chip. 10. A method for performing fast Fourier transforms on a quasi radix-16 processor having an executi unit, input memory, output memory, coefficient memory and cache memory, said method comprising the steps of: storing data in the input memory and coefficient memory; reading data from the input memory and coefficie memory; performing calculations on the data from input memory and coefficient memory with the execution unit; storing the output of the execution unit in cach memory; reading data from cache memory; performing calculations on the data from cache memory, input memory and coefficient memory with the execution unit; and 28 £ the execution unit in outpu . storiinngg the output o memory-

Inventors: BHATIA ROHIT, FURUTA MASARU, BHATIA, ROHIT, FURUTA, MASARU
Applicants: SHARP KK, SHARP MICROELECT TECH INC, SHARP KABUSHIKI KAISHA, SHARP MICROELECTRONICS TECHNOLOGY INC.
Application year: 1992
Main classification: G06F15
IPC codes: G06F17