Sequential memory accessing

Abstract: A processing system provides efficient accessing by a processor of a memory during a sequential memory access. The processing system includes a memory having a plurality of storage locations, each being addressable at a corresponding different storage address, a processor coupled to the memory for addressing the memory storage locations for accessing the storage locations and control means coupled to the memory and to the processor. The control means is responsive to a sequential access by the processor for causing the processor to address selected spaced apart ones of the storage locations in order and is arranged to access the other memory locations in order between the processor addresses to provide an access rate of one word of information per system clock cycle.

Description: The present invention generally relates to a processing system and more particularly to a processing system which exhibits improved efficiency in memory accessing during sequential memory accesses. Processing systems are well known in the art. Such systems generally include a processor which performs executions on operand data pursuant to operating instructions and a memory for providing the processor with the operating instructions and data. The processor of such a system is also generally arranged to write data to the memory, such as resultants, resulting from the executions performed on operand data. The reading of operating instructions and data from the memory and the writing of data to the memory are generally referred to as memory accesses by the processor. During a single access, the processor reads or writes a full or partial word of information from the memory. A full word may, for example, be 32 bits wide, and a partial word, 16 bits wide. The memory, for storing the data and instructions, generally includes a plurality of memory locations with each location having a unique memory location address. In many instances, the memory is formed by a plurality of memory banks with each bank having a plurality of addressable storage locations. The memory banks are generally organized such that each memory location of one bank finds a corresponding memory location in the other banks having the same address except for a one- or two-bit designator which designates the memory bank in which the addressed memory location resides. For example, in a two memory bank system, a memory location of the first bank may have an address N while the corresponding memory location of the second bank may have an address of N+4. The memory addresses may be, for example, 32 bits wide with the addresses differing in the third or A(2) bit so that when the A(2) bit is zero, the first bank is addressed and when the A(2) bit is one, the second bank is addressed. As a further example, in a four memory bank system, a memory location of the first bank may have an address N, while the corresponding memory location of the second, third and fourth banks would have addresses N+4, N+8, and N+12, respectively. Here, the A(3) and A(2) bits of the 32-bit address would serve as the designator to determine which bank is being addressed. In performing memory accesses, the processor generates a memory location address and conveys the same over a multiple-bit address bus to the memory banks. For a read operation, a memory controller provides a ready signal while the memory bank having the memory storage location corresponding to the conveyed address provides the requested data or instruction from that memory location to the processor over a bidirectional, multiple-bit, data/instruction bus. For a write operation, the memory controller provides the ready signal and the processor provides the addressed memory storage location with the data over the data/instruction bus. The timing between the processor and the memory is generally controlled by a system clock which may be external to the processor or generated by the processor. The system clock provides a series of clock cycles including a high phase and a low phase. The timing control by the system clock may be such that the processor provides addresses, control signals and data during the high phase of the system clock and receives control signals and data or instructions from the memory during the low phase. Processing systems generally require multiple system clock cycles from the time the processor provides a memory address to when the memory either provides the requested data or instruction word in the case of a read access or to when the memory is ready to receive the data word from the processor in the case of a write access. For example, such a sequence can require two system clock cycles, four system clock cycles, or more than four system clock cycles, depending upon the design of the processing system. While such time periods for memory accesses may be acceptable for single, one word accesses, it would be desirable to speed-up this process when multiple-words of information are to be conveyed between the processor and memory banks, as, for example, during sequential memory accessing. The processing system described herein provides efficient transfer of multiple words of information between the processor and memory when the processor makes a sequential address memory access request. The processing system is more particularly of advantage when the processor makes a sequential address memory access request wherein the memory banks are interleaved. Interleaving is a process, well known in the art, wherein the address banks are sequentially addressed by a processor. As will be seen hereinafter, the processing system provides efficient sequential address accessing by permitting the processor to address only a certain one or certain ones of the memory banks. A memory controller sequences the other memory banks in proper order to permit the microprocessor to generate the address of the memory location of the memory banks it is to address early to the end that words of information can be conveyed between the processor and the memory at a rate of one word per system clock cycle. In EP-A-283115 there is disclosed a processor with burst mode addressing capability supported by a memory accessed by the processor. The Wescon Conference Record Vol. 34, November (1990), pages 488 - 494, discloses a burst mode addressing processor with a memory control circuit arranged to access memory banks with interleaving. According to the present invention there is provided a processing system comprising: memory means including a plurality of storage locations, each of the storage locations being addressable at a corresponding different storage address; and a processor coupled to the memory means for addressing and accessing the storage locations; characterised in that control means is coupled to the memory means and to the processor, the control means being responsive to the processor to effect a sequential access of the memory means in a predetermined sequence whereby the processor sequentially addresses selected first storage locations of the plurality of storage locations and the control means sequentially accesses selected second storage locations of the plurality of storage locations, the selected first storage locations being alternately arranged with the selected second storage locations, and the processor addressing a next location of the selected first storage locations before the control means completes accessing selected second storage locations. In one embodiment of the invention, the memory means comprise first and second memory banks, the control means being so arranged that the processor sequentially addresses the storage locations of one of the memory banks. The control means is then further arranged to access the storage locations of the other memory bank. In a further embodiment, the memory means comprises a plurality of memory banks, and the control means is so arranged that the processor addresses one of the memory banks. The control means then accesses the other memory banks. The processing system preferably includes a first bus between the processor and the memory means for conveying data between the processor and the memory means, and a second bus between the processor and the memory means for conveying the storage location addresses from the processor to the memory means. The processing system preferably includes a system clock coupled to the processor and the memory means, the clock providing a repetitive clock cycle timing signal to control the timing of the processor and the memory means. The processor is arranged to hold each of the storage location addresses valid during multiple cycles of the system clock, and the control means is arranged to access the second storage locations as the addresses are held valid by the processor to permit the processor to write a word of data to or read a word of data from the memory means during each cycle of the system clock. In the accompanying drawings, by way of example only: Figure 1 is a schematic block diagram of a processing system embodying the present invention which includes a memory having a pair of memory banks; Figure 2 is a series of waveforms which may be referred to in understanding the manner in which the processing system of Figure 1 may be implemented; Figure 3 is a schematic block diagram of a processing system which includes a memory having four memory banks in accordance with a second embodiment of the present invention; and Figure 4 is a series of waveforms which may be referred to in understanding the manner in which the processing system of Figure 3 may be implemented. Referring now to Figure 1, it illustrates in schematic block diagram form, a processing system 10 structured in accordance with a first embodiment of the present invention. The processing system 10 generally includes a processor 12, a memory 14 including a first or even memory bank 16, and a second or odd memory bank 18. The processing system 10 further includes a memory controller 20 and a system clock 22. The memory controller 20 may be external to the memory banks 16 and 18 or may be within the memory 14 comprising the memory banks 16 and 18. The system clock 22 may be external to the processor 12 as illustrated or may be internal to the processor 12, wherein the processor 12 generates the system clock repetitive control cycles, also without departing from the present invention. The processing system 10 further includes a first bus 24 coupled between the processor 12 and the memory banks 16 and 18. A second bus 26 is also coupled between the processor 12 and the memory banks 16 and 18. The processor 12 is preferably of the type which performs executions upon operand data pursuant to operating instructions, wherein the processor acquires the operating instructions and operand data from the memory 14 comprising the memory banks 16 and 18. Also, the processor 12 is preferably of the type which writes resultants resulting from the executions upon the operand data pursuant to the operating instructions, to the memory 14 comprising memory banks 16 and 18. To that end, the first bus 24 comprises a data/instruction bus for conveying data and instructions between the processor 12 and the memory banks 16 and 18. The data/instruction bus 24 is preferably a 32-bit bus including individual conductors for data/instruction bits 0 through 31. In order to obtain the data and operating instructions from the memory 14, each of the memory banks 16 and 18 includes a plurality of addressable storage locations for storing data and operating instructions. To enable the accessing of the memory banks 16 and 18, the processor 12 is arranged to generate the addresses of the storage locations, which addresses are conveyed to the memory banks 16 and 18 over the address bus 26. The address bus 26 is also preferably a 32-bit bus including individual conductors for address bits 0 through 31. The conductor corresponding to address bit A(2) is coupled to the memory controller for reasons to be explained hereinafter. When accessing the memory 14 for either reading data or instructions from the memory 14 or writing data to the memory 14, the processor 12 generates the appropriate addresses corresponding to the memory bank storage locations to be accessed and then the memory banks 16 and 18 provide the requested data/instruction or store the data to be transferred from the processor 12 to the memory 14. The memory banks 16 and 18 are preferably arranged such that each memory location of memory bank 16 finds a corresponding memory location in memory bank 18. The corresponding memory locations have addresses which differ by a designator contained within address bit A(2). As a result, a memory location in memory bank 16 having address N will find a corresponding memory location in memory bank 18 having an address N+4. In other words, ttie memory bank 16 is addressed when the A(2) bit is a zero and the memory bank 18 is addressed when the address bit A(2) is a one. The memory locations of memory banks 16 and 18 are arranged sequentially. The memory locations of memory bank 16 are arranged so that the sequential address for the storage locations in memory bank 16 will be, for example, N, N+8, N+16, et cetera. Correspondingly, the memory locations of memory bank 18 will be in a sequence having addresses N+4, N+12, N+20, et cetera. As will be seen hereinafter, when the processor 12 requests a sequential access to the memory 14, the memory banks 16 and 18 will be interleaved such that the processor 12 receives data or instruction words or transfers data words to the memory banks 16 and 18 in sequence, as for example, first to memory 16 at address N, then memory bank 18 at address N+4, then memory bank 16 at address N+8, and then to memory bank 18 at address N+12. A control bus 28 also couples the processor 12 to the memory controller 20. The control bus 28 conveys various control signals between the processor 12 and memory controller 20 which will be further described hereinafter. These control signals assist in the coordination of a memory access from the processor 12 to the memory 14. The system clock 22 is coupled to both the processor 12 and the memory controller 20. It provides timing control between the processor 12 and the memory controller 20. The system clock 22 provides a repetitive series of clock cycles which include a high phase and a low phase. The processing system 10 is preferably arranged such that during the high phase of the system clock 22, the processor 12 initiates memory addresses, control signals, and data and during the low phase, the memory 14 or controller 20 initiates control signals and data or operating instructions. In accordance with the prior art, a simple access by the processor 12 to the memory 14 may take two system clock cycles to complete. In order to render information transfer more efficient, the processor 12 is arranged to request a sequential memory access to obtain data or instruction words or write data words to the memory at a rate of one word per system cycle. For purposes of this preferred embodiment, it is assumed that a word of information contains 32 bits. However, partial words of information may also be conveyed, as for example 16 bits, wherein the selection of a whole word or partial word is made by address bits A(0) and A(1). The control signals conveyed between the processor 12 and memory controller 20 over control bus 28 are identified herein as *REQ, R/*W, *BURST, *RDY, and *ERLYA. Each of these control signals is defined hereinafter. *REQ is a signal generated by the processor upon requesting a memory access. When this signal is active (low), the address for the access appears on the address bus 26. R/*W indicates whether the processor access is a read or a write access. If the access is a read access, this signal will be high and if the access if a write access, this signal will be low. *BURST is a control signal generated by the microprocessor to indicate a burst-mode access. When this signal is active low, it indicates to the memory 14 that a sequential, interleaved memory access is being requested by the processor 12 within the page mode being assumed. *RDY indicates, for a read access, that a valid data or instruction word is on the data/instruction bus 24. For a write access, this signal indicates that the access is complete and that data need no longer be driven by the processor 12 on the data/instruction bus 24. Lastly, *ERLYA is generated by the memory controller 20 in response to the *BURST signal generated by the processor 12. This signal, as will be seen hereinafter, causes the processor 12, during its sequential access, to provide sequential addresses for only memory bank 16 which, as will be seen hereinafter, results in the early transmission of burst-mode addresses. Referring now to Figure 2, it illustrates waveforms which represent the manner in which the processing system 10 may be implemented in practicing the present invention in accordance with this first preferred embodiment. As can be seen from the Figure, waveforms representing the system clock (MEMCLK), the address bits, the access request signal, the read or write control signal, the burst control signal, the ready signal, the early addressing signal, and the data/instruction bus bits are represented during six system clock cycles starting with the request for a sequential memory access by the processor 12. The processor 12 initiates the sequential memory access during the high phase of the system clock cycle 1. At this time, the processor 12 places address N onto the bus, drives the memory access request signal to an an active low, drives the read/write control signal high to indicate a read access, and drives the *BURST control signal low to indicate to the memory controller 20 that a sequential access has been requested. As will be noted in Figure 2, the processor 12 holds the address N on the address bus valid for two complete system clock cycles. During the low phase of the system clock cycle 2, the memory controller 20 drives the *RDY control signal low to indicate that the data or instruction from memory bank 16 is currently on the data/instruction bus 24 and also drives *ERLYA control signal to an active low in response to the processor driving *BURST low during the high phase of the system clock cycle 1. At this time, the requested data or instruction word stored at address N in memory bank 16 is currently on the data/ instruction bus to be read by the processor 12. During the high phase of system clock cycle 3, the processor 12 then generates the next sequential address for memory bank 16 which is address N+8. Because the memory controller 12 received the A(2) address bit of zero from the microprocessor 12, it sequences memory bank 18 to activate memory bank 18 to cause that memory bank to provide the data or instruction word stored at address N+4 onto the data/instruction bus 24 during the low phase of system clock cycle 3 at the same time the memory controller 20 drives the *RDY control signal to an active low to indicate to the processor 12 that the data or instruction word stored at memory location N+4 of memory bank 18 is currently on the data/instruction bus 24. In response to the address N+8 on the address bus 26, the memory bank 16 then provides the data or instruction word stored at address N+8 on the data/instruction bus 24 during the low phase of the system clock cycle 4. At the same time, the memory controller 20 drives the *RDY control signal to an active low to inform the processor 12 that the data or instruction word stored at address N+8 of memory bank 16 is currently on the data/instruction bus 24. The foregoing sequence continues until the sequential memory access of processor 12 is complete. As can be seen from the foregoing, even though a simple or single access by processor 12 normally takes two system clock cycles to complete, because the memory controller 20 activates memory bank 18 in between the addresses generated by processor 12 for memory bank 16, the processor 12 is able to obtain a data or instruction word from the memory 14 during each system clock cycle. In addition, this improved efficiency in sequential accessing results from the fact that the microprocessor 12 can provide the addresses for memory bank 16 early. If the sequential address were to be conducted as a series of simple accesses, the microprocessor would have provided address N+4 during the high phase of system clock cycle 3 and held that address valid until the high phase of system clock cycle 5. However, by virtue of the present invention, the processor 12 can provide address N+8 early when it otherwise would have provided address N+4. As a result, the *ERLYA control signal provided by the memory controller 20 causes the processor 12 to address only memory bank 16. Further, the memory controller 20 sequences the other memory bank, memory bank 18, in between the accesses of memory bank 16 by the processor 12. While Figure 2 illustrates the sequential accessing by processor 12 of memory 14 for a read access, the same waveforms would result for a write access except that the R/*W control signal would have been driven to an active low by the processor 12 during the high phase of system clock cycle 1 and would have driven the data for storage in storage location having address N onto the data/instruction bus 24 during the high phase of system clock cycle 2. From there, the sequence of events would have been as illustrated to permit the processor 12 to write data words to memory 14 at a rate of one data word per clock cycle with the data words being alternately stored in memory bank 16 and memory bank 18 during alternate system clock cycles. Referring now to Figure 3, it illustrates another processing system 30 structured in accordance with a second preferred embodiment of the present invention. The processing system 30 generally includes the processor 12, the system clock 22, the memory controller 20, and a memory 32 comprising a first memory bank 34, a second memory bank 36, a third memory bank 38, and a fourth memory bank 40. In a manner similar to the embodiment of Figure 1, the processor is coupled to the memory banks 34, 36, 38 and 40 by a data/instruction bus 24 for conveying data or instruction words between the processor 12 and memory 32 and an address bus 24 to permit the processor 12 to address the addressable storage locations of memory banks 34, 36, 38 and 40. The processor is also coupled to the memory controller 20 by the control bus 28 for conveying the same control signals as previously described with respect to the embodiment of Figure 1. Also, the memory controller 20 is coupled to the address bus 24 for receiving address bus bits A(3) and A(2). Like the processing system embodiment of Figure 1, the system clock 22 may be external to the processor 12 as illustrated or may be internal to the processor 12. Also, like the processing system embodiment of Figure 1, the data/instruction bus 24 is preferably a 32-bit bus conveying data or instruction words having bits 0 through 31 and the address bus 26 is also preferably a 32-bit bus conveying address bits 0 through 31. The memory banks 34, 36, 38 and 40 also preferably include a plurality of addressable storage locations wherein a storage location of one bank finds a corresponding storage location in the other banks with the addresses of the corresponding memory locations differing by the state of the address bits A(3) and A(2). When these address bits are both zeroes, memory bank 34 is addressed, when A(3) is zero and A(2) is one, memory bank 36 is addressed, when A(3) is one and A(2) is zero, memory bank 38 is addressed, and when both of these bits are ones, memory bank 40 is addressed. As previously mentioned, the memory controller 20 is coupled to the address bus 26 for receiving the condition of these address bits. The memory controller 20 is also coupled to each of the memory banks 34, 36, 38 and 40, for sequencing the memory banks in a manner to be described hereinafter. The processing system 30 includes four memory banks because it preferably is arranged to allow a single memory access by processor 12 to memory 32 to be completed within four clock cycles of the system clock 22. As will be seen hereinafter, when the processor 12 initiates a sequential memory access of memory 32, the memory controller 20 will sequence memory banks 36, 38 and 40, to provide the processor 12 with data or instruction words at a rate of one word per system clock cycle or to permit the processor 12 to write data words to the memory 32 at a rate of one data word per system clock cycle. Referring now to Figure 4, a sequential read access is initiated by processor 12 during the high phase of system clock cycle 1. At this time, the processor 12 provides address N to address memory bank 34, drives the *REQ control signal to an active low to request the memory access, drives the R/*W control signal high to indicate that the access is a read access and drives the *BURST control signal active low to inform the memory controller 20 that the access is a sequential access. During the low phase of the system clock cycle 2, the processor 12 is holding address N valid, the memory controller 20 generates the *ERLYA control signal to an active low which will cause, as will be seen hereinafter, the processor 12 to address the memory storage locations of memory bank 34 in sequence. During the high phase of system clock cycle 3, the processor 12 generates address N+8. The generation of N+8 is done by convention to simplify the processor hardware. However, without departing from the present invention, the microprocessor 12 could have held the address N active from the high phase of cycle 1 to the high phase of cycle 5 as well. It will be noted that the data stored at address N is provided to the data/instruction bus 24 during the low phase of cycle 4 at the same time that the memory controller drives the *RDY control signal to an active low to indicate to the processor 12 that the requested data from address N is currently on the data/ instruction bus 24. Even though the processor 12 generates address N+16 during the high phase of cycle 5, the memory controller 20 sequences the memory banks 36, 38 and 40, during successive system clock cycles to provide the data stored at address N+4 of memory bank 36 to the data/instruction bus 24 during the low phase of cycle 6 along with the *RDY control signal driven to an active low. The foregoing sequence continues until the sequential access is completed by the processor 12. As can be seen from the foregoing, with the four-bank interleaved embodiment of Figure 3, the processor 12 addresses memory bank 34. When the memory controller 20 senses that the A(3) and A(2) bits are both zeroes, it will sequence memory banks 36, 38 and 40, during successive system clock cycles to enable the processor 12 to receive data or instruction words from the memory 32 at a rate of one word per system clock cycle. As with the embodiment of Figures 1 and 2, the waveforms of Figure 4 would be essentially identical for a processor write access except that the R/*W control signal would have been driven to an active low by the processor during the high phase of cycle one and the processor would have provided the data for storage at address N on the data/instruction bus 24 during the high phase of cycle 4. Otherwise, the sequence of events would have been identical. As an alternative embodiment, if the processing system 30 was arranged to complete a simple access in two system clock cycles, the memory controller 20 could cause the processor 12 to address memory banks 34 and 38 and the memory controller 20 could then have sequenced memory banks 36 and 40 in the proper sequence to provide the sequential accessing by the processor 12 without departing from the present invention. As can be seen from the foregoing, the present invention provides a processing system having improved efficiency for accessing memory during sequential memory accesses. Even though a simple access may take multiple clock cycles, by virtue of the present invention, sequential memory accesses may be accomplished by the processor at a rate of one word per system clock cycle.

Claims: A processing system comprising: memory means (14, 32) including a plurality of storage locations, each of the storage locations being addressable at a corresponding different storage address; and a processor (12) coupled to the memory means (14, 32) for addressing and accessing the storage locations; characterised in that control means (20) is coupled to the memory means (14, 32) and to the processor (12), the control means (20) being responsive to the processor (12) to effect a sequential access of the memory means (14, 32) in a predetermined sequence whereby the processor (12) sequentially addresses selected first storage locations of the plurality of storage locations and the control means (20) sequentially accesses selected second storage locations of the plurality of storage locations, the selected first storage locations being alternately arranged with the selected second storage locations, and the processor (12) addressing a next location of the selected first storage locations before the control means (20) completes accessing selected second storage locations. A processing system as defined in claim 1 wherein the memory means (14) comprise first (16) and second (18) memory banks, wherein the control means (20) is so arranged that the processor (12) sequentially addresses the storage locations of one (16) of the memory banks, and wherein the control means (20) is arranged to access the storage locations of the other (18) memory bank. A processing system as defined in claim 1 wherein the memory means (32) comprises a plurality of memory banks (34, 36, 38, 40), wherein the control means (20) is so arranged that the processor (12) addresses one (34) of the said memory banks, and wherein the control means (20) accesses the other memory banks (36, 38, 40). A processing system as defined in claim 3 wherein the memory means comprises four memory banks (34, 36, 38, 40). A processing system as defined in claim 1 wherein the memory means (32) comprises a plurality of memory banks (34, 36, 38, 40), wherein the control means (20) is so arranged that the processor (12) sequentially addresses alternate ones (34, 38) of the memory banks, and wherein the control means (20) accesses the other (36, 40) memory banks. A processing system as defined in claim 5 wherein the memory means comprises first (34), second (36), third (38) and fourth (40) memory banks, wherein the control means (20) is so arranged that the processor (12) addresses the first and third memory banks, and wherein the control means (20) accesses the second and fourth memory banks. A processing system as defined in claim 1 wherein the processor (12) provides a first control signal (*BURST) when initiating the sequential access of the memory means (14, 32), and wherein the control means (20) is responsive to the said first control signal. A processing system as defined in claim 7 wherein the control means (20) provides a second control signal (*ERLYA) responsive to the first control signal to cause the processor (12) to address the said selected first storage locations in order. A processing system as defined in claim 1 wherein the processor (12) initiates either a sequential read access or a sequential write access to the memory means. A processing system as defined in claim 1 further including a first bus (24) between the processor (12) and the memory means (14, 32) for conveying data between the processor and the memory means, and a second bus (26) between the processor (12) and the memory means (14, 32) for conveying the said storage location addresses from the processor to the memory means. A processing system as defined in claim 1 further including a system clock (22) coupled to the processor (12) and the memory means (14, 32), the system clock providing a repetitive clock cycle timing signal to control the timing of said processor and said memory means, wherein the processor (12) is arranged to hold each of the said storage location addresses valid during multiple cycles of the system clock, and wherein the control means (20) is arranged to access the said second storage locations as the said addresses are held valid by the processor to permit the processor to write a word of data to or read a word of data from the memory means during each cycle of the system clock.

Inventors: JOHNSON WILLIAM M, WITT DAVID B, JOHNSON, WILLIAM M., WITT, DAVID B.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1992
Main classification: G06F12
IPC codes: G06F12