Disk array storage control system

Abstract: A system interrupt signal for a disk array is generated by selectively combining interrupt signals received from individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the system interrupt signal includes a first logic circuit (140) for combining a first group of selected interrupt signals to generate a group interrupt signal having an active state when each one of the signals in the first group is at an active state, and a second logic circuit (120) which combines a second group of selected interrupt signals to generate an independent interrupt signal having an active state when any one of the interrupt signals of the second group has an active state. The group and independent interrupt signals are gated together to generate a common system interrupt signal. The first and second logic circuits (120,140) can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user. The circuit includes filtering and latching circuits (160,170) to prevent interference with an existing array interrupt signal during reconfiguration of the group or independent interrupt logic circuits (120,140).

Description: The invention relates to apparatus for generating a system interrupt signal for a storage disk array, said disk array including a plurality of interrupt signal sources. The invention also relates to a method for generating a system interrupt signal for a storage disk array. Recent and continuing increases in computer processing power and speed, in the speed and capacity of primary memory, and in the size and complexity of computer software has resulted in the need for faster operating, larger capacity secondary memory storage devices; magnetic disks forming the most common external or secondary memory storage means utilized in present day computer systems. Unfortunately, the rate of improvement in the performance of large magnetic disks has not kept pace with processor and main memory performance improvements. However, significant secondary memory storage performance and cost improvements may be obtained by the replacement of single large expensive disk drives with a multiplicity of small, inexpensive disk drives interconnected in a parallel array, which to the host appears as a single large fast disk. Several disk array design alternatives were presented in an article titled "A Case for Redundant Arrays of Inexpensive Disks (RAID)" by David A. Patterson, Garth Gibson and Randy H. Katz; University of California Report No. UCB/CSD 87/391, December 1987. This article discusses disk arrays and the improvements in performance, reliability, power consumption and scalability that disk arrays provide in comparison to single large magnetic disks. Five disk array arrangements, referred to as RAID levels, are described in the article. The first level RAID comprises N disks for storing data and N additional "mirror" disks for storing copies of the information written to the data disks. RAID level 1 write functions require that data be written to two disks, the second "mirror" disk receiving the same information provided to the first disk. When data is read, it can be read from either disk. RAID level 3 systems comprise one or more groups of N+1 disks. Within each group, N disks are used to store data, and the additional disk is utilized to store parity information. During RAID level 3 write functions, each block of data is divided into N portions for storage among the N data disks. The corresponding parity information is written to a dedicated parity disk. When data is read, all N data disk must be accessed. The parity disk is used to reconstruct information in the event of a disk failure. RAID level 4 systems are also comprised of one or more groups of N+1 disks wherein N disks are used to store data, and the additional disk is utilized to store parity information. RAID level 4 systems differ from RAID level 3 systems in that data to be saved is divided into larger portions, consisting of one error many blocks of data, for storage among the disks. Writes still require access to two disks, i.e., one of the N data disks and the parity disk. In a similar fashion, read operations typically need only access a single one of the N data disks, unless the data to be read exceeds the block length stored on each disk. As with RAID level 3 systems, the parity disk is used to reconstruct information in the even of a disk failure. RAID level 5 is similar to RAID level 4 except that parity information, in addition to the data, is distributed across the N+1 disks in each group. Although each group contains N+1 disks, each disk includes some blocks for storing data and some blocks for storing parity information. Where parity information is stored is controlled by an algorithm implemented by the user. As in RAID level 4 system, RAID level 5 writes require access to at least two disks; however, no longer does every write to a group require access to the same dedicated parity disk, as in RAID level 4 systems. This feature provides the opportunity to perform concurrent write operations. Another disk array arrangement, referred to as parity striping, is presented in an article titled "Parity Striping of Disc Arrays: Low-Cost Reliable Storage with Acceptable Throughput" by Jim Gray, Bob Horst and Mark Walker; Tandem Computers, Inc., Tandem Technical Report No. 90.2, January 1990. In the parity striping system, only parity information is striped across the disks, but the parity is mapped as large contiguous extents. Data is not striped across the disks. The individual magnetic disks utilized in the various disk array configurations discussed in the articles referred to above may provide individual interrupt signals, each interrupt signal indicating that a specific disk has completed an operation or encountered a problem. It is an object of the present invention to provide a versatile method and apparatus of the kind specified, for generating a common interrupt signal for a disk array storage system. Therefore, according to one aspect of the present invention, there is provided apparatus for generating a system interrupt signal for a storage disk array, said disk array including a plurality of interrupt signal sources, characterized by first combining means adapted to combine a first group of selected interrupt signals to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; second combining means adapted to combine a second group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second group has a second binary value; and third combining means adapted to combine said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal and said independent interrupt signal has a first binary state and having a second binary state when both said group interrupt signal and said independent interrupt signal have a second binary state. According to another aspect of the present invention, there is provided a method for generating a system interrupt signal for a storage disk array, said disk array including a plurality of interrupt signal sources, characterized by the steps of: combining a first group of selected interrupt signals provided by said interrupt signal sources to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; combining a second group of selected interrupt signals provided by said interrupt signal sources to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second binary value; and combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal and said independent interrupt signal has a first binary state and having a second binary state when both said group interrupt signal and said independent interrupt signal have a second binary state. One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of a disk array controller incorporating the interrupt generation architecture of the present invention. Figure 2 is a functional block diagram of the SCSI Array Data Path Chip (ADP) shown in Figure 1 which incorporates the interrupt generation architecture of the present invention. Figure 3 is a functional block diagram of the interrupt module shown in Figure 2, representing a preferred embodiment of the present invention. Figures 4A through 4F show a schematic diagram of the independent interrupt masking mechanism block shown in Figure 3. Figure 5A and 5B show a schematic diagram of the group interrupt masking mechanism block shown in Figure 3. Figures 6A and 6B show a schematic diagram of the filter blocks and interrupt latch block shown in Figure 3. Referring now to Figure 1, there is seen a block diagram of a SCSI (small computer system interface) disk array controller incorporating the interrupt generation architecture of the present invention. The controller includes a host SCSI adapter 14 to interface between the host system data bus 12 and SCSI data bus 16. Parity generation and data and parity routing are performed within SCSI Array Data Path Chip (ADP) 10. ADP chip 10 interconnects SCSI data bus 16 with six additional data busses, identified by reference numerals 21 through 26. SCSI bus interface chips 31 through 35 interface between respective SCSI data busses 21 through 25 and corresponding external disk drive data busses 41 through 45. Bus 26 connects ADP chip 10 with a 64 kilobyte static random access memory (SRAM) 36. ADP chip 10, SCSI adapter 14 and SCSI bus interface chips 31 through 35 all operate under the control of a dedicated microprocessor 51. All data busses shown, with the exception of bus 16, include nine data lines, one of which is a data bus parity line. Bus 16 includes eighteen data lines, two of which are bus parity lines. Additional control, acknowledge and message lines, not shown, are also included with the data busses. SCSI adapter 14, SCSI bus interface chips 31 through 36, SRAM 36 and microprocessor 51 are commercially available items. For example, SCSI adapter 14 is a Fast SCSI 2 chip, SCSI bus interface chips 31 through 35 are NCR 53C96 chips and microprocessor 51 is a Motorola MC68020, 25 megahertz microprocessor. Also residing on the microprocessor bus are a one megabyte DRAM, a 128 kilobyte EPROM, an eight kilobyte EEPROM, a 68901 multifunction peripheral controller and various control and status registers. SCSI data path chip 10 is an application specific integrated circuit device capable of handling all data routing, data multiplexing and demultiplexing, and parity generation and checking aspects of RAID levels 1, 3 and 5. Data multiplexing of non-redundant data among five channels is also accommodated. ADP chip 10 handles the transfer of data between host SCSI adapter 14 and SCSI bus interface chips 31 through 35. The ADP chip also handles the movement of data to and from the 64 kilobyte SRAM during read/modify/write operations of RAID level 5. Figure 2 is a functional block diagram of the SCSI Array Data Path Chip (ADP) shown in Figure 1. The ADP chip consists of the following internal functional blocks: control logic block 60 including diagnostic module 62, configuration control and status register module 64, interrupt module 66 and interface module 68; DMA FIFO block 70; and data and parity routing block 100. The main function of control block 60 is to configure and to test the data path and parity path described in herein. Microprocessor interface module 68 contains basic microprocessor read and write cycle control logic providing communication and data transfer between microprocessor 51 (shown in Figure 1) and control and status registers within the control block. This interface utilizes a multiplexed address and data bus standard wherein microprocessor read and write cycles consist of an address phase followed by a data phase. During the address phase a specific register is selected by the microprocessor. During the following data phase, data is written to or read from the addressed register. Configuration control and status register module 64 includes numerous eight-bit registers under the control of microprocessor interface module 68 as outlined above. The contents of the control registers determine the configuration of the data and parity paths. Status registers provide configuration and interrupt information to the microprocessor. Diagnostic module 62 includes input and output data registers for the host and each array channel. The input registers are loaded by the processor and provide data to host bus 16, array busses 21 through 25 and SRAM bus 26 to emulate host or array transfers. The output registers, which are loaded with data routed through the various data buses, are read by the microprocessor to verify the proper operation of selected data and parity path configurations. Interrupt module 66 contains the control logic necessary to implement masking and grouping of ADP chip and individual channel interrupt signals. Any combination of five channel interrupt signals received from the disk controllers associated with channels one through five and three internally generated ADP parity error interrupt signals can be combined together to generate interrupt signals for the microprocessor. The function of DMA FIFO block 70 is to hold data received from the host until the array is ready to accept the data and to convert the data from eighteen bit bus 16 to nine bit busses 18. During read operations DMA FIFO block 70 holds the data received from the disk array until the host system is ready to accept the data and converts the data from nine-bit busses 18 to eighteen bit bus 16. Data and parity routing block 100 contains the steering logic for configuring the data and parity paths between the host, the disk array and SRAM 36 in response to control bytes placed into the control registers contained in module 64. Block 100 also includes logic for generating and checking parity and reconstructing data lost due to a single disk drive failure. Figure 3 is a functional block diagram of interrupt module 66 shown in Figure 2, representing a preferred embodiment of the present invention. The architecture disclosed includes two masking switches identified as independent interrupt masking mechanism 120 and group interrupt masking mechanism 140, connected to receive an interrupt signal from each array channel. The interrupt signals are shown as being provided by block 103, titled interrupt sources. Block 103 may also include interrupt signal sources other than the array channels, such as parity error detectors. Independent interrupt masking mechanism 120 is configured internally in response to control signals received from control/status register module 64, discussed above, to combine the signals received from interrupt sources 103 into a single independent interrupt signal on line 121. Similarly, group interrupt masking mechanism 140 is configured internally in response to control signals received from control/status register module 64 to combine the signals received from interrupt sources 103 into a single group interrupt signal on line 141. The internal structure and operation of masking switches 120 and 140 will be discussed in greater detail below with reference to Figures 4 and 5. The outputs of masking switches 120 and 140 are provided to an interrupt latch 180 which holds the system interrupt signal, generated by combining the outputs of masking switches 120 and 140, during a masking time window, explained below, and passes the system interrupt signal at all other times. The interrupt latch is controlled by two front-end filters 160 and 170, referred to as the independent interrupt filter and the group interrupt filter, respectively. Filters 160 and 170 operate in response to address decode signals received from microprocessor 51. The output of latch 180 is provided to a back-end filter 190, also referred to as the system interrupt filter, the output of which provides the "filtered" system interrupt signal for the array. The internal construction of independent interrupt masking mechanism 120 is shown in detail in the schematic diagram of Figures 4A through 4F. The independent interrupt masking mechanism includes eight two-input NAND gates, identified by reference numerals 421 through 428. Each one of NAND gates 421 through 428 is connected to receive an interrupt signal from an array channel or other interrupt signal source via one of input lines 401 through 408, respectively. More particularly, each one of gates 421 through 425 receives an interrupt signal from one of the corresponding array channels 1 through 5, while gates 426 through 428 receive a parity error interrupt signal, a memory error interrupt signal and a processor error interrupt signal, respectively. The remaining inputs of the NAND gates are connected to receive control signals from an eight-bit register 430, each one of NAND gates 421 through 428 being connected to a respective one of the BIT0 through BIT7 register outputs. The BIT0 through BIT7 inputs of register 430 are connected to the processor data bus, shown as bus 53 in Figures 1 through 3, to receive control codes, referred to as MASK1 codes, from the controller processor. The outputs of NAND gates 421 through 428 are provided to an eight-input NAND gate 450. The output of NAND gate 450 is provided to an inverter 460 to form the independent interrupt signal on line 121. In operation, independent interrupt masking mechanism 120 generates an interrupt signal on line 121 when a non-masked interrupt signal is received from one of the eight interrupt sources connected to lines 401 through 408. Masking of the interrupt signals received from lines 401 through 408 is accomplished by writing a logic 1 to the corresponding one of bits 0 through 7 of control register 430. Each register bit set high provides a logic 0 signal to the input of one of NAND gates 421 through 428, thereby blocking the transmission of the associated interrupt signal to OR gate 450. OR gate 450 combines the interrupt signals associated with control register 430 bits which have been set low. The output of OR gate 430 is inverted to generate the independent interrupt signal. Also shown in Figures 4A and 4F are two eight-bit status registers 470 and 480. Interrupt status register 470 is connected to receive the interrupt signals placed on lines 401 through 408 and provide the interrupt signals to processor data bus 53 in response to the receipt of a read interrupt register signal from the controller processor. Independent mask status register 480 is connected to receive the output of control register 430 and provide the control information to processor data bus 53 in response to the receipt of a read interrupt MASK1 signal from the controller processor. Registers 430, 470 and 480 all reside within control/status module 64. Figures 5A and 5B show a schematic diagram of group interrupt masking mechanism 140. The group interrupt masking mechanism includes five OR gates identified by reference numerals 521 through 525. Each gate includes a first input connected to receive a corresponding interrupt signal from array channels 1 through 5 and a second input connected to one of the outputs of eight-bit group mask control register 530. More specifically, OR gate 521 is connected to receive the interrupt signal from array channel 1 via line 501 and the BIT0 output of register 530, gate 522 receives the array channel 2 interrupt signal from line 502 and the BIT1 output of register 530, gate 523 inputs are connected to receive the interrupt signal from array channel 3 and the BIT2 output of register 530, gate 524 inputs are connected to receive the interrupt signal from array channel 4 and the BIT3 output of register 530, and OR gate 525 receives the array channel 5 interrupt signal and the BIT4 output of register 530. The group mask control register inputs are connected to processor bus 53 to receive control codes, referred to as MASK2 codes, from the controller processor. The outputs of OR gates 521 through 525 are provided to a NAND gate 540, the output of which forms the group interrupt signal on line 141. NAND gate 540 is also connected to receive as input the output of a second NAND gate 550 which combines the BIT0 through BIT4 outputs of register 530. In operation, group interrupt masking mechanism 140 generates a group interrupt signal on line 141 when interrupt signals are received from all non-masked sources connected to lines 501 through 505. Masking of the interrupt signals received from lines 501 through 505 is accomplished by writing a logic 1 to the corresponding one of bits 0 through 4 of control register 530. Each register bit set high provides a logic 1 signal to the input of one of OR gates 521 through 525, thereby blocking the transmission of the associated interrupt signal to NAND gate 540. NAND gate 540 combines the interrupt signals associated with control register 530 bits which have been set low to generate the group interrupt signal. NAND gate 550, which is connected to receive register 530 bits 0 through 4, disables the operation of gate 540 when control register 530 bits 0 through 4 are all set high. Also shown in Figure 5B is group mask status register 560 connected to receive the output of control register 530 and provide the control information stored therein to processor data bus 53 in response to the receipt of a read interrupt MASK2 signal from the controller processor. Registers 530 and 560 both reside within control/status module 64. A schematic diagram of independent interrupt filter 160, group interrupt filter 170, interrupt latch 180 and system interrupt filter 190 is provided by Figures 6A and 6B. Filter 160 is seen to include a first D-type flip-flop 602 having its preset (S) input connected to receive a processor reset signal, its data (CD) and clear (R) inputs connected to receive the processor write interrupt mask1 signal, and its clock (C) input connected to receive a system clock signal from the host system. The Q output of flip-flop 602 is provided to the data input of a second D-type flip-flop 604 also having its preset input connected to receive the processor reset signal, its clear input connected to receive the processor write interrupt mask1 signal, and its clock input connected to receive the system clock signal. The Q output of flip-flop 604 forms the output of filter 160. The construction of group interrupt filter 170 is similar to the construction of filter 160. D-type flip-flops 606 and 608 of filter 170 correspond to flip-flops 602 and 604 of filter 160, respectively, however the data and clear inputs of flip-flop 606 and the clear input of flip-flop 608 are connected to receive the processor write interrupt mask2 signal. The output of flip-flop 608 forms the output of filter 170. Interrupt latch 180 includes an OR gate 623 having inverting inputs connected to receive the independent interrupt signal from independent interrupt masking mechanism 120, the group interrupt signal from group interrupt masking mechanism 140, and interrupt signals provided by other sources. The combined signal output of gate 623 is provided to the data input of a latch 627. A NAND gate 621 combines the outputs of filters 160 and 170 to produce the control (G) input for latch 627. The Q output of latch 627 forms the output of interrupt latch 180. System interrupt filter 190 includes two D-type flip-flops identified by reference numerals 631 and 633. Each of flip-flops 631 and 633 has its preset input connected to reference voltage VDD, its clear input connected to receive the processor reset signal, and its clock input connected to receive the system clock signal. The output of interrupt latch 180 is provided to the data input of flip-flop 631 and the Q output of flip-flop 631 is connected to the data input of flip-flop 633. The Q output of flip-flop 633 forms the system interrupt signal. Interrupt filters 160 and 170 operate to enable latch 627 to hold the system interrupt signal constant during updating of the contents of the independent interrupt and group interrupt control registers, respectively. The output of filter 160 is immediately set low, operating latch 627 to hold its output constant, when the write interrupt mask1 signal provided to the clear inputs of flip-flops 602 and 604 is set low. The write interrupt mask1 signal is set low during updating of the contents of control register 430. Group interrupt filter 170 operates latch 627 to hold its output constant whenever the write group mask2 is set low. The write group mask2 signal is set low during updating of the contents of control register 530. Interrupt filters 160 and 170 also sychronize the latch control signal to the system clock, and extend the period of the latch operation for a minimum of one clock cycle after the mask signal is returned to a high state to prevent any interrupt glitches that could be generated during control register updating. System interrupt filter 190 is provided to synchronize the output of latch 627 to the system clock and remove the asynchronous aspect of the output of latch 627 which could result in latch metability. It can thus be seen that there has been provided by the present invention a simple method and apparatus for combining the interrupt signals received from the individual disks included in disk array. Disk interrupt signals can be masked individually, permitting selected interrupt signals to pass to the system or controller processor, or interrupt signals can be grouped, such as to generate a signal to inform the processor that the array has completed an operation. The apparatus provides grouping and masking without software assist and can be reconfigured easily to accommodate changes in the array. Those skilled in the art will recognize that the invention is not limited to the specific embodiments described above and that numerous modifications and changes are possible without departing from the scope of the present invention. For example, the architecture shown can be modified to accommodate a disk array having more or less than the five channels shown.

Claims: Apparatus for generating a system interrupt signal for a storage disk array, said disk array including a plurality of interrupt signal sources, characterized by first combining means (140) adapted to combine a first group of selected interrupt signals to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; second combining means (120) adapted to combine a second group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second group has a second binary value; and third combining means (180,190) adapted to combine said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal and said independent interrupt signal has a first binary state and having a second binary state when both said group interrupt signal and said independent interrupt signal have a second binary state. Apparatus according to claim 1, characterized in that said first combining means (140) includes a plurality of first gates (521-525) corresponding respectively to said interrupt sources, each of said first gates (521-525) having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a mask code; and a second gate (540) connected to receive the outputs of said first gates (521-525), the output of said second gate (540) providing said group interrupt signal; in that said second combining means (120) includes a plurality of third gates (421-425) corresponding respectively to said interrupt sources, each one of said plurality of third gates (421-425) having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a mask code; and a fourth gate (450,460) connected to receive the outputs of said plurality of third gates (421-425), the output of said fourth gate (450,460) providing said independent interrupt signal; and in that said third combining means (180,190) includes a fifth gate (623) having a first input connected to receive said group interrupt signal and a second input connected to receive said independent interrupt signal, the output of said fifth gate (623) determining said system interrupt signal. Apparatus according to claim 2, characterized in that said third combining means includes synchronizing means (190) responsive to the output of said fifth gate (623) and a system clock signal and adapted to synchronize said system interrupt signal to said system clock signal. Apparatus according to claim 3, characterized in that said synchronizing means (190) includes a D-type flip-flop (631) having its data input responsive to the output of said fifth gate (623) and its clock input connected to receive said system clock signal. Apparatus according to any one of claims 2 to 4, characterized in that first combining means (140) includes first masking means (530) connected to said first gates (521-525) for selecting said first group of interrupt signals in accordance with said first mask code; and in that said second combining means (120) includes second masking means (430) connected to said third gates (421-425) for selecting said second group of interrupt signals in response to said second mask code. Apparatus according to claim 5, characterized in that said third combining means includes latching means (627) responsive to the output of said fifth gate (623) for latching said system interrupt signal during updating of said first and second mask codes. Apparatus according to claim 6, characterized in that said latching means includes storage means (160,170) connected to receive a first write mask signal associated with the updating of said first mask code and a second write mask signal associated with the updating of said second mask code to generate a latch enable signal, said latch enable signal having a first binary state when any one of said first or second write mask signals has a first binary state; and a latch (627) having its data input connected to the output of said fifth gate (623) and its enable input connected to receive said latch enable signal. A method for generating a system interrupt signal for a storage disk array, said disk array including a plurality of interrupt signal sources, characterized by the steps of: combining a first group of selected interrupt signals provided by said interrupt signal sources to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; combining a second group of selected interrupt signals provided by said interrupt signal sources to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second group has a second binary value; and combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal and said independent interrupt signal has a first binary state and having a second binary state when both said group interrupt signal and said independent interrupt signal have a second binary state. A method according to claim 8, characterized by the step of synchronizing said system interrupt signal with a system clock signal.

Inventors: JIBBE MAHMOUD K, MCCOMBS CRAIG C, JIBBE, MAHMOUD K., MCCOMBS, CRAIG C.
Applicants: HYUNDAI ELECTRONICS AMERICA, NCR INT INC, SYMBIOS LOGIC INC, NCR INTERNATIONAL, INC., SYMBIOS LOGIC INC.
Application year: 1992
Main classification: G06F3
IPC codes: G06F13, G06F9, G06F3