Non-volatile semiconductor memory device

Abstract: In collectively and electrically erase a plurality of memory cells, to set the threshold values of the memory cells constant, electrons are previously stored in the floating gates of the memory cells (M₁₁-M lm ) (S1). The memory cells whose floating gates are accumulated with electrons are electrically erased and the threshold value of each erased memory cell is checked. The collective erasing of the memory cells is repeated until the threshold values of all the memory cells become equal to or below a first value (V EV ) (S2-S9). When it is detected that the threshold values of the memory cells become equal to or below the first value (V EV ), it is discriminated if those threshold values are equal to or above a second value (V TN (E) min ) smaller than the first value (S10-S15). When there is a memory cell whose threshold value is equal to or below a minimum value (V TN (E) min ) allowable on the design base in the previous discrimination step, that memory cell is over-erased and the memory chip containing the memory cell is determined as a defect (S12).

Description: The present invention relates to a non-volatile semiconductor memory device essentially comprising MOSFET's, and, more particularly, to an electrically erasable and programmable non-volatile semiconductor memory device (hereinafter called "EEPROM"). Fig. 1 shows an example of the structure of a conventional collectively-erasable EEPROM (hereinafter referred to as "flash EEPROM". Referring to Fig. 1, a memory cell block MX has memory cells (M 11 , ..., M 1m , ... M l1 , ..., and M lm ) arranged in a matrix. A Y selector group YS comprises switches each of which connects a selected one of digit lines (D 1 , ..., and D l ) to an sense amplifier SA and a write circuit WC. Those switches respectively consist of N-channel, enhancement type MOSFET's (NE-MOSFET's) Q Y1 to Q Yl that are connected between a node SB and the associated digit lines D 1 to D l . Y address lines Y 1 to Y l are connected to output terminals of a Y decoder (referred to as "Y-DEC" (not shown)) to specify the Y addresses of the memory cells. X address lines W 1 to W m are connected to output terminals of an X decoder (referred to as "X-DEC" (not shown)) to specify the X addresses of the memory cells. The sources of the memory cells M 11 , ..., M lm , ..., M l1 , ..., and M lm are commonly connected to a node SS. Also connected to the node SS is an output terminal of an erase control circuit ERC. The write circuit WC electrically writes data in a selected memory cell, while the sense amplifier SA amplifies data stored in the selected memory cell. An input/output (I/O) buffer I/OB sends write data, supplied from an input/output (I/O) terminal I/OT, to the write circuit WC in write mode, and outputs data, supplied from the sense amplifier SA, to the I/O terminal I/OT. It is known that an actual flash EEPROM includes multiple circuits of the type shown in Fig. 1 (for example, 16 circuits for a 16-bit parallel input/output). For diagram's sake, however, Fig. 1 shows only one of the circuits. In the following description, it is defined that a memory cell, which has been electrically erased or has no electrons injected in its floating gate, is storing "1" and the threshold value of such a memory cell is expressed as V TM (E), and that a memory cell, which has been electrically programmed or has electrons injected in its floating gate, is storing "0" and the threshold value of such a memory cell is expressed as V TM (W). Further, the threshold values of NE-MOSFET's are the same and are expressed as V TN . Referring now to Fig. 2 and Table 1 below, a description will be given of the operations of a flash EEPROM in individual modes in the case where the memory cell M 11 is selected by the address signal. Table 1 gives voltages applied to the main nodes and the signal lines in individual modes. (1) Write Mode This mode is to write data "0" into a memory cell (or to charge the floating gate with electrons). A high voltage V PP is applied to the selected X address line W 1 and 0 V to the non-selected X address lines W 2 -W m , while V PP is applied to the selected Y address line Y 1 and 0 V to the non-selected Y address lines Y 2 -Y 1 . The common source SS is applied with 0 V. When data "0" is supplied to the I/O terminal I/OT, the write circuit WC becomes active so that a high voltage V PP appears at the output terminal. Consequently, a high voltage (V PP - V TN ) is applied to the selected digit line D 1 , injecting electrons into the floating gate of the memory cell M 11 . This raises the threshold value of the memory cell M 11 to V TM (W). The threshold value V TM (W) is generally designed higher than the power supply voltage V CC . When data "1" is supplied to the I/O terminal I/OT, on the other hand, the write circuit WC becomes inactive so that the selected digit line D 1 is discharged via the memory cell M 11 to have 0 V. Accordingly, no electrons will be injected to the floating gate of the memory cell M 11 . (2) Erase Mode This mode is to electrically erase a memory cell (or to discharge the electrons accumulated into the floating gate). This mode includes a block erase mode to collectively and electrically erase some memory cells on a chip and a chip erase mode to electrically erase the whole memory cells on the chip. The following will describe how to electrically erase the whole memory cells included in the cell array MX shown in Fig. 1. Before the erase mode is set, data "0" is written in the all memory cells. Then, 0 V is applied to the all the X address lines W 1 -W m and all the Y address lines Y1-Yl, and a high voltage V PP to the common source SS. As a result, every NE-MOSFET included in the Y selector YS is turned off, causing all the memory cells to be turned off. The electrons stored in the floating gate of each memory cell are discharged to the source. This drops the threshold value of each memory cell to V TM (E). In general, V TM (E) is designed lower than the power supply voltage V CC . (3) Read Mode This mode is to read out the contents of a memory cell. The power supply voltage V CC is applied to the selected X address line W 1 and 0 V to the non-selected X address lines, while V CC is applied to the selected Y address line Y 1 and 0 V to the non-selected Y address lines. The sense amplifier SA outputs a predetermined bias voltage, e.g., 1.5 V, to bias the digit line D 1 , connected to the selected memory cell M 11 , via a switch Q Y1 . The common source SS is applied with 0 V. With the memory cell M 11 electrically programmed ("0" stored in that cell), the memory cell M 11 becomes non-conductive due to the threshold value V TM (W) of the memory cell M 11 designed higher than V CC . The sense amplifier SA detects the status of the memory cell M 11 and sends "0" to the I/O terminal I/OT. With the memory cell M 11 electrically erased ("1" stored in that cell), the memory cell M 11 becomes conductive due to the threshold value V TM (W) of the memory cell M 11 designed higher than V CC . The sense amplifier SA detects the status of the memory cell M 11 and sends "1" to the I/O terminal I/OT. (4) Write Verify Mode This mode is to check if writing data "0" into a memory cell has been successful or check if the threshold value V TM (W) becomes higher than the power supply voltage V CC . A program verify voltage V PV is applied to the selected X address line W 1 , and the other nodes and signal lines are applied with the same voltages as done in the read mode. Assuming that V PV = 7 V , when the threshold value of the electrically-programmed memory cell M 11 is lower than 7 V (e.g., V TM (W) = 6 V ), the memory cell M 11 becomes conductive. The sense amplifier SA detects it and outputs "1" to the I/O terminal I/OT, indicating that the data writing to the memory cell is insufficient. When the threshold value of the memory cell M 11 is higher than 7 V (e.g., V TM (W) = 7.5 V ), on the other hand, the memory cell M 11 becomes non-conductive. The sense amplifier SA detects it and outputs "0" to the I/O terminal I/OT, indicating that the data writing to the memory cell is complete. (5) Erase Verify Mode This mode is to check if electric erasing of a memory cell has succeeded or check if the threshold value V TM (W) becomes lower than the power supply voltage V CC . For instance, when the memory cell M 11 is selected by the address signal after erasing is complete, an erase verify voltage V EV is applied to the selected X address line W 1 , and the other nodes and signal lines are applied with the same voltages as done in the read mode. Assuming that V EV = 3.5 V , when the threshold value of the memory cell M 11 is higher than 3.5 V (e.g., V TM (E) = 4 V ), the memory cell M 11 becomes non-conductive. The sense amplifier SA detects it and outputs "0" to the I/O terminal I/OT, indicating that the memory cell has not been erased sufficiently. When the threshold value of the memory cell M 11 is lower than 3.5 V (e.g., V TM (E) = 3 V), on the other hand, the memory cell M 11 becomes conductive. The sense amplifier SA detects it and outputs "1" to the I/O terminal I/OT, indicating that electrical erasing of the memory cell is complete. The erase mode and erase verify mode are generally performed as a sequential operation. Fig. 3 presents a flowchart illustrating this sequential operation. This flowchart is extracted from Fig. 3 in IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989, pages 1259-1263, "A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory." Fig.2 exemplifies a conventional X decoder X-DEC. In Fig. 2, the signal line VW is applied with the high voltage V PP in write mode and erase mode, with the power supply voltage V CC in read mode, with the verify voltage V PV in write verify mode, and with the erase verify voltage V EV in erase verify mode, as apparent from Table 1. As also apparent from Table 1, the signal line B(W+V) is applied with the power supply voltage V CC in write mode and with 0 V in the other modes. An address and a signal ER, which becomes "H" (high) only in erase mode and "L" (low) otherwise, are input to a NOR circuit NOR1. The reference symbol "Q X1 " denotes an N-channel depletion MOSFET (ND-MOSFET), and the reference symbols "Q X2 ," "Q X4 ," "Q X12 ," "Q X22 " and "Q Xn2 " denote P-channel enhancement MOSFET's (PE-MOSFET's) whose substrates are connected to the signal line VW. The reference symbols "Q X3 ," "Q X11 ," "Q X13 ," "Q X21 ," "Q X23 ," "Q Xn1 " and "Q Xn3 " denote N-channel enhancement MOSFET's (NE-MOSFET's). Unless otherwise specified, the substrates of the NE-MOSFET's are connected to the ground line (GND). Let us assume that the threshold value (V TD ) of the ND-MOSFET is set to V TD = -2.5 V . Referring to Fig. 2 and Table 1, the operation of the conventional X decoder will be described below. Suppose that all the address signals input to the NOR circuit NOR1 have become "L" to select the illustrated X decoder and the X address line W 1 has been selected by the signal lines X 1 , BX 1 , X 2 , BX 2 , ..., X n and BX n . (1) Write Mode The signal lines are set as follows: VW = V PP , B(W+V) = 0 V , X 1 = V PP , X 2 to X n = 0 V , BX 1 = 0 V and BX 2 to BX n = V PP . Further, the power supply voltage V CC is applied to the node XA, and the absolute value of the threshold value of the ND-MOSFET Q X1 , 2.5 V, is applied to the node XB. An inverter which is constituted of the MOSFET's Q X2 and Q X3 inverts the voltage at the node XA and applies 0 V to the node XC, turning on the MOSFET Q X4 . The MOSFET's Q X11 and Q X12 are turned on, and the MOSFET's Q X21 , Q X22 , ..., Q Xn1 and Q Xn2 are rendered non-conductive. As the MOSFET Q X13 is non-conductive and the MOSFET's Q X23 , ..., and Q Xn3 are conductive, the voltages at the nodes XB and X D1 rise from 0 V to V PP . The nodes X D2 to X Dn are discharged to 0 V by the MOSFET's Q X23 to Q Xn3 , respectively. Therefore, the high voltage V PP is applied to the selected X address line W 1 , and 0 V to the non-selected X address lines W 2 to W n . (2) Erase Mode The signal lines are set as follows: VW = V PP , B(W+V) = 0 V , X 1 to X n = 0 V , and BX 1 to BX n = V PP . The nodes XA and XB are discharged to 0 V, and the nodes X D1 , X D2 , ..., and X Dn are discharged via the MOSFET's Q X13 , Q X23 , ..., Q Xn3 , respectively, setting the all the X address lines W 1 , W 2 , ..., and W n to 0 V. (3) Read Mode The signal lines are set as follows: VW = V CC , B(W+V) = V CC , X 1 = V CC , X 2 to X n = 0 V , BX 1 = 0 V and BX 2 to BX n = V CC . The MOSFET's Q X11 and Q X12 are turned on, and the MOSFET Q X13 is turned off as in the write mode, so that power supply voltage V CC is applied to the selected X address line W 1 . (4) Write Verify Mode The signal lines are set as follows: VW = V PP , B(W+V) = 0 V , X 1 = V CC , X 2 to X n = 0 V , BX 1 = 0 V and BX 2 to BX n = V CC . The power supply voltage V CC is applied to the node XA. As the absolute value of the threshold value of the ND-MOSFET Q X1 is 2.5 V, the node XB is charged to 2.5 V. When the voltage at the node XC is changed to 0 V, the MOSFET Q X4 is turned on. Then, the voltage at the node XB rises to the write verify voltage V PV . The MOSFET's Q X11 and Q X12 are turned on, and the MOSFET's Q X21 , Q X22 , ..., Q Xn1 and Q Xn2 are turned off. Therefore, the write verify high voltage V PV is applied to the selected X address line W 1 , and 0 V to the non-selected X address lines W 2 to W n . (5) Erase Verify Mode The signal lines are set as follows: VW = V EV , B(W+V) = 0 V , X 1 = V CC , X 2 to X n = 0 V , BX 1 = 0 V and BX 2 to BX n = V CC . Therefore, the read verify voltage V EV is applied to the selected X address line W 1 , and 0 V to the non-selected X address lines W 2 to W n . A change in the threshold value of a memory cell in erase mode will now be explained in detail. As mentioned earlier, erasing a memory cell is executed in the sequence illustrated in Fig. 3. In general, a plurality of memory cells are electrically and collectively erased using an erase pulse signal as short as 10 µs. Then, it is checked if erasing each memory cell is complete. If there is any memory cell whose erasing is not completed, erasure and verification are repeated. If there is even one memory cell whose erasing speed is slow, all of the other memory cells are repeatedly erased, lowering the threshold value V TM (E). Fig. 4 illustrates the relationship between the cumulative value tPe of the applying time of the erase pulse that is applied to the memory cells and the threshold value V TM (E) of the memory cells for the memory cell having the fastest erasing speed (characteristic Q), the memory cell having the slowest erasing speed (characteristic P), and the memory cell whose erasing speed become abnormally fast due to a variation in the manufacturing process (characteristic R). When the cumulative time for the erase pulse is t1, the threshold value of the memory cell having the lowest erasing speed is higher than the erase verify voltage V EV as shown by the characteristic P, so that erasing and verifying the memory cells will be further repeated. At the cumulative time t2, even the threshold value of the memory cell having the lowest erasing speed becomes lower than the erase verify voltage V EV . Accordingly, it is detected that erasing all the memory cells has been completed. At this time, the threshold value of the memory cell having the lowest erasing speed is about 2.0 V as shown by the characteristic Q. The threshold value of the memory cell whose erasing speed is abnormally fast is abnormally dropped to 0.5 as shown by the characteristic R. When the threshold value of the memory cell falls further to take a negative value, this memory cell is rendered conductive even when it is not selected. As a result, the flash EEPROM will malfunction. The flash EEPROM should therefore fulfill the requirement that the threshold value V TM (E) of the memory cell having the highest erasing speed does not become equal to or below 0 V when erasing the memory cell having the lowest erasing speed is completed. A phenomenon that a non-selected memory cell is rendered conductive by the parasitic capacitance between the drain and floating gate of the memory cell is a factor to determine the lower limit of the threshold value V TM (E) of the erased memory cell. This phenomenon will be described below. Fig. 5 is a cross section of a memory cell of a flash EEPROM. A control gate CG is connected to the X address line. Fig. 6 shows an equivalent circuit of the capacitance component accompanying the memory cell shown in Fig. 5. In Fig. 6, C CF represents the capacitance between the control gate CG and the floating gate FG, C FD represents the capacitance between the floating gate FG and the drain D, and C FS represents the capacitance between the floating gate FG and the source S. As shown in Fig. 6, the floating gate FG is capacitively coupled to the drain D and source S through a tunnel oxide film TI, and is capacitively coupled to the control gate CG through an interlayer insulating film IV (the P substrate is set to 0 V). Thus, the voltage V FG of the floating gate FG when a voltage V CG is applied to the control gate CG is given by an equation 1, and the voltage V FG of the floating gate FG when a voltage V D is applied to the drain D is given by an equation 2. V FG = (C CF x V CG )/(C FS + C FCC + C FD + C CF ) V FG = (C FD x V D )/(C CF + C FS + C FCC ) Given that C CF = 5.0 x 10 -3 PF , C FS = 2.0 x 10 -3 PF , C FD = 1.0 x 10 -3 PF , and C FCC = 2.0 x 10 -3 PF , an equation 3 below is derived from the equation 1, and an equation 4 below from the equation 2. V FG = 0.5 x V CG V FG = 0.1 x V D It is apparent from that the influence of the voltage V D of the drain on the voltage V FG of the floating gate is 1/5 of the influence of the voltage V CG of the control gate on the voltage V FG of the floating gate. On the assumption that the drain voltage V D in write mode is set to 5 V, a description will be given of how a non-selected memory cell is rendered conductive by the parasitic capacitance between the drain and floating gate of the memory cell, referring to Figs. 1 and 5 to 7. In writing data in the memory cell M 11 , 5 V is applied to the digit line D 1 , a high voltage V PP to the X address line W 1 , and 0 V to the other X address lines. Thus, 5 V is applied to the drain D of a memory cell other than M 11 and connected to the digit line D 1 , e.g., M 1m , and 0 V is applied to the control gate CG and source S of that memory cell M 1m . It is apparent from the equations 3 and 4, that 5 V applied to the drain D is equivalent to 1 V applied to the control gate CG. When the threshold value of the memory cell M 1m is 1 V or below, the memory cell M 1m becomes conductive even through 0 V is applied to the control gate CG. Fig. 7 illustrates the relationship between the drain voltage V D of a non-selected memory cell and the drain current I D . With the threshold value of the non-selected memory cell being 1 V, the drain voltage V FD when the non-selected memory cell is turned on is 5 V. When any non-selected memory cell is turned on, the voltage of the selected digit line drops, so that the writing speed may become slow or writing may not be possible. To avoid such a problem, it is essential to check if the threshold value of an erased memory cell does not cause the non-selected memory cell to be turned on due to C FD . Conventionally, however, no measures have been taken to check if the threshold value of an erased memory cell is below the lower limit. In short, in erasing the conventional flash EEPROM, if there is any memory cell whose erasing is not completed, all the memory cell are erased. If there is even one memory cell whose erasing speed is abnormally fast due to a variation in the fabrication process or some other reasons, therefore, the threshold value may become negative, causing that memory cell to be always turned on. Even when the threshold value does not become negative, a non-selected memory cell connected to the selected digit line may be turned on, slowing the writing of the selected memory cell or disabling the writing. GB-A-2215155 discloses a further flash EPROM/EEPROM-device and a program/erase selection for such flash memory. On the other hand, US-A-4841482 wherein the preamble of claim 1 is bared, discloses a circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having a floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode. It is therefore an object of the present invention to provide a highly reliable memory cell. It is an advantage of the present invention to provide an EEPROM capable of checking if the threshold value of an erased memory cell is below a predetermined lower limit. The above object is achieved by a semiconductor memory device according to claim 1. The claims are related to different advantageous aspects of the present invention. It is a further advantage of the invention to provide a method of checking if an EEPROM contains any memory cell whose threshold value, after erasure, is below a predetermined lower limit, and removing that EEPEOM as a defect if such cell exists. With this invention, it is possible to check if the threshold value of an erased memory cell is equal to or greater than a predetermined value. Thus, a chip containing a memory cell, which has been over-erased to have its threshold value abnormally low, can be removed as a defect. Fig. 1 is a block diagram illustrating the structure of a conventional EEPROM; Fig. 2 is a circuit diagram showing the structure of a conventional X decoder; Fig. 3 is a flowchart illustrating an erasure operation for the conventional EEPROM; Fig. 4 is a graph showing the relationship between the cumulative value tPe of the applying time of an erase pulse and the threshold value of memory cells; Fig. 5 is a cross section of a memory cell of a flash EEPROM; Fig. 6 shows an equivalent circuit of the capacitance that accompanies a memory cell; Fig. 7 is a graph illustrating the relationship between the drain voltage and drain current of a non-selected memory cell; Fig. 8 is a circuit diagram showing the structure of an X decoder according to a first embodiment of the present invention; Fig. 9 is a block diagram showing the structure of a flash EEPROM according to the first embodiment of this invention; Fig. 10 is a circuit diagram showing one example of a margin check voltage generator shown in Fig. 9; Fig. 11 is a circuit diagram showing another example of the margin check voltage generator; Fig. 12 is a timing chart for explaining the operation of the flash EEPROM in erase margin check mode; Fig. 13 is a timing chart for explaining the operation of the flash EEPROM in erase mode; and Fig. 14 is a circuit diagram showing the structure of an X decoder according to a second embodiment of this invention. Preferred embodiments of the present invention will now be described referring to the accompanying drawings. Fig. 8 illustrates the structure of an X decoder according to the first embodiment of the present invention. This X decoder is the conventional X decoder in Fig. 2 to which a margin check voltage application control circuit MCC is added. Like or same reference numerals and symbols as used in Fig. 2 are also used in Fig. 8 to avoid repeating their explanation. The control circuit MCC outputs a voltage equal to a lower limit V MC of the threshold value, determined by the designing of memory cells, to a node XS in erase margin check mode. The erase margin check mode is characterizing this embodiment and is to check if the threshold value of an erased memory cell is higher than the lower limit V MC that is determined by the designing of memory cells. The control circuit MCC comprises PE-MOSFET's Q M1 and Q M3 , and NE-MOSFET's Q M2 , Q M4 , Q M5 and Q M6 . A signal line EV 2 is connected to a first inverter comprising the MOSFET's Q M1 and Q M2 . Applied to this signal line EV 2 is a signal, which becomes a high level in erase margin check mode and a low level otherwise. The output of the first inverter is supplied to a second inverter, which comprises the MOSFET's Q M3 and Q M4 , and the gate of the MOSFET Q M6 . The output of the second inverter is supplied to the gate of the MOSFET Q M5 . The NE-MOSFET Q M5 has a drain connected to a signal line MC and a source connected to both the node XS and the gate of the NE-MOSFET Q M6 . Applied to the signal line MC is V TM (E)min = V MC , the lower limit of the threshold value of an erased memory cell, which is determined by the cell design. The node XS is connected to the sources of NE-MOSFET's Q X13 , Q X23 , ..., and Q Xn3 that pull down X address lines W 1 to W m . Fig. 9 shows the structure of a flash EEPROM according to the first embodiment. This flash EEPROM is constructed by adding the aforementioned margin check voltage application control circuit MCC and a margin check voltage generator MCG for generating the mentioned margin check voltage V MC to the conventional type in Fig.1. Figs. 10 and 11 illustrate examples of the margin check voltage generator MCG. Referring to Fig. 10, a PE-MOSFET Q MC1 is connected between the power supply voltage V CC and the signal line MC, and has a gate supplied with a signal BCel, which becomes a high level in standby mode and a low level otherwise. An NE-MOSFET Q MC2 has its drain and gate connected to the signal line MC, with its source grounded. To reduce the dependency of the margin check voltage V MC on the power supply voltage V CC , the current driving ability of the NE-MOSFET Q MC2 is designed to be sufficiently larger than that of the PE-MOSFET Q MC1 . Given that the threshold value of the NE-MOSFET Q MC2 is V TN2 , the margin check voltage V MC is approximately equal to V TN2 . By properly setting the threshold value V TN2 of the NE-MOSFET Q MC2 , therefore, the margin check voltage V MC can be set to the lower limit V TM (E)min that is determined by the designing of memory cells. Fig. 11 illustrates an example of the margin check voltage generator MCG in the case where the voltage of the signal line MC is controlled by a voltage supplied outside the chip. This example is not covered by the present invention. The margin check voltage V MC is applied to a terminal V PP at the stage of checking the functions of the chip, and the high voltage V PP is applied there in the other modes. The operation of the X decoder according to this example will be described referring to Figs. 8, 10 and 12 and Table 2 below. Fig. 12 shows changes in voltages of the signal lines and the nodes in erase margin check mode. Table 2 shows voltages of the individual sections in each mode of the flash EEPROM according to this embodiment. Since the voltage of the signal line EV 2 is set to a low level in other modes than the erase margin check mode, the NE-MOSFET Q M5 is turned off and the MOSFET Q M6 is turned on. Consequently, 0 V is applied to the node XS, allowing the X decoder in Fig. 8 to operate in the same fashion as the conventional X decoder in Fig. 2. In erase margin check mode, the voltage settings are VW = V CC , B(W+V) = V CC , X 1 to X n = 0 V and BX 1 to BX n = V CC . Further, the power supply voltage V CC is applied to the selected Y address line Y 1 , and 0 V to the non-selected Y address lines. Assuming that the threshold value of the MOSFET Q MC2 , V TN2 , is designed to 1 V, the voltage V MC of the signal line MC becomes 1 V. When the mode becomes the erase margin check mode, the voltage of the signal line EV 2 changes to a high level from the low level. This turns on the MOSFET Q M5 and turns off the MOSFET Q M6 , so that the voltage at the node XS changes to 1 V from 0 V. The MOSFET's Q X11 , Q X12 , Q X21 , Q X22 , ..., Q Xn1 , and Q Xn2 are all turned off, and MOSFET's Q X13 , Q X23 , ..., and Q Xn3 are all turned on. This causes all the voltages at the nodes X D1 , X D2 , ..., and XD n to be V MC (= 1 V), so that the X address lines W 1 , ..., and W n all become 1 V. Therefore, 1 V is applied to the control gates CG of all the memory cells M 11 , ..., and M lm connected to the selected digit line D 1 . If the threshold value of the memory cell M 11 is lower than 1 V, the MOSFET Q M11 becomes conductive, and the sense amplifier SA detects this event and outputs "0" to the I/O terminal I/OT. As a result, it is detected that there is at least one over-erased memory cell among those connected to the digit line D 1 whose threshold value is lower than the lower limit V TM (E)min. By carrying out the above-described operation for each digit line (by switching the NE-MOSFET's Q Y1 , ..., and Q Yl of the Y selector group), it is possible to check if the threshold values of the all the memory cells are equal to or above the lower limit V TM (E)min that is determined by the cell design. When this operation is performed on finished memory chips at a final stage of a manufacturing process, a chip having an over-erased memory cell can be removed as a defect. The flash EEPROM according to this embodiment can be set to the erase margin check mode as well as the normal erase mode and erase verify mode. The erasure, the erase verify and erase margin check are thus performed as one sequence. Fig. 13 presents a flowchart for this sequential operation, and is the flowchart in Fig. 3 to which steps for the erase margin check are added. The operation of the flash EEPROM of this embodiment in erase mode will now be described referring to Fig. 13. First, to set the threshold values of the memory cells constant, data "0" is written in every memory cell (S1). Then, the erase mode is set to collectively and electrically erase the memory cells in the chip (S2). Then, the erase verify mode is set (S3), and data stored in the memory cells are read out in order (S4-S9). When an insufficiently-erased memory cell is found, the memory cells are collectively erased again (S7, S2-S9). The above erasing operation and verifying operation are repeated until the completion of erasing all the memory cells is detected. When erasing all the memory cells is detected (YES in S8), the erase margin check mode is set (S10). In this mode, as described earlier, the margin check voltage V MC is applied to all the word lines W 1 -W n , and the MOSFET's Q Y1 -Q Yl are sequentially turned on to select the digit lines D 1 -D l in order (S11-S14). If there is any over-erased memory cell (one having the characteristic R in Fig. 4), that memory cell will become conductive. The sense amplifier SA detects this event and outputs "1" to the I/O terminal I/OT. The chip containing such an over-erased memory cell is discriminated as a defect (S12). If there is no over-erased memory cell, however, all the memory cells remain off, and the sense amplifier SA outputs "0" to the I/O terminal I/OT for all the digit lines. Then, the read mode is set (S15). According to this embodiment, therefore, it is possible to detect a memory chip which contains a memory cell whose erasing speed is abnormally fast due to a variation in the manufacturing process or some other reasons and remove it as a defect. Although a logical gate to which the address is input is a NOR circuit is used in Fig. 8, it may be accomplished by a combination of a NAND circuit and an inverter. A high-voltage supplying circuit 100 is in no way limited to the one shown in Fig. 8, but it may take any structure as long as the circuit can supply a high voltage to the node XB in write mode. While a NE-MOSFET and a PE-MOSFET are connected in parallel, like the MOSFET's Q X11 and Q X12 , in Fig. 8, the NE-MOSFET or PE-MOSFET may be used alone. Fig. 14 illustrates an X decoder according to the second embodiment of the present invention. This X decoder has the structure in Fig. 3 to which NE-MOSFET's Q X14 , Q X24 , ... and Q Xn4 are added. The gates of the NE-MOSFET's Q X14 , Q X24 , ... and Q Xn4 are connected to the signal line EV 2 , which becomes a high level in erase margin check mode and a low level otherwise. Those MOSFET's Q X14 , Q X24 , ... and Q Xn4 have their sources applied with the margin check voltage V MC and their drains respectively connected to X address lines W 1 -W n . The operation of this X decoder will be explained below. In erase margin check mode, the voltage settings are VW = V CC , B(W+V) = V CC , X 1 to X n = 0 V , BX 1 to BX n = V CC , and BA X1 to BA Xn = V CC . Further, the power supply voltage V CC is applied to the selected Y address line, and 0 V to the non-selected Y address lines. In erase margin check mode, the margin check voltage V MC is applied to the signal line MC. When a signal on the signal line EV 2 changes to a high level from a low level, MOSFET's Q X14 , Q X24 , ... and Q Xn4 are all turned on, while the MOSFET's Q X11 , Q X12 , Q X13 , Q X21 , Q X22 , Q X23 , ... Q Xn1 , Q Xn2 and Q Xn3 are all turned off, causing the voltages of all the X address lines W 1 , ..., and W n to become the margin check voltage V MC . It is therefore possible to check if there is a memory cell whose threshold value is lower than the margin check voltage V MC for the individual digit lines. In short, this embodiment can remove a chip, which is likely to slow the writing speed or disable writing due to the over-erasure of memory cells, as a defect at the stage of checking the functions of the chip (e.g., the inspection at the time of factory shipment). It is thus possible to provide highly reliable flash EEPROM's.

Claims: A non-volatile semiconductor memory device comprising: a plurality of memory cells (M 11 -M lm ) each for storing data by a change in a threshold value; a plurality of row address lines (W 1 -W m ); a plurality of digit lines (D 1 -D l ); write means (XDEC, YDEC, Y 1 -Y l , WC) connected to said plurality of memory cells (M 11 -M lm ) for writing predetermined data in a selected memory cell by setting the threshold value of said selected memory cell higher than a predetermined value (V MC ); read means (XDEC, YDEC, Y 1 -Y l ) to read out stored data from said memory cells; means (SA) for sensing and amplifying signals on said digit lines (D 1 -D l ) for outputting said amplified signal; wherein each of the plurality of memory cells (M 11 -M lm ) has a current path, one end of which is connected to an associated one of said digit lines (D 1 -D l ) and has a gate connected to an associated one of said row address lines (W 1 -W m ); erasing means (XDEC, YDEC, Y 1 -Y l , ERC) connected to said plurality of memory cells (M 11 -M lm ) for electrically erasing said plurality of memory cells; and checking means (MCC, MCG, XDEC, YDEC, Y 1 -Y l , SA) connected to said plurality of memory cells (M 11 -M lm ) for checking if the threshold value of those memory cells electrically erased by said erasing means are equal to or greater than a margin check voltage (XS); wherein said margin check voltage (XS) is substantially equal to a minimum value (V TN (E) min ) of threshold values of those of said memory cells which are electrically erased; said checking means (MCC, MCG) applying the margin check voltage (XS) simultaneously to all of said row address lines (W 1 ,.., W m ) to detect whether or not there is an electrically erased memory cell whose threshold value is lower than the margin check voltage (XS), thereby to detect if there is an electrically over-erased memory cell; said checking means comprising a margin check voltage application controlling circuit (MCC) into which the voltage (MC) output from a margin check voltage generating circuit (MCG) is input, and from which said margin check voltage (XS) is output characterized in that said margin check voltage generating circuit (MCG) includes a first MOSFET (Q MC1 ) connected between the power supply voltage (VCC) and the input of said margin check voltage application controlling circuit (MCC) and supplied with a control signal (Bce1), and a second MOSFET (Q MC2 ), the drain and gate of which are connected to said input of said margin check voltage application controlling circuit (MCC), and a source is connected to ground, the threshold voltage (V TN2 ) of the second MOSFET is used to adjust the voltage (MC) output to the margin check voltage application controlling circuit (MCC), thereby adjusting said margin check voltage (XS). The semiconductor memory device according to claim 1, characterized in that the margin check voltage application controlling circuit (MC10) comprises a first N-channel type MOSFET (QM5), the drain thereof being connected to the output (MC) of that margin check voltage generating circuit (MCG), the gate thereof being connected to a signal line which is at "H" during a margin check mode and is at "L" during other modes, the source thereof delivering said margin check voltage (XS) at the output of said margin check voltage application controlling cirucit; and a second N-channel type MOSFET (QM6), the drain thereof being connected to said margin check voltage (XS), the gate thereof being connected to a signal line which is said "L" during the margin check mode and is at "H" during other modes, the source thereof being connected to ground. The semiconductor memory device according to claim 1, characterized in that said read means includes: selecting means (YDEC, Y 1- Y l ) for sequentially selecting said digit lines (D 1 -D l ); and means for applying said margin check voltage (XS) to control gates of said memory cells (M 11 -M lm ) commonly connected to the digit line (D 1 etc.) which is selected by said selecting means to read out stored data from said memory cell, and detecting whether or not there is an electrically erased memory cell whose threshold value is lower than said margin check voltage (XS) in order to detect if there is an electrically over-erased memory cell. The semiconductor memory device according to claim 1, characterized in that said read means includes: selecting means (YDEC, Y 1 -Y l ) for selecting a digit line (D 1 -D l ); and means for applying said margin check voltage (XS) to control gates of said memory cells (M 11 -M lm ) commonly connected to said selected digit line (D 1 etc.) to detect if a voltage on said selected digit line drops. The semiconductor memory device according to claim 1, characterized in that said read means includes: means (XDEC, MCC), connected to said row address lines (W 1 -W m ), for, upon reception an address and said margin check voltage (XS), applying a read voltage (V CC ) to a selected row address line (W 1 etc.) in read mode, applying a write voltage (V PP ) to a selected row address line (W 1 etc.) in write mode, and applying said margin check voltage (XS), supplied from said generating means (MCG), to all of said plurality of row address lines (W 1 -W n ) to detect if there is any electrically over-erased memory cell. The semiconductor memory device according to claim 1, wherein, after electric erasure of said plurality of memory cells (M 11 -M 1m ) by said erasing means is complete, said read means detects whether or not there is an electrically erased memory cell whose threshold value is lower than said margin check voltage (XS) in order to detect if there is an electrically over-erased memory cell. The semiconductor memory device according to claim 5, characterized in that said erasing means includes means (S1-S9) for repeating electric erasure of all of said plurality of memory cells until all the threshold values of said plurality of memory cells become equal to or smaller than a given value.

Inventors: HASHIMOTO KIYOKAZU, HASHIMOTO, KIYOKAZU, HASHIMOTO, KIYOKAZU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G11C16
IPC codes: G11C29, G11C17, G11C16