Semiconductor memory device

Abstract: In a mask ROM, for each of the memory cell groups, a load circuit connected to data lines for the respective memory cell group, a sense amplifier, and a switching circuit are provided. The switching circuit selectively connects one of the data lines which are simultaneously selected, to the sense amplifier. A data line for a dummy memory cell is also connected to the sense amplifier.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a high-speed read mode. 2. Description of the Prior Art: As the processing speed of microprocessors have been remarkably improved in recent years, a semiconductor memory device is increasingly required to operate at a high speed. Accordingly, some improved semiconductor memory devices have been developed (for example, "A 20ns 1Mb CMOS Burst Mode EPROM" by B. ASHMORE et al., 1989 IEEE International Solid-State Circuit Conference). These devices perform the normal random access more rapidly, and have a high-speed read mode. In the high-speed read mode, the read operation can be performed more rapidly, though the access methods are limited somewhat. Figure 5 shows a prior art mask ROM (Read Only Memory) which has such a high-speed read mode. In the mask ROM, one row select line C i is designated by decoding high order bits of an input address. Then, a plurality of transistors Q i0 -Q in in a data line selection circuit 11 are turned on, so as to select a plurality of data lines D i0 -D in , corresponding thereto. Any one column select line W j is designated by decoding low order bits except for the least significant bits of the input address. One row select line C i and one column select line W j are designated, so that a plurality of memory cells 12 are simultaneously selected. The memory cells 12 comprise transistors Q ij0 -Q ijn , respectively. Each of these transistors Q ij0 -Q ijn is a MOSFET, and is formed in a semiconductor fabricating process in such a manner that the threshold voltage thereof is high when storing logical "1", and the threshold voltage becomes similar to that of the normal enhancement type when storing logical "0". Therefore, when one column select line W j is designated to become HIGH, the transistors Q ij0 -Q ijn of memory cells 12 corresponding to the column select line W j are normally off ("1") or normally on ("0"), in accordance with the logic state. When the plurality of transistors Q i0 -Q in in the data line selection circuit 11 are turned on by the designation of the row select line C i , the transistors Q ij0 -Q ijn of memory cells 12 selected by the column select line W j are connected to sense amplifiers 13 , respectively. As a result, the potentials of the data lines D i0 -D in selected by the row select line C i gradually change to HIGH ("1") or LOW ("0"), respectively, in accordance with the logic states of the connected transistors Q ij0 -Q ijn . These weak potentials are amplified by the respective sense amplifiers 13 , in order to be valid. In the normal random access, one of bank select lines P 0 -P n is designated to be HIGH in accordance with the least significant bits of the input address. Thus, only one of transistors Q p0 -Q pn in a switching circuit 14 is turned on through which the output of the sense amplifier 13 connected to the corresponding one of data lines D i0 -D in is sent out to an output buffer 15 . Therefore, in the normal random access, the logic state stored in one memory cell 12 designated by the input address can be read out via the output buffer 15 . When the logic state of memory cell 12 is read out through the corresponding one of the data lines D i0 -D in in this way, also the potentials at the remaining data lines D i0 -D in which are not selected by the switching circuit 14 have already become valid by the respective sense amplifiers 13 . In this condition, when another one of the bank select lines P 0 -P n is switched to be HIGH, the logic state of the corresponding memory cell 12 can be immediately read out without waiting for the potentials of the data lines D i0 -D in to be valid. Therefore, in the high-speed read mode, for example, the least significant bits of the input address are automatically generated by an address counter, etc., so that the bank select lines P 0 -P n are sequentially switched to be HIGH, whereby the transistors Q P0 -Q Pn in the switching circuit 14 are sequentially turned on. Thus, the logic states of a plurality of memory cells 12 are sequentially read out through the plurality of data lines D i0 -D in simultaneously selected by one row select line C i . As shown in Figure 6 , the input address becomes valid at time t 10 . In response to this, one row select line C i and one column select line W j are designated to be HIGH. Then, the data lines D i0 -D in are connected to the respective sense amplifiers 13 , and the potentials of the data lines D i0 -D in change to be valid at time t 11 . Since the bank select line P 0 has been designated to be HIGH at this time, the output of the sense amplifier 13 connected to the data line D i0 is sent out to the output buffer 15 . Next, the bank select line P 1 is switched to be HIGH at time t 12 , and the output of the sense amplifier 13 connected to the data line D i1 is sent out to the output buffer 15 . Thereafter, the bank select lines P 2 -P n are sequentially switched to be HIGH, so that the outputs of the sense amplifiers 13 connected to the corresponding data lines D i2 -D in are sent out to the output buffer 15 . As a result, the reading from the first memory cell 12 comprising the transistor Q ij0 requires the time period of t 11 -t 10 which continues until the potential of the data line D i0 becomes valid, as in the normal random access. On the contrary, since the potentials of the data lines D i1 -D in simultaneously selected are already valid, the logic states of the corresponding memory cells 12 respectively comprising transistors Q ij1 -Q ijn can be immediately read out by switching the bank select lines P 1 -P n in the succeeding readings. However, in the above-mentioned prior art semiconductor memory device, it is required to provide the sense amplifiers 13 respectively on all data lines D i0 -D in which are simultaneously selected by one row select line C i , in order to set a high-speed read mode. Therefore, as the number of bits which can be simultaneously read out for a high speed reading increases, the number of sense amplifiers 13 must be increased. This causes the occupied area on a chip and the power consumption to increase. Therefore, the prior art semiconductor memory device with a high-speed read mode has a problem in that if the number of bits which are simultaneously read out increases, the chip area and the power consumption increase. SUMMARY OF THE INVENTION The semiconductor memory device according to this invention, which overcomes the above-discussed and numerous other disadvantages and deficiencies of the prior art is defined in independent claims 1 and 3. In a preferred embodiment, said load circuit comprises transistors each connected to said data lines. In a preferred embodiment, said memory cells includes at least one dummy memory cell for each of said memory cell groups. In a preferred embodiment, a dummy data line for said dummy cell is connected to one input of said sense amplifier, and others of said data lines are connected to another input of said sense amplifier through said switching circuit. In a preferred embodiment, an equalizing circuit is connected between said dummy data line and said data lines. In a preferred embodiment, when an address becomes valid, said equalizing circuit connects said dummy data line with said data lines for predetermined period of time. According to the above configuration, when a plurality of memory cells are simultaneously selected by the designation of one row select line and one column select line, the potentials of the data lines connected to these memory cells gradually change by the respective load circuits in accordance with the on/off states of the respective memory cells. After the potentials of the data lines become valid, the data lines are selectively connected to the sense amplifier by the switching circuit. Thus, for the readout of the first memory cell, it requires a time period until the potential of the data line becomes valid. However, thereafter, for the readout of the other memory cells which are simultaneously selected, since the potentials of the data lines are already valid, the readout can be immediately performed by amplifying in the sense amplifier. Since the sense amplifier is constituted by a complicated circuit such as a differential amplifier circuit, the sense amplifier occupies a large area on a chip and the power consumption is large. On the other hand, the load circuit has a simple configuration in which, for example, one transistor is provided for each data line, so that the occupied area and the power consumption are small. According to the semiconductor memory device of the invention, a sense amplifier with a complicated configuration can be commonly used for a plurality of data lines, only by providing simple load circuits. Therefore, the chip area and the power consumption can be reduced while the high-speed read mode is provided as in the prior art. Thus, the invention described herein makes possible the objectives of: (1) providing a semiconductor memory device with a high speed read mode which can be manufactured in reduced size; and (2) providing a semiconductor memory device with a high speed read mode which can operate at a reduced power consumption. BRIEF DESCRIPTION OF THE DRAWINGS This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1 is a block diagram showing the schematic configuration of a mask ROM according to the invention. Figure 2 is a block diagram showing the configuration of the embodiment of Figure 1 in more detail. Figure 3 is a time chart illustrating the potential transition of data lines in the embodiment of Figure 1 . Figure 4 is a time chart illustrating the operation of a high-speed read mode in the embodiment of Figure 1 . Figure 5 is a block diagram showing the configuration of a prior art mask ROM. Figure 6 is a time chart illustrating the operation of a high-speed read mode in the mask ROM of Figure 5 . DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows a mask ROM according to the invention. As shown in Figure 1 , in a mask ROM of this embodiment, memory cells 2 are respectively connected to the crossings of eight data lines D i0 -D i7 and one column select line W j . These data lines D i0 -D i7 are connected to a sense amplifier 3 via a data line selection circuit 1 and a switching circuit 4 . These data lines D i0 -D i7 are also connected to a load circuit 6 via the data line selection circuit 1 . The memory cells 2 comprises transistors Q ij0 -Q ij7 , respectively. When the column select line W j becomes HIGH, the transistors Q ij0 -Q ij7 of memory cells 2 are turned off ("1") or on ("0") in accordance with the logic state previously established in the semiconductor fabrication process. The data line selection circuit 1 comprises transistors Q i0 -Q i7 . When the row select line C i becomes HIGH, all the transistors Q i0 -Q i7 are turned on. In the switching circuit 4 , when one of bank select lines P 0 -P 7 becomes HIGH, the corresponding one of transistors Q P0 -Q P7 is turned on, so as to selectively connect the corresponding one of the data lines D i0 -D i7 with the sense amplifier 3 . The eight data lines D i0 -D i7 shown in Figure 1 constitute one set, and a plurality of such sets are provided, though not shown in the figure. Corresponding to these sets, row select lines C i and data line selection circuits 1 other than those shown in Figure 1 are provided, respectively. When any one row select line C i is designated by decoding high order bits of an input address, one set of data lines D i0 -D i7 is conducted and selected by the corresponding data line selection circuit 1 . A plurality of column select lines W j are provided other than that shown in Figure 1 . When one of the column select lines W j is designated by decoding low order bits except for the least significant bits of the input address, the transistors of the memory cells 2 connected to the respective crossings of the corresponding column select line W j and each of the data lines D i0 -D i7 are turned on/off for selection. Although not shown, a number of memory cells 2 are arranged at the crossings of the respective data lines D i0 -D i7 and the column select lines W j in a two-dimensional matrix. A plurality of switching circuits 4 and sense amplifiers 3 are provided for the respective sets of data lines D i0 -D i7 . When one of the bank select lines P 0 -P 7 is designated by decoding the least significant bits of the low order bits of the input address, the corresponding one of the data lines D i0 -D i7 is connected to the corresponding sense amplifier 3 , as described above. As shown in Figure 2 , a differential amplifier circuit comprising MOSFETs constitutes the sense amplifier 3 . One of the data lines D i0 -D i7 connected by the switching circuit 4 is coupled to one input of the sense amplifier 3 . To the other input of the sense amplifier 3 , is coupled a dummy data line D d (which is omitted in Figure 1 ). The dummy data line D d is connected to a dummy cell 7 provided at the crossing of the column select line W j and the dummy data line D d , and functions as a reference circuit for the sense amplifier 3 . The dummy cell 7 comprises a transistor Q jd which has the same characteristics as those of a transistor in the memory cell 2 storing a logic state of "0". The dummy data line D d is connected to the respective data lines D i0 -D i7 via an equalizing circuit 8 . The equalizing circuit 8 comprises transistors Q E0 -Q E7 . When an equalizing signal EQU becomes HIGH, the transistors Q E0 -Q E7 are turned on, so that the dummy data line D d is connected to the respective data lines D i0 -D i7 . The sense amplifier 3 is disconnected from the power source when a chip enable signal CE is HIGH (i.e., when not active). The load circuit 6 comprises transistors Q Li0 -Q Li7 and Q Ld and a NOR gate 6a . Each of the transistors Q Li0 -Q Li7 and Q Ld is connected between the power source and the corresponding one of the data lines D i0 -D i7 and dummy data line D d . These transistors are in the conductive state when the output of the NOR gate 6a is HIGH. The transistor Q Ld is a MOSFET having the driving current characteristic which is doubled as compared with that of the other transistors Q Li0 -Q Li7 . One input of the NOR gate 6a is coupled to the dummy data line D d . Only when the chip enable signal CE is LOW (active), the NOR gate 6a outputs the inversion of the logic level of the dummy data line D d . The operation of the mask ROM with the above-mentioned configuration will be described by referring Figures 3 and 4 . As shown in Figure 3 , when the input address becomes valid at time t 0 , in response to this, one row select line C i and one column select line W j are designated to be HIGH. Then, the transistors Q ij0 -Q ij7 in memory cells 2 and the transistor Q jd in dummy cell 7 are respectively turned on or off in accordance with the logic state, and the respective transistors Q i0 -Q i7 in the data line selection circuit 1 are turned on. The equalizing signal EQU is set HIGH for a predetermined time period T during which the transistors Q E0 -Q E7 are turned on, whereby the respective data lines D i0 -D i7 and the dummy data line D d are connected so as to equalize the potentials thereof. When the equalizing signal EQU returns to LOW and the transistors Q E0 -Q E7 are turned off after the time period T has elapsed, the potentials of the transistors Q i0 -Q i7 and the dummy data line D d start to change in accordance with the on/off states of the transistors Q ij0 -Q ij7 and Q jd , respectively. In other words, since the dummy cell 7 is in the logic state of "0", the potential of the dummy data line D d changes to the potential V REF at which the charge current of the transistor Q Ld in the load circuit 6 balances with the discharge current of the transistor Q jd in the on state, and then becomes valid. When the logic state of the memory cell 2 is "1", the transistors Q ij0 -Q ij7 are in the off state, and therefore the potentials of the corresponding transistors Q i0 -Q i7 change to the potential V H at which the corresponding transistors Q Li0 -Q Li7 are turned off, and the potentials become valid. Furthermore, when the logic state of the memory cell 2 is "0", the potentials of the corresponding transistors Q i0 -Q i7 change to the potential V L at which the charge currents of the corresponding transistors Q Li0 -Q Li7 balance with the discharge currents of the transistors Q ij0 -Q ij7 in the on state, and the potentials become valid. Since the transistor Q Ld of the dummy cell 7 has the doubled driving current characteristic, the order of these potentials in magnitude is as follows: the potential V H , the potential V REF and the potential V L (V H > V REF > V L ) . After the potentials of the respective data lines D i0 -D i7 and the dummy data line D d become valid in this way, the sense amplifier 3 compares at time t 1 the potential of one of the data lines D i0 -D i7 selected by the switching circuit 4 with the potential of the dummy data line D d , and outputs its result to the output buffer 5 . As described above, in the normal random access, an input address becomes valid at time t 0 , whereby one row select line C i and one column select line W j are designated, and one of the data lines D i0 -D i7 is selected by the switching circuit 4 . Then, after time t 1 , the logic state of the corresponding memory cell 2 can be read out. Furthermore, when accessing with another address, the logic state of the corresponding memory cell 2 can be read out after a time period (t 1 -t 0 ) has elapsed from when the input address became valid. In the high-speed read mode, as shown in Figure 4 , the first read of the memory cells 2 simultaneously selected by one row select line C i and one column select line W j requires the same time period (t 1 -t 0 ) as in the normal random access from time t 0 at which the input address becomes valid to time t 1 at which the potentials of the respective data lines D i0 -D i7 and the dummy data line D d become valid. However, thereafter, since the potentials of the respective data lines D i0 -D i7 are already valid, the other seven memory cells 2 can be read at a high speed by switching the bank select lines P 0 -P 7 which sequentially become HIGH at time t 2 , time t 3 , ···. The time periods between times t 2 and t 3 , times t 3 and t 4 ,··· (i.e., time periods between the time and the succeeding time) are sufficiently shorter than the time period (t 1 -t 0 ). As seen from above, in the mask ROM of this embodiment, in order to realize the high-speed read mode similar to the prior art, the load circuit 6 is provided with the transistors Q Li0 -Q Li7 which are connected to the data lines D i0 -D i7 , respectively. Therefore, the required number of the sense amplifiers 3 each of which comprises a differential amplifier circuit including a number of MOSFETs and with a large power consumption can be reduced to one-eighth with respect to the prior art. As apparent from the above description, in the semiconductor memory device of the invention, a sense amplifier with a complicated configuration can be commonly used for a plurality of data lines only by providing simple load circuits. Therefore, the chip area and the power consumption can be reduced while the high-speed read mode is provided as in the prior art. It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope of this invention as defined by the appended claims.

Claims: A semiconductor memory device comprising: a sense amplifier (3); a plurality of memory cells (2) each for storing information; a plurality of loads (6); a plurality of data lines (D i0 to D i7 ) each having a first portion and a second portion, each of said plurality of memory cells being connected to a corresponding one of said first portions, and each of said plurality of loads being connected to a corresponding one of said second portions; first switching means (4) for selectively connecting any one of said plurality of second portions to an input of said sense amplifier; and second switching means (1) for simultaneously connecting said second portions to said respective first portions of said plurality of data lines to establish in cooperation with a corresponding one of said plurality of loads valid data on each of said second portions before said first switching means selectively connects any one of said plurality of second portions to said input of said sense amplifier. A semiconductor memory device according to claim 1, wherein said second switching means comprises a plurality of groups of switching elements, one of said groups of switching elements is selected from said plurality of groups of switching elements by decoding an input address, and said selected group of switching elements simultaneously connects said first portions connected to said selected group of switching elements to said respective second portions of said plurality of data lines. A semiconductor memory device comprising; a differential sense amplifier (3) having a first input terminal and a second input terminal; a plurality of memory cells (2) each for storing information; a dummy cell (7) for storing a standard information; load means (6) having a plurality of transistors (Q Li0 to Q Li7 , Q LD ); a dummy data line (Dd) having a first dummy portion and a second dummy portion coupled to each other, said dummy cell (7) being connected to said first dummy portion and said second input terminal of said sense amplifier being connected to said second dummy portion ; a plurality of data lines (D i0 to D i7 ) each having a first portion and a second portion, each of said plurality of memory cells being connected to a corresponding one of said first portions, and each one of said transistors (Q Li0 to Q Li7 , Q Ld ) being connected to a corresponding one of said second portions of said data lines and dummy data line first switching means (4) for selectively connecting any one of said plurality of second portions of said data lines to said first input terminal of said differential sense amplifier; second switching means (1) for simultaneously connecting said second portions to said respective first portions of said plurality of data lines to establish in cooperation with a corresponding one of said plurality of transistors valid data on each of said second portions before said first switching means selectively connects any one of said plurality of second portions to said first input terminal of said differential sense amplifier; an equalizing means (8) for equalizing each state of said plurality of second portions with a state of said second dummy portion; and wherein said differential sense amplifier is arranged to compare a state of one of said second portions of said data lines selected by said first switching means with a state of said second dummy portion. A semiconductor memory device according to claim 1, wherein at least one of said plurality of loads comprises a transistor. A semiconductor memory device according to claim 1, wherein said plurality of memory cells include at least one dummy memory cell (7). A semiconductor memory device according to claim 5, wherein a dummy data line (Dd) for said dummy cell (7) is connected to one input of said sense amplifier, and said second portions of said plurality of data lines are connected to another input of said sense amplifier through said first switching means. A semiconductor memory device according to claim 6, wherein equalizing means (8) is connected between said dummy data line and said respective second portions of said plurality of data lines. A semiconductor memory device according to claim 7, wherein, when said equalizing means receives a valid signal, said equalizing means connects said dummy data line with said second portions of said plurality of data lines for predetermined period of time.

Inventors: HOTTA YASUHIRO, HOTTA, YASUHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: G11C17
IPC codes: G11C17, G11C16