High speed, low power high common mode range voltage mode differential driver circuit

Abstract: A transceiver is provided having a driver circuit (2), with a signal input on line (6) to pull up/pull down circuits (14, 17), each with an output current mirror circuit (15, 18), which terminate input drive to the pull up/pull down circuits (14, 17) if the output exceeds a predetermined level. Speed-up circuits (16, 19) rapidly turn off current sources for circuits (14, 17) when the input signal falls below a predetermined level.

Description: FIELD OF THE INVENTION This invention relates in general to transceivers, and, in particular to driver circuits for transceivers. BACKGROUND OF THE INVENTION This application is related to U.S. patent application serial no. 07/782,706 (TI-16714) filed October 25, 1991. A transceiver is an electrical device for sending and receiving electrical signals, in particular signals representative of data in a digital format. A transceiver is disposed at the interface between one system or device and a transmission line coupled to another system or device. For example, transceiver is used at the output of a computer to transmit the computer output over a wire to a peripheral device, such as a video display terminal or a printer. Many systems that have a central processing unit or microprocessor or microcomputer use transceivers. Such systems may be computers, telephone systems, disk drives, automotive control systems and other industrial systems. The transmission line connectible to the transceiver may be a ribbon, coaxial cable or a twisted pair of wires. The latter transmission line is typically coupled to a transceiver that conforms to the RS 485 interface standard. A transceiver comprises two parts, a driver and a receiver. The driver has an input coupled to the output of a system, typically at the serial output of a UART (universal asynchronous receiver transmitter) device. The UART device converts the normal parallel data bits on a computer bus to a stream of serial bits. That serial stream of bits forms the input signal to the driver circuit of a transceiver. The driver circuit converts the logic level signal of the input to a level compatible with the transmission line. For example, the driver may convert a TTL, ECL or CMOS logic level signal to an RS 485 signal having a differential voltage equal to or greater than 1.5 volts and capable of driving a 54 ohm load. Prior art driver circuits have been integrated onto a single semiconductor substrate using only bipolar transistors. Such devices have high speed and high drive capability but also consume large amounts of power even when no signal is being driven. Bipolar transistor circuits usually have bias current sources that power the bipolar transistors even when no signal is being driven. In addition, the number of transceivers that could be integrated onto a single semiconductor substrate has been limited by the power consumption of the bipolar transistors. At present, no more than four RS485 type transceivers can be integrated onto a single substrate, but it is desirable to increase the density of integration by adding more, high drive, high speed bipolar drive circuits to the transceiver substrate. One solution to the power consumption problem has been to use only CMOS transistors in the driver circuit. However, pure CMOS circuits have several limitations. One is component breakdown voltage. CMOS devices simply cannot handle the voltage ranges of input signals to achieve an acceptable range of common mode operation. Common mode operation is a measure of driver performance. Accordingly, there exists a long felt need for a transceiver with a driver having low power consumption in its quiescent state, a high common mode operation, and high speed. DE-A-3 941 840 discloses a FET-TTL interface circuit comprising a first npn bipolar transistor arranged between a first potential and an output of the circuit, and a second npn bipolar transistor connected between the output and a second potential (ground). A first p-channel MOSFET has its source connected to the first potential, its drain connected to the base of the first bipolar transistor and its gate connected to an input of the circuit. A second n-channel MOSFET has its drain connected to the base of the first bipolar transistor, its source connected to the base of the second bipolar transistor, and its gate connected to the input of the circuit. A third n-channel MOSFET has its drain connected to the first potential, its source connected to the base of the second bipolar transistor, and its gate connected to the input of the circuit. A fourth n-channel MOSFET has its drain connected to the base of the second bipolar transistor, its source connected to the second potential, and its gate connected to the output of the circuit. A fifth n-channel MOSFET has its drain electrode connected to the output of the circuit, its source connected to the basis of the second bipolar transistor, and its gate connected to the input of the circuit. The document PATENT ABSTRACTS OF JAPAN, Vol. 14, No. 288, (E-943) [4231] for JP-A-2 092 113 discloses a circuit in which a p-type MOS transistor has its source-drain path connected in series with the source-drain path of an n-type MOS transistor. One end of the series-connected MOS transistors is connected to V DD and the other end is connected to ground. Two bipolar transistors likewise have their collector-emitter paths connected in series from V DD to ground. The junction of the series-connected bipolar transistors is connected to an output terminal. A further n-type MOS transistor has its source-drain path connected from the output terminal to the base of the bipolar transistor that is connected to ground. An input terminal is connected to the gates of all three MOS transistors. The circuit speeds up operation by discharging the charge accumulated in the base of a first one of the bipolar transistors changing from ON to OFF into the base of the other bipolar transistor changing from OFF to ON. The document PATENT ABSTRACTS OF JAPAN, Vol. 12, No. 449, (E-686) [3296] for JP-A-63 176 015 discloses a circuit to prevent a harmful current from flowing into an integrated circuit from a common bus connected with an output terminal. A switching circuit, interposed between a first power supply and a first MOS transistor, is turned on/off in "interlocking" relationship with the on/off state of the first power supply. In more detail, an npn transistor as switching element is interposed between a power terminal and a p-type MOS transistor. The emitter of the npn transistor is connected to the source of the p-type MOS transistor and the collector is connected, together with the base, to the power terminal. With power supply voltage turned off and the npn transistor turned off in "interlocking" relationship therewith, the current path between an output terminal and the power terminal is disconnected. It is stated that even when an "H" signal is supplied to the common bus connecting to the output terminal from another integrated circuit, no harmful current flows [from] the output terminal to the power terminal. The present invention provides a driver circuit having an input node and an output node, comprising: a first current source coupled to the input node and coupled to a voltage supply; a first bipolar transistor having a base coupled to the current source, and being coupled to the voltage supply and the output node to deliver a first output current; a second current source coupled to the output node and a second voltage supply; a second bipolar transistor having a base coupled to the second current source and further coupled between the second voltage supply and the output node to deliver a second output current; characterized in that: a first current limiting circuit for limiting the first output current is coupled to the first current source and the first bipolar transistor; a second current limiting circuit for limiting the second output current is coupled to the second current source and the second bipolar transistor; and wherein the first current limiting circuit comprises a third bipolar transistor having a base coupled to the base of the first bipolar transistor, an emitter coupled to the emitter of the first bipolar transistor and a collector coupled to the input node, the third bipolar transistor being scaled to the first bipolar transistor. The embodiment of the invention illustrated in the accompanying drawings solves the problems of the prior art and meets the long felt need in the art by providing a transceiver with BiCMOS circuitry. The illustrated embodiment arranges the CMOS transistors to minimize power consumption in a quiescent state and the bipolar transistors to drive and switch the load. In particular, the transceiver driver circuit has a pull up/pull down circuit with CMOS transistors supply base current to the bipolar pull up and pull down transistors. In its quiescent state the CMOS transistors draw no current so the power consumption of the circuit under no load conditions is minimized. The illustrated embodiment allows the integration of five or more transceivers with bipolar differential driver circuits on one substrate. The driver circuit also includes a current mirror circuit. The current mirror circuit protects the driver from exceeding the drive current and voltage for the transmission line and the rated currents and voltages of the pull up/pull down transistors. The current mirror is coupled between the input and output of the pull up/pull down circuit. It measures the output current. If a predetermined output current is exceeded, the current mirror circuits turn off the current supply to the base of the bipolar transistor. The current mirror circuit comprises a pair of bipolar transistors sized to be a fraction of the size of the pull up/pull down transistors. The driver circuit also has a speed up circuit. The speed up circuit comprises CMOS transistors coupled between ground and the base of the bipolar pull up/pull down transistors. The gates of the speed up bipolar transistors are coupled to the input of the driver. When the input driver signal goes low, the gates turn on to connect the appropriate base of the pull up or pull down transistor to ground and thereby speed up the shut off of the pull up or pull down transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig 1. is a block diagram of a system using a transceiver. Fig 2. is a block diagram of a differential driver for the transceiver of Fig. 1. Fig 3. is an electrical schematic of half of the differential driver of Fig.2. Turning to Figure 1, there is shown a first system 20, for example a computer having a transceiver 1 coupled to a pair of transmission lines 12, 13 which terminate at a peripheral device 22, such as a video display terminal or a printer. The transceiver 1 comprises a driver circuit 2 and a receiver circuit 3. In response to a signal, output from the computer 20 to a chip enable function pin 4, the transceiver 1 will enable either the driver 2 or the receiver 3. Information in the form of single-ended digital signals is output from the computer 20 typically over a large bus, including a number of lines such as lines 6 and 7. Line 6, for example, meets a single-ended signal which is converted by the driver circuit 2 to a signal level compatible with the requirements of transmission lines 12, 13. In the preferred embodiment, the transmission lines 12, 13 are designed to match a standard RS485 interface. The transmission lines are also coupled via lines 10 and 11 to receiver circuit 3. Chip enable pin 4 will couple the output of receiver 3 consisting of single-ended signals to computer 20 input via a line such as 8 or 9. Lines 8, 9 are generally also part of a large bus of computer 20. The system shown in Figure 1 has a single transceiver. Current levels of integration compatible with bipolar circuits allow for an integration of a maximum of four transceivers on a single semiconductor substrate. However, with the subject invention, it is possible to integrate five or more transceivers on a single substrate. So far, the invention has been successful in integrating as many as nine transceivers on a single substrate. The driver circuit 2 is shown in further schematic detail in Figure 2. The input signal passes through a single-ended to differential signal transmitter such as is known in the art and is input respectively over lines 6 and 7 to pull up/pull down circuits 14, 17. Both of the pull up/pull down circuits 14, 17 comprise bipolar drive transistors with MOS current sources providing power to the bases of the drive transistors. The details of a typical driver circuit will be discussed further in connection with Figure 3. Pull up/pull down circuits 14, 17 each have an output circuit mirror circuit 15, 18, respectively coupled between the outputs of the pull up/pull down circuits and the circuits themselves. The current mirror circuits 15, 18 measure the output on transmission lines 12, 13. If the output exceeds a certain predetermined level, then the current mirrors terminate the input drive to the pull up/pull down circuits 14, 17. Pull up/pull down circuits 14, 17 also have speed up circuits 16, 19, respectively coupled thereto. The speed up circuits 16, 19 sense the input signal level on input lines 6,7. When the input signal falls to a predetermined level indicating no signal on lines 6,7, the speed up circuits 16, 19 assist in rapidly turning off the current sources that provide current for the pull up/pull down circuits. Turning to Figure 3, there is shown a schematic diagram of one of the driver circuits 14, 17 of Figure 2. An input voltage Vi is provided to the gate of an NMOS transistor MN 1 , and to the input of an inverter 22. The output of inverter 22 is connected to the gate of a p-channel transistor MP 1 through a resistor Rip2, and to the gate of an n-channel transistor MN 2 through resistor Ri2. The drain of p-channel transistor MP 1 is connected to the bases of NPN transistors Q1 and Q 1A as well as to the anode of Schottky diode D S1 , The source of transistor MP 1 is connected to the cathode of Schottky diode D S2 the anode of which is connected to a supply voltage Vcc. The collector of transistor Q1 is connected to Vcc through Schottky diode D S5 , while the collector of transistor Q 1A is connected to Vcc through resistor R IOSH and Schottky diode D S6 . Resistor R IOSH is also connected across the emitter and base of a PNP transistor Q P1 , which has its emitter connected to Vcc. The emitter of transistor Q P1 is connected to the gate of transistor MP 1 through a Schottky diode D S7 . The emitters of transistors Q1 and Q 1A are connected to node 6 through resistors R EH1 and R EH2 , respectively. The gate of transistor mn2 is connected to the gate of an n-channel transistor MN 3 and to the collector of an NPN transistor Q3. The source of transistor MN 2 is connected to the drain of transistor MN 1 and to the bases of NPN transistors Q2 and Q 2A , as well as to the source of transistor MN 3 . The drain of transistor MN 3 is connected to node 6 through Schottky diode D S8 . The collector of transistor Q2 is connected to node 6 through Schottky diode D S9 , well as to one end of resistor R IOSH , which has its other end connected to the base of a PNP transistor Q P2 , and to the emitter of transistor Q P2 . The collector of transistor Q2 A is connected to the base of transistor Q P2 . The emitters of transistors Q2 and Q2 A are connected to ground through resistors R EL1 and R EL2 , respectively. The collector of transistor Q P2 is connected to the base of transistor Q3. The base of Q3 is connected to ground through resistor Rg, while the emitter of Q3 is connected to ground, as is tiiu source of transistor MN 1 . The circuit shown in Figure 3 provides a push-pull drive to one end of a differential transmission line, shown as R L and C L node 6. A logic input signal Vi is provided at the input of the driver circuit 14 or 17. A complementary signal Vip2 is generated with the use of inverter 22, preferably a simple CMOS inverter. When Vi is high, Vip2 goes low, turning on transistor MP 1 , which provides base drive current for the pull up stage output transistor Q1, which provides drive current to the load. At the same time, since Vip2 is low, transistor MN 2 is turned off, so as not to drain current from drive transistor Q1. NN 3 is also simultaneously turned off to prevent current drain from node 6. Q1a, Qp1, R IOSH and Rip2 form a current limiting circuit, which is a requirement of RS485. Q1 and Q 1A are matched as scaled to each other such that the collector current of Q 1A is a multiple of the collector current of Q1. In the preferred embodiment, the scaling factor is fifty to one. As the output impedance drops (going toward a short circuit condition on the output), there is a voltage drop across the base-emitter junction of QP 1 . As it goes up and reaches forward bias voltage, QP 1 delivers collector current back to the gate of MP 1 , generating a voltage drop across Rip2, turning MP 1 off. R IOSH is chosen so that at the appropriate Q 1A collector current, QP 1 is turned on. The scaling factor between Q1 and Q 1A is chosen such that the value of R IOSH can be reasonable, and thus easily manufacturable. When Vi is high, it also is provided to the gate of MN 1 , turning it on, which provides a low impedance path from the bases of sink transistors Q2 and Q 2A , helping turn them off. When Vi is low, inverter 22 provides a high signal to PMOS transistor MP 1 , turning it off, which then removes the drive current from sourcing transistors Q1 and Q1a. At the same time, the high signal is provided to the gate of MN 2 and to MN 3 . The source of MN 2 is thus tied to base of Q2, while its drain is connected to the bases of Q1 and Q 1A through D S2 . This provides a discharge path for its stored base charge, which provides for a quick turn off, allowing the circuit to operate with zero quiescent current under no load conditions. It also provides a brief surge of current which is used to help turn Q2 on. Simultaneously, MN 3 is also turned on, tied from the output node 6 to the bases of drain transistors Q2 and Q 2A . Thus, the base drive current for sink transistors Q2 and Q 2A actually comes from the load, which is an advantage. The base drive, which would normally account for 10-15% of the power required, would conventionally come from the power supply. This configuration allows minimum power dissipation. The sink transistors have the same ratio that the drive transistors Q1 and Q 1A have. The current through Q 2A is monitored in a similar manner to the current through Q1A, Q2A, Qp2, R IOSL and R 12 form the current limiting circuit for the sink transistors Q2 and Q2A. When the voltage drop across R IOSL reaches one Vbe, transistor. QP 2 turns on, which provides base current to Q3, turning Q3 on, which in turn sinks the drive signal to the gate of MN 2 and MN 3 , turning them off, which removes the drive current from the bases of Q2 and Q2A, turning them off. Schottky blocking diodes are used with high voltage MOS and bipolar components to allow extended output common mode range above Vcc and below ground, as required by RS485. For the pull-up stage, D S2 blocks the current path through the drain-backgate diode of MP 1 when the output is pulled above Vcc. Ds5 and Ds6 provide similar blocking under the same conditions for the base collector diodes of Q1 and Q1A. For the pull down stage, Ds7 provides blocking for the current path formed by the base-collector diodes of Q2 and Q2A. Although the invention has been described and illustrated with a certain degree of particularity, is understood that the present disclosure has been made by way of example only and that numerous changes in the combination and arrangement of parts or steps may be resorted to by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims: A driver circuit having an input node and an output node, comprising: a first current source (MP 1 ) coupled to the input node and coupled to a voltage supply (Vcc); a first bipolar transistor (Q 1 ) having a base coupled to the current source (MP 1 ), and being coupled to the voltage supply (Vcc) and the output node to deliver a first output current; a second current source (MN 2 ) coupled to the output node and a second voltage supply; a second bipolar transistor (Q 2 ) having a base coupled to the second current source (MN 2 ) and further coupled between the second voltage supply and the output node to deliver a second output current; characterized in that: a first current limiting circuit (Q 1A , Q p1 , R IOSH , R ip2 ) for limiting the first output current is coupled to the first current source (MP 1 ) and the first bipolar transistor (Q 1 ); a second current limiting circuit (Q 2A , Q p2 , R IOSL , R i2 ) for limiting the second output current is coupled to the second current source (MN 2 ) and the second bipolar transistor (Q 2 ); and wherein the first current limiting circuit comprises a third bipolar transistor (Q 1A ) having a base coupled to the base of the first bipolar transistor (Q 1 ), an emitter coupled to the emitter of the first bipolar transistor (Q 1 ) and a collector coupled to the input node, the third bipolar transistor (Q 1A ) being scaled to the first bipolar transistor (Q 1 ). The driver circuit of claim 1, wherein the second current limiting circuit comprises: a fourth bipolar transistor (Q 2A ) having a base coupled to the base of the second bipolar transistor , an emitter coupled to the emitter of the second bipolar transistor (Q 2 ), and a collector coupled to the collector of the second bipolar transistor (Q 2 ). The driver circuit of claim 2, wherein the fourth bipolar transistor (Q 2A ) is scaled to the second bipolar transistor (Q 2 ). The driver circuit of any preceding claim, wherein the first current limiting circuit further comprises: a fifth bipolar transistor (Q p1 ) having a base coupled to the collector of the third bipolar transistor (Q 1A ), and a current path coupled between the first voltage supply (Vcc) and the input of the first current source (MP 1 ). The driver circuit of any preceding claim, wherein the second current limiting circuit further comprises a sixth bipolar transistor (Qp 2 ) having a base coupled to the collector of the fourth bipolar transistor (Q 2A ), and a current path coupled between the collector of the fourth bipolar transistor (Qp 2 ) and the input of the second current source (MN 2 ). The driver circuit of any preceding claim, wherein the first and second current sources comprise a pair of CMOS transistors (MP 1 , MN 2 ). The driver circuit of any preceding claim, wherein the second current source (MN 2 ) is off when the first current source (MP 1 ) is on. The driver circuit of any preceding claim, wherein the first current source (MP 1 ) is off when the second current source (MN 2 ) is on.

Inventors: TOMASSETTI STEVEN R, TSONG DANNY, TOMASSETTI, STEVEN R., TSONG, DANNY
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1992
Main classification: H03K19
IPC codes: H03K19, H04B1, H03K17