Simplified low-noise output buffer circuit

Abstract: An output buffer circuit has a pull-up output transistor (14) controlled by a first node (15) and a pull-down output transistor (16) controlled by a second node (18). The first node (15) is coupled to the second node (18) through a switching stage (10) controlled by feedback from the output terminal (3). When the output buffer circuit is switched between the high and low output states, the switching stage (10) is initially on, switches off shortly after the potential of the output terminal (3) begins to change, then switches on again when the output terminal (3) reaches a certain intermediate potential.

Description: BACKGROUND OF THE INVENTION This invention relates to an output buffer circuit, more particularly to an output buffer circuit with a simple circuit configuration and reduced switching noise. Switching noise occurring on power supply and ground lines when an output buffer is switched between different states is a serious problem in integrated circuits. The major cause of such noise is the abrupt charging or discharging of a capacitive output load to which the buffer is connected. A minor cause is direct flow of current from the power supply to ground through the buffer circuit at the instant of switching. Prior-art solutions to this problem have not been entirely satisfactory. For example, Japanese Patent Application Kokai Publication No. 216518/1986 discloses a tri-state output buffer circuit with two field-effect output transistors, the gates of which are interconnected through a transmission gate that is switched on and off by a control signal. The transmission gate reduces switching noise by delaying the turn-on times of the output transistors, so that they are never both on simultaneously. This scheme eliminates the minor cause of the switching noise problem, but fails to address the major cause. Reducing the dimensions of the transistors in the transmission gate so that the output transistors turn on more slowly is not a satisfactory solution. Aside from slowing the operation of the circuit, it solves the problem only up to a certain output load capacitance. For larger capacitive loads the problem of switching noise still remains, because the relevant output transistor still turns too quickly in relation to the charge or discharge time of the capacitive output load. Japanese Patent Application Kokai Publication No. 244124/1986 discloses an output buffer circuit having two or more pull-up output transistors coupled in parallel to the power supply, and two or more pull-down output transistors coupled in parallel to ground. The turn-on times of the transistors are staggered so as to reduce peak charge or discharge current, while providing sufficient current-driving ability after all pull-up or pull-down transistors have been turned on. The drawback of this scheme is the large number of circuit elements required, e.g. twenty-four transistors in the disclosed circuit, many having their drains connected directly to the output terminal and requiring large pattern areas to prevent such problems as latch-up. This scheme is accordingly inappropriate for gate arrays and other devices in which a large number of output buffers must fit into a restricted space. EP-A-0 344 604 discloses an output buffer, wherein a resistive circuit of CMOS structure is connected between the gates of the CMOS transistors. The resistive circuit reduces the changes in the gate potentials of output buffer transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output buffer transistors, is minimized. The output buffer of EP-A-0 344 604 is similar to the output buffer disclosed in the above-mentioned Japanese Application Kokai Publication No. 216518/1986, the features of which are also described in the preamble of claim 1. SUMMARY OF THE INVENTION It is accordingly an object of the present invention to reduce switching noise in output buffer circuits. Another object of the present invention is to simplify the structure of output buffer circuits. Yet another object of the invention is to improve the switching speed of output buffer circuits. The objects are solved by an output buffer as defined in claim 1. The subclaims show further developments of the output buffer of claim 1. The invented output buffer circuit has an output terminal, a power supply terminal, and a ground terminal. The output terminal is coupled to the power supply terminal through first switch having a first control terminal, the coupling being responsive to input at the first control terminal. The output terminal is coupled to the ground terminal through second switch having a second control terminal, the coupling being responsive to input at the second control terminal. The first control terminal and second terminal are mutually coupled through a third switch. The third switch is also coupled to the output terminal, and the mutual coupling of the first and second control terminals is responsive to the potential of the output terminal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a novel tri-state output buffer circuit. Fig. 2 is a partial redrawing of Fig. 1, illustrating a load capacitance and stray inductance. Fig. 3 is a waveform diagram illustrating the operation of the output buffer circuit in Fig. 1. Fig. 4 is a schematic diagram of a prior-art output buffer circuit. Fig. 5 is a graph of peak ground noise voltages in novel and prior-art output buffer circuits. Fig. 6 is a schematic diagram of a novel totem-pole output buffer circuit. DETAILED DESCRIPTION OF THE INVENTION Tri-state and totem-pole embodiments of the invented output buffer circuit will be described with reference to the attached drawings. The drawings are intended only to illustrate the invention; they do not restrict its scope, which should be determined solely from the appended claims. Referring to Fig. 1, a novel tri-state output buffer circuit has a data input terminal 1, a control input terminal 2, an output terminal 3, a power supply terminal 4, and a ground terminal 5. The power supply and ground terminals 4 and 5 are coupled to internal power supply and ground lines of an integrated circuit of which the output buffer circuit in Fig. 1 is a part. The power supply terminal 4 supplies a nominally constant power supply potential to the output buffer circuit; the ground terminal 5 supplies a nominally constant ground potential. The conventional symbols V CC and GND will be used to denote the power supply and ground potentials. The terms "high" and "low" will also be used to refer to the power-supply and ground potentials, respectively. In the following descriptions a power-supply potential of five volts and ground potential of zero volts will be assumed, but the invention is of course not limited to these specific values. The output buffer circuit in Fig. 1 is divided into three stages. A final output stage 8 directly drives the output terminal 3. A switching stage 10 (the semiconductor switching means referred to in the summary of the invention) turns on elements in the final stage 8. A control stage 12 controls the switching stage 10, and turns off elements in the final stage. The final stage 8 comprises a pull-up output transistor and a pull-down output transistor. The pull-up output transistor is a p-channel metal-oxide-semiconductor field-effect output transistor 14 with a source electrode coupled to the power supply terminal 4, a gate electrode coupled to a first node 15, and a drain electrode coupled to the output terminal 3. The pull-down output transistor is an n-channel metal-oxide-semiconductor field-effect output transistor 16 with a source electrode coupled to the ground terminal 5, a gate electrode coupled to a second node 18, and a drain electrode coupled to the output terminal 3. For the sake of brevity, p-channel and n-channel metal-oxide-semiconductor field-effect transistors will be referred to below by the standard acronyms PMOS and NMOS, the word "electrode" will be omitted, and nodes will be identified only by their reference numerals. The switching stage 10 has a pair of PMOS transistors 20 and 22 coupled in series between nodes 15 and 18. The source of the PMOS transistor 22 is coupled to node 15, the drain of the PMOS transistor 22 is coupled to the source of the PMOS transistor 20, and the drain of the PMOS transistor 20 is coupled to node 18. The gate of the PMOS transistor 20 is coupled to the output terminal 3. The gate of the PMOS transistor 22 is coupled to a node in the control stage 12 as described later. The switching stage 10 also has a pair of NMOS transistors 24 and 26 coupled in series between nodes 15 and 18. The source of the NMOS transistor 26 is coupled to node 18, the drain of the NMOS transistor 26 is coupled to the source of the NMOS transistor 24, and the drain of the NMOS transistor 24 is coupled to node 15. The gate of the NMOS transistor 24 is coupled to the output terminal 3. The gate of the NMOS transistor 26 is coupled to the control input terminal 2. The control stage 12 comprises an inverter 28, PMOS transistors 30 and 32, and NMOS transistors 34 and 36. The input of the inverter 28 is coupled to the control input terminal 2; the output of the inverter 28 is coupled to a node 38 which is coupled to the gate of the PMOS transistor 22 in the switching stage 10. The sources of the PMOS transistors 30 and 32 are both coupled to the power supply terminal 4, and their drains are both coupled to node 15. The gate of the PMOS transistor 30 is coupled to the control input terminal 2. The gate of the PMOS transistor 32 is coupled to the data input terminal 1. The sources of the NMOS transistors 34 and 36 are both coupled to the ground terminal 5, and their drains are both coupled to node 18. The gate of the NMOS transistor 34 is coupled to node 38. The gate of the NMOS transistor 36 is coupled to the data input terminal 1. Referring to Fig. 2, the output terminal 3 is coupled to a capacitive load, represented here as a capacitor C L disposed between the output terminal 3 and an external ground 40 such as a ground plane of a printed circuit board. The ground terminal 5 is coupled to a similar external ground 41, but there is a stray inductance L G between the ground terminal 5 and the external ground 41. Due to well-known inductive effects, when the capacitive load C L discharges through the NMOS output transistor 16 and ground terminal 5 to the external ground 41, the stray inductance L G generates a noise voltage V GN at the ground terminal 5. This output buffer circuit operates in three states: a high output state in which the output terminal 3 is coupled to the power supply terminal 4, a low output state in which the output terminal 3 is coupled to the ground terminal 5, and a high-impedance state in which the output terminal 3 is coupled to neither of these terminals. When the control input terminal 2 is low, the output buffer circuit is in high-impedance state. When the control input terminal 2 is high, the output buffer circuit is in the high or low output state according to the state of the data input terminal 1. A description of the operation in these three states, and of switching among them, will be given next. First the high-impedance state circuit will be described. If the control input terminal 2 is low, node 38 is high and the NMOS transistor 26 and PMOS transistor 22 in the switching stage 10 are both off, so the gates of the output transistors 14 and 16 are decoupled from one another. The NMOS transistor 34 and PMOS transistor 30 are on, so node 15 is high, which turns off the PMOS output transistor 14, and node 18 is low, which turns off the NMOS output transistor 16. The output terminal 3 is consequently in the high-impedance state, coupled to neither the power supply nor ground. Next the operation in switching from the high-impedance state to the output state will be described. The description will refer to Fig. 3, which shows waveforms at the control input terminal 2, the data input terminal 1, nodes 15 and 18, the output terminal 3, and the power supply terminal 4. These waveforms were obtained by circuit simulation. In Fig. 3, V OUT indicates the voltage of the output terminal 3. V TN and V TP are the gate-source threshold voltages of NMOS and PMOS transistors, respectively. V TN and V TP both have values of about 0.8 volts: if the source of an NMOS transistor is at the ground potential of zero volts, the transistor begins to conduct when its gate potential rises above 0.8 volts; if the source of a PMOS transistor is at the power supply potential of five volts, the transistor begins to conduct when its gate potential falls below 4.2 volts. If the source potential of an NMOS transistor is higher than the ground potential, or the source potential of a PMOS transistor is lower than the power supply potential, V TN and V TP no longer apply. The reason is that PMOS transistors are formed in a substrate biased to the power supply potential, and NMOS transistors are disposed in grounded p-wells. The gate-source potential difference needed to turn on an NMOS transistor therefore increases as the source potential rises; similarly, the gate-source potential difference needed to turn on a PMOS transistor increases as its source potential falls. These increased threshold voltages are denoted V TN ' and V TP ' in the drawing. Suppose now that the control input terminal 2 is originally low and the data input terminal 1 is originally high, as shown at the extreme left in Fig. 3. Node 15 is high and node 18 low as described above. The potential of the output terminal 3 depends on the state of its load C L ; a potential substantially midway between the high and low potentials is shown in Fig. 3, but the actual output potential may be any potential between V CC and GND. If the control input terminal 2 changes from low to high, in the control stage 12, the PMOS transistor 30 and the NMOS transistor 34 turn off. Since the data input terminal 1 is high, the PMOS transistor 32 is off and the NMOS transistor 36 is on. Thus node 15 is decoupled from the power supply terminal 4, while node 18 remains coupled through the NMOS transistor 36 to the ground terminal 5. In the switching stage 10, the PMOS transistor 22 and NMOS transistor 26 turn on. The source potential of the PMOS transistor 20 is therefore near V CC while the source potential of the NMOS transistor 24 is near GND. In view of the threshold voltages V TP and V TN described above, regardless of the potential V OUT of the output terminal 3, at least one of the two transistors 20 and 24 is on. A conducting path therefore exists through the switching stage 10. Node 15 thus discharges through the switching stage 10 and NMOS transistor 36 to the ground terminal 5, and the potential of node 15 falls. In a certain interval, marked by the letter "q" in Fig. 3, the potential drop is temporarily slowed for a reason that will be explained later, but the potential of node 18 soon falls all the way to the ground level. With nodes 15 and 18 both low, the NMOS output transistor 16 remains in the off state but the PMOS output transistor 14 turns on, coupling the output terminal 3 to the power supply terminal 4. The potential of the output terminal 3 rises to the high level. The output buffer is now in the high output state. In the switching stage 10 the PMOS transistor 20 switches off because V OUT is high, but the NMOS transistor 24 remains on. Next the operation of output buffer in switching from the high output state to the low output state will be explained. At time t 0 in Fig. 3 the data input terminal 1 is driven low. In the control stage 12, the NMOS transistor 36 turns off and the PMOS transistor 32 turns on, decoupling node 18 from the ground terminal 5 and coupling node 15 to the power supply terminal 4. The potential of node 15 promptly rises. At time t 1 node 15 reaches the high level, turning off the PMOS output transistor 14 and decoupling the output terminal 3 from the power supply terminal 4. In the switching stage 10, although the PMOS transistor 20 is off, the NMOS transistors 24 and 26 are both on. Node 18 therefore charges from node 15 through the NMOS transistors 24 and 26, and the potential of node 18 also begins to rise. As the potential of node 18 rises, however, so do the source potentials of the NMOS transistors 26 and 24 in the switching stage 10. The gate-source voltages of the NMOS transistors 26 and 24 are thus reduced, diminishing the conductivity of these transistors. Moreover, the threshold voltage V TN ' increases as discussed above. At time t 2 the difference between the gate potential (V OUT ) of the NMOS transistor 24 and its source potential (the potential of node 18) no longer exceeds V TN ', and the NMOS transistor 24 turns off. This temporarily halts the potential rise of node 18 at the value of V OUT - V TN ' at time t 2 , which is about three volts. This value is high enough to turn on the NMOS output transistor 16, the threshold value of which is V TN (0.8 V). V OUT therefore begins to fall as the capacitive load of the output terminal 3 discharges to the ground terminal 5. The discharge begins even before time t 2 . As long as node 18 remains at three volts, however, the rate of discharge is limited to the drain current the NMOS output transistor 16 at this gate potential, which is only about half the drain current at the full gate potential of V CC . When the output voltage V OUT falls below V CC - V TP the PMOS transistor 20 in the switching circuit 10 turns on and allows node 18 to resume charging. At first negligible charge current flows, but as V OUT falls further the conductivity of the PMOS transistor 20 increases, allowing more charge current to flow. The resulting slight rise in potential of node 18 increases the conductivity of the NMOS output transistor 16, accelerating the fall of V OUT . These effects reinforce one another, and at time t 3 in Fig. 3, when V OUT is considerably lower than V CC - V TP , the potential of node 18 begins to rise again at an appreciable rate. This time the potential of node 18 rises all the way to the V CC , while the potential V OUT of the output terminal 3 falls to the ground level. The output buffer circuit is now in the low output state. In the final stage 8 the NMOS transistor 16 is fully turned on, its gate potential being V CC . In the switching stage 10 the NMOS transistor 24 is off, but the PMOS transistors 20 and 22 are both on, holding node 18 at V CC . The bottom waveform in Fig. 3 shows the potential of the ground terminal 5. As mentioned earlier, discharge current from the output terminal 3 induces ground noise. The peak discharge current, however, occurs between times t 2 and t 3 , shortly after the discharge begins, when the gate potential of the NMOS output transistor 16 is being held at an intermediate value of about three volts. Current flow is accordingly restricted, and the induced ground noise level is low. The solid lines in Fig. 3 indicate V OUT and ground noise waveforms for the invented circuit in Fig. 1. The dashed lines indicate waveforms for a prior-art circuit. It can be seen that ground noise in the invented circuit is only about half that in the prior art. The prior-art circuit from which these dashed waveforms were obtained is illustrated in Fig. 4. This is the circuit disclosed in Japanese Patent Application Kokai Publication No. 216518/1986, cited above. Elements corresponding to elements in Fig. 1 are denoted by the same reference numerals. The main difference between this prior-art circuit and the invented circuit is that in the prior-art circuit, the switching stage 10 is not coupled to the output terminal 3 and has no elements controlled by the output voltage V OUT . In the output state, one or the other of the transistors 22 and 26 in the switching stage 10 is always turned on. Thus in switching from the high output state to the low output state, for example, the potential rise of node 18 is not checked at an intermediate point but proceeds at a steady rate. The corresponding uninterrupted rise in the conductivity of the output transistor to rise allows a larger peak discharge current to flow from the output terminal 3 to ground, producing a larger peak noise voltage at the ground terminal. Fig. 5 illustrates peak ground noise voltages when one, two, four, and eight output buffers, all connected to the same ground line, are switched simultaneously from the high to the low output state. Curve A is for the invented circuit. Curve B is for the prior-art circuit in Fig. 5. Curve C is for the prior-art output buffer circuit disclosed in Japanese Patent Application Kokai Publication No. 244124/1986. The values in this graph were obtained by circuit simulation under identical conditions for all three circuits. All control transistors had the same dimensions, and output transistors were designed to assure an output low voltage (V OL ) of 0.4 V or less while sinking an output current (I OL ) of 24 mA. A stray ground inductance L G of 15 nH was assumed for all three circuits. As Fig. 5 shows, the invented circuit produces much less ground noise than in curve B, and also produces slightly less ground noise than in curve C, despite the fact that curve C comes from a complex circuit having twenty-four transistors while the invented circuit has only twelve transistors. (The inverter 28 in Fig. 1 comprises two transistors.) Referring again to Fig. 3, the invented circuit is similarly effective in reducing power supply noise during switching from the low to the high output state. If the data input terminal 1 is driven high at time T 0 , the PMOS transistor 32 turns off and the NMOS transistor 36 turns on, decoupling node 15 from the power supply terminal 4 and coupling node 18 to the ground terminal 5. Node 18 falls promptly to ground level at time T 1 , turning off the NMOS output transistor 16. The potential of node 15 now falls by a process analogous to that detailed earlier. At time T 2 the PMOS transistor 20 in the switching stage 10 turns off, temporarily halting the potential drop of node 15 near the value of V OUT + V TP ', which is about 3.5 V. This value is low enough to turn on the PMOS output transistor 14, so the capacitive load of the output terminal 3 begins to charge and V OUT begins to rise. The rise of V OUT turns on the NMOS transistor 24 in the switching stage 10, however, and at time T 3 the potential of node 15 begins to fall again at an appreciable rate. In the final state node 15 is at the ground potential, so the PMOS output transistor 14 has its full current driving ability, while V OUT is high. Although not shown in Fig. 3, noise at the power supply terminal 4 generated by the switch from the low output state to the high output state is reduced in the same way that ground noise was reduced before. Charge current in the interval q' from time T 2 to time T 3 is limited because the gate potential of the PMOS output transistor 14 is being held at an intermediate value. The induced noise voltage is correspondingly small. The same restriction operated during the switching from the high-impedance state to the output state in the interval "q" in Fig. 3, reducing noise at that time too. The invented output buffer circuit thus deals with the major cause of switching noise, which was excessive flow charge or discharge current. The invented circuit succeeds in restricting peak current flow even in the case of extremely large capacitive output loads, because the switching stage 10 is controlled by direct feedback from the output terminal 3. Regardless of the capacitance of the load, the switching stage 10 switches off and holds the gate of the output transistor 14 or 16 at an intermediate potential until the potential of the output terminal 3 has itself risen or fallen to an intermediate value. Current flow is therefore restricted until the interval of peak charge or discharge current flow has passed. Another advantage of the invention is that when this interval has passed, the switching stage 10 promptly switches on again so that the output transistor can quickly finish turning on. Because of the feedback from the output terminal, the circuit can be easily designed so that intervals such as q and q' in Fig. 3 have the minimum length necessary for noise reduction. The circuit can moreover be optimized for minimum switching time at different capacitive loads, a feature not found in the prior art. The invented circuit can accordingly be expected to operate faster than other low-noise output buffer circuits. As is also clear from Fig. 3, in switching from high to low output, the NMOS transistor 16 does not begin to switch on until the PMOS output transistor 14 has already switched off (node 18 does not rise appreciably until node 15 has already fallen to ground level). Similarly, in switching from low to high output, the PMOS transistor 14 does not begin to switch on until the NMOS output transistor 16 has already switched off (node 15 does not fall appreciably until node 18 has already reached V CC ). Accordingly, current never flows directly from the power supply terminal 4 to the ground terminal 5 through the output buffer circuit, eliminating a second source of noise. Fig. 6 shows a novel totem-pole output buffer circuit that employs a subset of the circuit elements in Fig. 1. The same reference numerals are used. The data input terminal 1, output terminal 3, power supply terminal 4, ground terminal 5, PMOS transistors 14 and 32, and NMOS transistors 16 and 36 are interconnected in the same way as in Fig. 1. The switching stage 40 In Fig. 6 comprises only the PMOS transistor 20 and NMOS transistor 24, which are coupled in parallel between nodes 15 and 18. The gates of both of these transistors are coupled to the output terminal 3, as they were in Fig. 1. This output buffer circuit differs from the one in Fig. 1 in having no control input terminal 2, and in lacking the transistors and inverter that were driven by the control input terminal 2 in Fig. 1. When the control input terminal 2 in Fig. 1 is high, the transistors 30 and 34, which are coupled in parallel with the transistors 32 and 36, can be ignored because they are switched off. The transistors 22 and 26, which are coupled in series with the transistors 20 and 24, can be ignored because they are switched on. Fig. 1 then becomes functionally equivalent to Fig. 6. The output buffer circuit in Fig. 6 accordingly has only two states: a high output state and a low output state. The operation of this circuit in switching between these two states is identical to the operation of the circuit in Fig. 1 in switching between the high and low output states, so further description will be omitted. The benefits of the invention are the same as before: peak charge or discharge current to or from the output load is restricted, reducing noise at the power supply and ground terminals; flow of current directly from the power supply terminal 4 to the ground terminal 5 is prevented; switching time can be optimized for different load capacitances; and all this is accomplished with a small number of transistors (only six). There are many other ways in which the invention can be embodied. For example, instead of using PMOS and NMOS transistors as in Figs. 1 and 6, the invention can be practiced with other semiconductor elements. The necessary modifications will be apparent to those skilled in the art.

Claims: An output buffer circuit comprising: an input terminal (1) for receiving an input signal; an output terminal (3) for providing an output signal; first and second potential terminals (4, 5) for receiving power supply potentials; a first switch (14) coupled between said first potential terminal (4) and said output terminal (3), said first switch (14) having a first control terminal (15); a second switch (16) coupled between said second potential terminal (5) and said output terminal (3), said second switch (16) having a second control terminal (18); a third switch (32) coupled between said first potential terminal (4) and said first control terminal (15), said third switch having a control terminal coupled to said input terminal (1); a fourth switch (36) coupled between said second potential terminal (5) and said second control terminal (18), said fourth switch having a control terminal coupled to said input terminal (1); a switching circuit (10 or 40) coupled between said first control terminal (15) and said second control terminal (18); characterized in that said switching circuit (10 or 40) is coupled to said output terminal (3) and electrically connects said first control terminal (15) and said second control terminal (18) in response to the output signal to temporarily slow a potential drop at the first control terminal or to temporarily halt a potential rise at the second control terminal, respectively. The output buffer of claim 1, wherein said switching circuit (40) comprises fifth and sixth switches (20, 24) coupled in parallel between said first and second control terminals (15, 18), and said fifth and sixth switches (20, 24) have control terminals coupled to said output terminal (3) together. The output buffer of claim 1, further comprising a control input terminal (2) for receiving a control signal. The output buffer of claim 3, wherein said switching circuit (10) comprises: a fifth switch (20) having a first terminal coupled to the second control terminal (18), a second terminal and a control terminal coupled to said output terminal (3); a sixth switch (22) having a first terminal coupled to the second terminal of said fifth switch (20), a second terminal coupled to the first control terminal (15) and a control terminal coupled to said control input terminal (2); a seventh switch (24) having a first terminal coupled to the first control terminal (15), a second terminal and a control terminal coupled to said output terminal (3); and an eighth switch (26) having a first terminal coupled to the second terminal of said seventh switch (24), a second terminal coupled to the second control terminal (18) and a control terminal coupled to said control input terminal (2). The output buffer of claim 3 or 4, further comprising: a ninth switch (30) coupled between said first potential terminal (4) and the first control terminal (15), said ninth switch (30) having a control terminal coupled to said control input terminal (2); and a tenth switch (34) coupled between said second potential terminal (5) and the second control terminal (18), said tenth switch (34) having a control terminal coupled to said control input terminal (2).

Inventors: SATORU TANOI, SATORU, TANOI, Satoru, Tanoi, c/o Oki Electric Industry Co., Ltd.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1992
Main classification: H03K19
IPC codes: H03K19, H03K17