CODEC synchronisation

Abstract: A codec comprises a control circuit (1) for generating a frame synchronous signal (F2) and a clock signal (C2) which are controlled to comply with differnt types of data carried on a received digital signal (DR) to be converted to a received analog signal (AR) in a decoder (2) and data carried on a transmitting digital signal (DX) converted from a transmitting analog signal (AX).

Description: The invention relates to a codec including an encoder and a decoder, and, more particularly, to a codec well adapted to the processing of digital signals distributed on a time axis. A known codec comprises a decoder for converting a received digital signal to a received analog signal, and an encoder for converting a transmitted analog signal to a transmitted digital signal. In operation, when the rising edge of a frame synchronisation signal is detected, a transmitted analog signal is converted in the encoder to a transmitted digital signal having a predetermined number of bits, such that each bit is synchronous with the rising edge of each clock pulse, and a received digital signal having the same predetermined number of bits is converted in the decoder to a received analog signal, such that each bit of the received digital signal is synchronous with the falling edge of a clock pulse. However, the known codec has a disadvantage in that the significant amount of data which can be processed in one frame is small, because the signal conversion is carried out only for a digital signal of the predetermined number of bits, and for an analog signal of a length corresponding to the predetermined number of bits, after the detection of the rising edge of the frame synchronisation signal. The known codec has a further disadvantage in that another set of an encoder and a decoder are required to conduct signal conversion with a conversion rate which is different from the conversion rate of one bit per one clock. A prior art codec described in EP-A-0 020 079 divides the external clock pulses in frequency in accordance with the ratio of the frequency of the frame pulses and the frequency of the external clock pulses. According to the present invention there is provided a codec comprising: a decoder for converting a received digital signal to a received analog signal in synchronism with a first frame synchronisation signal and a first clock signal; an encoder for converting a transmitted analog signal to a transmitted digital signal in synchronism with the first frame synchronisation signal and the first clock signal; and controlling means for controlling the decoder and the encoder to carry out conversion between digital and analog signals by supplying a second frame synchronisation signal and a second clock signal thereto; wherein the controlling means is adapted in response to a control signal to convert individually both (a) the first frame synchronisation signal and (b) the first clock signal to (a) the second frame synchronisation signal and (b) the second clock signal, such as to comply with the timing and/or length of the data carried on the received and transmitted digital signals. The invention will be explained in more detail in conjunction with appended drawings, wherein: Fig. 1 is a block diagram showing a known codec; Fig. 2 is a timing chart showing a first operation of the known codec as shown in Fig. 1; Fig. 3 is a timing chart showing a second operation of the known codec as shown in Fig. 1; Fig. 4 is a block diagram showing a codec of a preferred embodiment according to the invention; and Fig. 5 is a timing chart showing operation of the codec of the preferred embodiment according to the invention. Before explaining a codec of a preferred embodiment according to the invention, the aforementioned known codec will be explained in Fig. 1. The known codec comprises a decoder 11 for converting a received digital signal of eight bits DR to a received analog signal AR in synchronism with the falling edge of each clock signal C11 after the rising edge of a frame synchronisation signal F11, and an encoder 12 for converting a transmitted analog signal AX to a transmitted digital signal of eight bits DX in synchronism with the rising edge of each clock signal C11 after the rising edge of the frame synchronisation signal F11. Fig. 2 shows a first operation of the known codec. In this first operation, when the rising edge of the frame synchronisation signal F11 is detected, the decoder 11 starts the digital-to-analog conversion of the received digital signal DR to provide the received analog signal AR, and the encoder 12 starts the analog-to-digital conversion of the transmitted analog signal AX to provide the transmitted digital signal DX. In the decoder 11, the received digital signal DR of eight bits is converted in synchronism with the falling edge of the clock signal C11 to the received analog signal AR by a conversion rate of one bit per one clock. This conversion is repeated each time the rising edge of the frame synchronous signal F11 is detected. In the encoder 12, the transmitted analog signal AX is converted to the transmitted digital signal DX of eight bits, such that each bit of the transmitted digital signal DX is synchronous with the rising edge of the clock signal C11 with a conversion rate of one bit per one clock. The conversion is repeated each time the rising edge of the frame synchronous signal F11 is detected. Consequently, the received digital signal of eight bits DR including data R11, R21, ..... which is received from a transmission line is converted to the received analog signal AR, and the transmitted analog signal AX is converted to the transmitted digital signal DX including data X11, X21, ..... which will be transmitted through a transmission line. Fig. 3 shows a second operation of the known codec. The basic principle of the second operation is the same as that of the first operation. In the second operation, however, the conversion rate is one bit per two clocks. For the difference of the conversion rate, two sets of decoders and encoders are required to conduct the first and second operations in the known codec. Next, a codec of a preferred embodiment according to the invention will be explained in Fig. 4. The codec comprises a control circuit 1 for generating a frame synchronisation signal F2 and a clock signal C2 which are dependent on the data types of received and transmitted digital signals by receiving an external frame synchronisation signal F1 supplied from a frame synchronisation signal generator 4, an external clock signal C1 supplied from a clock signal generator 5, and a control signal CTL supplied from a control signal generator 6. A decoder 2 converts a received digital signal DR to a received analog signal AR in accordance with the frame synchronisation signal F2 and the clock signal C2 supplied from the control circuit 1, and an encoder 3 converts a transmitted analog signal AX to a transmitted digital signal DX in accordance with the frame synchronisation signal F2 and the clock signal C2. In the control circuit 1, the external frame synchronisation signal F1 and the external clock signal C1 are converted to the frame synchronisation signal F2 and the clock signal C2 complying with the types of the received and transmitted digital signals DR and DX in accordance with the control signal CTL. Fig. 5 illustrates the operation of the codec of the preferred embodiment, in which the first type of a received digital signal DR1 and a transmitted digital signal DX1, and the second type of a received digital signal DR2 and a transmitted digital signal DX2 are processed. First, it is assumed that a first control signal CTL corresponding to the first type of the received and transmitted digital signals DR1 and DX1 including data R11, R12, ..... and X11, X12, ....., respectively, is supplied to the control circuit 1, so that a frame synchronisation signal F21 and a clock signal C21 both corresponding to the first type of the digital signals DR1 and DX1 are supplied from the control circuit 1 to the decoder 2 and the encoder 3. In the decoder 2, the received digital signal DR1 of eight bits including data R11, R21, ..... is converted converted in synchronism with the falling edge of the clock signal C21 after the detection of the rising edge of the frame synchronisation signal F21 to the received analog signal AR with a conversion rate of one bit per one clock, and, in the encoder 3, the transmitted analog signal AX is converted to the transmitted digital signal DX1 of eight bits including data X11, X21, ..... in synchronism with the rising edge of the clock signal C21 after the detection of the rising edge of the frame synchronisation signal F21 with a conversion rate of one bit per one clock. Consequently, the transmitted digital signal DX1 including data X11, X21, ....., to which the transmitted analog signal AX is converted, is transmitted through a transmission line, and the received analog signal AR is obtained from the received digital signal DR1 including data R11, R21, ..... which is received from a transmission line. Then, the frame synchronisation signal F22 and the unchanged clock signal C21 are supplied from the control circuit 1 to the decoder 2 and the encoder 3, so that the received digital signal DR1 including data R12, R22, ....., is converted in the same manner as above to the received analog signal AR, and the transmitted analog signal AX is converted in the same manner as above to the transmitted digital signal DX1 including data X12, X22 ..... . In the same manner, the frame synchronisation signals F23, F24, ..... and the unchanged clock signal C21 are supplied from the control circuit 1 to the decoder 2 and the encoder 3 at predetermined timings as understood from Fig. 5, so that data X13, X14, ..... of the transmitted digital signal DX1 and data R13, R14, ..... of the received digital signal DR1 are processed as explained above. Second, it is assumed that a second control signal CTL corresponding to the second type of the received and transmitted digital signals DR2 and DX2 including data R11, R12, ..... and X11, X12, ..... respectively, is supplied to the control circuit 1, so that the frame synchronisation signal F21 and a clock signal C22 both corresponding to the second type of the digital signals DR2 and DX2 are supplied from the control circuit 1 to the decoder 2 and the encoder 3, wherein the clock signal C22 is of a frequency obtained by dividing the frequency of the clock signal C21 by two, and of a pulse width obtained by multiplying the pulse width of the clock signal C21 by two, so that one clock of the clock signal C22 is equal to two clocks of the clock signal C21. In the decoder 2, the received digital signal DR2 of eight bits including data R11, R21, ..... is converted in synchronism with the falling edge of the clock signal C22 after the detection of the rising edge of the frame synchronisation signal F21 to the received analog signal AR with a conversion rate of one bit per one clock, and, in the encoder 3, the transmitted analog signal AX is converted to the transmitted digital signal DX2 of eight bits including data X11, X21, ..... in synchronism with the rising edge of the clock signal C22 after the detection of the rising edge of the frame synchronisation signal F21 with a conversion rate of one bit per one clock. Consequently, the transmitted digital signal DX2 including data X11, X21, ....., to which the transmitted analog signal AR is converted, is transmitted through a transmission line, and the received analog signal AR is obtained from the received digital signal DR2 including data R11, R21, ..... which is received from a transmission line. Then, the frame synchronisation signal F23 and the unchanged clock signal C22 are supplied from the control circuit 1 to the decoder 2 and the encoder 3, so that the received digital signal DR2 including data R12, R22, ..... is converted in the same manner as above to the received analog signal AR, and the transmitted analog signal AX is converted in the same manner as above to the transmitted digital signal DX2 including data X12, X22 ..... . As described above, the external frame synchronisation and clock signals F1 and C1 are converted to the internal frame synchronisation signal F2 such as F21, F22, F23, ..... and the internal clock signals C2 such as C21, C22 in accordance with the data timing and the data length of the received and transmited digital signals DR and DX such as DR1, DR2, ..... and DX1, DX2, ..... . Therefore, all types of data of received and transmitted digital signals can be encoded and decoded by using a single set of an encoder and a decoder. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth. For instance, only one of the frame synchronisation signal and the clock signal may be controlled to comply with a type of data carried on received and transmitted digital signals.

Claims: A codec comprising: a decoder (2) for converting a received digital signal (DR) to a received analog signal (AR) in synchronism with a first frame synchronisation signal (F1) and a first clock signal (C1); an encoder (3) for converting a transmitted analog signal (AX) to a transmitted digital signal (DX) in synchronism with the first frame synchronisation signal (F1) and the first clock signal (C1); and controlling means (1) for controlling the decoder (2) and the encoder (3) to carry out conversion between digital and analog signals by supplying a second frame synchronisation signal (F2) and a second clock signal (C2) thereto; wherein the controlling means (1) is adapted in response to a control signal (CTL) to convert individually both (a) the first frame synchronisation signal (F1) and (b) the first clock signal (C1) to (a) the second frame synchronisation signal (F2) and (b) the second clock signal (C2), such as to comply with the timing and/or length of the data carried on the received and transmitted digital signals. A codec according to claim 1, wherein the controlling means (1) has inputs for receiving the first frame synchronisation signal (F1), the first clock signal (C1), and the control signal (CTL), and generates the second frame synchronisation signal (F2) and the second clock signal (C2) which are supplied to the decoder (2) and the encoder (3), said control signal representing the timing and/or length of the data carried on the received and transmitted digital signals. A codec according to claim 2, wherein the rising edge of the second frame synchronisation signal (F2) is controlled by the controlling means (1) to comply with the timing of the data carried on the received and transmitted digital signals, and the frequency and pulse width of the second clock signal (2) are controlled by the controlling means (1) to comply with the length of the data carried on the received and transmitted digital signals.

Inventors: KANBARA SATOSHI, KANBARA, SATOSHI, Kanbara, Satoshi, c/o NEC IC Microcomputer Systems
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H04B14
IPC codes: H04B14, H03M1