EPROM cell with a readily scalable down interpoly dielectric

Abstract: The use of an O-N-RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O-N-O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling down.

Description: The present invention relates to a fabrication process of nonvolatile, read-only programmable memories. Static, electrically programmable, nonvolatile, read-only memories, commonly referred to by the acronym EPROM, are fundamental devices for implementing microprocessors systems. These memories, formed by a matrix of memory cells arranged in rows and columns and individually addressable through row and column decoders, may belong to different "families", in terms of the particular electrophysical mechanism which is used for erasing data electrically recorded in the cells, notably EPROM E 2 PROM and FLASH-EPROM. In trying to make ever more compact devices (i.e. ULSI devices), it is necessary to reduce the dimensions of the single cells, i.e. the minimum lithographically definible width. Of course, a reduction of the cell's area accomplished by a correlated reduction of the junctions' depth, i.e. the depth of the diffused regions or simply of the diffusions formed in the semiconducting substrate, as well as of the thicknesses of the layers which are formed over the semiconducting substrate, while preserving the essential electrical characteristics for a reliable functioning of the memory cell. In other words, beside the problems of photolithographic definition there are technological problems which are connected to a "scaling down" of the different features which form the functional integrated structure of an electrically programmable, nonvolatile memory cell. In this type of memories, the dielectric used for isolating a floating gate, which is commonly patterned form a first deposited layer of doped polycrystalline silicon, from a control gate structure, physically superimposed (capacitively coupled) to the floating gate. The insulating dielectric layer between the two conducting layers of the floating gate and of the control gate must be capable to prevent any migration of electrical charge (injected into the floating gate from the semiconducting substrate and there stored in a substantially permanent mode), toward the control gate. On the other hand, the thickness of this dielectric layer must be sufficiently small for determining a good capacitive coupling between the control gate and the floating gate. The published Japanese patent application No. JP 3262150 (Patent Abstract of Japan 21/11/91), describes a semiconductor capacitor of low leakage constituted by a natural oxide film grown on a polycrystalline silicon film to constituting the lower electrode of the capacitor which is nitrided by rapid nitriding in an ammonia atmosphere and coated with a thin silicon nitride film. Finally a phosphorous-containing polycrystalline silicon film is deposited as an upper electrode before patterning the capacitor. In modern devices utilizing two superimposed levels of polysilicon, the first for defining floating gates of single memory cells therefrom (and the gates of the transistors of the external circuitry) and the second for defining control gate structures (commonly the row lines or wordlines of the matrix, instead of utilizing as an interpoly dielectric (i.e. between the two superimposed layers of doped polycrystalline silicon) a layer of silicon oxide, typically generated by thermally oxidizing in presence of water vapor, the surface of the polysilicon of first level i.e. of the floating gates, a multilayer of Oxide-Nitride-Oxide (O-N-O) is used having found that such a multilayer may be produced with a reduced initial defectivity in respect to an oxidation layer produced by a direct oxidation of the polysilicon. This permits to achieve leakage current levels which are compatible with the most stringent specifications of charge retention of the floating gate (i.e. nonvolatility of the stored data). Moreover, the process temperatures used for depositing a layer of silicon nitride and the temperature for oxidizing silicon nitride in order to form such a O-N-O multilayer are lower than the temperature which is required to grow an oxide having good dielectric characteristics by direct oxidation of the surface of a floating gate of doped polysilicon of first level. The attendant damage of the other important dielectric layer of the cell structure, i.e. of the gate oxide which isolates the floating gate from the channel region of the semiconducting substrate which at this stage of the fabrication process has already been formed, is also considerably reduced by a lower process temperature when forming the interpoly dielectric layer. Nothwithstanding the fact that the isolating O-N-O structure between two levels of polysilicon has represented a remarkable technological step forward in respect to the prior technique of forming a single dielectric layer of oxide, also this technique imposes limitations to the scaling down of features, because of a residual, though reduced, intrinsic defectivity of the staked layers. The bottom layer of oxide of the O-N-O multilayer is particularly sensitive to scaling down because of an intrinsic tendency to a substantial defectivity and moreover a reduction of the thickness of the deposited nitride layer beyond a certain limit does not ensure a sufficient imperviousness to oxygen during the subsequent thermal oxidation treatment of a top portion of the thickness of the deposited nitride layer in order to form the insulating dielectric layer of the floating gate from the control gate. An initial defectivity and a difficulty in preventing a growth of the bottom oxide layer of the O-N-O structure during the subsequent thermal oxidation step for the formation of the insulating oxide layer, reflects negatively on the reliability of memories. On the other hand the possibility of forming a dielectric layer for integrated capacitances which ensure a degree of reliability higher than the O-N-O structureis known. According to this technique, disclosed in the Article: "Enhanced Reliability of Native Oxide Free Capacitor Dielectrics on Rapid Thermal Nitridized Polysilicon" of N. Ajika, et al., Symphosium VLSI, Technology Digest, page 63, the coupling surface area between a first electrode consisting of a doped polysilicon layer is thermally nitridized for depositing on this nitridized surface a layer of silicon nitride whose surface will then be thermally oxidized in order to form a dielectric layer of silicon oxide having outstanding dielectric characteristics. This ON/RTN multilayer has been proposed as a dielectric multilayer of improved characteristics as compared with an O-N-O dielectric multilayer for making storage capacitances for high density DRAM memories. In this realm of utilization, the dielectric layer doesn't have a function of retaining the electrical charge for a substantially indefinite period of time in absence of a power supply, as is instead the case of nonvolatile, read only memories (ROM). It has now been found that it is possible to reduce the problems connected to the scaling down of ROM memories by forming the isolating dielectric between a floating gate (poly I) and a control gate (poly II) by subjecting the surface of the polysilicon of a floating gate (poly I) to a rapid thermal nitridization process by treating the polysilicon at a temperature comprised between 900°C and 1100°C for a period of time comprised between 15 and 150 seconds, in a nitrogen atmosphere. This produces a nitridized layer of nitridization of the polysilicon onto which a layer of silicon nitride is deposited for a thickness which may be as high as 15 nm. Subsequently top surface layer of the deposited silicon nitride is oxidised in presence of water vapor at a temperature comprised between 900°C and 1000°C until growing a dielectric layer of silicon oxide whose thickness is preferably comprised between a minimum of about 5 nm and a maximum of about 20 nm. Surprisingly, it has been found that, notwithstanding the fact that electrical charge may migrate from the polysilicon of the floating gate through the nitridization layer to the deposited silicon nitride layer, the fundamental electrical parameters of the memory cell do not change. In particular the variation of the threshold voltage of the cell shows a negligeable variation. By contrast, the dielectric layer thus formed shows an excellent ability to retain the electrical charge stored in the floating gate both in terms of retention time and of maximum working temperature, in absence of power supply. In practice, it is possible to form an interpoly dielectric layer having a real thickness comprised between 10 and 30 nm. Moreover the conditions of the thermal treatment (temperature and duration) during the successive steps of nitridization, deposition of silicon nitride and oxidation, are not such as to produce serious damages to the integrity of the dielectric gate layer (gate oxide) present between the floating gate of poly I and the semiconducting substrate. The Figures from 1 to 12 schematically show the succession of the various steps of a fabrication process of a memory cell in accordance with the present invention. The figures depict a fragmentary microsection, representative of a single memory cell which is being formed in a well region 1w of a second type of conductivity created in a semiconducting substrate 1 of a first type of conductivity. The active area occupied by the cell is defined laterally by an isolation diffused region 2 of a second type of conductivity (channel stopper) formed in the semiconductor 1 under the definition edges of a field oxide structure 3, which is normally thermally grown by oxidizing the single crystal semiconductor 1 in areas left unmasked by an oxygen impervious layer (commonly a layer of silicon nitride). Concisely the sequence of steps depicted in the figures is the following. Fig. 1 : formation of a dielectric gate layer 4 on the active area. Fig. 2 : deposition and subsequent doping of a first poly-silicon layer 5 (poly I). Fig. 3 : definition of the first level polysilicon (poly I) by a masking (M) and etching step. Figures 4 and 4 bis : rapid thermal nitridization treatment of the surface of the patterned polysilicon layer 5 at a temperature comprised between 900°C and 1100°C, for a time comprised between 15 and 150 seconds in a nitrogen atmosphere, followed by the deposition of a layer of silicon nitride having a thickness of about 15 nm and a partial oxidation of the thickness of the deposited layer of nitride in presence of water vapor at a temperature comprised between 900°C and 1000°C, until growing a dielectric layer of silicon oxide, whose thickness may reach 20nm. Fig. 4 bis is an enlarged portion of the cross section of Fig. 4, wherein the stratification is made visible. The layer 6a represents the nitridized top portion of the layer of the polysilicon 5 (i.e. of the floating gate). The layer 6b represents a residual thickness of the silicon nitride layer deposited over the nitridized layer 6a after oxidation. The layer 6c represents a dielectric layer of silicon oxide grown by oxidising a top portion of the thickness of the deposited silicon nitride. Fig. 5 : deposition of a "dummy" layer of polysilicon 7 over the dielectric multilayer 6 (O-N-RTN) for protecting the so formed isolation multilayer 6 (i.e. the oxidized top layer 6c). Fig. 6 : formation of a so-called matrix mask M1 and etching the dummy layer 7 of polysilicon and of the multilayer O-N-RTN 6 in areas left unmasked by the mask M1. Fig. 7 : removal of the residual masking material and deposition and subsequent doping of a second layer of polysilicon (poly II) 8. Fig.8 : deposition of a layer 9 of tungsten silicide (WSi 2 ) or of polycrystalline silicon. Fig. 9 : definition through a so-called poly-II-mask, M2, and subsequent etching of the layer 9 and of the polysilicon silicon layer 8 of second level (poly II). Fig. 10 : masking of the area occupied by circuitry external to the memory matrix by means of mask M3 and subsequent selfaligned etching of the stack composed of the interpoly layer 6, the polysilicon layer 5 of first level (poly I) and the underlying layer 4 of gate oxide, until exposing the semiconductor in areas "unmasked" by the gate structure. Fig. 11 : implantation of dopant for forming cell junctions 11 and 12 of said first type of conductivity. Fig. 12 : diffusion of the dopant and reoxidation of the surface of the semiconductor in the source and drain areas of the cell.

Claims: A process for fabricating a nonvolatile read only memory comprising a plurality of memory cells, comprising the sequence of steps of: providing a substrate having active cell areas therein; depositing a polysilicon layer, and patterning said polysilicon layer to form isolated floating gates over plural ones of said active cell areas; treating the surface of said insulated polysilicon layer at a temperature in the range of 900°C-1100°C for between 15 and 150 seconds in a nitrogen atmosphere, to form a nitridized surface layer thereon; depositing a layer of silicon nitride over said nitridized surface layer; oxidizing part of the thickness of said deposited layer of silicon nitride, in the presence of water vapor, at a temperature in the range of 900°C-1000°C, for a time sufficient to grow a dielectric layer of silicon oxide having a thickness comprised between 5 and 20 nm; and depositing a second thin film conductor layer and patterning said second thin film conductor layer to form control gates over said floating gates, said control gates being connected to form operative transistor gates. The process of claim 1, wherein said step of depositing a layer of silicon nitride is performed to a thickness of no more than 15 nm. The process of claim 1, wherein said nitridized layer, said layer of silicon nitride and said layer of silicon oxide have a total real thickness in the range of 10-30 nm.

Inventors: CLEMENTI CESARE, GHIDINI GABRIELLA, TOSI MARINA, CLEMENTI, CESARE, GHIDINI, GABRIELLA, TOSI, MARINA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H01L21
IPC codes: G11C17, H01L21, H01L29, H01L27