Noise generating device

Abstract: A noise generating device is provided which includes a pseudo-random number generator having a shift register that performs shift operations to sequentially shift the bit in the input stage to the next higher significant stage and an exclusive-OR circuit that XORs a plurality of bits from selected stages of the shift register and feeds back to the first stage of the shift register, and an analog filter having an analog element that limits the band of digital data created from the bits in the shift register of the pseudo-random generator and outputs as an analog signal.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a noise generating device used, for example, for testing the characteristics of communications equipment and audio systems. 2. Description of the Prior Art: Testing the characteristics of communications equipment and audio systems requires a signal source capable of producing random noise having a spectrum uniformly distributed over a specified band. In Figure 3 is shown a prior art noise generator used as such a noise signal source, which generally comprises a digital signal processor (DSP) 11 and a D/A converter 12 . The DSP 11 is a general-purpose programmable processor designed for high-speed digital processing, and into which a pseudo-random number generator 11a for generating pseudo-random numbers and a digital filter 11b for limiting the bandwidth of the pseudo-random numbers are programmed. Digital data output from the DSP 11 is converted by the D/A converter 12 into an analog signal and output on line 13 for noise. One particular drawback associated with the above prior art noise generator is that the equipment is expensive in construction since it requires the provision of the versatile but expensive DSP 11 and the D/A converter 12 for converting the digital data output from the DSP 11 into an analog signal. In view of the above problem, there is a strong need in the art for a noise generating device which can be implemented using an inexpensive hardware configuration comprising a pseudo-random number generator constructed from a shift register, etc. and an analog filter. US 4,855,944 discloses a noise generator with a pseudo-random number generator, using a shift register, and a FIR filter, including an operational amplifier. The outputs of the stages of the register are connected to one input of the operational amplifier. Each output of the register is connected to the input of the amplifier through a resistor, or an inverter and a resistor. Accordingly, the present invention addresses the aforementioned shortcomings of the above known and similar device and methods for generating noise. The present invention is summarized and described in detail below. SUMMARY OF THE INVENTION The present invention provides a noise generating device as set out in claim 1. Noise having a uniform spectrum can be generated by a simple hardware configuration comprising a pseudo-random generator constructed from a shift register, etc. and an analog filter. As a result, the device is inexpensive to manufacture. According to one embodiment of the present invention, a noise generating device is provided which includes a pseudo-random number generator having a shift register that performs shift operations to sequentially shift the bit in the input stage to the next higher significant stage and an exclusive-OR circuit that XORs a plurality of bits from selected stages of the shift register and feeds back to the first stage of the shift register, and an analog filter having an analog element that limits the bandwidth of the digital data created from the bits in the shift register of the pseudo-random number generator and outputs as an analog signal. The following description and annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are however, indicative of just one or more of the various ways in which the principles of the invention may be employed. Other advantages, and novel features of the invention will become apparent from the following detailed description of the present invention when considered in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS This invention may be better understood and its numerous advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1 is a block diagram showing one embodiment in accordance with the present invention; Figure 2 is a further detailed circuit block diagram of the embodiment shown in Figure 1 in accordance with the present invention; Figure 3 is a block diagram showing a prior art noise generator using a DSP; Figure 4a is a block diagram of an eight stage embodiment of the pseudo random number generator in accordance with the present invention; Figure 4b is a detailed circuit block diagram of the present invention using the pseudo random number generator of Figure 4a ; and Figure 4c is a block diagram of the pseudo random number generator of Figure 4a after a subsequent clock cycle. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described below with reference to the drawings wherein like numerals are used to refer to like elements throughout. Figures 1 and 2 illustrate one embodiment of the present invention. Figure 1 is a block diagram of a noise generating device 10 and Figure 2 is a further detailed circuit block diagram of the noise generating device 10 . As shown in Figure 1 , the noise generating device 10 of the present embodiment comprises a pseudo-random number generator 1 and an analog filter 2 . As is described in detail below, in the preferred embodiment the pseudo-random number generator 1 is so configured that shift operations are repeated while feeding back the bits from a plurality of stages of a shift register to the input stage thereof through the exclusive-OR circuit. Therefore, by appropriately selecting the stages from which the bits are fed back to the input stage, pseudo-random numbers of m-sequence (maximum-length linearly recurring sequence) can be generated. With pseudo-random numbers of m-sequence, random bit trains whose period is 2 m can be generated, where m denotes the number of stages of the shift register. Digital data comprising such a bit train can serve as a suitable signal source to generate noise that is uniformly distributed in a multidimensional space. The analog filter 2 is a filter circuit consisting of analog elements such as resistors, an operational amplifier, etc. and is used to limit the bandwidth of the digital data created from the bits in the shift register of the pseudo-random number generator and to output them as an analog signal. As a result, there is provided a noise generating device having a simple and inexpensive hardware configuration comprising a pseudo-random number generator constructed from a shift register, etc. and an analog filter. As shown in Figure 2, the pseudo-random number generator 1 in the exemplary embodiment is a 23-bit scrambler comprising a 1-bit 23 stage shift register 1a and an exclusive-OR circuit 1b and is so configured as to perform shift operations to sequentially shift the bit in the input stage of the shift register 1a to the next higher significant stage synchronized with a clock signal from an oscillator (not shown). In the pseudo-random number generator 1 , as each shift occurs, the most significant bit of the shift register 1a (the bit entered 23 shifts before) is XORed with a lower significant bit thereof (the bit entered p shifts before) by means of the exclusive-OR circuit 1b and the XORed result is input to the least significant stage, thereby generating pseudo-random numbers of m-sequence in accordance with the following recurrence equation (Equ. 1). X i = X i-23 ⊕ X i-p In the thus configured pseudo-random number generator 1 , the maximum period of the bit train to be output is limited by the number of stages of the shift register 1a . In this embodiment, the maximum period is 2 23 - 1. The "p" in the above equation represents the number of stages that is so determined as to prevent the generation of periods shorter than the maximum period. The analog filter 2 is a filter circuit comprising an operational amplifier 2a and a large number of resistors R1-R23 . The outputs of the respective stages of the shift register 1a of the pseudo-random number generator 1 are alternately applied to the non-inverted input (+) and the inverted input (-) of the operational amplifier 2a through the respective resistors R1-R23 . These resistors R1-R23 constitute a resistor array whose values are set so that the digital data comprising the 23 stages of the shift register 1a will have a prescribed passband by the adding and subtracting operations of the operational amplifier 2a. The output of the operational amplifier 2a is fed back to the inverted input (-) through a resistor Rf, and the non-inverted input thereof is grounded via a resistor Ra. In the thus configured noise generating device of the present embodiment, the pseudo-random number generator 1 sequentially generates digital data which displays pseudo-random numbers of m-sequence by causing the shift register la to perform shift operations. The digital data is passed through the analog filter 2 where its bandwidth is limited, and is output as an analog signal on line 3. Thus, according to the present embodiment, the pseudo-random number generator 1 of simple hardware configuration comprising the shift register la, etc. generates random digital data, which is output as an analog signal through the analog filter 2 similar to a D/A converter in a hardware configuration; therefore, the noise generating device 10 is inexpensive to manufacture. Briefly comparing the operation of an embodiment of the present invention to that of a conventional noise generating device, reference is made to Figures 4a to 4c which illustrate an eight stage embodiment of the present invention. In accordance with the above described m-sequence method represented by Equ.1, an initial value is set in the shift register la. In the exemplary embodiment, an initial "10110110" is placed in the contents of the shift register 1a using known techniques. As is illustrated in Figure 4b , the contents of each stage in the shift register 1a determines whether the corresponding resistor R1-R8 is connected to a logic " 1 " level (e.g., 5 volts) or a logic "0" level (e.g., 0 volts). Thus, those stages in the shift register 1a which contain a "1" are represented in Figure 4b as having a output which connects the corresponding resistor to the 5-volt supply. Similarly, those stages in the shift register 1a which contain a "0" have an output which connects the corresponding resistor to a 0-volt ground. The noise voltage is provided on line 3 as described above. Synchronizing with a clock signal to the shift register 1a from, for example, an oscillator (not shown), the shift register 1a starts shifting as is conventional. As a result, the output of the exclusive-OR circuit 1b is input to the least significant stage as described above. Figure 4c illustrates the contents of the shift register 1a from Figure 4a after one clock cycle. As a result, it will be appreciated that the noise voltage on line 3 will change with each successive shift in the shift register 1a . The above steps are repeated with each clock cycle. Therefore, the pseudo-random number generator 1 generates random numbers resulting in noise whose spectrum is uniformly distributed in a multidimensional space. As a result, more random noise can be obtained as compared with the prior art. Briefly describing a prior art approach for generating noise, a linear combination method using the algorithm (X n = aX n-1 + C) (mod M) often is used wherein, for example, M = 256, a = 45 and C = 1. Such an algorithm is programmed in a 32-bit digital signal processor. The random number value is calculated by setting the initial value X 0 = 1. X 1 is given by X 1 = 45 x 1 + 1 = 46 expressed by 32 bits 46 ÷ 256 = 0...46. The value 46 is input to the digital filter as a random number. Digital data is output to a D/A converter after the filter operation, and then a noise voltage is obtained by the D/A conversion. Subsequently, the next random number value is calculated, i.e., X 2 = 45 x 46 +1 = 2071 2071 ÷ 256 = 8...31. The number 31 is input to the digital filter as a random number. Thereafter, the same steps are repeated. It will be appreciated that random numbers obtained according to the above prior art approach will have a regularity of lattice structure in a multidimensional space, or will not be as random as that provided by the present invention.

Claims: A noise generating device (10) comprising: generating means (1) for generating pseudo-random data, said generating means (1) comprising a shift register (1a) which performs shift operations to sequentially shift a bit in an input stage to a next higher significant stage and an exclusive-OR circuit (1b) which performs an exclusive-OR operation between a pair of bits from selected stages of the shift register (1a) and feeds back to the input stage of the shift register (1a); and means (2) for generating an analog signal as a function of the respective outputs of the stages of the shift register (1a), the analog signal generating means (2) including an operational amplifier (2a); characterized in that the respective outputs of the stages of the shift register (1a) are alternately applied to the non-inverting and inverting inputs of the operational amplifier (2a) through respective resistors (R1-R23). The noise generating device (10) of claim 1, wherein said means (2) for generating an analog signal is a filter means for receiving the pseudo-random data and outputting an analog signal, the filter means comprising an analog element for limiting the bandwidth of the digital data signal generated from the bits of the shift register (1a) of the generating means (1), and the operational amplifier (2a). The noise generating device (10) of claim 1 or claim 2, wherein the shift register (1a) is a 1-bit N-stage shift register (N is a natural number greater than 1); and the pair of bits from selected stages of the shift register (1a) includes the most significant bit thereof. The noise generating device (10) of claim 3, wherein N equals 23.

Inventors: MURATA YASUMOTO, NISHIWAKI YUJI, YOSHIKAWA SHUICHI, MURATA, YASUMOTO, NISHIWAKI, YUJI, YOSHIKAWA, SHUICHI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: G06J1
IPC codes: H03K3, G01R31, H03M1, G06J1, H03B29