Generation of horizontal sync pulse

Abstract: A system eliminates the adverse effects of serration and equalization pulses (periodically generated during the vertical sync interval) in regulating the frequency of horizontal sync pulses. These sync pulses provide timing information to regulate a video display. The system includes circuitry for stripping and processing the horizontal and vertical sync signals and the serration pulses from the video signals. These pulses are introduced to a first AND gate and through a first delay line to an input of a second AND gate. Frequency divider output signals are introduced to the first AND gate and to a third AND gate through a second delay line having an equal delay with the first delay line. The output from the first AND gate passes to second inputs of the second and third AND gates. The second and third AND gates produce signals which represent the time difference between the sync and divider output signals and which have a maximum time difference equal to the delays of the delay lines. In doing so, the gates eliminate the effects of the serration and equalization pulses. A phase comparator compares the times of occurrence of the second and third AND gate signals and introduces to a low pass filter the signals representing the time difference. A voltage controlled oscillator produces a signal having a frequency dependent upon the magnitude of the output voltage from the filter. The frequency of the oscillator signals is passed to a frequency divider. The resultant divider signals are introduced to the first AND gate and the second delay line.

Description: This invention relates to a system for generating sync pulses in video signals representing video images. More particularly, the invention relates to a system for eliminating the effects of serration and equalization pulses in generating sync pulses in video signals representing video images. Video images are generally represented by video signals produced in a raster scan. In such a raster scan, a horizontal sync pulse is produced at the beginning of the video signals representing each horizontal line. A vertical sync pulse is also produced at the end of the video signals representing a complete image. When the vertical sync pulse is produced, there is a relatively long blanking period during which the beam producing the image is returned from the lower right corner of the screen to the upper left corner of the screen so that a new raster scan can be initiated. During this blanking period, serration and equalization pulses are produced periodically to define successive intervals in the vertical blanking period. One purpose of the sync pulse defining the beginning of each horizontal line is to insure that the beginning of each horizontal line occurs on a regulated basis such that the beginning of the successive horizontal line will define a straight vertical line. This assures that the image will be displayed on the screen without any distortion. To accomplish this, the rate of production of the horizontal sync pulses in the video signal is regulated. However, the serration and equalization pulses interfere with this regulation and adversely affect the time for the production of the sync pulses. This prevents the image displayed on the video screen from being as precise as might otherwise be desired. The problems described in this paragraph have existed for a long period of time without correction in spite of full knowledge in the industry of the existence of this problem over such period of time and consideration over this period of time of how to resolve the problem. From US-A 4,974,081 a clock pulse generating circuit is known capable of generating a stabilized clock pulse without being effected by disturbances due to vertical equalization pulses. The clock pulse generating circuit includes a PLL circuit for generating a clock pulse which is phase-synchronised with an input signal. The circuit further includes a synchronising circuit for generating a window signal synchronised with the horizontal synchronisation signal. The synchronisation condition is judged with respect to the composite synchronising signal and a gate circuit permits passage of the composite synchronising signal only during existence of the window signal. The object of the present invention is to provide an apparatus for generating sync pulses under elimination of the effects of the serration and equalization pulses which is simple in structure and may be manufactured at low cost. This object is solved by an apparatus comprising the features of claim 1. Preferred embodiments are subject to various dependent claims. Figure 1 is a circuit diagram, mostly in block form, of a prior art system for generating sync pulses in a video signal; Figure 2 schematically shows timing diagrams illustrating how the sync pulses are regulated by the system of the prior art for regulating the time of occurrence between successive sync pulses; Figure 3 illustrates how noise signals and serration pulses adversely affect the time between the generation of successive sync pulses by the system of the prior art; Figure 4 is a circuit diagram (constituting one embodiment of the invention) in block form for inclusion in the system of Figure 1 to eliminate the adverse effects of the noise signals and the serration and equalization pulses in generating the successive sync pulses at the proper timing intervals; Figure 5 illustrates the generation of the horizontal sync pulses and the vertical sync and serration and equalization pulses in the stages prior to the circuitry shown in Figure 4 and the generation of only the horizontal sync pulses as a result of the operation of the circuitry shown in Figure 4; Figure 6 schematically shows timing diagrams illustrating the timing relationship of pulses produced at strategic terminals in the circuitry shown in Figure 4 when the pulses are produced within particular time limits controlled by such circuitry; Figure 7 schematically shows timing diagrams illustrating the timing relationship of the pulses produced at such strategic terminals when the pulses are produced outside of such particular time limits; Figure 8 shows timing diagrams illustrating how fast the system of this invention responds to correct errors in the timing of the horizontal sync pulses even during a vertical retrace period when serration and equalization pulses are produced. A prior art circuit system is shown in Figure 1 and generally illustrated at 10. The system 10 includes a stripper 12 which receives a video signal on a line 14 and strips the horizontal and vertical sync signals and the serration and equalization pulses from the line. The horizontal pulses are illustrated at 16 in Figure 3; the vertical sync pulses are illustrated at 17 in Figure 3; and the serration and equalization pulses are respectively illustrated at 18 and 19 in Figure 3. The horizontal sync pulses 16 are produced at the beginning of each horizontal line to provide a timing for the video signals in that line. The vertical sync pulses 17 are produced at the end of the scanning of the bottom horizontal line in a frame and until the beam has been returned to the beginning of the scanning of the top horizontal line. The serration pulses 18 are produced during the vertical sync pulse 17 to provide a timing during the vertical sync pulse. The equalization pulses 19 are produced at the beginning and end of the vertical sync pulse. The sync pulses from the stripper 12 are introduced to a processor 20 which separates the horizontal and vertical sync pulses and introduces these sync pulses to an input terminal (A) of a phase detector 24 in a phase-locked loop generally indicated at 26 in Figure 1 and shown in broken lines in that Figure. The phase-locked loop 26 also includes a low pass filter 28 shown within broken lines and schematically illustrated by a resistor 30, a resistor 32 and a capacitor 34 connected in series between the output of the phase detector 24 and a reference potential such as ground. The output voltage on the terminal common to the resistors 30 and 32 is introduced to a voltage controlled oscillator 36. The output from the oscillator 36 in turn passes to a divider 38 which passes its output to another input (B) to the phase detector 24. The phase detector 24 compares the phases of the sync pulses from the processor 20 and a divided clock signal from the divider 38. These signals are schematically illustrated in Figure 2. For the case where the negative-going edge of a sync pulse 40 from the processor 20 precedes the negative-going edge of a signal 42 from the divider 38, the phase detector 24 produces a positive signal 44. The positive signal 44 is produced only during the period of time between the negative edge of the pulse 40 and the negative edge of the signal 42. The signal 44 may be considered as a control or resultant signal. The signal 44 is introduced to the filter 28 which passes only the low frequency components in the signal. These low frequency components cause the frequency of the signals from the oscillator 36 to be increased. The oscillator 36 produces signals at a suitable frequency such as approximately 14.31818 megahertz. The frequency of this signal is divided by a suitable divider such as 910 to produce signals at a suitable frequency such as 15,750 kilohertz corresponding to the frequency of the horizontal sync pulses 16. Since the frequency of the oscillator signals introduced to the phase detector 24 is increased, the phase difference between the sync pulses from the processor 20 and the divider signals 44 is correspondingly reduced. Figure 2 also illustrates the case where the negative edge of the sync pulse 46 from the processor 20 follows the negative edge of the signal 48 from the divider 38. Under such circumstances, a voltage pulse 50 having a negative polarity is produced by the phase detector 24. This signal is produced only during the period between the negative edge of the divider signal 48 and the sync pulse 46. This signal is filtered by the filter 28 to produce the low frequency components and these components are introduced to the voltage controlled oscillator 36 to reduce the frequency of the signals from the oscillator. After being divided in frequency by the divider 38, these signals are introduced to the phase detector 24 and the difference in time between the sync pulses from the processor 20 and the frequency-divided signals from the oscillator 36 is narrowed. In this way, the frequency of the oscillator 36 is regulated to provide the sync pulses at the desired rate for providing a high resolution of the video image on a screen. When the times of occurrence of the negative edges of the pulses from the processor 20 and the frequency-divided signals from the oscillator 36 are the same, no signal is introduced to the oscillator so that the frequency of the signals from the oscillator remains unchanged. The problem with conventional sync circuits may be readily seen from Figure 1. During the normal portion where a video signal is being generated at the line 14, the sync stripper 12 receives only the horizontal sync pulses 16 and introduces these pulses to the processor 20. However, during the vertical retrace interval, additional sync pulses pass through the processor 20. These additional pulses are the serration and equalization pulses respectively illustrated schematically at 18 and 19 in Figure 3. These pulses occur at times when no horizontal sync pulses 16 are being produced. The pulses 18 cause the phase detector 24 to produce positive pulses which increase the frequency of the oscillator 36. The phase detector 24 outputs a positive level until the next horizontal sync pulse 16 is produced. The net effect of the serration pulses 18 during the vertical retrace period is to increase the frequency of the signals from the oscillator 36 even though no change in frequency is required. The start of the first horizontal sync pulses in the next generation of the video image on the video screen accordingly occurs at an improper time. The equalization pulses 19 produce a similar effect on the timing of the horizontal sync pulses 16. Figure 4 illustrates a circuit generally indicated at 100 and constituting one embodiment of the invention. The circuit 100 includes a line 102 for receiving sync pulses from the processor 20 in Figure 1 and a line 104 for receiving frequency divided signals from the divider 38 in Figure 1. The pulses on the line 102 pass to a delay line 106 providing a suitable delay such as approximately four microseconds (4 µsec.) and to an input terminal of a NAND gate 108. The signals on the line 104 pass to a delay line 110 also providing a suitable delay such as approximately four microseconds (4 µsec.) and to a second input terminal of the NAND gate 108. The output from the NAND gate 108 passes through an amplifier inverter 112 to input terminals of AND gates 114 and 116. A second input terminal of the AND gate 114 receives signals from the delay line 106 and a second input terminal of the AND gate 116 receives signals from the delay line 110. The output terminals of the AND gates 114 and 116 are connected to the input terminals of the phase detector 24 also shown in Figure 1. Figure 5 shows horizontal sync pulses 120 in a first row and the horizontal sync pulses and serration and equalization pulses 122 in a second row. The pulses 120 effectively remain after the circuitry shown in Figure 4 has operated to remove the serration and equalization pulses. The operation of the circuitry shown in Figure 4 in removing the serration pulses 122 (Figure 5) is illustrated by the examples shown in Figures 6 and 7. In the example shown in Figure 6, the sync pulses 130 from the processor 20 precede the divided oscillator signals 132 from the divider 38 by a period of approximately one (1) microsecond (1µsec.). This is indicated in Figure 6 by Δ = 1. The sync pulses from the processor 20 are indicated at A in Figure 6 to correspond to the input terminal A to the phase detector 24 in Figure 1. Similarly, the signals from the divider 38 are indicated at B in Figure 6 to correspond to the input terminal B to the phase detector 24 in Figure 1. The delay lines 106 and 110 respectively delay the signals 130 and 132 by four microseconds (4 µsec.) as indicated respectively at 134 and 136 in Figure 6. The N AND gate 108 and the amplifier inverter 112 in Figure 4 operate to pass a signal only when both the sync pulses 130 and the divider signals 132 have reached a positive level. Thus, the NAND gate 108 and the amplifier inverter 112 operate to produce a signal at the later of the times that a sync pulse 130 has reached a positive level on the line 102 and a divider signal 132 has reached a positive level on the line 104. The signal produced by the NAND gate 108 and the amplifier inverter 112 is introduced to the AND gate 114 as is the signal passing through the delay line 106. The signal passing through the AND gate 114 operates upon the phase detector 24 to obtain an output from the phase detector. This output continues for a maximum period of four microseconds (4 µsec.). Within this period of four microseconds (4 µsec.), the delay line 110 will introduce a signal to the AND gate 116. This signal passes through the AND gate 116 to the phase detector 24 to inactivate the phase detector. The positive signal from the phase detector 24 will have a width just equal to the time difference between the A delayed output 134 and the B delayed output 136. This positive signal causes the frequency of the oscillatory signals from the oscillator 36 to increase, thereby decreasing the period of time between the pulse on the line 102 from the processor 20 and the signal on the line 104 from the divider 38. Figure 7 provides an example of the operation of the circuitry of Figure 4 when the period between the pulse on the line 102 and the divider signal on the line 104 exceeds four microseconds (4 µsec.), the period of the delay provided by each of the delay lines 106 and 110. In the example shown in Figure 7, the time between the pulse on the line 102 and the signal on the line 104 is assumed to be five microseconds (5 µsec.). This is illustrated by a pulse 160 on the line 102 and a signal 162 on the line 104 and is also indicated by Δ = 5 between the rising edges of the pulses 160 and 162 in Figure 7. This causes the NAND gate 108 and the amplifier inventer 112 in Figure 4 to provide an output five microseconds (5 µsec.) after the signal is provided on the line 102. The output signal from the NAN gate 108 and the amplifier inverter 112 in Figure 4 passes immediately through the AND gate 114 since the AND gate has been previously prepared for activation by a signal from the delay line 106. The output from the AND gate 114 is illustrated at 164 in Figure 7. Four microseconds (4 µsec.) after the AND gate 114 starts to pass a signal, the delayed signal on the line 104 passes through the AND gate 116. This is indicated at 168 in Figure 7. This signal causes the phase detector to be reset. Thus, the phase detector 24 output has a positive level for a period of only four microseconds (4 µsec.) even though the period of time between the pulse on the line 102 and the signal on the line 104 exceeds four microseconds (4 µsec.). This is true whenever the signal on one of the lines 102 and 104 precedes the signal on the other line by a time period in excess of four microseconds (4µs). The circuitry shown in Figure 4 accordingly eliminates any effect of serration pulses 18 or equalization pulses 119 in the operation of the phase detector 24. Figure 8 schematically illustrates the period of time in which applicant's system responds to regulate the time between the generation of successive sync pulses. In Figure 8, vertical retrace pulses are schematically illustrated at 200 and horizontal sync pulses are schematically illustrated at 202. The output signals from the phase detector 24 are schematically illustrated at 204. As will be seen, the regulation in the operation of the phase detector 24 occurs in only a few horizontal lines of the raster scan of a video image. The system described above has certain important advantages. It regulates the frequency of the signal from the voltage controlled oscillator 36 so that the horizontal sync pulses occur at precisely controlled periods even during the vertical retrace period and the time immediately after the vertical retrace period. The system of this invention accomplishes this by eliminating any effects of serration and equalization pulses on such regulation. The effects of serration and equalization pulses on such regulation are eliminated by producing control signals for regulating the frequency of the signals from the voltage controlled oscillator during the period between the sync pulses from the processor 20 and the signals from the divider 30 when this period is less than a particular value such as approximately four microseconds (4 µsec.). When the period of time between the pulse on the line 102 and the signal from the divider 38 is greater than four microseconds (4 µsec.), the activation of the phase comparator 24 is limited to four microseconds (4 µsec.).

Claims: Apparatus for generating sync pulses in video signals under elimination of the effects of the serration and equalization pulses, including: means (12,20) for providing sync pulses (130,160) from a video signal (14), means (36,38) for providing oscillatory signal pulses (132,162) having a variable frequency, means (24,106,108,110,112,114,116) responsive to the sync pulses (130,160) and the oscillatory signal pulses (132,162) for producing a control pulse, said control pulse only being generated as long as the sync pulses and the pulses from the oscillatory signal pulse providing means at least partially overlap in time, otherwise no control pulse being generated, said control pulse having a polarity dependent upon the relative order of occurrence in time of the sync pulses and the oscillatory signal pulses and having a duration dependent upon the time difference between the occurrence of the sync pulses (130,160) and the oscillatory signal pulses (132,162), said means (24,106,108,110,112,114,116) being adapted to limit the duration of the control pulse to a particular maximum value if the time difference between the sync pulses and oscillatory signal pulses exceeds this maximum value, and means (26) responsive to the control signal for varying the frequency of the oscillatory signals (132,162) to coordinate such frequency with the rate of occurrence of the sync pulses (130,160). Apparatus according to claim 1, characterized in that the means (24, 106-116) for providing the control signal includes means for providing a particular delay to the sync pulses (130,160) and to the oscillatory signal pulses (132,162) and means for determining the time relationships between particular pairs of the sync pulses (130,160), the oscillatory signal pulses (132,162), the delayed sync pulses (134,164) and the delayed oscillatory signal pulses (136,168). Apparatus according to claim 2 characterized in that the determining means include a NAND gate (108) and AND gates (114,116) responsive to the sync pulses (130,160), the oscillatory signal pulses (132,162), the delayed sync pulses (134,164) and the delayed oscillatory signal pulses (136,168) for determining the polarity and duration of the control signal. Apparatus according to claim 2 or 3 characterized in that the means for providing a particular delay include a first delay line (106) for delaying the sync pulses (130,160) by the particular delay and a second delay line (110) for delaying the oscillatory signal pulses by the particular delay and further include first logic means (114) responsive to the sync pulses, the oscillatory signal pulses and the delayed pulses from the first delay line (106) to produce a first output and further include second logic means (116) responsive to the sync pulses, the oscillatory signal pulses and the delayed signals from the second delay line (110) to produce a second output and wherein a phase detector (24) is responsive to the first and second outputs to produce the control signal. Apparatus according to claim 4, characterized in that the first logic means (114) are operative only upon the simultaneous occurrence of the sync pulses, the oscillatory signal pulses and the delayed sync pulses from the first delay line (106) to produce the first output and the second logic means (116) are operative only upon the simultaneous occurrence of the sync pulses, the oscillatory signal pulses and the delayed oscillatory signal pulses from the second delay line (110)to produce the second output.

Inventors: COLLES JOSEPH H, COLLES, JOSEPH H.
Applicants: BROOKTREE CORP, BROOKTREE CORPORATION
Application year: 1992
Main classification: H04N5
IPC codes: H04N5