Regulated delay line

Abstract: Three delay lines (10,12,14) may have common characteristics. The first delay line (10) delays the rising edge of an input signal and a first inverter (20) inverts this signal to provide a falling edge. A second inverter (24) inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line (12) in a second path with the second inverter (24). The signals from the two paths may be introduced to a comparator (22) which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines (10,12) to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line (14) to adjust its delay in accordance with the adjustments in the delays in the first and second delay lines (10,12). In this way, the third delay line (14) provides the same time for rising edges and falling edges in data signals introduced to the line.

Description: The present invention relates to a delay circuit means and, in particular, to a delay circuit means for providing the same time delay for rising edges and falling edges in signals introduced to the delay means. JP-A-6369315 discloses a circuit having a first delay path 6 and a second delay path 11 which both receive the same input signal. Each delay path 6, 11 delays the input signal and the delayed difference is detected through the combined functions of units 12, 13, 14, 15, 8 and 9. The resultant delay difference signal is used to control the supply voltage to one of the delay paths and thus to control the delay characteristic of this delay path. JP-A-61103312 discloses a circuit in which an unbalance of the delay characteristic to leading and trailing edges is compensated by serially connecting two delay circuits 6 and 8, wherein the first delay circuit 6 receives an inverted version of the input signal and the second delay circuit is a delayed version of the original input signal through use of an additional inverter 7. According to JP-A-5950610 the unbalance of the delay amount a P and N-channel MOS-pair is corrected by impressing a control voltage to the gates thereof. Then, the unbalance is detected in accordance with the delay amount at the leading and trailing of an output waveform and, based on this difference, a further control signal is generated which is applied to the other gate. In digital circuitry, the propagation delays in a delay line for signals having rising characteristics are generally different from the propagation delays for signals having falling characteristics. This results from differences in the active components in the circuitry and also possibly from the propagation of the signals with the rising characteristics in different paths from the propagation of the signals with the falling characteristics. However, in an ideal delay line, it is desirable to have the same delay in the rising edge of a signal as in the falling edge of the signal regardless of the data being propagated and regardless of the delay provided by the delay line. Such a delay line may be considered to provide "delay symmetry". Prior attempts in providing "delay symmetry" in a delay line have been non-adaptive. In other words, by a careful design of electrical circuitry or by a careful layout of electrical circuitry on an integrated circuit chip or by a one-time adjustment such as the laser trim of circuitry on an integrated circuit some degree of delay symmetry has been attained. However, this delay circuitry has been attained by these methods only at some unique condition such as nominal processing of a particular voltage at a particular temperature. An example of the design approach specified in the previous paragraph is to cascade paired, identical, inverting delay lines each of which has asymmetrical delays. To achieve net symmetrical delays in the paired delay lines, attempts have been made to match output loads to the output and input characteristics of the delay lines. In these attempts, careful attention has had to be paid to ensure that each of the delay lines receives substantially the same input source characteristics and output loading as the other delay line. For simplicity, the delay lines have generally received a non-adjustable voltage to control delay so that the circuitry including the delay lines has provided no adjustable means for compensating for asymmetry. The circuitry described in this paragraph has been particularly employed in ring oscillators for producing output signals with a fifty percent (50%) duty cycle. In another example in the prior art, CMOS inverters of the n and p type have been converted into delay elements by inserting current sources in series with the inverters to constrain the operation of the inverters. The current sources have been set, typically by current mirroring techniques, to provide matched values in an attempt to provide delay symmetry in the inverters. However, the results are strongly dependent upon the layout of the circuitry on an integrated circuit chip and upon the threshold of the gates in the current sources. These gate thresholds become somewhat indeterminate because of the characteristics of the current sources, thereby limiting the ability of the circuitry to provide delay symmetry. It is the object of the present invention to provide an improved delay means having symmetrical delay for rising and falling edges. This object is solved by the subject matter of claim 1. Preferred embodiments of the present invention are the subject matter of the dependent claims. In the drawings: Figure 1 is a circuit diagram of one embodiment of the invention; Figure 2 illustrates voltage characteristics at strategic terminals in the circuitry shown in Figure 1; and Figure 3 illustrates the construction in additional detail of one of the stages included in the embodiment shown in Figure 1. In the embodiment shown in Figure 1, three (3) delay lines 10, 12 and 14 are provided, all preferably with common characteristics. Each of the delay lines 10, 12 and 14 is adapted to provide a delay with variable characteristics dependent upon the characteristics of the voltage introduced to the delay line from an output line 16. An input signal is introduced to the delay line 10 from an input line 18. The output from the delay line 10 passes to an inverter 20, the output of which is connected to a comparator 22. The input signal on the line 18 is also introduced to an inverter 24 which preferably has common characteristics with the inverter 20. The output from the inverter 24 is introduced to the delay line 12 and the output from the delay line is introduced to the comparator 22. The output from the comparator 22 is introduced to a charge pump 26 having characteristics of operating as a low pass filter. The control voltage on the line 16 is obtained from the operation of the charge pump 26. An input signal introduced to the input line 18 is illustrated at 30 is Figure 2. This signal is delayed by the delay line 10 by a time tdr to produce a signal indicated at 32 in Figure 2. The delayed signal 32 is then inverted by the inverter 20 as indicated at 34 in Figure 2. As will be seen, the inverter 20 provides an additional delay tiF in the delayed signal 32 to produce the signal 34. This signal 34 is introduced to one input terminal of the comparator 22. As will be seen, the signal 34 has a falling edge whereas the input signal 30 has a rising edge. The input signal 30 with the rising edge on the line 18 is also introduced to the inverter 24 which inverts the signal to produce a signal 36 with a falling edge. As will be seen, the falling edge of the signal 36 is delayed by a time tiF with respect to the rising edge of the signal 30. The delay provided by the inverter 24 corresponds to the delay provided by the inverter 20 because the inverters 20 and 24 have common characteristics. The inverted signal 36 is delayed by the delay line 12 by a time tDF. The delayed signal is illustrated at 38 in Figure 2 and is introduced to a second input terminal of the comparator 22. As will be seen, the delay line 10 and the inverter 20 provide one path. The total delay of the input signal 30 in this path is tDR + tiF. Similarly, the inverter 24 and the delay line 12 provide a second path. The total delay of the input signal 30 in this path is tDF + tiF. Since the delay tiF in provided by the inventor each of the two paths is the same as in the other path, any difference in the delay provided in the input signal 30 in the two paths is tDR + tiF - (tDF + tiF) = tDR - tDF where tDR - tDF = the difference in the delay imparted to the input signal 30 in the two different paths. The comparator 22 is constructed to provide a binary signal having a first logic level (representing a binary "1") when the falling edge of the signal 34 occurs before the falling edge of the signal 38. In like manner, the comparator 30 provides a signal having a second logic level (representing a binary "0") when the falling edge of the signal 38 occurs before the falling edge of the signal 34. The binary signal from the comparator 22 is indicated at 40 in Figure 2 when the binary signal has a logic level indicating a binary "1". This signal is sampled by the charge pump 26 at a particular time (indicated at 42 in Figure 2) after the signal is produced on a steady state basis rather than on a transient basis. The sampled signal is introduced to the charge pump 26. The charge pump 26 acts in part as a low pass filter to introduce the output signal from the comparator 22 to the charge pump 26 at a low frequency. When the output signal from the comparator 22 has a logic level representative of a binary "1", the magnitude of the output voltage VCS on the line 16 from the charge pump 26 is changed (e.g. increase in magnitude) in one direction. The magnitude of the output voltage VCS on the line 16 from the charge pump 26 is changed in an opposite direction (e.g. decrease in magnitude) when the output signal from the comparator 22 has a logic level (indicated at 44 in Figure 2) representing a binary "0". The voltage VCS on the line 16 is introduced to the delay lines 10 and 12 to adjust the relative delays in these delay lines so that the difference in time between the time delay tDR in the first delay path and the time delay tDF in the second delay path will be minimized. In this way, the rising and falling edges in each of the delay lines 10 and 12 are provided with delay symmetry. The voltage VCS on the line 16 is also introduced to the delay line 14 having common characteristics with the delay lines 10 and 12. As will be appreciated, the delay lines 10, 12 and 14 can be particularly provided with common characteristics when they are disposed on an integrated circuit chip. The delay line 14 receives data, preferably digital, at its input terminal from an input line 50. Since the delay line 14 receives the control voltage VCS, it provides a signal with symmetrical rising and falling edges in the same manner as discussed above for the delay lines 10 and 12. In this way, the delay line 14 delays data on the line 50 on a controlled basis to provide output data with symmetrical rising and falling edges. Figure 3 illustrates a circuit constituting one embodiment of the comparator 22 in the system shown in Figure 1. The embodiment shown in Figure 3 includes a pair of stages 60 and 62 preferably having common characteristics. Each of the stages includes a CMOS "OR" gate and an inverting amplifier to provide an "NCR" logic gate. The stage 60 has a first input terminal connected to the output of the inverter 20 in Figure 1 and a second input terminal connected to the output of the inverter 62. A first input terminal of the stage 62 receives the output from the delay line 12 and a second input terminal of the stage 62 receives the output from the stage 60. The output of the stage 60 is introduced to the charge pump 26. When the inverter 20 provides an output with a falling edge as indicated at 34 in Figure 2 and the output of the inverter 62 is low, the "OR" gate in the stage 62 passes a signal which is inverted by the inverting amplifier in the stage to produce a voltage of high amplitude. This voltage is sampled and the sampled voltage is introduced to the charge pump 26 to provide a change in one direction in the magnitude of the voltage VCS from the charge pump. The voltage of high amplitude on the output from the stage 60 is introduced to one of the inputs to the "OR" gate in the stage 62. This causes the "OR" gate in the stage 62 to pass a signal. This signal is inverted by the amplifier in the stage 62 such that a voltage of low amplitude is produced by the stage. At the same time, the stage 60 produces a voltage of high amplitude on its output terminal. It may sometimes happen that the falling edge of the signal in the delay line 12 occurs before the falling edge of the signal from the inverter 20. At such times, a high voltage is produced on the output of the stage 62 and a low voltage is produced on the output of the stage 60. The low voltage on the output of the stage 60 is sampled and this sampled voltage is introduced to the charge pump 26 to obtain a change in the magnitude of the voltage VCS from the charge pump in an opposite direction to that discussed previously. The apparatus described above has certain important advantages. It provides a servo system for directly measuring the effects of a delay line on an input signal and for controlling these time effects to provide a signal with symmetrical rising and falling characteristics. It provides this control on a digital rather than an analog basis. Furthermore, the servo control is provided by two parallel paths each having the same input impedance and output loading as the other. However, such constraints are not provided for the delay line 14, which responds to the digital data to be processed. As a result, the delay line 14 is free to face optimally with any components or stages associated with the delay line. There are other advantages obtained from the system of this invention. For example, the delay lines 10 and 12 are not constrained to be either inverting or non-inverting. Furthermore, the system does not require any configuration or layout matching between the path providing rising edge delay and the falling edge delay in any delay line. Rather, in this invention, symmetry between the rising and falling edges in the signal in the delay line 14 is obtained by adjusting the delay tDR in the path including the delay line 10 and the delay tDF in the path including the delay line 12 so that these delays are equal.

Claims: Delay circuit means comprising: first means (10, 20) for delaying an input signal and for inverting the delayed input signal to provide a first resultant signal, second means (24, 12) for inverting the input signal and for delaying the inverted input signal to provide a second resultant signal, third means (22) responsive to said first resultant signal and said second resultant signal for providing an indication of a difference in delay between said signals, and fourth means (26, 16) responsive to the indication from the third means for adjusting the delays provided by said first and second means in a direction to minimise any differences in delay between said first and second resultant signals. Delay circuit means according to claim 1, wherein said first means includes first delay means (10) and the second means includes second delay means (12) having substantially the same characteristics as the first delay means. Delay circuit means as set forth in either claim 1 or claim 2, further including, fifth means (14) providing a delay adjustable by the fourth means in accordance with the adjustments made by the fourth means in the delays in the first and second means. Delay circuit means according to claim 2 or 3, wherein said fifth means includes third delay means (14) having delay characteristics corresponding substantially to the delay characteristics of the first (10) and second (12) delay means. Delay circuit means according to any of the preceding claims wherein said third means (22) includes a comparator. Delay circuit means according to any of the preceding claims wherein the first and second inverting means have substantially identical characteristics. Delay circuit means according to claim 5 wherein said comparator includes two NOR-gates, a first input terminal of the first NOR-gate receiving said first resultant signal and a second input terminal of said first NOR-gate receiving the output of the second NOR-gate, a first terminal of the second NOR-gate receiving said second resultant signal and a second input terminal of the second NOR-gate receiving the output of said first NOR-gate and wherein the output of said first NOR-gate indicates the delay between said first resultant signal and said second resultant signal. Delay circuit means according to any of the preceding claims wherein said fourth means (26, 16) includes a low-pass filter means. Delay circuit means according to claim 7, wherein said low-pass filter means includes a charge pump circuit.

Inventors: LOU PERRY W, LOU, PERRY W.
Applicants: BROOKTREE CORP, BROOKTREE CORPORATION
Application year: 1992
Main classification: H03K5
IPC codes: H03K5