Signals generator having not-overlapping phases and high frequency

Abstract: A non-overlapping phase, signal generator (1) comprises first and second loop oscillators (O1,O2) including cascaded inverters. Defined in each cascade of inverters are first and second circuit nodes between the inverters. Between the first node (2) of the first oscillator and the second node (3A) of the second oscillator, there is connected a transistor having a control terminal connected to the first node of the second oscillator. Connected between the first node (2A) of the second oscillator (O2) and the second node (3) of the first oscillator is a transistor having a control terminal connected to the first node of the first oscillator (O1).

Description: This invention relates to non-overlapping two-phase, signal generators useful in integrated circuits for very high frequency applications, i.e. frequencies lying close to the upper limit allowed by the integration technology, in particular to such generators as are intended for voltage booster and CMOS-type memory devices. There are many applications that require the availability of non-overlapping two-phase signals having an at least near-square waveform and a "non-overlap" characteristic whereby they should be iso-frequential and substantially in phase opposition. An example is disclosed in the European Patent No. 0 350 462. At the highest frequencies and as may be appropriate for particular applications, it can be accepted that the leading and trailing edges of a waveform be other than true vertical. Two iso-frequential signals ϕ1 and ϕ2, substantially in phase opposition and having near-square waveforms, can be obtained conventionally using a loop oscillator consisting of an odd number of cascaded inverters; if the outputs from two adjacent inverters to each other are taken to drive the set (S) and reset (R) inputs of a set-reset type of flip-flop wherein the output signals are both zero when the set and reset inputs are both one, then the output signals from the flip-flop (Q, Q ) will fill the above requirements; in fact, each output, Q and Q , can only switch from a logic level of 0 to a logic level of 1 after the other output has attained a logic level of 0. The logic level "1" usually corresponds to the signal "active" phase. Alternatively, the output of just one of the loop inverters may be taken and the flip-flop driven with that signal and its negated, as obtained therefrom by means of an inverter. In either cases, the oscillation period, and hence the repetition period of the generated signals, will be equal to the sum total of the switch times of the oscillator inverters. Where the phase "non-overlap" time is to be increased, an even (and normally equal) number of inverters may be connected in each of the two positive feedback paths of the flip-flop, as conventionally implemented, for example, with two logic gates of the NOR type. However, where a very high signal frequency is sought, the number of the inverters comprising the loop oscillator should be quite small; in the extreme, a loop formed of as few as three inverters could be used, with each inverter comprising transistors of small dimensions in order to minimize the switch times. In this case, the switch times for the available signals at the various nodes in the loop, and those required by the logic gates which make up the flip-flop, are not negligible compared to oscillation period (as is the case, instead, with a large number of stages in the loop), thereby the two signals Q and Q would be active for an extremely short time, and as a result, they may be unable to apply their drive function to the circuit for which they have been generated. A very high signal frequency becomes necessary, for instance, where the non-overlapping phase signals are used, as mentioned, to drive a voltage booster device which is to afford high output current capabilities; the deliverable current being indeed directly proportional to the frequency of the drive signals. Voltage booster circuits are also employed in integrated storage devices for write functions in the cells. In the instance of non-overlapping two-phase signals operating at the limits allowed by the integration technology, a small overlap in the signal active phases and less-than-true "verticality" of the fronts and backs of the signals are considered to be acceptable on condition that the active phase times be sufficient. It is an object of this invention to provide a non-overlapping phase signal generator which exhibits, when compared to prior art generators, improved "non-overlap of phases" at the highest frequencies, without involving any substantial reduction in the active phase times. A further object of the invention is to ensure proper operation of the non-overlapping phase signal generator at the highest frequencies irrespective of the technology employed for its integration. These objects are achieved by a signal generator as defined in the characterizing portions of Claims 1 and 8. The features and advantages of a non-overlapping two-phase signal generator according to the invention will become apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a diagram, partly in block form, of a non-overlapping phase signal generator according to the invention; and Figure 2 shows a circuit embodiment of the diagram in Figure 1 for its integration by CMOS technology. The circuit embodiment of a non-overlapping phase signal generator according to the invention comprises, as shown in Figure 1, two paired oscillators Q1 and Q2 substantially identical with each other (both as regards their circuit pattern, and their corresponding components and integration layout). In this embodiment, each oscillator comprises three inverters, I11, I21, I31 and I12, I22, I32 respectively, connected in a loop, whereby the two oscillators have a very a high frequency of oscillation if the inverters are suitably dimensioned. Of course, solutions are also possible which employ a larger number of inverters in each loop. The two oscillators, which have ideally the same frequency of oscillation, are operated in phase opposition. For this purpose, a control device is provided according to the invention which can maintain the phase difference between the two oscillators at 180°, and drive it to this value if found different. Connected between the two loop oscillators are, in fact, two field-effect transistors in the embodiment shown that may be integrated by CMOS technology, which transistors function as switch means actuated automatically by the polarity condition of the signal in the loops of the two oscillators. In the embodiment shown of oscillators having three cascaded inverters, a first transistor Mc has its gate terminal connected to a circuit node 2 between the first inverter and the second inverter of oscillator O1, and is connected with its source and drain terminals between a circuit node 3, across the second and third inverters of oscillator O1, and a first circuit node 2A, across the first and second inverters of oscillator O2. A second transistor Mca has its gate terminal connected to the circuit node 2A and is connected with its source and drain terminals between the circuit node 2 and a second circuit node 3A, across the second and third inverters of the second oscillator O2. The two nodes 3 and 3A constitute the two signal outputs F and F. The signals being output generally are not applied to a load directly, but rather through suitable circuit means, commonly referred to as drivers in the pertinent literature. The principle on which a generator according to the invention operates will be now described. In normal operation of the oscillators, as the voltage on node 2 becomes high, the voltage on node 3 becomes low; accordingly, the transistor Mc will be turned on and bring the voltage on node 2A to a low, should not the latter be at a low already. A similar function (driving the node 2 to a voltage low as the voltage on the node 2A is at a high) is served by transistor Mca. The waveforms of the voltages present on the nodes 2 and 2A, and hence those for the nodes 3 and 3A, which represent the outputs F and F of the two oscillators, are therefore held in phase opposition, or else driven to this condition, as desired. Thus, the generation can be obtained of two signals at a very high frequency which have substantially non-overlapping complementary waveforms. Phase control of the ouput signals from both oscillators is very good even in the presence of a mismatch, as may exist within an integrated circuit between corresponding elements of the two oscillators, Thus, the oscillation frequencies of the paired oscillators will be the same even in the presence of such mismatches, so that the waveforms generated by both oscillators can be isofrequential and substantially non-overlapping. The two blocks denoted by the references D1 and D2 (drivers which may be either inverting or non-inverting) serve, as mentioned, the function of driving the load circuit, and may be embodied in any conventional manner. In fact, to attain a high frequency of operation, the transistors used in the two oscillators generally have small dimensions and cannot drive directly any higher load capacitance than a modest value. The driver blocks are effective to minimize the capacitive load actually present on the oscillator outputs ( F and F), and to match the latter to the input capacitances of the circuit to be driven, thereby optimizing the oscillator operation and minimizing the switch times for the signals which drive the load circuit. Of course, the two blocks D1 and D2 should be substantially identical with each other (both circuit-wise and as far as the corresponding components and the integrated circuit layout are concerned) to ensure identical paths for the two complementary signals. A circuit pattern that embodies the generator proposed herein is illustrated by Figure 2. In this embodiment, each oscillator has one of the inverting elements implemented by a Schmitt trigger (blocks T1 and T2, of conventional construction), to thereby make triggering more reliable (by virtue of the high voltage gain afforded by this circuit block within its switch voltage range) and achieve improved stability of the oscillation frequency. As for the construction of the drivers, it is well known in this field that for a satisfactory matching of a digital circuit output to a capacitive load, the interposition of a cascade of inverters between the output and the load becomes advisable; the number of the cascade-connected inverters should be selected to suit (the optimum number thereof being selected each time by the designer contingent on specific applications), and each inverter should have larger dimensions than the preceding one. The final stage in the driver may comprise several inverters identical with one another, each arranged to drive a portion of the load circuit separately. For driving very small loads, the driver may comprise a simple inverter or even be omitted altogether and replaced with a short-circuit; in this case the two paired oscillators would drive the load circuit directly. The circuit shown in Figure 2 lends itself for use in applications aimed at substantially no power draw when the signals with two non-overlapping phases are not to be used. For this purpose, the circuit includes circuit means adapted to prevent oscillation of both loops when the generated signals are not used. The inputs of both oscillators are held respectively blocked by two transistors M5 (oscillator O1) and M5A (oscillator O2). In order to have substantially no current static draw, the oscillation voltage of the third inverter (Schmitt trigger) in oscillator O1 and the second inverter in oscillator O2 is cut off, and the node 3A in oscillator O2 is held at ground level. The voltage supply to the two inverters just named is cut off by having the source electrodes of transistors MT4 and M3A connected, instead of to VDD, to the pole PU which is the output of the inverter formed by MI1 and MI2 and is driven through an external signal OP ; the node 3A being held at ground level through a transistor M6A. A transistor M6 is connected in the oscillator O1 to improve matching of the two oscillators (although this is no indispensable expedient). Upon the signal OP becoming low, the oscillation loops are activated, and the two oscillators generate the required output signals (the waveforms of both signals being, of course, the same as those sought on expiration of an initial transient lapse). The external control signal OP is, for example, a signal that would, in voltage booster circuits as employed in storage devices, be generated automatically during the cell "non-write" phase, that is, when no high write voltage from the non-overlapping phase signal generator is required. To close with, a major advantage of a non-overlapping phase signal generating circuit according to the invention is that two standard paired oscillators, substantially identical with each other, can be driven at the desired phases by the sole use of a pair of transistors. The simplicity of such circuit means avoids deterioration in the performance of the two oscillators, even at the highest frequencies. An additional advantage is that the signal active phase times can be optimized using no flip-flops. It is understood that the circuit described and illustrated herein may be modified and altered within the scope of this invention.

Claims: A non-overlapping phase, signal generator circuit comprising: at least first and second loop oscillator circuits (01,02) with cascaded inverters (I11, I21, I31 and I12, I22, I32), each oscillator circuit having first and second circuit nodes (2,3,2A,3A) with at least one of said inverters connected therebetween (I21, I22), characterized in that it comprises: at least first and second switch circuit means (Mca,Mc), each having first and second terminals and a control terminal, the first switch circuit means (Mca) being connected with its first and second terminals between the first circuit node (2) of the first oscillator circuit (01) and the second circuit node (3A) of the second oscillator circuit (02), the second switch circuit means (Mc) being connected with its first and second terminals between the second circuit node (3) of the first oscillator circuit (01) and the first circuit node (2A) of the second oscillator circuit (02), the control terminal of the first switch circuit means (Mca) and the control terminal of the second switch circuit means (Mc) being respectively coupled to the first circuit node (2A) of the second oscillator circuit (02) and the first circuit node (2) of the first oscillator circuit (O1). A signal generator circuit according to Claim 1, characterized in that the second circuit node (3,3A) of each of the two oscillator circuits is a signal output terminal. A signal generator circuit according to Claim 1, characterized in that the first and second switch circuit means (Mca,Mc) are transistors. A signal generator circuit according to Claim 1, characterized in that the first and second switch circuit means (Mca,Mc) are field-effect transistors having gate terminals respectively connected to the first circuit node (2A) of the second oscillator circuit (02) and the first circuit node (2) of the first oscillator circuit (01). A signal generator circuit according to Claim 3, characterized in that it is integrated monolithically by CMOS technology. A signal generator circuit according to Claim 1, characterized in that an odd number of inverters are connected between the first and the second circuit nodes (2,3,2A,3A) of each oscillator circuit (O1,O2).

Inventors: MARCHESI GIANMARCO, TORELLI GUIDO, MARCHESI, GIANMARCO, TORELLI, GUIDO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H03L7
IPC codes: H03K5, H03K3, G11C17, H03L7