Method and system for a multi channel and search global position signal processor

Abstract: There is disclosed a multi channel GPS digital signal processor on a single IC. Each channel (11,12) contains circuitry to process L1 or L2 P(Y) and C/A-code signals. In addition a search processor (123) is included to achieve fast signal acquisition. Low power adder/accumulators (3901-Fig.4) have been designed to provide for a high precision digital oscillator (103; 104) whose output is synchronous to a high speed clock. The IC contains a full low power null detector and eight correlators (111, 113, 115, 117; 112, 114, 116, 118).

Description: TECHNICAL FIELD OF THE INVENTION This invention relates to global positioning signalling and more particularly to a device for achieving multi channel and search processing for a global position system. BACKGROUND OF THE INVENTION The Navstar Global Positioning System (GPS) is used to determine exact geographic position (i.e., latitude, longitude and altitude) absolute velocity as well as the exact time. The navigation device must calculate the position, velocity and the time by determining distance and relative velocity to a series of satellites. The velocity of the receiver is calculated from the doppler frequency shift of signals transmitted from the satellites. This distance is called range and the doppler shift yields range rate. A GPS receiver must receive signals generated from a satellite about 11,000 miles away. A GPS satellite transmits about a 6 watt spread spectrum signal. The satellite and receiver, therefore, has to employ spread spectrum techniques to differentiate the signal from the noise. "Spread spectrum" means that the frequency or instantaneous phase of the signal being transmitted changes as a function of time. Using correlation techniques, the receiver can track the spread spectrum signal coming from the satellite by estimating a duplicate image of the signal. A precise match of the satellite's spread spectrum produces a potential signal processing gain of up to 53 decibels. The use of spread spectrum techniques is essential to receive 6 watts of energy transmitted 11,000 miles away. At the antenna, the GPS signal is about 20 dB below ambient cosmic noise. Prior GPS digital receivers, for instance the receiver disclosed in IEEE PLANS '90 : Position location and Navigation Symposium Record - 1990 - Las Vegas, N.V, USA, 20-23 March 1990, pages 286 - 292, G.B. FRANK et al, performed signal processing functions in the analog domain thereby requiring many expensive discrete components, some of which needed to be tuned to match the circuitry. A common cost/performance tradeoff was to multiplex or sequence one or two channels. By digitizing the GPS signal at the final IF stage and performing all channel signal processing functions digitally in a low cost CMOS IC, GPS receiver performance is greatly improved and cost is reduced. Such a system is disclosed in concurrently filed copending patent application entitled "System and Method for a Digital Navigation Satellite Receiver," which patent is hereby incorporated by reference herein. While the IC presents significant benefit to a GPS receiver, it also presents several problems in building an IC that is low cost and consumes little power. Digitizing the GPS signal at the final IF requires high frequency operation for a signal processing device, i.e. 40 to 60 megahertz for a double sideband GPS signal. Features in a GPS signal processing device which improve performance in hostile environments include full null zone signal integration, multiple correlators, anti-spoofing, and a search processor for fast acquisition. When all these features are combined in one chip, it is very difficult to meet power consumption goals for the device and to minimize the gate count of the device, thereby minimizing its cost. In addition to the cost of the IC, there is a finite limit to the number of gates which can be put on the IC and thus designing a circuit that will fit on a single IC is difficult. EP-A-0 251 156 discloses a global positioning system (GPS) receiver having a common radio frequency section and a separate digital signal processing channel for each of a plurality of satellite signals which are simultaneously being received and processed by the receiver in order to calculate the position, velocity or other desired parameters of the receiver. The radio frequency section receives and processes both of the standard satellite signals on different frequency L1 and L2 carriers in order to provide the multi-channel digital section signals from which the relative phase of the carriers from each of the plurality of satellites may be determined. GB-A-2 153 177 discloses a receiver for a Navstar satellite navigation system including amplification and down conversion to zero i.f. frequencies to produce quadrature signals. Analogue-to-digital converters are provided to digitise separately the quadrature signals and the receiver also includes local digital code generating means and means for correlating the digitised quadrature signals separately with the same locally generated digital codes. Channel signal processing means are provided to which the outputs of the correlation means are applied, the processing means being arranged to control the code and carrier tracking of the receiver. Correction means responsive to control signals generated in the processing means are provided to effect phase rotation of the baseband signal phasor represented by the quadrature signals to effect Doppler tracking in the receiver loop. The receiver includes a digital data memory means loaded with data in the form of "look-up" tables incorporating combinations of signal input conditions, means for applying the digitised quadratised signals a partial address signals for the memory means, and means for generating additional address signals for the memory means, and means for generating additional address signals for the memory means in response to the control signals to effect phase rotation correction by accessing the memory means in accordance with the address signals to produce an output signal for the signal processing means. The present invention provides a digital signal processing (DSP) circuit for use in a global positioning system (GPS) receiver, said DSP circuit comprising, on a single integrated circuit, at least one signal processing channel, said channel including circuitry means for processing a code signal from a satellite of said GPS, characterized in that: Y-code generator circuitry is also provided on said single integrated circuit; said at least one signal processing channel includes circuitry means for processing at least one of a valid P-code signal and Y-code signal from at least one satellite of said GPS, and comprises a multiplicity of correlators; a search processor for fast signal acquisition and a discrete Fourier transform (DFT) module for converting integration samples from the correlators into a multiplicity of frequency bins of sample data are provided, the search processor being arranged to interpolate between the frequency bins to produce a multiplicity of additional bins. We successfully integrated all the aforementioned high performance features into a shortly to be described single IC containing two complete GPS signal processing channels and a search processor for fast acquisition. In order to meet these high performance requirements, we designed a special adder/accumulator architecture for high speed sample integration compatible with full null zone anti-jamming techniques. A similar architecture also reduces gate count in the carrier and code clock digital oscillators. We also designed an architecture for correlators which greatly reduces power and gate count. This architecture also supports full null zone and a feature called "adjacent correlator presumming. Lastly we implemented a digital oscillator architecture which, while running synchronous to the high frequency between 40 and 60 megahertz, the majority of the circuitry runs at one-eighth of that frequency, thereby reducing power. Accordingly, one technical advantage of our IC is that there is provided an adder/accumulator which supports full null zone and greatly reduces power. It is a further technical advantage of our IC that a GPS receiver circuit uses a low gate count adder/accumulator for providing a digital oscillator. It is a further technical advantage of our IC to provide a low power high precision digital oscillator whose output is synchronous to a high speed clock. It is a further technical advantage of our IC that a complete automonous search processor which implements an 8-point DFT and Tong detection algorithm is included which can control either or both channels during search operations. It is a further technical advantage of our IC that there are two channels included, each of which can track L1 or L2 P or Y-code and C/A-code simultaneously and that the Y-code generation function is included in the IC. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present invention may be acquired by referring to the detailed description and claims considered in connection with the accompanying drawings in which like reference numbers indicate like features wherein: FIGURES 1 and 2 show block diagrams of the system; FIGURE 3 shows the prior art of a conventional adder/accumulator digital oscillator; FIGURE 4 shows the approach taken for the code clock generator; FIGURES 5, 6 and 7 show state diagrams for the code clock generator; FIGURE 8 shows state machine operation versus frequency plan; FIGURE 8A shows the three most significant bits of the phase word as a function of S; FIGURE 9 highlights the operational performance of the code clock generator; FIGURE 10 shows a block diagram of the carrier generator; FIGURE 11 shows the carrier generator state diagram; FIGURE 12 highlights operational performance of the carrier generator; FIGURE 13 shows frequency dependent phase bias; FIGURE 14 lists the thirty largest phase settability anomalies; FIGURES 15, 16 and 17 show the phase settability anomalies for the code clock generator; FIGURES 18 and 19 show the phase range of each state for the code clock generator; FIGURE 20 shows the same for the carrier generator; FIGURE 21 shows the non-orthogonal axes for the carrier generator; FIGURE 22 shows the phase settability anomalies for the carrier generator; FIGURE 23 shows prior art for a 6-bit adder/accumulator; FIGURE 24 shows a block diagram of the special adder/accumulator; FIGURES 25-28 show how a special adder/accumulator is built; FIGURE 29 shows a block diagram of the intermediate correlator module; FIGURES 30 and 31 show the pulse generators required for the special adder/accumulator; FIGURES 32-35 discuss valid inputs for this adder/accumulator; FIGURE 36 shows a special cell which was generated to achieve a balanced rise and fall time; FIGURE 37 shows the special adder/accumulator cell; FIGURE 38 shows a 4-bit adder/accumulator with carry; FIGURES 39a and 39b show the adder/accumulator with latches; FIGURE 40 shows a block diagram of the back-end correlator module; FIGURE 41 shows how the eight complex adder/accumulators are built; FIGURE 42 shows how the pulse encoder works; FIGURE 43 shows a detailed circuit of the sample accumulators; FIGURE 44 describes adjacent correlator presumming; FIGURE 45 shows performance without adjacent correlator presumming; and FIGURE 46 shows performance with adjacent correlator presumming. DETAILED DESCRIPTION OF THE INVENTION The P-Code Channel on-a-Chip (PCOAC) of the instant invention is a dual channel GPS signal processor integrated circuit. A 95-pin ceramic pin-grid-array (PGA) contains the 348,300 transistor CMOS gate array. Major features include: two independent GPS channels; a search processor for improved acquisition time; an embedded Y-code generator: system synchronization control; and a 16-bit processor interface. FIGURE 1 shows a block diagram of PCOAC 10. Unused functions can be turned off allowing for a high level of power conservation in applications where power usage and/or heat dissipation is an important consideration. Each channel of circuit 10 is a dedicated signal processing circuit which de-modulates the code and carrier of a GPS signal and performs pre-detection integration. Each channel contains a code clock generator 103 (104), a P and C/A-code generator 105 (106), an L1/L2 carrier generator 109 (110), eight correlators 111, 113, 115, 117 (112, 114, 116, 118) and a noise meter 119 (120). Each of the eight correlators can be selected to operate with C/A-code or P-code. A Y-code generator 108 common to both channels provides independent Y-code for both channels. Search processor 123 and discrete fourier transform (DFT) function 124 improve signal acquisition capability. The DFT separates the sample integration data into seven frequency bins. Search processor 123 interpolates between these seven frequency bins to obtain six additional frequency bins, producing a total of thirteen frequency bins per correlator. The search processor implements a Tong detection algorithm on all eight correlators for each of the thirteen frequency bins resulting in the simultaneous search of 104 search bins per channel. PCOAC 10 supports three frequency plans, 57.7920 MHz, 40.9216 MHz and 40.9200 MHz operation. Several programmable clocks/interrupts 130 are provided to synchronize the host processor to PCOAC operation. Various interrupt schemes are designed to allow trade-offs to be made between system performance, processor throughput requirements and the complexity of the software. A standard 16-bits processor interface 131 is utilized. In order to minimize read/write overhead to the PCOAC, integration samples are buffered 121 (122) and the memory map is designed so that block moves are all that is required for channel updates during normal tracking operations. FIGURE 2 is a block diagram of the top level modules which electrically make up channel A(11) of PCOAC 10: Base Band Module 130 generates several global clocks for system synchronization: Channel Timing Module 101 generates all clocks and synchronization pulses specific to a single channel; Code Generator Module 21 includes a programmable code clock generator, P-code and C/A-code generator/setters, and P-code and C/A-code state advance and retard for search; Y-Code generator Module 108 converts the P-code into Y-code for both channels simultaneously even during code state advances; Front-End Correlator Module 201 provides L1 or L2 carrier generation, a carrier mixer, a P-code and C/A-code delay shift register (to generate eight code phases), code mixers, data wipe-off, and noise meter signal selection; Intermediate Correlator Module 202 performs the first stage of sample integration for eight complex correlators and a noise meter; Back-End Correlator Module 203 performs the final stage of sample integration, and also performs noise measurement for aiding in search and tracking (one per channel); I RAM 204 and Q RAM 205 are two 64 x 16-bit 3-port RAMs per channel for sample integration buffering or to hold intermediate values for DFT calculations; Discrete Fourier Transform (DFT) Module 124 converts integration samples from all correlators of both channels into seven frequency bins of sample data for search operations; Search Processor Module 206 interpolates six additional frequency bins from those provided by the DFT module, performs Tong detection on all thirteen frequency bins of data and retards the code state until a signal is found; Search Processor RAM 207 is a 64 x 16-bit 3-port RAM used by the search processor as a holding register for active Tong counts during search or noise measurement buffering during tracking; Processor Interface Module 131 provides address decode to generate internal read and write strobes, integration sample buffering control, a programmable ring oscillator for test and other miscellaneous functions; Digressing momentarily in order to receive spread spectrum signals, as in a GPS receiver, it is necessary to very closely match the signal generated by the signal source (i.e., the satellite). In GPS, two precisely controllable digital oscillators are required per channel, one to match the code frequency (nominally 10.23 MHz) and one to match the final carrier IF (between 10.1 and 15.1 MHz depending on receiver configuration). To meet nyquist sampling requirements, the PCOAC samples incoming signals at greater than 40 MHz (up to 57.792 MHz depending on which frequency plan is implemented in the receiver). FIGURE 3 shows the most straightforward way (prior art) to implement a high precision digital oscillator, whose output is synchronous to a high speed clock. The circuit uses a loadable adder/accumulator 303, 304 & 305, pipelined as required. This approach was used in a single C/A-code channel or a chip previously developed. Since this device sampled incoming signals at only 12.799 MHz, power was less of a consideration than gate count. However, if on the PCOAC an adder/accumulator of adequate precision (32-bits) were to run a 57.792 MHz, it would consume about 150 mW of power. Since on the PCOAC, four such adder/accumulators are required (two per channel), total power consumed by these digital oscillators would be 600 mW. Using an innovative low power approach, each digital oscillator in PCOAC 10 consumes only 43 mW on average at 57.792 MHz, saving a total of 428 mW per PCOAC or a total of 1.3 watts in a six channel receiver. Unlike the adder/accumulator digital oscillator approach, this approach limits the output frequency of the digital oscillator to a limited range about a center frequency. The more narrow that range is, the more power that can be conserved. Also, this approach requires slightly more gates than the conventional approach (roughly 5 to 30 percent more depending on the number of bits of precision and other design specifics). As shown in FIGURES 4 and 10, this innovative approach is used in the PCOAC for code clock generator 103 (FIGURE 4) and carrier generator 109 (FIGURE 10). An approximation of a part of this approach is used for circuit simplification, causing some phase settability anomalies. Also, the carrier generator generates two 2-bit outputs 90° out of phase. These 2-bits outputs cause some additional phase settability anomalies. Code clock generator 103 shown in FIGURE 4 is designed to generate a P-code clock with a nominal frequency of 10.2300 MHz. Phase and frequency of the P-code code clock is programmable via processor interface 131 (FIGURE 1) and bit latches 3904, 3905, 409. FIGURE 9 shows the frequency range, frequency settability, and phase settability for the three reference clock frequencies of PCOAC 10. The code clock output is generated by dividing down the reference clock by a programmable non-integer divisor. For example, in the 57.792 MHz plan, the reference clock is divided down by 5.649266862 to generate a code clock with a frequency of 10.23 MHz. To minimize power consumption, the code clock generator is designed to run a minimum of circuitry at reference clock frequency. Most of the code clock generator circuitry runs at one eighth the reference clock frequency. The benefit of low power is a tradeoff in performance in phase settability at certain frequencies. State machine 408, which runs at the reference clock frequency, generates the final code clock output. Averaged over time, it divides the reference clock down by the desired divisor. On each reference clock active edge, the state machine advances the phase of the code clock by a fixed number of degrees. A carry input to the state machine modifies the number of degrees the code clock is advanced on a given reference clock active edge. FIGURE 8 shows the number of degrees the code clock phase is advanced on each reference clock and a result of each carry for each of the three frequency plans. This state machine is further illustrated in FIGURES 5, 6 & 7 for the 57.792 MHz plan, the 40.9216 MHz plan and the 40.9200 MHz plan, respectively. The phase advance assigned to each reference clock period and to each carry and the frequency of carries determines the average frequency of the code clock output. Returning to FIGURE 4 (or FIGURE 10), 32-bit adder/accumulator 3901 determines the frequency of the carry input to the state machine. The 32-bit adder/accumulator is clocked once every eighth reference clock. Each time it is clocked, a frequency word provided by the host processor is added to the value held in the accumulator. Every time the accumulator rolls over, a carry signal is generated to the state machine. Therefore, the frequency of carries is calculated as follows: (1) Fcarry = Fref 8 x FW 2 32 where Fcarry is the frequency of carries, Fref is the reference clock frequency and FW is the 32-bit frequency word provided by the host processor. The average frequency of the code clock output is calculated as follows: (2) Fcdclk = Fref x PAref 360 + Fcarry x PAcarry 360 = Fref x PAref 360 + Fref 8 x FW 2 32 x PAcarry 360 = Fref x (PAref + FW/2 35 x PAcarcy) 360 where PAref is the phase advance per reference clock and PAcarry is the phase advance per carry (see FIG 8). Solving this equation for the frequency word (FW) yields the following equation. Carry delay circuit 407 improves instantaneous phase resolution and reduces frequency dependent phase bias. Each carry is delayed a number of reference clocks from the time the adder/accumulator rolls over depending on by how much the adder/accumulator overflows. Ideally, the carry should be delayed by: (4) Dcarry = INT (8 x (1 - AW/FW)) where AW is the value of the word in the accumulator after it rolls over and Dcarry is the number of reference clocks to delay the carry. This approach causes a carry to occur eight reference clocks after when it would occur in a conventional adder/accumulator digital oscillator. This approach exactly matches the ideal performance of a digital oscillator with its adder/accumulator running at reference clock frequency, but uses less power because its adder/accumulator is running at one eighth the reference clock frequency. Implementing the ideal carry delay described above would be difficult, therefore an approximation is implemented. The approximation implement delays the carry in accordance with the following equation: (5) Dcarry = 8 - INT (AW/2 29 ) where Dcarry is the number of reference clocks the carry is delayed. The reason this approximation is not exact for the full range of the frequency word is that the value left in the accumulator after a carry will never be greater than the frequency word, thus limiting the range of reference clock periods by which the carry is delayed. As the frequency word approaches zero, the carry delay is always eight; however, carries are infrequent and therefore phase bias approaches zero. As the frequency word approaches 2 32 -1, carries occur frequently, but the carry delay approaches the correct number of reference clock periods. This is proved by substituting 2 32 for FW into the equation showing the ideal carry delay algorithm, as follows: (6) Dcarry = INT (8 x (1 - AW/2 32 )) = INT (8 - AW/2 29 ) = 8 - INT (AW/2 29 ) The phase bias as a function of the frequency word caused by approximating the carry delay is given below: (7) PBcda = -PAcarry x FW x (FW/2 32 - 1) 2 33 where PBcda is the phase bias as a result of the carry delay approximation. FIGURE 13 illustrates this bias. This phase bias does not degrade closed loop tracking performance. However, it may be important to consider for measuring absolute phase of a signal (for example to generate a precision time mark) or for measuring the relative phase between two signals when the difference between their doppler is significant. To setup initial phase of the code clock, the host processor provides the initial state of the state machine and the initial value of the thirteen most significant bits of the accumulator. The remaining nineteen bits of the accumulator are set to zero when a new code phase takes effect. Since the state machine has either six or eight discrete states, each state represents a range of phase. Since state 100 2 is the state where the clock output changes from zero to one, this state represents an average phase of zero degrees. The range of phase it represents is -30 to +30 degrees for the 57.792 MHz plan and -22.5 to +22.5 degrees for the 40.9216 and 40.9200 MHz plans. FIGURES 18 and 19 illustrate the phase range of each state for the 57.792 MHz plan and the 40.9216 and 40.9200 MHz plans respectively. In other words, instantaneous phase is a function of what state the state machine is in and the value held in the accumulator. Assuming the average value held in the accumulator is 2 31 (half of the maximum value), then phase is expressed by the following equation: where Pcdclk is the code clock phase, NS is the number of states in the state machine, S is the state of the state machine, and AW is the value of the word in the accumulator at any time. S=O is defined as the state where the code clock goes high and all remaining states are numbered sequentially going counter clockwise (see FIGURES 5, 6 and 7). For a desired phase, the host processor provided phase word can be calculated from the following equations. The initial state of the state machine, S, is calculated first using the following equation: where NS is the number of states in the state machine, Pcdclk is the desired code clock phase (must be positive) and S is the state that the state machine must be initialized to. After S is calculated, AW is calculated using the following equation: where PAcarry is phase advance per carry (see FIGURE 8) and AW is the value the adder/accumulator must be initialized to. In this equation, eight is added to force the value of the expression to be positive before taking the modulo. The phase word which the host processor must write out is a function of the initial state of the state machine, S, and the initial state of the adder/accumulator, AW. The three most significant bits of the phase word determine the initial state of the state machine. FIGURE 8A shows the value of the three most significant bits of the phase word as a function of S for all setups. This is derived directly from FIGURES 5, 6 and 7 which show the state assignments for the state machine for each frequency plan. The thirteen least significant bits of the phase word determine the initial state of the thirteen most significant bits of the accumulator: the remaining accumulator bits are set to zero. The following equation shows the value of the thirteen least significant bits of the phase word as a function of AW: (11) PW (13 lsbs) = INT [ AW 2 19 ] A more direct way to calculate the phase word involves using a simple equation and then modifying the result as required. The equation is: Then the result is modified as follows: IF PAcarry < 0 THEN PW = PW EXOR 8191 (invert 13 least significant bits) If NS = 6 AND PW ≥ 24576 THEN PW = PW + 8192 This yields the final phase word for the host processor to write out. During the development of this invention, a problem was found in that the phase is not always finally settable. There are phase settability anomalies depending upon the frequency to which the digital oscillator is set. A description of this problem follows. Code clock average phase is calculated based on the assumption that the average value of the adder/accumulator during a sample integration period is half the maximum value possible (a previous assumption). This is not true in all cases. Code clock phase is actually calculated using the following equation for all cases: (13) Pcdclk = 360 x S NS + PAcarry x [ AW - AA 2 32 ] where AA is the average value of the adder/accumulator for a sample integration period. The average value of the adder/accumulator for a sample integration period is a function of the frequency word and the initial state of the adder/accumulator and is calculated using the following equation: where N is the number of times the adder/accumulator is incremented in a sample integration period. For most frequency words, as N approaches infinity, the average adder/accumulator value is very close to 2 31 and is not effected by the initial adder/accumulator value (AW). However, certain specific frequency words cause the average adder/accumulator value to be a function of the initial acder accumulator value. When this occurs, a phase settability anomaly occurs. The frequency words which cause a phase settability anomaly, and the degree to which phase settability is effected can be determined as follows: 1) Reduce the following fraction as much as possible: (15) n d = FW 2 32 where n is the numerator of the reduced fraction and d is the denominator of the reduced fraction. 2) Phase settability is calculated by the following equation: (16) P stby = 360 NS x d where P stby is the phase settability and NS is the number of states in the state machine. For example, when the frequency word is zero (n=0 and d=1), the adder/accumulator remains at its initial state for the entire sample integration period, thus AA = AW. When AW is substituted for AA in the equation 14, then code clock phase is no longer a function of the initial adder/accumulator value, but only of the initial state of the state machine. This causes a phase settability anomaly, which when the frequency word is zero, does not allow phase settability to a finer resolution than 360 divided by the number of states in the state machine (45° for the 40.9200 and 40.9216 MHz plans and 60° for the 57.792 MHz plan). Other frequency words will result in a finite number of discrete adder/accumulator values evenly spaced apart. For example, if the frequency word is 2 31 (n=1 and d=2) then the value held in the adder/accumulator at any time is one of two values: (17) AW or MOD (AW + 2 31 , 2 32 ). In this case the average value of the adder/accumulator is: (18) AA = AW + MOD (AW + 2 31 , 2 32 ) 2 Thus another phase settability anomaly occurs when the frequency word is 2 31 in which the phase settability is: (19) Pstby = 360 NS x 2 (22.5° for the 40.9200 and 40.9216 MHz plans and 30° for the 57.792 MHz plan). FIGURE 14 shows the phase settability for all values of d which yield a phase settability of 2 degrees or greater. FIGURES 15, 16 & 17 graph these phase settability anomalies with normal code clock generator operating range super-imposed for the 57.792 MHz plan, the 40.9216 MHz plan and the 40.9200 MHz plan, respectively. Values of d which are not binary multiples are not strictly attainable; however, since the sample integration period is not infinite, values for d which are not a binary multiple are effectively attainable. Turning now to FIGURE 10, carrier generator 109 creates an inphase (I) and quadrature (Q) replica of the L1 or L2 intermediate frequency (IF) carrier signal. The output of the carrier generator, called carrier, is generated synchronous to the reference clock. The inphase (I) and the quadrature (Q) parts of the carrier are each two bits. Phase and frequency of the carrier is programmable via the host processor. FIGURE 12 shows the frequency range, frequency settability, and phase settability for the three reference clock frequencies supported by the PCOAC. The carrier is generated using the same principle as is used for generating the code clock. The state machine for the carrier generator operates using the same principle as for the code clock generator state machine. State assignments for the carrier generator are the same for all three PCOAC supported frequency plans. The carrier phase advances 90° per reference clock and either +45° or -45° per adder/accumulator carry. The 45° phase advance or retard per carry (PAcarry) is controlled by a high/low frequency control bit. FIGURE 11 shows the complex carrier output as a function of state. Note that the state machine generates a 2-bit number for each part of the complex carrier at each state. These two bit numbers can either be a -2,-1, +1 or +2. The host processor can set a bit which hard limits the output to +1 and -1. The quadrature carrier lags the inphase carrier by 90 degrees. The adder/accumulator for the carrier generator is exactly the same as for the code clock generator. The average frequency of the carrier output is calculated as follows: (20) FCarrier = Fref 360 (90 + FW 2 35 x PAcarry) where Fcarrier is average frequency of the carrier, Fref is the reference clock frequency, FW is the 32-bit frequency word provided by the host processor and PAcarry is the phase advance per carry (+45 or -45). The carry delay circuit for the carry generator is the same as it is for the code clock generator. The frequency depend phase bias caused by this delay circuit is calculated the same as for the code clock generator. Carrier phase is controlled the same way as code clock phase. The state machine has eight states. Each state represents a phase range of 45 degrees. State 000 represents an average phase of 22.5 degrees. The range of phase which it represents is 0 to +45 degrees. Figure 20 illustrates the phase range of each state. Assuming the average value held in the accumulator is 2 31 (half of the maximum value), the carrier phase is expressed by the following equation: where Pcarrier is the carrier phase, S is the state of the state machine as defined in FIGURE 11, and AW is the current content of the adder/accumulator. The host processor sets the initial state of the state machine and the thirteen most significant bits of the accumulator. For a desired phase, the phase word can be calculated from the following equations. The initial state of the state machine, S, is calculated first using the following equation: (22) S = MOD [ INT [ Pcarrier 45 ] , 8 ] where Pcarrier is the desired carrier phase and S is the state that the state machine must be initialized to as defined in FIGURE 11. After S is calculated, AW is calculated using the following equation: (23) AW = 2 32 x MOD [ Pcarrier PAcarry + 8 , 1 ] where PAcarry is the phase advance per adder/accumulator carry (-45 or +45 degrees) and AW is the value the adder/accumulator must be initialized to. In this equation, eight is added to force the value of the expression to be positive before taking the modulo. The phase word which the host processor must write out is a function of the initial state of the state machine, S, and the initial state of the adder/accumulator, AW. The three most significant bits of the phase word determine the initial state of the state machine. The thirteen least significant bits of the phase word determine the thirteen most significant bits of the accumulator; the remaining bits of the accumulator are set to zero. The following equation shows the phase word as a function of S and AW: (24) PW = S x 2 13 + INT [ AW 2 19 ] A more direct way to calculate the phase word involves using a simple equation and then modifying the result as required. For Pcarrier from 0° to less than 360°, the equation is: (25) PW = 2 16 x Pcarrier 360 Then the result is modified as follows: IF PAcarry < 0 THEN PW = PW EXOR 8191 (invert 13 least significant bits) There are two contributors to carrier phase settability anomalies, the adder/accumulator carry delay circuit and the unequal spacing of states due to having four output levels. Phase settability anomalies resulting from the carry delay circuit have been previously described. only phase settability anomalies resulting from the unequal spacing of states will be described now. The carrier generator state machine has eight states. Ideally these states would be evenly spaced 45 degrees apart. Because the carrier generator has four output levels (-2, -1, +1 and +2), the states are not evenly spaced. FIGURE 21 shows an ideal spacing versus the actual spacing achieved with four output levels. As can be seen from the FIGURE, four states are on one set of orthogonal axes and the other four states are on another set of orthogonal axes. Each set of axes has a phase bias associated with it with respect to the ideal case. The phase bias associated with states 000 2 , 010 2 , 100 2 and 110 2 is 4.065 degrees and with states 001 2 , 011 2 , 101 2 , and 111 2 is -4.065 degrees. Note, when carrier hard-limiting is enabled, the outputs are effectively evenly spaced alleviating the cause of this phase settability anomaly. For most set-ups, the state machine will spend very close to half the time on each set of axes during an integration period, thus the biases cancel. However, some set-ups will cause the state machine to spend significantly more time on one set of orthogonal axes than on the other. Phase bias associated with a set-up is calculated using the following equation: (26) P bias = P e x 8.130 - 4.065 where P bias is the phase and P e is the percentage of time the state machine dwells on an even state (000 2 , 010 2 , 100 2 or 110 2 ) during an integration period. This phase bias, unless compensated for, causes a phase settability anomaly. Frequencies which cause phase settability anomalies are ones which cause the state machine to dwell a significantly different percentage of the time on one set of orthogonal axes than on the other. The carrier generator state machine only changes the set of axes it is on when the adder/accumulator carries. Therefore, frequency words which cause this type of phase settability anomaly are the ones which cause the adder/accumulator to carry an even number of times every odd number clocks. For example, if the adder/accumulator carries twice every five clocks, then two out of every five clocks (40 percent of the time) the state machine will be on one set of axes and three out of every five clocks (sixty percent of the time) the state machine will be on the other set of axes. This results in a phase bias of +/-0.813 degrees, or a phase settability anomaly of 1.626 degrees. Only two frequency words cause this type of phase settability anomaly to be greater than 2 degrees. A frequency word of zero causes a phase settability anomaly of 4.07 degrees and a frequency word of 2/3 x 2 32 causes a phase settability anomaly of 2.71 degrees. FIGURE 22 shows all phase anomalies greater than 2 degrees for the carrier generator as a function of the frequency word. Super-imposed on this graph, is the normal operating range for the carrier generator for each mode of operation. This design approach can benefit any system where power conservation is important and where a high precision digital oscillator is required whose output must be synchronous to a high speed clock. The more bits of precision required and the higher the frequency of the reference clock, the greater the power savings over a conventional adder/accumulator digital oscillator approach. FIGURE 29 shows a block diagram of the intermediate correlator module 202 (FIGURE 2). Each of the eight complex correlators per channel in the PCOAC includes four six bit adder/accumulators, two for in phase accumulation and two for quadrature accumulation. The adder/accumulators function in pairs, one to accumulate positive values and one to accumulate negative values. In addition to the 32 adder/accumulators required per channel for the eight correlators, two adder/accumulators are required per channel to support the noise meter, making a total of 68 adder/accumulators on the chip running at up to 57.792 MHz. This makes power dissipation an issue. Using asynchronous design techniques one of these adder/accumulators takes less than 60 gates and dissipates less than 7 mW. A conventional ripple-adder with a 6-bit register, takes about 90 gates and dissipates about 25 mW. FIGURE 23 shows the block diagram of a conventional adder/accumulator, while FIGURE 24 shows the block diagram of the specially developed adder/accumulator. For 68 adder/accumulators, this is a difference of almost 2,000 gates and, for a system with six complete L1 and L2 channels, this is a difference of about 6.8 watts. Permutation is used elsewhere in the PCOAC and is discussed later. This adder/accumulator is the most significant of many design innovations that make the PCOAC possible. The implementation of intermediate correlator module 202 (FIGURE 2) requires the development of three custom macro-cells, which are combined to form a hard-macro function called ICORR. These three custom macro-cells are: the BIADD6, the aforementioned 6-bit adder/accumulator (binary multiple only), the PULGENA, a pulse generator to drive the two BIADD6s for noise measurements, and the PULGENB, a pulse generator to drive a group of sixteen BIADD6s associated with four correlators. The BIADD6 is a 6-bit adder/accumulator designed for low power operation and low gate utilization. It is implemented using a ripple counter 2402 with a boolean exclusive OR between each stage 2401. (FIGURE 24) FIGURE 25 shows a standard 6-bit ripple counter with a clear direct input. FIGURE 26 shows this same ripple counter with a transmission gate exclusive OR 2603, 2605, 2607, 2609, 2611 between each stage 2502, 2503, 2504, 2505, 2506, 2507 and with the input data gated with a pulse input 2601, 2602, 2604, 2606, 2608, 2610. FIGURE 27 shows the same function as FIGURE 26 but with the transmission gate exclusive ORs replaced with boolean exclusive ORs, 2702 and 2708. These exclusive ORs are used to inject a pulse to any stage of the ripple counter. Boolean exclusive OR gates are required because transmission gate exclusive OR gates which are available produce a glitch which affects circuit operation. The content of the ripple counter is the accumulated value. When the clock input to one of the toggle flip/flops (which comprise the ripple counter) is pulsed, the value 2 n is added to the accumulated value where n (0 to 5) indicates which flip/flop input is pulsed. FIGURE 28 shows the final implementation of the BIADD6 macro-cell. Ripples start from either edge of an injected pulse depending upon the state of the previous flip/flop. The worst case ripple through the BIADD6 is when the BIADD6 contains a 111110 2 and a 2 is added followed by adding a 32. When this occurs, the second flip/flop is clocked on the falling edge of the first injected pulse and the sixth flip/flop is clocked on the rising edge of the second injected pulse. Therefore, the BIADD6 must ripple from the second flip/flop to the last flip/flop during the pulse low time (significantly less than one reference clock period). To provide more margin, negative edge clocking flip/flops are used to reduce propagation delay for a ripple and pulse injection to the last stage is delayed 2807 in order to give more time for a worst case ripple. A pulse generator is also used to provide a short positive going pulse, which also provides more time for the worst case ripple. There are two pulse generators, PULGENA and PULGENB. PULGENA is a custom macro-cell designed to provide short high going pulses for the two BIADD6 cells allocated to the noise meter. FIGURE 31 shows the PULGENA custom cell. The pulse generator works by ANDing 3106 and 3107 the reference clock with a delayed and inverted version of the reference clock 3103, 3104 and 3105 and with the sign bit for the next sample of noise data. PULGENA has two sign inputs, one active high and the other active low. It also has an off input which forces the delayed reference clock low, thus masking the pulse outputs. A great deal of SPICE simulation was required to verify the width of the pulse generated is never too narrow to to be missed by the BIADD6 and is always narrow enough to guarantee the worst case ripple through the BIADD6. PULGENB is a custom macro-cell designed to provide short high going pulses for sixteen BIADD6 cells allocated to one set of four correlators. FIGURE 10 shows the PULGENB custom cell. One pulse generator is used for all sixteen BIADD6s for power conservation. The PULGENB is designed using the same principle as the PULGENA. The BIADD6 custom cell architecture requires that only certain inputs be used, primarily binary multiple only inputs. FIGURE 32 lists the valid inputs for the BIADD6 in all applications. FIGURE 33 shows an example of how two BIADD6 cells are used together to perform the high frequency integration. FIGURE 37 shows inputs which are always invalid and will cause the BIADD6 to operate in a way that is unpredictable. Lastly, FIGURE 35 shows inputs which may produce determinant results depending on the values that are already contained in the BIADD6 circuit. These input values yield determinant results when the following two criteria are met. Two adjacent bits of the adder/accumulator cannot be added to during the same reference clock period, and the bit adjacent to and less significant than a bit being added to cannot be carried into during the same reference clock period. By modifying the BIADD6 cell slightly, it is possible to make an adder/accumulator which is not restricted to adding only binary-multiples. To do this, the boolean logic exclusive OR must have a balanced rise and fall time and the whole adder accumulator must have time to settle between clock edges (both the rising and falling edges are active). Asynchronous pulses occur at the output of these boolean logic EXORs when the data input to the EXOR is pulsed and the previous flip-flop carries. A balanced rise and fall time of the EXOR ensures that this pulse will meet the minimum pulse width requirement for the flip-flop. FIGURE 36 shows the transistor level model of the boolean EXOR used in a previously developed experimental ASIC. Two P transistors are used in parallel to balance the N transistors. The technology used for the PCOAC has balanced P and N transistors, therefore the boolean EXOR in the PCOAC has only four P transistors. FIGURE 37 shows the special adder/accumulator cell developed for the PCOAC. It uses a 2-to-1 multiplexer 3702 to give the adder/accumulator two ports. Using an N-to-1 multiplexer in a similar manner would expand the operation of the adder/accumulator cell to N ports. FIGURE 38 shows how these cells are connected together to create a 4-bit adder/accumulator. To add margin for reliability, delay 3802, 3803, and 3804 are added between stages 3701. The flip-flops 3808, 3809, 3810 are used to pipeline the carry between adder/accumulator stages. FIGURE 39 shows a 32-bit adder/accumulator built by pipelining 4-bit adder/accumulators together. Referring back to FIGURE 38, after each complete addition, the most significant bit 11 of a 4-bit adder/accumulator is clocked into register 3808. The clock 12 used for this operation is called the carry clock. The bit is then clocked into another register using the opposite edge of the carry clock. A delayed version of the carry clock 13 clocks this bit a third time to propagate it to the carry input of the least significant bit of the next stage just after the addition at that stage has been started. It is necessary to use a delayed version of the carry clock to ensure that the carry is not injected too soon thus violating the minimum pulse width requirement of the least significant toggle flip-flop. This 32-bit adder/accumulator 3901 is used four times in the PCOAC, once in each code clock generator (FIGURE 4) and once in each carrier generator. In addition, a non-pipelined adder/accumulator uses the special adder/accumulator cell 3701 (FIGURE 37) for implementing part of the search processor circuitry 206 (FIGURE 2). This adder/accumulator configuration saves gates over a conventional adder/accumulator. We are now going to discuss circuitry contained within the back end correlator module 203 of FIGURE 2. In order to perform predetection integration in the back end correlator module, it is prior art to use synchronous up/down counters. In a previous development, it was found that ripple counters could be used which would either count up 1 or not count at all. Two ripple counters would be used for each correlator, one for inphase integration, and one for quadrature integration. A separate counter common to all correlators in a channel, was kept to keep track of how many reference clocks were generated during an integration period. At the end of an integration, the number of reference clocks or accumulated bias is subtracted from the final value accumulated for each in-phase and quadrature integrator. This circuit had to be modified for two reasons. The first reason is that the circuit supports full null zone which means that the value in the chip of the demodulated signal is no longer just +1 or -1, but has multiple possible input valves. Secondly, in order to support search, we perform adjacent correlator presumming, and this removes the signal to noise ratio holes between correlators. FIGURE 40 shows a block diagram of the back end correlator module 203 from FIGURE 2. The problems previously mentioned are solved in the sample accumulators 4101 of FIGURE 41. The carries from the intermediate correlator module enter the sample accumulators and are immediately divided down by 8, 4107 and 4108, and are then reclocked 4109, 4110 and edge detection is performed, 4111 and 4112. Re-clocking occurs prior to edge detection in order to reduce the chance that a meta-stable state might effect a final accumulation value. From the output of the edge detector pulses are encoded 4113. FIGURE 42 shows the translation from carries from the intermediate correlator to which pulses are encoded. The pulses are encoded in such a way that a bias of 1 is added on every clock. The output of the pulse encoder will either be nothing, a pulse with a value of 1, or a pulse with the value of 2. These pulses go into a 22-bit ripple counter 4114, whose first stage uses the adder/accumulator technique previously mentioned so that a 1 or a 2 can be added. A separate bias accumulator 4106 is kept which keeps track of reference clocks or how many times the +1 value is added. At the end of each integration a 22 bit 16:1 multiplexer 4104 selects each accumulated value and subtracts the bias off using the adder 4105. These values are stored in the I&Q RAM 204 and 205 of FIGURE 2. FIGURE 43 shows the detailed circuitry required to build a sample accumulator as previously described. For search applications, the search processor previously described and also described in the above-mentioned copending patent application entitled "System and Method for a Digital Navigation Satellite Receiver" uses all correlators to search for the signal. FIGURE 45 shows the relative signal to noise ratio as a function of code error or how far the incoming signal is away from the signal generated in the chip at a particular correlator. As can be seen in this FIGURE, there is a 2.5 dB signal to noise ratio hole between each of the correlators which are spaced 0.5 chips apart. To eliminate this hole, adjacent correlator values are summed together FIGURE 44. This process is called adjacent correlator presumming. It is called presumming because it is done during predetection integration. The adder/accumulators support this, as shown in FIGURE 43. FIGURE 46 shows the results of adjacent correlator presumming. As can be seen, there is a flat 1.25 dB loss, but there are no signal to noise ratio holes. Our sample accumulator/circuit accomplishes this, as shown in FIGURE 43, by taking the pulses encoded from the adjacent correlator and applying those values to the 22 bit accumulator 4114. In doing this, the correlator controller must clock the bias accumulator 4106 of FIGURE 41 at twice its normal rate, as noted at the bottom of FIGURE 41.

Claims: A digital signal processing (DSP) circuit for use in a global positioning system (GPS) receiver, said DSP circuit comprising, on a single integrated circuit (IC), at least one signal processing channel (A, B), said channel (A) including circuitry means (105, 115) for processing a code signal from a satellite of said GPS, characterized in that: Y-code generator circuitry (108) is also provided on said single integrated circuit; said at least one signal processing channel (A, B) includes circuitry means (105, 115) for processing at least one of a valid P-code signal and Y-code signal from at least one satellite of said GPS, and comprises a multiplicity of correlators (111-118); a search processor for fast signal acquisition and a discrete Fourier transform (DFT) module (124) for converting integration samples from the correlators into a multiplicity of frequency bins of sample data are provided, the search processor being arranged to interpolate between the frequency bins to produce a multiplicity of additional bins. A circuit as claimed in claim 1, wherein the search processor implements a Tong detection algorithm. A circuit as claimed in any preceding claim, including: multiple L1/L2 P(Y) and C/A-code channels. A circuit as claimed in claim 3, further including: circuitry for tracking C/A and P(Y)-code simultaneously. A circuit as claimed in claim 3, further including: circuitry for processing P-code or Y-code selectively. A circuit as claimed in claim 3, wherein said Y-code generator circuitry comprises a single Y code generator common to all said multiple channels. A circuit as claimed in claim 3, further including: circuitry for selectively processing said L1 or L2 signals. A circuit as claimed in claim 3, further including: circuitry for supporting full null zone signal inputs. A circuit as claimed in claim 3, further including: a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock. A circuit as claimed in claim 3, further including: an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a ripple counter for reducing power and gate count. A circuit as claimed in claim 3, further including: a correlator configuration using ripple counters for predetection integration and bias accumulation; and an adder for subtraction of said bias. A circuit as claimed in claims 2 and 3 including: two P(Y) and C/A-code channels; support circuitry means for processing null zone signals; and wherein said channels each comprise: a carrier generator; a code clock generator; a P-code generator; a C/A-code generator; eight predetection integration accumulators; and a noise meter; said search processor comprising: a discrete fourier transform circuit; first circuitry means for performing frequency bin interpolation; second circuitry means for implementing a Robertson approximation for envelope calculation; third circuitry means for implementing a Tong detection algorithm to determine if signal is present; a threshold calculator which uses measurements from said noise meter; fourth circuitry means for calculating a second search threshold for the interpolated frequency bins; fifth circuitry means for advancing or retarding code state as required during search; a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.

Inventors: LAPADULA LEONARD J III, LU CHYI H, PAWLOWSKI GEORGE W, REKIETA DAVID, SCOTT HUGH L, STILES MITCHEL B, VOLPI JOHN P, LAPADULA, LEONARD J., III, LU, CHYI H., PAWLOWSKI, GEORGE W., REKIETA, DAVID, SCOTT, HUGH L., STILES MITCHEL B., VOLPI, JOHN P.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1992
Main classification: G01S5
IPC codes: G01S5, G01S1