A METHOD AND A DEVICE FOR CONTROLLING A RADIO TRANSMITTER

Abstract: The invention relates to a method and a device for controlling a radio transmitter. In the method, the radio transmitter is alternately caused to assume an ON state in which a desired outbound RF power is transmitted, and an OFF state in which no RF power is transmitted, the RF power being determined in the ON state by means of a power control signal (Vc) controlling the amplification of transmitter amplifiers (3, 4). In order that it could be ensured that the data period falls within the useful period of the transmitter, within which the value of the RF power to be transmitted is constant, a data stream (D2) is delayed with respect to the power control (Vc) when the transmitter is caused to assume the ON state.

Description: A method and a device for controlling a radio transmitter The invention relates to a method and a device for controlling a radio transmitter. In the method the radio transmitter is alternately caused to assume an ON state in which a desired outbound RF power is transmitted, and an OFF state in which no RF power is transmitted, the RF power being determined in the ON state by means of a power control signal controlling the amplification of transmitter amplifiers. The device according to the invention, in turn, is such as defined in the preamble portion of the attached claim 3. The method and the device according to the invention are intended for use in the base station of the GSM mobile radio network, but it is equally applicable to radio systems of other types in which the transmitter is keyed on the basis of varying transmission requirements. The advantage to be gained from the arrangement according to the invention is greatest in systems based on time-division multiplex¬ ing, in which high requirements are set on the trans¬ mission rate. The GSM radio system utilizes dynamic control of transmitting power both at the base station and at mobile stations. The power control word comprises four bits, which means that there are 16 power levels available. The spacing between two successive power levels is 2 dB, and so the entire power control range is 30 dB. In a so-called TX-on time slot, in which the transmission takes place, the transmitting power is adjusted in each time slot of the frame to one of the 16 different power levels in accordance with the above-mentioned power control word. A so-called TX- off time slot, in turn, is a time slot in which no transmission occurs (the RF power is zero). In this connection, EP Patent Application 414352 A2 is re¬ ferred to, which describes in more detail both the GSM system and a radio transmitter belonging to it, the transmitting power of the radio transmitter being adjustable in the TX-on time slot to one of the above-mentioned 16 power levels. At the beginning of the transmitting time slot (TX-on), the transmitter power increases with a pre¬ determined delay as compared with the power control voltage, whereas the data stream in the transmitter is not delayed in the same proportion. Therefore there is the risk that the first data bits are transmitted at the beginning of the transmitting time slot before a full transmitter power is achieved. Correspondingly, wrong bits may be transmitted at the end of the transmitting time slot at full transmitter power. The object of the present invention is to provide a method and a device by means o-f which it can be ensured that the data period falls within the useful period of the transmitter, within which the value of the outbound RF power is constant. This is achieved by means of a method according to the inven¬ tion in such a way that a data stream is delayed with respect to the power control when the transmitter is caused to assume the ON state. The device according to the invention, in turn, is characterized by what is disclosed in the characterizing portion of claim 3. The basic idea of the invention is that the data stream is delayed with respect to the power control so that it can be ensured that the outbound data will fall entirely within the useful period of the transmitter. In the following the invention will be de¬ scribed in more detail with reference to the examples shown in the attached drawings, wherein Figure 1 is a simplified block diagram illustrating the transmitter of a base station in the GSM system in aspects relevant to the invention; and Figure 2 shows a more detailed realization of a delay circuit according to the invention. Figure 1 shows a simplified block diagram illustrating the transmitter of a GSM base station in aspects relevant to the present invention. The refer¬ ence numeral 1 indicates a separator and delay cir¬ cuit to the inputs of which a digital data signal D is applied. In addition, a byte clock BCK and a time slot clock SLCK are coupled to the separator and delay circuit for the synchronization of the system (the byte clock is an internal clock of the trans¬ mitter having a duration of 20 pulses at the beginning of each time slot, that is, the byte clock breaks the data applied to the separator circuit into bytes; and the time slot clock is a clock which generates one pulse per time slot so that it is high during the pulses generated by the byte clock). Data about the desired power level in each particular case is included in the digital data signal D. In the separator and delay circuit 1, the power level data is separated and converted into an analog power control voltage V c corresponding to the level in question. The power control voltage V c is then applied to a power control unit 2 of the transmitter. In the power control unit the power control voltage V c is converted into a current I p i n by means of which the amplification of a preamplifier 3 of the trans- mitter is controlled. The preamplifier 3 is connected to a power amplifier 4 of the transmitter, which power amplifier applies RF power to a transmitting antenna 5. TX on/off data separated from the data stream is also applied from the separator and delay circuit 1 to the power control unit 2, which breaks off a voltage +V-^ to the preamplifier in a TX off situation. A serial data signal DI which no longer contains power level data is applied by the separator and delay circuit to a quadrature modulator 1' gener- ating I and Q components which are applied to an up- converter 6 which converts the signals to a higher frequency and applies them further to the pre¬ amplifier 3. The power amplifier 4 also provides data on a forward power P E for the power control unit 2, so that the power control can be adopted to amplifi¬ cation changes occurring e.g. at transistor stages. Figure 2 shows more closely how the separator and delay circuit 1 effects the delaying of data. An inbound data stream D2, from which the power level data has already been separated, is connected direct¬ ly to a data input 8 of a first in first out memory (FIFO) 7, and a bit clock signal bCK of the system correspondingly to a clkout pin 9 of the first in first out memory. The byte clock BCK is connected to a clock input pin (clkin) 10 of the first in first out memory and to a data delay control circuit 11 to which the time slot clock SLCK is also connected. An output signal CD from the delay control circuit 11 is coupled to an output enable pin 12 of the first in first out memory 7, and a data output 13 of the first in first out memory 7 is coupled to the quadrature modulator 1" for applying the data signal DI to the modulator. The control signal CD is generated by means of the byte clock and the time slot clock in the delay control circuit 11, and it is used to delay the out¬ put signal of the first in first out memory, that is, the data stream DI to the modulator, so that the data stream will fall within the useful period of the transmitter (which is 148 bits in duration in the GSM system). The delay control circuit can be effected by conventional random logic, and it can be combined with delay adjustment. More accurate circuit and operational diagrams are not shown, as each manufacturer can use his own internal synchronization signals, by means of which one skilled in the art can easily realize a simple delay operation. Even though the invention has been described above with reference to the example shown in the attached drawings, it is obvious that the invention is not restricted to it, but it can be modified in many ways within the inventive idea defined in the attached claims. In principle, the delay of the data stream could also be effected in the modulator; how¬ ever, the realization of the delay is easier in a digital stage than in an analog modulator.

Claims: Claims : 1. A method for controlling a radio trans¬ mitter, wherein the radio transmitter is alternately caused to assume an ON state in which a desired out¬ bound RF power is transmitted, and an OFF state in which no RF power is transmitted, the RF power being determined in the ON state by means of a power control signal (V c ) controlling the amplification of transmitter amplifiers (3, 4), c h a r a c t e r i z¬ e in that a data stream (D2) is delayed with respect to the power control (V c ) when the trans¬ mitter is caused to assume the ON state. 2. A method according to claim 1, c h a r a c - t e r i z e d in that the data stream (D2) is applied to a first in first out memory (7) having an output signal (DI) which is delayed. 3. A device for controlling a radio trans¬ mitter, comprising means for causing the radio trans- mitter to alternately assume an ON state in which a desired outbound RF power is transmitted, and an OFF state in which no RF power is transmitted, the RF power being determined in the ON state by means of a power control signal (V c ) controlling the amplifica- tion of transmitter amplifiers (3, 4), c h a r a c ¬ t r i ze d in that it comprises means (7, 11) for delaying a data stream (D2) with respect to the power control (V c ). 4. A device according to claim 3, c h a r a c - t e r i z e d in that the delay means comprise a first in first out memory (7) having an output signal (DI) which is delayed with respect to its in¬ put signal (D2).

Inventors: SEPPAELAE SEPPO, SEPPAELAE, SEPPO
Applicants: TELENOKIA OY
Application year: 1992
Main classification: H03G3
IPC codes: H03G3, H04B1, H04B7