ANALOG-TO-DIGITAL CONVERTER AND METHOD OF FABRICATION

Abstract: A two-step analog-to-digital converter (300) and BiCMOS fabrication method to make the converter. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from analog devices. The converter uses NPN current switching in a flash analog-to-digital converter (306) and in a digital-to-analog converter (310) for low noise operation. CMOS digital error correction (318) and BiCMOS output drivers (320) provide high packing density plus large output load handling. Timing control (330) aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small-long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Description: ANALOG-TO-DIGΓΓAL CONVERTER AND METHOD OF FABRICATION TECHNICAL FIELD The present invention relates to electronic semiconductor devices and methods of 5 fabrication, and, more particularly, to semiconductor devices useful for conversion < . between analog and digital signals and fabrication methods integrating both bipolar and field effect devices. BACKGROUND AND SUMMARY OF THE INVENTION Digital processing and transmission of electrical signals has become commonplace 10 even for basically analog information. Examples range from handheld digital voltmeters to the transition beginning in the 1960s of the public long distance telephone network from analog transmission to pulse code modulation (PCM) digital transmission. Application of digital methods to analog information requires an analog-to-digital (A/D) conversion, and the linearity, resolution, and speed of such conversion depends upon the application. For 15 example, digital voltmeters usually call for A/D conversion with good linearity and resolution (18-bits) but which may be slow (1 Hz); whereas, video applications demand high speed (30 million samples and conversions per second) but tolerate low resolution (8- bits) and poor linearity. Intermediate requirements of 12-bit resolution, good linearity, and 3 Msps (million samples per second) speed appear in applications such as medical imaging 20 with ultrasound, robotic control, high speed data acquisition, process control, radar signal analysis, disk drive head control, vibration analysis, waveform spectral analysis, and so forth. Multichannel information acquisition with arrays of A/D converters leads to another requirement: small aperture jitter so that synchronism of the channels can be maintained. Well known types of A/D converters include the successive approximations 25 converter which produces a digital output by a succession of trial-and-error steps using a digital-to-analog converter (DAC) and the flash converter which compares an input signal to multiple reference levels simultaneously and outputs a digital version of the closest reference level in a single step. The successive approximations converter provides high resolution and linearity but with low conversion speed, and the flash supplies high speed 30 at the cost of resolution and linearity. Note that a flash converter with n-bit resolution typically has a voltage divider with 2 s taps and 2" comparators, and this becomes unwieldy for high resolution. See, however, copending U.S. patent application Ser. No. 696,241, filed May 6, 1991 and assigned to the assignee of the present application. A compromise between these two types is the two-step flash A/D converter which uses a first coarse flash conversion to find the most significant bits and then reconstructs an analog signal from first flash output and subtracts this from the input signal to create an error signal from which a second flash conversion finds the least significant bits. Generally see Grebene, Bipolar and MOS Analog Integrated Circuit Design (Wiley-Interscience 1984), page 871. Generally, it is desirable that A/D converters combine still higher speed and resolution with lower noise. Methods of fabrication used for various semiconductor devices include the combination of bipolar transistors with CMOS transistors (BiCMOS), with analog portions of the integrated circuit using bipolar transistors for their low noise and digital portions using CMOS transistors for their high packing density. See for example R.Haken et al, "BiCMOS Processes for Digital and Analog Devices," Semiconductor International 96 (June 1989). However, improved BiCMOS fabrication methods are needed to achieve higher speed and resolution with lower noise on a monolithic circuit. The present invention provides a monolithic two-step flash A/D converter with high speed and resolution and a BiCMOS method of fabrication applicable to such converters and other integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described with reference to the accompanying drawings which are schematic for clarity, Figures 1-2 illustrate applications of a preferred embodiment analog-to-digital converter; Figure 3 is a functional block circuit diagram of the preferred embodiment; Figures 4-5 are flow and timing diagrams for the operation of the preferred embodiment; Figures 6-8 show aspects of the sample and hold of the preferred embodiment; Figures 9-22 show aspects of the flash converter of the preferred embodiment; Figures 23a-30 show aspects of the digital-to-analog converter of the preferred embodiment; Figures 31-37 show aspects of the error amplifier of the preferred embodiment; Figures 38-39 show aspects of the error correction of the preferred embodiment; Figures 40-44 show aspects of the output buffer of the preferred embodiment; Figures 45-49 show aspects of the timing controller of the preferred embodiment; fφ 5 Figures 50-51 show aspects of the power up reset of the preferred embodiment; Figures 52a-57 show aspects of the reference voltage generator of the preferred embodiment; Figures 58a-d are layouts for some preferred embodiment devices; Figures 59a-h are profiles for some preferred embodiment devices; 10 Figures 60-80 are cross-sectional elevation views of steps of a preferred embodiment method of fabrication; Figures 81-85 show aspects of the ESD protection of the preferred embodiment; Figures 86-87 show aspects of the isolation structure of the preferred embodiment; Figures 88-96 show aspects of the alternative embodiments; and 15 Figure 97 illustrates a time-temperature trade-off. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 schematically illustrates an ultrasound analysis system 100 which includes a sound generator 102, sound detector 104, first preferred embodiment analog-to-digital converter 106, digital signal processor 108, and video display 110. System 100 generates 20 high frequency (100 KHz) sound waves that penetrate object 120, and these waves reflect from interior structures of object 120 to be detected by detector 104. Converter 106 converts the detected analog signal to a digital form for signal processing by DSP 108, and video display 110 presents the results on a CRT. Mechanically the scanning sound generator 102 and detector 104 over the surface of object 120 provide reflection 25 information to reconstruct an image of the interior structure. Use of system 100 for human medical diagnosis or analysis demands relatively high speed operation for patient convenience and relatively high resolution for image reconstruction. Converter 106 is a 12-bit, subranging (half-flash or two-step) converter with digital error correction which samples an analog input in the range of -2.5 volts to +2.5 volts at a sampling rate of 3 Msps (million samples per second) and with an input bandwidth of 30 MHz. 12-bit resolution implies that the least significant bit of output corresponds to a 1.22 mV input interval. An input bandwidth of 30 MHz means that converter 106 can track video signals and that an array of converters 106 with sequential clocking can 5 provide video digitization; see Figure 2 which shows n converters 106 clocked by sequential commands CONV1, CONV2, ... CONVn. This array gives an effective sampling rate of 3n MHz. Converter 106 operates over a temperature range of -55 C to + 125 C with integral and differential linearity error and full scale error all about or less than 1 bit. Converter 10 106 uses a combination of bipolar and CMOS (BiCMOS) devices together with polysilicon- polysilicon capacitors and nickel-chromium thin film resistors plus laser trimming. Most CMOS gate lengths are about 1 μm and NPN emitters typically are about 2 μm by 3 μm with multiple devices paralleled to provide larger emitter areas. Also, matched devices may be split and laid out in symmetrical arrangements to help thermal balance and 5 insensitivity. Converter overview Figure 3 is a functional block diagram of the first preferred embodiment converter, indicated generally by reference numeral 300, which includes analog signal input terminal 302, sample and hold block 304, 7-bit flash analog-to-digital converter block 306, most- 0 significant-bits (MSB) latch 308, 7-bit digital-to-analog converter (DAC) block 310 (the DAC is trimmed to more than 14-bit accuracy), error amplifier 312, least-significant-bits (LSB) latch 314, subtractor 316, error correction block 318, output buffer 320, outputport 322, overflow/underflow block OF/UF 324, voltage reference block 326 with output terminal 328, timing controller and oscillator block 330, conversion command input terminal 332, and analog switch 334. Converter 300 is a two-step subranging analog-to- digital converter which uses the same 7-bit flash converter for both the MSB and the LSB conversions. Correction of device errors makes use of MSB and LSB overlap. The 12-bit output uses a two's complement representation of negative numbers, so an input of 0 volts leads to an output of 100000000000, an input of -1.22 mV gives an output of 0111 1111 1111, and an input of -2.5 volts yields 0000 0000 0000. An input of + 1.22 mV gives an output of 1000 0000 0001, and an input of +2.5 volts yields 1111 1111 1111. Operation summary Figure 4 is a flow diagram for a conversion by converter 300 and Figure 5 is a V 5 timing diagram (in nanoseconds) for the conversion flow which basically proceeds as <ϋι follows. A falling edge of the convert command (CONV) input at terminal 332 begins the conversion process; see the bottom panel of Figure 5. Just prior to the CONV command, sample and hold 304 was tracking (following) the input V^t) at terminal 302, analog switch 334 was connecting the output of sample and hold 304 to flash converter 306, the 10 comparators and encoder of flash converter 306 were following the sample and hold 304 output (which ideally is V t)) but without latching, DAC 310 was holding at a 0 volt output due to a fixed input, and error amplifier 312 was clamped to a 0 volt output. The CONV command at time to switches sample and hold 304 into the hold mode and with a fixed output equal to V^to). This switching requires a settling time of about 30 15 nanoseconds (nsec) due to charge injection by the switch; see the HLDSTTL pulse in the second panel from the bottom of Figure 5. For simplicity, V k (to) will be called V^. At the end of the HLDSTTL pulse, the first flash convert clock FLASH 1 rises to latch the comparators of flash converter 306 which have been following the essentially constant output Vj,, of sample and hold 304. The comparators ideally are outputting a quantization 20 of Vj,, to the encoder which has been encoding this quantization as a 7-bit number; see the FLASH1 pulse in the third from bottom panel of Figure 5. After about 28 nsec to allow settling by the latching circuitry of flash converter 306, the FLASH1 pulse falls low to store the 7-bit output in MSB latch 308 (not shown in Figure 4 but incorporated in Digital Subtractor and Error Correction). This 7-bit output is the binary encoding of the quantized 25 version of the input signal V^ with quantization levels separated by about 39 mV. Because the final 12-bit output of converter 300 will be a binary encoding of the quantized version of V fa with quantization levels separated by 1.22 mV (39 mV divided by 32), this 7-bit output contributes only to the seven most significant bits of the final 12-bit output. Note that an output of 0000000 from flash converter 306 corresponds to an input signal of about -2.5 volts, whereas an input signal of about 0 volts will lead to an output of 1000000 and an input of about +2.5 volts will yield an output of 1111111. Next, the rising edge of the 80 nsec DAC settling pulse (DACSTTL pulse in the fourth from bottom panel of Figure 5) performs three tasks: (1) it puts the 7-bit output of flash converter 306 stored in MSB latch 308 into DAC 310, which reconstructs the quantization of V k from the 7 bits, this reconstruction is denoted V,, below, (2) it puts the output of flash converter 306 into subtractor 316 which adds a fixed 7-bit code to compensate for the bipolar mode of operation and error correction, and (3) it switches analog switch 334 to connect the output of error amplifier 312 to the input of flash converter 306. Then the DAC 310 output begins slewing towards its final value, V.,, and feeds an input of error amplifier 312 which, however, remains clamped for about 10 nsec to avoid noise and saturation problems. During the remaining 70 nsec of the DACSTTL pulse, DAC 310 settles to its final output V., and error amplifier 312 amplifies the difference between V^ and V„, by a factor of 32. That is, error amplifier 312 amplifies the quantization error by 32; see the left middle portion of Figure 4. The second step conversion begins at the end of the DACSTTL pulse: flash converter 306 has been following the output of error amplifier 312 which has been settling to the amplified quantization error, and the rising edge of the second flash convert pulse (FLASH2 in the fifth from bottom panel of Figure 5) latches the comparators of flash converter 306. The falling edge of FLASH228 nsec later stores the encoded quantized version of the amplified quantization error in LSB latch 314, which feeds the most significant two bits to error correction block 318. Due to the amplification factor being only 32, rather than 128 as 7-bit conversion would suggest, the second conversion's most significant bits overlap the first conversion's least significant bits. If the components of converter 300 were errorless, then the overall conversion would amount to the following. The first flash conversion effectively decomposes V Λ as V fc = V q + V^ where V q is the quantized version of V b with quantization levels separated by about 39 mV and (V k -V,) is the first quantization error. The 7-bit output in MSB Latch encodes V„. DAC 310 errorlessly reconstructs V, from the 7 bits in MSB Latch 308; that is, V,, equals V q . Next, the second flash conversion effectively decomposes the amplified first quantization error 32^^,) as 32(V k = W q + [32(V io -V q )-W 0 ] where W q is the quantized version of 32(V in -V q ). Again the quantization levels are separated by about 39 mV and is the second quantization error. The 7-bit output in LSB Latch encodes W q . So the final quantized output is V q + W q /32 with roughly V q generating the most significant bits and W q /32 the least significant bits. Thus the combined effect of both flash conversions is to decompose Vj,, as V fc = V q + W q /32 + [32(V in -V q )-W q ]/32 That is, the overall quantization error equals the second quantization error divided by 32; so the overall quantization error is at most 39mV/32 which equals 1.22 mV. Error correction block 318 corrects any dynamic error (within tolerance) caused by the limited linearity accuracy of flash converter 306 during the first conversion step; the two most significant bits of the second conversion overlap the two least significant bits of the first conversion and provide the basis for the correction. Error correction block 318 provides the seven most significant bits and LSB latch 314 the five least significant bits to 12-bit output buffer 320 which makes the bits available at output port 322. Error correction and output buffer 320 loading consume about 20 nsec; see the LOADOP pulse in the sixth from bottom panel of Figure 5. This completes the overall conversion; and if CONV remains low, another sampling and conversion begins. The seventh from bottom panel of Figure 5 shows the ACQUIRE pulse which activates sample and hold 304 to acquire another sample, and the eighth from bottom panel (the top panel) of Figure 5 shows the End of Conversion pulse EOC. The settling time for sample and hold 304 after switching from hold mode to sample mode is about 100 nsec and uses both the 80 nsec ACQUIRE pulse and the 20 nsec EOC pulse. The righthand portion of the second from bottom panel of Figure 5 indicates the HLDSTTL pulse of the next conversion. The analog signal input range is 5 volts (-2.5 volts to +2.5 volts), so the quantization, 7-bit encoding, and subsequent analog reconstruction of input signal V ta will ideally yield a quantized approximation V,, with level spacings of 39.0625 mV and such that the approximation only differs from the input signal by at most one-half of a level spacing (19.53125 mV). Hence the difference, V^-V,,, after amplification by a factor of 32 in error amplifier 312, will ideally fall in the range of -625 mV to +625 V and thus not exceed one quarter of the input range of flash converter 306. Therefore, the output of the second pass through flash converter 306 should be seven bits with the three most significant bits being either Oil or 100 for negative or positive inputs, respectively. Consequently, the two most significant bits of the second pass overlap the two least significant bits of the first pass through flash converter 306, and this implies a 12-bit overall output rather than a 14-bit output as would have been guessed from the two 7-bit conversions. Discussion of error correction block 318 below details this overlapping of bits and also leads to overflow/underflow block 324 which indicates an original input out of the -2.5 to +2.5 volts range. Converter 300 has the following features: the timing pulses driving the operation do not overlap; only one function runs at a time, which lessens noise coupling; the sample and hold control provides aperture delay of less than 20 nanoseconds and aperture jitter of less than 25 picoseconds; clock signals driving flash converter 306 are translated to bipolar levels with a swing of 0.7 volts (V^ and lessen switching noise; subtractor 316 completes its operation prior to the activation of error amplifier 312 to lessen noise problems and avoid overdrive; the switching delay in activation of error amplifier 312 permits a settling of the DAC 310 output; and the output buffer 320 turns on its drivers sequentially to lessen ground bounce. The small aperture jitter permits the parallel configuration of converters, as illustrated in Figure 2. Converter 300 uses separate digital and analog power supplies and digital and analog grounds. The power supplies Vcc and Vdd are at +5 volts and Vee and Vss are at -5 volts with analog bipolar and CMOS devices operating between +5 and -5 volts but with the digital CMOS devices operating between +5 volts and ground. Figures 6-57 illustrate the elements of converter 300 in greater detail, including elements only implicitly shown in Figure 3; and the accompanying description follows the same order as the preceding overview. Sample and Hold Figures 6-7f schematically show circuitry of sample and hold block 304 with Figure 6 providing a functional block diagram and Figures 7a-f a schematic circuit diagram. Figure 8 shows settling from a 2.5 volt input step function. As seen in Figure 6, sample and hold 304 includes differential amplifier 602, differential amplifier 604, and capacitor 606 arranged as a closed-loop integrating type sample and hold circuit. Timing controller block 330 controls switch 608 through buffer 610. In the sample mode, switch 608 connects the output of amplifier 602 to the inverting input of amplifier 604 which charges or discharges capacitor 606 so that the output Vout tracks the input Vj,, at terminal 302. During hold mode switch 608 connects the output of amplifier 602 to ground to prevent saturation, and amplifier 604 holds the charge on capacitor 606 and also drives the bipolar input of error amplifier 312 and, when analog switch 334 is thrown, the bipolar input of flash converter 306. NPN devices are used in the input amplifier where device matching, high speed, and large transconductance are needed. MOS transistors are used in the sample and hold switch where their low off-state leakage, fast switching speed, and charge injection compensation ensure low pedestal error and fast hold mode settling. The high input impedance of MOS transistors is utilized in the input stage of the output amplifier. The high input impedance provides a very low droop rate. The high speed characteristics of the bipolar transistors are utilized in the rest of the output amplifier (gain and output stages) to achieve a large bandwidth which translates into low acquisition times. Figures 7a-f show amplifier 602 as a high output impedance transconductance amplifier. The inputs 701-702 connect to a modified Darlington differential pair 703-704 with emitter degeneration resistor 706 for improved slew rate; the inputs (which are V k and Vout) are to be in the range of -2.5 to +2.5 volts and the rails are at +5 volts and - 5 volts. The outputs of the differential pair 703-704 connect to the sources of PMOS cascode devices 707-708 which replace PNP devices and provide a high frequency level shift function and drive the Wilson current mirror made of NPNs 710-715. The single- ended output of amplifier 602 at node 718 connects to sample and hold switch 608 which consists of a pair of CMOS transmission gates 720-721 , gate 720 connects output node 718 to ground and gate 721 connects output node 718 to inverting input 731 of amplifier 604 and capacitor 606. The CMOS transmission gate switch includes charge cancelling devices to reduce charge injection error and leakage current. The switch control signal (called IRQ below) from block 330 enters node 730 and directly drives level translator 725 to switch gate 721 but is delayed by inverter chain 727 for driving level translator 724 to switch gate 720. Hence, switching from sample mode to hold mode has a few nsec gap between the disconnection of the output of amplifier 602 from the inverting input of amplifier 604 to the connection of the output to ground. This gap avoids injecting charge from the switching to ground into holding capacitor 606 and thus lessens pedestal error. Amplifier 604 is a two gain stage amplifier with a large PMOS source-coupled pair used as an input differential pair 731-732 to provide high input impedance, low noise, and no dc gate current and using a NPN current mirror load 734. The single-ended output of the PMOS pair 731-732 drives an all-NPN output stage 736. Figures 7a,e also show start up circuit 740, bias circuit 742 for amplifier 602, and bias circuit 744 for amplifier 604; the use of separate bias circuits limits noise and talkback. Capacitor 606 has 15 pF capacitance and is made of two layers of polysilicon separated by a grown oxide of 900 A thickness for low leakage. Both amplifier 602 and amplifier 604 are made of a combination of CMOS and NPN devices, which permits the fast, high gain of amplifier 602 (input impedance of about 20 Mohms) and the low leakage input of amplifier 604 during the hold mode. The high gain plus the grounding of amplifier 602 during hold mode to prevent saturation (the input at V^ keeps changing whereas Vout holds, so the differential input can become large) permits an acquisition time of less than 100 nsec for 0.01% error; that is, after switching to sample mode Vout tracks within 0.5 mV of V within 100 nsec. See Figure 8, which illustrates the extreme case of V ont initially at 0 volts and V k at +2.5 volts. The droop rate is less than 1 mV/μsec. Figures 7g-l illustrate an alternate embodiment of the sample and hold 304 using PNP transistors. The PMOS cascode devices 707 and 708 are replaced with PNP bipolar transistors 707A and 708A to exploit their superior frequency response. The greater transconductance of the PNP transistor presents a lower impedance to the collectors of the input transistors 703 and 704, which reduces the parasitic time constant and improves acquisition time. A push-pull type output stage is made possible by the addition of the complementary PNP transistors 750 and 751. This type of output stage is capable of driving lower impedance loads. For a given load, the addition of the PNP will reduce rfe phase shift in the output stage and allow a greater overall bandwidth. 5 The following table compares the improved specifications of the preferred embodiment sample and hold amplifiers to that presently available. Parameter Input Range Input Resistance 10 Input Capacitance Input Offset Input Bias Current Open Loop Gain Unity Gain Bandwidth 15 Acquisition Time Droop Rate Slew Rate Pedestal Error Hold Mode Settling, .8% 20 Hold Mode Settling, .015 % Analog switch Timing controller block 330 controls analog switch 334 which is a set of analog CMOS transmission gates. Analog switch 334 must be able to pass analog signals in the - 2.5 to +2.5 volt range. With the power rails at -5 volts and +5 volts the analog CMOS 25 transmission gates easily handle this range. Alternative switch implementations such as controlled CMOS inverters could also be used. Flash converter Figures 9-22 schematically show the 7-bit flash converter block 306. In particular, Figure 9 illustrates the overall flash architecture which includes an array of 127 comparator cells (labelled 902-1 through 902-127), each with a voltage reference input (Vref) connected to a tap on resistor ladder 904 and a signal input V^ connected to the signal to be converted (either the output of sample and hold 304 or the output of error amplifier 312). Adjacent comparator cells 902 are functionally interconnected so that only the cell which senses a Vref closest to the input signal V* will output a logic high to array 906. Encoder 906 generates a 7-bit binary output (at ECL levels) which corresponds to the Vref closest to V fa . Level translators 908-1 through 908-7 translate this to CMOS levels and feed MSB Latch cells 308-1 to 308-7 and LSB Latches cells 314-1 to 314-7. Latches 910-1 through 910-7 are for testing. The 128 resistors (labelled 904-1 through 904-128) of ladder 904 each have a nominal resistance of 3.8 ohms. The total resistance of ladder 904 is 486 ohms. With a 5-volt drop the ladder will draw about 10 mA and dissipate 50 mW. The resistors 904 are fabricated from polysilicon with a width of at least 40 um in order to avoid electromigration problems at the contacts. Voltage references (Vref = +2.5V and Vref = -2.5V) drive ladder 904 so that the drop across each resistor equals 39.0625 mV, corresponding to a least significant bit (LSB) output. To insure that 1000000 will be the outcome of an input within 19.5 mV (1/2 LSB) of 0 volts, resistor 904-65 is center tapped to analog ground (e.g., by replacing resistor 904-65 with two pairs of parallel connected 3.8 ohm resistors connected in series and tapping the series connection). To. compensate for this center tap of resistor 904-65, resistor 904-1 is replaced by a 1.9 ohm resistor (two 3.8 ohm resistors in parallel) and resistor 904-128 is replaced by a 5.7 ohm resistor (3.8 ohm and 1.9 ohm resistors in series). Thus, disregarding any comparator cell input bias curent, the Vref input to comparator cell 902-1 is -2.480 volts (-2.5 + 1/2 LSB); the Vref input to comparator cell 902-2 is 1 LSB higher than to cell 902-1; and so forth up to a Vref input to comparator cell 902-64 of -1/2 LSB, a Vref input to cell 902-65 of +1/2 LSB, and continuing up to a Vref of 2.441 volts (2.5 - 3/2 LSB) for cell 902-127. The output of comparator cells 902 is encoded by encoder 906 which feeds seven level translators and latches 908-1 through 908-7. Only a single one of comparator cells 902 has a high output due to a segment detecting output NOR gate with inputs also from the two adjacent comparator cells; and encoder 906 is just a simple array of NPN transistors with bases tied to the comparator cell outputs and emitters tied to the seven bitlines feeding the level translators/latches 908. Thus when comparator cell 904-j has the high output, all of the NPN transistors in the jth row turn on and pull the connected bitlines up about 0.54 volts (from 4.46 volts to 5.0 volts) and thereby encode the output. Level translators 908 and latches 308 on the bitlines amplify and translate the 0.54 volt swings on the bitlines into full CMOS levels and latch them. The encoding expresses positive numbers with a leading bit equal to 1 and negative numbers in two's complement form with a leading bit equal to 0. Figures lOa-b are a schematic circuit diagram for a comparator cell 902 which has first gain stage 1010, second gain stage 1020, latch 1030, and output NOR gate 1050. First gain stage 1010 includes NPN emitter-followers 1001 and 1002 for buffering the Vref and Vin input signals, respectively, to NPN differential pair 1003-1004, which have NMOS 1017 as their current source. NMOS 1011 and 1012 provide current sources, load resistors 1013 and 1014 are made of NiCr, and NPN 1019 is diode connected. The devices operate with +5 volt (Vcc) and -5 volt (Vee) power supplies. The outputs of first gain stage 1010 are limited to a swing of about 2.0 volts. These feed the inputs of second gain stage 1020 which includes input NPN differential pair 1021-1022, NiCr load resistors 1023 and 1024, NPN switch 1027, resistor 1028, and NMOS current source 1029. Second stage 1020 operates with +5 volts and ground power supplies. The outputs of second stage 1020 drive latch 1030, formed with cross-coupled NPNs 1033-1034. NPN 1031 provides the coupling from the collector of NPN 1033 to the base of NPN 1034. NPN 1032 couples the collector of NPN 1034 to the base of NPN 1033. NMOS 1035 and 1036 are current sources for NPN 1031 and 1032, respectively. NPNs 1037 and 1038 provide diodes, NPN 1041 is a switch, and resistor 1043 connects NPN 1041 to current source 1029. The latch devices also operate with +5 volts and ground power supplies. Second stage 1020 and latch 1030 operate as follows. The flash clock (the flash clock is the sum of FLASH1 and FLASH2) is translated to Vbe levels (see Figures 14a-b and CLK in Figure 10b) and drives the base of switch NPN 1041. The complement of the flash clock drives the base of switch NPN 1027. Thus, prior to a conversion, switch NPN 1027 is on and differential pair 1021-1022 is active but switch 1041 is off and cross- coupled pair 1033-1034 are inactive. However, NPNs 1031 and 1032 are both active and the result of the comparison of Vref with Vin (which may be varying) passes to NOR gate 1050 (to the base of NPN 1051) and to the NOR gates of the adjacent comparator cells. 5 Once flash clock goes high, switch 1027 cuts off the current to differential pair 1021-1022 and turns on switch 1041. This activates cross coupled NPN 1033-1034 to latch in the most current result of the comparison. Note that the switching and latching involves only current switching in NPN devices, so the voltage swings stay down in the range of 0.5 volt and do not create as much noise as comparable CMOS logic switching. 10 Latch 1030 has three outputs: inverting nodes 1045 and 1046 and noninverting node 1047. Node 1045 is one of the three inputs for NOR gate 1050; inverting node 1046 is an input to the NOR gate of the adjacent comparator cell receiving a higher Vref; and noninverting node 1047 is an input to the NOR gate of the adjacent comparator cell receiving a lower Vref. NOR gate 1050 includes parallel pulldown NPNs 1051, 1052, and 15 1053, plus NMOS current source 1055, logic reference voltage input NPN 1057, and pullup resistor 1058. The output of NOR 1050 connects to a row of encoder 906. The input (base) of NPN 1051 connects to an inverting output (node 1045) of latch 1030, the input of NPN 1052 connects to an inverting output of the latch of the adjacent comparator cell with a lower Vref, and the input of NPN 1053 connects to the noninverting output of 0 the adjacent comparator cell with a higher Vref. Hence, the output of NOR gate 1050 is logic low unless all three of NPNs 1051-1053 are turned off, and this provides a logical segment detection in comparators 902 as follows. NOR gate 1050 in comparator cell 902-j is high precisely when its node 1045 is low and node 1045 from cell 902-(j-l) is also low and node 1045 from cell 902-(j+l) is 5 high. This corresponds to V k being greater than Vref for cell 902-j (and Vref for cell 902-(j-l) which is lower) and being less than Vref for cell 902-(j+l). And in this case NOR gate 1050 of cell 902-j being high pulls the jth row of encoder 906 high which in turn pulls the appropriate coding columns high. The NOR gates in all other cells 902-k have at least one of NPNs 1051-1053 turned on to pull the kth row of encoder 906 low 0 and thereby not affect any of the coding columns. The NOR gates 1050 also provide some error correction. The NOR gate outputs will only be high if Vin is greater than Vref for cells 902-(i-l) and 902-i and if Vin is less than Vref for cell 902-(i+ 1). This requirement on the states of three adjacent cells avoids having two adjacent cells output a logic high signal at the same time. Otherwise, if two adjacent cells have high outputs the resulting binary code could have a value of up to twice the correct value; the three input NOR gate prevents this from happening. Figure 11 shows the circuitry for level translators 908-1 through 908-7. The corresponding column of encoding array 906 connects to diode 1102 into the base of NPN 1105 of differential pair 1105-1106. The base of NPN 1106 connects to a bias with level midway between the extremes of the swing at the base of NPN 1105. The currents through NPNs 1105-1106 are mirrored by PMOS mirrors 1110-1111 and 1112-1113 and then NMOS mirror 1114-1115 to drive a CMOS output inverter 1120. Figure 12 illustrates the bias circuit for NPN 1106. Figure 13 shows bias generator 1300 for setting gate voltages in the comparator cells 902. Figures 14a-b show the clock generator for translating the CMOS level flash clock signal to +1/2 Vbe and -1/2 Vbe level signals for driving switch NPNs 1027 and 1041 in comparator cells 902. Each of the 127 comparator cells 902 has seven current source NMOS devices (1012, 1017, 1011, 1029, 1035, 1036, and 1055 in Figure 10). Thus a large number of equal parallel current sources must be provided to insure uniform behavior of the comparator cells. Figure 15 shows a standard base current compensated NPN current mirror 1500 with two outputs; the resistor current typically is an order of magnitude larger than the base currents. This current mirror overcomes base current error sensitivity of a basic NPN curent mirror, but has the drawback of having to provide a base current for every output NPN, which becomes intolerable for the 128x7 outputs required by the comparators 902. Figure 16 illustrates a basic NMOS current mirror 1600 which has the advantages of high packing density and zero bias current, and low drain to source operating voltages when a large number of outputs are required. However, the NMOS current mirror is sensitive to kickback noise. That is, a transient voltage spike at one of the outputs capacitively couples (i.e., a gate-to-drain parasitic capacitor) to gate bias line 1602. This causes a gate bias fluctuation and a current fluctuation in all of the other outputs. The magnitude of the gate bias fluctuation depends upon Z C +Z^ where Z^ is the impedance of the gate-to-drain capacitor and Z is the impedance to ac ground of gate bias line 1602. In effect, a high pass filter exists between each output and gate bias line 5 1602 because Z^ varies as the reciprocal of frequency. The impedance Z is the reciprocal of the transconductance of NMOS 1604 if the impedance of reference current source 1610 and the output impedance of NMOS 1604 are large and neglected. Hence, the small transconductance of NMOS 1604 generally leads to the kickback noise sensitivity of the basic NMOS current mirror 1600. The preferred embodiment current mirror 1700, shown schematically in Figure 17, inserts an NPN current mirror 1705 between reference current source 1710 and NMOS 1704 of an NMOS current mirror 1709. This lowers the impedance to ac ground of gate bias line 1702 because the high transconductance of NPN 1706 provides a path to ac ground paralleling NMOS 1704. An order of magnitude drop in the impedance may be easily achieved without a large increase in substrate area occupied by the devices. Thus current mirror 1700 can provide 20 dB further kickback noise rejection plus maintain the advantages of NMOS current mirrors. The current mirror 1700 operates as follows. NMOS 1714 is matched with NMOS 1704 to provide the same voltage drop for equal currents. NPN 1716 and NPN 1726 match NPN 1706, so they form a base current compensated current mirror with matching NPN 1728 the shunt resistor. NMOS 1724 matches NMOS 1704 and 1714 to provide the same voltage drop. Thus the emitter current from NPN 1706 mirrors the reference current from source 1710 within a factor that can be taken as 1 presuming a large gain by NPN 1726. Output NMOS transistors 1751, 1752, 1753, etc. match NMOS 1704 and have the same gate bias, so the outputs mirror the reference current. Of course, the load devices 1724 and 1728 could be replaced by resistors, but this typically occupies more substrate area. Current mirror 1700 can be modified in various ways to adapt these principles of kickback noise rejection to other MOS current mirror circuits. For example, Figure 18 shows a basic stacked NMOS current mirror as would be used for high output impedance applications with reference current source 1810 through NMOS 1804-1805 being mirrored by the output NMOS stacks. Figure 19 shows a preferred embodiment version 1900 of a stacked NMOS current mirror where NPN 1906 provides high transconductance to lessen kickback coupling. Indeed, simulations on the current mirrors 1800 and 1900 confirm that <a. 5 mirror 1900 provides 31 dB of additional kickback rejection. Figure 20 illustrates a low current version of current mirror 1700. The reference current from source 2010 is divided among NMOS devices 2004-1, 2004-2, ... 2004-N so each device 2004-j outputs only 1/N of the reference current. Figure 21 shows current mirror 2100 which modifies current mirror 1700 to 10 compensate for the Early voltage induced errors of NPN 1706. Current mirror 2100 includes NPN 2107 with a fixed bias set to match the Vce of NPN 2106 to the Vce of NPN 2116. Figure 22 illustrates a PMOS current mirror 2200 which includes the kickback suppression using NPNs. Current mirror 2200 provides the high transconductance of NPN 15 2206 in series with NPN 2220 to create the low impedance from gate bias line 2202 to ac ground. The reference current from source 2210 is mirrored into NMOS 2212 and then into NMOS 2214, which has twice the gate width of NMOS 2212. Thus twice the reference current passes through NMOS 2214. And NPN 2206 is biased by PMOS 2211 to pass the reference current. Consequently, PMOS 2204 and NPN 2220 also pass the 20 reference current, and this is mirrored by output PMOS 2231 and 2232 through gate bias line 2202. NPN 2220 provides a Vbe voltage drop to match that of NPN 2206, and PMOS 2204 matches PMOS 2211. Current mirror 1700 could be converted to a PMOS current mirror by replacing NPN with PNP and NMOS with PMOS. Similarly, the other current mirrors 1900, 2000, 25 2100, and 2200 could be transformed by P and N type device switches. MSB latch MSB latch 308 is a set of seven standard latches 308-1 through 308-7 indicated in Figure 9, which are clocked to load the outputs of translators 908-1 through 908-7 at the _ falling edge of FLASH1. The falling edge also cuts off the current to latches 1030 and reapplies current to the differential pairs 1021-1022 in the comparator cells 902. This prepares flash converter 308 for another conversion. The outputs of MSB latch 308 are labelled Al, A2, ... A7. DAC 5 Figures 23-30 illustrate various components of DAC 310. As shown in Figures 23a-d, the DAC includes core 2302, control amplifier 2304, reference cell 2305, and interface 2310. Sample and hold 304, analog switch 334, and error amplifier 312 are also shown in Figures 23c-d. DAC 310 uses current scaling with the CMOS bits from MSB Latch 308 translated to ECL levels within interface 2310 which then drive current switches 10 in core 2302. The DAC output current feeds error amplfier 312, as shown in Figure 31. Figures 24a-d show core 2302 with cells 2401-2415 controlled by the bits from MSB latch 308. Figure 26 shows the current switch structure 2600 for the cells 2401-2404, and Figure 25 shows the current switch structure 2500 for the cells 2405-2415. Each cell 2500 or 2600 has an input NPN differential pair 2501-2502 or 2601-2602 tied to a current 15 source made of biased NPN 2510 and NiCr resistor 2512 or biased NPN 2610 and NiCr resistor 2612. Resistor 2512 is shown as two resistors in series, and resistor 2612 is shown as four resistors in series. When input 2520 receives a logic high signal (-0.7 volt), and complementary input 2521 receives a logic low signal (-2.1 volts), NPN 2501 turns on and NPN 2502 turns off. This steers the current from output 2530 to current source 20 2510-2512 and leaves output 2531 in a high impedance state. Reversed inputs similarly steer the current from output 2531 and leave output 2530 in a high impedance state. Cell 2600 is analogous. Thus the switching in the core cells only steers a constant current and involves voltage swings of 1.4 volts. This provides lower noise than is attainable with CMOS switching. 5 Cells 2405-2415 all have equal current sources (see Figure 25 with resistor 2512 at 1 Kohms) and correspond to the higher order bits from MSB Latch 308. A7 (the highest order bit) drives four cells: 2412-2415; A6 drives two cells: 2406-2407; and A5 drives cell 2405. i each case if the bit is a 1, then the cell steers the current from DAC output 2430, and if the bit is a 0, the cell steers the current from DAC output 2431. The four cells 2408-2411 provide a constant current, through current mirrors 2420, to DAC output 2430. This constant output current just offsets the current absorbed by cells 2412- 2415 when bit equals 1 and corresponds to the fact that a 0 volt input V k leads to a 1000000 from flash converter 306. Cells 2401-2404 (cells as in Figure 26) have proportionally smaller current sources than those of cells 2405-2415 by the use of proportionally larger resistors 2612: A4 switches half the current switched by A5 because resistor 2612 of cell 2404 is about twice the value of the resistor 2512 of cell 2405. Similarly, A3 switches half the current switched by A4, A2 switches half the current switched by A3, and Al switches half the current switched by A2. Figures 27a-c show interface 2310 which translates the CMOS levels of bits Al A2 .. A7 to bipolar levels with a translation cell for each current cell in core 2302; and Figure 28 illustrates the translation cell. Interface 2310 also isolates the analog currents in core 2302 from the CMOS switching noise. Figure 29 shows the connection of control amplifier 2304 and reference cell 2305 to the core cells. Figure 30 shows override register 2320 which simply applies 1000000 to interface 2310 when the SWITCH signal is low and passes Al A2 ... A7 from MSB Latch 308 to interface 2310 when the SWITCH signal is high. This control by the SWITCH signal has the advantages of (1) applying all bits Al A2 .. A7 simultaneously to the current switches so that DAC 310 settles directly toward its final output current rather than hunting as when currents are switched sequentially; and (2) the 1000000 input holds the output of DAC 310 to its midrange 0 current, which minimizes the maximum output current change when switched to pass Al A2 ... A7. The falling edge of FLASH1 drives the SWITCH signal high, so Al A2 ... A7 pass to drive the DAC core current switches and begin the settling of the DAC output current to V„/R. The SWITCH signal returns low on the rising edge of the ACQUIRE signal which follows the FLASH2 signal by about 30 nsec. SWITCH going low throws analog switch 334 to disconnect the output of error amplifier 312 from the input of flash converter 306 and reconnect sample and hold 304. Thus the output of DAC 310 settling back to 0 does not create any noise for the second step conversion. The settling precedes a first flash conversion in a second sample of V k (t) by enough time to ready DAC 310 for another conversion. DAC 310 takes about 35 nsec to settle to 14-bit accuracy. The linearity of DAC 310 depends primarily upon (1) the Early voltage magnitude and matching among the NPNs used in the current switching cells, (2) the current gain and matching among the same NPNs, and (3) the quality of the NiCr film used for the resistors in the cells. Error amplifier Error amplifier 312 includes two serially-connected gain amplifiers with the first amplifier providing a gain of 4 and the second a gain of 8 for an overall gain of 32. Figure 31 illustrates the connections of the two gain amplifiers 3100 and 3101 with feedback resistor ratios setting the gains. DAC 310 absorbs current Io to subtract V„,, the reconstructed quantized version of V ώ , from V k supplied by sample and hold 304. That is, sample and hold 304 supplies a current of V k /R to the virtual ground at the inverting input of amplifier 3100; and DAC 310 absorbs the current Io equal to V- q /R. Thus the voltage at node 3110 is ^ V^-V,,). R is about 400 Q. Gain amplifier 3100 (and gain amplifier 3101) has a two gain-stage folded cascode design. The output stage includes level shifting and a modest gain. The input stage develops most of the gain in order to maintain a high bandwidth while minimizing error sources. The input stage is a precision stage with low input bias currents and quad cross- coupled input NPN devices. Parallel clamping input stage protects amplifier 3100 during overdrive conditions; such as when V k appears at the inverting input without any offsetting current from DAC 310. Figure 32 shows gain amplifier 3100 in block form, and Figures 33a-d show it in schematic circuit form. Amplifier 3100 includes: bipolar differential input stage 3210; CMOS differential input/clamp stage 3220; differential to single ended stage 3230 which combines bipolar and CMOS devices; output stage 3240; and overdrive protection switches 3250. In a more general configuration CMOS differential stage 3220 could have its inputs connected to the inputs of the bipolar differential input stage to create a two channel amplifier with differing input gain stages selectable by switches 3250. Normal operation of amplifier 3100 has switch 3252 closed and bipolar stage 3210 fully biased and in complete control over the output; switch 3251 is open to completely debias CMOS stage 3220 which then lacks any control over the output. In contrast, clamp operation of amplifier 3100 has switch 3252 open to force bipolar stage 3210 to operate at very low bias current supplied by source 3253 and exert limited control over the output. Operation of bipolar stage 3210 at very low current rather than turning it totally off permits rapid energization when switching from clamp operation to normal operation. Also clamp operation has switch 3251 closed to energize CMOS stage 3220 which takes control of the output. Feedback resistors 3261-3262 and the potential applied to resistor 3262 (ground in Figure 32) determine the clamp operation output voltage (0 volts). CMOS devices are utilized both to provide matched biasing currents and to sense voltages; this avoids base current errors of bipolar bias and sense circuits and avoids corruption of the match currents. Exploiting CMOS produces excellent input characteristics like low offset voltage temperature coefficient and low input current and boosts open loop gain. Speed is the most critical requirement of amplifier 3100, and the NPN devices have a cutoff frequency of at least 3 GHz. High beta NPNs are used to meet the input bias current conditions. Stacked PMOS devices are used to produce high impedances to achieve large open loop gain in the first stage. Figures 33a-d schematically show amplifier 3100 with CMOS stage 3220 and switches 3250 in Figure 33a. Zener based bias circuit 3310 in Figure 33b, bipolar input stage 3210 in Figures 33b-c, differential to single ended stage 3230 in Figures 33c-d, and output stage 3240 in Figure 33d. Bias circuit 3310 uses Zener diode D660 and forward biased NPN diode Q596 and diffused resistor R662 to achieve a temperature stable bias for NPN Q592. NPN Q592 provides a reference current through resistors R618, R657, R619, R705, R706 to a current mirror made of NPNs Q149, Q599, and Q600 plus resistors R597 and R609 and an NPN base bias on line 3312 for other current sources in amplifier 3100. PMOS M602-M603 also mirror the current to provide a PMOS bias on line 3311 for other current sources in amplifier 3100. The bipolar input stage 3210 includes differential input NPN emitter followers Q166 and Q168 driving NPN emitter coupled pair Q165-Q169 with NPNs Q211, Q162 and Q161 connecting them to NPN current source Q156 plus resistor Rl 10. Note that the noninverting input (base of NPN Q166) connects to ground through RX (see Figure 31) and that the inverting input (base of NPN Q168) connects to the output of DAC 310. Each of the inputs can vary between -2.5 volts and +2.5 volts, but during amplification of the quantization error the magnitude of the input difference should be less than 40 mV. However, when DAC 310 is held at a 0 current output, the magnitude of the input difference could be up to 2.5 volts, and CMOS differential input stage 3220 provides protection during such overdrive, as described below. The power rails Vee and Vce for input stage 3210 are at -5 volts and +5 volts. The differential output signals from stage 3210 pass through NPN shielding devices Q163 and QI64 to differential-to-singled-ended stage 3230. Stage 3230 has cascoded PMOS M27 and M30-M32 and a pair of voltage followers and a current mirror for conversion to a single-ended output to drive output stage 3240. One voltage follower is for the load current mirror and the other is to drive output stage 3240. The voltage followers are basically made of NMOS M12, NPN Q181, and NPN Q182 for the current mirror and of NMOS Mil, NPN Q184, and NPN Q183 to drive output stage 3240. Output stage 3240 includes NPNs Q191, Q192, and Q193. Any current and voltage mismatches between these two voltage followers will generate error currents causing degradation of open loop voltage gain, offset voltage, and offset voltage temperature coefficient. Ideal voltage followers have 0 input current and maintain equivalent collector- to-base voltage drops for current mirror devices Q176, Q177, Q178, and Q179 while contributing minimal phase shift. Figure 34 shows a standard voltage follower based upon MOS devices for very high input impedance. Such followers have poor Vgs matches which cause Vcb mismatch between the NPN mirror devices Q12a and Q13a. This generates error currents and degrades performance. Figure 35 shows a standard voltage follower formed with bipolar devices to provide a good voltage match. Such followers have relatively low input impedance. The mismatch of the base currents produces an error current that degrades performance. The two separate current sources for each of the followers in Figures 34 and 35 also leads to a source of mismatch and performance degradation. The voltage followers of amplifier 3100 (Figure 33c-d), shown in a simplified form in Figure 36, are called composite voltage followers (CVF) due to the combination of both MOS and bipolar devices. This arrangement benefits from the high input impedance of the MOS devices (MO and M9) while the cross-coupled bipolars (Q4, Q6, Q10, and Qll) improve the match of the followers beyond that obtainable with MOS devices alone. This improvement works for both DC and transient signal conditions. Improvement in match between the MOS MO and M9 devices is partially accomplished by providing matched currents to the MOS devices. These currents match under both DC and transient signal conditions. Because the MOS devices have —0 input current, no error currents are generated at the differential to single-ended conversion point, labelled HIP in Figure 36. This results in improvements in open loop gain, offset voltage, and offset voltage temperature coefficient over that obtainable using only bipolar transistors. Match of the followers is improved by the use of one current source to bias both transistors, with further improvement due to the cross-coupled bipolars biasing the NMOS followers. One of the followers (A) feeds the signal from the High Impedance Point (HIP) to the output stage, the second follower (B) is required as a voltage clamp in the current mirror (Q12 and Q13). DC bias current for both followers is provided by current source 17. No special restrictions are placed on the actual implementation of 17. An NPN or NMOS device is sufficient. The implementation in Figure 33c-d uses an NPN as the negative bias current rail for amplifier 3100 NPN current sources. The CVF of Figure 36 operates as follows. The current from 17 is divided by NPN devices Q4 and Q6. Although this application has the current equally split between these two devices, other applications may find advantages in another ratio. Device Q4 provides half of the NMOS M9 operating current, while Q6 provides half of the NMOS M0 operating current. The other half of the M0 current comes from NPN Qll, and the other half of the MO current comes from NPN Q10. This cross-coupling of bias for the NMOS followers provides an improved operating point match for the NMOS followers M0 and M9 and the current mirror devices Q12 and Q13. This leads to better open loop voltage gain, offset voltage, and offset voltage temperature coefficient performance of amplifier 3100. The bias current division function of the cross-coupled bipolar devices (that results in an improved amplifier) also divides the load current of both followers. Half of the OUTPUT load current comes from M9 through Q4, with the other half from MO through Q6. The base current of the current mirror devices Q12 and Q13 load both followers in a similar way. Half of this load current comes from MO through Q10 and half from M9 through QIL This sharing of load currents between the followers insures that the Composite Voltage Followers maintain identical operating points leading to better match and an improved amplifier. The PMOS current mirror (M16-M19) and NMOS current mirror (M14-M15) close the loop around the Composite Voltage Followers. The drain current of MO is exactly duplicated as the drain current of M15 (applies to DC and Transient current). The drain current of MO (M15) is composed of: 17/2 + lout 2 + (IbQ12 + IbQ13)/2 + IdM15/2 = IdMO The drain current IdM9 of M9 is composed of: 17/2 + lout/2 + (IbQ12 + IbQ13)/2 + IdM15/2 = IdM9 The end result is (as desired): IdMO = IdM9 The operating currents of the NMOS followers match perfectly due to the cross- coupling of the NPNs (Q4,Q6,Q10,Q11) and the mirroring of MO's drain current to M15's drain. The dividing action of the cross-coupled devices along with the mirroring of MO's drain current insure that MO and M9 see the same load. This applies to both DC and transient conditions. Both NMOS followers see the same transients. This improves the settling time because the CVF presents a symmetric load to the mirror devices Q12 and Q13. Any asymmetry would cause undesirable ringing in the settling waveform. Any transient voltage or current at the HIP would be mirrored over to the other input device, but symmetry will lead to less ringing. Figure 37a shows a PNP version of the Composite Voltage Follower and Figures 37b-c show all NPN and all NMOS versions. In particular, the all NPN version of Figure 37b has the same cross coupling and consequent symmetry but will not have the high input impedance of the CVF of Figures 36 and 37a. The aE NMOS version of Figure 37c will not have the high speed of the CVF of Figures 36 and 37a. Also, in all of the CVFs the ratio of current division by the cross coupling could be changed by ratioing the emitter areas or gate widths of the cross-coupling devices. As shown in Figures 33, the output of the Composite Voltage Follower drives the bases of NPNs Q191 and Q193 in output stage 3240 in the lower righthand portion of Figure 33d. The output terminal Out of output stage 3240 feeds back to CMOS stage 3220. Resistor 3261 of Figure 32 corresponds to R167 in Figure 33b, and resistor 3262 of Figure 32 corresponds to the series resistors R607, R693, R694, R695, and R696. CMOS stage 3220 has as inputs differential NMOS pair M621 and M639 tied to NPN current source Q627 and Q626 plus resistor R630 of Figure 33a. The differential outputs of the NMOS pair connect to the differential outputs of bipolar stage 3210 at cascode PMOS M27, M30, M31, and M32. The clamp terminal in Figure 32 corresponds to the Clamp terminal at the lefthand edge of Figure 33a. Switches 3251 and 3252 of Figure 32 are implemented primarily by NPN Q625 driven by differential PMOS pair M645-M646 with current mirror load of NMOS M641-M642 in Figure 33a. In particular, a low (ground) signal at terminal Clamp turns on M645, turns off M646, and pulls node 3303 up to about -2.2 volts (at room temperature) because the diode stack NPNs Q631, Q632, Q619, and Q638 limits anything higher. This turns on NPN Q625 and thus steers the current supplied by PMOS current source M614 away from PMOS M620 and into NPN current source Q626. With no current supplied by M620, all of the current for NPN source Q156 (Figure 33c) comes from the bipolar differential pairs and puts bipolar stage 3210 into maximum gain condition. Also, Q625 supplying the current to source Q626 implies Q627 turns off and inactivates CMOS differential pair M621-M639, so CMOS stage 3250 presents high impedance outputs. Conversely, a high (+5 volts) signal at terminal Clamp turns on M646, turns off M645, and pulls node 3303 down to about -3.6 volts (because the base of NPN Q633 is at about -2.9 volts) which turns off NPN Q625 and thus steers the current supplied by PMOS M614 into PMOS M620 and then into NPN current source Q156. Supplying this current to Q156 leaves only a small trickle current to be drawn from die bipolar differential pairs, and bipolar stage 3210 remains active but with very small gain. With Q625 turned off, NPN Q627 supplies the current from source Q626 to NMOS pair M621, M639. The output of the NMOS pair will overpower tiiat of the reduced gain bipolar stage 3210, and the resistor feedback from Out to the NMOS pair will hold amplifier 3100 at a 0 volt output. CMOS stage 3220 has lower transconductance than bipolar stage 3210, 5 so the amplifier is more stable in the clamp mode. i summary, DAC 310 and amplifier 3100 operate together as follows. Initially, a low SWITCH signal holds the input to DAC 310 at 1000 000 to thus its output at 0 current, and a low Clamp signal puts amplifier 3100 in clamp mode with CMOS stage 3220 holding the output at 0 volts despite any nonzero V k input from sample and hold 10 304. When the SWITCH signal goes high the encoded quantized version of V k (A7A6...A1) enters DAC 310 and the output current of DAC 310 begins settling to V^R where V„, equals the reconstructed quantized version of V.,. At this time the inputs to bipolar stage 3210 of amplifier 3100 are ground at the noninverting input and DAC 310 output current plus VJR current from sample and hold 304 at the inverting input. 5 Amplifier 3100 remains in clamp mode for a delay period of about 10 nsec. This permits other switching noise to attenuate and the DAC 310 output current to get close to -V- q /R to avoid overdrive saturation of bipolar stage 3210. Then the Clamp signal goes high to disable CMOS stage 3220 and jump the gain of bipolar stage 3210. Bipolar stage 3210 then settles to its amplification of the settling quantization error. DAC 310 settles to 14- 0 bit accuracy (0.3 mV) within about 50 nsec. The bipolar stage 3210 has a high cutoff frequency and amplifier 3100 tracks the settling quantization error. Similarly, amplifier 3101 tracks the output of amplifier 3100 so that the overall output of error amplifier 312 settles to within 4 mV of final output within 80 nsec. Amplifier 3100 could be configured for general purpose use. The inputs to the bipolar and NMOS differential pairs could be tied together as the differential inputs, and the digital signal at terminal Clamp just a selection between the bipolar and NMOS inputs. Thus amplifier 3100 is a channel selectable amplifier with the two channels providing different performance. The bipolar channel provides high speed and low noise operation, while the CMOS channel provides high input impedance. SB latch LSB latch 314 is a set of seven standard latches, 314-1 through 314-7 indicated in Figure 9, which are clocked to load die outputs of translators 908-1 through 908-7 at the falling edge of the FLASH2 clock. The falling edge also cuts off the current to latches 1030 and reapplies current to the differential pairs 1021-1022 in comparator cells 902, and so prepares flash converter 308 for anotiier conversion. The outputs are called Cl, C2, ...C7. Subtracter Subtracter 316 is simply a binary adder that subtracts 0000 010 from A7 A6 ... Al by adding the two's complement of 0000 010, namely 1111 110, to A7 A6 ...Al and calling the result B12 Bll ... B6. The carry bit is called CR1: Subtracting 0000 010 compensates for the 1000 000 output of flash converter 306 with a 0 volt input during the second flash conversion to create the least significant bits. A more detailed explanation appears in the discription of error correction block 318. Subtracter 316 performs the substruction within about 6 nsec, and during this time DAC 310 has begun to settle to its V^R output current, but error amplifier 312 remains clamped. Error correction Figure 38 schematically shows the circuitry of error correction block 318. This logic implements part of the following procedure and many other implementations also exist and can be automatically generated by logic design programs. A7 A6 A5 ...Al denotes the output of flash converter 306 on the first conversion of input V k and held in MSB latch 308; that is, A7 A6 ...Al is the binary coding of the quantized version V q of V j , with quantization levels spaced 39.0625 mV and with V^ equal to 0 volts ideally yielding A7 A6 ... Al equal to 1000 000 due to the bipolar input range. DAC 310 reconstructs the quantized version V q of V k from the binary code; call this V,,. Thus, ideally, Vj,, and V„, only differ by at most 19.53125 mV (one half of a 39.0625 mV quantization level). Error amplifier 312 outputs 32(V k -V fq ) and this ideally falls in the range of -0.625 V to +0.625 V and leaves room for error as will be described below. Figure 39 heuristically illustrates how V k within a quantization level will lead to 32(V k - V„ within the -0.625 to +0.625 volt range for the second conversion. Flash converter 5 306 converts 32C V,,) to C7 C6 ...Cl which LSB latch 314 stores. Due to the amplification by 32, the quantization level separation of 39.0625 mV on the second conversion corresponds to a 1.22 mV level in V^-V,,. Again, if V^-V,,, is 0, then C7C6...C1 equals 100 0000. Subtracter 216 subtracts 0000010 from A7 A6 ... Al and the result is termed B12 Bll ... B6 with the carry termed CRl; the carry term results from the subtraction being performed by addition of the two's complement of 0000010, namely 1111 110. Thus V k equal to 0 would ideally haveB12 Bll ... B6 equal to 0111 110 and CRl equal to 1. This subtraction of 0000010 compensates for C7 C6 being 10 when the quantization error V k - V„, equals 0. Error correction block 318 (Figure 38) adds C7 C6 to B12 Bll ... B7 B6 to yield D12 Dll ... D7 D6 and with carry called CR2: B12 Bll B10 B9 B8 B7 B6 + C7 C6 CR2 D12 Dll D10 D9 D8 D7 D6 Lastly, the final output by output buffer 320 will be D12 Dll ... Dl where D5 = C5, D4 = C4, D3 = C3, D2 = C2, and Dl = Cl. Also, the exclusive OR of CRl and CR2 outputs as OR. To clarify the foregoing, consider an example in the ideal case of errorless devices. Let V k be +1.1000 volts. First, 1.074 volts is the highest quantization level which does not exceed +1.1000 volts; thus flash converter 306 will output 1011 100 because 11 100 is binary for 28 and 28 times 39.0625 mV equals 1.09375 volts which is the midpoint between the quantization levels for codes 28 and 29. The leading 1 in the 1011 100 output just represents the fact that V k is positive; recall that a 0 input generates a 1000000 output and negative inputs generate leading 0 outputs. So A7 A6 ... Al equals 1011 100. Ii this were expressed in terms of a quantization with quantization levels separated by 1.22 mV (as in die final output of converter 300), tiien the code would simply be 1011 1000 0000 because 11 1000 0000 is binary for 28 times 32 and 28 times 32 times 1.22 mV equals 1.09375 volts. Subtractor 316 adds 1111 110 and 1011 100 to give B12 Bll ... B6 equal to 1011 5 010 with a carry to make CRl equal to 1. Note that CRl is always 1 unless A7 A6 ... Al were 0000 000 or 0000 001 which corresponds to V^ being about -2.5 volts or out of range and below -2.5 volts. Next, DAC 310 takes the 1011 100 input and reconstructs +1.09375 volts, the first quantized version of V^ and previously called V„,. Then error amplifier 312 amplifies die quantization error (V^-V,,) of +0.00625 volt by 32 to yield +0.2000 volt. Now +0.176 volt is the highest quantized level below +0.2000 volt, so flash converter 306 will convert 0.2000 to an output of 100 0101 because 101 is binary for 5 and 5 times 39.0625 mV equals 0.1953 volt which is the midpoint between the quantization levels for codes 5 and 6. Again, the leading 1 represents die fact diat the input was positive. C7 C6 ... Cl equals 100 0101. Because +0.2000 volt is 32 times +0.00625 volt and 39.0625 mV is 32 times 1.22 mV, die first quantization error (V^-V,,) itself quantizes as 000101 in terms of 1.22 mV separated quantization levels. Thus the 00 0101 directly added to die 1011 1000 0000 from die 1.22 mV level version of the first quantization gives the final output of 1011 1000 0101. Thus die leading 1 for a second flash conversion output must be compensated if C7 C6 ... Cl is to be added to yield the final output. The subtraction of 01 from A7 A6 ... Al to form B12 Bll ... B6 is just tiiis compensation; furthermore the increment of the index by 5 expresses the first quantization in terms of 1.22 mV levels. Note diat the maximum input to flash converter 306 on die second flash conversion is 625 mV, so the maximum output is 101 0000 widi die leading 1 again indicating a positive input. This means diat die most significant two bits C7 and C6 do not (with errorless devices) contain any information beyond the already-compensated sign of the first quantization error and can overlap B7 and B6. Hence, D12 Dll ... Dl as the sum of B12 Bll ... B6 and C7 C6 ... Cl will be the correct result previously noted: 1011 010 + 100 0101 1011 1000 0101 and the carry CR2 equals 0. CR2 will always be 0 unless B12 Bll ... B6 is 1111 111 or 1111 110 which means A7 A6 ... Al must have been 0000 000 or 0000 001, again V k 5 was about -2.5 volts. As previously noted, CRl is always 1, so the exclusive NOR of CRl and CR2 is 0. The CRl and CR2 bits provide out of range detection of V k as follows. If V k exceeds +2.5 volts, tiien die first flash conversion yields A7 A6 ... Al equal to 1111 111 and the quantization error is greater than +39.0625 mV because DAC 310 reconstructs 10 1111 111 as 2.4609375 volts, the highest quantization version. Hence, error amplifier 312 outputs a voltage exceeding +1.25 volts, and the second flash conversion output C7 C6 ... Cl is at least 110 0000. Subtractor 316 computes B12 Bll ... B6 as: 1111 111 + 1111 110 5 1 1111 101 So CRl equals 1. Adding B12 Bll .. B6 and C7 C6 to generate D12 Dll ... D6: + 11 1 0000 000 0 And CR2 also equals 1. Thus the exclusive NOR of CRl and CR2 is 1 which indicates overflow/underflow, and D12 Dll ... are 0's so it is an overflow. Similarly for V k less tiian -2.5 volts: A7 A6 ... Al is 0000000 and error amplifier 312 outputs a voltage less tiian -1.25 volts. The second flash conversion outputs at most 011 1111. Subtractor 316 computes B12 Bll .. B6 as: 5 0000 000 and CRl is 0. The computation of D12 Dll ... D6: 1111 110 and CR2 also is 0. Hence, the exclusive NOR of CRl and CR2 again is 1 and indicates * 5 the overflow/underflow, and D12 Dll ... are l's so it is an underflow. Nonideal devices in converter 300 may lead to errors in the output, but die ■ * foregoing procedure can correct for the most common ones. In particular, die most common source of error lies in the accuracy of flash converter 306, and the headroom (see Figure 39) available in flash converter 306 on the second flash conversion permits the 10 correction as follows. If flash converter 306 outputs a code that is 1 LSB higher than it should be, then DAC 310 will reconstruct V,,, that is 39.0625 mV higher than the true first quantization of V k , and error amplifier 312 will output an amplified quantization error diat is 1.25 volts lower tiian it should be. Thus the second quantization by flash converter 306 is one lower in C6 than it should be, and this precisely cancels the original code error of 15 1 LSB too high. An example will clarify: Let V k be +1.1000 volts as in the previous example, then the true first quantization level is 1.074 volts and flash converter 306 should output 1011 100. But presume flash converter 306 fails to be truly linear and outputs 1011 101 for this input. Then DAC 310 will reconstruct V„, using the erroneous code 1011 101 and output 1.13281 20 volts as V„,. Now the quantization error V^V,, equals -0.03281 volts ratiier than the +0.00625 volts tiiat would follow from a correct code. Error amplifier men amplifies this quantization error to -1.05 volts rather than the +0.200 volts following from a correct code. Note tiiat this falls out of die expected errorless range of -0.625 to +0.625 volt. Now flash converter 306 quantizes -1.05 volts as -1.0547 volts which is -27 times 39.0625 25 mV and outputs 0100101 because 100101 is the two's complement of 011011 which is binary for 27 and die leading 0 indicates a negative number. (Of course, die nonlinearity of flash converter 306 may again affect die least significant bit.) Then the computations " are as follows. Substractor 316 finds B12 Bll ... B6: 1011 101 l ion on This compares to B12 Bll ... B6 equal to 1011 010 for die correct code case. Next, error correction 318 adds C7 C6 to find D12 Dll .. D6: 1011 011 + 01 5 1011 100 and filling in the C5 ... Cl yields the final output as 1011 10000101 which is hte correct final output. A similar correction takes place if flash converter 306 outputs a code 1 LSB too small. Again using tiie example of V equal to + 1.1000 volts: The first flash converter 10 306 output would incorrectly be 1011 011 and DAC 310 would reconstruct V,, as 1.0547 volts. Then die first quantization error V f c-V,,) would be +0.0453, and error amplifier 312 would output +1.45 volts for die second flash conversion. The second flash converter 306 output would be 1100101 because 100101 is binary for 37 and die leading 1 indicates a positive. The computation of B12 Bll ... B6 is: 5 1011 011 + mi no 1 1011 001 and the addition of C7 C6 (11) to yield D12 Dll ... D6: 1011 001 0 + 11 1011 100 Filling in C5 .. Cl gives a final output of 1011 1000 0101 which matches die correct output; of course, the least significant bit could be different due to die nonlinearity of flash converter 306 on die second flash conversion. 5 The maximum correctible error from incorrect code on die first flash conversion is 1.5 LSB because die headroom on die second flash conversion (see Figure 39) is 1.875 volts, both for positive and negative, and this equals 32 times 1.5 times 39.0625 mV. Overflow/underflow Overflow/underflow block 324 is just an exclusive NOR of CRl and CR2 as explained in die description of error correction block 318. Figure 40 shows thirteen flip- flops for storing die seven bits D12 Dll ... D6 from error correction block 318, the five 5 least significant bits C5 C4 ... Cl (D5 D4 ... Dl) from LSB latch 314, and the exclusive NOR of me two carries CRl and CR2 (upper righthand corner). The LOADOP signal clocks the flip-flops. Output buffer Output buffer 320 includes fourteen drivers each the same as driver 4100 shown 10 in Figure 41. One driver for each of outputs D12 D11 ... Dl, one for die exclusive NOR output of overflow/ underflow block 324, and one for die IRQ (interrupt request) signal. Driver 4100 operates with CMOS digital power levels: between +5 volts and ground. The data bits D12 Dll ... Dl and exclusive NOR output enter driver 4100 at the IN terminal and an enable signal at die EN terminal controls driver 4100. Driver 4100 15 provides NPN output transistors 4102-4103 to drive capacitive loads beyond the capabilities of simple CMOS drivers plus also provides a lower output voltage V OL than prior art BiCMOS driver 4200 shown in Figure 42. In particular, die simple driver of 4200 cannot achieve low V 0L levels, such as less tiian 0.4 volts, especially at low • termperatures, due to die base emitter drop of NPN 4203 when it is on and pulling die 20 output low. Figure 43 shows driver 4300 which is a version of driver 4100 simplified by die removal of die enable circuitry (NMOS 4150-4156) and die ESD protection NPNs 4104-4105. Prior art driver 4200 operates as follows: a high input at IN inverts through CMOS inverter 4206-4207 to a low and thus turns on PMOS 4210 and turns off the NMOS 4211- 25 4212. PMOS 4210 on drives the base of NPN 4202 high to turn on NPN 4202 and pull up output terminal OUT. The PMOS 4210 on also pulls up the gate of NMOS 4213 which turns on NMOS 4213 to pull the base of NPN 4203 to ground and keep NPN 4203 off. NMOS 4211-4212 off isolate output terminal OUT from the bases of NPNs 4202-4203; and OUT is high. Conversely, a low at input IN inverts tiirough CMOS inverter 4206- 4207 to a high that turns off PMOS 4210 and turns on NMOS 4211-4212. NMOS 4212 on connects die base and collector of NPN 4203 togetiier to form a diode and pull OUT down to about 0.7 volts but no lower: this is die V O problem. During switching, die base charge must be rapidly removed to avoid delays, and NMOS 4211-4213 accomplish this. 5 Drivers 4100 and 4300 include the same devices as driver 4200 but have additional circuitry to generate a low output V OL lower tiian 0.7 volts by enhanced driving of die base of output NPN 4303. Li particular, NMOS 4321 and resistor 4320, in addition to the diode connection dirough NMOS 4312 (plus diode 4322), drive the base of NPN 4303. Drivers 4100 and 4300 operate as follows. A high input at IN will invert and turn on 10 PMOS 4310 to drive the base of NPN 4302 and will turn off NMOS 4311-4312 and also NMOS 4321; this operates in die same manner as driver 4200 for a high input. Conversely, a low input at IN inverts to turn on NMOS 4312 which makes die connection of base and collector of NPN 4303 (dirough diode 4322) to form a diode and pull OUT down to about 1.4 volts, analogous to the operation of driver 4200. But die low at IN also 15 inverts to turn on NMOS 4321 which supplies drive from Vdd dirough resistor 4320 to put NPN 4303 into saturation and tiiereby drop die collector-to-emitter voltage to about 0.1 volt. This saturation pulls down OUT to about 0.1 volt. Diode 4322 prevents die drive by NMOS 4321 from shunting directiy to OUT and lessening its effect. Lastiy, small resistors may be inserted between OUT and each of die NPNs 4102-4103 and 4302- 20 4303 in order to reduce inductive (from bond wires) kickback under capacitive loads. Driver 4100 operates in die same manner as driver 4300 when die EN input is high due to NMOS 4154-4156 and PMOS 4152 all being turned on and NMOS 4153 being turned off. Conversely, EN low turns off PMOS 4152 to isolate PMOS 4110 and keep NPN 4102 off, turns on NMOS 4153 to keep NPN 4103 off, and turns off NMOS 4154- 25 4156 to isolate OUT and stop base driver NMOS 4121. That is, driver 4100 presents a high impedance at OUT. The fourteen drivers 4100 within output buffer 320 are arranged along die outer edge of die silicon die containing the circuitry of converter 300. The enable signal for die drivers propagates along die die edge so diat die drivers turn on sequentially widi a small 0 (<1 nsec) delay between turn ons to lessen ground bounce and other noise diat accompanies die power switching. Figure 44 shows a layout of converter 300 widi fourteen drivers marked 4401-4412 for Dl through D12, 4413 for the exclusive NOR, and 4414 for IRQ. Signals originate in area 4450 and propagate in die direction of die arrows. Lastly, die output format follows from die state of external signal A0: A0 low has buffer 320 output a 12-bit word as described, and A0 high splits the 12-bit word into two 8-bit words widi die second word having four trailing 0s. Buffer 320 multiplexes die two 8-bit words. Timing, controller, and oscillator Timing controller and oscillator block 330 includes timing generator 4500 shown in Figure 45 and made of seven oscillator cells 4501-4507, each of die structures shown in Figure 46a as cell 4600. Cell 4600 basically generates a timed delay by sensing when die charge on a capacitor being charged by a constant current source reaches a tiireshold value. Varying die capacitance or the current or both varies the time interval. In more detail: a constant current of 65 uA is mirrored into PMOS 4602 (suggested by die broken line PMOS 4601 diode in Figure 46a); tiius when the signal at terminal CNTRL switches low, this mirrored current passes through turned-on PMOS 4605 and begins charging up a capacitor (suggested by broken line capacitor 4607) at terminal CAP. The voltage at CAP increases linearly widi time. Now the NMOS differential pair 4611-4612 widi PMOS current mirror load 4615-4616 form a comparator widi one input, die gate of NMOS 4611, connected to CAP and the other input, the gate of NMOS 4612, connected to a reference voltage of Vdd/2 volts supplied by a voltage divider to terminal BIAS2.8. Consequently, when die voltage at CAP is increasing from 0 towards Vdd/2 volts, die comparator output at node 4620 remains low and the inverters 4621-4622 buffer this to a low at terminal OUT, plus inverter 4623 inverts tiiis to a high at terminal #OUT. Also, inverter 4621 inverts the low at node 4620 to a high that keeps PMOS 4630 off. Now when die voltage at CAP approaches Vdd/2 volts, die comparator begins switching to a high output at node 4620, and inverter 4621 inverts this to a low which turns on PMOS 4630 to supply a large current to help rapidly charge up capacitor 4607. That is, PMOS 4630 provides positive feedback and thereby sharpens die transition; see Figure 47 showing die voltage at CAP for various capacitors. CNTRL low also keeps NMOS 4605 turned off, but when the CNTRL switches high, NMOS 4605 will turn on to discharge capacitor 4607 to ground. Furtiier, a high signal at terminal MR (master reset) will also discharge capacitor 4607 to ground. Li short, when CNTRL is high, CAP is low, OUT is low, and #OUT is high; and when CNTRL is low, CAP ramps up, OUT goes high after die ramp delay, and #OUT goes low after die ramp delay. The comparator 4611-4612 plus 4615-4616 detection could be replaced by a simple inverter designed to switch at a particular threshold as shown by inverter 4630 in Figure 46b. This alternative eliminates two devices and the bias line from cell 4600; die threshold of inverter 4630 can be adjusted by setting die ratio of the gate widths of die PMOS 4631 and NMOS 4632 making up inverter 4630. The comparator approach of cell 4600 permits accurate control of die switching point by control of die bias point which can be placed at levels otiier tiian Vdd/2. Widi a comparator the bias may be referenced to a fraction of Vdd and thus at higher supply voltages die bias point is higher and die pulse width is almost constant; in contrast, with an inverter the this is less tightly controlled because die tiireshold has a greater variation widi respect to supply voltage. Further, die dependence of carrier mobility on temperature implies a general slowing down of devices widi increasing temperature, so providing a current to mirror into PMOS 4602 that varies with temperature in a desired way will yield a pulse width diat varies as desired widi temperature. Further, die current mirror could have different size devices for different cells so diat die capacitors would not have to be varied in size for die different time intervals required, and die current mirror could be realized widi bipolar transistors. And replacing die inverter fed by CNTRL widi more complex gates can provide for further control of die timing. Figure 45 shows die seven oscillator cells 4501-4507 arranged sequentially widi die #OUT of each cell feeding die CNTRL input of die next cell so die cells activate in sequence. OR gates 4511-4517 each has inputs of the CNTRL and OUT of the corresponding cell; tiius an OR gate goes low precisely when CNTRL goes low and OUT has not yet switched high due to die ramp delay. Because die #OUT signal is one gate delay from die OUT signal, each OR gate will be high before die succeeding OR will go low and die sequence of pulses from die OR gates will be nonoverlapping. Timing diagram Figure 5 illustrates the outputs of die OR gates with their following inverters which have large size for driving large loads: OR gate 4511 provides die 30 nsec low- going HLDSTTL (holdsettle) pulse of die second from die bottom panel of Figure 5, OR gate 4512 plus inverter die 28 nsec FLASHl pulse of die tiiird from the bottom panel, OR gate 4513 plus inverter the 80 nsec DACSTTL pulse of the fourth from die bottom panel, OR gate 4514 plus inverter die 28 nsec FLASH2 pulse of die fifth from tiie bottom panel, OR gate 4515 plus inverter die 20 nsec LOADOP pulse in die sixth from die bottom panel, OR gate 4516 plus inverter die 100 nsec ACQUIRE pulse of the seventh from the bottom panel, and OR gate 4517 plus inverter die 20 nsec EOC pulse of the top panel. Of course, timing generator 4500 could have been realized by an oscillator driving a ripple counter widi decoding die count to provide the timing pulses; however, use of an oscillator (widi a 10 nsec period) would have created periodic switching noise which die capacitor charging of cells 4501-4507 avoids. Figure 48 illustrates schematically controller 4800 witiiin block 330. Controller 4800 receives die external control signals of chip select (#CS, active low), output enable (#OE, active low), convert (#CONV, active low), plus internal signals FLASHl, FLASH2, and EOC from timing generator 4500, and generates die internal control commands CNTRL ("control" which drives timing generator 4500), IRQ ("interrupt request" which drives sample and hold 304 plus an external bus driver), flashclock, and Outputen (enabling output drivers in buffer 320). Controller 4800 operates as follows: first, when #CS is high at terminal 4802, then both NOR gates 4804-4805 are low and this holds Outputen terminal 4808 low and feeds low data to flip-flops 4810-4811. The #Q output of flip-flop 4810 drives the CNTRL signal, so flip-flop 4810 widi low data implies CNTRL remains high and keeps timing generator 4500 from starting a new cycle and converter 300 becomes idle. Now presume #CS is low. A high signal at #CONV terminal 4812 also drives NOR gate 4804 low to feed low data to flip-flops 4810-4811 to prevent timing generator 4500 from starting a new cycle. When #CONV switches low, NOR gate 4804 goes high, and flip-flops 4810-4811 have a high at tiieir data inputs. NOR gate 4804 going high also propagates presuming EOC at terminal 4822 is low) dirough die inverter chain made of NAND gate 4830 and inverters 4831-4835 to clock flip-flops 4810-4811 about 8 nsec after the high at their data inputs; this delay insures die data input is high and filters out very short #CONV pulses. Thus a low going #CONV pulse of duration greater tiian 8 nsec makes CNTRL go low and IRQ go high about 10 nsec after #CONV switches low, and tiiese values are held in flip- flops 4810-4811 until reset. Note that EOC is low because CNTRL was high and all capacitors in the oscillator cells are in reset condition giving a low output. As described previously, CNTRL going low activates timing generator 4500 which tiien outputs die pulses of Figure 5 to drive a conversion cycle by converter 300. Also, IRQ going high switches sample and hold 304 into hold mode, so die aperture delay of converter 300 is the delay from CONV to IRQ plus die switching in sample and hold 304. The aperture jitter is kept to a very low level by die sharp tiiresholds of die inverter chain. Note tiiat die external input terminals #CS, #EN, #CONV, and #A0 each has a translation buffer for conversion from TTL (0.8 volt low and 2.0 volt high) to digital CMOS levels, and die typical 8 nsec delay includes tiiis translation. The end-of-conversion pulse EOC from timing generator 4500 feeds back into controller 4800 at terminal 4822, and if #CONV remains low, men die EOC pulse triggers another conversion, but if #CONV has returned high, tiien EOC has no effect. In particular, witii #CONV low, a high going edge of EOC will propagate dirough inverter 4840, NAND gate 4830, and inverter chain 4831-4835 to drop the clock input to flip-flops 4810-4811 low. The high going edge of EOC will also switch AND gate 4842 high, and thus drive OR gates 4844 and 4848 high to reset flip-flop 4810 and switch CNTRL high. CNTRL going high will put a low at the input of the AND gate 4842 terminating the EOC pulse with a propogation delay of gates 4842, 4844, 4848, and 4810. The reset of flip- flops 4810-4811 overrides any otiier signal. Then die falling edge of die EOC pulse will propagate dirough die same chain to drive die clock inputs of flip-flops 4810-4811 high and clock in die highs (from #CONV low) at tiieir data inputs and tiiereby drive #CNTRL low to start another cycle by timing generator 4500. Thus #CONV held low results in a continuous conversion mode by converter 300. ACQUIRE pulse going high at terminal 4852 from die timing generator 4500 resets flip-flop 4811 to put IRQ low until die next cycle. For the duration of the time that CNTRL remains high the converter will not start a new cycle because the EOC signal from terminal 4822 blocks NAND gate 4830. Controller 4800 just ORs FLASHl and FLASH2 from timing generator 4500 and input at terminals 4861-4862 to create FLASHCLK at terminal 4863 to drive flash converter 306. The falling edge of FLASHl also clocks flip-flop 4871 to load the data held by flip-flop 4810 (#CNTRL) and output this through AND (which is for testing purposes only) to 4873 as signal SWITCH. This SWITCH signal releases DAC 310 from die 1000 000 input (see Figure 30) and switches analog switch 334 to direct the output of error amplifier 312 to flash converter 306 to set up converter 300 for the second conversion at FLASH2. Figure 49 recapitulates die overall timing for converter 300 for continuous conversion operation as represented by CONV remaining low in die first panel. The falling edge of CONV drives controller 4800 after a delay of 6 nsec through NOR 4804, NAND 4830, and inverters 4831-4835 to simultaneously clock flip-flops 4810 and 4811 to switch CNTRL low and IRQ high (second and third panels of Figure 49). IRQ going high turns on an output bus driver to signal an interrupt to the microprocessor or other signal processors being fed conversions by converter 300. IRQ switching high also drives level translator 725 in sample and hold 304 which switches transmission gate 721 to disconnect die output of amplifier 602 and tiius begin amplifier 604 holding V to on capacitor 606. CNTRL going low starts a cycle of timing generator 4500 and includes driving HLDSTTL low after one OR gate 4511 switching delay (fourth panel of Figure 49). The disconnection by transmission gate 721 in sample and hold 304 contributes a finite charge injection into node 606 and HLDSTTL provides a settling time of 30 nsec before returning high to start die next timing pulse. The comparators of Flash converter 306 have been and continue tracking die output of sample and hold 304 and sending a quantized version to the NPN encoder of Flash converter 306. One gate delay after HLDSTTL returns high FLASHl goes high to drive Flashclk high and have die comparators and NPN encoder latch in die 7 bits encoding die quantized output of die comparators. The falling edge of FLASHl (28 nsec later) drives down FLASHCLK to latch the 7 bits in the CMOS latches (MSB Latch 308) but releases the comparators and die encoder array. One gate delay after FLASHl returns low DACSTTL switches high to start an 80 nsec settling time pulse; see fifth and sixtii panels of Figure 49. The falling edge of FLASHl also after a gate delay clocks flip-flop 4871 to drive SWITCH high in controller 4800. SWITCH going high performs three functions: (1) it switches the input of the DAC from 1000000 to the 7 bits held by MSB Latch 308 and thus DAC begins slewing to its final output, (2) activates Subtractor 316 to subtract 0000010 from the 7 bits in MSB Latch 308, and (3) tiirows analog switch 334 to feed die output of error amplifier 312 to flash converter 306 instead of die output of sample and hold 304. Thus die flash converter comparators and encoder array are now tracking die output of error amplifier 312 which is still clamped to 0 volts. The subtraction in Subtractor 316 generates noise, but is completed witiiin 6 nsec. After a delay of 10 nsec from SWITCH going high to allow noise at die input to error amplifier 312 due to various switching happening on the chip to subside (including subtractor, timing generator, switch, and DAC output), the clamp is released from error amplifier 312 (see eighth panel of Figure 49) which then begins to settle to amplifying die difference of die DAC output (still settling but already witiiin a 100 mV of its final value) and the held V k output of sample and hold 304. The remaining 70 nsec of the DACSTTL pulse permit DAC and error amplifier settling. Indeed, simulations show DAC settling to 14-bit accuracy in about 50 nsec. Flash converter 306 is tracking die error amplifier output. One gate delay after DACSTTL returns low FLASH2 goes high to drive FLASHCLK high and have die comparators and die encoder of flash converter 306 latch die 7 bits encoding die quantized version of die output of error amplifier 312, and die falling edge of FLASH2 (28 nsec later) drops FLASHCLK low which latches the 7 bits in the CMOS latches of LSB Latch 314. See the ninth panel of Figure 49. One gate delay after FLASH2 returns low LOADOP goes high to drive and LOADOP remains high for 20 nsec for die digital computation. One gate delay after LOADOP returns low ACQUIRE goes high to drive IRQ low and perform six functions: (1) terminate die interrupt signal on the output bus, (2) switch the input to DAC 310 from the 7 bits in MSB Latch 308 to the 7 bits 1000000 and thereby force DAC 310 back to a 0 volt output, (3) switch Clamp high to clamp error amplifier 312 to a 0 volt output, (4) put the results of the data output flip-flops onto die output bus, (5) switch sample and hold 304 back to the sampling mode, and (6) drive SWITCH low to tiirow analog switch 334 to feed die output of sample and hold 304 to flash converter 306 instead of die output from error amplifier 312. Thus flash converter 306 begins tracking die varying V k output of sample and hold 304 again. ACQUIRE remains high for 100 nsec to permit sample and hold 304 to settle in to tracking V k . One gate delay after ACQUIRE returns low EOC goes high to drive CNTRL high, and then 20 nsec later EOC goes low to drive CNTRL low and IRQ high to begin another conversion cycle. Note that the 20 nsec of EOC high is also time for sample and hold 304 to settle to tracking V k . The timing of operations shown in Figure 49 have various features, including die following. (1) SWITCH simultaneously changes the 7 input bits to DAC 310 from 1000 000 to the 7 bits in MSB Latch 308 in contrast to just letting DAC 310 follow the 7 bits being output be encoder array 906 of flash converter 306; tiiis prevents extreme output swinging (such as if the second most significant bit switches and tiien shortly thereafter die most significant bit switches) and may provide a quicker overall settling of DAC 310 despite die extra time taken to load MSB Latch 308 and switch die gates in Figure 30. The 10 nsec delay between SWITCH going high and Clamp going low covers me time for Subtractor 316 to complete its operation plus DAC 310 to complete the bulk of the output swing; tiius the noise generated by digital Subtractor 316 and large swings of DAC 310 output subside prior to activation of error amplifier 312 and help avoid saturation of its transistors. In contrast, if the error amplifier were continually active but with diode output clamping in an attempt to limit transistor saturation, tiien die large input swings and noise during die 10 nsecs while DAC 310 output swings and subtractor 316 switches may cause Zener breakdown of die emitter-base junctions of input transistors and, furthermore, the output of die error amplifier likely would swing rapidly between its clamped extremes and 5 thereby drive flash converter 306 wildly. The timing of converter 300 illustrated in Figure 49 aggregates the digital noise from subtractor 318 with the rapid swings of DAC 310 in die same 10 nsec period during which error amplifier 312 is clamped and has input transistors in a very low current state. (2) Anotiier feature of the timing of Figure 49 is the simultaneous switching of 10 sample and hold 304 from hold mode to sampling mode and die tiirowing of analog switch 334 to switch the input to flash converter 306 from die output of error amplifier 312 (which is simultaneously being clamped) to die output of sample and hold 304. Both die throwing of analog switch 334 and die switching to sampling mode create large transients for the input of flash converter 306, and tiius the aggregation of these transients into a 15 single time interval provides for quicker overall converter operation. The 100 nsec duration of the ACQUIRE pulse plus die following 20 nsec of die EOC pulse provide sample and hold 304 sufficient time to settle to tracking V k (t); Figure 8 shows a simulation. Recall diat die input amplifier 602 was grounded during die hold mode to prevent saturation, and tiiat widi an input bandwidth of 30 MHz die input V k to amplifier 20 602 could have oscillated between its extremes five or six times during tiie hold mode. (3) A further feature of die timing of Figure 49 occurs when flash converter latches in a quantization and its encoding: converter 300 does not execute any other operations simultaneously and die latching by flash converter 306 happens at die end of a quiet settling period: after die 30 nsec of HLDSTTL or after the 70 nsec of DACSTTL 5 following die 10 nsec delay. This prevents noise generated by otiier operations corrupting the accuracy of die flash conversions; in particular, the subtraction in block 316 operation must be performed prior to die error correction in block 318 if both carries CRl and CR2 will be used, and thus aggregating die subtraction with the intial swings from DAC 310 effectively puts the subtraction noise in an already-disturbed time interval. If both carries 0 were not needed, tiien die subtraction could be merged widi the error correction. A feature not explicit in die timing of Figure 49 lies in die sequential turning on of the output drivers in buffer 320 to avoid kickback (note die inductive bond wires from the substrate to its lead frame) and ground bounce that may occur witii all drivers being simultaneously turned on. As indicated by layout Figure 44 die drivers are located along 5 die outer edge of die silicon substrate containing converter 300, and tiiese drivers have data lines and an enable line that originate in area 4450 and follow the edge of die substrate and tiiereby provide by tiieir propagation delay a sequential turning on of die drivers. Note tiiat all of tiiis driver activity occurs at the same time mat die rising edge of ACQUIRE switches sample and hold 304 to sampling mode and tiirows analog switch 10 334; diat is, die driver transients are also aggregated with other noisey operations into a common time interval. Alternative embodiments mat preserve some of tiie foregoing timing features include using an always-on amplifier, but switching off its input during the 10 nsec (or more) mat include die largest transients of DAC 310. The DAC could have continually 5 updated input bits widi such an input-switched error amplifier. The following table summarizes the operation of converter 300 in terms of die external inputs #CS, #CONV, #OE, and #A0; the table also shows the output IRQ: #CS #CONV #OE #A0 IRQ Function No operation 0 Continuous convert mode Output 12-bits or 8 MSBs Output 4 LSBs with trailing 0s Converter in acquisition mode Converter doing conversion 5 High impedance output state Of course, die continuous convert mode requires a falling edge for #CS and #CONV to get started. Figure 50 schematically shows the power up reset (PUR) circuit 5000 within block 330. Circuit 5000 provides a PUR pulse to insure various components of converter 300 0 are put into known initial states upon power up of converter 300. In particular, the two digital power supplies, Vdd at +5 volts and Vss at -5 volts, and die two analog power supplies, Vce at +5 volts and Vee at -5 volts, may be applied in differing orders and lead to erratic behavior by partially powered-up devices. Circuit 5000 operates as follows: NMOS differential pair 5001-5002 compares die voltages at nodes 9 and 10 where die voltage at node 9 is resistor 5011, 5013 division of Vce to ground and equal to about 0.6 Vce, and the voltage at node 10 is resistor 5012 diode NMOS 5010 division of die same Vce to ground. So Vce rising from ground towards +5 volts will cause the voltages on nodes 9 and 10 to rise. However, diode 5010 has a turn on voltage of about 1-2 volts; so for Vce small, die voltage at node 10 will track Vce and die voltage at node 9 will track 0.6 Vce. Diode 5010 has an on impedance tiiat together with resistor 5012 divides Vce to about 0.5 Vce at node 10; thus as Vce increases above about 2 volts the voltage on node 10 increases less rapidly tiian that on node 9, and at Vce equal to about 4 volts die voltage on node 9 surpasses tiiat on node 10. Figure 51 illustrates die voltages at nodes 9 and 10 for a linearly increasing Vce. Now with Vce at about 2-3 volts die digital devices such as inverters 5030-5031 and exclusive NOR gate 5040 become active (Vdd connects to Vce through resistor 5020), and until NMOS 5001-5002 turn on both inverters 5030-5031 will see a Vce input and output lows to exclusive NOR 5040 and tiius a high PUR. NMOS differential pair 5001-5002 remains off until Vee has dropped below about -2.8 volts (four Vbe's) to turn on die current source made of NPN 5050, diodes 5051, and resistor 5052. Thus two cases occur: (1) Vce rises more quickly than Vee falls and (2) Vee falls more quickly tiian Vce rises. Li the first case no current flows in 5050-5051 because Vee is less tiian -2.8 volts and notiiing drives die differential pair 5001-5002. Therefore, resistors 5003 and 5004 pull both nodes 11 and 12 high widi die rising Vce and no current flows. This drives inverters 5030 and 5031 botii low giving a high at output PUR. As soon as a current flow from Vee dirough die current source is established, the differential pair 5001-5002 switches and forces nodes 11 and 12 in opposite directions due to the differential pair action, and this switches PUR low. Li the second case differential pair 5001-5002 has its current source on while Vce is still low, and Vce low implies low inputs to inactive invertors 5030, 5031. As Vce rises to about 2-3 volts, digital devices activate and NMOS 5002 conducts due to node 10 being higher tiian node 9. Thus, node 11 is high and node 12 is low to yield a low at PUR. Then when Vce reaches about 4 volts nodes 9 and 10 have about the same voltage and both NMOS 5001 and NMOS 5002 conduct to have nodes 11 and 12 both low and have exclusive NOR 5040 drive PUR high. Next, as Vce exceeds 4 volts, the voltage at node 9 exceeds die voltage at node 10, and NMOS 5002 stops conducting to switch node 12 high and tiius exclusive NOR 5040 high and PUR low. That is, as die voltage at node 9 passes diat at node 10 the inverters 5030-5031 sequentially switch and generate a PUR pulse. The width of die pulse depends upon the thresholds of inverters 5030-5031. The PUR pulse drives the master reset (MR) of both the cells of timing generator 4500 and controller 4800. Similarly, during normal operation if Vee should rise from -5 volts to about -2.8 volts, then PUR will go high until Vee again drops below -2.8 volts. Also, if Vce drops below about 4 volts, again PUR will go high. Hence, circuit 5000 also detects power supply interruptions. Voltage reference Voltage reference 326 provides a temperature stabilized reference voltage of about 2.5 volts witii a variation of at most 1 mV over a temperature range of -55 C to + 125 C. Voltage reference 326 includes a bandgap generator witii correction circuitry as shown in schematic Figures 52a-b and 53. In particular, voltage reference 326 includes a standard bandgap circuit plus a correction circuit 5300; for explanation, consider the simplifed version of voltage reference 326 shown in Figure 54. Operational amplifier 5402 (5202 in Figure 52a) drives die bases of NPN transistors 5411 and 5431 (5211-5224 in parallel and 5231-5232 in parallel, respectively, in Figure 52b) where NPN 5411 has an emitter witii seven times the area of the emitter of NPN 5431. The collectors of NPNs 5411 and 5431 connect to a power supply through equal resistors 5441 and 5442 (5241 and 5242 in Figure 52b) witii the inputs of amplifier 5402 tapping off at the collectors. Amplifier 5402 insures that die collector currents of NPNs 5411 and 5431 remain die same, and tiius the difference in emitter areas implies mat there is a difference in me base to emitter voltage Vbe for die NPNs. This difference voltage ΔVbe equals (kT/q)ln7 where k is Boltzmann's constant, T the absolute temperature, and q the electronic charge. ΔVbe equals about 50 mV at room temperature and increases linearly witii absolute temperature. This difference voltage appears across resistor 5445, and die voltage VgO at die bases of die NPNs is given by VgO = Vbe + (ΔVbe)2R ! /R 2 where Vbe is the base-emitter bias for NPN 5431, R t is the resistance of resistor 5446 and R 2 is the resistance of resistor 5445 (resistors 5246 and 5245, respectively, in Figure 52b). Now Vbe decreases linearly widi absolute temperature, so picking the ratio of the resistances correctly makes VgO temperature independent, at least to first approximation. The resistive divider made of resistors 5451- 5453 (resistors 5251-5253 in Figure 52a) steps up VgO to Vout which is close to 2.5 volts. The circuitry 5270 in Figures 52a-b suppresses power supply noise and cancels base current error of all NPNs connected to node VgO. To correct die output Vout (Vref in Figure 52b) for its approximate 6 mV variation over the temperature range -55 C to +125 C (illustrated in Figure 55), correction circuit 5300 absorbs a temperature-dependent compensation current loom from resistor divider 5451-5453 and thereby increases Vout by RIcom where R is the resistance of resistor 5451 (5251 in Figure 52a). Figure 56 shows correction circuit 5300 in simplified form. Compensating current loom is derived from comparing ΔVbe (which varies directiy with absolute temperature) to Vout/K, a fraction of Vout which is almost temperature independent when compared tiTchanges in ΔVbe. These two voltages are fed into NPN differential pair 5601-5602 (5301-5302 in Figure 53) with the NPNs sized so that Icom will be zero at the peak temperatiire T p where Vout would peak widioutlcom. Figure 55 that shows the peak temperature to be about +27 C (roughly, room temperature). At T p the equal collector currents, I, of NPNs 5601-5602 equal the currents delivered by current sources 5611-5612 (current mirrors 5311-5312 from 5313). Diodes 5621-5622 (5321-5323 in Figure 53) insure that Icom always increases Vout. For temperatures above T p Icom flows through diode 5621 and satisfies: ΔV^-Vout/K = (kT/qJlnCA^com+IJ/g-IcomM+R^com+I -Ra -Icom) where A is ratio of the area of the emitter of NPN 5601 to that of NPN 5602 and R x and R 2 are die resistances of resistors 5631 and 5632, respectively (resistors 5331 and 5332 in Figure 53). For temperatures below T p Icom flows dirough diode 5622 and satisfies the following equation: ΔV^-Vout/K = (kT/αJlntAflcom-I / +IcomJl+R^com-O-Ri +Icom) As previously noted, A is fixed to make Icom zero at T p which translates to ΔV be -Vout K = (kT p /q lnA+R j I-R-l for both equations. This still has R, and R 2 as variables, and these are picked by making die compensation voltage generated by Icom at -55C and + 125C just cancel die deviation of the uncompensated Vout from its peak value; diat is, in Figure 55 the endpoints of the curve are pulled up. Figure 57 shows die compensated Vout. Figure 53 shows Vout/K to be generated by resistor divider 5351-5352, ΔVbe by current mirroring from VgO driving NPN 5360 with emitter resistor 5361 to current source 5314 and resistor 5362, and current mirroring from 5315 to provide die 21 current source 5370 (5670 in Figure 56). Correction circuits 5300 and 5600 supply die compensation current Icom witiiout any switching devices and tiiereby avoid switching noise. Mediod of Fabrication Figures 60-80 illustrate in cross sectional elevation view steps in a first preferred embodiment method of integrated circuit fabrication. The method may be used to fabricate converter 300 and die variations described. The mediod provides botii high performance 5 bipolar transistors and high packing density CMOS transistors. This permits integration of mixed-mode analog-digital circuits without loss of performance over multiple chip implementations. Indeed, analog circuits often require bipolar devices due to their high transconductance, low 1/f noise, and ease of matching Vbe, whereas digital circuits often require CMOS devices due to tiieir high packing density, high noise tiireshold, and low 10 power dissipation. The method provides the following devices: an NPN transistor with a beta of at least 80 and a cutoff frequency f τ of at least 4 GHz and a breakdown voltage of at least 10 volts, an isolated PNP transistor with a beta of at least 60 and an f τ of at least 1.5 GHz, a super beta NPN transistor witii a beta of at least 300, a substrate PNP transistor, 5-volt NMOS and PMOS for digital circuitry, 10-volt NMOS and PMOS for 15 analog circuitry, an isolated poly-to-poly capacitor using poly oxide, and a precision laser- trimmable thin-filniNiCr resistor for optimizing circuit performance after fabrication. The power supplies would be at -5 volts, ground, and +5 volts witii die substrate at about -5 volts. The digital CMOS operates between ground and +5 volts despite die substrate bias. Figures 58a-d show typical plan views of various devices, and Figure 59a-h illustrate the 20 doping profiles of various devices. The effective gate lengths are typically 0.9 μm and die emitter size about 1.4 μm square although other sizes are available with the same process steps. The mediod is modular so tiiat various groups of steps may be omitted if a circuit does not demand all of the foregoing devices; however, die mediod uses only 21 mask 25 levels to fabricate all of these devices. In addition, one further mask level permits inclusion of a low-noise Zener diode. The mediod, including die Zener diode fabrication, includes die following steps: (1) Begin witii a <100> oriented monocrystalline silicon wafer of p-type witii resistivity in the range of 8 to 15 ohm-cm and with oxygen concentration in the range of 30 30 to 36 parts per million. This level of oxygen exceeds die room temperature solid solubility limit, and die heat treatments of steps (2) and (11) initiate deep defects sites and precipitate oxygen in the interior of the silicon wafer. Later processing steps will grow these initial deep defects into major dislocations and will also drive oxygen from die surface leaving a denuded surface zone. The dislocations and precipitated oxygen will getter various impurities such as iron and copper introduced in subsequent processing steps, and die denuded zone provides low defect silicon for device fabrication. These internal defects decrease die lifetimes and diffusion lengtiis of minority carriers deep in the substrate. Note that this enhances the effectiveness of the noise suppressing buried layers 8601, 8602 and 8605 discussed below and illustrated in Figures 86-87. (2) Thermally grows a silicon dioxide ("oxide") layer of tiiickness 5300 A on die surface of the silicon wafer. Steam oxidation (about one hour at 1050 C) provides quicker oxidation than dry oxidation (more than 10 hours at 1100 C). Indeed, growtii in oxygen for two hours at 750 C will stabilize microclusters of oxygen precipitates and a subsequent growtii in steam for one hour at 1050 C will generate interstitial silicon which helps dissolve oxygen near die wafer surface to form a denuded zone for device fabrication. (3) Spin a layer of photoresist onto die oxide coated wafer, and expose and develop a pattern in die photoresist defining all needed N+ buried layers. Botii types of NPN devices (regular and high beta) and botii types of PMOS devices (digital and analog) plus poly-to-poly capacitors and NiCr resistor areas will all be situated over N+ buried layers. (4) Use die patterned photoresist as a mask to wet etch die exposed underlying oxide with buffered HF. (5) Strip the patterned photoresist witii piranha (a sulfuric acid, hydrogen peroxide solution). This leaves the oxide coated silicon wafer with openings in the oxide layer at die locations of eventual buried N+ layers. (6) Implant arsenic ions at an energy of 80 KeV and a dose of 3 x 10 15 ions/cm 2 using the patterned oxide as an implant mask. The projected range for arsenic ions at 80 KeV is about 400-500 A in both silicon and oxide, so die arsenic ions do not penetrate the oxide and only enter die silicon through the openings defining the N+ buried layers. (7) Spin another layer of photoresist onto the oxide coated wafer, and expose and develop a pattern in tiie photoresist defining all needed N- buried layers. Botii digital NMOS and PMOS devices plus isolated PNP devices and Zener diodes will all be located over N- buried layers. This layer of photoresist will cover all of die openings in die underlying oxide dirough which the arsenic was implanted in step (6) except in die locations of digital PMOS devices where die opening in the oxide will again be exposed. Additionally, the oxide in die N- buried layer locations will be exposed. Note tiiat only a single oxide is being used for botii N+ and N- buried layer location definition; this avoids oxide strip and regrowtii steps. (8) Use the patterned photoresist as a mask to wet etch die exposed underlying oxide with buffered HF. Buffered HF etches oxide much faster than silicon, so the exposed silicon in die digital PMOS locations will not be significantly etched. (9) Implant phosphorus ions at an energy of 120 KeV and a dose of 2 x IO 13 ions/cm 2 with the patterned photoresist as die implant mask. The projected range of phosphorus at 120 KeV in photoresist is about 2000 A and in silicon about 1400 A; thus the photoresist can effectively mask the phosphorus even over the locations of oxide openings from step (4). Note mat the phosphorus (peak 1400 A) is much deeper tiian the previously implanted arsenic (peak 500 A) in die locations for digital PMOS devices. (10) Strip the patterned photoresist witii piranha. This leaves the oxide coat witii openings from both steps (4) and (8). (11) Anneal die oxide coated wafer in an oxidizing atmosphere to botii grow 2300 A of oxide on exposed silicon (and further increase the thickness of the existing oxide coat elsewhere) and drive in die implanted arsenic and phosphorus. The oxide grows faster on die exposed silicon, so when die oxide is removed in step (13) a faint pattern of die N+ locations will appear on silicon surface. The phosphorus diffuses faster than the arsenic, and the resulting N+ arsenic doped regions extend down about 3 micrometers (μm) from die wafer surface and the N- phosphorus doped regions extend down about 7 μm. Note that a single drive in diffusion for both die arsenic and die phosphorus saves significant overall processing time in comparison with separate drive ins of die arsenic and phosphorus. The oxide growtii plus drive in may be performed as follows: first, use a nitrogen atmosphere (witii a little oxygen to prevent silicon nitride formation) at 750 C for about three hours to condense oxygen nucleation in bulk so unstable microclusters grow into more stable precipitate centers which later attract more oxygen and lead to large defects. Second, again in a nitrogen atmosphere widi a little oxygen at 1200 C for about three and two thirds hours, drive in the buried layer implants, denude the surface, and grow bulk defects. Lastiy, in a hydrogen peroxide atmosphere at 950 C for one half hour, grow the majority of the oxide. (12) Strip the oxide witii buffered HF. Figure 60 illustrates the resulting regions in wafer 6001 for representative devices as follows: 6010 and 6020 will be N+ buried layers for NPN and high beta NPN devices, respectively, 6030 will be an N- buried layer for an isolated vertical PNP, a substrate PNP does not need die buried layer, 6040 will be an N- buried layer for a Zener diode, a high voltage NMOS device does not need a buried layer, 6050 will be the N+ buried layer for a high voltage PMOS device, 6060 is a buried N- layer for the digital NMOS and PMOS with 6070 the N+ buried layer for the digital PMOS, and 6080 will be an N+ buried layer for a poly-to-poly capacitor and for a NiCr resistor. The buried N- layer 6060 will form a pseudo-substrate for the digital CMOS: wafer 6001 will be biased at -5 volts and die analog devices (bipolar and high voltage CMOS) will operate between power rails at +5 volts and -5 volts, whereas die digital CMOS will operate between the usual 0 and +5 volts. Thus die digital CMOS needs isolation from the portion of wafer 6001 at -5 volts. Buried layer 6060 biased at +5 volts (usual CMOS bias for N substrate) provides this isolation by forming a reversed biased junction with die remainder of wafer 6001. Hence, switching noise electrons generated by die digital CMOS will be contained in N-layer 6060 and away from die analog devices by die 10-volt barrier at die junction with the P-wafer at -5 volts. (13) Spin a 1.5 μm thick layer of photoresist onto bare wafer 6001 , and expose and develop a pattern in die photoresist defining all needed P+ buried layers and also P+ channel stops. The buried P+ locations may be aligned to the pattern of die N+ buried layer locations. Both isolated and substrate PNP devices, Zener diodes, and both high voltage and digital NMOS devices will all be located over P+ buried layers. (14) Implant boron ions at an energy of 120 KeV and does of 1 X IO 14 ions/cm 2 using the patterned photoresist as die implant mask. The boron has a projected range of about 3500 A in silicon and 5000 A in photoresist. Strip tiie photoresist with piranha; Figure 61 shows the resulting cross section with representative device locations. In particular, P+ buried channel stop regions 6110 will eventually be under recessed isolation oxide regions, P+ buried layer 6120 will be die subcollector for die isolated vertical PNP device, P+ buried layer 6130 will be part of the surface collector contact for the substrate PNP device, P+ buried layer 6140 will be part of die anode structure of die Zener diode, and P+ buried layers 6150 and 6160 will underlie die high voltage analog and digital NMOS devices, respectively. Note that P+ buried layers 6120, 6140, and 6160 lie completely witiiin N- buried layers 6030, 6040, and 6060, respectively, which act as pseudo N- substrates. Later oxide isolation makes this structure essentially become an N- substrate on P-wafer 6001 and yields isolated circuits and true complementary devices from a triple buried layer structure. The implanted boron will be driven in to a deptii of about 2.5 μm during the epitaxial deposition of step (15), so there is no separate drive in anneal. (15) Etchback about 2000 A of implanted wafer 6001 in HC1 at 1175 C (2 minutes) in preparation for epitaxial deposition; this etchback must be limited to avoid removing a significant amount of the implanted boron. Epitaxially deposit in situ arsenic-doped silicon layer 6210 of thickness 1.7 μm onto implanted wafer 6001 by tiiermal decomposition (—1060 C) of dichlorsilane plus arsine. The arsenic doping level is set to yield a resistivity of 0.8 ohm-cm (roughly 8 X IO 15 atoms/cm 3 ) for layer 6210. This combination of thickness and resistivity provides die correct performance of die NPN devices in terms of breakdown and Early voltages plus also permits counter doping to provide P wells in the epilayer 6210. The P wells need to be generated witii a very low thermal budget, so epilayer 6210 must be thin. The epitaxial deposition temperature also drives in die boron implanted in step (14). Figure 62 illustrates die epilayer 6210 on wafer 6001. Further, the avoidance of drive ins (low thermal budget) and a shallow emitter permit such a tiiin epilayer due to die lessening of dopants diffusing up from die buried layers (subcollectors) to narrow die active collectors. Indeed, the epilayer thickness and doping relate to Early voltage and emitter-collector breakdown so tiiat the following can be achieved for die NPN devices: The specific details below are for the 10-volt process. Note that the product of beta times early-voltage is at least 5000, and about 6000 is typically achieved. (16) Thermally grow a pad oxide of thickness 625 A on epilayer 6210 in steam at 5 approximately 900 C; this consumes about 300 A of epilayer 6210. This pad oxide will provide stress relief for the silicon nitride ("nitride") oxidation mask during die subsequent recessed local oxidation of the silicon (LOCOS) to create recessed isolation oxide regions. (17) Deposit by LPCVD a 1200 A tiiick layer of nitride on die pad oxide. (18) Spin a 1.5 μm tiiick layer of photoresist onto die nitride/oxide coated wafer 10 6001, and expose and develop a pattern in die photoresist defining all recessed isolation oxide locations. (19) Plasma etch the nitride, pad oxide, plus underlying silicon using die patterned photoresist as tiie etch mask. The nitride and pad oxide are relatively thin, so an isotropic etch would suffice for the initial stages of the plasma etch, and a mixture of SF 6 and 0 2 15 gives a relatively anisotropic etch of the silicon. Etch about half way through epilayer 6210, that is, to a depth of about 0.65-0.7 μm. (20) Strip the photoresist with piranha. This leaves trenches in wafer 6001 with . die patterned nitride and pad oxide coating the tops of die mesas between die trenches. (21) Oxidize die exposed silicon trenches in an oxygen atmosphere at 975 C and 20 a pressure of 25 atmospheres for 25 minutes to grow oxide to a thickness of 1.5 - 1.7 μm. The nitride protects die mesa tops from oxidation, but oxide grows laterally under the edges of tiie nitride to form "bird's head" bulges which will be eliminated in step (22). In die trenches the oxidation consumes the remaining vertical portion of epilayer 6210 and reaches to buried P+ channel stop regions 6110 or tiie N+ buried layers 6120, 6150, and 25 6160 and the P+ buried layers 6010, 6020, 6050, and 6070. Note that the relatively tiiin epilayer 6210 permits die oxidation to consume die epilayer in the trenches witiiout creating excessive bird's head or overrunning a low thermal budget. Also, die tiiin epilayer 6210 permits narrow recessed isolation oxide regions for close packing of devices, especially among die NPN devices which need isolated collectors. The isolation oxide extends above die silicon surface and tills permits later planarization to avoid touching die mesa silicon. This also permits pad oxide overetch in step (31) to remove the "bird's beak" without recessing the isolation oxide top; consequently, the gate widtii of MOS devices increases. Note that the deposited epilayer tiiickness was about 1.7 μm but up diffusion of the buried layers decreases this to about 1.3 μm if the edge of die buried layer is taken to be where tiie dopant concentration exceeds the original epilayer concentration by a factor of 10; that is, about 1 X IO 17 . The isolation, oxide grows down to overlap tiie buried layers and thereby perform its isolation function. (22) Spin on planarizing photoresist to a thickness of 1.5 μm; the photoresist covers the irregular surface created by die oxidation of step (21) but has an essentially planar top surface. Etch back the photoresist plus the bird's head oxide bulges widi a plasma etch of CHF 3 and 0 2 . This removes all of die photoresist and approximately planarizes die surface. (23) Strip the nitride widi hot H 3 P0 4 . Figure 63 shows the resulting structures in wafer 6001 with the recessed isolation oxide regions 6310 and 6320; die pad oxide is too thin to show on the drawings but remains as a deterrent to channeling in the implants of steps (25), (26), (29), (30), and (33). The 6310 isolation regions have underlying P+ channel stop buried regions and separate two N type buried layers. (24) Spin a 1.5 μm thick layer of photoresist onto wafer 6001, and expose and develop a pattern in die photoresist defining die N wells needed for botii analog and digital PMOS devices. (N-well is primarily just epilayer 6210; tiiis step is for surface doping to form die buried channel of proper Y .) (25) Implant threshold adjusting boron ions at 30 KeV and a dose of 2.3 X 10 12 ions/cm 2 using die patterned photoresist from step (24) as die implant mask. This boron dose will set the PMOS device tiireshold voltages to about -1.0 volt. Note tiiat die projected range for 30 KeV boron ions is about 1000 A in silicon. (26) Implant N well phosphorus ions at 160 KeV and a dose of 1.5 X IO 12 ions/cm 2 using the same patterned photoresist as the boron implant of step (25). The projected range of 160 KeV phosphorus is about 2200 A; thus the phosphorus implant lies beneath die boron tiireshold adjustment implant but the phosphorus implant remains close to the surface. Recall that epilayer 6210 had a deposited tiiickness of about 1.7 μm thick and an arsenic concentration of about 8 X 10 15 atoms cm 3 , but over the N+ buried layers die epilayer 6210 deposition itself and other heat treatments caused updiffusion so die effective epilayer thickness is about 1.2 μm. After the boron and phosphorus implants, the net donor concentration at a deptii of about 2000 A is 1.5 X IO 16 atoms/cm 3 and at a depth of about 1000 A the boron has converted the doping to a net acceptor concentration of about at most 1 X IO 16 atoms/cm 3 . The PN junction formed at a depth of about 1500 A has a depletion region extending to the wafer surface, and die PMOS devices will be buried channel type devices. The high voltage PMOS will almost be a surface channel device due to the two gate oxidations, and V^ is fairly high. Indeed, die N wells have an overall retrograde doping (increasing donor concentration widi depth) down to the N+ buried layer peak despite die bump from tiύs phosphorus implant, see Figure 59d. In general, retrograde doping reduces latchup and snapback parasitics by providing high conductivity wells in spite of the low surface doping required for proper MOS tiiresholds. The buried N+ layers below die N wells further reduces latchup and snapback by providing very high conductivity regions. The well anneal of step (35) will spread out die implants, but the digital PMOS devices will remain buried channel devices and die high voltage analog PMOS devices will be almost surface channel devices. (27) Strip die patterned photoresist witii piranha. Figure 64 shows die resulting structure with N wells 6450 for analog PMOS devices and N wells 6470 for digital PMOS devices. (28) Spin a 1.5 μm tiiick layer of photoresist onto wafer 6001, and expose and develop a pattern in die photoresist defining die P wells needed for botii analog and digital NMOS devices, die Zener diodes, and also die collector for die isolated PNP and a portion of the collector contact structure for the substrate PNP. (29) Implant threshold adjusting boron ions at 50 KeV and a dose of 2.8 X IO 12 ions/cm 2 using the patterned photoresist from step (28) as the implant mask. This boron dose will set die NMOS device tiireshold voltages to about +0.65 volt. As noted in steps (25)-(26) die projected range for 30 KeV boron ions is about 1000 A in silicon and die dose suffices to convert the upper 1000 A of epilayer 6210 to P type. (30) Implant P-well, P double-charged boron ions at 125 KV and a dose of 2.7 X 10 12 ions/cm 2 using die same patterned photoresist as die boron tiireshold adjustment implant of step (29). The projected range of 250 KeV double-charged boron is about 6500 A; this dose suffices to convert epilayer 6210 to P type despite die original arsenic concentration of about 8 X IO 15 atoms/cm 3 . During the well anneal of step (35) boron from P+ buried layers 6120, 6130, 6150, 6160 will diffuse slightly upwards and meet die spreading implanted boron to change all of epilayer 6210 to P type widi die net donor concentration averaging about 4 X IO 16 atoms cm 3 and peaking at tiie original implant deptii of about 6500 A. The P wells including P+ buried layers have an effectively retrograde doping, but less drain capacitance tiian implanted-only retrograde well; see Figures 59c and 59e for doping profiles of tiie completed devices. The buried P+ layers below die P wells further reduces latchup and snapback by providing high conductivity regions. Also, the vertical PNP devices will use this P well as its collector, so the higher doping levels will lessen die resistivity between the P+ subcollector 6120 and die collector contact 7526 to be formed later. (31) Strip the patterned photoresist widi piranha. Figure 65 illustrates the P collector 6520 of die isolated PNP, tiie collector contact portion 6530 of substrate PNP, P well 6540 for the Zener diodes, and P wells 6550 and 6560 of analog and digital NMOS devices, respectively. (32) Spin a 1.5 μm thick layer of photoresist onto wafer 6001, and expose and develop a pattern in die photoresist defining the Zener diode location. (33) Implant boron ions at 160 KeV and a dose of 1.2 X IO 14 ions/cm 2 using the patterned photoresist from step (32) as die implant mask. The projected range of 160 KeV boron is about 4500 A. The boron dose suffices to convert the central portion of epilayer 6210 to P type with a doping concentration of roughly 1 X 10 18 atoms/cm 3 . Figure 59h shows die doping profile for die completed Zener diode. (34) Strip the patterned photoresist with piranha; Figure 66 shows the resulting converted portion 6640 of epilayer 6210 for the Zener diode. (35) Anneal wafer 6001 in a nitrogen atmosphere for 30 minutes at 975 C. This activates the implanted dopants and causes some diffusion, especially of the boron. (36) Strip the pad oxide witii an HF etch plus overetch to remove most of die bird's beak from tiie oxidation of step (21). This effectively increases the widtii of the silicon mesas between the isolation oxides. After a cleanup, thermally grow 185 A thick gate oxide on die exposed silicon of wafer 6001 in a dry oxygen atmosphere at 920 C; of course, die isolation oxides 6310 and 6320 also increase slightly in thickness. (37) Deposit 5500 A thick undoped poly silicon on the oxidized wafer 6001 widi LPCVD by silane decomposition. (38) Spin a 1.5 μm tiiick layer of photoresist onto the polysilicon covered wafer and expose and develop a pattern in die photoresist defining die deep N+ contacts to N+ buried layers 6010 and 6020 and N- buried layer 6030. Recessed isolation oxide surrounds these deep N+ contact locations, so die contacts will self-align with large photoresist openings. (39) Plasma etch openings in the layer of undoped polysilicon widi SF 6 and 0 2 using the patterned photoresist as an etch mask. This etch selective etches polysilicon and effectively stops on the 185 A oxide; see Figure 67 showing polysilicon 6710. (40) Strip the patterned photoresist widi piranha. (41) Wet etch (HF) die 185 A oxide exposed by die openings in undoped polysilicon layer 6710 formed in step (39). That is, apertured polysilicon 6710 forms the etch mask, so the exposed portions of recessed isolation oxide will also be etched, but only a few hundred A will be lost. Figure 67 shows die openings 6910, 6920, and 6930 through both polysilicon layer 6710 and die 185 A oxide. (42) Dope apertured polysilicon 6710 and die silicon exposed dirough openings 6910, 6920, and 6930 with phosphorus by decomposing POCl 3 on the surface at 890 C. The resulting resistivity of the doped polysilicon is about 11 ohms/square, and die upper portion of the exposed silicon dopes to N+. The deep N+ contact regions have a carrier concentration of greater than 1 X lO^/cm 3 . This doping of botii the polysilicon layer and the deep N+ contact regions witii die same step eliminates a separate diffusion or implant. (43) Spin a 1.5 μm thick layer of photoresist onto apertured-polysilicon coated wafer 6001, and expose and develop a pattern in die photoresist defining die digital NMOS and PMOS device gates and interconnection lines plus the bottom plates of the poly-to-poly capacitors plus covering the exposed silicon in openings 6910, 6920, and 6930. Because openings 6910, 6920, and 6930 were larger than the portions of wafer 6001 doped, die photoresist can be smaller an the openings and tiiereby not cover any of the adjacent polysilicon. The gates may have nominal lengtiis of 1.4 μm as drawn but effective lengths of 0.9 μm. (44) Plasma etch the polysilicon with SF 6 and 0 2 or HBr and Cl 2 using the patterned photoresist as an etch mask. This etch selective etches polysilicon and effectively stops on oxide, so an overetch to guarantee removal of polysilicon will also not etch significantly down into wafer 6001. (45) Strip the patterned photoresist widi piranha, and strip the exposed gate oxide with HF leaving just gate oxide 6810 under the gates 6860 and 6870 and die lower capacitor plate 6880 formed from polysilicon 6710 in step (44). (46) Thermally oxidize patterned-polysilicon-coated wafer 6001 in an oxygen atmosphere at 920 C to grow a second gate oxide of tiiickness 300 A on the exposed silicon. Note tiiat the exposed surfaces of the patterned doped polysilicon from step (44) oxidize much more rapidly tiian the silicon of wafer 6001 due to the heavy doping of die polysilicon, and an oxide of tiiickness 900 A forms on the polysilicon. Figure 68 illustrates the resulting structure on wafer 6001 including 185 A first gate oxide 6810 under digital NMOS and PMOS gates 6860 and 6870, respectively, 300 A second gate oxide 6820 on the wafer surface, and 900 A oxide 6830 on die surface of polysilicon gates 6860 and 6870 and polysilicon lower plate 6880 of die poly-to-poly capacitor. (47) Deposit a second layer of 5500 A tiiick undoped polysilicon on coated wafer 6001 witii LPCVD using silane decomposition. See Figure 69 showing second polysilicon layer 6950. Note that steps (38) - (41) could have been omitted above and inserted here using polysilicon 6950 in place of polysilicon 6710. (48) Dope second polysilicon layer 6950 widi phosphorus by decomposing POCl 3 at 890 C. The resulting resistivity of the doped polysilicon is about 11 ohms/square. (49) Spin a 1.5 μm thick layer of photoresist onto coated wafer 6001, and expose and develop a pattern in the photoresist defining die analog NMOS and PMOS device gates and interconnection lines plus the top plates of the poly-to-poly capacitors. The gates have nominal lengths of 2.0 μm. (50) Plasma etch the polysilicon widi SF 6 and 0 2 or HBr and Cl 2 using die patterned photoresist as an etch mask. This selectively etches polysilicon and effectively stops on oxide, so an overetch to guarantee removal polysilicon will also not etch significantly down into wafer 6001; however, the 300 A second gate oxide 6820 not 5 protected by die patterned photoresist plus polysilicon will be partially removed, and die 900 A oxide 6830 on first polysilicon will be slightly thinned. (51) Strip the patterned photoresist with piranha. Figure 70 shows tiie resulting analog NMOS and PMOS gates 7050 and 7056, respectively, on 300 A second gate oxide 6820 and poly-to-poly capacitor with top plate 7080 separated from lower plate 6880 by 10 900 A oxide 6830. Figure 70 also shows deep N+ contacts 7010, 7020, and 7030 that were formed in step (42). If steps (38)-(41) had been moved to follow step (47), tiien the doping of step (48) would form deep N+ contacts 7010, 7020, and 7030. (52) Spin a 1.5 μm tiiick layer of photoresist onto coated wafer 6001, and expose and develop a pattern in the photoresist defining die base locations for the isolated PNP 15 devices and also die lightly doped drain extensions of die analog NMOS devices. (53) Implant phosphorus ions at 160 KeV and a dose of 5.0 X 10 13 ions/cm 2 using the patterned photoresist from step (52) as die implant mask. The projected range of 160 KeV phosphorus is about 2200 A. The phosphorus dose suffices to convert the upper portion of P well 6520 to N type with a doping concentration of roughly 2 X 10 18 20 atoms/cm 3 . Recall that P well 6520 has retrograde boron doping, so the remaining P type lower portion of P well 6520, which will form die active collector of the isolated PNP, will have retrograde doping. (54) Strip the patterned photoresist with piranha. (55) Thermally grow a thin (300 A) mesa oxide on die exposed surfaces of wafer 25 6001 plus on the exposed surfaces of patterned second polysilicon; this oxide passivates die sidewalls of gates 7050 and 7056. The oxide growth also enhances the thickness of the other oxides. Figure 71 shows mesa oxide 7190 and sidewall oxide 7170 plus the converted portion 7120 of P well 6520 and die drain extension 7150 in P well 6550. (56) Spin a 1.5 μm thick layer of photoresist onto coated wafer 6001, and expose 30 and develop a pattern in die photoresist defining die N+ source/drains needed for die digital NMOS devices, the sources needed for analog NMOS devices, and die N well contacts in botii analog and digital PMOS devices. (57) Implant phosphorus ions at 100 KeV and a dose of 1.0 X 10 14 ions/cm 2 using the patterned photoresist from step (56) as the implant mask. This phosphorus dose will form a deeper and less heavily doped peripheral portion of the source/drains and provide some doping gradient to lessen the maximum electric fields. Note diat die projected range for 100 KeV phosphorus ions is about 1200 A in silicon and easily penetrates mesa oxide 7190. (58) Implant arsenic ions at 100 KeV and a dose of 5.0 X IO 15 ions/cm 2 using die same patterned photoresist as die phosphorus implant of step (57); this forms the more heavily doped shallower portion of the source drains. The projected range of 100 KeV arsenic is about 500-600 A in silicon and oxide. Thus the arsenic implant lies near the surface, and the net donor concentration near the surface will be about 1.5 X IO 20 atoms/cm 3 and at a depth of about 1000 A the net donor concentration will be about 1.3 X IO 20 atoms/cm 3 at the end of die processing. (59) Strip die patterned photoresist by ashing (oxygen bumoff) and piranha. Figure 72 shows the resulting structure with N+ sources 7250 for analog NMOS devices, N+ well contacts 7256 and 7270 for analog and digital PMOS devices, and N+ source/drains 7260 for digital NMOS devices. (60) Spin a 1.5 μm tiiick layer of photoresist onto coated wafer 6001, and expose and develop a pattern in die photoresist defining die bases for die high beta NPN devices. (61) Implant boron ions at 125 KeV and a dose of 6.0 X 10 12 ions/cm 2 using die patterned photoresist from step (60) as die implant mask. This boron dose will form a deeper portion of the bases. Note that the projected range for 125 KeV boron ions is about 4000 A in silicon and easily penetrates mesa oxide 7190 but does not extend to die bottom of N layer 6210 which will form die active collector of the high beta NPN. (62) Implant boron ions at 30 KeV and a dose of 2.0 X IO 12 ions/cm 2 using the same patterned photoresist as the boron implant of step (61); this forms the shallower portion of the base. The projected range of 30 KeV boron is about 1000 A in silicon and oxide; the resulting doping level in the active base region averages about 1.5 X 10" atoms/cm 3 at a deptii of about 0.4 μm. Thus the base will have a fairly small dose very deep, much deeper tiian the emitter to be formed, so die active electrical charge of the base will be formed predominantiy with the implant dose control of die implanter and avoid heavy compensation by the emitter as witii diffused base devices. This increases die uniformity and decreases the variability of d e high beta NPNs from lot to lot and even within a die; indeed, matches witiiin 1-2% are obtained. The shallow boron implant precludes inversion around the emitter but is totally compensated within the emitter and does not contribute a base electrical charge. This also permits independent tailoring of the radiation hardness of the devices. Figure 59b shows die doping profile. (63) Strip the patterned photoresist widi piranha. (64) Deposit 2200 A thick borosilicate glass ("BSG") with CVD by reaction of silane, nitrous oxide, nitrogen, and diborane to yield a glass witiiout boron in die range of 0.5% to 1.5% by weight. Alternately, undoped CVD oxide could be used. The BSG deposits upon the preexisting oxides and brings die total oxide (silicon dioxide plus BSG) thickness on the mesas to about 2500 A. Figure 73 shows the resulting H base (P type base for high beta NPN) 7320 in N layer 6210 and deposited BSG layer 7310; note diat oxide 7190 does not appear separate from BSG 7310. The oxide thickness must be uniform because the active base for the standard NPN devices is implanted dirough the oxide in step (66) and tiius base implant depth and device characteristics uniformity depend upon oxide tiiickness. The deposition of BSG along widi die underlying thermal oxide has a uniformity of about 0.3% of sigma. (65) Spin a 1.5 μm thick layer of photoresist onto wafer 6001, and expose and develop a pattern in die photoresist defining die bases for die standard NPN devices. (66) Implant boron ions at 130 KeV and a dose of 4.7 X 10 13 ions/cm 2 using the patterned photoresist from step (65) as die implant mask. Note mat the projected range for 130 KeV boron ions is about 4000 A in silicon and oxide, so after penetrating the 2500 A thick oxide 7310 the boron travels about 1500 A into the silicon. Note that the dose exceeds die dose of die high beta NPN, so the standard NPN has a shallower and more conductive base than the high beta NPN. Also, implanting through oxide 7310 insures that crystal damage due to the implant extends to d e silicon surface and tiius later annealing and crystal regrowth proceeds from die bulk rather than from a surface layer. Figure 74 illustrates base 7410. (67) Strip the patterned photoresist with piranha. (68) Anneal wafer 6001 to activate the implants and regrow damaged crystal at 950 C in a nitrogen atmosphere for 60 minutes. (69) Spin a 1.5 μm thick layer of photoresist onto wafer 6001, and expose and develop a pattern in die photoresist defining die locations of P+ source/drains of botii the analog and the digital PMOS devices, P well contacts for botii the analog and digital NMOS devices, base contacts for both standard and high beta NPN devices, collector contacts and emitters for botii isolated and substrate PNP devices, and anode contact for Zener diodes. (70) Implant boron ions at 100 KeV and a dose of 1.2 X IO 15 ions/cm 2 using the patterned photoresist from step (69) as die implant mask. Note mat the projected range for 100 KeV boron ions is about 3000 A in silicon and oxide witii a projected straggle of about 600 A. Thus the peak of the implant lies near the surface of the silicon under tiie 2500 A thick oxide 7310, and high concentrations of boron extend a few hundred A into the silicon. This implant also could be used to form substrate resistors with resistivities of about 100 ohms square. Note that the implant of step (66) which forms the bases for the NPN devices also could be used to form substrate resistors with resistivities of about 1000 ohms/square and die implant of steps (60-62) for bases of high beta NPN devices leads to substrate resistors of about 3000 ohms/square. In contrast, the NiCr resistors made in steps (87-89) and which are laser trimmable form resistors of about 200 ohms square, and resistors made from the doped polysilicon layers have resistivities of about 12 ohms/square. This indicates tiiat the first preferred embodiment mediod has a variety of resistivities for resistor fabrication. (71) Strip die patterned photoresist witii piranha. Figure 75 shows NPN base contact 7510, high beta NPN base contact 7520, isolated PNP emitter 7524 and collector contact 7526, substrate PNP emitter 7530 and collector contact 7532, Zener diode anode contact 7540, analog NMOS weE contact 7550, analog PMOS source/drains 7556, digital NMOS well contact 7560, and digital PMOS source/drains 7570. (72) Deposit 7800 A thick borophosphosilicate glass ("BPSG") by CVD using silane, nitrous oxide, nitrogen, phosphine, and diborane to yield 2-3% boron and 3.5-4.5% phosphorus by weight. The BPSG deposits upon the preexisting oxides and brings die total oxide (silicon dioxide plus BSG plus BPSG) tiiickness on the mesas to about 1 μm, and this oxide is called die Field Oxide. The BPSG over planar areas has a thickness variation of only about 0.3%, so the total oxide also has high tiiickness uniformity. (73) Density the BPSG of step (72) in steam at 800 C for 20 minutes to stabilize die boron and phosphorus dopants. Theoretically, tiiis densification uses the catalytic effect of hydrogen and rapid diffusion of steam to drive die boron and phosphorus dopants to bind to oxygen in tiie silicon dioxide and thus lessens die outdiffusion of dopants during later processing. That is, the boron and phosphorus in the as-deposited BPSG are primarily elemental, and die steam densification oxidizes die boron and phosphorus. Indeed, die diffusion of elemental dopants from BPSG into die NiCr or other thin-film resistors to be formed later disrupts the resistor stability and degrades die capability of targeting the final value of resistivity. Experimentally, steam densified BPSG released less tiian about 2 X IO 19 /cm 3 boron into a NiCr thin film, whereas dry densified BPSG released at least about 1 X IO 20 /cm 3 boron into a NiCr tiiin film. The bonding of die boron and phosphorus to oxygen can be detected, at least in die upper portions of the BPSG layer, by XPS (Xray photospectrometry), FTTR (Fourier transform infrared), or S S (secondary ion mass spectroscopy). The densification should convert most of the boron and phosphorus to oxygen-bonded form. However, steam densification degrades NPN performance, possibly by base grading out to decrease the Early voltage or by dopant segregation at the emitter periphery. Thus densification should be as short as possible and at as low a temperature as possible and still stabilize the dopants. Figure 97 shows a time-temperature trade-off for die steam densification. Of course, the limits could be shifted depending upon die BPSG composition and die resistor and NPN tolerances. Furthermore, steam densification appears to degrade NMOS hot electron performance if the boron percentage in the BPSG is high and die phosphorus percentage low; whereas if the phosphorus percentage is high and the boron percentage is low, then little degradation occurs. Thus confine the boron to the range of 1% to 3% and have the phosphorus percentage at least 1 higher than the boron percentage. For example, 2.25% boron and 4.5% phosphorus yields good overall results. This steam densification also increases die adherence of die TiW metal deposited in step (91) to the BPSG. Adherence problems for dry densified BPSG may also arise from the out diffusion of dopants. (74) Spin a 1.5 μm tiiick layer of photoresist onto coated wafer 6001, and expose and develop a pattern in the photoresist defining die contacts to active regions of all devices and also to any substrate resistors. (75) Plasma etch the oxide widi CHF 3 and 0 2 using the patterned photoresist as an etch mask and with endpoint detection. Note that the oxide has various tiiicknesses, although each of die tiiicknesses is quite uniform: the deposited oxide is 2150 A tiiick, and the BPSG is 7800 A thick. If the thermal oxider is 350 A thick in the emitter area, then the thermal oxide would be 2000 A tiiick over the collector (an additional 1650 A), and die tiiermal oxide would be 1200 A tiiick over the first polysilicon gates (an additional 850 A). This etch selective etches oxide at a rate more an nine times that of silicon, but to clear the oxide over die collector, witii endpoint detection etch stop, leads to die removal of 200-300 A of silicon in die emitter area. This removal is tolerably small because the oxides are uniform and tiius require only a minimal overetch. Note that a buffered HF etch generally has better selectively than plasma etches and does not create the crystal damage due to high energy ion impacts of a plasma, but wet etches generally cannot achieve the small geometries for high digital device packing, especially dirough thick (1 μm) oxides. (76) Strip the patterned photoresist witii piranha; Figure 76 shows the resulting BPSG 7610 plus BSG plus thermal oxide witii smootii topography plus apertures for contacts. (77) Spin a 1.5 μm thick layer of photoresist onto coated wafer 6001, and expose and develop a pattern in die photoresist defining die locations of N+ + which includes die NPN (botii standard and high beta) emitters, tiie tops of deep N+ contacts 7010, 7020, and 7030, die base contact PNPs (botii isolated and substrate), the Zener diode catiiode, and the contact to the drain of the analog NMOS devices. (78) Implant arsenic ions at 80 KeV and a dose of 1.0 X IO 16 ions/cm 2 using the patterned photoresist from step (77) plus die exposed apertured BPSG as die implant mask. Note at the projected range for 80 KeV arsenic ions is about 500 A in silicon. The N+ + emitters formed are called "washed emitters" and are die same size as and self- aligned to die contact apertures in BPSG 7610 created in step (75). N+ + also forms enhanced contact regions to otiier N-type regions like the N base of the PNP transistors. The deep N+ contacts, which cost no diffusion or deposition step, came efficiently at the polysilicon doping step. This N++ arsenic implant damages the surface of wafer 6001 and tiie resultant defects enhance die diffusivity of the phosphorus previously deposited during die polysilicon doping step. Thus shorter and lower temperature anneals of die base and emitter implants may be used and still diffuse die phosphorus down to die N+ buried layers 6010 and 6020 plus N buried layer 6030. The implanted emitter self-aligns to die contacts apertures from step (75) rather tiian being nested in conventional analog fabrication. Thus the washed emitter can be e same size as die minimum contact aperture provided by the lithography used and is much smaller tiian a nested emitter. Figure 77 shows the N++ implanted regions 7710 (NPN emitter), 7715 (NPN collector contact), 7720 (high beta NPN emitter), 7725 (high beta NPN collector contact), 7730 (isolated PNP base contact), 7735 (contact to buried layer 6030), 7737 (base contact for substrate PNP), 7740 (Zener cathode), and 7750 (contact to drain of high voltage NMOS). (79) Strip the patterned photoresist by ashing plus piranha. (80) Deposit 200 A thick cap oxide widi CVD by reaction of silane, nitrous oxide, and nitrogen at 400 C. The oxide deposits upon both the exposed silicon in die apertures formed during step (75) and die preexisting oxides (BPSG 7610 on mesa oxide 7310). The cap oxide provides a barrier against autodoping during the arsenic implant activation anneal to follow in step (81). Without cap oxide, dopants would diffuse out of die BPSG (which is about 2.25% boron oxide and 4.5% phosphorus oxide) and into the exposed silicon. (81) Anneal coated wafer 6001 at 1,000 C in a nitrogen atmosphere for 8 minutes (general 950 - 1050 C for 5 - 30 min). This anneal activates and diffuses the arsenic implants of step (78) to a depth of 0.3 μm plus flows the BPSG 7610 to smooth out the corners of die apertures etched in step (75) and over poly lines. (82) Etch the cap oxide witii buffered HF; this opens the bottoms of the apertures in BPSG 7610 and mesa oxide 7310. Note tiiat the cap oxide (deposition in step (80) and removal in this step) could be omitted if autodoping during die anneal to activate the emitter implants does not push device characteristics out of an acceptable range. (83) Sputter deposit a 220 A tiiick layer of platinum onto coated wafer 6001. (84) Sinter platinum-covered coated wafer 6001 in a nitrogen atmosphere at 450 C for 50 minutes. The platinum which deposited upon the silicon exposed by die apertures of step (75) reacts with the silicon to form platinum silicide (PtSi), whereas die platinum which deposited upon the BPSG does not react because silicon, phosphorus, and boron are all more electropositive than platinum and will not be reduced by die platinum. Note that PtSi forms on both P type and N type silicon and botii single crystal silicon and polysilicon, so all contacts to silicon will have a PtSi interface. PtSi has a high conductivity of 6 - 8 ohms/square for a thin (<500 A) layer, and a low barrier to P-type silicon. (85) Strip the unreacted platinum while leaving the PtSi with a wet etch using aqua regia (HC1 plus HN0 3 ) which dissolves platinum by forming soluble platinum chlorides. (86) Spin a 1.5 μm tiiick layer of photoresist onto coated wafer 6001, and expose and develop a pattern in die photoresist defining die locations for nickel chromium (NiCr) tiiin film resistors on top of BPSG 7610. (87) Wet etch, with buffered HF, the surface of the oxide (BPSG 7610) exposed through the openings in the patterned photoresist to slightly undercut the photoresist. The undercut insures that the subsequent deposited NiCr does not build up at the vertical photoresist edges of the exposed oxide and prevent a clean lift-off. (88) Sputter deposit a 100 A thick layer of NiCr (60% Ni and 40% Cr) onto photoresist covered coated wafer 6001. This NiCr film is so tiiin that it does not cover the sidewalls of the openings in the patterned photoresist but rather just covers horizontal surfaces; namely, the exposed BPSG in the photoresist openings and die top surface of the photoresist. — (89) Lift-off the patterned photoresist by dissolving it in a solution of acetone, methanol, and deionized water. This also lifts off the NiCr that deposited upon die top surface of the photoresist but does not affect die NiCr deposited upon BPSG 7610. (90) Strip any remaining patterned photoresist witii organic solvent such as AZ300T. Figure 78 shows PtSi interfaces 7805-7882 and NiCr resistors 7890. (91) Sputter deposit a 1700 A thick layer of titanium tungsten (TiW which is basically tungsten with about 10% titanium added for adhesion) and tiien sputter deposit a 6,000 A thick layer of copper silicon aluminum (about 1 % copper and 1/2% silicon with the copper added to suppress hillocking and the silicon about the saturation limit). These two layers form the first metal level and may include local interconnections. Adhesion is also promoted by the previous steam densification of BPSG 7610. (92) Spin on photoresist and expose and develop it to define locations over the PtSi interfaces and contacts to die NiCr resistors. (93) Plasma etch the copper silicon aluminum widi Cl 2 plus BC1 3 using die patterned photoresist as die etch mask. This plasma etch permits high packing density because it avoids the undercut and line widtii decrease of wet etches. The plasma etch proceeds very slowly in TiW and die etch is terminated before penetration of the TiW. Thus the TiW effectively protects the underlying tiiin NiCr from plasma etch damage and subsequent change of resistivity. (94) Strip the patterned photoresist witii organic solvent such as AZ300T. (95) Wet etch the exposed TiW with EDTA plus H 2 0 2 which selectively stops etching at NiCr, BPSG, and aluminum. Indeed, die copper silicon aluminum remaining from the plasma etch of step (93) protects the underlying TiW except at die film edges where some undercutting occurs. Because the TiW is only 1700 A thick, the undercut can be held to 2550 A even witii a 50% overetch. Figure 79 illustrates the patterned first level metal contacts 7905-7990. (96) Deposit 2.3 μm thick interlevel oxide 8010 by CVD from reaction of TEOS and oxygen at 390 C to cover the first level metal, NiCr resistors 7890 and BPSG 7610. The interlevel oxide will provide die interlevel dielectric between die first and second metal levels, but die upper surface of the oxide has topography roughly reflecting the bumpiness of the underlying first level metal which has 8000 A high dropoffs. (97) Sinter at 475 C in forming gas (75% N 2 plus 25% H^; this reduces contact resistance of die first level metal to PtSi to silicon. (98) Spin on 1.5 μm tiiick photoresist and expose and develop it to define locations over the first level metal for vias to second level metal. Note tiiat the photoresist has covers the bumpiness of the interlevel dielectric but has an essentially flat top surface except for the patterned vias. (99) Plasma etch tiie interlevel dielectric 8010 witii the via patterned photoresist as die etch mask using CHF 3 plus 0 2 which etches botii the interlevel dielectric and die photoresist. Thus the via pattern persists through the interlevel dielectric and die planar surface of the patterned photoresist propagates to planarize the interlevel dielectric surface; however, the isotropic nature of the etch broadens die vias and slopes tiieir sidewalls. The etch stops in die vias when it reaches first level metal except for die lateral etching; tiius the deptiis of the vias can vary to accommodate variation in the thickness of the interlevel dielectric. The etch is timed and stopped to insure a minimum tiiickness of at least 0.5 μm of interlevel dielectric at its tiiinnest portion, which occurs over the poly-to-poly capacitors due to tiie stacked polysilicon layers. (100) Strip any remaining patterned photoresist with organic solvent. (101) Sputter deposit a 1.6 μm thick layer 8020 of silicon aluminum (1% silicon) on the planarized interlevel dielectric 8010 for second level metal. The second level metal covers tiie sloped sidewalls of die vias in die interlevel dielectric to connect to die first level metal exposed at die bottoms of the vias. Bond pads are formed in second level metal. (102) Spin on photoresist and expose and develop it to define die second level metal interconnections. (103) Plasma etch the silicon aluminum 8020 witii Cl 2 plus BC1 3 and CHF 3 using the patterned photoresist as die etch mask. (104) Strip the patterned photoresist widi a plasma of oxygen plus a follow up wet strip with organic solvent as a clean up. _ (105) Deposit 0.8 μm thick oxide 8030 by reacting TEOS plus oxygen with the middle 0.6 μm doped with phosphorus. Then deposit 0.4 μm tiiick silicon nitride 8040. The oxide and nitride will form the passivation layer, which has a total thickness, including die interlevel oxide from step (96), of about 2.2 μm over NiCr resistors 7890. A plasma reaction of silane with ammonia and nitrogen using dual RF (13 MHz and 600 KHz) deposits nitride witii a low hydrogen and low Si-H bond content to improve subsequent laser trimming results. Typical nitride films have 30% (atomic percent measured) total hydrogen and 20% Si-H bonded hydrogen, whereas nitride 8040 has only 20% total hydrogen and 12% Si-H bonded hydrogen. Hydrogen not Si-H bonded is usually N-H bonded and stable, so die reduction of Si-H bonded hydrogen by about a factor of two provides laser trimming benefits noted in die following. See Figure 80 showing interlevel oxide 8010, second level metal 8020, passivation oxide 8030, and passivation nitride 8040. (106) Sinter at 475 C in a nitrogen atmosphere to reduce the via resistance. (107) Spin on photoresist and expose and develop it to define openings to die bond pads. (108) Plasma etch nitride 8040 with CF 4 and wet etch oxide 8030 with buffered HF down to the bond pads. (109) Strip die patterned photoresist with organic solvent. This completes die semiconductor processing of wafer 6001. To finish me fabrication: probe die on tiie wafer; laser trim precision analog circuits including laser trim the NiCr resistors by focussing a laser beam through interlevel oxide 8010, passivation oxide 8030, and nitride 8040 to vaporize portions of the NiCr film; saw wafer 6001 into dice; mount die individual dice on lead frames; connect bond wires to die bond pads; electrically test the mounted and bonded dice; and lasdy package die trimmed dice. The laser trimming of NiCr tiiin film resistors typically has a pulsed laser spot scan the thin film and melt/disperse away portions of it into the oxide. This increases the resistance by removing metal. However, the kerf area at die edges of the cut portions is a complex scalloped structure of partially removed metal, and this kerf area can apparently change conductivity over time. Indeed, resistors which have been laser trimmed typically show much greater resistance drift over time than untrimmed resistors. Experimentally, laser trimmed NiCr resistors with oxide plus nitride passivation show very good stability when tiie nitride has a low Si-H content (12%) and low stress (2 X 10 8 dynes/cm 2 compressive) as in step (105) but poor stability when the nitride has die typical high Si-H content (20%) and high stress (2 X IO 9 dynes/cm 2 ). There are tiiree possible explanations for the dependence of resistance drift on tiie nitride characteristics: (1) Si-H bonds are weak and nitride with high Si-H content may release free hydrogen. Such free hydrogen may assist the regrowth or annealing of kerf areas over the operating life of the resistor and thereby lower resistance over time. Note that hydrogen has been found responsible for changing the resistance of single crystal and polysilicon diffused resistors, and hydrogen in die form of steam has been shown to be more effective than oxygen treatment in annealing oxides. (2) The compressive stress of the nitride may mechanically move die NiCr over time and tiiereby change its resistance. And die movement in the kerf area will dominate the resistance change. (3) Si-H bonds scatter the laser light and spread out die spot during trimming. This leads to a broader kerf area and consequent greater kerf changes. 200 C accelerated life testing with the preferred embodiment trimmed NiCr resistors gave a resistance drift of only 0±0.2%. Electrostatic discharge (ESD) protection for integrated circuits fabricated witii the first preferred embodiment method appears in Figures 82-85. Generally, MOS IC products are prone to ESD damage if tiieir input and output pins are left unprotected. It is, tiierefore, a common practice to place ESD protection devices between the input or output pins and tiie supply voltage rails. MOS diodes as die ESD protection devices are used in typical CMOS digital integrated circuits where die output signal swings between Vce (+5.0V) and Gnd (0V). Usually, die silicon substrate is tied to Gnd, which makes the substrate the natural return point for both the output signal and the ESD current. Li mixed mode analog-digital system applications, it is very common to have blocks of circuits operating from several different voltage supply rails. For example, a digital circuit based on positive logic levels would operate in between Vce (+5V) and Gnd (0V), while another digital circuit based on unusual negative logic levels operates between Gnd and Vee (-5V). And yet another analog circuit may operate between Vce and Vee. It is rather common for a BiCMOS integrated circuit to have analog circuits at one end that operate between die full supply rails (Vce and Vee) and digital circuits at another end operating between full supply rails, or the positive supply rails (Vce and Gnd) for positive logic compatibility. In this latter case, all digital signals would return to the Gnd supply, and tiierefore the ESD protection for the signal pins would be implemented conventionally as shown in Figure 81. It may not be necessary in many cases to place any ESD protection devices between die signal terminal and the Vee supply rail because it is not relevant to the operation of the circuit under consideration, especially when gate oxides are relatively thick (greater tiian 250 A). Notice, however, that the return path for the ESD current is not necessarily the Gnd supply line in this case, because the silicon substrate is now tied to the Vee rail, not the Gnd line, as in MOS. Therefore, the conventional ESD protection scheme illustrated in Figure 81 may be vulnerable to the ESD events when the discharge current path finds its way to die silicon substrate, especially for thin gate oxide devices. In high-performance, high-speed, mixed-mode BiCMOS products, the digital circuits would require a thin gate CMOS part, which would exacerbate the aforementioned ESD vulnerability. The preferred embodiment provides an additional current path between the circuit terminal and die silicon substrate, even though the actual signal swings only between the positive supply rails under normal operating conditions. Since many ESD events occur during integrated circuit handling by human beings, it is likely that the ESD pulses discharge to the silicon substrate rather than to the ground pins, which would result in ruptured CMOS gates in the BiCMOS digital circuitry. The ESD protection circuit can be implemented by placing conventional ESD devices, such as a bipolar transistor operating in BVceo mode, between die circuit terminal and the Vee line. Two arrangements are shown in Figures 82-83. The first one shown in Figure 82 has the ESD protection devices connected directly between the digital signal terminal (output in die figures) and the Vee rail in addition to the conventional ESD protection scheme as shown in Figure 81 in order to provide a direct ESD current path to protect the BiCMOS digital circuit. The second one in Figure 83 has an ESD device connected between Gnd and Vee in addition to the conventional ESD circuit shown in Figure 81. In this circuit, the ESD current would flow dirough the ESD Device 2 and the ESD Device 3 in order to provide yet anodier circuit path to die ESD pulse current. The actual ESD devices could be any nonlinear devices which present very high impedance to die circuit under normal circuit operation but turn on into a very low impedance mode when die signal terminal reaches a certain tiireshold above the normal operating voltage. The ESD capture threshold of die ESD device should be set in such a way that it is higher than the normal supply rail voltages but sufficiently lower than the gate rupture voltage of the CMOS devices in die BiCMOS digital circuit. Figure 84 shows an example of die first arrangement: a combination of the bipolar transistor operating in BVceo mode witii a bipolar transistor diode witii the base shorted to the collector in order to meet die ESD capture threshold requirements stated above. Figure 85 shows an example of the second arrangement. Here a bipolar transistor operating in BVebs mode is used to meet die ESD tiireshold requirements. Noise suppression for integrated circuits fabricated witii the first preferred embodiment mediod may be enhanced witii the isolation between digital and analog regions as shown in Figures 86-87. In effect two parallel buried P+ layers 8601-8602, each about 20 μm wide, and intervening 10 μm buried N+ layer 8605 at a distance of 6 μm from each P+ buried layer form a moat between digital and analog regions. P+ 8601-8602 biased to -5 volts and N+ 8605 biased +5 volts sets up a (weak) electric field in die underlying nondepleted substrate 6001 that intercepts drifting minority electrons injected by tiie digital devices. Botii P+ 8601 and P+ 8602 are needed to create the (symmetrical) field which penetrates somewhat down into substrate 6001. Opposite polarities would also work. Converter 300 may be fabricated widi die first preferred embodiment BICMOS mediod to fit on a die of size 7.11 mm by 5.96 mm. See Figure 44 for a plan view. Further Modifications and Variations The preferred embodiments, both devices and methods, may be modified in many ways. For example, die use of tiie same flash converter for both conversions could be replaced by die use of two separate flash converters and a consequent pipelining effect. Figure 88 shows converter 8800 having two sample and hold blocks 8801-8802 widi sample and hold 8802 essentially providing extended holding of die V^, acquired by sample and hold 8801 while 8801 acquires the next sample. More explicitly, Figure 89 is a simplified timing diagram illustrating the operation of converter 8800 as follows. Sample and hold 8801 follows (acquires) V k (t) and at time 0 switches to hold V^ and flash converter 8811 has been following the output of sample and hold in the same manner as flash converter 306 follows sample and hold 304. But in converter 8800 sample and hold 8802 now also acquires the fixed V b being held by sample and hold 8801. Thus, when error amplifier 8822 needs the V k to compare to the reconstruction by DAC 8820, sample and hold 8802 will supply it and sample and hold 8801 can be acquiring the next sample. After 30 nsec of settling, flash converter 8811 latches and after 28 nsec supplies the 7 bits to MSB Latch 8830 and tiien to DAC 8820 in the same manner as in manner as with converter 300. Sample and hold 8802 now is holding V k and sample and hold 8801 is released for the next sample. Error amplifier 8822 operates in the manner of error amplifier 312 and flash converter 8812 is following the output of error amplifier 8822. Error correction 8834 is analogous to error correction block 318. As soon as the 7 bits from MSB Latch 8830 are put into block 8834, sample and hold 8801 switches again to hold, and flash converter 8811 processes the next sample and loads MSB Latch 8830. Thus the overall conversion rate increases by the diminished acquire time required by die input sample and hold but at the cost of requiring two matched flash converters and a second sample and hold (which only has to acquire dc signals). Figure 90 illustrates another approach with two sample and hold blocks being used to diminish die acquire time: sample and hold blocks 9001 and 9002 are ping-ponged to alternately play die role of sample and hold 304. The advantage is as witii converter 8800: while one sample and hold is holding V^ for tiie error amplifier the other sample and hold is already acquiring the next sample. Sample and hold blocks 9001-9002 plus controlling ping-pong signal could be used directly in place of sample and hold 304 in converter 300. Figure 91 shows a timing diagram for the ping-pong operation. The timing controller 4500 could be composed of oscillator cells 4600 connected in parallel witii differing time delays and witii logical combinations of the outputs to create the desired timing pulses. For example, Figure 92 shows timing generator 9200 made of four parallel cells 4600 with increasing time delays as shown in die top panels of timing diagram Figure 93. The logic gates convert tiie cell outputs to the outputs shown the bottom panels of Figure 93. Because all of the cells start charging their timing capacitors when CNTRL goes low, smaller currents for the longer time delays can be used, giving lower power consumption. Also, the capacitors could all be the same size and differing 5 charging currents could be obtained by differing mirror device sizes. Power up reset circuit 5000 could have the NPN 5050 plus NPN diode chain 5051 replaced widi NMOS versions or even a single NMOS biased at about -2 volts by a resistive divider from ground to Vee. Alternatively, circuit 5000 could have all of die MOS devices, including the inverters and gate, replaced witii digital bipolar devices. 10 The voltage reference 326 could be a bandgap generator with a curvature correction circuit as shown in simplified version in Figure 94. Indeed, reference circuit 9400 has the standard bandgap reference opamp 9402 and NPNs 9411 and 9431 of different sizes; output resistors 9451-9453 again boost output and provide for die curvature correction current to generate a temperature dependent voltage increase as witii reference 326. The 15 correction circuit in 9400 uses two PMOS differential pairs 9482-9483 and 9492-9493 in place of die single NPN differential pair 5601-5602 of Figure 56. An approximately temperature independent bias (Vout K) drives one PMOS of each pair and a temperature varying bias (the collector of NPN 9431) drives die otiier PMOS of each pair. Each pair has a current mirror load but with oppositely driven outputs; that is, the output of the 20 9482-9483 pair taps the drain of the temperature-independentiy driven PMOS 9482 and the output of the 9492-9493 pair taps the drain of die temperature-dependently driven PMOS 9493. As witii the correction circuit of Figure 56, diode connections to the outputs provide die compensation current Icom so no switches need be tiirown to provide positive Icom for temperatures both above and below T p . 5 Error amplifier 312 can be generally used as a two channel amplifier with different input characteristics: one channel a high input impedance MOS and die other channel a high gain NPN. Switching between channels follows from the control of the bias currents. More generally, multiple channels could be used widi a selection of bias currents as to the characteristics desired: two or more channels could have MOS or otiier type FET, e.g., 0 JFET, inputs with different device sizes for different gains or even differing numbers of internal gain stages, two of more channels could have bipolar inputs (NPN or PNP), and differing gains could be used for switching between large and small input signals. As with sample and hold 304, PNP devices could be used in addition to the NPN and CMOS devices actually appearing in the schematic diagrams. For example, in die output buffer 320 the drivers of Figures 41 and 43 could have NPNs 4102 and 4302 replaced by PNPs to give a complementary output. Circuits using structures such as NPN diodes could also be made witii MOS diodes, diodes witii resistors, or devices controlled by a fixed bias (or a fraction of a supply rail voltage in the case of start up circuits). Various processes such as metal, polysilicon or polycide gate, triple level metal, silicon-on-insulator, and so forth could be used. P-type regions and devices can be interchanged with N-types. Indeed, Figure 95 shows a cross sectional elevation view of devices made according to die preferred embodiment mediod of fabrication modified for buried oxide substrate 9501. Substrate 9501 contains buried oxide layer 9503, which can be either implanted or created by bonding wafers or by otiier dielectric isolation techniques; the substrate below oxide 9503 need not be monocrystalline and may even be insulator as in substrate 9501 being silicon-on-sapphire. Deep trenches 9505 penetrate to buried oxide 9503 to isolate subcircuits, not every device, and extends die idea of pseudosubstrate 6060 for digital CMOS. This effectively isolates the digital noise from the analog circuits. A modified fabrication method would proceed as follows: start with a substrate having 2-5 μm of silicon over an oxide layer; then implant buried layers and grow an epitaxial layer as in die first prefeπed embodiment. Etch deep trenches and refill diem (witii dielectric, oxide/polysilicon, etc.) and planarize. Then continue as with the first preferred embodiment. For greater density seal die shallow trench sidewalls (ROI in first preferred embodiment) for prevention of lateral encroachment during die isolation oxidation (e.g., SWAMI type process or polybuffered LOCOS). Other variations of the first preferred embodiment fabrication method include separate digital and analog power supplies and grounds for different voltage ranges for tiie digital and analog witii corresponding different gate oxide tiiicknesses, drain doping levels, epilayer tiiicknesses, and so forth. Figure 96 illustrates the general split between digital and analog circuits where the digital circuits are isolated by die pseudosubstrate and die analog voltage V need not equal die +5 volts digital power supply. Indeed, die effective separation of good digital and good analog devices permits integration of low noise analog front ends witii a significant amount of digital logic to create monolitiiic items. Examples of such integration include a complete radio witii an RF front end plus an audio back end, and a video processor witii a front end correlator followed by analog signal processing (filter, modulator, demodulator, limiter) to provide botii an analog signal with the base band stripped out and a detection of the carrier which is followed by analog-to-digital conversion of die analog signal plus digital signal processing witii the carrier detection providing die timing. Li fact, the ultrasound example of Figure 1 could have a DSP, a digital-to-analog converter, and die ultrasound head integrated on a single chip so tiiat the transmitted waves could be digitally controlled but drive a high voltage transducer. Variations in the first preferred embodiment to enhance die PNP performance include: replacing steps (69)-(70) which implant boron at 100 KeV dirough 2500 A thick oxide for PMOS source/drains and PNP emitters with steps immediately following step (62) that will implant boron at 30 KeV through just the mesa oxide and will yield better PNP emitters but shorten the effective channel lengths of the PMOS. Further, less variability in PNP base parameters can be had by an implant separate from die drain extension implant of steps (52)-(53). This separate PNP base implant would follow step (54) and include phosphorus at 180 KeV witii a dose of 1 X 10 14 ions/cm 2 . The resultant isolated PNP should have a beta of 60, an Early voltage of 15 volts, f τ of 1.3 GHz, and breakdown BV^ of at least 10 volts. Additional enhancement to die Early voltage of die isolated PNP can come from variations that reduce diffusions, such as dropping step (35) and using quicker gate oxidations. Another variation providing a PNP which more accurately complements the NPN uses a washed emitter. Li particular, P+ emitter implants 7524 and 7530 from step (70) are replaced by a separate implant using the apertured BPSG for alignment as witii the NPN emitter implant. The PNP emitter implant follows the NPN emitter implant and cap oxide deposition. The use of washed-emitters for the PNP permits the same higher density as with die NPNs and also probably increases tiie Early voltage of the PNPs up to 20 volts. The use of the second polysilicon layer 6950 in place of the first polysilicon layer 6710 for the simultaneous doping of polysilicon and substrate has an advantage diat less tiiermal oxide is grown on the locations of the substrate doping because the second gate oxide would be grown prior to second polysilicon layer 6950 deposition. This makes the apertures through the oxide easier to etch. That is, steps (38)-(41) could be moved to follow step (47) with the change that the 185 A first gate oxide would now be 300 A second gate oxide. The advantage of using first polysilicon layer for the simultaneous doping is the further heat treatment to diffuse in the phosphorus. The use of thinner polysilicon for die CMOS gates would permit die use of thinner BPSG. In this case the ratio of the NPN emitter deptii to die total oxide thickness etched to form die emitter apertures could be as low as about 1 to 2. As with the error amplifier, the voltage follower could be used in a general setting witii differential inputs and differential outputs. In particular, follower B in Figure 36 could have an output and current source matching that of follower A. The load NPNs could be eliminated.

Claims: CLAMS What is claimed is: 1. An integrated timing circuit, comprising: (a) an input terminal; (b) a plurality of timing cells, each of said cells including, (i) an input node and first and second output nodes; (ii) a capacitor; (iii) a voltage level detector widi input connected to said capacitor and output coupled to botii said first and second output nodes widi a detection output at said first output node preceding a detection output at said second output node; (iv) a current source and a switch selectably connecting said current source to said capacitor, said switch controlled by a signal at said input node; and (v) a timing output node coupled to said input node and said first output node; (c) said cells connected in series with the input node of tiie first cell connected to said input terminal and the input node of each other cell connected to die second output node of the preceding cell, _ (d) whereby a signal at said input terminal leads to a sequence of nonoverlapping signals at said timing output nodes witii the duration of said signals determined by tiie capacitance of said capacitor, the magnitude of said current source, and the voltage level at which said detector indicates detection. 2. A power supply level detector, comprising: (a) a positive node; (b) a negative node; (c) a ground node; (d) a first voltage divider connected between said positive node and said ground node; (e) a second voltage divider connected between said positive node and said ground node, die output of said second divider greater than the output of said first divider when the potential difference between said positive node and said ground node is less tiian VI but greater tiian VO, and die output of said second divider less tiian the output of said first divider when die potential difference between said positive node and said ground node is greater tiian V2 with V2 greater than VI; (f) a current source connected to said negative node and active when the potential difference between said ground node and said negative node exceeds V3; (g) a differential pair powered by said current source and driven by die outputs of said first and second dividers, die outputs of said pair are (1) botii greater than a threshold voltage V4 when said current source is inactive, (2) both less than V4 when said current source is active and die potential difference between said positive node and said ground node is between VI and V2, and (3) split by V4 when said cuπent source is active and die potential difference between said positive node and said ground node is either between VO and VI or greater than V2; and (h) logic circuitry to detect when said differential pair outputs are split by V4. 3. A current mirror, comprising: (a) a first cuπent minor with a first reference cuπent node and a first miπored cuπent node, said first cuπent mirror witii bipolar transistor(s) coupling said first miπored cuπent node to ac ground; and (b) a second current minor with a second reference cuπent node connected to said first miπored cuπent node and at least one second mirrored cuπent node, said second reference current node coupling to a field effect transistor. 4. A driver, comprising: (a) an input node; (b) an output node; (c) a bipolar transistor coupled between said output node and a first reference node, said bipolar transistor with its base coupled to said input node; (d) base drive circuitry connected to die base of said bipolar transistor, when active said base drive circuitry supplies current to said base to drive said bipolar transistor into saturation. 5. A differential voltage follower, comprising: (a) first and second input nodes; (b) first and second output nodes; (c) a first follower with input connected to said first input node and witii output connected to said first output node and to a first current source; (d) a second follower witii input connected to said second input node and widi output connected to said second output node and to a second cuπent source; (e) wherein said first follower includes a first cuπent mirror and said second follower includes a second current mirror, said first and second current mirrors cross- coupled to tie die currents dirough said followers. 6. A reference voltage circuit, comprising: (a) a bandgap generator including: (i) first and second bipolar transistors of differing emitter areas and with their bases tied together; and (ii) a differential amplifier witii inputs sensing the collector currents of said first and second bipolars, and with output driving die bases of said bipolars, said bandgap generator providing an uncompensated output with a maximum when the temperature of operation equals Tp; (b) a correction circuit connected to said bandgap generator to provide a compensation current of a single polarity and dependent upon the difference between the temperature of operation and Tp and including: (i) first and second current devices; (ii) first and second current sources, said first device connected to said first source at a first node and said second device connected to said second source at a second node, said devices and sources characterized by (A) die difference between die current supplied by said first source and die current capacity of said first device decreases witii temperature but is zero at Tp and (B) die difference between the current supplied by said second source and the current capacity of said second device increases witii temperature but is zero at Tp; (iii) first and second diodes connecting said bandgap generator to said first and second nodes, respectively; (c) whereby at temperatures above Tp said correction circuit draws compensation cuπent from the bandgap generator dirough said first diode, and at temperatures below Tp said coπection circuit draws cuπent through said second diode. 7. An integrated circuit two-channel amplifier, comprising: (a) a first amplifier with a first gain and a first input impedance; (b) a second amplifier widi a second gain and a second input impedance; and (c) a switch to select one of said first and second amplifiers. 8. An integrated circuit two-channel amplifier, comprising: (a) a first amplifier with a bipolar transistor input; (b) a second amplifier with a field effect transistor input; (c) an input node connected to both an input of said first amplifier and an input of said second amplifier; (d) an output stage connected to die outputs of both said first and second amplifiers; and (e) a switch when in a first state decreases die gain of said first amplifier and when in a second state decreases die gain of said second amplifier. 9. An integrated circuit amplifier, comprising: (a) a differential pair input; (b) a cuπent source driving said differential pair; (c) a protection switch which when in a first state sources cuπent to said cuπent source to lessen the drive current for said differential pair and when in a second state does not source current to said current source; (d) whereby the gain of said differential pair depends upon die state of said switch. 10. A mediod of error correction in a two-step analog-to-digital converter, comprising tiie steps of: (a) converting an input analog signal to an N-bit digital word; (b) reconstructing a second analog signal from said N-bit word; (c) converting an amplified difference between said input analog signal and said second analog signal to an M-bit word where the amplification is by a factor of 2 K ; (d) adding to said N-bit word die two's complement of die N— K most significant bits of die M-bit word which would result from a conversion of 0 in step (c) and tiiereby form a second N-bit word plus a first carry bit; (e) adding to said second N-bit word die N-K most significant bits of said M-bit word to form a third N-bit word plus a second carry bit; and (f) forming an output digital word with its N most significant bits equal to said third N-bit word and its M— (N— K) least significant bits equal to the M— (N— K) least significant bits of said M-bit word. 11. An integrated circuit two-step analog-to-digital converter, comprising: (a) an analog-to-digital converter (ADC); (b) a digital-to-analog converter (DAC); (c) an error amplifier with input coupled to die output of said DAC; (d) a controller, said controller holding said error amplifier inactive for a first time interval following a switching of the input of said DAC from a fixed input to the output of said ADC. 12. An integrated circuit, comprising: (a) a plurality of analog NPN devices; (b) a plurality of analog CMOS devices; and (c) a plurality of digital CMOS devices; (d) wherein said analog NPN and analog CMOS devices are coupled between VI and V2 power voltages, and said digital CMOS devices are coupled between V3 and V4 power voltages, where die magnitude of VI — V2 is greater tiian the magnitude of V3 — V4. 13. A mediod of fabrication of integrated circuits, comprising die steps of: (a) depositing a layer .of polysilicon over a substrate; (b) forming openings in said layer to expose portions of said substrate; (c) doping said layer and said exposed portions of said substrate simultaneously; (d) then patterning said layer of polysilicon. 14. An integrated circuit, comprising: (a) a reference voltage node; (b) a positive voltage node; (c) a negative voltage node; (d) a signal node; (e) a plurality of devices coupled among said nodes; and (f) a plurality of electrostatic discharge protection devices, a first protection device connected between said signal node and said positive voltage node, a second protection device connected between said signal node and said negative voltage node, and a third protection device connected between said signal node and said reference voltage node. 15. An integrated circuit with subcircuit isolation, comprising: (a) a semiconductor substrate of a first conductivity type; (b) a subcircuit region in said substrate and of a second conductivity type opposite said first type; (c) a plurality of devices formed over said region and which are coupled between power voltages VI and V2; (d) a plurality of devices formed over said substrate and away from said region and which are coupled between power voltages VI and V3 where the magnitude of V1-V3 is greater tiian the magmtude of V1-V2. 16. An integrated circuit, comprising: (a) a semiconductor substrate of a first conductivity type; (b) a first plurality of devices formed in said substrate; (c) a second plurality of devices formed in said substrate; and (d) an isolation structure in said substrate and located between said first and second pluralities and including: (i) a bias region of a second conductivity type opposite said first conductivity type; and (ii) first and second contact regions of first conductivity type, said first and second contact regions adjacent said bias region and with said bias region separating said first and second contact regions; (e) whereby when said bias region is reversed biased widi respect to said substrate and said contact regions, said isolation structure collects minority carriers. 17. An integrated circuit, comprising: (a) a silicon semiconductor substrate including an epilayer and witii buried layers beneath said epilayer; (b) a plurality of silicon dioxide regions extending through said epilayer and abutting said buried layers; and (c) a vertical analog bipolar transistor, the emitter, base, and active collector of said bipolar transistor formed in said epilayer over one of said buried layers, said 5 transistor characterized by an Early voltage of at least 30 volts. 18. An integrated circuit, comprising: (a) a laser-trimmed resistor; and (b) a silicon nitride layer over said resistor, said layer characterized by a silicon- bonded hydrogen content of about or less than 12% atomic. 10 19. An integrated circuit, comprising: (a) a layer of borophosphosiliciate glass (BPSG) over a substrate, said BPSG characterized by densification in steam; and (b) a tiiin film resistor on said layer. 20. A method of fabrication of an integrated circuit, comprising die steps of: 15 (a) forming an opening in a first layer of doped silicon dioxide on a substrate; (b) depositing a barrier layer on said exposed substrate and first layer; and (c) heating said substrate to flow said first layer; (d) wherein said barrier layer is characterized by a tiiickness that (i) allows said first layer to flow at least half as much as it would have flowed without said barrier layer 20 and (ii) stops at least half of die dopants diat would have diffused out of said first layer and into said previously exposed substrate. 21. A method of forming resistors in an integrated circuit, comprising the steps of: (a) depositing a tiiin film resistor on a dielectric; (b) depositing a conductive buffer layer on said thin film; 25 (c) depositing an interconnect conductor layer on said buffer layer; (d) etching said interconnect layer with said buffer layer as an etch stop and with an etch not selective with respect to said thin film; (e) etching said buffer layer widi an etch which is selective with respect to said thin film. 30 22. An integrated circuit, comprising: (a) a semiconductor substrate; (b) a dielectric layer of tiiickness D over a region of said substrate; (c) a bipolar transistor formed in said region witii an emitter self-aligned to an aperture in said layer and said emitter extending a distance less tiian D/2 from a surface into said substrate. 23. An integrated circuit, comprising: (a) a semiconductor substrate; (b) a dielectric layer over said substrate; (c) a bipolar transistor formed in said substrate witii die emitter of said bipolar self- aligned widi an aperture in said layer; (d) a NMOS transistor formed witii a source drain region in said substrate and wid a contact region in said source/drain region aligned with an aperture in said layer; (e) wherein said contact region and said emitter have approximately the same depths. 24. A method of fabrication of an integrated circuit, comprising the steps of: (a) forming an aperture in a layer of flowable dielectric over a base region in a semiconductor substrate; (b) introducing dopants through said aperture to form an emitter region within said base region; and (c) heating said substrate to simultaneously anneal said emitter region and flow said dielectric. 25. A method of fabricating an integrated circuit, comprising the steps of: (a) patterning photoresist directly on tiie surface of a semiconductor substrate; (b) implanting buried layer dopants into said substrate using said patterned photoresist as implant mask; (c) growing an epitaxial layer on said implanted substrate prior to any anneal of said implanted substrate; and (d) forming a transistor at the surface of said epitaxial layer and over said buried layer dopants. 26. An integrated circuit, comprising: (a) a layer of borophosphosilicate glass (BPSG) overlying a substrate; and (b) a tiiin film resistor on said layer, said resistor widi a boron concentration of less than 4 x IO 19 atoms cm 3 . 27. An integrated circuit, comprising: (a) a P type substrate; 5 (b) a plurality of vertical analog NPN transistors; (c) a plurality of digital CMOS transistors; and (d) a vertical analog PNP transistor with active collector over a P buried layer which is witiiin an N buried layer in said substrate, where the peak doping concentration in said P buried layer is greater tiian the peak doping concentration in said N buried layer. 10 28. A mediod of fabrication of an integrated circuit, comprising die steps of: (a) implanting a buried layer in a silicon substrate; (b) growing an epilayer on said substrate, said epilayer less tiian about 2 μm thick; (c) locally growing silicon dioxide dirough said epitaxial layer to said buried layer; (d) forming base and emitter regions in said epitaxial layer and over said buried 5 layer; (e) forming a bipolar transistor with said emitter region as emitter, said base region as base, said epitaxial layer as active collector, and said buried layer as ohmic collector where said bipolar transistor has a breakdown voltage BV e∞ of at least 10 volts and an Early voltage of at least 30 volts.

Inventors: BACRANIA KANTILAL, CHI CONG IN, CHURCH MICHAEL DAVID, COTREAU GERALD M, DEJONG GLENN ALAN, FISHER GREGORY JAMES, GASNER JOHN THOMAS, ITO AKIRA, JOHNSTON JEFFREY MICHAEL, KING KEN RICHARD, KUTCHMARICK DAVID, RHEE CHOONG-SUN, RIEMER DAVID WAYNE, BACRANIA, KANTILAL, CHI, CONG, IN, CHURCH, MICHAEL, DAVID, COTREAU, GERALD, M., DEJONG, GLENN, ALAN, FISHER, GREGORY, JAMES, GASNER, JOHN, THOMAS, ITO, AKIRA, JOHNSTON, JEFFREY, MICHAEL, KING, KEN, RICHARD, KUTCHMARICK, DAVID, RHEE, CHOONG-SUN, RIEMER, DAVID, WAYNE
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1992
Main classification: H03K5
IPC codes: G01R19, G05F3, G11C27, H01L21, H01L27, H03F1, H03F3, H03G1, H03K5, H03K7, H03K17, H03K19, H03M1