Flash-erasable semiconductor memory device having an improved reliability

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor devices and more particularly to a flash-erasable EPROM device or simply a flash memory device that has an improved reliability. In relation to the storage device of computers, there is a continuous demand for a nonvolatile semiconductor memory device having a large capacity for storing information. Particularly, the so-called flash-erasable memory device or simply flash memory device has been studied intensively in recent years as an alternative of hard disk devices. In flash memory devices, rewriting of data is possible similarly to the conventional random access memories, while the device can hold the written information even when the electrical power is turned off. Thus, the device is ideal for external storage device of computers such as a hard disk. Further, application to the memory cards is studied. In relation to various applications of the flash memory device, intensive efforts are in progress to improve the reliability of the device. FIG.1 shows the structure of a typical memory cell transistor that forms a flash memory device. Referring to FIG.1, the memory cell transistor is constructed on a semiconductor substrate 1 and includes a source region 6 and a drain region 7 formed in the substrate 1 similarly to a conventional MOS transistor. On the upper major surface of the substrate 1, a gate insulation film 2 is provided to cover the channel region extending between the source region 6 and the drain region 7, and a gate electrode 3 is formed on the gate insulation film 2 in correspondence to the channel region of the device. Further, a capacitor insulation film 4 is provided to surround the gate electrode 3, and the gate electrode 3 thereby forms a floating gate electrode. Further, an electrode 5 is provided on the floating gate electrode 3 such that the electrode 5 is insulated from the electrode 3 by the capacitor insulation film 4. Thereby, the electrode 5 is used as a control electrode. Hereinafter, the operation of a flash memory of the NOR type will be described. When writing data, a predetermined drive voltage is applied across the source region 6 and the drain region 7 such that the electrons are caused to flow from the source region 6 to the drain region 7. Simultaneously, a large positive voltage is applied to the control electrode 5 to induce a large electric field between the floating gate electrode 3 and the substrate 1. Thereby, the electrons transported along the channel region and accelerated in the vicinity of the drain region 7 are injected into the floating gate electrode 3 through the gate insulation film 2 as hot electrons. Once the electrons are injected, the electric charges associated with the electrons controls the conduction of the channel region between the source and drain regions 6 and 7. In other words, one can read the content of the data written into the memory cell transistor by detecting the conduction thereof. When erasing data, on the other hand, a large electric field is induced between the floating gate 3 and the source region 6 by applying a large positive voltage to the source region 6. Thereby, the electrons in the floating gate 3 dissipate into the source region 6 by causing a tunneling through the gate insulation film 2. FIG.2 shows the foregoing control scheme of the flash memory device for the writing mode for wiring data into the memory cell, the reading mode for reading data from the memory cell, and the erasing mode for erasing data from the memory cell, wherein the voltage V H is set typically to +12 volts, while the voltage V M may be set to +6 volts. Further, the voltage V L is set to about +5 volts. FIG.3 shows the overall construction of a typical flash memory device. Referring to FIG.3, the device includes a memory cell array 11 in which a plurality of memory cell transistors each having a construction of FIG.1 are arranged in rows and columns, and the memory cell in the memory cell array 11 is selected in response to address data that is supplied to a row address buffer circuit 12 for activating a row decoder 13 and a column address buffer circuit 14 for activating a column decoder 15. There, the row decoder 13 selects a word line WL in response to the row address data latched in the row address buffer circuit 12 while the column decoder 15 controls a column selection gate 16 to select a bit line BL in response to the column address data that is latched in the column address buffer circuit 14. In order to achieve inputting and outputting of data, there is provided a data bus 17 connected to an input/output buffer circuit 18, and the data on the bus 17 is written into a selected memory cell such as the memory cell 11a via a write amplifier 19 and the column selection gate 16. on the other hand, the data stored in the selected memory cell is transferred to the input/output buffer circuit 18 via the column selection gate 16 and a sense amplifier 20. Further, in order to control the read/write operation of the memory device, there is provided another buffer circuit 21 that is supplied with an output enable signal /OE, a chip enable signal /CE, and further with a write enable signal /WE, wherein the signal /OE is used for enabling the data output of the input/output buffer circuit 18, the signal /CE is used for the chip selection, and the signal /WE is used for enabling the writing of data into the selected memory cell. Further, there is provided an erase power supply unit 22 that characterizes the NOR type flash memory device, wherein the power supply unit 22 supplies a predetermined erase voltage when erasing the data from the memory cell array. As is well known, the erasing of data occurs simultaneously for all the memory cells in the memory cell array 11 in the flash memory device. In addition, in order to control the operation of memory cell device including the erase power supply 22, a controller 23 is provided. There, the controller 23 is supplied with data from the data bus 17 as well as an output of the buffer circuit 21 and controls the read/write as well as erase operation of the device. FIG.4 shows the writing of data into the memory cell transistor of FIG.1, wherein the vertical axis represents the drain current and the horizontal axis represents the drain voltage. As already noted with reference to FIG.2, the voltage V D is applied to the drain region during the writing process of data, while the voltage V H is applied simultaneously to the control gate. Referring to FIG.4, it will be noted that the drain current increases in an interval designated as "1" with increasing drain voltage V D , while the drain current decreases suddenly in correspondence to the interval designated as "2" with further increase in the drain voltage V D . In correspondence to this negative bump of the drain current, the injection of electrons into the floating gate electrode occurs. Further, when the drain voltage V D has reached an avalanche voltage V ABD , an avalanche breakdown occurs in the channel region of the memory cell transistor and the drain current increases steeply. Thereby, an efficient injection of the electrons is achieved into the floating gate. Thus, the flash memory device generally uses the avalanche voltage V ABD for the voltage V M shown in FIG.2 to achieve an efficient writing of the data. In fact, the drain voltage V D is clamped at the level V ABD when the foregoing positive control voltage V H is applied to the control gate. On the other hand, when the voltage of the control gate is low or zero in correspondence to an operational state of the device wherein no writing of data occurs, the drain current changes as shown in the broken line in FIG.4. There, the drain current remains low until a breakdown voltage V JCT is reached. In response to the voltage V JCT , a breakdown occurs at the p-n junction between the drain region and the substrate. Generally, the voltage V JCT is larger than V ABD by more than one volt. Thereby, there can occur a possibility that the writing of data into a first memory cell transistor can affect the operation of a second memory transistor that shares the power supply line commonly with the memory cell transistor. It should be noted that the large drain voltage applied to the first memory cell transistor for writing data induces a large electric field between the drain region and the floating gate in the second memory cell transistor. Thereby, the electric charges stored in the second memory cell transistor can dissipate into the drain of the same memory cell transistor and the data held therein is destroyed. This interference of memory cell transistors is known as disturbance." Further, the conventional flash memory device has suffered from the problem of limited flexibility in the design of redundant construction in that only the column redundancy is possible as shown in FIG.5. Referring to FIG.5, the drawing corresponds to FIG.3 and includes the memory cell array 11 that in turn includes a number of memory calls M 1,1 - M 2,3 provided in correspondence to intersections of word lines WL 1 - WL 2 and bit lines BL 1 - BL 3 . In FIG.5, those parts corresponding to the parts described previously are designated by the same reference numerals and the description will be omitted. It will be noted that the column selection gate 16 includes transfer gate transistors Tsw 1 - Tsw 3 for selecting the bit lines BL 1 - BL 3 respectively. In the memory cell array 11 of FIG.5, it will be noted that there is provided another transfer gate transistor Tsw 4 that is activated in response to an output of a decoder 24 for selecting another bit line BL 4 , and a column redundant memory cell array 11 CR is provided in connection to the bit line BL 4 . There, the redundant memory cell array 11 CR includes memory cell transistors M 1,4 and M 2,4 having respective drains connected commonly to the bit line BL 4 and the memory cell array 11 CR is activated in response to the output of the redundant decoder 24 that in turn is controlled by a defect detection circuit 25. There, the circuit 25 is supplied with the column address data from a column buffer circuit 14 and compares the same with the address data for defective memory cells stored in a memory device not illustrated. When the address data indicates the selection of a defective memory cell, the circuit 25 activates the redundant decoder 24 that'in turn selects the redundant bit line BL 4 . It should be noted that such a redundant memory cell array may be provided as a part of a utility memory cell array that is provided separately from the real memory cell array for various purposes such as testing. In other words, one can use such a memory cell array 11 CR also for testing as will be discussed later with reference to the embodiment of the present invention. In such a conventional flash memory device, it is desirable to provide a row redundant memory cell array in addition to the column redundant memory cell array 11 CR for increasing the degree of freedom for saving the defect in the memory cells. However, such a construction of row redundant memory cell array has been generally impossible in the flash memory devices. Hereinafter, the reason of this undesirable situation will be examined briefly. In the flash memory devices, the electric charges are removed from the floating gate each time the data stored in the memory cell is erased. As already noted, such an erasing process is conducted by applying a positive voltage to the source region. Thereby, all the memory cells that are connected commonly to the source supply voltage experience dissipation of the electric charges from the floating gate. In other words, the data stored in the memory cells that form the memory cell array of the device are erased simultaneously. Another point that requires special attention in the flash memory devices is that the dissipation of electrons from the floating gate should be achieved in such a manner that no substantial electric charges remain in the floating gate after the erasing of data has occurred in the memory cell. When the removal of electrons is excessive, the floating gate may charge positively and the memory cell transistor is turned on permanently. In order to avoid this problem of "excessive erasing," it is generally practiced to write data "0" into the memory cell by injecting electrons to the floating gate before each erasing process of data. Thus, when a row redundant memory cell array is constructed by modifying the circuit of FIG.5, for example such that the word line WL 2 is selected in place of the word line WL 1 for saving defective memory cells connected to the word line WL 1 , the writing of the data "0" does not occur to the memory cells connected to the word line WL 1 . on the other hand, the removal of the electric charges occurs also in these memory cells in response to the erasing process, as these memory cells are connected also to the erase power supply unit 22. Thereby, the memory cell transistors M 1,1 - M 1,4 connected to the word line WL 1 are inevitably erased excessively as a result of the excessive removal of the electrons to the drain region. When this occurs, the floating gate is injected with holes and the memory cell transistors take a permanently turned-on state. As the transistors M 1,1 - M 1,4 are connected to the bit lines BL 1 - BL 4 , such an erroneous turning-on of the memory cell transistors inevitably causes a erroneous voltage level of the bit lines and the overall operation of the flash memory device becomes defective. In the conventional flash memory devices having the column redundancy as shown in FIG.5, it is proposed to divide the memory cell array into a plurality of blocks each driven by an independent power supply unit such that the simultaneous erasing of data occurs only in each block instead of the entirety of the memory cell array. When the column redundancy is applied to such a device, however, the redundant memory cell columns are provided in each block and there arises an inconvenience in that a substantial device area is occupied by the redundant memory cell columns. Thereby, there is a demand to reduce the area of the device that is occupied by the redundant memory cell column. In the conventional memory devices such as dynamic random access memories or static random access memories, it has been practiced to provide a utility memory cell block for testing the device. Such a utility block is used for example for the purpose of guaranteeing a predetermined number of times for the rewriting of data into the memory cell transistors forming the memory cell array. In the flash memory devices, however, erasing of data is achieved in the ordinary, "real" memory cell block each time the data is erased from the utility memory cell block, as long as the memory cell transistors in the real memory cell block share the electric power supply with the memory cell transistors in the utility memory cell block. Thereby, the memory cell transistors in the real memory cell block are erased excessively and the proper read/write operation of the device Is no longer possible. In other words, the conventional flash memory devices have suffered from the problem that the test for guaranteeing the number of times the write operation can be achieved properly is impossible. In addition, in the conventional flash memory devices, there has been a problem in that one has to design the device to have a relatively large channel length in correspondence to the relatively large voltage applied to the source region for erasing data from the memory cell transistors, such that a sufficient junction breakdown voltage is secured. On the other hand, such a large channel length inevitably imposes a problem in the miniaturization of the device. Thus, it is desired to reduce the magnitude of the .voltage that is applied to the memory cell transistor for erasing information therefrom. US-A-4 404 659 discloses a semiconductor memory device according to the preamble of claim 1. This device is a PROM consisting of a plurality of FAMOS's (memory MISFETs) each having a control gate connected to a word line, and a drain connected to a bit line. The potential on the bit line is raised to Vpp 2µs after the potential on the word line is raised to Vpp, and is lowered to zero 2µs before the potential on the word line is lowered to V DD . JP-A-62-6494 discloses a semiconductor memory device in which the bit line potential and the word line potential have a similar relationship to that disclosed in US-A-4 404 659. SUMMARY OF THE INVENTION Accordingly, it is desirable to provide a novel and useful flash memory device, wherein the foregoing problems are eliminated. According to a first aspect of the present invention, there is disclosed a semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region; and a control electrode provided on said floating gate with a separation therefrom by a capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; addressing means for selecting a memory cell transistor in said memory cell array; writing means for writing information into said selected memory cell transistor, said writing means comprising write control means supplied with a write control signal (PGM) when writing information into said selected memory cell transistors; and reading means for reading information from said selected memory cell transistor; wherein said writing means is operable to raise the drain voltage of a selected said memory transistor a delay time after raising the gate voltage thereof, and/or operable to lower the gate voltage of the selected said memory cell transistor a delay time after lowering the drain voltage thereof; characterised in that: said semiconductor memory device is a flash-erasable device having erasing means for erasing information from a plurality of memory cell transistors included in said memory cell array simultaneously; said writing means produces a gate control signal and a drain control signal in response to said write control signal, said write control signal, said gate control signal and said drain control signal being defined by respective leading edges and respective trailing edges, and said writing means further comprising: gate control means supplied with said gate control signal from said write control means for producing a gate control voltage to be supplied to said control electrode of said selected memory cell transistor such that said gate control voltage is produced in response to said leading edge of said gate control signal and ends with said trailing edge of said gate control signal; and drain control means supplied with said drain control signal from said write control means for producing a drain control voltage to be supplied to said drain region of said selected memory cell transistor such that said drain control voltage is produced in response to said leading edge of said drain control signal and ends with said trailing edge of said drain control signal; and in that said write control means controls said drain control signal and said gate control signal such that at least one of the cases (a) and (b) occurs, wherein, in said case (a), said leading edge of said drain control signal follows said leading edge of said gate control signal after a delay time defined by a logic circuit included in said write control means and causing a logic inversion in said gate control signal, and wherein, in said case (b), said trailing edge of said gate control signal follows said trailing edge of said drain control signal after a delay time needed defined by a logic circuit included in said write control means and causing a logic inversion in said drain control signal. According to a second aspect of the present invention, there is provided a method for writing information into a flash-erasable semiconductor memory device, said flash-erasable semiconductor memory device comprising: a memory cell array that includes a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region; and a control electrode provided on said floating gate with a separation therefrom by said capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; said method comprising the steps of: selecting a memory cell transistor to which a writing of information is to be achieved; producing a gate-control signal in response to a write control signal supplied to said flash-erasable semiconductor memory device; producing a drain control signal in response to said write control signal; increasing, in response to said gate control signal, a level of a gate voltage that is supplied to said control electrode of said selected memory cell transistor to a predetermined level used for writing information; increasing, in response to said drain control signal, a level of a drain voltage that is supplied to said drain region to a predetermined level used for writing information, said step of increasing the level of the drain voltage being achieved a first delay time after said step for increasing the level of the gate voltage has been achieved; decreasing the level of said drain voltage, in response to said drain control signal, after said step of increasing the level of said drain voltage; and decreasing the level of said gate voltage, in response to said gate control signal, a second delay time after said step of decreasing the level of said drain voltage; said first delay time comprising a delay time needed for causing a logic inversion in said gate control signal, said second delay time comprising a delay time needed for causing a logic inversion in said drain control signal. An embodiment of the present invention can provide a flash memory device, wherein a reliable read/write operation is guaranteed by controlling the magnitude of the voltage applied to the control electrode such that the control voltage is clamped at the avalanche voltage. Thereby, the problem of excessive rising of the control voltage and hence the problem of the interference between adjacent memory cell transistors is avoided. Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the structure and operation of a typical flash memory cell transistor; FIG. 2 is a diagram showing the biasing of the flash memory cell transistor for various operations of the memory device; FIG.3 is a circuit diagram showing an overall construction of a typical conventional flash memory device; FIG.4 is a diagram showing an injection of electrons into a floating gate of the flash memory; FIG.5 is a block diagram showing the structure of a conventional flash memory having a column redundancy; FIG.6 is a diagram showing the principle of the present invention; FIG.7 is a diagram showing the circuit diagram of a control circuit used in the flash memory of FIG.6; FIGS.8(A) - 8(C) are diagrams showing the timing for biasing the flash memory of FIG.6; FIG.9 is a block diagram showing the overall construction of a flash memory that uses the control circuit of FIG.7; and FIG.10 is a diagram showing the structure of a memory cell transistor used in the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.6 shows the principle of the present invention. Referring to FIG.6, the flash memory includes the memory cell array schematically illustrated in the form of the memory cell transistor 11a, wherein the control circuit 23 of the flash memory as represented schematically in FIG.3 includes a signal generator 233 that is supplied with an output signal PGM of the buffer circuit 21 in response to the write enable signal /WE when writing data. There, the circuit 233 produces a first control signal PGMR and a second control signal PGMC in response to the signal PGM, wherein the signal PGM causes a transition to the high level state during the interval in which the writing of data is achieved. The circuit 231 in turn produces a gate voltage V G in response to the signal PGMR and the voltage level of the control gate represented as "G" in FIG.6 is held at a high level state corresponding to the voltage V H during the interval in which the signal PGMC assumes the high level state. The circuit 232 in turn produces a drain voltage represented as V D in FIG.6 such that the drain voltage V D is held at the level V M during the high level interval of the signal PGMC. In the present embodiment, in order to guarantee that the drain voltage V D shown in FIG.4 is clamped at the avalanche voltage V ABD , the gate voltage V G is set to the high level state V H before the drain voltage V D rises to the high level state V M , and the gate voltage V G maintains the high level state even after the drain voltage V D has caused a transition to the low level state. Thereby, the problem of the drain voltage V D exceeding the voltage V ABD is successfully avoided and the problem of disturb or interference between the memory cell transistors is eliminated. FIG.7 shows the circuit diagram of the circuit 233. Referring to FIG.7, it will be noted that the circuit 233 includes an inverter 233a supplied with the signal PGM and produces an output as a logic inversion of the signal PGM. The output of the inverter 233a is supplied on the one hand to a NAND gate 233d and on the other hand to a NOR gate 233e, wherein the NAND gate 233d and the NOR gate 233e form a flip-flop circuit that includes a first feedback path for feeding back the output of the NAND gate 233d to another input terminal of the NOR gate 233e via an inverter 233b and a second feedback path for feeding back the output of the NOR gate 233e to another input terminal of the NAND gate 233d via an inverter 233c. Thereby, the output signals PGMR and PGMC are obtained respectively at the output of the NAND gate 233d and the output of the NOR gate 233e with a timing relationship as shown in FIGS.8(A) - 8(c), wherein FIG.8(A) shows the waveform of the signal PGM, FIG.8(B) shows the waveform of the signal PGMR, and FIG.8(C) shows the waveform of the signal PGMC. Referring to FIGS.8(A) - 8(C), it will be noted that PGMR rises substantially in synchronization to the leading edge of the PGM, while the leading edge of the PGMC is delayed with respect to the leading edge of the PGM by an interval td 1 , wherein the interval td 1 corresponds to the delay caused by the NAND gate 233d and the inverter 233b. In other words, the delay td 1 is set such that the rise of the drain voltage V D occurs after the rise of the gate voltage VG in the circuit 233 of FIG.7. Further, it should be noted that the PGMC causes a transition to the low level state substantially in synchronization with the trailing edge of the PGM, while the trailing edge of the PGMR appears after a delay of td 2 with respect to the trailing edge of the PGM, wherein the delay td 2 is determined by the delay caused by the NOR gate 233e and the inverter 233c. Again, the delay td 2 is determined such that the gate voltage returns after the drain voltage returns to the low level state. This indicates that the gate voltage V G is held at the high level state V H for a while, even when the drain voltage V D has caused a transition to the low level state. As a result of the timing relationship shown in FIGS.8(A) - 8(C), it will be noted that in no moment the situation occurs wherein the drain voltage V D rises while the gate voltage V G is held at the low level state. Thereby, the voltage level V D never rises beyond the avalanche voltage V ABD , and the problem of the disturbance described earlier is effectively eliminated. FIG.9 is a block diagram similar to FIG.5 and shows the construction of the memory device that uses the foregoing circuit 233 for the formation of the signals PGMR and PGMC. In FIG.9, those parts corresponding to FIG.5 are designated by the same reference numerals and the description will be omitted. Referring to FIG.9, it will be noted that the PGMR is supplied to a row selection power supply circuit 13A that produces the output signal V G in response to the high level state of the PGMR, and the signai V G is supplied to the row decoder 13 to which the row address data is supplied simultaneously. There, the row decoder 13 selects a word line such as WL 1 in response to the row address data supplied thereto and supplies the gate voltage V G to the selected word line WL 1 . Further, there is provided a column power supply circuit 15A that is supplied with the PGMC, wherein the circuit 15A activates the column decoder 15 in response to the high level interval of the PGMC. Further, the PGMC is supplied also to a drain power supply circuit 19A that forms a part of the write amplifier 20, and the drain voltage V D is controlled as already described with reference to FIGS.8(A) - 8(C) in response to the PGMC. As the chance that the gate voltage of the selected word line such as WL 1 remains low while the level of the voltage V D is held at the high level state V M is positively eliminated in the present construction, the drain voltage V D never increases beyond the avalanche voltage V ABD , and the problem of the disturbance is successfully eliminated. It should be noted that the delay times td 1 and td 2 are determined to be larger than the difference between the signal delay occurring in the conductor strip that transfers the signal PGMR from the circuit 233 to the control gate of the selected memory cell transistor and the signal delay occurring in the conductor strip for transferring the signal PGMC from the circuit 233 to the drain region of the selected memory cell transistor. It should be noted that the conductor strip used for carrying the signal PGMR is generally formed of polysilicon and the delay occurring in the conductor strip for transferring the signal PGMR is generally larger than the delay occurring in the conductor that transfers the signal PGMC. By setting the delay time td 1 and td 2 as such, the phase relationship shown in FIGS.8(B) and (C) is guaranteed also on the control gate and on the drain region of the memory cell transistor. In the foregoing embodiment, one may employ a laminated structure of silicon nitride sandwiched by a pair of silicon oxide films for the capacitor insulation film 4 shown in the memory cell transistor of FIG.1. By employing such a laminated structure, it is possible to reduce the thickness of the capacitor insulation film without sacrificing the reliability and anti-leak characteristics of the device. Thereby, an efficient capacitor coupling is achieved between the control electrode and the floating gate electrode. It should be noted that the silicon oxide film formed on the polysilicon floating gate shown in FIG.1 tends to form pinholes when the thickness is reduced due to the effect of the grain boundaries in the gate electrode. By covering the thin silicon oxide film by a silicon nitride film and forming a thin silicon oxide film further on the silicon nitride film, one can successfully eliminate the leak from the floating gate while reducing the thickness of the capacitor insulation film. FIG.10 shows the structure of such a memory cell transistor that has the laminated structure for the capacitor insulation film 4. In FIG.10, those parts corresponding to the parts shown in FIG.1 are represented by the same reference numerals. There, it will be noted that the capacitor insulation film 4 includes a silicon oxide film 4a formed directly on the floating gate electrode 3, a silicon nitride film 4b deposited on the silicon oxide film 4a, and a silicon oxide film 4c formed on the silicon nitride film 4b. In the embodiment described heretofore, it should be noted that the power supply unit 22 may be a switching circuit for switching the source voltage between a high level voltage such as +12 volts and a low level voltage such as +5 volts, instead of the voltage generator circuit that generates the high voltage output and the low voltage output. In such a construction, two voltage sources, the first for providing the high voltage and the second for providing the low voltage are used, and the power supply unit merely switches the output voltage in response to a control signal. Further, the present invention is not limited to the embodiment described heretofore, but various variations and modifications may be made without departing from the scope of the invention.

Claims: A semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region; and a control electrode provided on said floating gate with a separation therefrom by a capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; addressing means for selecting a memory cell transistor in said memory cell array; writing means for writing information into said selected memory cell transistor, said writing means comprising write control means (233) supplied with a write control signal (PGM) when writing information into said selected memory cell transistors; and reading means for reading information from said selected memory cell transistor; wherein said writing means is operable to raise the drain voltage of a selected said memory transistor a delay time after raising the gate voltage thereof, and/or operable to lower the gate voltage of the selected said memory cell transistor a delay time after lowering the drain voltage thereof; characterised in that : said semiconductor memory device is a flash-erasable device having erasing means for erasing information from a plurality of memory cell transistors included in said memory cell array simultaneously; said writing means produces a gate control signal (PGMR) and a drain control signal (PGMC) in response to said write control signal (PGM), said write control signal, said gate control signal and said drain control signal being defined by respective leading edges and respective trailing edges, and said writing means further comprising: gate control means (231) supplied with said gate control signal (PGMR) from said write control means (233) for producing a gate control voltage (V G ) to be supplied to said control electrode (G) of said selected memory cell transistor (11a) such that said gate control voltage (V G ) is produced in response to said leading edge of said gate control signal (PGMR) and ends with said trailing edge of said gate control signal (PGMR); and drain control means (232) supplied with said drain control signal (PGMC) from said write control means (233) for producing a drain control voltage (V D ) to be supplied to said drain region (D) of said selected memory cell transistor (11a) such that said drain control voltage (V D ) is produced in response to said leading edge of said drain control signal (PGMC) and ends with said trailing edge of said drain control signal (PGMC); and in that said write control means (233) controls said drain control signal (PGMC) and said gate control signal (PGMR) such that at least one of the cases (a) and (b) occurs, wherein, in said case (a), said leading edge of said drain control signal (PGMC) follows said leading edge of said gate control signal (PGMR) after a delay time (td 1 ) defined by a logic circuit included in said write control means (233) and causing a logic inversion in said gate control signal (PGMR), and wherein, in said case (b), said trailing edge of said gate control signal (PGMR) follows said trailing edge of said drain control signal (PGMC) after a delay time (td 2 ) needed defined by a logic circuit included in said write control means (233) and causing a logic inversion in said drain control signal (PGMC). A flash-erasable semiconductor memory device as claimed in claim 1, wherein said write control means (233) produces said gate control signal (PGMR) such that said leading edge of said gate control signal is substantially coincident to said leading edge of said write control signal (PGM), and wherein said write control means (233) produces said drain control signal (PGMC) such that said trailing edge of said drain control signal is substantially coincident to said trailing edge of said write control signal (PGM). A flash-erasable semiconductor memory device as claimed in claim 1, wherein said capacitor insulation film has a laminated structure including a silicon nitride layer sandwiched by a pair of silicon oxide layers. A method for writing information into a flash-erasable semiconductor memory device, said flash-erasable semiconductor memory device comprising: a memory cell array that includes a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region; and a control electrode provided on said floating gate with a separation therefrom by said capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; said method comprising the steps of: selecting a memory cell transistor (11a) to which a writing of information is to be achieved; producing a gate-control signal (PGMR) in response to a write control signal (PGM) supplied to said flash-erasable semiconductor memory device; producing a drain control signal (PGMC) in response to said write control signal (PGM) ; increasing, in response to said gate control signal (PGMR), a level of a gate voltage (V G ) that is supplied to said control electrode (G) of said selected memory cell transistor (11a) to a predetermined level used for writing information; increasing, in response to said drain control signal (PGMC), a level of a drain voltage (V D ) that is supplied to said drain region (D) to a predetermined level used for writing information, said step of increasing the level of the drain voltage (V D ) being achieved a first delay time (td 1 ) after said step for increasing the level of the gate voltage (V G ) has been achieved; decreasing the level of said drain voltage (V D ), in response to said drain control signal (PGMC), after said step of increasing the level of said drain voltage (V D ) ; and decreasing the level of said gate voltage (V G ), in response to said gate control signal (PGMR), a second delay time (td 2 ) after said step of decreasing the level of said drain voltage (V D ) ; said first delay time (td 1 ) comprising a delay time needed for causing a logic inversion in said gate control signal (PGMR), and said second delay time (td 2 ) comprising a delay time needed for causing a logic inversion in said drain control signal (PGMC). A method as claimed in claim 4, wherein said step of increasing the level of said drain voltage (V D ) is delayed with respect to said step of increasing the level of said gate voltage (V G ) by a delay time (td 1 ) larger than a signal delay occurring in a conductor strip connected to said control electrode. A method as claimed in claim 4, wherein said step of decreasing the level of said gate voltage (V G ) is delayed with respect to said step of decreasing the level of said drain voltage (V D ) by a delay time (td 2 ) larger than a signal delay occurring in a conductor strip connected to said control electrode.

Inventors: AKAOGI TAKAO, KAJITA TATSUYA, OGAWA YASUSHIGE, WATANABE HISAYOSHI, YAMASHITA MINORU, AKAOGI, TAKAO, KAJITA, TATSUYA, OGAWA, YASUSHIGE, WATANABE, HISAYOSHI, YAMASHITA. MINORU
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1992
Main classification: G11C16
IPC codes: H01L21, H01L27, G11C16