DC to DC converter

Abstract: An improved DC to DC converter is provided in particular for converters with high power density requirements. The converter comprises an input voltage source and a capacitor connected in series to the voltage source. A switching transistor configuration connects the voltage source and the capacitor alternatively to the primary windings of a transformer. The secondary windings of the transformer are connected to a full-wave rectifier and a filter. The output voltage provided at the output of the filter is modulated by a controlling means.

Description: BACKGROUND Field of Invention This invention applies to the field of DC to DC power conversion and in particular to converters required to provide high power density. Prior Art A vast variety of topologies have been invented over the years with the purpose of improving power density of power converters. Some of these topologies provide means to reduce or to eliminate switching losses in order to allow increased frequency of operation, increased efficiency, reduced size and weight. Typical of this approach is the technique disclosed in Patent No. 4,415,959, issued to P. Vinciarelli, for "Forward Converter Switching at Zero Current" which reduces the size of the energy storage components. Another approach is disclosed by U.S. Patent No. 4,618,919, issued to Hubert C. Martin, Jr., for "Topology for Miniature Power Supply with Low Voltage and Low Ripple Requirements". This patent combines two single ended (flyback) converters to increase effective ripple frequency and reduce the size of energy storage components. Another approach is to maximise the energy of switching devices and the transformer in order to improve the power transfer characteristics of the converter as indicated in US Patent No. 4 441 146 issued to P. Vinciarelli for "Optimal resetting of the transformer's core in single ended forward converters" and in US Patent No. 4 809 148 issued to Barn for "Full-fluxed, single ended DC converter". A further, similar circuit configuration is disclosed in Patent SU-A-892614, which uses a single cored transformer with a single winding in the primary transformer circuit. From this document the features of the preamble of claim 1 are known. Finally, in an article published in the PCIM magazine, January 1991, p 8, "New PWM Topology features zero-voltage switching and constant switching frequency", and also disclosed in US Patent No. 4 959 764, John A. Bassett proposes a topology that offers both the improved utilisation of components and lossless switching, thereby allowing efficient operation at high frequency. While each of the above disclosures addresses some facets of the power conversion issue, none provides an approach achieving all of the advantage discussed above. The present invention provides a DC to DC converter comprising: an input voltage source, a capacitance, an output circuit, a switching circuit for connecting the output alternatively across the voltage source and the capacitance; the output circuit further comprising primary inductor means coupled in series with the switching circuit whereby to produce a bidirectional current flow through the inductor means on operation of the switching means, secondary inductor means providing electrical isolation from and inductively coupled to the primary inductor means, the secondary inductor means including series coupled inductors, and first and second rectifiers each having a first terminal coupled to one of the series connected inductors respectively and second terminal connected to a common point for producing full wave rectification of current flowing in the secondary inductor means characterised in that the primary inductor means includes first inductor means and separate second inductor means coupled in series to the switching circuit, and the secondary inductor means includes a third inductor means and a separate fourth inductor means coupled in series, the first and third, and the second and fourth inductor means forming respective separate inductive couplings. Embodiments of the invention will now be described by way of example, with reference to the accompanying drawings. In general, Figures 1 to 7 are intended to illustrate the principles of operation of power converters so as to enable an example of the invention shown in Figure 8 to be fully understood. In more detail: Figure 1a is a simplified circuit diagram illustrating the principles of operation of power converters; Figure 1b represents the wave diagrams of various components of Figure 1a; Figure 2a is a circuit diagram illustrating features of another power converter circuit; Figure 2b represents the wave diagrams of various components in Figure 2a; Figure 3a is a circuit diagram illustrating features of still another power converter circuit; Figure 3b is a circuit diagram showing an embodiment of the switching circuit which may be used with the present invention; the output circuit is another example of an output stage of a power converter circuit; Figure 3c is a circuit configuration of a prior art topology; Figure 4a is a wave diagram of magnetizing currents for full load and no load conditions in Figure 3b; Figures 4b and 4c depict the wave forms of switching transistor currents in Figure 3b; Figure 4d is a wave diagram of the current in primary winding 32 in figure 3b; Figure 5 is the wave diagram of point A of Figure 3a or 3b at no load; Figure 5b is a wave diagram of point A in Figure 3a or 3b at full load; Figure 6 is a circuit diagram illustrating features of another power converter circuit; Figure 7 is a circuit diagram illustrating features of yet another power converter circuit; and Figure 8 is a circuit diagram illustrating one embodiment of the present invention. In Figure 1a, a voltage source 14 supplies a voltage Vin to a flyback converter formed by a toggle switching device 12, a capacitor 16 of value C 1 , and an inductor 10 of value L. Switch 12 is assumed to be in position A for a time interval t 1 , then instantaneously moves to position B for a time interval t 2 . The process is repeated indefinitely with a period T given by: T = t 1 + t 2 Duty cycle D is defined as: D = t 1 T This action of switch 12 connects inductor 10 alternatively across the input voltage source 14 and cross capacitor 16 . Assuming that capacitor 16 has a value large enough such that the variation of the voltage V c1 across capacitor 16 during a time interval T is negligible, its steady state value must satisfy the volt-second balance across inductor 10: Vin . t 1 = V c1 t 2 V c1 =Vin. t 1 t 2 By substituting (1) and (2) into (4) we get: V c1 =Vin D 1- D This is the familiar DC transfer function of the buck boost (flyback) converter. The important characteristic of this flyback converter is that due to the bidirectional nature of the switch 12, energy can flow from either voltage source 14 to capacitor 16 or vice versa during either position of the switch. This is illustrated in Figure 1b, wherein the current flowing through inductor 10 is triangular and has zero average value, and the voltage across it is a square wave with a positive value V in and a negative value Vc 1 . Referring now to Figure 2a, a bridge rectifier 20 and a filter formed by inductor 22 with a value L f and capacitor 24 with a value C f are now connected across the inductor 10, with a resistor 26 loading the filter's output. The average output voltage Vo appearing across the load 26 is given by: V o =Vin.D+Vin D 1- D .(1- D ) or, V o = 2 VinD Equation (7) shows the DC transfer characteristic of the circuit of Figure 2a, i.e., the value of its output voltage as a function of the input voltage and the operating duty cycle. Switch 12, in addition to driving the bidirectional flyback converter, also operates as a double ended converter in conjunction with the circuit connected in parallel to inductor 10, generating the output voltage given by equation (7). The introduction of the loading circuit of Figure 2a which includes the full wave rectifier 20, filter inductor and capacitor 22 and 24 and load resistor 26, alters the current in the flyback inductor 10 as discussed below. Assuming that the filter inductor 10 is large enough such that its current i L is ripple free, during interval t 2 this current will be extracted from capacitor 16. Consequently, the volt-second balance constraint on flyback inductor 10 will cause a DC current level buildup in it, thereby maintaining the voltage on capacitor 16 at the value given by equation (5). The current in inductor 10 under intermediate load and under full load is shown in Figure 2b. As is shown later, the situation where ΔI LPTP has twice the value of the output current Io is of particular significance for zero voltage switching operation. Although the circuit of Figure 2a can be used as is, circuit configurations where the output voltage is isolated from the input circuit or at least is referred to the same ground find more applications. One such circuit shown in Figure 3a can be obtained by using an isolation transformer 30 to connect the rectifier bridge 20, the filter 22-24, and the load 26 across the flyback inductor 10 . At this point, a significant simplification may be obtained by eliminating inductor 10 and replacing it with the magnetizing inductance of the primary winding 32 of transformer 30, after gapping its core or using a core material capable of supporting the DC flux resulting from the DC current buildup mentioned before. It will be evident to those versed in the art that depending on the application, transformer 30 may be configured as an autotransformer and can have a center-tapped secondary or a multitude of secondaries if more than one output voltage is desired. In order to contrast the advantages of the switching arrangement in Figure 3b with the prior art, Figure 3b can be compared to prior art circuits like the one disclosed in U.S. Patent 4,441,146. In Figure 3b, the toggle switch is realized using two MOS transistors 34 and 36, driven by two complementary signals so that when transistor 34 is on, transistor 36 is off and vice versa. Also, in order to avoid cross conduction, a short delay time is provided between the turn-off of one transistor and the turn-on of the next. This delay will have no impact on the operation as described above, since when transistor 34 is turned off, the current of the flyback inductor (now the shunt inductance of transformer 30) will free wheel through the body diode of 36 and vice versa. For reference purposes, the circuit shown in U.S. Patent 4,441,146 at Figure 4e is shown herein in Figure 3c, this being one of several possible embodiments. The components 38 and 40 form a "magnetizing current mirror" that resets the core of the transformer. In this case, the magnetizing inductance of the transformer 42 is fulfilling no useful purpose. Presumably the magnetizing inductance is kept at the highest value possible in order to minimize magnetizing current and, as opposed to the circuit of the present invention, eliminates any DC component from the core flux at any operating condition. Otherwise, the circuit is a single ended forward converter, with an output voltage given as: Vo=Vin.D Equation (8) assumes unity turns ratio for transformer 42. Assuming that the converter is designed to operate over an input voltage range Vin (min) to Vin (max) , corresponding to a duty cycle range D max to D min , the ripple voltage appearing across the filter inductor will have a maximum peak to peak value of: V ptp(F W D) = Vin max In the converter illustrated in Figure 3b, the peak-to-peak ripple will be the difference between the secondary voltage during the conduction of transistor 34 and the secondary voltage during the conduction of transistor 36. Assuming the same input voltage range and same output voltage, the transformer turns ratio has to be 0.5 (ref. eq. 7). The peak-to-peak voltage will therefore be: V ptp (NEW) = 0.5 ( Vin - VinD 1- D ) or V ptp (new) = 0.5 Vin (1-2 D ) 1- D As we can see, the value of the voltage is a function of the duty cycle and it nulls at D = 0.5. Furthermore, assuming a practical range of D of 0.35 to 0.7 (an input voltage range of 2:1) the maximum peak to peak voltage will occur at the highest input voltage and will have the value: V ptp (new) = 0.5. Vin max 1-0.7 1-0.35 =0.2308 Vin This value represents an improvement of a factor of V ptp (FWD) /V ptp (NEW) = 4.33. The significance of this result is that the filter inductor can be reduced by a factor of 4.33 in the circuit of Figure 3b for the same value of peak-to-peak ripple current in the output circuit as compared to a forward converter operating over the same range of input voltage and duty cycles. Further examination of the switching circuit of Figure 3b reveals an additional important property. By connecting capacitor 44 with a value of C S1 and capacitor 46 with a value of C S2 across transistors 34 and 36, it is possible to delay the rise of the voltage across the switches at turn-off until the current in the switch reaches zero, thereby virtually eliminating turn-off losses. Furthermore, by delaying the turn-on of the transistors until the load current is clamped by the body diodes (or diodes connected in parallel to the switches in case devices other then MOSFETS are used), the capacitors across the devices are charged/discharged by the load current, thereby eliminating the turn on losses of the switches. In order to achieve these operating conditions, some constraints must be imposed on the circuit's elements. For one optimized performance, the following constraints apply: I L ptp = I mag ptp = Vin min D max · T L =2 I'o max This equation allows calculation of L mag : L mag = L = Vin min D max T 2 I'o max where I'o max is the value of the output current reflected to the primary of the transformer 30. This constraint will bring the magnetizing current of transformer 30 to change between zero and 2I'o max (ref. Fig. 4a) at full load and between -Io' max and +Io' max at no load. As shown in Figures 4b and 4c, the current in Q 1 , transistor 34 at the turn-off instant may vary from I'o max at no load to 3I'o max at full load, while the current in Q 2 , transistor 36 at turn off will be always equal to I'o max . These circuits will be available to charge/discharge capacitors 44 and 46 during the dead time intervals between the transistors conduction. Figure 4d shows the current of the primary winding 82 of transformer 30. Figures 5a and 5b show the voltage at point A of Fig. 3 at no load and full load respectively. Since the lowest currents occur at no load, guaranteeing that the primary current of the transformer can charge the capacitors at no load during the available dead time, the constraints on the values of the capacitors and the dead time are determined by the no load condition: I'o max . t d =( C S1 + C S2 )Δ V max . where t d is dead time between the conduction of transistors 34 and 36 and ΔV max is the maximum peak to peak value of voltage at point A of Figure 3, the value of this voltage is given by: Δ V max =[ Vin ( 1 1- D )] max Evidently, this value depends on the range of input voltage and the maximum duty cycle. For an input voltage range of 2 and a maximum duty cycle of 0.7, ΔV max will occur at minimum input voltage and will be equal to 3.333 Vin min . Equation 15 allows us to choose arbitrarily either the value of the capacitors or the value of the dead time t d . For instance, when operating at a high frequency it may be desirable to use the drain-to-source capacitance of the transistors themselves to obtain zero voltage switching. By substituting the value of the capacitances in Equation 15 we can find the value of t d necessary to guarantee zero voltage switching. On some occasions the value of self-capacitance or parasitic capacitance of transistors 34 and 36 may be such that capacitors 44 and 46 are not necessary. The converter may still operate with zero switching losses using the self capacitance of transistors 34 and 36. Also, by making the peak-to-peak magnetizing current of the transformer either higher or lower than twice the reflected load current (Equation 13), we either increase the conduction losses in the switches and the primary of the transformer, or lose the zero voltage switching before reaching full load. Nevertheless, economic and other trade offs may dictate a relaxation of these constraints so only part of the potential improvement is realized. It should be understood that by applying circuit theory rules to the configurations of Figures 1a, 2a and 3b, those versed in the art can modify the circuits without altering its topological essence or its mode of operation. For instance, by using two primary windings 60 and 62, as shown in Fig. 6, the circuit can be modified so that both switches are referred to the same point. In the converter illustrated in Figure 7, the output circuit includes two separate inductors 70 and 72 each having a value L/2 which is half the value of inductor 10 of Figure 1a. Inductors 70 and 72 are connected in series with diodes 74 and 76. A capacitor 78 is connected between the common terminal of the inductors and the common terminal of the diodes. Hence, the output circuit provides full wave rectification by using two rectifiers 74 and 76 and a capacitor 78. The output voltage across the load in Figure 7 is only one half the value of the voltage V 0 obtained by the output circuit of Figure 2a. An advantage of the output circuit of Figure 7 is the use of only two rectifiers instead of a full bridge rectifier. Another advantage is the use of the inductors 70 and 72 as both flyback converter inductor and output filter inductors for the output voltage. The output circuit is similar to the circuit disclosed in US patent No. 4,899, 271 issued to Seiersen. Figure 8 illustrates one embodiment of the invention. The output circuit includes two separate inductors 82 and 84 each having a value L/2 which is one half the value of inductor 10 of Figure 1a. Inductors 82 and 84 each have isolation windings 82a and 84a. Inductors 82 and 84 each have low magnetizing inductance. The isolation windings 82a and 84a are connected in series with diodes 80 and 86 connected at each end of the isolation windings. A capacitor 88 is connected between the common terminal of the isolation windings and the common terminal of the diodes. Load 90, is connected in parallel with capacitor 88. Hence, the output circuit provides full wave rectification by using two rectifiers 80 and 86 and a capacitor 88. The output circuit provides the benefits of isolation and voltage conversion, without the requirement of center tapping as is done in output circuits shown in Figure 3b and Figure 6. It should be appreciated that the topology of output circuit illustrated in Figure 8 can be independently utilised in many applications with full-wave rectification and isolation. It should further be appreciated that the switching circuit illustrated in Figure 3b is suitable for use with the embodiment illustrated in Figure 8.

Claims: A DC to DC converter comprising: an input voltage source (14); a capacitance (16) ; an output circuit; a switching circuit (12) for connecting the output alternatively across the voltage source and the capacitance; the output circuit further comprising primary inductor means (L1, L2; 82, 84) coupled in series with the switching circuit whereby to produce a bidirectional current flow through the inductor means on operation of the switching means, secondary inductor means providing electrical isolation from and inductively coupled to the primary inductor means, the secondary inductor means including series coupled inductors (82a, 84a), and first and second rectifiers (80,86) each having a first terminal coupled to one of the series connected inductors respectively and second terminal connected to a common point for producing full wave rectification of current flowing in the secondary inductor means characterised in that the primary inductor means includes first inductor means (82) and separate second inductor means (84) coupled in series to the switching circuit, and the secondary inductor means includes a third inductor means (82a) and a separate fourth inductor means (84a) coupled in series, the first and third, and the second and fourth inductor means forming respective separate inductive couplings. A converter according to claim 1 wherein the first (82) and second (84) inductor means are of substantially equal value. A converter according to claim 1 or 2 wherein the third (82a) and fourth (84a) inductor means are of substantially equal value. A converter according to any preceding claim wherein the switching circuit includes two electronic switching devices (Q1,Q2), the first switching device when closed connecting the output circuit across the input voltage source (14) and the second switching device when closed connects the output circuit across the capacitance (16). A converter according to claim 4 wherein said switching circuit switches said two switching devices (Q1, Q2) such that (a) said first switching device (Q1) is turned on while said second switching device (Q2) is off; (b) said first switching device is turned off and both said switching devices are off for a short dead-time interval; (c) said second switching device is turned on and said first switching device is off; (d) said second switching device is turned off and both said switching devices are off again for a short dead-time interval; and (e) the process is repeated periodically. A converter according to claim 5 further comprising capacitance (C S1 , C S2 ) in parallel with at least one of said switching devices, so that voltage across said switching device is virtually zero prior to turning on or off. A converter according to claim 6 wherein said capacitance in parallel with said switching devices comprise self-capacitance of said electronic switching devices. A converter according to any preceding claim wherein said inductor means have substantially low magnetizing inductance.

Inventors: COHEN ISAAC, COHEN, ISAAC
Applicants: LAMBDA ELECTRONICS INC, LAMBDA ELECTRONICS, INC.
Application year: 1992
Main classification: H02M3
IPC codes: H02M3, H02M7