Differential circuit implemented by bipolar transistors free from excess base-emitter reverse bias voltage

Abstract: A differential circuit comprises a differential stage (11) responsive to input voltage levels in an ECL range for producing an output signal at an output node (OUT11), a setting stage (12) associated with the differential stage (11) and responsive to a set signal (SET2) in a CMOS range for setting the output node (OUT11) to a predetermined level, wherein a level-shift element (14) is coupled between a bipolar transistor (Q23) responsive to the set signal (SET2) and the common emitter node (N11) of bipolar transistors (Q21;Q22) responsive to the input voltage levels so that each bipolar transistor is protected from damage due to excess reverse bias voltage being applied across the base node and the emitter node.

Description: This invention relates to a differential circuit and, more particularly, to a bipolar implementation. A standard differential circuit implemented by bipolar transistors is illustrated in Fig. 1, and comprises an n-p-n type bipolar transistor Q1 coupled between a power voltage source Vcc and a constant current source 1, and a series combination of a resistor R1 and an n-p-n type bipolar transistor Q2 coupled between the power voltage source Vcc and the constant current source 1. An input node IN1 is coupled with the base node of the n-p-n type bipolar transistor Q1, and a reference voltage level Vr is supplied to the base node of the n-p-n type bipolar transistor Q2. An input voltage signal for a CMOS circuit is supplied to the input node IN1, and is greater in amplitude than a signal for an ECL circuit. A voltage signal for a CMOS circuit varies its voltage level in a CMOS range, and a voltage signal for an ECL circuit varies its voltage level in an ECL range. The collector node of the n-p-n type bipolar transistor Q2 serves as an output node OUT1 of the differential circuit. The differential circuit thus arranged behaves as follows. If the input voltage signal at the input node IN1 is higher than the reference voltage level Vr, the n-p-n type bipolar transistor Q1 allows much current to flow therethrough, and the n-p-n type bipolar transistor Q2 decreases the amount of current passing therethrough. Then, voltage drop at the resistor R1 is decreased, and the output node OUT1 goes up. However, if the input voltage signal becomes lower than the reference voltage level Vr, the voltage level at the output node OUT1 is reduced. Turning to Fig. 2 of the drawings, the standard differential circuit shown in Fig. 1 is modified so that a differential voltage signal is applicable to a pair of input nodes IN2 and IN3. Input voltage levels at the input nodes IN2 and IN3 form the differential voltage signal, and are swung in the ECL range. The input voltage levels are respectively supplied from the pair of input nodes IN2 and IN3 to the base nodes of the n-p-n type bipolar transistors Q3 and Q4 and an output node OUT2 is provided between a resistor R2 and the n-p-n type bipolar transistor Q4. The differential circuit shown in Fig. 2 further has an n-p-n bipolar transistor Q5 coupled between the power voltage source Vcc and a constant current source 2, and a set node SET1 is coupled with the base node of the n-p-n type bipolar transistor Q5. A set signal is supplied to the set node SET1, and is variable in the CMOS range. While the set signal remains in the low voltage level, the n-p-n type bipolar transistor Q5 is turned off, and the differential circuit is responsive to the differential voltage signal. However, if the set signal goes up to the high voltage level, the n-p-n type bipolar transistor Q5 turns on, and a large amount of current flows through the n-p-n type bipolar transistor Q5. This results in drastic decrease in the amount of current passing through the resistor R2 regardless of the differential voltage signal, and the output node OUT2 is forcibly elevated to a set level or the high voltage level. However, a problem is encountered in the prior art differential circuits shown in Figs. 1 and 2 in that the n-p-n type bipolar transistors Q1/ Q2 and Q3/ Q4 tend to be destroyed due to reverse bias voltage level between the emitter node and the base node. In detail, when the input voltage level at the input node IN1 is reduced to zero, the voltage level at a node N1 is elevated with the current passing through the n-p-n type bipolar transistor Q2, and the voltage level at the node N1 causes large reverse bias voltage to be applied between the base node and the emitter node of the n-p-n type bipolar transistor Q1. The large reverse bias voltage may destroy the n-p-n type bipolar transistor Q1. If the reference voltage level Vr is lowered, the n-p-n type bipolar transistor Q2 suppresses the voltage level at the node N1, and the n-p-n type bipolar transistor Q1 is not significantly damaged in the presence of zero volt at the input node N1. However, when the input node IN1 goes up to the high voltage level, the n-p-n type bipolar transistor Q1 allows the node N1 to go up, and large reverse bias voltage is applied between the emitter node and the base node of the n-p-n type bipolar transistor Q2. Therefore, the n-p-n type bipolar transistor Q2 is more liable to be destroyed instead of the n-p-n type bipolar transistor Q1. Since the set signal voltage level varies in the CMOS range, the differential circuit shown in Fig. 2 encounters the similar problem. Namely, if the set signal goes down to zero volt, a large reverse bias voltage is applied between the emitter node and the base node of the n-p-n type bipolar transistor Q5. To preserve the n-p-n type bipolar transistor Q5, the differential voltage signal or the voltage levels at the input nodes IN2 and IN3 may be lowered. However, the large reverse bias voltage is applied to one of the n-p-n type bipolar transistors Q3 and Q4 when the n-p-n type bipolar transistor Q5 turns on. If the n-p-n type bipolar transistors Q1 to Q5 are scaled up, damage is reduced. However, scaled-up component transistors are not desirable for an electric circuit, especially, for designing such an electrical circuit in a semiconductor integrated circuit. In order to overcome the problem inherent in the prior art differential circuits shown in Figs. 1 and 2, differential circuits shown in Figs. 3 and 4 are proposed. The differential circuit shown in Fig. 3 is disclosed in Japanese Patent Application laid-open (Kokai) No. 59-205825, and comprises a first series combination of a resistor R3 and two n-p-n type bipolar transistors Q6 and Q7 coupled between a power voltage source Vcc and a constant current source 3, and a second series combination of a resistor R4 and two n-p-n type bipolar transistors Q8 and Q9 coupled in parallel to the first series combination. An input node IN4 is coupled with the base node of the n-p-n type bipolar transistor Q6, and a reference voltage Vr is supplied to the base node of the n-p-n type bipolar transistor Q8. For this reason, the differential circuit shown in Fig. 3 basically behaves as similar to the differential circuit shown in Fig. 1 with an input signal in the CMOS range applied to the input node IN4, and converts the input signal in the CMOS range to an output signal of the ECL range at an output node OUT3. However, the n-p-n type bipolar transistors Q7 and Q9 are of the diode-connected transistor, and cause the emitter nodes of the n-p-n type bipolar transistors Q6 and Q8 to be higher in voltage level than a node N2 by the emitter-base forward bias voltage levels of the diode-connected n-p-n type bipolar transistors Q7 and Q9, respectively. This results in small reverse bias voltage between the emitter node and the base node of the n-p-n type bipolar transistor Q6 or Q8 under application of the input voltage signal of zero volt to the input node IN4 or application of lowered reference voltage level Vr to the base node of the n-p-n type bipolar transistor Q8. In other words, the n-p-n type bipolar transistors Q6 and Q8 are less liable to be damaged. The differential circuit shown in Fig. 4 is disclosed in Japanese Patent Application laid-open (Kokai) No. 59-12626, and comprises a first series combination of a resistor R5 and an n-p-n type bipolar transistor Q10 coupled between a power voltage source Vcc and a constant current source 4 and a second series combination of a resistor R6 and an n-p-n type bipolar transistor Q11 coupled in parallel to the first series combination. An input node IN5 is coupled through a resistor R7 to the base node of the n-p-n type bipolar transistor Q10, and another input node IN6 is directly coupled with the base node of the n-p-n type bipolar transistor Q11. Input voltage levels at the input nodes IN5 and IN6 form a differential voltage signal, and the input voltage level at the input node IN5 is swung in the CMOS range. The differential circuit shown in Fig. 4 also converts the input voltage signal at the input node IN5 to an output voltage signal in the ECL range at an output node OUT4. In order to preserve the n-p-n type bipolar transistor Q10 from damage, an n-p-n type bipolar transistor Q12 is coupled between the power voltage source and the base node of the n-p-n type bipolar transistor Q10. Since the emitter node of the n-p-n type bipolar transistor Q10 is coupled with the base node of the n-p-n type bipolar transistor Q12, the n-p-n type bipolar transistor Q12 turns on in the presence of the input voltage level of zero volt at the input node IN5. In other words, the voltage level at a node N3 allows a forward bias voltage to take place between the base node and the emitter node of the n-p-n type bipolar transistor Q12, and the n-p-n type bipolar transistor Q12 turns on. The power voltage level is supplied from the source Vcc through the n-p-n type bipolar transistor Q12 to the base node of the n-p-n type bipolar transistor Q10. Then, the reverse bias voltage is eliminated from the n-p-n type bipolar transistor Q10, and the forward bias voltage between the base node and the emitter node of the n-p-n type bipolar transistor Q10 is approximately equal to the forward bias voltage between the base node and the emitter node of the n-p-n type bipolar transistor Q12. Thus, the differential circuits shown in Figs. 3 and 4 are free from the problem inherent in the differential circuits shown in Figs. 1 and 2. However, the differential circuits shown in Figs. 3 and 4 merely convert the input voltage signals in the CMOS into the output signals in the ECL range, and can not forcibly set the output nodes OUT3 and OUT4 to high voltage level regardless of the input voltage levels. The setting function is desirable for a complex electric circuit. Moreover, the differential circuits shown in Figs. 3 and 4 can not achieve any logical operation, and, accordingly, the differential circuits shown in Figs. 3 and 4 require logic gates coupled with the output nodes OUT3 and OUT4 for logical operations. However, the logic circuits increase component transistors, and the electric circuit is liable to be enlarged. EP-A-95929 discloses an ECL circuit in which an output can be set by applying an ECL voltage to a set input. It does not disclose how to prevent damage if a voltage of CMOS levels is applied to the set input. It is an object of the present invention to provide a differential circuit which can forcibly set an output node thereof at a predetermined level without damaging component bipolar transistors. To accomplish the object, the present invention proposes to associate a set-transistor with a differential stage through a level-shift means. In accordance with the present invention, there is provided a differential circuit comprising: a. first and second input nodes adapted to receive first and second input voltages variable in an ECL range; b. a differential stage having a first bipolar transistor coupled between a first voltage level and a common node, a first series combination of a resistor and a second bipolar transistor coupled between said first source of voltage level and said common node, and a constant current source associated with said first bipolar transistor and the first series combination and coupled with a second voltage level different from said first voltage level, said first and second input voltage levels being supplied to the base nodes of said first and second bipolar transistors, respectively; c. an output node provided between said resistor and said second bipolar transistor; and d. a setting stage provided in association with said differential stage, and responsive to a set signal for setting said output node to a predetermined voltage level, wherein said setting stage has a third bipolar transistor responsive to said set signal, and characterised by level shift means coupled between said common node and said constant current source and by the third transistor being connected between said first voltage level and a node between said constant current source and said level-shift means and being responsive to a set signal variable in a CMOS range. Said differential stage may have a fourth bipolar transistor coupled between said first voltage level and said common node, a third input voltage level in said ECL range being supplied from a third input node to the base node of said fourth bipolar transistor so that said differential stage achieves a logical operation on said one of said first and second input voltage signals and said third input voltage signal. Preferably said level shift means is implemented by a series combination of diode-connected bipolar transistors. The features and advantages of the differential circuits according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram showing the arrangement of the prior art differential circuit; Fig. 2 is a circuit diagram showing the arrangement of another prior art differential circuit; Fig. 3 is a circuit diagram showing the arrangement of yet another prior art differential circuit; Fig. 4 is a circuit diagram showing the arrangement of still another prior art differential circuit; Fig. 5 is a circuit diagram showing the arrangement of another differential circuit according to the present invention; Fig. 6 is a circuit diagram showing the arrangement of a modification of the differential circuit shown in Fig. 5; and Fig.7 is a graph showing voltage levels at essential nodes of the modification in terms of a set signal. Turning to Fig.5 of the drawings, a differential circuit embodying the present invention largely comprises a differential stage 21 and a setting stage 22. The differential stage 21 comprises a first n-p-n type bipolar transistor Q31 coupled between a power voltage source Vcc and a common node N21, a first series combination of a resistor R21 and a second n-p-n type bipolar transistor Q32 and a constant current source 23 associated with the first n-p-n type bipolar transistor Q31 and the first series combination and coupled with a ground node GND, and a pair of input nodes IN14 and IN15 are respectively coupled with the base nodes of the first and second n-p-n type bipolar transistors Q31 and Q32. Input voltage signals swung in the ECL range are supplied from the pair of input nodes IN14 and IN15 to the first and second n-p-n type bipolar transistors Q31 and Q32. An output node OUT12 is provided between the resistor R21 and the second n-p-n type bipolar transistor Q32. The setting stage 22 comprises a third n-p-n type bipolar transistor Q33 coupled between the power voltage source Vcc and the constant current source 23, and a level-shift circuit 16 coupled between the common node N21 and the constant current source 23, and a set signal in the CMOS range is supplied from a set node SET3 to the base node of the third n-p-n type bipolar transistor Q33. The differential circuit thus arranged behaves as follows. While the set signal remains in zero volt, the third n-p-n type bipolar transistor Q33 is turned off, and the differential stage 21 is responsive to the input voltage signals at the pair of input nodes IN14 and IN15. If the input voltage signal at the input node IN14 is higher than the input voltage signal at the other input node IN15, the first n-p-n type bipolar transistor Q31 increases current passing therethrough, and, accordingly, the second n-p-n type bipolar transistor Q32 decreases current passing therethrough. The current thus decreased allows the resistor R21 to reduce the voltage drop, and the output voltage signal at the output node OUT12 is raised. On the other hand, if the input voltage signal at the input node IN14 is lower than the input voltage signal at the other input node IN15 the differential stage 21 lowers the output voltage signal at the output node OUT12. Thus, the differential operation is achieved by the differential stage 21 in so far as the set signal remains in zero volt. Since the level-shift circuit 16 is inserted between the common node N21 and the emitter node of the third n-p-n type bipolar transistor Q33, only small reverse bias voltages are applied between the base node and the emitter node of the third n-p-n type bipolar transistor Q33, and the third n-p-n type bipolar transistor Q33 is hardly damaged. If the set signal SET3 goes up to the high voltage level, the third n-p-n type bipolar transistor Q33 turns on, and only a negligible amount of current flows through the series combination of the resistor R21 and the second n-p-n type bipolar transistor Q32. The output node OUT12 is forcibly raised regardless of the input voltage signal at the input node IN14. Thus, the differential circuit can also set the output node OUT12 to the high voltage level. As described hereinbefore, the reverse bias voltage is relatively small, and it is unnecessary to lower the input voltage signals at the pair of input nodes IN14 and IN15. Therefore, positive voltage level supplied from the third n-p-n type bipolar transistor Q33 merely produces small reverse bias voltage between the base node and the emitter node of the n-p-n type bipolar transistor Q31 or Q32 supplied with lower input voltage signal, and the n-p-n bipolar transistors Q31 and Q32 are hardly damaged. The differential circuit implementing the second embodiment can be modified as shown in Fig.6. The modification can carry out an OR operation, and a fourth n-p-n type bipolar transistor Q34 is further coupled between the power voltage source Vcc and the common node N21. An input voltage signal in the ECL range is supplied from an input node IN16 to the base node of the fourth n-p-n type bipolar transistor Q34. However, the other circuit components are similar to those of the differential circuit shown in Fig. 5, and the corresponding circuit components are designated by the same references used in Fig. 5 without detailed description. In this modification, a level-shift circuit 17 is implemented by a series combination of diode-connected n-p-n type bipolar transistors Q35 and Q36. A reference voltage Vr is supplied to the base node of the second n-p-n type bipolar transistor Q32, and the first to third n-p-n type bipolar transistors Q31, Q32 and Q34 carry out an OR operation on the input voltage signals at the input nodes IN14 and IN16. Namely, if at least one of the input voltage signals at the input node N14 or N16 becomes higher than the reference voltage level Vr at the input node N15, the associated n-p-n type bipolar transistor Q31 or Q34 increases the current passing therethrough, and the second n-p-n type bipolar transistor Q32 decreases the current passing through the resistor R21. Then, the output node OUT12 is raised to the high voltage level. However, if both input nodes IN14 and IN16 remain low, the second n-p-n type bipolar transistor Q32 increases the current passing- through the resistor R21, and the output voltage level at the output node OUT12 is lowered. The advantages of the differential circuit shown in Fig.5 are also achieved by the modification. Fig.7 shows the voltage level at a node N22 in terms of the voltage level of the set signal SET3. The input nodes IN14 and IN16 are fixed to the ground voltage level or other low constant voltage level, and the set signal is increased in voltage level from zero volts to five volts or the Vcc level. Plots S stands for the set signal. The node N22 is initially constant, and is, then, increased in voltage level together with the set signal as shown in plots N22, and reverse bias voltage Veb of about 1.6 volts is applied between the base node and the emitter node of the fourth n-p-n type bipolar transistor Q33. Therefore, the fourth n-p-n type bipolar transistor Q33 is not damaged. Thus, the level-shift circuit 17 or the diode-connected n-p-n type bipolar transistors Q35 and Q36 canprevent the fourth n-p-n type bipolar transistor Q33 from damage. Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the present invention. For example, the differential circuit and the modification may be fabricated from p-n-p type bipolar transistors.

Claims: A differential circuit comprising: a. first and second input nodes (IN14/IN15) adapted to receive first and second input voltages variable in an ECL range; b. a differential stage (21) having a first bipolar transistor (Q31) coupled between a first voltage level (Vcc) and a common node (N21), a first series combination of a resistor (R21) and a second bipolar transistor (Q32) coupled between said first source of voltage level and said common node, and a constant current source (23) associated with said first bipolar transistor and the first series combination and coupled with a second voltage level (GND) different from said first voltage level, said first and second voltage levels being supplied to the base nodes of said first and second bipolar transistors, respectively; c. an output node (OUT12) provided between said resistor and said second bipolar transistor; and d. a setting stage (22) provided in association with said differential stage, and responsive to a set signal for setting said output node to a predetermined voltage level, wherein said setting stage has a third bipolar transistor (Q33) responsive to said set signal, characterised by level shift means (16) coupled between said common node (N21) and said constant current source (23) and by the third transistor being connected between said first voltage level and a node between said constant current source and said level-shift means and being responsive to said set signal, said set signal being variable in a CMOS range. A differential circuit as set forth in Claim 1, in which said differential stage further has a fourth bipolar transistor (Q23, Q34) coupled between said first voltage level and said common node, a third input node (IN16) to the base node of said fourth bipolar transistor so that said differential stage achieves a logical operation on said one of said first and second input voltage signals and said third input voltage signal. A differential circuit as set forth in any preceding claim, in which said level-shift means is implemented by a series combination of diode-connected bipolar transistors (Q35, Q36).

Inventors: ASAZAWA HIROSHI, ASAZAWA, HIROSHI, ASAZAWA, HIROSHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H03K19
IPC codes: H03K19