Turn-on control circuit for electric devices

Abstract: A circuit (2) comprising a comparator (15) supplied with a turn-on voltage (V ST ) increasing gradually during the turn-on phase of a device (1) for protection. When the control voltage reaches a predetermined value (V₁), the comparator (15) supplies a diagnostic enabling signal (V o1 ) to a diagnostic stage (6, 8), which, in the event an undesired condition is detected at the output (7) of the device (1), supplies a clamp enabling signal to the control terminal of a clamping transistor (23) located between the input (19) of the circuit and ground, and which, when enabled, prevents the turn-on voltage (V ST ) from increasing further, and so prevents the device (1) from being turned on.

Description: The present invention relates to a turn-on control circuit for devices, in particular power devices, having a circuit for detecting error, fault or otherwise undesired conditions. The present invention is particularly suitable for devices, such as described in EP-A-0 368 528, having an input supplied with an electric quantity, which, when the device is turned on, switches gradually from a first to a second steady-state value, such as those with a standby input (to which the following description refers purely by way of example), which are designed to switch from a standby state wherein the voltage at the standby input is low, to an operating (play) state. Typical devices of this sort are audio amplifiers to which the following description refers. In audio amplifiers, errors or faults may occur at times in the connections between the amplifier outputs and the load (loudspeakers). For example, the output may be grounded or connected to the supply line due to an insulation fault in the cable supplying the signal to the load; the load may be disconnected due to an interruption in the signal supply cable; or metal fragments on the printed circuit on which the connections are made may result in shortcircuiting of the outputs or of points of different potential. When such faults occur prior to turning on the amplifier, this may supply or absorb an excessive amount of current which may damage the amplifier when it is turned on. It is an object of the present invention to provide a circuit designed to overcome the above problem by preventing the controlled device from assuming anomalous or indeed dangerous conditions, and which, more specifically, provides for detecting faults prior to turn-on of the device, and for preventing the device from being turned on as long as such faults persist. According to the present invention, there is provided a device turn-on control circuit as claimed in Claim 1 or Claim 2. In other words, according to the present invention, upon detection of a potentially dangerous condition or at any rate such as to result in undesired consequences (hereinafter referred to as faults), a clamping element connected to the input of the circuit is activated for preventing any further increase in input voltage and so preventing the device from being turned on. The system according to the present invention is particularly suitable for amplifiers connected permanently to the supply, such as those with a standby input compatible with CMOS logic levels. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Fig.1 shows a block diagram of a first embodiment of the circuit according to the present invention; Fig.2 shows a block diagram of a first variation of the circuit according to the present invention; Fig.3 shows a block diagram of a second variation of the circuit according to the present invention; Fig.4 shows a circuit diagram implementing the Fig.1 block diagram. Number 1 in Fig.1 indicates the device to be protected (in this case, an audio amplifier), and number 2 the turn-on control circuit. Device 1 presents an enabling input 3 (EN) connected to the output of a DEVICE ENABLING block 4 containing all the voltage and current sources necessary for operation of device 1; an input 5 connected to the output of a DIAGNOSTIC ENABLING block 6 containing all the voltage and current sources required for pre-turn-on diagnosis; and an output 7 (of n lines) connected to the input of a FAULT DETECTING block 8 for detecting any undesired conditions which may result in faulty operation of device 1. Fault detecting block 8 (which, together with diagnostic enabling block 6, forms a fault detecting stage) presents an output 9 to which any information relative to the presence of undesired conditions is supplied, and which is connected to a number m of lines 10 (one for each possible malfunctioning condition) having a buffer circuit 11. Circuit 2 also comprises three comparators 15, 16, 17 having their positive inputs connected (via resistor 18) to a standby input 19 supplied with standby voltage V ST , and their negative inputs connected to respective reference potentials V₁, V₂, V₃, where V₁ < V₂ < V₃. The output of comparator 15 (potential V o1 ) is connected to the enabling input of diagnostic enabling block 6 and to one terminal of a controlled switch 20, the control terminal of which is connected to one output of fault detecting block 8, and the other terminal of which is connected via resistor 21 to the collector of an NPN type transistor 22 (defining a disabling element) having its base connected to the output of comparator 16 (potential V o2 ) and its emitter grounded (reference potential). The collector of transistor 22 is also connected to the base of a second NPN type transistor 23 (defining a clamping element) having its emitter grounded and its collector connected to the common node 24 of the positive inputs of comparators 15-17. Between node 24 and ground, provision is made for a capacitor 25 defining a low-pass filter with resistor 18. The output of comparator 17 (potential V o3 ) is connected to the enabling input of device enabling block 4; and a third NPN type transistor 27 (defining a diagnostic disabling element) presents its collector connected to the output of comparator 15, its base connected to the output of device enabling block 4, and its emitter grounded. With the exception of low-pass filter 18, 25, control circuit 2 is preferably integrated on the same chip as device 1. The Fig.1 circuit operates as follows. The potential V ST controls the operating state of the device (low = off, high = on), is lower than V₁, V₂, V₃ before turning on the device, and increases gradually to a value greater than V₃ after the device is turned on. Before the device is turned on, when V ST = 0, the outputs of comparators 15-17 are zero, and blocks 4, 6 and 8 are off. In the absence of undesired conditions ("faults"), the increase in V ST presents the following phases: 1) V ST < V 1 In this phase, by virtue of the low output of comparators 15-17, blocks 4, 6 and 8 and device 1 remain off, and no external signal is supplied over lines 10. 2) V 1 < V ST < V 2 In this phase, output potential V o1 of comparator 15 is high, thus enabling diagnostic enabling block 6, for determining the presence of any error conditions; V o2 is low, so that transistor 22 remains off; and V o3 is also low, so that device enabling block 4 is disabled and device 1 remains off. If no error condition is detected, the output of fault detecting block 8 remains low, so that controlled switch 20 remains open, transistor 23 remains off, and voltage V ST continues increasing normally. Conversely, in the event of an error condition being detected, the output of fault detecting block 8 switches to high, so as to supply an error output signal over line 10 and close switch 20; and transistor 23 is turned on, thus closing a negative feedback loop also comprising comparator 15 and resistor 21, and so preventing voltage V ST from increasing further. The stability of the feedback loop is guaranteed by capacitor 25. Consequently, as long as the error condition detected by block 8 persists, V ST is maintained low and prevented from reaching thresholds V₂, V₃ by transistor 23, so that the feedback loop remains on, and block 4 and device 1 remain off. 3) V 2 < V ST < V 3 This phase depends on no error condition being detected or, conversely, on the error being eliminated beforehand, in which case, the output of comparator 16 switches to high, thus turning on and saturating transistor 22, and transistor 23 remains off, thus preventing voltage V ST from being clamped under normal operating conditions and so enabling it to increase to the steady-state value. 4) V 3 < V ST When this applies, the output of comparator 17 switches so as to enable device enabling block 4 and turn on the sources of device 1 and, consequently, device 1 itself. When enabled, block 4 also turns on transistor 27, which grounds the output of comparator 15, thus disabling the diagnostic system (blocks 6, 8), so that device 1 operates normally. Fig.2 shows a variation 2' of circuit 2 in Fig.1. Circuit 2' is similar to that of Fig.1, and again comprises three comparators 15', 16', 17' supplying respective output potentials V o1' , V o2' , V o3' ; blocks 4, 6, 8; transistors 22, 23, 27; switch 20; and capacitor 25. The only difference as compared with circuit 2 lies in the connection of the outputs of comparators 16' and 17' to switch 20 and transistor 22, and more specifically in the fact that, instead of controlling the base of transistor 21, the output of comparator 16' is connected to one terminal of switch 20 (the other terminal of which is again connected to resistor 21); while the base of transistor 22 is connected directly to the output of comparator 17' over line 30. Like comparator 15 in Fig.1, comparator 15' in circuit 2' provides for enabling the diagnostic functions by enabling block 6 as soon as voltage V ST exceeds V₁. In the event of a fault being detected by block 8, this closes switch 20 while still allowing voltage V ST to reach V₂ by virtue of the fact that, previous to V₂, the output of comparator 16' is still low, and transistor 23 remains off. Conversely, in the event of a fault being detected, as soon as V ST ≥ V₂, the output of comparator 16' switches to high, thus turning on transistor 23 and preventing any further increase in V ST as long as the fault persists; and switch 20 is maintained closed by the output of fault detecting block 8. In the absence of or following removal of any fault, as V ST exceeds V₃, the output of comparator 17' also switches, which, in addition to enabling device enabling block 4, also turns on transistor 22 so as to disable the voltage clamping loop, after which, transistor 27 again provides for disabling operation of the diagnostic system. The Fig.2 variation is ideal in situations in which the enabling phase of diagnostic enabling block 6 may result in spurious output signals being supplied to fault detecting block 8, thus turning on transistor 23 and so preventing device 1 from being turned on even in the absence of a fault at outputs 7. This possibility is prevented by circuit 2' by virtue of V ST only being clamped when V ST > V₂, i.e. when diagnostic enabling block 6 is fully operative and therefore no longer in any condition to produce spurious output signals. Fig.3 shows a further variation 2" of the turn-on control circuit similar to that of Fig.1 and comprising blocks 4, 6, 8 and transistors 22, 23, 27. In this case, however, provision is made for two comparators 15" and 17" having the negative inputs connected to respective threshold potentials V₁ and V₃, and supplying respective output potentials V o1'' and V o3'' ; the terminal of switch 20 not connected to resistor 21 is connected directly to the output of comparator 15''; and the base of transistor 22 is connected directly to the output of comparator 17'' over line 30. The remainder of circuit 2'' is identical to that of Fig.s 1 and 2. In the event of a fault being detected by block 8, input voltage V ST in the Fig.3 circuit is clamped immediately, and the feedback loop is disabled by comparator 17'' as soon as device 1 is turned on. Circuit 2'' is thus extremely straightforward in design, and suitable for situations in which no danger exists of spurious signals being supplied when diagnostic enabling block 4 is turned on or during the final phase in the increase of input voltage V ST . Fig.4 shows a circuit diagram implementing the Fig.1 block diagram. Fig.4 shows resistor 18 between input 19 and node 24; capacitor 25 between node 24 and ground; and transistor 23 having the collector connected to node 24, the emitter grounded, and the base connected via resistor 21 to the output of a range comparator 40 implementing fault detecting block 8 and switch 20. Range comparator 40 presents two inputs 41, 42 set to respective threshold potentials V₄, V₅, where V₄ < V₅; and a third input connected to output 7 of device 1. In the example shown, output 7 coincides with input 5 of device 1, and is connected to the output of diagnostic enabling block 6 via a resistor 43. Block 6 implements, among other things, a reference voltage source, wherein V REF < V CC . The Fig.4 circuit also comprises a band-gap voltage source stage 44 including a pair of NPN type transistors 45, 46 having respective emitter areas A₁ and A₂, where A₁ > A₂. The base terminals of transistors 45, 46 are connected to each other and to node 24; the emitter terminal of transistor 46 is grounded via resistor 47; the emitter terminal of transistor 45 is connected to that of transistor 46 via a second resistor 48 (of resistance R₁); the collector terminal of transistor 45 is connected to the cathode of a diode 49 having its anode connected to a supply line 50 set to potential V CC ; and the collector terminal of transistor 46 is connected to that of a PNP type transistor 51 having its emitter connected to line 50, and its base connected to the cathode of diode 49. The collector terminal of transistor 51 is also connected to the base terminal of a diode-connected PNP type transistor 53 having its collector shortcircuited to the base, and its emitter terminal connected to line 50. The collector terminal of transistor 51 is also connected to the base terminals of three PNP type transistors 54, 55, 56, each forming a respective current mirror circuit with transistor 53. Transistors 54, 55 and 56 present emitter terminals connected to line 50, and collector terminals connected to the base terminals of respective NPN type transistors 58, 59, 60, the emitter terminals of which are grounded. Between the base terminals of transistors 58, 59, 60 and ground, there are provided respective resistors 61, 62, 63 having respective resistances R₂, R₃, R₄, where R₂ > R₃ > R₄. The collector terminal of transistor 58 (forming comparator 15 together with transistor 54 and resistor 61) is connected to the enabling input of diagnostic enabling block 6 and range comparator 40; the collector terminal of transistor 59 (forming comparator 16 together with transistor 55 and resistor 62) is connected to the input of a current mirror circuit 65 including a diode 66 (having its anode connected to line 50 and its cathode to the collector of transistor 59) and a PNP type transistor 67 (connected by the emitter terminal to line 50, by the base terminal to the cathode of diode 66, and by the collector terminal to the base terminal of transistor 22); and the collector terminal of transistor 60 (forming comparator 17 together with transistor 56 and resistor 63) is connected to the enabling input of device enabling block 4. The Fig.4 circuit operates as follows. Band-gap source 44 starts supplying diode-connected transistor 53 when input voltage V ST is such that voltage V R1 at the terminals of resistor 44 equals: V R1 = 0.026 mV ln (A 1 /A 2 ) After this value, diode 53 is supplied with current equal to the difference between the currents in components 49 and 51 (collector currents of transistors 45 and 46) which in turn are related in known manner to input voltage V ST . Consequently, as input voltage V ST increases, the drive current of transistor 53 and thus current I through the transistor also increases, which current I is mirrored in transistors 54, 55 and 56 and supplied to resistors 61, 62 and 63, thus causing a voltage drop at the base-emitter junction of respective transistors 58-60. Transistors 58-60 are turned on as soon as the voltage drop at the respective base-emitter junction reaches roughly 0.7 V. Therefore, by virtue of R₂ > R₃ > R₄, the increase in V ST first turns on transistor 58 followed by transistor 59 and, finally, transistor 60. As soon as it is turned on, transistor 58 generates a collector voltage V o1 capable of enabling the voltage source implemented by block 6 and range comparator 40, so that block 6 supplies reference output voltage V REF to terminal 5, 7 of device 1, which in this phase is in a tri-state condition. If terminal 5, 7 is is not grounded or switched to V CC , it therefore switches to V REF , so that comparator 40 presents a low output, transistor 23 remains off, and voltage V ST may continue rising until it reaches the value at which transistor 59 is turned on, thus turning on current mirror 65 and transistor 22, and preventing transistor 23 from being turned on even when, under normal operating conditions of device 1, the voltage at output 5, 7 exceeds V₅ or falls below V₄. As V ST continues rising, transistor 60 is also turned on, which enables block 4 for turning on device 1. Though not shown, in this case also, the collector terminal of transistor 60 may obviously drive transistor 27 for disabling diagnostic enabling block 6. Conversely, if output 5, 7 of device 1 switches to 0 V or V CC when transistor 58 and diagnostic enabling block 6 are turned on, the output of range comparator 40 switches to high, thus turning on transistor 23, which clamps voltage V ST at node 24 to an intermediate value lower than that at which transistors 59 and 60 are turned on, and the circuit is maintained in this condition until the fault causing the output to be grounded or switched to V CC is rectified. The advantages of the circuit according to the present invention will be clear from the foregoing description. In particular, it provides for preventing the device from being turned on under potentially dangerous conditions, even if no other protection is provided for. Moreover, it is straightforward in design; provides for troublefree application at the design stage to devices with standby inputs, particularly amplifiers, which, for practically all TV, car radio and home HI-FI applications, present a standby function; and can be adapted to cater to any hazardous or at any rate undesired condition by simply designing the diagnostic enabling and fault detecting blocks accordingly. The circuit may also be employed for supplying diagnostic signals to the user (person or control microprocessor) and so enabling any problems detected to be eliminated by the user. This is particularly useful when assembling the equipment featuring the controlled device (e.g. audio amplifier) for enabling any faulty connections to be detected and rectified prior to sale. The circuit provides for supplying simple output information (e.g. the signal produced by one or more open-collector type outputs) or complex information (e.g. via a serial or parallel bus), and requires no particular processing speed on the part of the user, by virtue of the device remaining protected as long as the fault persists. Moreover, once the fault is rectified, the turn-on sequence continues automatically, with no need for restarting or resetting the turn-on voltage. The circuit according to the present invention is also compatible with any diagnostic system operating during normal operation of the amplifier, even using the same fault detecting block and the same output buffer. To those skilled in the art it will be clear that changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention as defined in the appended claims. For example, as already stated, the diagnostic enabling and fault detecting blocks may be of different types; the device to be protected may be an audio amplifier, a less complex stage, or even a more complex unit; the circuit may be integrated with the device or formed separately; and, as opposed to the different sizing of resistors 61-63, transistors 58-60 in the Fig.4 circuit may be turned on sequentially by providing drive transistors 54-56 with different emitter area ratios so that they are turned on by different base currents.

Claims: A circuit (2; 2'; 2") for turn-on control of a device (1) requiring protection against undesired conditions, said device (1) being connectable to a turn-on input (19) supplied with an electric turn-on control quantity (V ST ) varying in value during turn-on, said device (1) being such that it is not turned-on before said electric quantity (V ST ) reaches a predetermined value (V₃), and also to a fault detecting stage (6, 8) for generating a fault signal in the event an undesired condition is detected in the device (1); characterized by the fact that it comprises: first comparing means (15; 15'; 15") having an input (24) connectable to said turn-on input (19), and an output connectable to said fault detecting stage (6, 8), said first comparing means generating a signal (V o1 ; V o1' ; V o1'' ) enabling operation of said fault detecting stage (6,8) when said electric quantity (V ST ) reaches a first value (V₁); a clamping element (23) having an enabling terminal supplied with a clamp enabling signal, and a clamping terminal connectable to said input (24) of said first comparing means, for preventing said electric quantity (V ST ) from varying and reaching said predetermined value (V₃) in the presence of said clamp enabling signal; and circuit means (20, 21) connectable to said fault detecting stage (6, 8) and connected to said terminal enabling said clamping element (23), said circuit means generating said clamp enabling signal in the presence of said fault signal. A circuit (2; 2'; 2") for turn-on control of a device (1) requiring protection against undesired conditions, said circuit comprising: a turn-on input (19) supplied with an electric turn-on control quantity (V ST ) varying in value during turn-on, said device (1) being such that it is not turned-on before said electric quantity (V ST ) reaches a predetermined value (V₃); and a fault detecting stage (6, 8) for generating a fault signal in the event an undesired condition is detected in the device (1); characterized by the fact that it comprises first comparing means (15; 15'; 15") having an input (24) connected to said turn-on input (19), and an output connected to said fault detecting stage (6, 8), said first comparing means generating a signal (V o1 ; V o1' ;V o1'' ) enabling operation of said fault detecting stage (6,8) when said electric quantity (V ST ) reaches a first value (V₁); a clamping element (23) having an enabling terminal supplied with a clamp enabling signal, and a clamping terminal connectable to said input (24) of said first comparing means (15; 15'; 15''), for preventing said electric quantity (V ST ) from varying and reaching said predetermined value (V₃) in the presence of said clamp enabling signal; and circuit means (20, 21) connected to said fault detecting stage and said terminal enabling said clamping element (23), for generating said clamp enabling signal in the presence of said fault signal. A circuit as claimed in Claim 1 or 2, characterized by the fact that said electric quantity is a voltage (V ST ) increasing gradually during turn-on. A circuit as claimed in Claim 3, characterized by the fact that it comprises comparing means (16; 16'; 17'') having an input connected to said turn-on input (19), and an output generating a signal (V o2 ; V o2' ; V o3'' ) when said voltage (V ST ) presents a second value (V₂; V₃) higher than said first value (V₁); by the fact that said circuit means (20, 21) are connected to the output of one (15; 15"; 16') of said first comparing means (15; 15'; 15") and said comparing means (16; 16'; 17''); and by the fact that said clamping element (23) defines a negative feedback path between said turn-on input (19) and said output of one (15; 15''; 16') of said first comparing means (15; 15'; 15'') and said comparing means (16; 16'; 17''). A circuit as claimed in Claim 3 or 4, characterized by the fact that said clamping element is a transistor (23) having a first terminal connected to said turn-on input (19), a second terminal connected to a reference potential line such as ground, and a control terminal connected to said circuit means (20, 21). A circuit as claimed in one of the foregoing Claims from 3 to 5, characterized by the fact that said circuit means (20, 21) comprise a switch (20) located between said output of said first comparing means (15; 15") and said enabling terminal of said clamping element (23), and having a control terminal connected to said fault detecting stage (6, 8). A circuit as claimed in Claim 6, characterized by the fact that it comprises second comparing means (16; 17") having an input connected to said turn-on input (19), and an output generating a clamp disabling signal (V o2 ; V o3'' ) when said voltage (V ST ) reaches a second value (V₂; V₃) higher than said first value (V₁); and a disabling element (22) having a control terminal connected to said output of said second comparing means (16; 17''), and a terminal connected to said enabling terminal of said clamping element (23), for generating a signal disabling said clamping element in the presence of said clamp disabling signal (V o2 ; V o3'' ). A circuit as claimed in Claim 7, characterized by the fact that said disabling element comprises a bipolar transistor (22) having its base terminal connected to said output of said second comparing means (16; 17''). A circuit as claimed in Claim 7 or 8, characterized by the fact that said output of said second comparing means (17'') is also connected to a device enabling stage (4) having an output connected to said device (1). A circuit as claimed in Claim 7 or 8, characterized by the fact that it comprises third comparing means (17) having an input connected to said turn-on input (19) and an output, and generating a device enabling signal (V o3 ) when said voltage (V ST ) presents a third value (V₃) higher than said second value (V₂); and by the fact that it comprises a device enabling stage (4) having an input connected to said output of said third comparing means (17), and an output connected to said device (1). A circuit as claimed in Claim 9 or 10, characterized by the fact that it comprises a diagnostic disabling element (27) connected to said fault detecting stage (6, 8) and having a control terminal connected to said output of said device enabling stage (4). A circuit as claimed in Claim 11, characterized by the fact that said diagnostic disabling element comprises a transistor (27) having a first and a second terminal connected to said fault detecting stage (6, 8) and to a reference potential line such as ground. A circuit as claimed in one of the foregoing Claims from 3 to 5, characterized by the fact that it comprises: second comparing means (16') having an input connected to said turn-on input (19), and an output connected to said circuit means (20, 21) for generating said clamp enabling signal (V o2' ) when said voltage (V ST ) presents a second value (V₂) higher than said first value (V₁); third comparing means (17') having an input connected to said turn-on input, and an output connected to a device enabling stage (4), for generating a clamp disabling signal (V o3' ) when said input voltage presents a third value (V₃) higher than said second value; a disabling element (22) having a control terminal connected to said output of said third comparing means (17'), and a disabling terminal connected to said terminal enabling said clamping element (23), for generating a signal disabling said clamping element in the presence of said clamp disabling signal (V o3' ); and by the fact that said circuit means (20, 21) comprise a switch (20) located between said output of said second comparing means (16') and said enabling terminal of said clamping element (23), and having a control terminal connected to said fault detecting stage (6, 8). A circuit as claimed in Claim 13, characterized by the fact that it comprises a diagnostic disabling transistor (27) having a first and a second terminal connected to said fault detecting stage (6, 8) and to a reference potential line such as ground, and a control terminal connected to said output of said device enabling stage (4). A circuit as claimed in any one of the foregoing Claims from 1 to 14, characterized by the fact that it comprises a controlled current source circuit (44) having a control input connected to said turn-on input (19) and an output, and generating a current correlated to said voltage (V ST ); a current mirror circuit (53, 54) having an input connected to said output of said current source circuit (44) and an output; and a transistor element (58) having a first terminal defining said output of said first comparing means (15), a second terminal connected to a reference potential line such as ground, and a control terminal connected to said output of said current mirror circuit; a resistive element (61) being provided between said control terminal of said transistor element (58) and said reference potential line.

Inventors: BOTTI EDOARDO, FASSINA ANDREA, BOTTI, EDOARDO, FASSINA, ANDREA
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H02H11
IPC codes: H03F1, H02H7, H02H11, H03G3