Method of fabricating GaAs mesfets with enhanced schottky barrier

Abstract: The Schottky barrier gate (8) contact is produced by wet-chemical removal of native oxide in a sealed inert gas ambient and blow-drying the wet-etched surface with the inert gas prior to deposition of gate electrode metal on GaAs (4) by electron beam evaporation in an inert gas ambient. Use of Pt, the gate contact metal results in a Schottky barrier height of 0.98 eV for Pt on n-type GaAs (0.78 eV). To lower the sheet resistivity of the gate contact, Pt is preferably used as a multi-layer contact in combination with metals having lower sheet resistivity, e.g. Pt Au belayer.

Description: Field of the Invention This invention is concerned with GaAs MESFETs with enhanced Schottky barrier. Background of the Invention Field Effect Transistor (FET) is a three-terminal device in which the current through two terminals (drain and source) is controlled by a voltage at a third terminal (gate). FET is a unipolar device, that is, the current involves only majority carriers. One variant of the FET is a Junction FET (a JFET) in which the control (gate) voltage varies the depletion width of a reverse-biased p-n junction. A similar device results if the p-n junction is replaced by a reverse-biased Schottky barrier by placing a metal gate electrode directly on the semiconductor. Such a device is called a metal-semiconductor FET (a MESFET). Typically, the MESFET is formed on an n-type GaAs layer grown epitaxially on a semi-insulating substrate and may or may not include other layers such as a buffer layer, positioned between the substrate and the n-type layer, or a contact layer, positioned between the n-type layer and ohmic drain and source contacts. A Schottky barrier gate is formed on top of the n-type GaAs layer. By reverse-biasing or forward-biasing the Schottky gate, the channel can be depleted or opened to a desired current level. By using GaAs instead of Si, a higher electron mobility is available and GaAs can be operated at higher temperatures and, therefore, higher power levels. Close geometric tolerances can be achieved, and the MESFET can be very small, with gate lengths L ≤ 1µm being common. This is important at high frequencies, since drift time and capacitances must be kept to a minimum. One of the enduring problems in GaAs MESFET technology, however, is the relatively low Schottky barrier height ( B ) of metals used for the gate contact. On the n-type GaAs the  B is basically insensitive to the metal used, with the values being typically in the range 0.71-0.8 eV. This is a limiting factor in the design of many GaAs circuits and the availability of a contact with a larger barrier height would allow fabrication of digital logic circuits with better noise margins. Some applications of GaAs MESFET technology would benefit from an increase in the relatively low Schottky barrier height ( B ) of metals used for the gate contact. A further advantage would be the relaxed requirement on the uniformity of threshold voltage of the component MESFETs. A number of different approaches to increasing the Schottky barrier height have been attempted. For example, an incorporation of a thin fully-depleted p-type layer under the gate contact on n-GaAs leads to an enhancement of the  B . Values up to 1.33 eV have been demonstrated using 50 Å thick C or Zn delta-doped p type layers (~6-7 × 10 19 cm -3 ) epitaxially grown on the n-type GaAs. See S. J. Eglash et al., Journal of Applied Physics , Vol. 61, No. 11, 1 June 1987, pp. 5159-5169. Another approach consists of depositing a thin interfacial layer of Si or other materials between the n-type GaAs and the metal contact. Barrier heights of 1 eV have been demonstrated by this technique. See J. R. Waldrop and R. W. Grant, Appl. Phys. Lett., Vol. 52, No. 21, (23 May 1988) p. 1794-1796. However, these techniques complicate the manufacture of MESFETs and may bring unexpected undesirable effects. The role of a thin layer of native oxide, e.g. of the order of 20-25 Å in thickness, in degrading the properties of alloyed ohmic contacts on GaAs has been widely recognized; however, less attention has been paid to its effects on Schottky contacts. Woodall's effective work function model, see J. M. Woodall and J. L. Freeouf, J. Vac. Sci . Technol. , Vol. 21, No. 2, (July/August 1982) pp. 574-576, suggests that the Fermi level at the interface is not fixed by surface states but rather is related to work functions of microclusters of one or more interfacial phases resulting from either oxygen contamination or metal-semiconductor reactions which occur during metallization. Thus, with an oxide-free interface, the Schottky barrier height of a metal contact should be dependent on the metal work function. EP-A-0 304 073 reports a Schottky contact formed after cleaning by successive wet etching, using NH 4 F, and spatter etching. Wet etching alone was found inadequate to remove the oxide coating. X.W. Wu et al. in "Nb/GaAs and NbN/GaAs Schottky Barriers", Applied Physics Letters, vol. 50, No. 5, pp.287-89 (2 February 1987) report-forming nitride/GaAs Schottky barriers after wet etching in aqueous H 2 SO 4 with H 2 O 2 followed by aqueous HCl and blow drying with nitrogen. Subsequent high temperature heat treatments were required to disperse the oxide layer completely, though such complete removal was not necessary when Nb was used for the contact, since Nb forms conductive oxides. M. Ogawa et al. in "GaAs Alloy Type Schottky Barrier Contacts", NEC Research and Development, Vol. 22, pp. 1-7 (July 1971) reports forming Pt-Nickel Alloy/GaAs Schottky barriers after wet etching in H 2 SO 4 . Again a high temperature heat treatment was required to disperse the oxide. Summary of the Invention The invention is as set out in claim 1. The gate contact of a MESFET device is produced by wet-chemical etching of the n-type GaAs in a sealed inert gas ambient to remove native oxide on GaAs, blow-drying the etched surface with inert gas, followed by electron beam evaporation deposition of Pt as a gate metal in the inert gas atmosphere. This procedure leads to a high barrier height (0.98 eV) for a Pt gate contact. A major disadvantage of using Pt on MESFETs is its relatively high sheet resistance. This can be overcome by using a multilayer gate contact of Pt with a metal having lower sheet resistance, such as a bilayer of PtAu. The use of wet-chemical cleaning and blow-drying of the cleaned surface with inert gas in a sealed nitrogen ambient prior to gate metal deposition, together with the use of Pt contacts, leads to MESFETs with reduced gate leakage currents in comparison to the more conventional TiPtAu gate processed devices. This results from the larger enhanced barrier height of Pt with respect to Ti. The use of Pt layer with at least one layer of metal having lower sheet resistance, such as a PtAu bilayer to reduce the gate resistance, eliminates the problem of the relatively high sheet resistance of Pt. Brief Description of the Drawing FIG. 1 is a schematic representation of an exemplary MESFET device; FIG.2 is a representation of an x-ray photoelectron spectroscopy (XPS) at two different XPS take-off angles of GaAs cleaned in air atmosphere (dashed line-high angle -90°, solid line-low angle - 10°); FIGs. 3 and 4 are each a representation of an XPS spectra of GaAs cleaned in sealed nitrogen ambient, showing an essentially oxide free surface; FIG. 5 is a representation of a reverse bias current from GaAs MESFETs utilizing either the modified PtAu metal or conventional TiPtAu as the gate metal; FIGs. 6 and 7 are each a representation of I D - V DS characteristics from GaAs MESFETs utilizing, respectively, either the modified PtAu or conventional TiPtAu as the gate metal; FIGs. 8 and 9 are each a representation of a gate leakage current, I G , as a function of V DS for the GaAs MESFETs of FIGs. 6 and 7 (PtAu gate metal) and FIGs. 6 and 8 (TiPtAu gate metal), respectively. Detailed Description In FIG. 1 is shown an exemplary MESFET device, 1, including a GaAs substrate, 2, a buffer layer, 3, an n-type channel layer, 4, an n + -type contact layer, 5, a drain and a source ohmic contacts, 6 and 7, respectively, and a gate contact, 8, upon a region of the n-type channel layer 4. No diffusions are involved, permitting small gate lengths, L ≤ 1 µm. Semi-insulating GaAs substrates, used in these MESFETs, were grown by the Horizontal Bridgman technique, and were uniformly doped with Si to give a net carrier density of 2 × 10 17 cm- 3 . The MESFET structures were grown on semi-insulating GaAs substrates by atmospheric pressure organic-metallic vapor phase epitaxy (OMVPE). Buffer layer 3 was 1500 Å thick undoped GaAs layer and channel layer 4 was a 1500 Å thick n-type GaAs layer doped with Si (2 × 10 17 cm -3 ). Contact layer 5 was a 1000 Å thick n + type Si-doped (2 × 10 18 cm -3 ) GaAs layer. Other thicknesses of these layers may be used, for example, the buffer layer may be from 0 to a few micrometers thick, the channel layer may be from 500 to 5,000 Å thick depending on the doping level and threshold voltage, and the contact layer may be from 200 to 3000 Å thick. The ohmic drain and source contacts 6 and 7, respectively, were formed by electron-beam evaporation of Ni/Au-Ge/Mo/Au metal patterned by lift-off AZ resist, followed by rapid thermal annealing at 420°C for 20 sec. Gate contact 8 was defined by etching away a region of n + type contact layer 5 down to the n-type GaAs layer and depositing on the n-type region a layer of metal in an inert gas-sealed electron beam evaporator. The etchant for the contact layer was an H 2 O 2 /H 2 O mixture in a ratio of 4:1, with pH adjusted by NH 4 OH to a value of about 7.2. The gate metal was deposited on the surface of the n-type GaAs by electron-beam evaporation. Prior to loading the wafer into the inert gas-sealed evaporator, the sample was placed in an inert gas-sealed environment similar to that of the evaporator, and any native oxide present on the n-type gate region was removed by immersing the sample in an aqueous ammonium hydroxide solution (NH 4 OH/H 2 O ratio ranging from 1:15 to 1:50) for 30 sec, followed by blow-drying the sample with filtered dry inert gas in the same inert gas-sealed environment. An important requirement for the filtered inert gas is substantial absence of water in the gas and such blow-drying of at least the surface of the gate region that the presence of water is precluded or at least restricted to a thickness equivalent to 0.5 monolayer or less. Thereafter the etched sample was transferred into the evaporator without breaking the inert gas-seal, wherein the gate electrode metal was deposited by electron beam evaporation in a known manner in a thickness from 200 to 5000 Å. Nitrogen is the preferred inert gas both for the inert gas-sealed environment and for the blow-drying. Other inert gases such as argon, helium, carbon dioxide are suitable for this purpose. In the specific example of the exemplary procedure, the metal for the gate contact was selected from Ni and Pt both of which have high work function. See E. H. Rhoderick and R. H. Williams "Metal-Semiconductor Contacts," Oxford Science Publications , Oxford, 2nd Ed., 1988, p. 10-11, and 48. The Ni or Pt metallization, deposited with this oxide-removing procedure as a layer 1500 Å thick each, was compared with a) 1500 Å Pt and Ni metallizations produced using a cleaning procedure in which the wet-chemical cleaning took place in an air ambient immediately followed by the loading of the sample into the inert gas-sealed evaporator, and b) TiPtAu gate, Ti(250Å/Pt(500Å)/Au(3000Å), contacts deposited on large area (200 µm diameter) Schottky diodes using the conventional cleaning technique which includes wet-chemical etching in air. Bilayer PtAu metallizations, Pt (800 Å)/Au (3000 Å), deposited on gate region samples cleaned in nitrogen-sealed ambient as well as the TiPtAu metallizations, Ti (250 Å)/Pt(500 Å)/Au (3000 Å), deposited on samples cleaned with conventional cleaning were applied on GaAs MESFETs with the gate dimensions of 1 × 30 µm 2 . Barrier heights,  B (eV), and ideality, n, of diodes with gates produced with these different procedures are disclosed in Table I below. Metal Cleaned in Open Air Cleaned in N 2 Sealed Ambient Work Function (eV)  B (eV) n  B (eV) n Ni 0.68 1.11 0.57 1.15 5.15 Pt 0.79 1.11 0.98 1.13 5.65 Reference Ti/Pt/Au 0.78 1.03 The Schottky barrier height characteristics were evaluated with a Hewlett-Packard parameter analyzer and were fitted to the standard equation assuming that thermionic emission was the dominant condition mechanism. Both Ni and Pt contacts produced with conventional preparation (wet etching in air ambient) show a common ideality factor of 1.11 and barrier heights of 0.68 and 0.79 eV, respectively. In these cases, the oxide clearly plays a dominant role. For wafers prepared by wet cleaning and blow-drying in a sealed N 2 ambient, the Ni contact showed an unexpectedly low  B of 0.57 eV and an ideality factor of 1.11, while the Pt contact displayed a barrier height of 0.98 eV with an ideality factor of 1.13. Although the barrier heights of these contacts do not precisely follow the Schottky model, they are definitely related to the metal work functions, as illustrated in Table 1. The barrier height for conventional TiPtAu metallization was 0.78 eV, with an ideality factor of 1.03. This is typical of this metallization scheme and cleaning procedure. This comparison shows that with this cleaning technique in an inert ambient and its higher metal work function, Pt is a useful as a gate metal on GaAs. Pt may be used as a gate contact by itself, but because of relatively high sheet resistivity of the metal, it may be used as a base metal for other metals having lower sheet resistivity such as gold, titanium, aluminum, and others. In such instances, platinum may be deposited as a thin layer, e.g. 200 to 2000 Å thick followed by a relatively thick layer, e.g. from 1000 to 5000 Å, of a metal with lower sheet resistivity and which may have lower work function. An example of such combination is a bilayer PtAu metallization. Figure 2 shows the XPS spectra at two different take-off angles from the sample cleaned by the conventional method. The lower take-off angle (10°) permits sampling of only about 1/3 of the depth of 30-40 Å on the high angle (90°) specimen. The oxide peak was greatly enhanced at glancing (low) angle showing that the oxide existed on the surface only within a few monolayers. In contrast, XPS spectra of GaAs cleaned and blown-dry with nitrogen in the sealed nitrogen ambient shows an essentially oxide free surface, as illustrated in FIGs. 3 and 4. These spectra wen taken from different lines (different binding energies) than those of FIG. 2, and are even more sensitive, sampling only the top 2 or 3 monolayers of the etched surface. FIG. 5 compares the reverse bias characteristics of MESFETs with the bilayer PtAu (solid line) gate metal with those of the conventional TiPtAu (dashed line). Up to a reverse bias of 5V, the current in the device using the PtAu metallization is an order of magnitude lower than in the case of the TiPtAu gate metal. The drain current (I d )-drain source voltage (V ds ) characteristics from both MESFETs as a function of gate voltage (Vg) are shown in FIGs. 6 and 7, respectively. These characteristics were measured in 0.25V steps for MESFETs with PtAu gate metallization with V g =0.8 to -0.949V and for MESFETs with TiPtAu with V g =0.8 to 0.699V. The device with the PtAu gate has better saturation behavior (FIG. 6); for example, its output resistance is higher and there is no sign of breakdown which is seen in device with the TiPtAu gate (right hand portion of FIG 7). The forward bias gate currents were also lower at a given voltage for MESFET with the PtAu gate (FIG. 8) than for the MESFET with the TiPtAu gate, (FIG. 9). The V g for both the PtAu and the TiPtAu contacts were measured with V g =0.8 to 0.674V in 0.25V steps. These facts are consistent with the large barrier height for PtAu. The significantly lower leakage currents and device performance improvement emphasize the advantage of the oxide removal procedure in accordance with this invention and the use of Pt metallization in direct contact with the GaAs surface cleaned by this procedure.

Claims: The method of fabricating a GaAs MESFET device comprising a semiconductor substrate, an n-type GaAs channel layer, an n + -type GaAs contact layer, drain and source ohmic contacts on a surface of the n + GaAs layer and a gate contact on a surface of the n-type GaAs channel layer forming a Schottky barrier contact with the n-type GaAs layer, which comprises forming said gate contact by evaporation of a metal multilayer structure comprising a Pt layer on a gate region of the n-type GaAs in an inert gas-sealed ambient, wherein said Pt layer is in direct contact with the surface of the n-type GaAs and wherein prior to the evaporation of the gate contact, a partially fabricated device is placed into the inert gas-sealed ambient, the surface of the gate region is wet etched with an etchant comprising NH 4 OH, and the wet etched surface is blow-dried with the inert gas. The method of claim 1 in which said inert gas is chosen from the group consisting of argon, helium, nitrogen and carbon dioxide. The method of claim 1 in which said inert gas is nitrogen. The method of claim 1, in which at least one layer of another metal, having lower sheet resistivity than Pt, overlies the Pt layer. The method of claim 4, in which said another metal is selected from the group consisting of gold, aluminum and titanium. The method of claim 5 in which said Pt layer is in the range 20 to 200nm thick and said another layer is in the range 100 to 500nm in thickness. The method of claim 4, in which said contact is PtAu. The method of claim 7, in which said Pt layer is 80nm thick and said Au layer is 300nm thick.

Inventors: EMERSON ADRIAN BRUCE, REN FAN, EMERSON, ADRIAN BRUCE, REN, FAN
Applicants: AT & T CORP, AT&T CORP.
Application year: 1992
Main classification: H01L21
IPC codes: H01L29, H01L21