A GTO-THYRISTOR AND A METHOD FOR THE MANUFACTURE OF A GTO-THYRISTOR

Abstract: The invention relates to a GTO-thyristor in a silicon disc which has on one side thereof an n-layer which is covered by an anode contact (50) and which on its opposite side is covered by a p-conducting base layer (51) on which a cathode structure and a gate structure are built. The cathode structure is comprised of upstanding islands having a greatest cross-dimension of 10-100 mu m or less, each having an n-layer (52) resting on a raised part of the base layer. The gate-electrodes (60) form a network which surrounds the islands on all sides thereof without being in contact therewith. This structure enables the islands to be given small dimensions, according to a method which only requires one sole fine-detailed mask, with the aid of etching, oxidizing and applying operations.

Description: A GTO-Thyristor and a Method for the Manufacture of a GTO-Thyristor Increasing interest has been shown in the GTO thyristor (Gate Turn Off) in recent years, particularly within the electrical power technology, these thyristors being able to operate with high voltages and large currents. The invention relates to a GTO-thyristor of the kind defined in the preamble of Claim 1. The invention also relates to a method for the manufacture of GTO-thyristors according to the preamble of Claim 7. A known type of GTO-thyristor is comprised of a silicon disc based on n-conductive silicon which is provided on its underside with a p-doped layer and an aluminium anode electrode and from the opposite side of which there is diffused into the disc a p-conductive layer against which n-conductor fingers lie at the top of the disc and are connected to a cathode electrode. Lying between these fingers are elongated gate-electrodes through which gate trigger current and gate turn-off current can be supplied and which are electrically insulated from the fingers of n-conductors but are able to deliver and remove charge carriers via the p-layer in relation to the n-p-junction between the fingers and the p-layer. In earlier known techniques, endeavours have been made to make turn-on more effective, by decreasing the degree of doping of the p-layer, although this increases the resistance with which the gate trigger current and gate turn-off current is applied, which is disadvantageous, particularly when turning off the gate, since the maximum gate turn-off current is then restricted by the voltage drop that can be tolerated with regard to breakdown risk. It has been proposed to reduce the width of the cathode fingers, for instance to a width of 50 μm or less, in order to compensate for this resistance effect. When the thyristors are then produced conventionally, utilizing a large number of steps with separate masks, serious problems of registering arise, resulting in difficulties in achieving a high yield. It is necessary to accurately check portion by portion thyristors that are constructed from possibly thousands of cathode fingers, in order to eliminate connection of fault-impaired cathode fingers to the cathode electrode common to the thyristor. A first object of the invention is to provide an improved cathode structure which is intended to reduce the resistance particularly for the turn-off currents from the gate electrodes. Another object is to enable the manufacture of thyristors with small linear tolerances, particularly by reducing the number of masks that must be used with a registering precision that corresponds to the small linear tolerances. According to the invention, these objects can be achieved by constructing the cathode structure in the manner set forth in the characterizing clause of Claim 1. The inventive structure is not restricted to a cathode structure, since the n-doped and p-doped regions may, just as well, be p-conducting and n-conducting regions with complementary construction in relation to what is described here and in the following. Because the two alternatives are mutually equivalent, the alternative embodiment will not be described here but is considered as claimed. In accordance with one preferred embodiment, the cathodes are small islands that are collected in segments with the islands distributed regularly in a quadratic network or in some other way, for instance in quincuncial distribution, with the gate arranged in the form of a network therebetween. A large number of such, equivalent segments may be distributed uniformly over the surface of a silicon disc in a component. These segments can then be checked individually in manufacture and should any segment be found faulty, this segment need not be connected to the common cathode electrode. The islands may have varying heights and the height of an island is normally at most 20 μm, although the islands may sometimes have heights in the order of fractions of a μm. Although the islands in the following exemplifying embodiment have a quadratic shape, it is possible to give the islands some other shape, for instance a poly-gonal, circular, ring or star-like shape. Neither is it necessary for the islands to be the same size. The islands may also be different, with different segment configurations over the component surface. For instance, in order to further decrease the voltage drop in the gate current supply, it may be beneficial to provide an island distribution factor which increases outwardly towards the edges when the gate-electrode is supplied with current from the centre, and also to space the segments successively further apart inwardly towards the centre, for the same purpose. It is also possible to provide ring-shaped islands with their own metal contacts in the centre and without contact with the common gate electrode, so that the potential in said islands will become floating. The invention also relates to a method for manufacturing GTO-thyristors which is particularly advantageous in the case of small-patterned details, in that the number of masks required herefor is greatly reduced and, in the case of one advantageous embodiment, only one fine- pattern mask need be used. This is achieved with the features set forth in Claim 9. According to the inven¬ tion, the method is based on the concept that subsequent to using a fine-pattern mask an etching or like process will result in raised, small islands with steep edges. Subsequent method steps can then be controlled by this three-dimensional, geometric topographical structure, particularly in combination with known anisotropically acting treatment stages. The invention will now be described in more detail with reference to an exemplifying embodiment thereof and also with reference to the accompanying drawings. Figure 1 illustrates a GTO-thyristor. Figure 2 illustrates a segment of one GTO-thyristor. Figure 3 is a scanning electron microscope image of part of a segment under manufacture. Figure 4 is, similarly, a scanning electron microscope image of a single cathode element of a GTO-thyristor. Figures 5a-i are cross-sectional views illustrating schematically the manufacturing stages of a GTO-transis- tor in accordance with an exemplifying embodiment. Figure 1 is a top view of a GTO-thyristor, and shows the thyristor roughly in its natural size. The thyristor has on its undersurface (not shown) an anode electrode which essentially covers said underside. Located in the centre of the thyristor is an opening 1 which extends to a gate layer, and the periphery of the upper surface nearest thereto is a metalized annular zone which is in contact with the thyristor gate electrodes. Surrounding the opening is a quadratic cellular structure having segments 2, which are covered on the upper side with metal electrodes which form cathode electrodes. When the thyristor is mounted, these cathode electrodes are in contact with a common lead-in contact, while another conductor contact lies against the anode on the underside and a gate contact abuts the annular zone around said opening from above. A sunken insulated gate conductor network is provided between the segments, this network branching further through the segments and being intended to fire and extinguish the thyristor. Figure 2 illustrates schematically one such segment 2, with the exclusion of the aforesaid covering metal electrode. Each such segment 2 includes a large number of small island-like silicon cathode elements 3 which are n- conducting and rest on a p-conducting base layer, which in turn rests on an n-conducting layer. The branch gate- electrode network is disposed in the corridors between these cathode elements 3. Because the distances between the gate electrodes and the centre of the n-p-junction between the cathode elements and the base layer beneath the islands is small, the turn-off efficiency in particular is greatly improved. Figure 3 illustrates cathode elements 3 during manufac¬ ture of the thyristor, these cathode elements having the form of islands upstanding over an exposed surface of base material. The mutual spacing between the islands is roughly 60 micrometers and the islands are quadratic having a side measurement of about 40 μm. Figure 4 illustrates one single island, from which it will be seen that said islands have extremely steep edges. The images shown in Figures 3 and 4 have been produced with the aid of a scanning electron microscope. In the case of one manufactured design, the thyristor contained 176 segments with 100 cathode islands per segment, i.e. a total of 17,600 cathode islands. There is nothing to prevent, however, the dimensions of the islands being reduced and the islands packed more dense¬ ly, which would further improve the effect. The proposed inventive method of manufacture namely enables the registering problems and other problems to be reduced, which in the case of miniaturization otherwise quickly lead to reduced yield of manufacture. The number of cathode islands per segment can thus vary within wide limits, e.g. 1-10,000, and the size of the elementary cells may be from 100 x 100 μm, as in the case of the illustrated embodiment, down to 20 x 20 μm and smaller. This is because the islands can be produced with the aid of only one single mask. The connection of the islands of the elementary cells with a common conducting layer for each segment requires a mask which requires considerably less registering precision. The various segments can then be tested individually and those segments which do not function satisfactorily can be eliminated, by etching away the cathode contact of such segments. An appropriate method of manufacture will now be des- cribed, this description also being intended to illus¬ trate the aforedescribed exemplifying embodiment. Figure 5a is a cross-sectional view of part of a silicon disc having a thickness of about 0.5 mm. A p-doped layer has been provided on the underside of the disc. This layer may also include a short circuiting pattern con¬ sisting of n-doped regions. An aluminium layer is then provided on the underside thereof. These anode- conducting layers have not been shown separately in the Figures, but are collectively designated 50 in the Figure. The disc is initially N-doped. A P-layer 51 has been doped-in from the top of the disc, whereafter a N - doped layer 52 has been formed on top of the P-layer 51. Islands such as those illustrated in Figures 3 and 4 are produced in the layer 52. This is achieved by the steps of applying a photo-resist layer 53, exposing said layer with a mask and developing the layer, and then anisotro- pically etching the silicon, down to a small distance beneath the boundary 54 between the layers 51 and 52. This results in the cross-sectional configuration shown in Figure 5b. In accordance with the Figure 5c illustration, the silicon surfaces are now oxidized to form an oxide layer 55, which is made relatively thin between the islands (anisotropic process) . This oxide layer is etched away partially in an aniso¬ tropic process, thereby exposing the interspaces between the islands while leaving the islands with their steep edges oxide-coated. The exposed surfaces are provided with a thin p -layer 56, for instance by ion implantation. The oxide-coated surfaces are therewith only slightly influenced, and a con- figuration according to Figure 5d is obtained. A metal layer, e.g. an aluminium layer 57, is then applied over the whole surface, whereafter a photo-resist layer 58 is spun over the aluminium layer. In view of the fact that the layer 58 shall not be exposed and developed, it is possible to use some other product, such as an insulating polymer. The resultant configuration is shown in Figure 5e. The spun photo-resist layer 58 is then etched down partially, so as to leave a resist layer 59 which covers the aluminium layer 57 between the islands. This results in the configuration shown in Figure 5f. All of the exposed aluminium is then etched away, in¬ cluding the aluminium which borders sideways on the residual photo-resist layer 59, while leaving the alumi¬ nium layer 60 which is protected by the photo-resist layer 59. The photo-resist is then removed, resulting in the configuration shown in Figure 5g, with the remaining aluminium layer 60 which is bordered on the steep edges of the islands by a gap 61. A polyimide solution is then spun onto the transistor and allowed to dry, whereafter the spun polyimide is etched down, roughly the same as the layer 58 in Figure 5e, until only the interspaces between the islands are filled with insulating polyamide 61, preferably to a level corresponding to the N-silicon upper surface 52 of the islands. This results in the configuration shown in Figure 5h. That part of the oxide layer 55 which covers the upper surfaces of the islands is now etched away and the whole is covered with a metal contact layer 62, such as an aluminium contact layer. The finished elementary cell construction is illustrated in section in Figure 5i. The main thyristor current can now flow from the contact layer 62 to the N-layer 52 of the cathode island, via the base layer 51 down into the N-base layer to the anode connection layer 50. The surrounding gate conductors 60 are included in a conductor network structure which surrounds all cathode islands and segments and is insulated from the contact layer 62 by the polyamide layer 61 and has good contact with the P-base layer 51 via the P -layer 56. The junction between the cathode layer 52 and the P-base layer 51 is protected by the oxide layer 55 remaining at the steep edges of the islands. As before mentioned, the proposed method is character- i- zed by the fact that it avoids the use of more than one sole small scale mask with the aid of a self-registering principle. The mask required to obtain contact layer 62 has a completely different and larger scale, which is on the section standard and not on the individual standard of the small cathodes. The above description of the different etching, applica- tion and oxidation steps of the illustrated embodiment has only been given briefly, in view of the fact that each step need not, in itself, be at variance from conventional semiconductor manufacturing process steps, such as from processes described, for instance, in Wolf + Tauber, "Silicon Processing for the VLSI Era" (Lattice Press, Sunset Beach, Cal., 1986), this work being hereby declared to be part of the present description by inclusion by reference. It therewith follows that manufacture in relation to the illustrated embodiment can be varied in many different ways and that the described embodiment is merely an embodiment at present preferred and is not intended to limit the scope of the invention defined in the following Claims.

Claims: Claims 1. A GTO-thyristor constructed from a silicon disc which has on one side thereof a first metal electrode (50) which is connected electrically to one side of a first region having a first conducting type (N), and the opposite side of said first region borders on one side of a second region (51) having a second conducting type, the opposite side of said second region bordering on region- wise localized third regions (52) of the first conductor type provided with second metal electrodes which are connected to a common electrode (62), the opposite side of said second region also bordering on gate electrodes (60, 56) side-located relative to said third regions and which are electrically isolated from the localized third regions, are in electrical contact with the second region and connected to a common control electrode, c h a r ¬ a c t e r i z e d in that the third regions (52) include islands which have steep side edges and are upstanding from the second region (51), wherein the islands have a greatest extension smaller than 200 μm, and wherein the gate electrodes (60) form a conductor network which surrounds each such island on all sides thereof. 2. A GTO-thyristor according to Claim 1, c h a r ¬ a c t e r i z e d in that the islands are distributed group-wise in segments (Figure 1) within which the islands are distributed uniformly and mutually spaced at distances of the same order of magnitude as the greatest extension of said islands, wherein the segments may be uniformly distributed at equal distances or at mutually different distances. 3. A GTO-thyristor according to Claim 2, c h a r ¬ a c t e r i z e d in that the islands in each segment are placed along an imaginary rectangular reticular network. 4. A GTO-thyristor according to Claim 2, c h r ¬ a c t e r i z e d in that cathode islands in one and the same segment have mutually different forms. 5. A GTO-thyristor according to Claim 1 or 2, c h a r a c t e r i z e d in that the islands are distributed outwardly from a centre so as to become more densely spaced radially outwards. 6. A GTO-transistor according to Claim 5, c h a r ¬ a c t e r i z e d in that the islands are distributed in groups in segments with intermediate gate electrodes, wherein said segments have different island density distributions. 7. A GTO-thyristor according to any one of the preced¬ ing Claims, c h a r a c t e r i z e d in that the islands are coated at their steep side edges with insu¬ lating silicon oxide layers (55) which also sidewise cover a boundary surface (54) between said third region and said second region (51), wherein said islands, in excess of said respective third regions, also include portions upstanding from the second region, so that said boundary surface (54) is terminated at the steep side edges of said islands. 8. A GTO-transistor according to Claim 1, c h a r ¬ a c t e r i z e d in that the first conducting type is n-conducting and the second conducting type is p-conducting. 9. A method for manufacturing a GTO-thyristor which has a pn-junction which extends between two layers essen¬ tially within the whole of a disc, of which a first layer extends to the bottom surface of the disc and is provided with a first metal electrode connection and the second layer forms a base material whose side opposite the aforesaid junction is provided with a number of mutually spaced, two-dimensionally restricted elongated third semiconductor layers which form pn-junctions against the second layer, said third semiconductor layers being connected to a metal collecting electrode, and between the third semiconductor layers a metal gate-electrode pattern in contact with the second layer and without direct contact with the third semiconductor layers, said gate-electrode pattern being connected to a gate*elec- trode which by voltage application is able to turn-on and turn-off respectively a current that flows between the first metal electrode and the collecting electrode, c h a r a c t e r i z e d in that the third semiconduc¬ tor layers (52) of limited extension are produced by pro- viding a further semiconductor layer (52) of opposite conducting type which covers the second layer (51), covering that further layer with a photo-resist layer (53), said photo-resist layer being exposed with the aid of a mask and developed so as to leave only small patches or flecks having a largest dimension of at most two- hundred micrometers and arranged in a regular pattern; in that an anisotropic etching operation is carried out through the whole thickness of the further semiconductor layer (52) covering said second layer (51) so as to form islands beneath the flecks of photo-resist (53) having steep edges which intersect the boundary (54) between the different conducting types of the second layer and the further layer, said islands being upstanding from an exposed, generally flat base material surface, whereafter the thus obtained three-dimensional topography (Figure 3) is used to place, by successive self-registering operations, the aforesaid gate-electrode pattern (60) between the islands and electrically isolated therefrom, in the form of a metal network which surrounds the islands on all sides thereof and which is in contact with the underlying base material. 10. A method according to Claim 9 , c h a r a c t ¬ e r i z e d in that a) a silicon disc is doped with a base layer (51) which forms said second layer and which has, in relation to the intrinsic conductivity of the silicon disc, a first conducting type opposite to a second conducting type, and also a further layer (52) having the first conducting type; b) in that a photo-resist layer (53) is applied onto the further layer and exposed with a mask and developed so as to leave distributed small surfaces having a greatest extension smaller than 200 μm; c) in that there is carried out an anisotropically acting etching process at portions where no photo-resist remains, to a depth exceeding the depth of the further layer and to leave islands having steep edges at the remaining small surfaces of photo-resist; d) in that an oxidation process is carried out to form an oxide layer (55) which completely covers the exposed surface of the second layer, the islands and their steep edges (Figure 5c); e) in that the oxide layer (55) is partially etched away to leave a layer which covers the islands and their steep edges but which exposes the base layer between the islands, whereafter a P -layer (56) is diffused into the thus exposed surface (Figure 5d); f) in that an aluminium layer (57) is applied over the exposed part of the second layer, the islands and their steep edges, whereafter this layer is covered with a liquid polymer (58), such as photo-resist, which is dried (Figure 5e); g) in that the polymer layer is etched down so as to expose the upper parts of the islands, leaving polymer layer (59) in the interspace between the islands (Figure 5f); h) in that the aluminium layer (57) is etched away, whereby the remaining polymer layer (59) protects part thereof (60) in the interspaces between the islands but forms empty parts (61) against their edges (Figure 5g) ; i) in that the whole is covered with an insulating layer (61), preferably a polyimide layer, which is thereafter etched down so as to remain only between the islands, which project partially therefrom, preferably flush with the upper surfaces of the islands beneath their oxide layers (55) (Figure 5h) ; and j) the island surfaces are freed from the oxide layer by an etching operation, whereafter a metal layer (62) is applied over the islands and the insulating layer (61) (Figure 5i) .

Inventors: BAKOWSKI MIETEK, ELDERSTIG HAAKAN, LJUNGBERG MARTIN, BAKOWSKI, MIETEK, ELDERSTIG, HAAKAN, LJUNGBERG, MARTIN
Applicants: ASEA BROWN BOVERI, ASEA BROWN BOVERI AB
Application year: 1992
Main classification: H01L29
IPC codes: H01L21, H01L29