Efficiency improved DRAM row redundancy circuit

Abstract: A redundancy scheme for a memory is disclosed which allows defect correction, particularly, word line to word line short correction (40, 36, 38, 18) through the use of a minimal number of redundant lines (RWL0, RWL1).

Description: FIELD of the Invention This invention is in the field of integrated circuits. More specifically this invention is in the field of memories. Background of the Invention Electronic devices and systems such as printers, copiers, electronic storage devices (memories) high definition television, enhanced definition television and computational devices (e.g. calculators and computers including personal computers, minicomputers, personal computers and microcomputers) requiring electronic storage devices, often provide data storage on an integrated circuit chip. Because these devices often require large amounts of storage space for many applications, these storage devices are embodied in memory, for instance, a dynamic random access memory (DRAM). Memory cells sometimes contain or are associated with defects. It is therefore necessary to replace defective memory or defect associated memory with memory from alternate memory cells commonly referred to as redundant memory. Once defective memory is detected the address corresponding to this memory is noted and the mechanism for implementing the redundant memory cells is enabled before the memory is used. The mechanism for implementing the redundant memory cells is usually embodied in a system based on blowing fuses. The scheme for producing a signal indicative of the desire to use the redundant memory or rather to match the row address of the defective memory is of extreme importance. This redundancy scheme forms an integral part of the dynamic random access memory. This scheme is also an integral part of the above described devices and systems, supplying substantial value to these and other devices and systems in which it is used. Figure 1a illustrates a schematic drawing of a prior art redundancy scheme. N-channel transistor 2 is connected to P-channel transistor 4 through fuse 14. The gates of transistors 4 and 2 are connected to a terminal for powering up the circuit as shown. The drain of transistor 4 is connected to the input of inverter 10 and the drain of P-channel transistor 6. The drain of P-channel transistor 6 is also connected to the gate of N-channel transistor 8. The output of inverter 10 is connected to the gate of N-channel transistor 12. The signals from an address bit and its complement, A N and A N- , respectively, are input into respective terminals of associated transistors 8 and 12. N represents integers from zero through N. A circuit such as the one illustrated in figure 1a exists for each set of address bits comprising an address bit and its complement. Each figure 1a circuit produces address factors R N from the input of address bits A N and A N- . In connection with using a redundant memory cell in place of a usual memory cell, fuse 14 is blown when address bit A N is at a logic high level. Consequently, a high level signal is input to the gate of transistor 8 and inverter 10, thus resulting in a turned on transistor 8 and a turned off transistor 12. Note that feed back through transistor 6 helps maintain this logic high level signal. Alternatively, if address bit A N is at a logic low level, fuse 14 is not blown. This results in a turned off transistor 8 and a turned on transistor 12. Figure 1b is a schematic drawing of the circuit which processes the address factors from a plurality of circuits of the type shown in figure 1a. Each address factor is input into the gate of a plurality of transistors each labeled 16. When an address match occurs such that memory is addressed needing replacement by redundant memory, the gates of transistors 16 connected to NAND gate 18 are each at a logic low level resulting in inputting a high logic level signal into NAND gate 18. Consequently, during a logic high enable signal to NAND gate 18, NAND gate 18 outputs a low level logic signal to inverter 20. Inverter 20 outputs a high logic level signal which enables the redundant memory cell word line for the current address. Note that the redundancy system implemented by figure 1b results in only replacing one memory cell word line at a time. Unfortunately, such single replacement system is inadequate given today's need for memory speed. Figure 1c illustrates a schematic drawing of a prior art redundancy scheme which allows multiple replacement of the usual memory cell word lines by redundant memory cell word lines. The circuit in figure 1c is similar to the circuit of figure 1b. Note that the most important difference lies in the fact that no address factor R 0 (an address factor produced by address bits A 0 and A 0- ) is used for input into a transistor 16. Consequently, this circuit results in replacing the use of two memory cell word lines with two redundant memory cell word lines during an address match since the least significant bit in an address makes no contribution by the way of address factors. During an address match with a logic high enable signal to NAND gate 18, NAND gate 18 outputs a logic low signal to inverter 20. NAND gate 18 and inverter 20 together implement an AND gate. Inverter 20 in turn outputs a high logic level signal. Depending on whether A 0 or A 0- is at a high logic level the output of inverter 22 or 24, each connected to the output of inverter 20, will transmit a low logic level to the input of inverters 26 or 28. This will result in either a high logic level signal on redundant word line RWLO or RWL1. A high logic level signal on a redundant word line allows the use of redundant memory cells with gates connected to this word line. Note that the foregoing described multiple replacement system does not always allow multiple replacement of certain defective word lines such as is produced by certain word line to word line shorts. Figure 2 is a diagram which illustrates this problem. Since address factor R 0 is not used in the multiple replace scheme, addresses A 0 and A 1 can attain any state, logic zero or logic one, during an address match. Consequently, the regular word lines are replaced by the redundant memory lines two at a time during an address match such that all address bits past the last address bit are the same as the address one desires to match. Therefore, if A, B, C, and D represent word line to word line shorts between to adjacent word lines, it is easily seen that although shorts A and C can be corrected by the foregoing described multiple replacement scheme, shorts B and D cannot be replaced by the multiple replacement scheme. This problem is further illustrated by the chart below. A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 For a given address that requires a row address match for redundant memory use, addresses 000 and 001 are indistinguishable to the scheme. Such is also the case with addresses 010 and 011. Addresses 001 and 010 have different A 1 bits. Therefore, it is impossible to simultaneously replace word lines corresponding to word line addresses 001 and 010 since no address bit match can occur at address bit A 1 . The prior art multiple replacement scheme solved this simultaneous replacement problem by blowing fuses so as to disregard not only address bit A 0 but also address bit A 1 . This results in replacement of 4 word lines at a time rather than two word lines at a time. Extending this scheme further, in cases where address bit A 2 presented a problem, the scheme replaced 8 word lines at a timer Unfortunately, as is apparent, such a solution does not always best allocate redundant word line resources. EP-A-0 049 629 discloses a redundancy scheme for replacing main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. The RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer. When the comparator senses a match, a control signal is generated to initiate substitution of spare memory cells for the defective main memory cells. Two programmable addresses (both row and column) are provided for maximum flexibility in correcting defects. With the two row fuses and the two column fuses, any two arbitrary groups of four rows and two columns can be replaced. Column address inputs and row address inputs time share a single buffer and the same comparison circuitry. A reduction in the number of fuses required may be effected by replacing second row and column fuse circuits with A+1 comparators, where A indicates the address of a defective cell stored in the first fuse circuits. The present invention as claimed in claim 1 provides a memory redundancy scheme circuit comprising: a NAND gate; a plurality of transistors connected to an input of said NAND gate, a controlling terminal of each said transistor suitable for receiving an address factor; characterized by : a logic function circuit operable to perform a selected logic function upon a plurality of address bits; a switch connected to said logic function circuit operable to couple said logic function circuit to said selected NAND gate input. A corresponding method is claimed in claim 7. A memory redundancy scheme circuit in accordance with the invention presents a more efficient solution to the multiple replacement problem discussed above. One way of carrying out the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figures 1a through 1c illustrate schematic drawings of prior art redundancy schemes. Figure 2 illustrates a diagram of the defect replacement pattern for a prior art redundancy scheme. Figure 3 illustrates a schematic drawing of a circuit illustrating an application of the invention's redundancy scheme. Figure 4 illustrates a diagram showing a portion the invention's redundancy replacement capability as applied to the circuit figure 3. Detailed Description of the Invention The invention's DRAM redundancy circuit provides a considerable advantage in selecting redundant word lines to replace the regular word lines. This circuit makes use of some function logical function of the non-matching address bits of two word lines between which a word line to word line short exists. For example, the logical function can comprise the exclusive OR, or some function of the exclusive OR (i.e. exclusive NOR) of the non-matching address bits of two word lines between which a word line to word line short exists. The chart below illustrates the necessary exclusive OR of address bits in an address in which certain address factors R N are ignored in decoding the redundant word line. For instance, where R 0 is ignored, A 0 and A 1 are exclusively ORed together to produce an input into a decoding circuit for correcting word line to word line shorts of the type indicated at B and D of figure 2. Where R 0 and R 1 are ignored, A 1 and A 2 are exclusively ORed together to produce an input into a decoding circuit for correcting word line to word line shorts wherein replacement occurring only four at a time with redundant word lines is not possible with the prior art scheme of the type previously discussed. For instance, the prior art scheme can not correct a word line to word line short for addresses 0011 and 0100 such that only four usual word lines are replaced with four redundant word lines. (Note that if address factors R 0 and R 1 are not used in a decoding scheme then multiple replacement of four usual word lines with four redundant word lines occurs.) The prior art scheme would require replacement of 8 word lines at a time to correct this type of defect since an address bit match is not possible at address bit A2. Where R 0 , R 1 and R 2 are ignored, A 2 and A 3 are exclusively ORed together to produce an input into a decoding circuit for correcting word line to word line shorts wherein replacement occurring only eight at a time with redundant word lines is not possible with the prior art scheme of the type previously discussed. For instance, the prior art scheme can not correct a word line to word line short for addresses 0111 and 1000 such that only eight usual word lines are replaced with eight redundant word lines. (Note that if address factors R 0 , R 1 , and R 2 are not used in a decoding scheme then multiple replacement of eight usual word lines with eight redundant word lines occurs.) the prior art scheme would require replacement of sixteen word lines at a time to correct this type of defect since it is not possible to match address bit A 3 . The foregoing scheme is easily extended to a greater number of bits. A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 EXOR A0 & A1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 EXOR A1 & A2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 EXOR A2 & A3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 Figure 3 illustrates a schematic drawing of the preferred embodiment of a circuit for implementing the invention's multiple replacement scheme as applied to the case where address factor R 0 is ignored. This circuit comprises some of the elements shown in figure 1c. Address bits A 0 and A 1 are exclusively NORed together by exclusive NOR gate 30. This logic is converted to an exclusive OR by processing the output of gate 30 through inverter 32. Inverter 32's output is connected to the gate of n-channel transistor 34. Transistor 34 is coupled to an input of NAND gate 18 by n-channel transistor 36. N-channel transistor 36 has its gate connected to the gate of n-channel transistor 38 and the output of inverter 40. N-channel transistor 42 is connected by its gate to fuse F and the input of inverter 40 and the drain of transistor 38. The gate of transistor 44 receives the signal from address factor R 1 . The operation of the circuit of figure 3 shall be explained with reference to figure 3 and figure 4 which is a diagram similar to that shown in figure 2 except that defect B is now correctable without having to resort to the use of a greater number of redundant word lines than the two shown. For the case where an address match occurs (indicating the need for redundancy replacement) and a type A or type C word line to word line short exists, fuse F is left intact. All of the address factors, R 1 through R N , are represented as low logic level signals to the gates of the transistors which receive the address factor signals. Since-inverter 40 is connected to supply voltage Vdd through fuse F, inverter 40 outputs a logic low level signal to the gate of transistors 36 and 38. This results in turned off transistors 36 and 38. Therefore, the exclusive OR logic performed on address bits A 0 and A 1 are isolated from input to NAND gate 18. Transistor 42 receives a high logic level signal at its gate to allow coupling of transistor 44 to NAND gate 18. Type A and type C defects are thus corrected by enabling redundant word lines RWL0 and RWL1. For the case where an address match occurs and a type B defect exists, fuse F is blown. Address factors R 2 through R N are represented by a logic low signal to the gates of transistors 16. Transistor 42 is shut off due to its disconnection from supply voltage Vdd through fuse F and due to the pull down of voltage from turned on transistor 38 which receives a logic high level signal from inverter 40. Address factor R 1 now no longer contributes to the decoding of redundant word lines. Transistor 36 is additionally turned on by inverter 40 and the exclusive OR logic circuitry of gate 30 and inverter 32 is coupled to NAND gate 18 through transistor 36. Note, however, that in the case of an address match, inverter 32 outputs a logic low level signal to the gate of transistor 34. Thus the NAND gate 18 input connection remains at a logic high level, thereby allowing redundant word line selection in connection with a logic high enable signal to NAND gate 18. For the case where no defect is noted, fuse F remains intact and at least one of address factors R 1 through R N is at a logic high level, thereby pulling the input of inverter 18 down to a logic low level. This prevents activation of the redundant word lines. Although the invention has been described in detail herein with reference to its preferred embodiment, it is to understood that this description is by way of example only and is not to be construed in a limiting sense. It is to be further understood that numerous changes in the details of the embodiments of the invention, and additional embodiments of the invention, will be apparent to, and may be made by persons of ordinary skill in the art having reference to this description. For instance, this scheme can be applied memory columns so as to provide for instance, bit line redundancy to correct defects on bit lines. Further, although the foregoing invention has been described with regard to a DRAM, it may be used as a redundancy scheme for any memory including read only memories and static random access memories. Note that in the circuits shown implementing the invention's scheme that p-channel transistors, n-channel transistors, and bipolar transistors (n-type or p-type) can be substituted for each other throughout. The fuses disclosed may comprise laser blown fuses as well as electrically blown fuses. It is contemplated that all such changes and additional embodiments are within the scope of the invention as claimed.

Claims: A memory redundancy scheme circuit comprising: a NAND gate (18); a plurality of transistors (16) connected to an input of said NAND gate (18), a controlling terminal of each said transistor (16) suitable for receiving an address factor (R 1 -R N ); characterized by: a logic function circuit (30) operable to perform a selected logic function upon a plurality of address bits (A 0 , A 1 ); a switch (36) connected to said logic function circuit (30) operable to couple said logic function circuit (30) to said selected NAND gate input. A memory redundancy scheme circuit as claimed in claim 1, wherein said logic function circuit (30) is operable to perform logic which is a function of an exclusive OR function. An electronic device including a memory redundancy scheme circuit as claimed in claim 1. An electronic device as claimed in claim 3, wherein the device is a memory, a calculator, a personal computer, a minicomputer, or a micro computer. An electronic system including a memory redundancy scheme circuit as claimed in claim 1. An electronic system as claimed in claim 5, comprising an enhanced definition television system or a high definition television system. A method of memory redundancy replacement comprising the steps of: performing a selected logic function upon a plurality of address bits (A 0 , A 1 ) using a logic function circuit (30); and inputting the result of said logic function (30) into a switch (36) connected to said logic function circuit (30) operable to couple said logic function circuit (30) to a redundant decoding circuit.

Inventors: SUKEGAWA SHUNICHI, SUKEGAWA, SHUNICHI
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1992
Main classification: G06F11
IPC codes: G11C29, G11C11