A semiconductor memory device

Abstract: A semiconductor memory device is provided wherein first data is read out from a first memory cell (101a) within a first readout period and second data is read out from the second memory cell within a second readout period. An amplifier circuit (107), receiving the first and second data, outputs first data signals (D) having a first electric potential level corresponding to the first and second data and a second data signal ( D ) having second electric potential level. A control circuit (120) generates, in response to an external control signal (RAS, CAS), a first control signal (LA2) in each of the first and second readout periods, the first control signal (LA2) indicating first logic level during an enabling period of time within each of the first and second readout periods, otherwise the first control signal (LA2) indicate second logic levels. A first latch circuit (129) latches the first data signal (D) in the respective first and second readout periods and outputs a first latched data signal (D1) at the time of the first control signal (LA2) indicating the first logic level. A second latch circuit (131) latches the second data signals ( D ) in the respective first and second readout periods and outputs a second latch data signal ( D1 ) at the time first control signal (LA2) indicates the first logic level. A reset circuit places the first and second latch circuits (129, 131) in an initial state after the first control signal (LA2) changes from the first logic level to the second logic level in the first readout period and before the first control signal (LA2) changes from the second logic level to the first logic level in the second readout period.

Description: The present invention relates to a memory output latch circuit comprising a latch means for latching complementary output signals from a sense amplifier, a control circuit arranged to produce a reset control signal pulse for each memory read cycle, and a latch resetting circuit responsive to each reset control signal pulse to reset the latch means. A conventional semiconductor memory device employs a memory cell array having memory cells, respectively storing data therein, and associated peripheral circuits. In the peripheral circuits, there is an output data latch circuit to latch, in response to a latch timing control signal, the logic level of a data signal based upon data stored in one of the memory cells and to control, in response to an output timing control signal, a data output circuit so as to output a signal having the appropriate logic level in every readout cycle defined by an external control signal such as RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. The latch and output timing control signals, applied to the data latch circuit, can respectively be generated in a prescribed limited period by the conventional control signal generator, comprised of a conventional combination of logic circuits in response to the external control signal. "Random-Access Memory Output Latch Reset Circuit", IBM Technical Disclosure Bulletin, vol. 31, no. 10, March 1989 discloses a resettable memory output latch circuit. In the disclosed arrangement a single latch circuit is used to latch both of the complementary sense amplifier output signals. US-A-4 797 573 discloses a memory output latch circuit in which the latch output is not reset but is dragged down to the signal earth. It is an object of the present invention to provide a semiconductor memory device employing an improved data latch circuit. It is also an object of the present invention to provide a semiconductor memory device employing a data latch circuit which can correctly perform the readout operation regardless of variations in the control signal generation timing. A memory output latch circuit according to the present invention is characterized in that the latch means comprises first and second latches for latching respective ones of said complementary output signals, the output of the first latch is applied to a first output means, the output of the second latch is applied to a second output means, the control circuit is arranged to produce an output enable signal pulse for each memory read cycle, the output means are responsive to the output enable signal pulses to pass the outputs of the latches and each reset control signal pulse is produced between two successive output enable signal pulses. Preferably, the control circuit includes a delay circuit for producing a pulse at a predetermined time after the end of each output enable pulse, the reset control signal pulse being derived from said pulse. Preferably, the latch means includes a transfer gate before each of the latches and the control circuit is arranged to produce an input control pulse during each output enable pulse, the transfer gates being responsive to the input control pulses to pass said complementary output signals to the latches. An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of the conventional memory cell array and some of associated peripheral circuits; FIG. 2 is a circuit diagram of a data latch circuit in accordance with the preferred embodiment of the present invention; FIG. 3 is a circuit diagram of a conventional data output circuit controlled by the data latch circuit shown in FIG. 2; and FIGS. 4A-4I are timing charts of control signals and data signals to explain the readout operation. A memory cell array 101 and associated peripheral circuit of a conventional semiconductor memory device are shown in FIG. 1. The memory cell array 101 employs a plurality of memory cells, respectively storing data therein such as memory cells 101a and 101b arranged in the matrix form. In every read cycle defined by the external control signals such as RAS (Row Address Strobe) and CAS (Column Address Strobe) signals, one of memory cells in the memory cell array 101 is selected by row and column decoders 103 and 105 in response to external address signals. The selected memory cell applies a certain electric potential, according to the data stored therein, to a sense amplifier circuit 107. The sense amplifier circuit 107 compares the applied electric potential from the selected memory cell with the reference electric potential and amplifies the electric potential difference between the applied and reference electric potential. As the result of the comparison, the sense amplifier circuit 107 outputs a first data signal D having either high or low electric potentials and a second data signal D having the potential opposite to that of the first data signal. The foregoing circuits are well known in the art, for example, employed in a 4 mega-bit dynamic RAM MSM514100 manufactured by OKI electric industry Co., Ltd. and explained in MEMORY DATA BOOK 1990/1991, page 220-233, issued on February, 1990. In this dynamic RAM, the high electric potential of first and second data signal is substantially a supply voltage Vcc (5V) while the low electric potential is substantially Ground (0V). And the reference electric potential is substantially half of the supply voltage level. There will be explained the embodiment of the present invention hereunder, assuming for simplification that according to the external address signals, the memory cell 101a storing logic ONE level data is selected in a first readout period of time and, thereafter, the memory cell 101b storing logic ZERO level data is selected in a second readout period of time following the first readout period of time. At the beginning (period of T1 in FIG. 4I) of the first readout period of time, the sense amplifier circuit 107 outputs a first data signal D having a high electric potential (Vcc) through a first data line 108 and a second data signal D having a low electric potential (ground) through a second data line 109 because of the memory cell 101a storing the logic ONE level as shown in FIG. 4E. A data latch circuit 110 as shown in FIG. 2 has first and second input terminals 111 and 113 respectively to receive a pair of the first and second data signals D and D through the respective first and second data lines 108 and 109. The data latch circuit also receives a first data latch signal LA1 at a terminal 115 thereof, a second data latch signal LA2 at a terminal 117 thereof and an activation signal A at a terminal 119 thereof. The first and second data latch signals LA1 and LA2 and activation signal A can be generated by a conventional control signal generator 120 employing conventional combination of logic circuits in response to RAS and CAS signals. The activation signal A controls the output of the data latch circuit 110 and is synchronized with RAS or CAS signals. The logic level of activation signal A is changed from a low (second) logic level to a high (first) logic level and then changed from the high logic level to the low logic level in every readout period of time as shown in FIG. 4A. The first data latch signal LA1 can be considered as a high level one shot pulse generated in every readout period of time to reset the data latch circuit 110 as shown in FIG. 4B. The second data latch signal LA2 can be considered as a low level one shot pulse generated in every readout period of time to provide with the data latch circuit the timing to latch the first and second data signals D and D after the data latch circuit is reset in response to the first data latch signal LA1 as shown in FIG. 4C. At the period of T2 in the first readout period of time, as shown in FIGS. 4B and 4C, a NAND circuit 121 receives the first data latch signal LA1 having the high logic level changed from the low logic level at one input terminal thereof and the second data latch signal LA2 having the high logic level at the other input terminal thereof, thus the output of NAND circuit 121 is changed from the high logic level to the low logic level. Therefore an output of a NAND circuit 124, receiving the output of the NAND circuit 121 at one input terminal thereof and a reset control signal having the high logic level at the other input terminal thereof, is changed to the high logic level and both of negative channel type MOS transistors Q5 and Q6 of a reset circuit 130, receiving the output of the NAND circuit 124 at the gate electrode thereof, are placed in ON status. Consequently, as shown in FIG. 4F a pair of third and fourth data line D1 and D2 are maintained at the low logic level (Ground level) at least at the period of T2 even if the third and second data line had stored electric charges therein due to electric noises generated at the previous period and, further, both of a first Flip-Flop circuit 129 comprised of two invertor circuit INV1 and INV2 and a second Flip-Flop circuit 131 comprised of two invertor INV3 and INV4 are respectively reset so as to output the low logic level. At the period of T3, as shown in FIGS. 4B and 4C, as the first data latch signal LA1 is maintained at the high logic level and the second data latch signal LA2 is changed to the low logic level, MOS transistor Q1, Q2, Q3 and Q4 are placed in ON status at the same time, while the MOS transistors Q5 and Q6 is placed in OFF status. Because the gate electrodes of positive channel type MOS transistors Q1 and Q3 respectively receive the second data latch signal LA2 through two inverters 133 and 135, the gate electrodes of negative channel type MOS transistors Q2 and Q4 respectively receive the second data latch signal LA2 through the invertor 133 while the gate electrodes of negative channel type MOS transistors Q5 and Q6 in the reset circuit 130 respectively receive the low level output signals from the NAND circuit 124 in response to the second data latch signal LA2. According to the MOS transistors Q1, Q2, Q3 and Q4 being in the ON status, the first Flip-Flop circuit 129 latches the high logic level corresponding to the high electric potential of the first data signal D and outputs a third data signal D1 having the high logic level to the third data line 125, while the second Flip-Flop circuit 131 latches the low logic level corresponding to the low electric potential of the second data signal D and output a fourth data signal D1 having the low logic level to the fourth data line 127 as shown in FIG. 4F. In order to maintain the logic level of the respective third and fourth data line 125, 127, the reset circuit 130 further has negative channel type transistors Q7 and Q8. The transistor Q7 has a source electrode, connected to Ground, a drain electrode, connected to the fourth data line 127 and a gate electrode, connected to the third data line 125, while the transistor Q8 has a source electrode, connected to Ground, a drain electrode, connected to the third data line 125 and a gate electrode, connected to the fourth data line 127. Thus, the transistor Q7 is in the ON status, while the transistor Q8 is in the OFF status since the third data signal D1 is in the high logic level and the fourth data signal D1 is in the low logic level. In the period of T3, a NAND circuit 169 in FIG. 2 receives the third data signal D1 having the high logic level at one terminal thereof, connected with the third data line 125 and the activation signal A having the high logic level at the other terminal thereof, connected with the terminal 119, thus outputs a fifth data signal D2 having the low logic level to an output terminal 133. At the same time, a NAND circuit 171 in FIG. 2 receives the fourth data signal D1 having the low logic level at one terminal thereof, connected with the fourth data line 127 and the activation signal A having the high logic level at the other terminal thereof, connected with the terminal 119, thus outputs a sixth data signal D2 having the high logic level to an output terminal 135. This can be to say that the data latch circuit 110 may output from the respective output terminals 133 and 135 thereof the respective fifth and sixth data signals D2 and D2 having the opposite logic level to the respective third and fourth data signals D1 and D1 , provided that the activation signal A is the high logic level. In case of the activation signal A being the low logic level, the data latch circuit 110 outputs the fifth and sixth data signals D2 and D2 respectively having the high logic level regardless of the logic level of the third and fourth data signals D1 and D1 . Therefore, as shown in FIG. 4G, the NAND circuit 169 and 171 in the data latch circuit 110 respectively output the fifth data signal D2 having the low logic level and the sixth data signal D2 having the high logic level during the period of T3 and the beginning of a period of T4 i.e. until the activation signal A is changed to the low logic level. The data latch circuit 110, further, employs a delay circuit 151. The delay circuit 151 has a NAND circuit 122 whose one terminal is connected to the terminal 119 through an inverter 153 and the other terminal is connected to the output terminal of the inverter 153 through three inverters 155, 157 and 159. The delay circuit 151 detects that the activation signal A has been changed from the high logic level to the low logic level and output, in response to the result of the detection, the low level one shot pulse during a prescribed period of time set by the inverters. There will be explained about the operation of the delay circuit 122 as follows: First, during the activation signal having the high logic level being generated, since the NAND circuit 122 receives the low level signal outputted from the output terminal of the inverter 153 at one terminal thereof and the high level signal outputted from the output terminal of the inverter 155, the NAND circuit 122 outputs the high level signal. Second, at the time of the activation signal having been changed from the high level to the second level, since the NAND circuit receives the high level signal from the output terminal of the inverter 153 at one terminal thereof and the low level signal changed from the high level signal after the prescribed period of time, corresponding to the delay time due to the inverters 155, 157 and 159, after the inverter 153 outputs the high level signal, the NAND circuit 122 outputs the low level signal during the prescribed period of time T5, as shown in FIG. 4D, and, then, outputs the high level output signal. In the period of time T5, since the NAND circuit 124 receives the low level signal outputted from the NAND circuit 122 at one terminal thereof and the high level signal outputted from the NAND circuit 121 at the other terminal thereof, the NAND circuit 124 outputs the high level signal to the gate of the negative channel type MOS transistors Q5 and Q6 in the reset circuit 130. Thereby, the second pair of the third and fourth data lines 125 and 127 are reset to the low level (Ground) and the first and second Flip-Flop 129 and 131 are also reset so as to respectively output the respective third and fourth data signal D1 and D1 each having the low logic level as shown in FIG. 4F. By the way, the number of the inverters 155, 157 and 159 in the delay circuit 151 can be changeable as long as the number of the inverters is odd and should be selected so as to provide the low level signal with the NAND circuit 124 during a sufficient period of time to reset both of the Flip-Flop circuits 129 and 131. In the period of time T6 after T5, all of the signals, applied to the data latch circuit 110, is back to the initial status of the first readout period of time, as shown in FIGS. 4A-4G. Then, the first readout period of time is ceased and the second readout period of time will be successively begun in response to the external control signals. At the beginning (period of T7 in FIG. 4I) of the second readout period of time following the first readout period of time, the sense amplifier circuit 107 outputs a first data signal D having a low electric potential (Ground) through a first data line 108 and a second data signal D having a high electric potential (Vcc) through a second data line 109 because of the second memory cell 101b storing the logic ZERO level. A data latch circuit 110 as shown in FIG. 2 has first and second input terminals 111 and 113 respectively to receive a pair of the first and second data signals D and D through the respective first and second data lines 108 and 109. The data latch circuit also receives a first data latch signal LA1 at a terminal 115 thereof, a second data latch signal LA2 at a terminal 117 thereof and an activation signal A at a terminal 119 thereof. The first and second data latch signals LA1 and LA2 and activation signal A are generated by a conventional control signal generator 120 in response to RAS and CAS signals. The activation signal A control the output of the data latch circuit 110 and is synchronized with RAS or CAS signals. The first data latch signal LA1 is used to reset the data latch circuit 110. The second data latch signal LA2 provides with the data latch circuit the timing to latch the first and second data signals D and D after the data latch circuit is reset in response to the first data latch signal LA1 as shown in FIGS. 4B and 4C. At the period of T8 in the second readout period of time, as shown in FIGS. 4B and 4C, a NAND circuit 121 receives the first data latch signal LA1 having the high logic level changed from the low logic level at one input terminal thereof and the second data latch signal LA2 having the high logic level at the other input terminal thereof, thus the output of NAND circuit 121 is changed from the high logic level to the low logic level. Therefore an output of a NAND circuit 124, receiving the output of the NAND circuit 121 at one input terminal thereof and a reset control signal having the high logic level at the other input terminal thereof, is changed to the high logic level and both of negative channel type MOS transistors Q5 and Q6 of a reset circuit 130, receiving the output of the NAND circuit 124 at the gate electrode thereof, are placed in ON status. Consequently, as shown in FIG. 4F a pair of third and fourth data line D1 and D1 are maintained at the low logic level (Ground level) at least at the period of T2 even if the third and second data line had stored electric charges therein due to electric noises generated at the previous period and, further, both of a first Flip-Flop circuits 129 comprised of two inverter circuits INV1 and INV2 and a second Flip-Flop circuit 131 comprised of two inverters INV3 and INV4 are respectively reset so as to output the low logic level. At the period of T9, as shown in FIGS. 4B and 4C, as the first data latch signal LA1 is maintained at the high logic level and the second data latch signal LA2 is changed to the low logic level, MOS transistors Q1, Q2, Q3 and Q4 are placed in ON status at the same time, while the MOS transistors Q5 and Q6 is placed in OFF status. According to the MOS transistors Q1, Q2, Q3 and Q4 being in the ON status, the first Flip-Flop circuit 129 latches the low logic level corresponding to the low electric potential of the first data signal D and outputs a third data signal D1 having the low logic level to the third data line 125, while the second Flip-Flop circuit 131 latches the high logic level corresponding to the high electric potential of the second data signal D and output a fourth data signal D1 having the high logic level to the fourth data line 127 as shown in FIG. 4F. In order to maintain the logic level of the respective third and fourth data line 125, 127, the transistor Q7 of the reset circuit 130 is placed in the OFF status, while the transistor Q8 is placed in the OFF status since the third data signal D1 is in the low logic level and the fourth data signal D1 is in the high logic level. In the period of T9, a NAND circuit 169 in FIG. 2 receives the third data signal D1 having the low logic level at one terminal thereof, connected with the third data line 125 and the activation signal A having the high logic level at the other terminal thereof, connected with the terminal 119, thus outputs a fifth data signal D2 having the high logic level to an output terminal 133. At the same time, a NAND circuit 171 in FIG. 2 receives the fourth data signal D1 having the high logic level at one terminal thereof, connected with the fourth data line 127 and the activation signal A having the high logic level at the other terminal thereof, connected with the terminal 119, thus outputs a sixth data signal D2 having the low logic level to an output terminal 135. As shown in FIG. 4G, the NAND circuits 169 and 171 in the data latch circuit 110 respectively continue to output the fifth data signal D2 having the high logic level and the sixth data signal D2 having the low logic level during the period of T9 and the beginning of a period of T10 i.e. until the activation signal A is changed to the low logic level. In the period of time T11, since the NAND circuit 124 receives the low level signal outputted from the NAND circuit 122, according to the detection of the activation signal A being changed from the high to the low logic level by means of the delay circuit 151, at one terminal thereof and the high level signal outputted from the NAND circuit 121 at the other terminal thereof, the NAND circuit 124 outputs the high level signal to the gate of the negative channel type MOS transistors Q5 and Q6 in the reset circuit 130. Thereby, the second pair of the third and fourth data lines 125 and 127 are reset to the low level (Ground) and the first and second Flip-Flops 129 and 131 are also reset so as to respectively output the respective third and fourth data signals D1 and D1 each having the low logic level, as shown in FIG. 4F. In the period of time T12 after T11, all of the signals, applied to the data latch circuit 110, is back to the initial status of the second readout period of time, as shown in FIGS. 4A-4G. Now there will be explained hereunder about a data output from a conventional data output circuit 140 shown in FIG. 3 in response to the fifth and sixth data signals D2 and D2 in every readout cycle. The data output circuit 140, shown in FIG. 3, receives the fifth data signal D2 from the output terminal 133 at a terminal 141 and the sixth data signal D2 from the output terminal 135 at a terminal 143. In case of both of the fifth and sixth data signals D2, D2 being in the high logic level i.e. in the periods of T1, T2, T5, T6, T7, T8, T11 and T12, both negative channel type MOS transistors Q9 and Q10 are placed in the OFF status and, then, the output terminal 142 is clamped at certain electric potential level such as 1.32 volts by means of a conventional clamp circuit (not shown) so as to avoid placing the output terminal 142 in the floating condition. In case of the fifth data signal D2 being in the low logic level and the sixth data signal D2 being in the high logic level, i.e. the first memory cell 101a storing the logic ONE level therein, a conventional bootstrap circuit 145 applies a super (boosted) voltage (Vcc + Vth) higher than the supply voltage Vcc to the gate electrode of the transistor Q9. Therefore, in the periods of T3 and T4, since the transistor Q9 is fully placed in the ON status so as to apply a maximum value equal to the supply voltage Vcc to the output terminal 142, while the transistor Q10, of which gate electrode receive the sixth data signal D2 through an inverter 149, is placed in the OFF status, the output terminal 142 outputs the high level signal substantially equal to the supply voltage level Vcc in the periods of T3 and T4 of the first readout period of time as shown in FIG. 4H. In case of the fifth data signal D2 being in the high logic level and the sixth data signal D2 being in the low logic level, i.e. the second memory cell 101b storing the logic ZERO level therein, a conventional bootstrap circuit 145 does not work and applies the low level signal (Ground) to the gate electrode of the transistor Q9 so as to place the transistor Q9 in the OFF status. While the transistor Q10, of which gate electrode receives the sixth data signal D2 through an inverter 149, is placed in the ON status, the output terminal 142 outputs the low level signal substantially equal to Ground in the periods of T9 and T10 of the second readout period of time, as shown in FIG. 4H. There has been explained hereinbefore about the first and second readout period of time in the readout cycle of the DRAM, but in another readout period of time following the first or second readout periods, the data stored in another memory cell may be successively or intermittently read out therefrom according to the similar operation as mentioned above. As mentioned above, according to the invention, since both the first and second Flip-Flop circuits 129 and 131 are reset so as to respectively output the initial logic level signals, such as the low logic level signals, by means of the delay circuit 151 and the reset circuit 130 prior to the activation signal A being changed from the low logic level to the high logic level in the second readout period of time, preferably within the first read cycle, the output data, read out in the first readout period will be never read out again in the second readout periods regardless of the activation signal A being changed to the high logic level in the second readout time. In order to explain the aspect of the present invention assuming that no delay circuit 151 is employed in the data latch circuit 110, the first and second Flip-Flop circuits 129 and 131 respectively output the third and fourth data signals D1 and D1 , latched in the first readout period of time, until the period of T8 as indicated by a broken line in FIG. 4F. Thus, according to the activation signal A being changed to the high logic level in the period of T7 of the second period of time, the fifth data signal D2 having the low logic level and the sixth data signal D2 having the high logic are unnecessarily outputted from the data latch circuit 110 as indicated by a broken line in FIG. 4G, and, consequently, the data output circuit 140 outputs a high level signal from the output terminal 142 thereof as indicated by a broken line in FIG. 4H in the period of T7. The unnecessary outputs from the data latch circuit 110 cause undesirable power and time consumption to the data output circuit 140 and, consequently, voltage and signal noises to the semiconductor memory device. Assuming the second memory cell 101b stores the logic ONE level therein instead of the logic ZERO level, the bootstrap circuit 145 might not generate the sufficient super voltage at the period of T9 and T10 and, consequently, the output terminal 142 outputs the high level signal below the supply voltage level Vcc during the period of T9 and T10 because of the short interval (between T7 and T9) of the operation of the bootstrap circuit 145. There is another way other than the application of the present invention to avoid such demerits. That is to control the activation signal so as to be changed to the high logic level within the period of T8, but is required to exactly control the activation signal. Contrary to this, the memory device according to the present invention does not have to control the activation signal A so as to be changed within the period of T8 as long as the control signal A is changed the high logic level within the period of from T7 to T8, therefore can be easily designed at this point. While the invention has been particularly shown and described above with reference to preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention. For example, in the embodiment discussed above, the high logic level is corresponding to the supply voltage level (Vcc = 5V) and the low logic level is corresponding to the ground level (Vss = 0V), but the high and low logic level may be respectively corresponding to other voltage levels as long as the readout operation can be effectively performed.

Claims: A memory output latch circuit comprising a latch means (129,131) for latching complementary output signals (D, D ) from a sense amplifier (107), a control circuit (120,121,122,155,157,159,153) arranged to produce a reset control signal pulse for each memory read cycle, and a latch resetting circuit (130) responsive to each reset control signal pulse to reset the latch means, characterized in that the latch means comprises first and second latches for latching respective ones of said complementary output signals, the output (D1) of the first latch (129) is applied to a first output means (169), the output ( D 1) of the second latch (131) is applied to a second output means (171), the control circuit is arranged to produce an output enable signal pulse (A) for each memory read cycle, the output means are responsive to the output enable signal pulses to pass the outputs of the latches and each reset control signal pulse is produced between two successive output enable signal pulses. A circuit according to claim 1, wherein the control circuit includes a delay circuit (151) for producing a pulse at a predetermined time after the end of each output enable pulse, the reset control signal pulse being derived from said pulse. A circuit according to claim 1 or 2, wherein the latch means includes a transfer gate before each of the latches and the control circuit is arranged to produce an input control pulse (LA2) during each output enable pulse, the transfer gates being responsive to the input control pulses to pass said complementary output signals to the latches. A semiconductor memory device including a memory cell array, a sense amplifier and a circuit according to claim 1, 2 or 3.

Inventors: MURASHIMA YOSHIHIRO, SUYAMA JUNICHI, MURASHIMA, YOSHIHIRO, SUYAMA, JUNICHI, Murashima, Yoshihiro, c/o Oki Electric Ind. Co., Suyama, Junichi, c/o Oki Electric Ind. Co. Ltd.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1992
Main classification: G11C7
IPC codes: G11C11, G11C7