Four quadrant analog multiplier circuit of floating input type

Abstract: A four quadrant analog multiplier circuit including first to third squaring circuits 1 to 3 each of which is composed of first and second differential circuits each of which is formed of first and second MOS transistors M 1 and M 2 , M 3 and M 4 , M 5 and M 6 , M 7 and M 8 , M 9 and M₁₀, and M₁₁ and M₁₂. A gate width-to-length ratio W 2 /L 2 of the second MOS transistor M 2 is larger than a gate width-to-length ratio W 1 /L 1 of the first MOS transistor M 1 . A gate of the first MOS transistor M 1 , M 5 and M 9 of each first differential circuit is connected to a gate of the second MOS transistor M 4 , M 8 and M₁₂ of the corresponding second differential circuit. A gate of the second MOS transistor M 2 , M 6 and M₁₀ of each first differential circuit is connected to a gate of the first MOS transistor M 3 , M 7 and M₁₁ of the corresponding second differential circuit. The gates of the MOS transistors M 1 and M 9 are connected in common to receive a first input signal V 1 , and the gates of the MOS transistors M 5 and M₁₁ are connected in common to receive a second input signal V 1 . Drains of the MOS transistors M 1 , M 3 , M 5 , M 7 , M₁₀, and M₁₂ are connected in common to a first output current terminal, and drains of the MOS transistors M 2 , M 4 , M 6 , M 8 , M 9 , and M₁₁ are corrected in common to a second output current terminal. A differential current between the first and second output current terminals is indicative of a product of the input signals V 1 and V 2 .

Description: SPECIFICATION Background of the Invention Field of the invention The present invention relates to an analog multiplier circuit, and more specifically to a high precision four quadrant analog multiplier circuit of a so-called floating input type, which can be effectively used particularly for modulation and demodulation of an analog signal. Description of related art Known conventional analog multiplier circuits include a Gilbert multiplier circuit composed of only bipolar transistors, a MOS multiplier circuit formed by substituting MOS transistors for the bipolar transistors of the Gilbert multiplier circuit, and a CMOS multiplier circuit formed by constituting the Gilbert multiplier circuit by CMOS transistor circuits. In the Gilbert multiplier circuit, when the magnitude of each of two input signal voltages V 1 and V 2 is extremely smaller than 2V T (where V T =kT/q, k : Boltzmann's constant, T : absolute temperature, q : electric charge of unit elecrtron), an output current is substantially in proportion to V 1 •V 2 . Namely, when each of the input signals is a small signal, the Gilbert circuit functions as the multiplier. In addition, each of the input signals must be applied in the formed of a differential signal Similarly, the MOS multiplier circuit functions as the multiplier when a pair of input signals are small. In addition, this MOS mulitplier circuit is disadvantageous in that a linear operation range for one of the input signals is smaller than that for the other input signal. Furthermore, the CMOS multiplier circuit also has only a narrow input signal range which can ensure a good linear operation. In each of the MOS multiplier circuit and the CMOS multiplier circuit, furthermore, each of the input signals must also be applied in the form of a differential signal. As mentioned above, the conventional multiplier circuits have been disadvantageous in that the dynamic range is narrow and each input signals must also be applied in the form of a differential signal. IEEE International symposium on circuits and systems, Vol.3, 1986, New York US, pages 1157-1160 describes an analog multiplier circuit comprising a squaring circuit comprising first and second differential circuits, each of which is formed of first and second MOS transistors, a gate of the first MOS transistor of the first differential circuit being connected to a gate of the second MOS transistor of the second differential circuit, and a gate of the second MOS transistor of the first differential circuit being connected to a gate of the first MOS transistor of the second differential circuit. A gate width-to-length ratio of each second MOS transistor is larger than a gate width-to-length ratio of the associated first MOS transistor. Summary of the Invention Accordingly, it is an object of the present invention to provide an analog multiplier circuit which has overcome the above-mentioned defect of the conventional one. Another object of the present invention is to provide a four quadrant analog multiplier circuit having a high degree of precision and of the so-called floating input type allowing that each input signal can be applied either in the form of a differential signal or in a floating input mode. Accordingly, the present invention provides a four quadrant analog multiplier circuit comprising: a first squaring circuit comprising first and second differential circuits, each of which is formed of first and second MOS transistors, a gate width-to-length ratio W 2 /L 2 of each second MOS transistor being larger than a gate width-to-length ratio W 1 /L 1 of the associated first MOS transistor, a gate of the first MOS transistor of the first differential circuit being connected to a gate of the second MOS transistor of the second differential circuit, a gate of the second MOS transistor of the first differential circuit being connected to a gate of the first MOS transistor of the second differential circuit; characterised in that said multiplier circuit further comprises second and third such squaring circuits, the gates of the first MOS transistors of the first differential circuits of the first and third squaring circuits being connected in common to receive a first input signal V 1 , the gate of the first MOS transistor of the first differential circuit of the second squaring circuit and the gate of the first MOS transistor of the second differential circuit of the third squaring circuit being connected in common to receive a second input signal V 2 , drains of the first MOS transistors, of the first and second differential circuits of the first and second squaring circuits and of the second transistors of the first and second differential circuits of the third squaring circuit being connected in common to a first current terminal I 1 , and drains of the second MOS transistors of the first and second differential circuits of the first and second squaring circuits and of the first transistors of the first and second differential circuits of the third squaring circuit being connected in common to a second output current terminal I 2 , whereby a differential current between the first and second output current terminals is indicative of a product of the input signals V 1 and V 2 . Preferably, the sources of the first and second MOS transistors of each first and second differential circuit of said first to third squaring circuits are connected in common to constant current sources, a common input terminal being connected to the gate of said second MOS transistor of the first differential circuit of each of said first and second squaring circuits, the connections of the drains of the first MOS transistors of the first differential circuits of the first and second squaring circuits and of the second transistors of the first and second differential circuits of the third squaring circuit to said first output current terminal, and of the drains of the second MOS transistors of the second differential circuit of the first and second squaring circuits and of the first transistors of the first and second differential circuits of the third squaring circuit to said second output current terminal forming an addition circuit; wherein said first squaring circuit is adapted to receive said first input signal to square said first input signal, said second squaring circuit is adapted to receive said second input signal to square said second input signal, said third squaring circuit is adapted to receive said first and second input signals to square a difference between said first and second inputs, and said addition circuit is adapted to subtract an output of said third squaring circuit from a sum of the outputs of said first and second squaring circuits. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of an embodiment of the multiplier circuit in accordance with the present invention; Figure 2 is a block diagram illustrating an operation of the multiplier circuit shown in Figure 1; and, Figure 3 is a graph illustrating an operation characteristics of the multiplier circuit shown in Figure 1; and Figure 4 is a circuit diagram of a modification of the multiplier circuit shown in Figure 1. Description of the Preferred embodiments Referring to Figure 1, there is shown a circuit diagram of an embodiment of the four quadrant analog multiplier circuit in accordance with the present invention, The shown multiplier circuit comprises a first squaring circuit 1 formed of MOS transistors M1 to M4, a second squaring circuit 2 formed of MOS transistors M5 to M8 and a third squaring circuit 3 formed of MOS transistors M9 to M12. In the first squaring circuit 1. a first differential circuit is formed of the MOS transistors M1 and M2 having their sources connected in common to a constant current source A1 of a constant current I 0 , and a second differential circuit is formed of the MOS transistors M3 and M4 having their sources connected in common to a constant current source A2 of a constant current I 0 . A gate of the MOS transistor M1 of the first differential circuit is connected to a gate of the MOS transistor M4 of the second differential circuit, and a gate of the MOS transistor M2 of the first differential circuit is connected to a gate of the MOS transistor M3 of the second differential circuit. In the second squaring circuit 2, a first differential circuit is formed of the MOS transistors M5 and M6 having their sources connected in common to a constant current source A3 of a constant current I 0 , and a second differential circuit is formed of the MOS transistors M7 and M8 having their sources connected in common to a constant current source A4 of a constant current I 0 . A gate of the MOS transistor M5 of the first differential circuit is connected to a gate of the MOS transistor M8 of the second differential circuit, and a gate of the MOS transistor M6 of the first differential circuit is connected to a gate of the MOS transistor M7 of the second differential circuit. In the third squaring circuit 3, a first differential circuit is formed of the MOS transistors M9 and M10 having their sources connected in common to a constant current source A5 of a constant current I 0 , and a second differential circuit is formed of the MOS transistors M11 and M12 having their sources connected in common to a constant current source A6 of a constant current I 0 . A gate of the MOS transistor M9 of the first differential circuit is connected to a gate of the MOS transistor M12 of the second differential circuit, and a gate of the MOS transistor M10 of the first differential circuit is connected to a gate of the MOS transistor M11 of the second differential circuit. A first input signal V 1 is supplied between a first signal input terminal 4 and a first antiphase input terminal 5, and a second input signal V 2 is supplied between a second signal input terminal 6 and a second antiphase input terminal 7. The first signal input terminal 4 is connected to the gates of the MOS transistors M1 and M4 of the first squaring circuit 1 and also the gates of the MOS transistors M9 and M12 of the third squaring circuit 3. In addition, the second signal input terminal 6 is connected to the gates of the MOS transistors M5 and M8 of the second squaring circuit 2 and also the gates of the MOS transistors M10 and M11 of the third squaring circuit 3. The first antiphase input terminal 5 and the second antiphase input terminal 7 are connected to each other and also connected to the gates of the MOS transistors M2 and M3 of the first squaring circuit 1 and the gates of the MOS transistors M6 and M8 of the second squaring circuit 2. Furthermore, drains of the MOS transistors M1 and M3 of the first squaring circuit 1, drains of the MOS transistors M5 and M7 of the second squaring circuit 2 and drains of the MOS transistors M10 and M12 of the third squaring circuit 3 are connected in common to an output current signal terminal 8 for an output current signal I 1 . In addition, drains of the MOS transistors M2 and M4 of the first squaring circuit 1, drains of the MOS transistors M6 and M8 of the second squaring circuit 2 and drains of the MOS transistors M9 and M11 of the third squaring circuit 3 are connected in common to an output current signal terminal 9 for an output current signal I 2 . This drain connection of the MOS transistors M1 to 12 constitutes a wired addition circuit. With the above mentioned arrangement, the first input signal V 1 is supplied between the first signal input terminal 4 and the first antiphase input terminal 5, and the second input signal V 2 is supplied between the second signal input terminal 6 and the second antiphase input terminal 7. Therefore, each of the first and second input signals V 1 and V 2 can be applied in the form of a differential signal. However, since the first antiphase input terminal 5 and the second antiphase input terminal 7 are connected to each other, the first antiphase input terminal 5 and the second antiphase input terminal 7 can be grounded. In this case, the first and second input signals V 1 and V 2 are supplied to only the first and second signal input terminals 4 and 6, respectively, in the form of a single line signal (not in the the form of a differential signal). This signal input type enabling the above mentioned two different signal input modes is called a "floating input type". The function of the multiplier circuit shown in Figure 1 can be shown by a function block diagram of Figure 2. In Figure 2, a squaring circuit 21 for squaring the input signal V 1 corresponds to the first squaring circuit 1 shown in Figure 1, and a squaring circuit 22 for squaring the input signal V 2 corresponds to the second squaring circuit 2 shown in Figure 1. In addition, a squaring circuit 23 for squaring a difference (V 1 - V 2 ) between the input signal V 1 and the input signal V 2 corresponds to the first squaring circuit 3 shown in Figure 1. An addition circuit 24 coupled to respective outputs of the squaring circuits 21 to 23, adds the outputs of the squaring circuits 21 and 22 and subtracts the output of the squaring circuit 23 from the added outputs of the squaring circuits 21 and 22. This addition circuit 24 corresponds to the wired addition circuit constituted of the above mentioned drain connection of the MOS transistors M1 to 12 in Figure 1. In other words, the addition circuit 24 is included in the first to third squaring circuits 1 to 3 shown in Figure 1. In the circuit shown in Figure 2, if the input signals V 1 and V 2 are applied, an output signal Vo of the addition circuit 24 is expressed by the following equation. V 1 2 + V 2 2 - (V 1 - V 2 ) 2 = 2V 1 V 2 Namely, a product 2V 1 V 2 of the input signals V 1 and V 2 can be obtained as a result of the multiplication of the input signals V 1 and V 2 . In the circuit shown in Figure 1, a ratio W/L of a gate width W to a gate length L of the MOS transistors M1 to M12 is expressed by W 1 /L 1 to W 12 /L 12 , respectively. The MOS transistors of each of the differential circuits of each of the three squaring circuits 1 to 3 are designed such that the ratio W/L of an odd-numbered MOS transistor is larger than the ratio W/L of an even-numbered MOS transistor W 2 /L 2 W 1 /L 1 = W 4 /L 4 W 3 /L 3 = W 6 /L 6 W 5 /L 5 = W 8 /L 8 W 7 /L 7 = W 10 /L 10 W 9 /L 9 = W 12 /L 12 W 11 /L 11 = k(> l) where L 1 =L 3 =L 5 =L 7 =L 9 =L 11 In addition, drain currents I d1 to I d4 of the MOS transistors M1 to M4 in the first squaring circuit 1 are expressed by the following equation. I d1 = α (V gs1 -V t ) 2 I d2 = kα (V gs2 -V t ) 2 I d3 = α(V gs3 -V t ) 2 I d4 = kα (V gs4 -V t ) 2 ∵ α = µ n COX 2 W 1 L 1 when µ n is a mobility of MOS transistor; COX is a gate capacitance per unit area; and V t is a threshold voltage. In addition, the drain currents I d1 to I d4 and gate-source voltages V gs1 to V gs4 of the MOS transistors M1 to M4 have the following relations, respectively. I d1 +I d2 = I 0 I d3 + I d4 = I 0 V gs1 -V gs2 = V gs4 - V gs3 = V 1 From the above mentioned equations, a difference (Id 1 - Id 2 ) between the drain currents I d1 and I d2 of the MOS transistors M1 and M2, and a difference (I d3 - I d4 ) between the drain currents I d3 and I d4 of the MOS transistors M3 and M4 are expressed as follows: Accordingly, a differential output current ΔI 1 of the squaring circuit 1 is obtained from the following equation: As will be apparent from the equation (13), the differential output current ΔI 1 of the squaring circuit 1 is in proportion to a square of the input signal V 1 . Namely, the circuit 1 functions as a squaring circuit. Similarly, differential output currents ΔI 2 and ΔI 3 of the squaring circuits 2 and 3 are expressed as follows: Therefore, an overall differential current ΔI of the multiplier circuit shown in Figure 1 is expressed as follows: Accordingly, as will be apparent from the equation (16), the differential current ΔI of the multiplier circuit shown in Figure 1 can be expressed by a product of the input signals V 1 and V 2 , and therefore, functions as a multiplier circuit. In addition, if the constant current value of each of the constant current sources A5 and A6 of the squaring circuits 3 is set to be 2I 0 , the item of I 0 in the equation (16) is cancelled. In this case, the differential output current ΔIa can be obtained from the following equations: The differential output current ΔIa corresponds to a difference between the output current I 1 and the output current I 2 . A similar effect can be obtained by adding a no-input squaring circuit which has the same construction as that of the squaring circuits 1 and 2 and in which a gate of each of MOS transistors M13 to 16 are connected to the common input line of the first and second antiphase input terminals 5 and 7, as shown in Figure 4. In this case, the constant current sources A1 to A8 has the same constant current capacity. As seen from the equation (18), the differential output current ΔIa of the multiplier circuit is determined by only the product of the input signals V 1 and V 2 and a proportion constant, which is also determined by physical property and mask size of the MOS transistors. In addition and more importantly, no approximation is made in the process of calculation for deriving the equations (16) to (18). Therefore, the precision of the multiplication operation characteristics of the disclosed multiplier circuit is considered to be governed by a proportion precision of circuit elements, namely, the MOS transistors. Accordingly, if the disclosed multiplier circuit is formed on a semiconductor integration circuit, it is possible to obtain a multiplier circuit having a high precision as an inherent nature. Figure 3 illustrate a result of a simulation of the operation property of the disclosed multiplier circuit. In the disclosed multiplier circuit, since each squaring circuit is composed of a pair of differential circuits each formed of first and second MOS transistors having a relation in which a gate width-to-length ratio of the second MOS transistor is larger than a gate width-to-length ratio of the first MOS transistor, the circuit can effectively utilize the voltage-current characteristics of MOS transistors having a square characteristics. Thus, in an input signal range capable of ensuring the good linearity, the multiplier circuit can operates in the floating input type or system.

Claims: A four quadrant analog multiplier circuit comprising: a first squaring circuit (1) comprising first and second differential circuits, each of which is formed of first and second MOS transistors (M 1 and M 2 , M 3 and M 4 ), a gate width-to-length ratio W 2 /L 2 of each second MOS transistor (M 2 , M 4 ) being larger than a gate width-to-length ratio W 1 /L 1 of the associated first MOS transistor (M 1 , M 3 ), a gate of the first MOS transistor (M 1 ) of the first differential circuit being connected to a gate of the second MOS transistor (M 4 ) of the second differential circuit, a gate of the second MOS transistor (M 2 ) of the first differential circuit being connected to a gate of the first MOS transistor (M 3 ) of the second differential circuit; characterised in that said multiplier circuit further comprises second (2) and third (3) such squaring circuits, the gates of the first MOS transistors (M 1 , M 9 ) of the first differential circuits of the first and third squaring circuits being connected in common to receive a first input signal V 1 , the gate of the first MOS transistor (M 5 ) of the first differential circuit of the second squaring circuit and the gate of the first MOS transistor (M 11 ) of the second differential circuit of the third squaring circuit being connected in common to receive a second input signal V 2 , drains of the first MOS transistors (M 1 , M 3 , M 5 , M 7 ) of the first and second differential circuits of the first and second squaring circuits and of the second transistors (M 10 , M 12 ) of the first and second differential circuits of the third squaring circuit being connected in common to a first output current terrninal I 1 , and drains of the second MOS transistors (M 2 , M 4 , M 6 , M 8 ) of the first and second differential circuits of the first and second squaring circuits and of the first transistors (M 9 , M 11 ) of the first and second differential circuits of the third squaring circuit being connected in common to a second output current terminal I 2 , whereby a differential current between the first and second output current terminals is indicative of a product of the input signals V 1 and V 2 . A circuit according to Claim 1, wherein the sources of the first and second MOS transistors (M 1 and M 2 , M 3 and M 4 , ..., M 11 and M 12 ) of each first and second differential circuit of said first to third squaring circuits (1,2,3) are connected in common to constant current sources (A 1 to A 6 ), a common input terminal being connected to the gate of said second MOS transistor (M 2 , M 6 ) of the first differential circuit of each of said first and second squaring circuits, the connections of the drains of the first MOS transistors (M 1 , M 3 , M 5 , M 7 ) of the first differential circuits of the first and second squaring circuits and of the second transistors (M 10 , M 12 ) of the first and second differential circuits of the third squaring circuit to said first output current terminal, and of the drains of the second MOS transistors (M 2 , M 4 , M 6 , M 8 ) of the second differential circuit of the first and second squaring circuits and of the first transistors (M 9 , M 11 ) of the first and second differential circuits of the third squaring circuit to said second output current terminal forming an addition circuit; wherein said first squaring circuit is adapted to receive said first input signal to square said first input signal, said second squaring circuit is adapted to receive said second input signal to square said second input signal, said third squaring circuit is adapted to receive said first and second input signals to square a difference between said first and second inputs, and said addition circuit is adapted to subtract an output of said third squaring circuit from a sum of the outputs of said first and second squaring circuits. A circuit according to Claim 2 wherein said constant current source (A 1 to A 4 ) connected to each of said first and second differential circuits of each of said first and second squaring circuits has a first constant current capacity, and said constant current source (A 5 , A 6 ) connected to each of said first and second differential circuits of said third squaring circuit has a second constant current capacity which is a double of said first constant current capacity. A circuit according to Claim 3 wherein said first and second differential circuits of all said first to third squaring circuits have the same proportion of said gate width-to-length ratio of said second MOS transistor (M 2 ) to said gate width-to-length ratio of said first MOS transistor (M 1 ). A circuit according to Claim 2 further including a fourth squaring circuit composed of first and second differential circuits each of which is formed of first (M 13 , M 15 ) and a second (M 14 , M 16 ) MOS transistors having their sources connected in common to a constant current source (A 7 , A 8 ) having the same constant current capacity as that of said constant current source connected to each of said first and second differential circuits of each of said first to third squaring circuits, gates of said first and second MOS transistors of said first and second differential circuits of said fourth squaring circuit being connected in common to each other and to said common input terminal. A circuit according to Claim 5 wherein said first and second differential circuits of all said first to fourth squaring circuits have the same proportion of said gate width-to-length ratio of said second MOS transistor to said gate width-to-length ratio of said first MOS transistor.

Inventors: KIMURA KATSUJI, KIMURA, KATSUJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G06G7
IPC codes: G06G7, H03C1