Image processing apparatus

Abstract: [Purpose] In a reproduced image in accordance with pseudo-half-tone processing, it is an object to prevent low-density areas (highlighted portions) of the image, to which the human eye is most sensitive, from graininess and obtain a reproduced image of high picture quality with little sense of graininess without increasing the size of a page memory. [Structure] The binary data monitoring unit 400 detects low-density areas of binarized image by the binarizing circuit 300. The resolution converting circuit 500 divides dots which exist in the low-density area into dots of higher resolution, whereby improving the resolution. Then, the output unit 600 outputs and records the image. This results in obtaining a reproduced image of high picture quality with little sense of graininess without increasing the size of a page memory.

Description: BACKGROUND OF THE INVENTION Field of the Invention: This invention relates to an image processing apparatus and, more particularly, to an image processing apparatus through which the resolution of binary image data can be improved. By way of example, the invention relates to an image processing apparatus applied to image processing in an image output unit such as a digital printer or digital facsimile machine. Description of the Prior Art: An image output unit such as a digital printer or digital facsimile machine most generally is a binary output (i.e., a "black" or "white" output) device for reasons of economy and safety. In a binary output unit of this kind, pseudo-half-tone processing, described below, is necessary in order to output a gray-level image. The most typical technique employed in the art is the dither method. In accordance with the dither method, an m x n (where m, n are natural numbers) dither matrix is prepared, a binary measurement is performed by comparing inputted multivalue data with the threshold values of corresponding matrix elements, and an m x n binarized block is formed, whereby a half-tone image is reproduced in pseudo-fashion. With the dither method, however, the number of gray levels that can be expressed is limited to (m x n + 1). This is undesirable in terms of resolution. By contrast, an error diffusion method, which was proposed in 1975 by Floyd and Sterinberg in the technical paper "An Adaptive Algorithm for Special Grayscale", which appeared in the 1975 SID International Symposium Digest of Technical Papers, surpasses the dither method in terms of both resolution and gray level. This technique has recently become the focus of much attention. In the error diffusion method, binarization is performed at a fixed threshold value, a corrective density is obtained by adding, to the density of a pixel of interest, a diffusion error from a pixel in back of the pixel of interest, the difference is calculated between this corrective density and a binarized density (e.g., "white" = 0, "black" = 255 when density is expressed using eight bits) resulting from the aforementioned binarization, and this difference is caused to diffuse as a new error to a pixel in front of the pixel of interest. However, in a reproduced image obtained by pseudo-half-tone processing such as the above-described error diffusion method, the graininess of low-density areas (highlighted portions), to which the human eye is most sensitive, becomes unsightly, and this is a factor that impedes an improvement in picture quality. Though graininess diminishes when the resolution of the output device is improved, the improvement in resolution is accompanied by the need for an increase in the page memory of a page printer or the like having such a memory, which is for storing one page. The result is higher cost. By way of example, if resolution in the main scanning direction is doubled, twice the amount of page memory will be required. If resolution is doubled in both the main and subordinate scanning directions, four times the amount of page memory will be required. Accordingly, a concern of the present invention is to provide an image processing method capable of preventing low-density areas (highlighted portions), to which the human eye is most sensitive, from developing graininess in an image reproduced based upon a pseudo-half-tone processing method, whereby a reproduced image of high picture quality and little sense of graininess can be obtained without increasing the size of a page memory. European Patent Specification EP-A-0238034 discloses image processing apparatus in which image data is binarised and in which binary image data is selected in accordance with a conversion ratio to maintain overall tonality. UK Patent Specification GB-A-2172169 discloses a resolution conversion technique which operates by dividing pixel information. Neither document addresses the problem with which the present invention is concerned. In accordance with the present invention there is provided image processing apparatus as set out in claim 1. An embodiment of the present invention makes it possible to obtain a binary image having a high picture quality and little sense of graininess. Preferred embodiments of the invention are particularly advantageous since the low-density areas of a binarised image are sensed, the dots present in the low-density areas are divided or split up into dots having a higher resolution, and these dots are outputted, whereby a reproduced image of high picture quality with little sense of graininess can be obtained without increasing the size of a page memory. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Fig. 1 is a block diagram illustrating the construction of a binarizing apparatus which is a typical embodiment of the present invention; Fig. 2 is a block diagram showing the detailed construction of a binarizing circuit illustrated in Fig 1; Fig. 3 is a circuit diagram showing the detailed construction of an error diffusion unit illustrated in Fig. 2; Fig. 4 is a diagram showing diffusion coefficients of error diffusion in the error diffusion unit of Fig 3; Fig. 5 is a block diagram showing the detailed construction of a comparator depicted in Fig. 2; Fig. 6 a diagram showing the input/output characteristic of the comparator shown in Fig. 2; Fig. 7 is a diagram showing the detailed circuit construction of an AND/OR circuit depicted in Fig. 2; Fig. 8 is a truth table of the AND/OR circuit depicted in Fig. 2; Fig. 9 is a block diagram showing the detailed construction of a binarizing unit illustrated in Fig. 2; Fig. 10 is a block diagram showing the detailed construction of a binary data monitoring unit 400 shown in Fig. 1; Fig. 11 is a detailed circuit diagram of an OR circuit shown in Fig. 10; Fig. 12 is a detailed circuit diagram of another OR circuit shown in Fig. 10; Figs. 13 and 14 are diagrams showing examples of windows of the binary data monitoring unit shown in Fig 1; Fig. 15 is a connection diagram showing the connections between a memory and flip-flops illustrated in Fig. 10; Fig. 16 is a block diagram showing the detailed construction of a resolution converting circuit depicted in Fig. 2; Figs. 17 and 18 are diagrams showing pixel data diffused in accordance with a first embodiment; Fig. 19 is a diagram showing the contents of a LUT shown depicted in Fig. 16; Fig. 20 is a diagram showing the operation performed by an OR circuit illustrated in Fig. 16; Fig. 21 is a diagram showing the circuit construction of a controller in Fig. 16; Fig. 22 is a timing chart showing various signals handled by the controller of Fig. 21; Fig. 23 is a block diagram showing the detailed construction of a resolution converting circuit according to a second embodiment; Figs. 24 and 25 are diagrams illustrating image data diffused in accordance with the second embodiment; Fig. 26 is a diagram showing the contents of a LUT depicted in Figs. 24 and 25; Fig. 27 is a diagram showing the operation performed by an OR circuit illustrated in Figs. 24 and 25; Fig. 28 is a block diagram illustrating the detailed construction of a resolution converting circuit according to a third embodiment; Figs. 29A and 29B are diagrams for describing image data diffused in accordance with the third embodiment; Fig. 30 is a diagram showing the contents of a LUT depicted in Fig. 28; Fig. 31 is a block diagram illustrating the detailed construction of a binary monitoring unit in accordance with a fourth embodiment; Fig. 32 is a detailed circuit diagram of an OR circuit shown in Fig. 31; Fig. 33 is a detailed circuit diagram of another OR circuit shown in Fig. 31; Figs. 34 and 35 are diagrams for describing windows of the binary data monitoring unit in accordance with the fourth embodiment; Fig. 36 is a connection diagram showing the connections between a memory and flip-flops illustrated in Fig. 31; Figs. 37A and 37B are diagrams for describing image data diffused in accordance with the fourth embodiment; Fig. 38 is a block diagram illustrating the detailed construction of a resolution converting circuit according to the fourth embodiment; Fig. 39 is a block diagram illustrating the detailed construction of a resolution converting circuit according to a fifth embodiment; Figs. 40A and 40B are diagrams for describing image data diffused in accordance with the fifth embodiment; Fig. 41 is a diagram showing the contents of a LUT depicted in Fig. 39; and Fig. 42 is a diagram for describing the operation of the resolution converting circuit of Fig. 39. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings. [Description of Common Embodiment (Figs. 1 - 15)] The construction of a binarizing apparatus shared by five embodiments set forth below will now be described. The binarizing apparatus is adapted to apply binarizing processing to multivalue image information that is capable of expressing the half-tones of one page of an output image, and to print out an image of light and dark shades capable of reproducing gray levels. When dot data is outputted in the print-out operation of this apparatus, the scanning direction of a printer head, laser beam or the like is made the main scanning direction, and the direction of printing paper transfer is made the subordinate direction. In each of the five embodiments, only the components which characterize the particular embodiment in the binarizing apparatus will be described. <General Description of Binarizing Apparatus (Fig. 1)> Fig. 1 is a block diagram illustrating the construction of a binarizing apparatus which is a typical embodiment of the present invention. In Fig. 1, numeral 100 denotes a page memory of a controller. The page memory 100 stores one page of image information of the output image. Digital data representing eight bits (256 tones) of density is sent to an input unit 200 over a data line 160. The input unit 200 temporarily stores the data sent from the page memory 100. Thereafter, in synchronization with a read clock, the data is read out of the input unit 200 successively and transferred to a processing section in order to be processed. Thus, even if data is transferred from the page memory 100 asynchronously with the processing section, the data can subsequently be outputted and processed in synchronization with the clock of the processing section. Numeral 260 denotes a data line on which the multivalue data synchronized to the clock of the processing section is outputted. This data represents 8-bit density information in the same manner as the digital data transmitted through the data line 160. A binarizing circuit 300 performs binarizing processing based upon information from the data line 260 and a data line 370 and outputs binary data (i.e., "1" (black) or "0" (white), which is the result of the processing, on a data line 360. A binary data monitoring unit 400 refers to the signal (signal line 360) outputted by the binarizing circuit 300 and to a monitoring area (a window area) of binarized pixels on the periphery of a pixel of interest and determines whether the window area contains a dot which is black ("1"). The monitoring unit 400 outputs the result of this determination on the signal line 370, thereby feeding it back to the binarizing circuit 300. Meanwhile the binary data monitoring unit 400 refers to a monitoring area (a window area different from that mentioned above) of binarized pixels on the periphery of the pixel of interest and determines whether the window area contains a dot which is black ("1"). The result of this determination is outputted on a signal line 460. Based upon the data transmitted through the signal line 460, a resolution converting circuit 500 serially outputs, successively in the form of two bits, data obtained by referring to a table, prepared in advance, having four times the amount of data. This serial output is performed during one clock of a synchronizing clock signal of the preceding processing section, which includes the binarizing circuit 300. As a result, the resolution of the output data in the main scanning direction of an output unit 600 is doubled. The output unit 600 performs the actual print-out of data arriving on signal line 560. The detailed construction of each portion of the binarizing apparatus comprising the components set forth above will now be described. <Description of Binarizing Circuit 300 (Figs. 2 - 9)> Fig. 2 is a block diagram showing the detailed construction of the binarizing circuit 300 illustrated in Fig. 1. The binarizing circuit 300 includes an error diffusion unit 310, which applies allotting processing to error components generated by binarization. The density signal of the pixel of interest enters an adder 320 from the signal line 260. Meanwhile, the sum total of errors allotted to the position of the pixel of interest is outputted on a signal line 390 from the error diffusion unit 310, and this signal also enters the adder 320. The adder 320 delivers the sum of these two input signal to a signal line 395. A comparator 330 compares the density of the pixel of interest with a group of fixed threshold values, determines the range within which the density resides and outputs a signal indicative of the determination to a signal line 336. Depending upon the data outputted on signal line 336 from the comparator 330 and the data outputted on signal line 370 from the binary data monitoring unit 400, an AND/OR circuit 340 outputs a binarized "black" dot inhibit signal on a signal line 346. A binarizing unit 350, which compares the density signal from the signal line 395 with a fixed threshold value, performs binarization upon taking the binarized dot inhibit signal from signal line 346 into consideration. A binarized signal from the binarizing unit 350 is outputted on a the signal line 360 as a single-bit ["1" (black) or "0" (white)] signal. Error components generated as a result of binarization are outputted on a signal line 380 and thus are fed back to the error diffusion unit 310. Fig. 3 is a block diagram showing the detailed construction of the error diffusion unit 310 depicted in Fig. 2. Numeral 311 designates an error-allotment control circuit, 312 a line memory (FIFO memory) for applying a one-line delay, 313a - 313e flip-flops for latching data, and adders 314a - 314e. In this arrangement, the error component from signal line 380 enters the error-allotment control circuit 311, which applies error components having the weighting coefficients shown in Fig. 4 to the adders. More specifically, a signal line 381 connects a quantity which is 1/8 of an error component to the adder 314e, a signal line 382 connects a quantity which is 1/8 of the error component to the adder 314d, a signal line 383 connects a quantity which is 2/8 of the error component to the adder 314c, a signal line 384 connects a quantity which is 1/8 of the error component to the flip-flop 313c, a signal line 385 connects a quantity which is 1/8 of the error component to the adder 314a, and a signal line 386 connects a quantity which is 2/8 of the error component to the adder 314b. The line memory 312 outputs the sum total of the errors allotted to the pixel of interest in the processing up to the immediately preceding cycle. This signal enters the adder 314a. Addition is performed in successive fashion and the sum total of the errors that have accumulated at the "position" of the pixel of interest is inputted to the flip-flop 313b. The result is outputted on the signal line 390. Fig. 5 is a block diagram showing the detailed construction of the comparator 330 illustrated in Fig. 2. As shown in Fig. 5, the comparator 330 includes level comparators 331a - 331d and an AND circuit 332. The density value of the pixel of interest enters from the signal line 260 and is applied to the "-" terminals of comparators 331a and 331c and to the "+" terminals of comparators 331b and 331d. Fixed threshold values "1", "11" enter the "+" terminals of comparators 331a and 331c, and fixed threshold values "10", "20" enter the "-" terminals of comparators 331b and 331d. Thus the density of the pixel of interest is compared with each of these threshold values. Specifically, as shown in Fig. 6, if the density value of the pixel of interest is "0", then the comparators 331a, 331c output "1" and the comparators 331b, 331d output "0". If the density value of the pixel of interest is in the range "1" ∼ "10", or "5", for example, only the comparator 331c outputs a "1"; the other comparators output "0". If the density value of the pixel of interest is in the range "11" ∼ "20", or "15", for example, only the comparator 331b outputs a "1"; the other comparators output "0". Finally, if the density value of the pixel of interest is "21" or greater, the comparators 331b, 331d output "1" and the other comparators output "0". The AND circuit 332 serves as a decoder of the density signal. For example, when the density is "0", the output on the signal line 336a is "1" and the output on each of the signal lines 336b - 336d is "0". In case of other density values, the signals indicated in the truth table of Fig. 6 are obtained. Fig. 7 is a block diagram showing the detailed construction of the AND/OR circuit depicted in Fig. 2. Fig. 8 is a truth table corresponding to the outputs on the signal lines of the AND/OR circuit depicted in Fig. 7. As shown in Fig. 7, the AND/OR CIRCUIT 340 includes AND gates 341a - 341c, OR gates 342a, 342b, and an inverter 343. Signal lines 370a, 370b introduce the outputs from the binary data monitor unit 400, described below. The binary dot inhibit signal is generated from these output signals and output signals from the comparators 331a - 331d. In a case where the data on signal line 336a is "1", i.e., the density value of the pixel of interest is "0", the binarized dot is forcibly made "0" (white). Accordingly, "1" is outputted as the inhibit signal on signal line 346 via the OR gate 342a. In a case where the density value of the pixel of interest has a level of "1" ∼ "10", i.e., the data on signal line 336b is "1", the window area is monitored in large size. If a black dot ("1") already exists, the binarized black dot is forcibly inhibited. In other words, in a case where the data on signal line 370a is "1", the AND condition of AND gate 341b is satisfied and "1" is outputted on signal line 346, via the OR gate 342a, as the inhibit signal of the binarized dot. Further, if the data on signal line 370a is "0" and the data on signal line 370b is "1", then in this case also "1" is outputted via the AND gate 341c. Similarly, "1" is outputted,by the AND gate 341b. Thus, "1" is outputted as the inhibit signal of the binarized dot on signal line 346 via the OR gate 342a. In a case where the density value of the pixel of interest has a level of "11" ∼ "20", i.e., the data on signal line 336c is "1", the window area is monitored in a small size. If a black dot ("1") already exists, the binarized dot is forcibly inhibited. In other words, if the data on signal line 370a is "1", the AND condition of AND gate 341a is satisfied and the AND gate 341a outputs "1". This is outputted as the inhibit signal of the binarized black dot on signal line 346 via the OR gate 342a. Fig. 9 is a block diagram showing the detailed construction of the binarizing unit 350 depicted in Fig. 2. As shown in Fig. 9, the binarizing unit 350 includes a comparator 351, a subtractor 353, a selector 354, an inverter 355 and an AND gate 356. The sum of the density value of the pixel of interest and the sum total of the error signals allotted to the position of the pixel of interest enters the comparator 351 from signal line 395. Meanwhile, a fixed threshold value ("127") also enters the comparator 351, which proceeds to compare the fixed threshold value with the above-mentioned sum of the density value and the sum total of the distributed errors [i.e., (density value of pixel of interest) + (sum total of distributed errors)]. The comparator 351 outputs the result of this comparison to the AND gate 356. More specifically, if the (density value of pixel of interest) + (sum total of distributed errors) is greater than the threshold value, "1" (black) is outputted; if it is smaller, "0" (white) is outputted. This output is applied to one input terminal of the AND gate 356. If the data on signal line 346 from the AND/OR circuit 340 is "1", i.e., if binarization is inhibited, then "0" is inputted to the AND gate 356 via the inverter 355. As a consequence, the AND condition of AND gate 356 is not satisfied and "0" is outputted to the signal line 360. On the other hand, if the (density value of pixel of interest) + (sum total of distributed errors) is greater than the threshold value and the data on signal line 346 is "0", i.e., if binarization is not inhibited, "1" is outputted on signal line 360. Further, the subtractor 353 outputs the result of subtracting "255" from the data on signal line 395 and applies this result to the selector 354. The data on signal line 395 is inputted to the other input terminal of the selector 354. If "1" is outputted on signal line 360 as the result of binarization, the output value of subtractor 353 applied to the selector 354 is selected and this value is outputted on signal line 380. If "0" is outputted on line 360, the data on signal line 395 is selected by the selector 354 and this is outputted on signal line 380. <Description of Binary Data Monitoring unit 400 (Figs. 10 - 15)> Fig. 10 is a block diagram illustrating the detailed construction of the binary data monitoring unit 400 shown in Fig. 1. As shown in Fig. 10, the monitoring unit 400 includes a FIFO memory 410 which has a 3 bits input and output and is capable of storing three lines of binary results, flip-flops 420a - 420g for latching data, and OR circuit units 430, 440. Binarized data from the memory 410 is successively inputted to the flop-flop 420g in synchronization with the clock signal. Thereafter, the data is shifted to the flip-flops 420f - 420a successively every clock pulse. Meanwhile, "1" or "0" from signal line 360 is inputted to the MSB side of the flip-flop 420f as the results processed by the binarizing circuit 300. Accordingly, the output of the flip-flops 420f - 420a is four bits. The binarized results (b 1 ′, b 2 ′, b 3 ′, b 4 ′) shown in Figs. 13, 14 are latched, in order from the least significant, in the flip-flop 420a. Similarly, the four bits (a 1 ′, a 2 ′, a 3 ′, b 5 ′) shown in Fig. 13 are latched in the flip-flop 420b, the four bits (b 1 , b 7 , b 8 , b 9 ) in the flip-flop 420c, the four bits (b 2 , a 1 , a 6 , a 11 ) in the flip-flop 420d, the four bits (b 3 , a 2 , a 7 , a 12 ) in the flip-flop 420e, the four bits (b 4 , a 3 , a 8 , a 13 ) in the flip-flop 420f, and the three bits (b 5 , a 4 , a 9 ) in the flip-flop 420g. The three bits (b 6 , a 5 , a 10 ) are outputted by the memory 410. The four bits from each of the flip-flops 420c - 420f, the three bits from the flip-flops 420g, and the three bits from the memory 410 enter the OR circuit unit 430. The four bits from each of the flip-flops 420a - 420f enter the OR circuit unit 440. Fig. 11 is a block diagram showing the detailed construction of the OR circuit unit 430 depicted in Fig 10. In Fig. 11, numerals 431 and 432 denote OR circuits. The inputs to the OR circuit 431 are the three bits (a 1 , a 6 , a 11 ) of the signal 421d from the flip-flop 420d, the three bits (a 2 , a 7 , a 12 ) of the signal 421e from the flip-flop 420e, the three bits (a 3 , a 8 , a 13 ) of the signal 421f from the flip-flop 420f, the two bits (a 4 , a 9 ) of the signal 421g from the flip-flop 420g, and the two bits (a 5 , a 10 ) of the signal 421h from the memory 410. The OR circuit 431 detects whether even one of these inputs is "1" (a black dot). The inputs to the OR circuit 432 are the four bits (b 1 , b 7 , b 8 , b 9 ) of the signal 421c from the flip-flop 420c, the bit (b 2 ) of the signal 421d from the flip-flop 420d, the bit (b 3 ) of the signal 421e from the flip-flop 420e, the two bit (b 4 ) of the signal 421f from the flip-flop 420f, the bit (b 5 ) of the signal 421g from the flip-flop 420g, the bit (b 6 ) of the signal 421h from the memory 410, and the output signal 370a of OR circuit 421. The OR circuit 432 detects whether even one of these inputs is "1" (a black dot). Thus, the OR circuit portion 430 detects whether there is a "1" (a black dot) in two window areas of different sizes, and the result is outputted on signal lines 370a and 370b. Fig. 12 is a block diagram showing the detailed construction of the OR circuit unit 440 depicted in Fig. 10. In Fig. 12, numerals 441 and 442 denote OR circuits. The character a 1 shown in Fig. 12 is one bit of the signal on signal line 421d from the flip-flop 420d and is outputted on signal line 460a. This is also the binarized result of the pixel of interest in the binary data monitoring window for conversion of resolution. The inputs to the OR circuit 441 are the three bits (a 1 ′, a 2 ′, a 3 ′) of the signal 421b from the flip-flop 420b, the three bits (b 1 , b 7 , b 8 ) of the signal 421c from the flip-flop 420c, the two bits (b 2 , a 6 ) of the signal 421d from the flip-flop 420d, the three bits (b 3 , a 2 , a 7 ) of the signal 421e from the flip-flop 420e, and the three bits (b 4 , a 3 , a 8 ) of the signal 421f from the flip-flop 420f. The OR circuit 441 detects whether even one of these inputs is "1" (a black dot). The inputs to the OR circuit 442 are the four bits (b 1 ′, b 2 ′, b 3 ′, b 4 ′) of the signal 421a from the flip-flop 420a, the bit (b 5 ′) of the signal 421b from the flip-flop 420b, the bit (b 9 ) of the signal 421c from the flip-flop 420c, the bit (a 11 ) of the signal 421d from the flip-flop 420d, the bit (a 12 ) of the signal 421e from the flip-flop 420e, the bit (a 13 ) of the signal 421f from the flip-flop 420f, and the output signal 460b from the OR circuit 441. The OR circuit 442 detects whether even one of these inputs is "1" (a black dot). Thus, the OR circuit portion 440 detects whether there is a "1" (a black dot) in two window areas of different sizes, and the result is outputted on signal lines 460a - 460c. Fig. 15 is a diagram for describing the details of the memory 410 and flip-flops 420a - 420g shown in Fig. 10. When the series of processing operations such as binarization and error diffusion ends in the above-described arrangement, the pixel of interest is shifted by one pixel to update the data in the window, and the foregoing processing is then repeated. At the end of processing, the three higher order bits (b 2 ′, b 3 ′, b 4 ′) of the data in flip-flop 420a are fed back to and stored in the three-line buffer 410 in order to be used in the next line of processing. Accordingly, the three higher order bits (b 2 ′, b 3 ′, b 4 ′) of the data on line 421a from flip-flop 420a are stored in the memory 410. At the same time, the data on signal line 360, which data is the result of binarization, is inputted to the MSB side of the flip-flop 420f, where the data is latched. Thus, the data in the flip-flops is shifted successively in synchronization with the clock, and the data which has finished undergoing processing is stored in the three-line memory. First through fifth embodiments of the present invention will now be described. These five embodiments relate to a binarizing apparatus having the construction shown in Fig. 1. Though portions common to these five embodiments are as already described, each is characterized in the construction and operation of the resolution analyzing circuit 500. In the description of each embodiment, therefore, the discussion will center on the construction and operation of the resolution analyzing circuit 500. [First Embodiment (Figs. 16 - 22)] In this embodiment, a case will be described wherein a binarized image is subjected to a two-fold resolution conversion in both the main and subordinate scanning directions, dots are split up and the result is outputted. Fig. 16 is a block diagram showing the detailed construction of the resolution converting circuit 500 depicted in Fig. 1. As shown in Fig. 16, the resolution converting circuit 500 includes a look-up table (hereinafter referred to as a "LUT") 510, OR gates 520 - 523, flip-flops 530 - 533 for latching data, FIFO memories 540, 541, 542 for storing two lines of binary results and having 2-bit, 2-bit and 8-bit input/outputs, respectively, a controller 550 for controlling memory access, and a shift register 570 for converting parallel data into serial data. Fig. 17 is a diagram showing a black dot (*), which is located in a small window area, split or subdivided into small dots of higher resolution. Fig. 18 is a diagram showing a black dot (*), which is located in a large window area, split or sub-divided into small dots of higher resolution. As will be understood from Figs. 17 and 18, dots are dispersed nearby in the small window area and more distantly in the large window area. Fig. 19 is a diagram showing in detail the contents of the LUT 510 depicted in Fig. 16. Patterns of a th , b th , c th , d th and e th columns are generated on signal lines 516a, 516b, 516c, 516d, 516e, respectively, from the LUT 510. In a case where data on signal line 460a from the binary data monitoring unit 400 is "0", i.e., when the pixel of interest is white, in Fig. 16, "0" is outputted as two dots in the main and subordinate scanning directions regardless of the data on the signal lines 460b and 460c from other window areas. Accordingly, as shown in Fig. 19, the signal line 516a of the a th column, the signal line 516b of the b th column, the signal line 516c of the c th column (which is that of the pixel of interest), the signal line 516d of the d th column and the signal line 516e of the e th column of LUT 510 together output "0" for all 12 bits from the LSB to the MSB. These outputs enter the OR gates 520 - 523 and the flip-flop 533, respectively, in Fig. 16. In a case where the data on signal line 460a from the binary data monitoring unit 400 is "1", i.e., when the pixel of interest is a black dot, and there was no "1" (black dot) in the large window area, i.e., when the outputs on the signal lines 460b and 460c are both "0", the "1"s (black dots) are dispersed far from the pixel of interest (the pixel marked by "*" in Fig. 18), as illustrated in Fig. 18. Accordingly, as depicted in Fig. 19, the LUT 510 produces the following outputs in the bit-order mentioned starting from the LSB: "000100000001", as the data of the a th column, from signal line 516a; "000000000000", as the data of the b th column, from signal line 516b; "000000000000", as the data of the c th column, from signal line 516c; "000100000001", as the data of the d th column, from signal line 516d; and "000000000000", as the data of the e th column, from signal line 516e. These outputs enter the OR gates 520 - 522 and flip-flop 533, respectively. In a case where the signal on signal line 460a from the binary data monitoring unit 400 is "1", i.e., the pixel of interest is a black dot, there was no "1" in the small window area but only in the window area outside this area, i.e., if the outputs on signal lines 460b and 460c are "0" and "1", respectively, the "1"s (black dots) are dispersed near the pixel of interest (the pixel marked by "*" in Fig. 17), as illustrated in Fig. 17. Accordingly, as depicted in Fig. 19, the LUT 510 produces the following outputs in the bit order mentioned starting from the LSB: "000000000000", as the data of the a th column, from signal line 516a; "001000001000", as the data of the b th column, from signal line 516b; "000000000000", as the data of the c th column, from signal line 516c; "001000001000", as the data of the d th column, from signal line 516d; and "000000000000", as the data of the e th column, from signal line 516e. These outputs enter the OR gates 520 - 522 and flip-flop 533, respectively. In a case where the signal on signal line 460a from the binary data monitoring unit 400 is "1", i.e., the pixel of interest is a black dot, and there was a "1" also in the small window area, i.e., if the outputs on signal lines 460b and 460c are both "1", a "1" (black dot) is simply added in both the main and subordinate scanning directions alongside the pixel of interest. Accordingly, as shown in Fig. 19, the LUT 510 outputs, in the bit order mentioned starting from the LSB, "000000000000" as the data of the a th and b th columns from the signal lines 516a and 516b. As the data of the c th column, "000011110000" is outputted from the signal line 516c in the order mentioned starting from the LSB. As the data of the d th and e th columns, "000000000000" is outputted, in the order mentioned starting from the MSB, from both the signal lines 516d and 516e. The data thus outputted enters the OR gates 520 - 523 and the flip-flop 533, respectively. The processing of the a th column implemented by the OR gate 520 and memories 540 - 542 will now be described. Here the content of the LUT 510 shown in Fig. 19 corresponds to the bits shown in Fig. 18. The inputs to the OR gate 520 are the 12 bits data outputted from the LUT 510 on signal line 516a, the 12 bits data from output signal line 536b of the flip-flop 530, which has stored the processed results up to the immediately preceding cycle, and a 8 bits data from signal line 546c of the memory 542, which has stored the results of processing from the second line onward. More specifically, as shown in Fig. 20, the LSB of the data outputted on signal line 516a, the LSB of the data outputted on signal line 536b, and the LSB of the data outputted on signal line 546c enter the LSB side of the OR gate 520, the data is outputted as the processing on the LSB side, and this output enters the LSB of the memory 540, where it is stored. The second bit of output data on signal line 516a, the second bit of output data on signal line 536b, and the second bit of output data on signal line 546c enter the second bit of the OR gate 521, the data is outputted as the second bit of processing, and this output enters the MSB of the memory 540, where it is stored. Further, the third and fourth bits of the output data on signal line 516a, the the third and fourth bits of the output data on signal line 536b, and the third and fourth bits of data on the signal line 546c enter the third and fourth bits of the OR gate 520, the data is outputted as the third and fourth bits of processing, and these outputs enter the LSB and MSB of the memory 541, where they are stored. In addition, the fifth through eighth bits of the output data on signal line 516a, the fifth through eighth bits of the output data on on signal line 536b, and the fifth bit through the MSB of the output data on signal line 546c enter the fifth through eighth bits of the OR gate 520, the data is outputted as the fifth through eighth bits of processing, and these outputs enter the LSB through the fourth bit of the memory 542, where they are stored. The ninth bit through MSB of the output data on signal line 516a, and the ninth bit through MSB of the output data on signal line 536b enter the ninth bit through the MSB of the OR gate 520, the data is outputted as the ninth bit through MSB of processing, and these outputs enter the fifth bit through MSB of the memory 542, where they are stored. The processing of the b th column implemented by the OR gate 521 and flip-flop 530 will now be described. The inputs to the OR gate 521 are the 12 bits data outputted from the LUT 510 on signal line 516b, and the 12 bits data from output signal line 536c of the flip-flop 531, which has stored processed results up to the immediately preceding cycle. The data is processed in correspondence with the LSB to the MSB, and the output is inputted to the flip-flop 530 in correspondence with the LSB to the MSB, where the data is stored. The processing of the c th and d th columns is executed in the same manner as set forth above. The data outputted on signal line 516e from the LUT 510 is directly inputted to the flip-flop 533, where it is stored as the e th column of processing. Fig. 21 is a block diagram showing the detailed construction of the controller 550 depicted in Fig. 16. In Fig. 21, the controller 550 includes a counter 551 for counting the number of pixels in one line in the main scanning direction, a J-K-type flip-flop 552, AND gates 553a and 553b, and an inverter 553c. The binary results from the binarization unit 350 are outputted on line 360, and the counter 551 performs a counting operation in synchronization with this output. More specifically, a signal synchronized with the transfer of the binary results is inputted to the clock input of the counter 551. The counter 551 also counts the number of pixels in one line. When the number of pixels in one half of a line have been counted, as shown in the timing chart of Fig. 22, a "1" is outputted on signal line 557a. Furthermore, when the number of pixels in the remaining half of the line have been counted, a carrier signal "1" is outputted on line 557b. In other words, "1" is outputted on signal line 557a when the counter 551 has counted the number of pixels in one half of a line, and "1" is outputted on signal line 557b when the counter 551 has counted the number of pixels in one line. Initially, when the counter 551 has counted the number of pixels in one line, the carrier signal "1" from the signal line 557b enters the J terminal of the flip-flop 552. As a result, the flip-flop 552 is set, and a "1" signal from the Q-output terminal of the flip-flop 552 is outputted on signal line 558b. The signal line 558b is connected to one input terminal of each of the AND gates 553a, 553b. During the counting of the number of pixels on the next line, a "0" is outputted on signal line 557a when the number of pixels in one half of the initial line is being counted. Since this signal enters the AND gate 553a via the inverter 553c, "1" is outputted by the AND gate 553a. Accordingly, "1" is outputted on output signal line 556a of the AND gate 553a, and the memory 540 shown in Fig. 16 is enabled so that the stored contents can be read out. Next, a "1" is outputted on signal line 557a when the number of pixels in the remaining half of the initial line is being counted. This signal enters the AND gate 553b. Since the AND condition of this gate is satisfied, a "1" is outputted on the output signal line 556b. In response to the output of "1" on signal line 556b, the memory 541 shown in Fig. 16 is enabled so that the stored contents can be read out. The speed at which data is read out of the memory 540 or 541 is twice that at which the data is written in these memories. More specifically, during the time that "1" is being outputted on signal line 556a while half of the pixels of one line are being transferred, the memory 540 is enabled and reading is performed at twice the speed. The two bits on signal line 546a enter the shift register 570, the parallel data is converted into serial data, and the serial output is performed on signal line 560 at twice the speed. Next, during the time that the remaining half of the pixels of one line are being transferred, "1" is outputted on signal line 556b and the memory 541 is enabled. Operation identical to that described above is performed in response to the output on signal line 546b. Finally, when the entire operation ends, an end signal is applied to the K-terminal of the flip-flop 552 to reset this flip-flop. As a result, a "0" is delivered from the Q-terminal and the AND gates 553a, 553b shut down. In accordance with this embodiment, as described above, low-density areas of a binarized imaged are sensed, the dots present in the low-density areas are split into dots having a higher resolution, and these dots are outputted. As a result, it is possible to obtain a reproduced image having a high resolution and little graininess without increasing the size of a page memory. [Second Embodiment (Figs. 23 - 27)] The present invention is not limited to the resolution conversion described in the first embodiment. It goes without saying that an arrangement in which a conversion is made to high resolution followed by recording also is covered by the present invention. In this embodiment, a case will be described in which dots are split and outputted by making the resolution four times greater in the main scanning direction and two times greater in the subordinate scanning direction. Reference will be had to the drawings to describe the procedure for executing the division into small dots, as well as the contents of the LUT, centered mainly on the resolution converting circuit 500 that characterizes this embodiment. Portions of the apparatus identical with those already described are designated by like reference characters and need not be described again. Fig. 23 is a block diagram illustrating the detailed construction of the resolution converting circuit 500 according to this embodiment. In Fig. 23 also, the resolution converting circuit 500 is substantially the same as that shown in Fig. 16 already described in connection with the first embodiment. Portions that are different are merely the bit structures of the various circuits. Accordingly, the reference numerals of these circuits are the same as those shown in Fig. 16 and these circuits need not be described again. In Fig. 23, numerals 540 - 542 denote FIFO memories for storing two lines of binary results and having a 4 bits, a 4 bits and a 16 bits input/outputs. Fig. 24 is a diagram showing an example in which a black dot (*), which is located in a small window area, is split or sub-divided into small dots of higher resolution in accordance with this embodiment. Fig. 25 is a diagram showing an example in which a black dot (*), which is located in a large window area, is split or sub-divided into small dots of higher resolution. As will be understood from Figs. 24 and 25, the black dots (*) are dispersed nearby in the small window area and more distantly in the large window area. Fig. 26 is a diagram showing the contents of the LUT 510 depicted in Fig. 23. In Fig. 26, patterns of 1 st , 2 nd , 3 rd , 4 th and 5 th columns are generated on signal lines 516a, 516b, 516c, 516d, 516e, respectively. In a case where data on signal line 460a from the binary data monitoring unit 400 is "0", i.e., when the pixel of interest is white, "0" is outputted as two dots in the main and subordinate scanning directions regardless of the data on the signal lines 460b and 460c from other window areas. Accordingly, as shown in Fig. 26, the signal line 516a of the 1 st column, the signal line 516b of the 2 nd column, the signal line 516c of the 3 rd column (which is that of the pixel of interest), the signal line 516d of the 4 th column and the signal line 516e of the 5 th column of LUT 510 together output "0" for all 12 bits from the LSB to the MSB. These outputs enter the OR gates 520 - 523 and the flip-flop 533, respectively. In a case where the data on signal line 460a from the binary data monitoring unit 400 is "1", i.e., when the pixel of interest is a black dot, and there was no "1" (black dot) in the large window area, i.e., when the outputs on the signal lines 460b and 460c are both "0", the "1"s (black dots) are dispersed far from the pixel of interest (the pixel marked by "*" in Fig. 25), as illustrated in Fig. 25. Accordingly, as depicted in Fig. 26, the LUT 510 produces the following outputs in the bit-order mentioned starting from the LSB: "000000010000000000000001", as the data of the 1 st column, from signal line 516a; "000000010000000000000001", as the data of the 2 nd column, from signal line 516b; "000000010000000000000001", as the data of the 3 rd column, from signal line 516c; "000000010000000000000001", as the data of the 4 th column, from signal line 516d; and "000000000000000000000000", as the data of the 5 th column, from signal line 516e. These outputs enter the OR gates 520 - 522 and flip-flop 533, respectively. In a case where the signal on signal line 460a from the binary data monitoring unit 400 is "1", i.e., the pixel of interest is a black dot, there was no "1" in the small window area but only in the window area outside this area, i.e., if the outputs on signal lines 460b and 460c are "0" and "1", respectively, the "1"s (black dots) are dispersed near the pixel of interest (the pixel marked by "*" in Fig. 24), as illustrated in Fig. 24. Accordingly, as depicted in Fig. 26, the LUT 510 produces the following outputs in the bit order mentioned starting from the LSB: "000000000000000000000000", as the data of the 1 st column, from signal line 516a; "000001000000000001000000", as the data of the 2 nd column, from signal line 516b; "000010010000000100100000", as the data of the 3 rd column, from signal line 516c; "000000010000000100100000", as the data of the 4 th column, from signal line 516d; and "000000000000000000000000", as the data of the 5 th column, from signal line 516e. These outputs enter the OR gates 520 - 522 and flip-flop 533, respectively. Finally, in a case where the signal on signal line 460a from the binary data monitoring unit 400 is "1", i.e., the pixel of interest is a black dot, and there was a "1" also in the small window area, i.e., if the outputs on signal lines 460b and 460c are both "1", a "1" (black dot) is simply added in both the main and subordinate scanning directions alongside the pixel of interest. Accordingly, as shown in Fig. 26, the LUT 510 outputs, in the bit order mentioned starting from the LSB, "000000000000000000000000" as the data of the 1 st and 2 nd columns from the signal lines 516a and 516b. As the data of the 3 rd column, "000000001111111100000000" is outputted from the signal line 516c in the order mentioned starting from the LSB. As the data of the 4 th and 5 th columns, "000000000000000000000000" is outputted, in the order mentioned starting from the MSB, from both the signal lines 516d and 516e. The data thus outputted enters the OR gates 520 - 523 and the flip-flop 533, respectively. The processing of the 1 st column implemented by the OR gate 520 and memories 540 - 542 will now be described. Here the content of the LUT 510 shown in Fig. 26 corresponds to the bits shown in Fig. 25. The inputs to the OR gate 520 are the 24 bits data outputted from the LUT 510 on signal line 516a, the 24 bits data from output signal line 536b of the flip-flop 530, which has stored the processed results up to the immediately preceding cycle, and a 16 bits data from signal line 546c of the memory 542, which has stored the results of processing from the second line onward. More specifically, as shown in Fig. 27, data from the LSB to the fourth bit on signal line 516a, data from the LSB to the fourth bit on signal line 536b, and data from the LSB to the fourth bit on signal line 546c enter the OR gate 520 from the LSB to the fourth bit, the data is outputted as the processing from the LSB to the fourth bit, and this output enters the memory 540 from the LSB to the MSB, where it is stored. Next, the data from the fifth bit to the eighth bit on signal line 516a, the data from the fifth bit to the eighth bit on signal line 536b, and the data from the fifth bit to the eighth bit on signal line 546c enter the fifth through eighth bits of the OR gate 520, the data is outputted as the fifth through eighth bits of processing, and this output enters the four bits from LSB to the MSB of the memory 541, where it is stored. Further, the data from the 9th bit to the 16th bit on signal line 516a, the data from the 9th bit to the 16th bit on the output signal line 536b, and the data from the 9th bit to the MSB on signal line 546c enter the 9th through 16th bits of the OR gate 520, the data is outputted as the 9th through 16th bits of processing, and this output enters the eight bits from the LSB to the eighth bit of the memory 542, where it is stored. Finally, the data from the 17th bit to the MSB on signal line 516a and the data from the 17th bit to the MSB on the output signal line 536b enter the 17th bit through the MSB of the OR gate 520, the data is outputted as the 17th bit through the MSB of processing, and this output enters the ninth bit to the MSB of the memory 542, where it is stored. The processing of the 2 nd column implemented by the OR gate 521 and flip-flop 530 will now be described. In Fig. 23, the inputs to the OR gate 521 are the 24 bits data outputted from the LUT 510 on signal line 516b, and the 24 bits data from output signal line 536c of the flip-flop 531, which has stored processed results up to the immediately preceding cycle. The data is processed in correspondence with the LSB to the MSB, and the output is inputted to the flip-flop 530 in correspondence with the LSB to the MSB, where the data is stored. The processing of the 3 rd and 4 th columns is executed in the same manner as set forth above. The data outputted on signal line 516e from the LUT 510 is directly inputted to the flip-flop 533, where it is stored as the 5 th column of processing. The controller 550 shown in Fig. 23 performs an operation similar to that in the first embodiment. However, since the bit lengths of the memories 540 and 541 are four bits, the 4 bits output from the signal 546a or 546b enters the shift register 570, a conversion is made from parallel to serial data, and a serial output is performed on signal line 560 at four times the speed. Finally, at the end of transfer of all binary results, the reading of data from the memory is completed in response to an end signal (not shown). In accordance with this embodiment, as described above, it is obvious that resolution can readily be converted to be any desired-number of times greater independently in the main and subordinate scanning directions. In addition, it is possible also to readily convert resolution to be any desired-number of times greater solely in the main scanning direction or solely in the subordinate scanning direction. In accordance with this embodiment, as described above, it is possible to obtain a reproduced image having a high resolution and little graininess without increasing the size of a page memory. [Third Embodiment (Figs. 28 - 30)] In this embodiment, a case will be described wherein a binarized image data is subjected to a two-fold resolution conversion in the main scanning direction. Fig. 28 is a block diagram illustrating the detailed construction of the resolution converting circuit 500 according to a third embodiment. As shown in Fig. 28, the converting circuit 500 includes the LUT 510, the OR gate 520, the flip-flop 530 for latching data, and the shift register 570 for converting parallel data into serial data. In comparison with the resolution converting circuits (Figs. 16 and 23) in accordance with the first and second embodiments, the resolution converting circuit 500 in accordance with this embodiment has basically the same components and the same reference characters are used to identify them. Fig. 29A is a diagram showing a black dot (*), which is located in a small window area, split or subdivided into small dots of higher resolution. Fig. 29B is a diagram showing a black dot (*), which is located in a large window area, split or sub-divided into small dots of higher resolution. As will be understood from Figs. 29A and 29B, black dots are dispersed near the pixel of interest (*) in the small window area and more distantly in the large window area. Fig. 30 is a diagram showing the contents of the LUT 510. In a case where data on signal line 460a from the binary data monitoring unit 400 is "0", i.e., when the pixel of interest is white, control is performed in such a manner that two "0"s appear in the main scanning direction regardless of the data on the signal lines 460b and 460c from other window areas. Two pixels of "0"s are outputted from the output unit 600. Accordingly, as shown in Fig. 30, the LUT 510 outputs "0" data for all 12 bits from the LSB to the MSB. This data enters one input of the OR gate 520. Further, ten bits from the MSB side of the flip-flop 530 are fed back to the other input of the OR gate 520 to enter the same. As a result, the 12 bits data from the OR gate 520 again enters the flip-flop 530 and therefore is rewritten. Furthermore, the 12 bits of the rewritten data outputted by the flip-flop 530 enter the shift register 540, from which two bits are outputted one bit at a time from the LSB side. In a case where the pixel of interest is "1" (a black dot) and there was no "1" in the large window area, i.e., if the outputs on the signal lines 460b, 460c are both "0", then "1" (a black dot) is diffused far from the pixel of interest, as illustrated in Fig. 29B. Accordingly, the LUT 510 outputs "000100000100" in this order starting from the LSB, as shown in Fig. 30, and this data enters one input of the OR gate 520. Furthermore, in a case where the pixel of interest is "1" (a black dot) and there was no "1" in the small window area but only in the area on the outside, i.e., if the outputs on the signal lines 460b, 460c are "0" and "1", respectively, then "1" (a black dot) is diffused near the pixel of interest, as illustrated in Fig. 29A. Accordingly, the LUT 510 outputs "000010001000" in this order starting from the LSB, as shown in Fig. 30, and this data enters one input of the OR gate 520. Finally, in a case where the pixel of interest is "1" (a black dot) and there was a "1" also in the small window area, i.e., if the outputs on signal lines 460b and 460c are both "1", a "1" (black dot) is simply added alongside the pixel of interest. Accordingly, as shown in Fig. 30, the LUT 510 outputs "000000011000" in this order starting from the LSB, and this data enters one input of the OR gate 520. Thus, the pattern generated by the LUT 510 is applied to the OR gate 520 and the results from the flip-flop 530 storing the pattern which prevailed up to the preceding cycle are fed back to the OR gate 520, whereby a correction is made by the OR gate 520. In other words, the LSB of the output data from the LUT 510 and the third bit of the output from the flip-flop 530 enter the OR gate 520, and these are outputted as the LSB. In addition, the second bit of the output from the LUT 510 and the fourth bit of the output from the flip-flop 530 enter the OR gate 520, and these are outputted as the second bit. Similarly, the tenth bit of the output from the LUT 510 and the MSB of the output from the flip-flop 530 enter the OR gate 520, and these are outputted as the tenth bit. Next, the 11th bit and the MSB of the output data from the LUT 510 are outputted directly from the OR gate 520 as data of the 11th bit and MSB. The foregoing results enter the shift register 540, whereby they are successively outputted two bits at a time from the LSB side. In accordance with this embodiment as described above, low-density areas of a binarized image are sensed and the dots present in the low-density areas are split up into dots of a higher resolution and printed, whereby it is possible to obtain a reproduced image having a high resolution and little graininess, without increasing the size of a page memory. [Fourth Embodiment (Figs. 31 - 38)] In this embodiment, a case will be described wherein a binarized image is subjected to a two-fold resolution conversion in the subordinate scanning direction to obtain a reproduced image having a high resolution. In comparison with the shared components described above, the construction of the binary data monitoring unit 400 in this embodiment differs part. Therefore, in the description that follows, reference will be had to the drawings to describe primarily the binary data monitoring unit 400 and the resolution converting circuit 500, which characterize this embodiment. <Description of Binary Data Monitoring Unit 400 (Figs. 31 - 36)] Fig. 31 is a block diagram showing the detailed construction of the binary data monitoring unit 400 in accordance with this embodiment. As shown in Fig. 31, the monitoring unit 400 includes a FIFO memory which has a 5 bits input/output and is capable of storing five lines of binary results, flip-flops 420a - 420e for latching data, and OR circuit units 430, 440. The circuit construction of Fig. 31 is substantially the same as that of the binary data monitoring unit shown in Fig. 10, and therefore the same reference characters are assigned. The difference between the two is the number of flip-flop circuits and the number of bits in the data outputted by these circuits. Binarized data (five bits) is read out of the memory 410 successively in synchronization with the clock, and this data is inputted to the flop-flop 420e. Thereafter, the data is shifted to the flip-flops 420d - 420a successively in synchronization with the clock pulses. Meanwhile, binarized data "1" or "0" is inputted from the signal line 360 to the MSB of the flip-flop 420d as the results processed by the binarizing circuit 300. Accordingly, the output of the flip-flops 420d - 420a is six bits. The binarized results (b 1 ′, b 3 ′, b 4 ′, b 5 ′, b 6 ′, b 7 ′) shown in Figs. 34, 35 are latched, in order from the least significant bit, in the flip-flop 420a. Similarly, the six bits (b 2 ′, a 1 ′, a 2 ′, a 3 ′, a 4 ′, a 5 ′) are latched in the flip-flop 420b; the six bits (b 1 , b 5 , b 6 , b 7 , b 8 , b 9 ) in the flip-flop 420c; the six bits (b 2 , a 1 , a 4 , a 7 , a 9 , a 13 ) in the flip-flop 420d; and the five bits (b 3 , a 2 , a 5 , a 8 , a 11 ) in the flip-flop 420e. The five bits (b 4 , a 3 , a 6 , a 9 , a 12 ) are outputted by the memory 410. The six bits, six bits and five bits from the respective flip-flops 420c - 420e, as well as the five bits from the memory 410, enter the OR gate portion 430. The six bits from each of the flip-flops 420a - 420d enter the OR gate portion 440. Fig. 32 is a block diagram showing the detailed construction of the OR gate unit 430 depicted in Fig 31. In Fig. 31, numerals 431 and 432 denote OR circuits. The inputs to the OR circuit 431 are the five bits (a 1 , a 4 , a 7 , a 10 , a 13 ) of the data outputted on the output signal line 421d from the flip-flop 420d, the four bits (a 2 , a 5 , a 8 , a 11 ) of the signal from the flip-flop 420e, and the four bits (a 3 , a 6 , a 9 , a 12 ) of the signal 420f from the memory 410. The OR circuit 431 detects whether even one of these inputs is "1" (a black dot). The inputs to the OR circuit 432 are the six bits (b 1 , b 5 , b 6 , b 7 , b 8 , b 9 ) of the data outputted on the output signal line 421c from the flip-flop 420c, the single bit (b 2 ) of the data outputted on the output signal line 421d from the flip-flop 420d, the single bit (b 3 ) of the data outputted on the output signal line 421e from the flip-flop 420e, and the single bit (b 4 ) of the data outputted on the output signal line 421f from the memory 410. The OR circuit 432 detects whether even one of these inputs is "1" (a black dot). Thus, the binary data monitoring unit 400 in accordance with this embodiment detects whether there is a "1" (a black dot) in two window areas of different sizes, and the result is outputted on signal lines 370a and 370b. Fig. 33 is a block diagram showing the detailed construction of the OR circuit unit 440 depicted in Fig. 31. In Fig. 33, numerals 441 and 442 denote OR circuits. The character b 7 shown in Fig. 33 is one bit of the signal on signal line 421c from the flip-flop 420c and is outputted on signal line 460a. This is also the binarized result of the pixel of interest in the binary data monitoring window for conversion of resolution. The inputs to the OR circuit 441 are the five bits (a 1 ′, a 2 ′, a 3 ′, a 4 ′, a 5 ′) of the data outputted on output signal line 421b from the flip-flop 420b, the four bits (b 5 , b 6 , b 8 , b 9 ) of the data outputted on the output signal line 421c from the flip-flop 420c, and the five bits (a 1 , a 4 , a 7 , a 10 , a 13 ) of the data outputted on the output signal line 421d from the flip-flop 420d. The OR circuit 441 detects whether even one of these inputs is "1" (a black dot). The inputs to the OR circuit 442 are the six bits (b 1 ′, b 3 ′, b 4 ′, b 5 ′, b 6 ′, b 7 ′) of the data outputted on the output signal line 421a from the flip-flop 420a, the bit (b 2 ′) of the data outputted on the output signal line 421b from the flip-flop 420b, the bit (b 1 ) of the data outputted on the output signal line 421c from the flip-flop 420c, the bit (b 2 ) of the data outputted on the output signal line 421d from the flip-flop 420d, and the output signal 460b from the OR circuit 441. The OR circuit 442 detects whether even one of these inputs is "1" (a black dot). It is detected whether there is a "1" (a black dot) in two window areas of different sizes as a result of binarizing the pixel of interest, and the result of detected is outputted on signal lines 460a - 460c. Fig. 36 is a diagram for describing the detailed flow of data through the memory 410 and flip-flops 420a - 420e shown in Fig. 31. When the series of processing operations ends in the above-described arrangement, the pixel of interest is shifted by one pixel to update the data in the window, and the foregoing processing is then repeated. At the end of processing, the five higher order bits (b 3 ′, b 4 ′, b 5 ′, b 6 ′, b 7 ′) of the data in flip-flop 420a are fed back to and stored in the five-line buffer 410 in order to be used in the next line of processing. Accordingly, the five higher order bits (b 3 ′, b 4 ′, b 5 ′, b 6 ′, b 7 ′) of the data outputted on the output signal line 421a from flip-flop 420a are fed back to and stored in the memory 410. At the same time, the result of binarization is inputted through signal line 360 to the MSB side of the flip-flop 420d, where the data is latched. Thus, the data in the flip-flops is shifted successively in synchronization with the clock, and the processed data in the flip-flops is stored in the five-line memory. <Description of Resolution Converting Circuit 500 (Figs. 37, 38)> Fig. 38 is a block diagram illustrating the detailed construction of the resolution converting circuit 500 according to this embodiment. As shown in Fig. 38, the converting circuit 500 includes the LUT 510, the OR gate 520, the flip-flop 530 for latching data, and the FIFO memory 540 for storing 11 lines of binary results and having 11 bits input/outputs. The content of LUT 510 is the same as that of the LUT shown in Fig. 30 described above. Fig. 37A is a diagram showing a black dot (*), which is located in a small window area, split or subdivided into small dots of higher resolution. Fig. 37B is a diagram showing a black dot (*), which is located in a large window area, split or sub-divided into small dots of higher resolution. As will be understood from Figs. 37A and 37B, dots are dispersed near the black dot (*), which is the pixel of interest, in the small window area and more distantly in the large window area. In a case where data on signal line 460a from the binary data monitoring unit 400 is "0", i.e., when the pixel of interest is white, two pixels of "0"s are outputted in the subordinate scanning direction regardless of the data value on the signal lines 460b and 460c from other window areas. Accordingly, as shown in Fig. 30, the LUT 510 outputs "0" data for all 12 bits from the LSB to the MSB. This data enters one input of the OR gate 520. Further, all 11 bits of output data from the memory 540 storing the results of processing which prevailed up to the preceding cycle are fed back in sequence from the LSB side and inputted to the other input of the OR gate 520. As a result, the output from the memory 540 is again inputted to the flip-flop 530 and therefore is rewritten. In a case where the pixel of interest is "1" (a black dot) and there was no "1" in the large window area, i.e., if the outputs on the signal lines 460b, 460c are both "0", then "1" (a black dot) is diffused far from the pixel of interest, as illustrated in Fig. 37B. Accordingly, the LUT 510 outputs "000100000100" in this order starting from the LSB, as shown in the LUT of Fig. 30, and this data enters one input of the OR gate 520. Furthermore, in a case where the pixel of interest is "1" (a black dot) and there was no "1" in the small window area but only in the area on the outside, i.e., if the outputs on the signal lines 460b, 460c are "0" and "1", respectively, then "1" (a black dot) is diffused near the pixel of interest, as illustrated in Fig. 37A. Accordingly, the LUT 510 outputs "000010001000" in this order starting from the LSB, as shown in the LUT of Fig. 30, and this data enters one input of the OR gate 520. Finally, in a case where the pixel of interest is "1" and there was a "1" also in the small window area, i.e., if the outputs on signal lines 460b and 460c are both "1", a "1" (black dot) is simply added alongside (in the subordinate scanning direction) the pixel of interest. Accordingly, as shown in the LUT of Fig. 30, the LUT 510 outputs "000000110000" in this order starting from the LSB, and this data enters one input of the OR gate 520. Thus, the pattern generated by the LUT 510 is applied to the OR gate 520, and the 11 bits fed back from the memory 540 storing the pattern which prevailed up to the preceding cycle are inputted to the OR gate 520 from the LSB side. The OR gate 520 performs a logical OR operation of each of these bits and applies the resulting bits to the flip-flop 530. In other words, the LSB of the output from the LUT 510 and the LSB of the output from the memory 550 both enter the OR gate 520, and these are outputted as the LSB. In addition, the second bit of the output from the LUT 510 and the second bit of the output from the memory 550 enter the OR gate 520, and these are outputted as the second bit. Thereafter, and in similar fashion, the 11th bit of the output from the LUT 510 and the MSB of the output from the memory 550 enter the OR gate 520, and these are outputted as the 11th bit. The MSB of the output from the LUT 510 is outputted directly from the OR gate 520 as the MSB. The LSB of the output from the flip-flop 530 is not delivered to the memory 550. This signal is outputted on signal line 560 to serve as the output signal. In accordance with this embodiment as described above, conversion of the resolution of the binarized image is executed in the subordinate scanning direction so that the image can be outputted upon having its resolution doubled by the conversion. [Fifth Embodiment (Figs. 39 - 42)] In this embodiment, a case will be described wherein conversion of the resolution of a binarized image is executed in a direction diagonal to the main scanning direction to split up dots. The splitting up of dots into smaller dots and the contents of the LUT will be described with reference to the drawings, based primarily upon the description of the resolution converting circuit 500 characterizing this embodiment. Fig. 39 is a block diagram illustrating the detailed construction of the resolution converting circuit 500 according to this embodiment. As shown in Fig. 39, the converting circuit 500 includes the LUT 510, the OR gates 520 - 522, the flip-flops 530-532 for latching data, the FIFO memories 550, 551 for storing one line of binary results and having a 2 bits input/outputs, and the shift register 540 for converting parallel data into serial data. Fig. 40A is a diagram showing a black dot (*), which is located in a small window area, split or subdivided into small dots of higher resolution. Fig. 40B is a diagram showing a black dot (*), which is located in a large window area, split or sub-divided into small dots of higher resolution. As will be understood from Figs. 40A and 40B, dots are dispersed near the black dot (*) in the small window area and more distantly in the large window area in this embodiment as well. Fig. 41 is a diagram showing the contents of the LUT 510 depicted in Fig. 39. Signal lines 516a, 516b, 516c respectively generate the first, second and third lines of a pattern. In a case where data on signal line 460a from the binary data monitoring unit 400 is "0", i.e., when the pixel of interest is white, two pixels of "0"s are outputted in the main scanning direction regardless of the contents of the data on the signal lines 460b and 460c from other window areas. Accordingly, as shown in Fig. 41, the LUT 510 outputs "0" data for all 12 bits from the LSB to the MSB on the signal line 516a of the first line, the signal line 516b of the second line, which is that of the pixel of interest, and the signal line 516c of the third line. This output enters the OR gates 520 - 522. The processing of a line executed using the OR gate 520, flip-flop 530 and shift register 540 will now be described. The inputs to the OR gate 520 are the 12 bits data outputted from the LUT 510 on signal line 516a, the 10 bits data, from the MSB side, of the 12 bits of output data from the flip-flop 530, which has stored the processed results up to the immediately preceding cycle, and a 2 bits data on signal line 556a from the memory 550, which has stored the results of processing from the second line onward. More specifically, as shown in Fig. 42, the third bit of data outputted on signal line 536a and the LSB of the data outputted on signal line 556a enter the LSB side of the OR gate 520, the data is outputted as the processing on the LSB side, and this output enters the LSB of the flip-flop 530. The second bit of output data on signal line 516a, the fourth bit of output data on signal line 536a and the second bit of data outputted on signal line 556a enter the second bit of the OR gate 520, the data is outputted as the second bit of processing, and this output enters the second bit of the flip-flop 530. Furthermore, the third bit of data outputted on signal line 516a and the fourth bit of the data outputted on signal line 536a enter the third bit of the OR gate 530, the data is outputted as the third bit of processing, and this output enters the third bit of the flip-flop 530. Thereafter, and in similar fashion, the tenth bit of the data outputted on signal line 516a and the MSB of the data outputted on signal line 536a are inputted to the tenth bit of the OR gate 520, and these are outputted as the tenth bit of processing. This output enters the tenth bit of the flip-flop 530. The 11th bit and the MSB of the data outputted on signal line 516a are inputted directly to the 11th bit and MSB of the flip-flop 530. The LSB and the second bit of the data outputted from the flip-flop 530 enter the shift register 540, whence they are outputted as a 2 bits serial. The processing of the second line, at which the pixel of interest is located, executed using the OR gate 521, flip-flop 531 and memory 550 will now be described. The operation regarding the second line is similar to that of the first line described above, and the data which passes through the signal line 556b from memory 551 enters instead of the data which passes through the signal line 556a from memory 550. Accordingly, the LSB and the second bit of data outputted on the signal line 516b, the third and fourth bits of data outputted on the signal line 536b from the flip-flop 531, and the LSB and the second bit of data outputted on the signal line 556b from the memory 551 respectively enter the LSB and second bit of the OR gate 521, and the result of processing is inputted to the LSB and the second bit of the flip-flop 531. The third through tenth bits of data outputted on the signal line 516b and the fifth bit through MSB of the output data from the flip-flop 531 respectively enter the third through tenth bits of the OR gate 521, and the result of processing is inputted to the third through tenth bits of the flip-flop 531. Furthermore, the 11th bit and the MSB of the data outputted on signal line 516b are inputted directly to the 11th bit and MSB of the flip-flop 531. The LSB and the second bit of the data outputted from the flip-flop 531 are written in the LSB and second bit of the memory 550. Finally, the processing of the third line executed using the OR gate 522, flip-flop 532 and memory 551 will be described. The operation regarding the third line is similar to that described above but, unlike the processing involving the first and second lines, there is no feedback from memory. More specifically, the LSB through the tenth bit of data outputted on the signal line 516c, and the third through MSB of the data outputted on the signal line 536c from the flip-flop 532 respectively enter the LSB through tenth bits of the OR gate 522, and the result of processing is inputted to the LSB through tenth bits of the flip-flop 532. The 11th bit and the MSB of the data outputted on signal line 516c are inputted directly to the 11th bit and MSB of the flip-flop 532. The LSB and the second bit of the data outputted from the flip-flop 532 are written in the LSB and second bit of the memory 551. If, in the above arrangement, the pixel of interest is "1" (a black dot) and there was no "1" in the large window area, i.e., if the outputs on the signal lines 460b and 460c are both "0", the "1" (black dot) is dispersed far from the pixel of interest and diagonally, as illustrated in Fig. 40B. Accordingly, as depicted in the LUT of Fig. 41, the LUT 510 produces the following outputs in the bit-order mentioned starting from the LSB: "000000000000", as the data of the 1 st line, from signal line 516a; "000000000100", as the data of the 2 nd line, from signal line 516b; and "000100000000", as the data of the 3 rd line, from signal line 516c. Subsequent processing is similar to that described above; only the data on the signal lines 516a, 516b and 516c changes. If the pixel of interest is "1" (a black dot), there was no "1" in the small window area but only in the window area outside this area, i.e., if the outputs on signal lines 460b and 460c are "0" and "1", respectively, the "1" (black dot) is dispersed near the pixel of interest and diagonally, as illustrated in Fig. 40A. Accordingly, as depicted in Fig. 41, the LUT 510 produces the following outputs in the bit-order mentioned starting from the LSB: "000000001000", as the data of the 1 st line, from signal line 516a; "000000000000", as the data of the 2 nd line, from signal line 516b; and "000010000000", as the data of the 3 rd line, from signal line 516c. Subsequent processing is similar to that described above; only the data on the signal lines 516a, 516b and 516c changes. Finally, in a case where the pixel of interest is "1" (a black dot) and there was a "1" also in the small window area, i.e., if the outputs on signal lines 460b and 460c are both "1", a "1" (black dot) is simply added alongside the pixel of interest. Accordingly, as shown in Fig. 41, the LUT 510 produces the following outputs in the bit-order mentioned starting from the LSB: "000000000000", as the data of the 1 st line, from signal line 516a; "000000110000", as the data of the 2 nd line, from signal line 516b; and "000000000000", as the data of the 3 rd line, from signal line 516c. Subsequent processing is similar to that described above; only the data on the signal lines 516a, 516b and 516c changes. In accordance with this embodiment, when conversion of resolution is applied to a binarized image, dots are split up in a direction diagonal to the main scanning direction and the image is outputted upon having its resolution doubled by the conversion. In each of the embodiments described above, a monochromatic image is dealt with as the image data. However, in a color image processing system comprising the colors Y (yellow), M (magenta), C (cyan) and BK (black), the present invention can be applied in similar fashion to each of the Y, M, C and BK items of data. In such case also, operations and effects almost the same as those described in the foregoing embodiments can be obtained. Though the error diffusion method is used as the binarization method in the five embodiments described above, this does not impose a limitation upon the invention; other binarization method may also be employed. As many apparently widely different embodiments of the present invention can be made without departing from the scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: An image processing apparatus for outputting an image having shades of light and dark based upon binary image data, comprising: input means (200, 300) for inputting binary image data; resolution converting means (500) for converting the resolution of the binary image data inputted by said input means in a manner such that the binary image data for one pixel becomes data for a plurality of pixels; and output means (600) for outputting a light-and-dark image based on an output obtained from said resolution converting means, characterised in further comprising: detecting means (400) for detecting in the binary image data inputted by said input means a pixel which is an isolated point, wherein, in said resolution converting means (500), the binary image data for the isolated pixel detected by said detecting means (400) is diffused into a broader area than an area required for the plurality of pixels obtained by said resolution converting means (500). Apparatus according to claim 1, wherein said input means comprises: multivalue image data input means for inputting multivalue image data, and binarising means (300) for binarising the multivalue image data. Apparatus according to claim 2, wherein the multivalue image data is data in which one pixel is expressed by eight bits and tones are capable of being expressed in 256 steps. Apparatus according to any preceding claim, wherein said detecting means (400) includes: searching means (Fig. 10) which, with regard to each pixel of the binary image data, searches for pixels peripheral to said pixel in order to detect the isolated point. Apparatus according to claim 4, wherein said search means includes: narrow-area searching means (441) which searches for peripheral pixels comparatively near said pixel; and wide-area searching means (442) which searches for peripheral pixels comparatively far from said pixel. Apparatus according to claim 5, wherein an area searched by said narrow-area searching means (441) and said wide-area searching means (442) is a rectangular area. Apparatus according to claim 5 or claim 6, wherein said narrow-area searching means (441) detects, by searching for the peripheral pixels, whether said peripheral pixels have a pixel whose value is "1". Apparatus according to any one of claims 5 to 7, wherein said wide-area searching means (442) detects, by searching for the peripheral pixels, whether said peripheral pixels have a pixel whose value is "1". Apparatus according to any one of claims 5 to 8, wherein said resolution converting means (500) diffuses the value of the pixel of the isolated point near the isolated point in a case where said search means has searched that there is a pixel whose value is "1" comparatively near the pixel of the isolated point, said resolution converting means (500) diffuses the value of the pixel of the isolated point far from the isolated point in a case where said search means has searched that there is a pixel whose value is "1" comparatively far from the pixel of the isolated point, and said resolution converting means (500) diffuses the value of the pixel of the isolated point to a pixel alongside the isolated point in a case where said search means has searched that there are pixels whose value is "1" comparatively near and comparatively far from the pixel of the isolated point.

Inventors: BANNAI YUICHI, SATO TOSHIHIKO, YAMAMOTO KUNIHIRO, BANNAI, YUICHI, SATO, TOSHIHIKO, YAMAMOTO, KUNIHIRO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N1
IPC codes: H04N1