Improved high voltage thin film transistor having a drift region with a linear doping profile and a field plate

Abstract: The present invention involves an improvement in the structure and method for making a high voltage thin film transistor of the silicon-on-insulator (SOI) type. In particular, the present invention sets forth the structure and technique for making this improved structure in which a gate electrode is formed extending over the linear doping profile so as to shield the drift region from external electric fields and decrease on-state resistance.

Description: The invention relates to a thin film SOI device, comprising a buried oxide layer, a thin layer of silicon on said buried oxide layer having a drift region, a top oxide layer on said thin layer of silicon, a gate region at the one end of said drift region said gate region including a gate electrode and a field plate extending from said gate electrode over said drift region, a drain region at the opposite end of said drift region and a source region laterally separated from said gate region. Such a device is known from US Patent No. 3,845,495. The present invention seeks to improve the breakdown voltages of the known device. Therefore the device is characterized in that the doping level in the drift region in the thin layer increases in a lateral direction a substantially linear and continuous way from the one end of the drift region to the opposite end of the drift region, where said buried oxide layer and said top oxide layer have substantially the same thickness. The gate electrode is formed at one side of the drift region which is covered by an upper oxide layer. Accordingly, the gate electrode extends from the gate region laterally over the top of this oxide layer to cover all of the underlying drift region of the silicon layer. In the inventive device a well protected drift region is provided since any impinging electric field, caused by moisture or other charged contaminants on the surface of the wafer, will terminate on the field plate of the gate electrode overlying the drift region. Further because of the buried and top oxide layer having the same thickness, the drift region may now be depleted from both the top and bottom, so that twice the conducting charge may be placed on the drift region to lower the on-resistance. It is further known from EP application 497427 which was published after the priority date of the present application to provide a thin film SOI device with a lateral linear doping drift region, i.e. a drift region which has a certain dope level at one side of the drift region, which dope level changes in a linear way in a lateral direction of the drift region from a relatively low level near the gate region to a relatively high level near the drain region. In this known device the silicon layer is provided as a thin layer of silicon having a thickness of about 200 to 300 nanometres. This structure forms a SOI semiconductor device having a high breakdown voltage characteristic. It is further known from US Patent No. 4,172,260 to use a drift region with a graded doping profil to increase breakdown voltages. The method of manufacturing this improved structure comprises forming a silicon layer on a buried oxide layer with the buried oxide layer being formed on a semiconductor substrate, forming a lateral linear doping region in the silicon layer, selectively thinning the drift region by local oxidation (LOCOS), leaving a thick top oxide layer over the drift region, and forming a gate region at a side of the top oxide layer with the gate region having a gate electrode with a portion extending laterally over a substantial portion of the top oxide layer where the lateral extent of the gate electrode overlies the thin lateral linear doping region. This technique of the present invention achieves the high voltage SOI semiconductor device having the improvements of the present invention. The invention will be described in detail, by way of example, with reference to the drawing figures. Therein: Figure 1 illustrates in cross-section the improved thin film transistor according to the present invention; and Figure 2 illustrates a simulated computer plot of potential contours in a device having a lateral gate extension according to the present invention. Similar reference numbers are used to identify corresponding parts of respective drawings. The improved SOI transistor of the present invention is illustrated in Figure 1. Therein, a substrate 3 which may be either n-type or p-type conductivity of any resistivity is provided. An oxide layer 2 is deposited onto this substrate layer. The thickness of the oxide layer 2 ranges from about 1 to 1.5 microns. Onto the oxide layer 2 is formed a silicon layer 1 having a linear lateral doping region 4. The formation of this linear lateral doping region is similar to that in EP application 497427. This way an SOI structure is formed, with the oxide layer 2 now forming the buried oxide layer 2. The area of the SOI device is surrounded by isolation regions 5 of insulating material. The silicon layer 1 is selectively thinned to a thickness ranging from 100 to 200 nanometres by standard LOCOS techniques. This involves using a mask of silicon nitride around the region 4 and growing a 1 to 1.5 micron thick layer of thermal silicon dioxide 6. This leaves the thinned layer 4 with the lateral linear doping profile providing the drift region of the SOI device. A polysilicon gate electrode and field plate 7 is formed by first growing a thin gate oxide 8 having a thickness of approximately 60 nanometer at the side of the oxide 6. Thereafter, 500 nanometres of polysilicon are deposited thereon to form the gate electrode and field plate region. In accordance with the present invention, a mask is provided before forming the gate electrode 7 to expose the upper surface of the silicon dioxide layer 6 so that the gate electrode 7 extends onto the surface of the upper oxide layer 6 as the field plate region. This field plate extends from the gate electrode over the drift region portion of the thinned silicon layer 4. The source and drain regions 10 are then formed of N+ conductivity, for example, at the sides of the gate and drift region. A p+ source region 11 is also formed so that the source contact 12 contacts both regions. A drain contact 12 is formed in contact with the drain region 10, while a gate contact 12 is formed in contact with the gate region 7 overlying the thin oxide layer 8. The top oxide layer 6 is formed with a thickness equal to the buried oxide layer 2. Also, the field plate of the gate electrode 7 extends laterally over the drift region 4. A well protected drift region 4 is provided since any impinging external field, caused by moisture or other charged containments on the surface of the wafer, will terminate on the field plate of the gate electrode overlying the drift region. Further, the drift region may now be depleted from both the top and bottom so that twice the conducting charge may be placed on the drift region to lower the on-resistance. In addition, since the SOI film is thick (0.75 - 1.25 microns) in the source and drain regions, the p-body 9 is not left floating as in the known device. Figure 2 shows a simulated computer plot of the electrostatic potential contours in a typical device having the field plate and gate 7 of the present invention. Such a SOI device has a high breakdown voltage of approximately 710 volts. The optimized drift region has a lateral doping profile n(x) with a peak doping near the drain region which is twice that of an identical structure without the gate electrode and field plate 7. The minimum drift region doping of the drift region 4, i.e. toward the gate structure, is also increased by a factor of 2.

Claims: A thin film SOI device, comprising a buried oxide layer (2), a thin layer of silicon (1) on said buried oxide layer (2) having a drift region (4), a top oxide layer (6) on said thin layer of silicon (1), a gate region at the one end of said drift region (4) said gate region including a gate electrode (7) and a field plate (7) extending from said gate electrode (7) over said drift region (4), a drain region (10) at the opposite end of said drift region (4) and a source region (10) laterally separated from said gate region, characterised in that the doping level in the drift region (4) in the thin layer (1) increases in a lateral direction in a substantially linear and continuous way from the one end of the drift region (4) to the opposite end of the drift region (4), where said buried oxide layer (2) and said top oxide layer (6) have substantially the same thickness. A thin film SOI device as claimed in Claim 1, wherein said buried oxide layer (2) and said top oxide layer (6) each have a thickness ranging from about 1 to 1.5 microns. A thin film SOI device as claimed in Claim 1, wherein said layer of silicon (1) has a thickness ranging from 100 to 200 nanometres. A thin film SOI device as claimed in Claim 1, wherein said gate electrode (7) and said field plate (7) each have a thickness of 500 nanometres. A method of making a semiconductor device according to any of the preceding claims, comprising the steps of (a) forming a silicon layer (1) on a buried oxide layer (2), said buried oxide layer (2) being formed on a semiconductor substrate (3), (b) forming a drift region (4) in said silicon layer (1), (c) simultaneously thinning said drift region (4) to a reduced thickness, and depositing a top oxide layer (6) over the thinned drift region (4), and (d) forming a gate region at a side of said top oxide layer (6), characterized in that the drift region is formed with a doping level that increases in a substantially linear way in a lateral direction from one end of the drift region (4) to the opposite end of the drift region, where said gate region has a gate electrode with a field plate (7) extending laterally over a substantial portion of said top oxide layer (6), the lateral extent of said field plate (7) overlying said drift region (4). A method according to Claim 5, characterised in that said buried oxide layer (2) and said top oxide layer (6) are formed with equal thickness. A method according to Claim 5, characterised in that said buried oxide layer (2) and said top oxide layer (6) are each formed with a thickness of about 1 to 1.5 micrometers. A method according to Claim 5, characterised in that said lateral linear doping region (4) is thinned to a thickness ranging from about 100 to 200 nanometres. A method according to Claim 5, characterised in that said silicon layer (1) from step (a) is formed to a thickness of about 0.75 to 1.25 micrometers.

Inventors: MERCHANT STEVEN, MERCHANT, STEVEN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H01L29
IPC codes: H01L29, H01L21