System for detecting failure in dual bus user network

Abstract: In each of a plurality of subscriber systems included in a B-ISDN for controlling access competition among a plurality of terminals under the DQDB protocol, the terminals (13) are electrically connected to a dual bus comprising a downbus (2a) and an upbus (2b) both extending from a network terminal (1). Each of the terminals has data transmission processing means (8), downbus processing means (10a), upbus processing means (10b), a timer (11) and failure detecting means (12). When data transmission request is issued from the data transmission processing means (8), the failure detecting means (12) is activated in response to this request to start the timer (12) so as to count a given time interval which has elapsed. If either a request message or data cannot be sent even when the timer takes time out, then the failure detecting means (8) determines that a failure has occurred in the dual bus.

Description: (1) Field of the Invention: The present invention relates to failure detecting systems in user networks and to a terminal for a user network. (2) Description of the Related Art: The research of the broad-band ISDN (Integrated Services Digital Network) has been developed to put an ISDN in which broad-band communication such as video communication and so forth is possible for practical use. The broad-band ISDN is currently realized by using an ATM (Asynchronous Transfer Mode). In the ATM, data is transferred by dividing it into fixed-length short packets called cells. The cells are exchanged and transferred by an ATM exchange or a node. In the ATM, a circuit or, in other words, a line between a sender and a receiver, is not always provided at any time, but a virtual circuit or virtual line is provided through which a necessary ATM cell is transmitted. Therefore, a plurality of virtual circuits commonly have a single transmission line. In this multiplication, a multiplication method called a statistical multiplication is employed. It is necessary to manage the statistical multiplication in such a way that the total data multiplied on a single transmission line does not exceed the capacity of the transmission line. By this, an effect of the multiplication is generated so that the efficient use of the circuit can be increased. Techniques has been developed to treat congestion when it occurs. For subscribers connected to such a broad-band ISDN, a plurality of data receiving/transmitting devices called terminal equipments or terminal adapters in a customer station are connected through a bus. As a configuration of the bus (a user network), a DQDB (Distributed Queue Dual Bus) is considered to be favorable. The present invention relates to a failure detecting system in an ISDN in which the communication between a local switch and each of the terminal equipments or terminal adapters is carried out in accordance with the DQDB protocol. In the broad-band ISDN communication employing the DQDB protocol in the user network side, congestion may be generated in an apparatus in the network side. The apparatus in which congestion may be generated may be an ATM exchange, a local switch, or any processing device for processing ATM cells. To relieve congestion generated in the apparatus at the network side, it can be considered to restrict a subscriber, which is sending ATM cells to the apparatus, in which the congestion has occurred, to transmit a cell. In a conventional congestion relieving system, a network terminator inserts busy bits equal to "1" into busy bit areas of cells in accordance with a required rate of restriction of cells to be transmitted. This conventional system is disclosed in the prior published applications US-A-5 231 630, filed on April 10, 1991 and US-A-5 341 373, filed on February 5, 1992. The cells having the busy bits equal to "1" are deemed as those being used by the terminal equipments or the terminal adapters. Therefore, no terminal equipment or a terminal adapter inserts data into these cells with the busy bits = "1". Accordingly, the cells with the busy bits ="1" inserted at the network terminator have no destination so that, when these cells are received by an apparatus such as an ATM exchange and so forth, these cells are deemed invalid so that they are discarded. As a result, the number of cells to be transmitted to the apparatus, such as the ATM exchange in which the congestion has been generated, is decreased and the congestion is relieved. In a conventional system described above, however, it has not been considered a failure in transmission of each cell to a bus. SUMMARY OF THE INVENTION It is an object of the present invention to provide a system capable of rapidly detecting any failure developed in the control of a cell based user network. According to one aspect of the invention there is provided a system as set out in claim 1. Another aspect of the invention is set out in claim 4. A terminal according to the invention is set out in claim 5. Preferred features are set out in dependent claims. According to the present invention, each of a plurality of terminals 13 respectively electrically connected to dual bus means 2 composed of a downbus 2a and an upbus 2b both extending from network terminal means 1, is provided with data transmission processing means 8, downbus processing means 10a, a timer 11 and failure detecting means 12, as illustrated in FIG. 1 which describes the principle of the invention. When a data transmission request is issued from the data transmission processing means 8, the failure detecting means 12 is activated in response to this request to start the timer 11 so as to count a given time interval which has elapsed from its start. Then, a failure in each bus is detected when either a request message or data cannot be transmitted after the given time interval has elapsed. At this time, it is determined based on information output from the downbus processing means 10a whether or not the request message has been transmitted during the given time interval. Further, it is determined based on information output from the upbus processing means 10b whether or not actual data has been transmitted during the given time interval. That is, when a cell 7 having a request bit 3 with a request message (i,e., "1") written therein is not transmitted from the downbus processing means 10a, it can be judged that a failure has occurred in the downbus 2a. On the other hand, when the actual data cannot be transmitted during the given time interval in spite of the fact that the request message has been sent, it can be judged that a failure has occurred in either the downbus 2a or the upbus 2b which extends in the downstream direction (i.e., in the left-side direction as seen in FIG. 1). According to the present invention, as has been described, any failure in the transmission of the data to the bus, which is developed under the bus control of the DQDB system, can rapidly be detected, thereby making it possible to rapidly deal with such failure. The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which preferred embodiments of the present invention are shown by way of illustrative example. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for describing the principle of the invention; FIG. 2 is a diagram for describing the structure of a system to which first and second embodiments of the present invention are applied; FIG. 3 is a block diagram showing a subscriber's downbus system employed in a subscriber station according to the first embodiment; FIG. 4 is a flowchart for describing a processing sequence of the first embodiment; FIG. 5 is a block diagram illustrating a bus system employed in a subscriber station according to the second embodiment; FIG. 6 is a flowchart for describing a processing sequence of the second embodiment; FIG. 7 is a diagram for describing a format of each cell employed in an ATM; FIG. 8 is a diagram for describing a subscriber station or system in a B-ISDN; FIG. 9 is a diagram for describing status transition of a terminal (TE) 13 used to describe a prior art; and FIG. 10 is a diagram for describing operations of a request counter (RC) and a down counter (DC) which perform competitive control simultaneously. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, the DQDB protocol will be described hereinafter in detail. In a system on a subscriber side, there is used an arrangement in which a plurality of terminals 13 (TE) are electrically connected to network terminal means (NT) by buses. As a system for controlling access competition among the terminals 13 connected to the network terminal by the buses, a DQDB (Distributed Queue Dual Bus) has been effective. A simple description will now be made of the DQDB with reference to FIGS. 7 and 8. FIG. 7 is a diagram for describing a format of a cell 7 under the ATM. FIG. 8 is a diagram for describing a subscriber station or system in the B-ISDN. The format of the cell 7 in the ATM comprises a header 5 having a capacity of 5 bytes and an information field 6 having the capacity equivalent to 48 bytes. The header 5 includes a busy bit 4 and a request bit 3 each represented in a capacity of 1 bit. The busy bit 4 is used to make a judgment as to whether or not effective data has been stored in the information field 6 of the cell 7. When the data has been written into the information field 6, "1" is entered or registered in the busy bit 4. The request bit 3 is used to make a judgment as to whether or not a request for writing data into the cell 7 has been made. When the data writing request is received from the terminal 13, "1" is entered in the request bit 3. That is, when a data transmission request is issued from a certain terminal 13, a cell 7 having a request bit 3 with "0" entered therein is basically firstly accessed to the downbus 2a. Then, the cell 7 having the request bit 3 set to "1" is returned to the downbus 2a again. Further, the terminal 13 waits for a cell 7 having a busy bit 4 with "0" entered therein, which appears on the upbus 2b, and performs a process for storing data in the cell 7 and transferring the cell 7 to the upbus 2b. It is obvious that access competition by the request takes place among a plurality of terminals 13 at this time. A procedure for controlling the access competition will, however, be described below with reference to FIG. 8. As subscriber stations or systems, there have been known those having structures in which a plurality of terminals such as general subscribers, a LAN or PBX, etc. are accommodated. Now, FIG. 8 shows a subscriber system in which a given number of terminals (TE) are electrically connected in parallel to network terminal means (NT) 1 by buses 2a, 2b. When the terminals (TE) are not activated in the ATM, they are connected to the network terminal means 1 by a terminal adaptor (TA). In this case, each of the terminals (TE) and the terminal adaptor (TA) are called generically the terminal (TE) 13 in the following description. The terminal (TE) 13 is electrically connected to the downbus 2a and the upbus 2b of the network terminal means (NT) 1. When the terminal (TE) 13 receives data, it provides access to a necessary cell over the downbus 2a. When data is transmitted from the terminal (TE) 13, necessary data is written into an information field 6 of an empty cell 7 while being passing through the upbus 2b by way of the downbus 2a. At this time, the following control is performed to adjust the access competition. FIG. 9 is a diagram for describing status transition of a terminal (TE) 13. FIG. 10 is a diagram for describing operations of a request counter (RC) and a down counter (DC) which perform competitive control. The request counter (RC) and the down counter (DC) are disposed in the terminal (TE) 13. The request counter (RC) is used to count the number of transmission requests of a terminal on the downstream side (network terminal means 1 side): the terminal 13 located on the side of the network terminal means 1 will hereinafter be referred to as an "higher-order terminal") of the upbus 2b as viewed from the present terminal. The down counter (DC) goes down to the presentterminal's turn to allot or set up a cell 7 in advance with respect to a request taking the precedence over a request by the present terminal. The access competition is controlled by each of the two types of these counters. When a data transmission request is issued in a state in which the terminal (TE) 13 is idle (Step 90 in FIG. 9) as shown in FIG. 9, a request message is sent to the downbus 2a (see FIG. 8) (Step 91 in FIG. 9). The request message is entered or registered in the request bit 3 of the ATM cell shown in FIG. 7 as "1". When the count of the request counter (RC) does not reach "0" at this time, the down counter (DC) is loaded with the count of the request counter (RC) so as to reset the request counter (RC) to "0". As a result, the request counter is ready to count down, i.e., the routine procedure proceeds to a count-down state (Step 93 in FIG. 9). Further, when the count of the request counter (RC) reaches "0", the routine procedure proceeds to a Ready state (Step 92). The count of the request counter (RC) represents the number of request messages generated from terminals 13 located on the higher-order side as viewed from the present terminal. Thus, when the count of the request counter (RC) reaches "0", no request is issued from the higher-order terminal, so that the routine procedure can immediately proceeds to the Ready state (Step 92 in FIG. 9). After the request counter has gone down to zero, the down counter (DC) is decremented by 1 each time a cell having a busy bit 4 (see FIG. 7) with "0" entered therein travels along or passes through the upbus 2b. When the count of the down counter (DC) reaches "0", the routine procedure proceeds to the Ready state (Step 92). When a cell having a busy bit indicative of "0" appears on the upbus in the Ready state, data is entered in the information field 6 of the cell and such a cell is sent to the bus (Step 94). Operations of the request counter and the down counter at the respective states, which have already been described in FIG. 9, will now be described with reference to FIG. 10. FIG. 10A shows the operation of the request counter (RC) from an idle state to request transmission. The request counter (RC) of the terminal (TE) 13 counts up, i.e., is incremented by 1 when a cell having a request bit 3 indicative of "1" passes through a downbus 2a. In addition, the request counter (RC) counts down, i.e., is decremented by 1 when a cell having a busy bit 4 indicative of "0" passes through an upbus 2b. As a result, the request counter (RC) counts the number of request bits of a cell transmitted by a higher-order terminal (TE) 13 located on the upstream side of the present terminal (TE), and counts down to unused or free cells which can be transmitted by the higher-order terminal. Now, FIG. 10B shows the below-mentioned operation of another request counter (RC). That is, a cell having a request bit indicative of "1" is sent to a downbus 2a. Then, the down counter (DC) is loaded with the count of the request counter (RC) so as to reset the request counter (RC) to zero. Thereafter, the routine procedure proceeds to the count-down state (Step 93 in FIG. 9), and the routine procedure proceeds to the Ready state when the count of the request counter (RC) reaches "0". The count operation of the request counter (RC) under this condition is carried out to confirm the number of a dispersed queue after a cell have been transmitted to a corresponding bus. Thus, the request counter (RC) is incremented by 1 under this condition when a cell having a request bit 3 indicative of "1" travels along or passes through a downbus 2a. However, the request counter (RC) does not count down even if a cell having a busy bit 4 indicative of "0" passes therethrough. That is, the down counter (DC) shown in FIG. 10C counts the number of incoming cells which can be transmitted by the present terminal. FIG. 10C shows the operation of the down counter (DC), which will be carried out in the following manner. That is, a cell having a request bit indicative of a desired value is sent to a downbus 2a. Then, the down counter (DC) is loaded with the count of the request counter (RC), so that the down counter is brought into the count-down state (Step 93 in FIG. 9). When a cell having a busy bit 4 indicative of "0" travels along an upbus 2b, the down counter (DC) is decremented by 1. When the count of the down counter (DC) reaches "0", the cell is sent (Step 94 in FIG. 9). Since a process for controlling the access competition by the requests among the terminals is carried out by using the request counter (RC) and the down counter (DC) as described above, the access competition control can be performed with a small time-delay. It has, however been found out by the present inventor that the prior art has the following problems. When a failure in transmission of each cell to a downbus 2a occurs in a higher-order terminal (i.e., a terminal as seen in a left to right arrangement from the present terminal in FIG. 8), for example, it is considered that each cell 7 having a request bit indicative of "1" is continuously sent to the downbus 2a. A first embodiment of the present invention will hereinafter be described. The present embodiment is effective in a case in which a request message itself cannot be sent owing to the failure of a higher-order terminal. As shown in Fig. 2, an ATM network 14 employed in the present embodiment comprises interconnected main exchangers 15 and a plurality of subscribers' exchangers 16 connected in cascade to the main exchangers 15. Further, network terminals (NT) 1 are elecrically connected in cascade to the respectively coresponding subscribers' exchangers 16. A plurality of terminals (TE) 13 are electrically connected directly any/or via terminal adaptors (TA) 17 to respectively corresponding buses (dual buses) 2 of the network terminals (NT)1. Subscriber stations or systems respectively comprises the network terminals (NT)1, the terminals (TE)13 and the termianl adaptors (TA) 17. FIG. 3 shows the structure of one subscriber system according to the present embodiment. Each of the terminals 13 has data transmission processing means 8, downbus processing means 10a, failure detecting means 12, a request counter (RC), and a down counter (DC). The data transmission processing means 8 has a function for transmitting data therefrom and a function for generating a data transmission request as a message, both information being sent to the downbus processing means 10a and the failure detecting means 12. The downbus processing means 10a takes in a cell 7, i.e., brings it from the downbus 2a, which travels therealong, and performs a process for writing request message into a request bit 3 in a header field 5 of the cell 7, for example. The result obtained by such a process of the downbus processing means 10a is sent to the failure detecting means 12 as a request transmission message. The failure detecting means 12 has a timer 11, which, in turn, serves as a subtractive timer and is loaded with an initial value from either a ROM or RAM (not described in Fig.3) in response to a start instruction so as to start a subtractive process, i.e., count down. Referring now to FIG. 3, a first terminal 13a, a second terminal 13b and a third terminal 13c are electrically connected to the downbus 2a and the upbus 2b. Let's now assume that, for example, the first terminal 13a is regarded as a higher-order terminal as viewed from the second terminal 13b, whereas the third terminal 13c is regarded as a lower-order terminal as seen from the second terminal 13b. A description will now be made principally of the second terminal 13b in the present embodiment. When a data transmission request is issued from the second terminal 13b, the cell having the request bit with "0" entered therein is accessed as has been described even in the prior art, and respective processes shown in FIGS. 9 an 10 are executed to transmit intended data at the final stage. However, when an error occurs in the cell 7 in which a request bit indicative of "1" has continuously been entered therein in the first terminal 13a as the higher-order terminal, the second terminal 13b cannot access to a cell 7 having a request bit indicative of "0". Therefore, the second terminal 13b cannot proceed to the routine procedures subsequent to Step 91 shown in FIG. 9. At this time, the second terminal 13b executes the following processes. When a data transmission request is first issued from the data transmission processing means 8 of the second terminal 13b (Step 401 in Fig.4), the timer 11 is activated (Step 402). In addition, the routine procedure 92 or 93 shown in FIG. 9 is executed parallel to the start of the timer 11. That is, the timer 11 is started simultaneously with the routine procedure (subsequent to the routine procedure 92 or 93) for the data transmission. Only when data cannot be transmitted before the timer 11 takes time out as will be described later, such a state is detected as a failure. The timer 11 now counts down as described above. When the count of the timer 11 reaches "0", a time-out signal is generated. In addition, a time-out period varies depending on a bus zone or band but may be a several mm secs when the data signalling rate ranges from 150 Mbps to 600 Mbps. When a plurality of terminals 13 are interconnected, the time-out period may be rendered longer as the terminals 13 are moved into lower-order places. That is, a higher priority is given to each of higher-order terminals upon the request transmission. This is because the time from the generation of a request to the actual transmission of data is long as the terminals 13 are moved into the lower-order places. During a period from the start of the timer 11 to the time-out, the failure detecting means 12 determines (in Step 404) whether or not a request message has been sent by the downbus processing means 10a, i.e., a cell 7 into which a request bit indicative of "1" has been written, has been transmitted. If the answer is determined to be yes in Step 404, the timer 11 is cleared (Step 405) and placed in the initial state (Step 400). When the time-out is carried out in a state in which the delivery of the request is not being performed (Step 403), a warning buzzer produces a sound indicative of a failure in the data transmission or a warning lamp is lighted to indicate or display the failure (Step 406). According to the present embodiment, as described above, a failure in the transmission of the data to the bus connected to the higher-order terminal 13a as seen from the present terminal 13b can easily be detected by monitoring a given time interval which has elapsed from the data transmission request. Incidentally, the initially-set value of the timer 11 of each of the terminals 13 may be changed depending on the number of the higher-order terminals or the processing capacity of each terminal. In the present embodiment, the terminal 13b has determined in Step 404 of FIG. 4 "whether or not a request message has been sent". However, the routine procedure in Step 404 may be replaced by a routine procedure for determining "whether or not actual data has completely been sent". When the actual data cannot be transmitted after the given time interval has elapsed from the time of the data transmission request, such replacement process can provide an advantageous effect in that a failure can relatively easily be detected although it is difficult to specify a point at which the failure occurs. A second embodiment will now be described below. The present embodiment is effective in an unwanted failure by which data cannot actually be transmitted in spite of the fact that a request message has been sent. FIG. 5 is a block diagram showing a bus system employed in a subscriber system or station according to this embodiment. Each of terminals 13 employed in the present embodiment basically comprises downbus processingunit 10a described in the first embodiment, failure detecting means 12, upbus processing means 10b, a request counter (RC) 18, and a down counter (DC) 20. The failure detecting means 12 has a subtractive timer 11 similar to that described in the first embodiment, which is, in turn, loaded with an initial value from either a ROM or a RAM (not described in Fig.5), for example, in response to a start instruction so as to start a subtractive process, i.e., count down. A method or system of detecting a failure will now be described below with reference to FIGS. 5 and 6. When a data transmission request is issued from data transmission processing means 8, for example, in FIG. 5, the value of request counter (RC) 18 is loaded in the down counter (DC). The request counter (RC) 18 is responsive to the data transmission request so as to count the number of cells 7 each of which travels along or passes through a downbus 2a and having a request bit 3 (= "1") into which a request message has been written as data. As a result, the number of the terminals 13 which are located on the higher-order side as seen from the present terminal (the second terminal 13b in the present embodiment) and have already issued data transmission requests, can be counted. When the downbus processing means 10a brings a cell 7 having a request bit 3 which is null (i.e., the request bit 3 with "0" entered therein) from the downbus 2a, the downbus processing means 10a registers a request message into the request bit 3 (i.e., the request bit 2 = "1") of the cell 7 as data and delivers the cell 7 into the downbus 2a again. When the upbus processing means 10b brings cells 7 from the upbus 2b, the down counter (DC) 20 counts the number of the cells 7 each having a busy bit 4 which is empty, i.e., the cells 7 each having an information field which is vacant. That is, each idle or empty cell 7, which passes through the second terminal 13b before the count of the down counter (DC) 20 reaches "0", is used for the data transmission of a higher-order terminal as viewed from the second terminal 13b. When the count of the down counter (DC) 20 has reached "0", the data used for the transmission request issued by the terminal referred to above is written into the information field 6 of the next vacant cell 7 so as to be sent to the upbus 2b. When a failure occurs in a lower-order terminal, e.g., a third terminal 13c as seen from the second terminal 13b, and the writing of "1" into the busy bit 4 is being continued, a cell having a busy bit indicative of "0" never reaches the upbus processing means 10b of the second terminal 13b. Therefore, the second terminal 13b cannot transmit desired data. According to this embodiment, when the failure detecting means 12 receives a request transmission message from the downbus processing means 10a (Step 601 in Fig.6), the timer 11 is started (Step 602). During a period from the start of the timer 11 to the time-out, the failure detecting means 12 determines (in Step 604) whether or not data has been transmitted by upbus processing means 10b, that is to say, the down counter (DC) 20 determines (in Step 604) whether or not data has been written into the information field 6 of the cell 7 having the busy bit 4 (= "0") after having gone down to "0", and the cell 7 has been transmitted to the upbus 2b. If the answer is determined to be yes in Step 604, the timer 11 is cleared (Step 605), and placed in the initial state (Step 600). When the time-out is carried out in a state in which the delivery of the data to the upbus 2b is not being performed (Step 603), a warning buzzer produces a sound indicative of a failure in the data transmission or a warning lamp is lighted to indicate or display the failure (Step 606). According to this embodiment, as described above, the failure in the transmission of the data to each bus connected to the lower-order terminal 13c as seen from the present terminal 13b can easily be detected by monitoring the given time interval which has elapsed from the time of the data transmission request. Incidentally, the initially-set value of the timer 11 of each of the terminals 13 may be changed depending on the number of the lower-order terminals or the processing capacity of each terminal. Having now fully described the invention, it will be apparent to those skilled in the art that many changes and modifications can be made without departing from the scope of the claims.

Claims: A system for detecting failures in a user network which transmits and receives information in cell form said system comprising: network terminal means (1); dual bus means including a downbus (2a) and an upbus (2b), both connected to said network terminal means for transmitting a cell having at least a header field indicative of the manner in which either a data transmission request as message or information has been stored and an information field with data stored therein; and a plurality of terminals (13), each connected to said dual bus means, including data transmission processing means (8) for issuing a data transmission request, downbus processing means (10a) for bringing said cell from said downbus to subject the same to a given process, followed by delivering to said downbus, and failure detecting means (12) for activating a timer (11) counting a given time interval in response to the data transmission request issued from said data transmission processing means and for detecting a transmission failure when the transmission of the information registered in said information field of said cell has not been detected before said timer takes time out. A system according to claim 1, wherein the time-out period of said timer is long as each of terminals other than a terminal located at the position nearest said network terminal means is progressively spaced away from said terminal nearest said network terminal means along said dual bus means. A system according to claim 1, wherein the header field of the cell, including a request bit for entering a request message therein and a busy bit for determining whether or not data has been stored therein; whereby said failure detecting means is activated to start said timer when a cell having a request bit with a request message entered therein is sent to said downbus after the data transmission request has been issued from said data transmission processing means in each of said terminals and to detect a failure in said dual bus means when a cell traveling along said upbus and having an empty busy bit is accessed and the transmission of said accessed cell having an information field with data entered therein to said upbus has not been detected before said timer takes time out. A system for detecting failures in a user network which transmits and receives information in cell form, said system comprising: network terminal means (1); dual bus means including a downbus (2a) and an upbus (2b), both connected to said network terminal means for transmitting a cell having at least a header field including a request bit for entering a request message therein, and an information field for storing data therein; and a plurality of terminals (13), each connected to said dual bus means including data transmission processing means (8) for issuing a data transmission request, downbus processing means (10a) for bringing said cell from said downbus to subject the same to a given process, followed by delivering to said downbus, and failure detecting means (12) for activating a timer (11) counting a given time interval in response to the data transmission request issued from said data transmission processing means and for detecting a failure in said dual bus means when said cell is accessed and the entry of the request message in said request bit of said cell has not been detected, before said timer takes time out. A terminal for a user network which transmits and receives in cell form by dual bus means said cell having a header field including a request bit for entering a request message therein, and a busy bit for indicating whether or not data has been stored in the cell, said terminal comprising: data transmission processing means (8) for issuing a data transmission request; downbus processing means (10a) for bringing a cell from a downbus in said dual bus means to subject the same to a given process and thereafter delivering the cell to said downbus; upbus processing means (10b) for bringing a cell from an upbus in said dual bus means to subject the same to a given process and thereafter delivering the cell to said upbus; request counter means (18) for accessing cells traveling along said downbus so as to count the number of request bits each time said cells having the request bits with request messages entered therein pass through said downbus; down counter means (20) for accessing cells traveling along said upbus so as to count down each time said cells having busy bits indicative of vacant states pass through said upbus; timer means (11) for starting counting a given time interval each time a cell with either a data transmission request or a request message registered therein is transmitted; and failure detecting means (12) for determining based on a time-out message from said timer means whether or not a failure has occurred in the dual bus means.

Inventors: ISHIBASHI RYOICHI, OHMORI HISAKAZU, TACHIBANA TETSUO, ISHIBASHI, RYOICHI, OHMORI, HISAKAZU, TACHIBANA, TETSUO, Ishibashi, Ryoichi, c/o Fujitsu Limited, Ohmori, Hisakazu, c/o Fujitsu Limited, Tachibana, Tetsuo, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H04Q11
IPC codes: G06F11, G06F13, H04Q11, H04L12