Method and circuit for noise shaping

Abstract: A noise shaping circuit permitting a wide dynamic range for input signal and having an improved S/N ratio. In Fig. 1, the circuit comprises a delay part 3 for delaying the output signal for a one-sampling period; a first subtraction part 1 for subtracting the delayed signal, via the delay part 3 from the input signal imparted to the input terminal so as to generate first subtraction results; a first integration part 2 for integrating the first subtraction results; a second subtraction part 4 for subtracting the input signal from the first integrated value of the part 2; a second integration part 5 for integrating the second subtraction value so as to obtain a second integrated value; an addition part 7 for adding the first and second integrated values so as to obtain an addition results, and a quantizer 6 for quantizing the addition results. The amplitude of the signal imparted to the part 5 is minimized by means of the part 4, so that the dynamic range of the part 5 is utilized with high efficiency.

Description: BACKGROUND OF THE INVENTION Field of the invention The present invention relates to methods and circuits for noise shaping, especially for noise shaping analog and digital circuits which widely distribute the quantize noise, due to the analog-to-digital conversion, outside the signal frequency band, so as to minimize the quantize noise in the signal frequency band and to obtain the high accuracy. Background Art Fig. 17 shows a signal flow of a conventional type second-order Δ-Σ noise shaping circuit. In the drawing, the circuit is adopted with a commonly-used noise shaping technique wherein the second order noise shaping characteristics are obtained by a Δ-Σ oversampling method. Such a technique is, for example, disclosed in the publication "Oversampling A-D conversion technique", NIKKEI Electronics Nos. 452-454, Nikkei BP Co. The second-order Δ-Σ noise shaping circuit shown in Fig. 17 consists mainly of an input terminal 11 for receiving an input signal X , an output terminal 12 for generating an output signal Y , subtractors 13 and 19, integrators 15 and 16 in which the transfer functions, utilizing the z-function, are referred to as 1/(1 - z -1 ), a quantizer 17 for executing the quantization so as to generate a quantize noise Q, and a one-sampling delay 18, respectively. In general cases, the one-sampling delay 18 will be composed as a D-to-A converter in the case of A-to-D conversion, while the delay 18 will be composed as a DFF (Delay Flip-Flop) in the case of D-to-A conversion. The following is a description of the signal flow of the second-order Δ-Σ noise shaping circuit shown in Fig. 17. First, the input signal X applied to the input terminal 11 is supplied to the subtractor 13. Furthermore, a delay signal D , namely the output signal Y delayed for one-sampling period via the one-sampling delay 18, is also supplied to the subtractor 13. The subtractor 13 subtracts the delay signal D from the input signal X and supplies the subtraction results to the integrator 15. The integrator 15 integrates the supplied signal and generates an output signal N , i.e. the integration results, to the subtractor 19. The subtractor 19 subtracts the delay signal D from the output signal N and supplies the subtraction results to the integrator 16. The integrator 16 integrates the supplied signal and generates an output signal M , i.e. the integration results, to the quantizer 17. The signal, quantized in the quantizer 17, is then generated from the output terminal 12 in the way of the output signal Y . Fig. 10 shows a more detailed circuit diagram of the conventional second order Δ-Σ noise shaping circuit shown in Fig. 17. Generally, as shown in Fig. 10, when the configuration in Fig. 17 is applied to an A-to-D converter, the integrators 15 and 16 will be realized by inverting amplifiers 115 and 116, and capacitors 51 and 52. The output signal Y of the quantizer 17 in Fig. 17 is supplied to the one-sampling delay 18 and delayed for a one-sampling delay period. The output signal Y , delayed for a one-sampling period, is then simultaneously supplied to the subtractors 13 and 19. However, in the case where the inverting amplifiers 115 and 116 are adopted as shown in Fig. 10, the plus/minus sign of the delayed output signal Y is inverted therein. In Fig. 17, the output signal Y is generated by the quantizer 17 and delayed for one-sampling period. In Fig. 10, this signal having the one-sampling delay is generated by D-to-A converters 118 and 118'. Furthermore, the output signal Y , having the one-sampling delay and the sign thereor being inverted, is added with the input signal by means of resistor R 2 , so that, essentially, a subtraction is executed. This signal is then integrated by the inverting amplifier 115 and the integrated results, referred to as the output signal N , is generated. Because the sign of the output signal N has been inverted, the signal addition executed by a resistor R 4 in the next stage, with the output signal Y having one-sampling delay, is essentially deemed to be a subtraction. The signal supplied to the inverting amplifier 116 is then integrated therein, so that an integration results, referred to as the output signal M , is generated. The signal M is then quantized by a comparator 117 and generated via the output terminal 12 as the output signal Y . The circuit shown in Fig. 17 can be expressed by the following formulae (1) to (3) wherein symbols N , M , Q and Y designates the output signal of the integrator 15, the output signal of the integrator 16, quantize noise in the quantizer 17, and the final output signal, respectively, so that the characteristics of this circuit can be analyzed by solving these formulae. N = 1 1 - z -1 (X -YZ -1 ) M = 1 1 - z -1 (N -YZ -1 ) Y = M + Q The following formula (4) is obtained by solving the above formulae (1) to (3) concerning the input signal X and output signal Y . Y = X + (1 - z -1 ) 2 Q In formula (4), the term "(1 - z -1 )" designates the differential, so that the output signal Y is equal to the additional results of the input signal X and second order differential of the quantize noise Q . The quantize noise Q is a noise having a Gaussian distribution regardless of the frequency, namely the white noise shown in Fig. 18. Fig. 18 shows the noise shaping effect concerning the quantize noise Q . In the drawing, the curve a shows the quantize noise Q , and the curve b shows the secondary differentiated results of the quantize noise Q . According to this drawing, in which the ordinate axis shows the power and the transverse axis shows the frequency, the secondary differentiated results "b=(1-z -1 ) 2 Q" are distributed such that components in the low frequency region are low and those in the high frequency region are high. Such a characteristic is so called the "noise shaping". As described above, according to the conventional noise shaping technique shown in Fig. 18, the quantize noise (white noise) having the Gaussian distribution is deformed. In addition, the high frequency region of the deformed noise is eliminated by means of a filter so as to minimize the noise components in the low frequency region, and to produce only those in the low frequency region. Therefore, even when a low resolution quantizer is utilized, highly accurate characteristics can be obtained. The following is a description of the MASH (Multi-stAge noise SHaping) method (IEEE Journal of Solid-State Circuit Vol. 22, No. 6, pp 921-929, December 1987) which has been proposed for the conventional Δ-Σ oversampling technique. Fig. 9 shows the signal flow of the conventional noise shaping digital circuit utilizing the MASH technique, and realizing the circuit having the second-order noise shaping characteristics, as in Fig. 10 by means of the MASH method. In the drawing, components corresponding to those of Fig. 17 are attached with the same symbols. The circuit shown in Fig. 9 comprises a subtractor 41, a differentiator 42 and an adder 43, which are not contained in the circuit in Fig. 17. The signal flow of the circuit will be described first. The input signal X imparted to the input terminal 11 is supplied to the subtractor 13. The first quantizer 17 generates an output signal Y1 . The signal Y1 is supplied to the one-sampling delay 18 wherein the signal is delayed for a one-sampling period. The delayed signal is then supplied to the subtractor 13. The subtractor 13 subtracts the output signal Y1 delayed for a one-sampling period, from the input signal X , and supplies the subtraction results to the first integrator 15. The first integrator 15 integrates the imparted signal thereto and supplies, to the subtractor 41, the integration results referred to as the output signal N . The subtractor 41 subtracts, from the input signal X , the output signal N generated by the first integrator 15. The subtractor 19 subtracts an output signal Y2 , generated by a second quantizer 17' and delayed for a one-sampling period, from the subtraction results P of the subtractor 41. The output signal of the subtractor 19 is then supplied to the second integrator 16 and integrated whereby the integrated results are produced in the way of the output signal M . The signal M is then supplied to a second quantizer 17' so as to quantize the signal M and to generate the quantized results, namely the output signal Y2 . The signal Y2 is then differentiated by the differentiator 42, and the differentiated results thereof is supplied to the adder 43. The output signal Y1 , quantized in the first quantizer 17, is added with the differentiated results in the differentiator 42, and the addition results are generated by the output terminal 12 in the way of the output signal Y . The circuit, utilizing the MASH technique, shown in Fig. 9 is aimed at improving stability. More specifically, in the case of the conventional Δ-Σ oversampling technique, the signal flow of the circuit in Fig. 17 is "subtractor 13 → first integrator 15 → subtractor 19 → second integrator 16 → quantizer 17 → one-sampling delay 18 → subtractor 13". In this signal flow, two integrators are maintained in a series and have a 180° phase delay, so that the circuit is naturally unstable. In contrast, the circuit shown in Fig. 9, concerning the MASH technique, contains two loops, the loop "subtractor 13 → integrator 15 → quantizer 17 → one-sampling delay 18 → subtractor 13", and the loop "subtractor 19 → integrator 16 → quantizer 17' → one-sampling delay 18' → subtractor 19". Each loop contains only one integrator so that the respective phase loop will be maintained at 90° and so that the circuit is absolutely stable. When the circuit in Fig. 9 is expressed by the z-function, the following formulae (5) to (8) concerning the output signal Y1 of the first quantizer 17, output signal Y2 of the first quantizer 17', the subtraction results P and the one-sampling delay 18 are obtained respectively. Y 1 = X + (1 - z -1 )Q 1 Y 2 = P + (1 - z -1 )Q 2 P = -Q 1 Y = Y 1 + (1 - z -1 )Y 2 Then, the following formula (9) is obtained by solving the above formulae (5) to (8). Y = Y 1 + (1 - z -1 )Y 2 = X + (1 - z -1 )Q 1 - (1 - z -1 )Q 1 + (1 - z -1 ) 2 Q 2 = X + (1 - z -1 ) 2 Q 2 Because formula (9) has the same configuration as formula (4), it is understood that the circuit shown in Fig. 9 has the second order noise shaping characteristics similar to that shown in Fig. 17. However, when the above formulae are solved relating to the output signals M and N concerning the integrators 15 and 16 respectively, the following formulae (10) and (11) are obtained. N = X - z -1 (1 - z -1 )Q M = X - z -1 Q - z -1 (1 - z -1 )Q The above formula (10) defines the output signal N of the integrator 15, and the other formula (11) defines the output signal M of the integrator 16. If the maximum absolute values of those signals do not exceed the dynamic ranges of integrators 15 and 16, stable noise shaping can be executed. However, if either value exceeds the corresponding dynamic range, the signal with the exceeded value is clipped at the maximum level or the minimum level of the respective integrators 15 and 16. If either signal is clipped, a drastic degradation of the S/N ratio will result accordingly. Because there is no correlative function existing between the input signal and quantize noise Q, the maximum absolute values of the output signal N of integrator 15 and that of output signal M of the integrator 16 are expressed by the following formulae (12) and (13) respectively, with the proviso "X>>(1 - z -1 )Q" in the low frequency region. N = ¦X¦ + ¦z -1 (1 - z -1 )Q¦ = ¦X¦ M = ¦X¦ + ¦z -1 Q¦ + ¦z -1 (1 - z -1 )Q¦ = ¦X¦ + ¦Q¦ According to the above formulae (12) and (13), it is clearly understood that the integrators 15 must have the ¦X¦ of the dynamic range and the integrator 16 must have the ¦X¦+¦Q¦ of the dynamic range in order to obtain the stable operation of the second-order Δ-Σ noise shaping circuit. According to the noise shaping technique, even if the quantizer 17 has low resolution, a highly accurate signal can be obtained. Therefore, in most cases, the quantize noise Q will be enlarged so that the wide dynamic range is required for the second-stage integrator. Especially, when the noise shaping circuit is utilized with low-voltage type A-to-D converter, a serious problem may be caused. That is, the integrator mainly consists of an operational amplifier and a capacitor, and the dynamic range of the operational amplifier is comparatively small. Furthermore, the substantial dynamic range will be further decreased equal to the difference between the original dynamic range and the absolute value of the quantize noise ¦Q¦. However, the quantity of noise quantity respectively imparted to the transistors and power sources is constant whether or not the dynamic range is decreased. As a result, there would be yet another problem that the S/N ratio is degraded with the decrease in dynamic range of the input signal. Meanwhile, in the case of the MASH technique, having a stable second order Δ-Σ noise shaping circuit, the output signal N of the integrator 15 can be obtained in the following formula (14). N = X - Q 1 = ¦X¦ + ¦Q 1 ¦ Similarly, the output signal M of the integrator 16 can be obtained in the following formula (15). M = -Q 1 - Q 2 = ¦Q 1 ¦ + ¦Q 2 ¦ According to the formulae (14) and (15), concerning the output signal N of the integrator 15 and the output signal M of the integrator 16, the maximum value of the output signal of the integrator 15 is N=¦X¦+¦Q 1 ¦. Consequently, the dynamic range of ¦X¦+¦Q 1 ¦ is required for the integrator 15 and, simultaneously, the dynamic range of the input signal is decreased so that the the S/N ratio is degraded. SUMMARY OF THE INVENTION It is accordingly, the first object of the present invention to provide a method and circuit for noise shaping for preventing the decrease in dynamic range and degradation of the S/N ratio. In the first aspect of the present invention, there is provided a noise shaping circuit (Fig. 2) having first subtraction means (13) for obtaining a difference between an input signal and a feedback signal; first integration means (15) for integrating the difference and for generating first integration results (N); second integration means (16) for integrating a value which varies in response to the first integration results and for generating second integration results (M); and feedback signal generation means (17, 18) for generating a feedback signal in response to the second integration results. The noise shaping circuit further comprises: second subtraction means (19) for supplying a difference between the input signal and the first integration results to the second integration means; and addition means (14) for supplying, addition results between the first integration results and the second integration results, to the feedback signal generation means. The present invention can be embodied as shown in Fig. 1 wherein the noise shaping circuit comprising: delay means 3 for delaying an output signal for one-sampling period; first subtraction means 1 for subtracting the signal, delayed by the delay means 3, from an input signal imparted to an input terminal so as to obtain first subtraction results; first integration means 2 for integrating the first subtraction results so as to obtain a first integrated value; second subtraction means 4 for subtracting the input signal from the first integrated value so as to obtain a second subtraction value; second integration means 5 for integrating the second subtraction value so as to obtain a second integrated value; adding means 7 for adding the first and second integrated values so as to obtain an addition results; and quantizer means 6 for quantizing the addition results. Furthermore, the above described circuit may be modified such that the first integration means comprises a first multiplier for multiplying the first integrated value with a first coefficient, and the second integration means comprises first integration means 2 and a second multiplier for multiplying the second integrated value with a second coefficient. Furthermore, the circuit may be modified such that each of the first and second integration means 2 and 5 comprise an inverting amplifier for inverting the sign of the input signal and for amplifying, and the quantizer means 6 is embodied by a differential comparator for executing the quantization in response to the output signals respectively generated by the first and second integration means. According to the present invention, the output signal, delayed for one-sampling period, is subtracted from the input signal, the subtraction results are then integrated, and the integrated value is subtracted by the input signal in the subtractor and further integrated. Then, the double integral value and the single integral value are added, and the addition results are quantized by the quantizer and generated. Therefore, the amplitude of the output signal of the integrator can be set comparatively narrower than the conventional circuit, so that the dynamic range of the signal component can be enlarged and the degradation of the S/N ratio can be prevented. As described above, the present invention remarkably differs from the prior art at the points where the input signal is subtracted from the output signal of the first integration means, and at the point where the addition results of the output signals of the first and second integration means are supplied to the quantizer means. Therefore, according to the present invention, the dynamic ranges of the integrators are utilized with high efficiency, the dynamic ranges of the input signal can be widened, and the S/N ratio can be improved. Furthermore, the output signal having one-sampling delay is merely supplied to the subtractor, so that the required number of D-to-A converters, conventionally "two", can be decreased to "one". Furthermore, when the differential comparator is adopted for the quantization, the circuit configuration can be simplified such that the adder and the quantizer are embodied by one circuit. The present invention can be further embodied as shown in Fig. 11 wherein the noise shaping circuit comprising: a first quantizer 1017 and a second quantizer 1020 for respectively quantizing signals imparted thereto; first addition means 1013 for generating a first addition signal wherein the first addition signal is a member of the group consisting of simplified first addition results between an output signal Y1 of the first quantizer 1017 and an inverted output signal of the second quantizer 1020, and complicated first addition results between the input signal and the simplified addition results divided by a specific value and delayed for one-sampling period by means of delay means 1018; first integration means 1051 for integrating the first addition signal, for inverting an integrated results therein, and for generating an inverted results as an inverted signal N ; second integration means 1052 for integrating an addition results between the output signal N of the first integration means 1051 and the input signal, for inverting an integrated signal, and for generating an inverted results as an inverted signal M ; and second addition means 1014 for imparting, to the second quantizer 1020, the signal M generated by the second integration means 1052, and for generating a second addition signal wherein the second addition signal is a member of the group consisting of simplified second addition results between the output signal Y1 of the first quantizer 1017 and an inverted output signal Y2 of the second quantizer 1020, and results of the simplified second addition results divided by the specific value. The present invention can be further embodied as shown in Fig. 15 wherein the noise shaping circuit comprising: a first quantizer 1017 and a second quantizer 1020 for respectively quantizing signals imparted thereto; first addition means 1021 for generating a first addition signal wherein the first addition signal is a member of the group consisting of simplified first addition results and complicated first addition results, wherein the simplified addition results are obtained by adding the output signal Y1 generated by the first quantizer 1017 and delayed for one-sampling period by means of a first delay means 1018 and an inverted output signal Y2 generated by the second quantizer 1020, inverted and delayed for one-sampling period by a second delay means 1018', and the complicated addition results are obtained by dividing the simplified first addition results by a specific value; second addition means 1013 for adding the first addition signal and the input signal and for generating an addition results; first integration means 1051 for integrating the addition results generated by the second addition means 1013 and for generating an inverted integrated results as an inverted signal N ; second integration means 1052 for integrating an addition results between the inverted signal N generated by the first integration means 1051 and the input signal, and for supplying, to the second quantizer 1020, an inverted integrated results as an inverted signal M ; and third addition means 1014 for imparting, to the first quantizer 1017, the output signal N of the first integration means 1051, and for generating a third addition signal wherein the third addition signal is a member of the group consisting of simplified third addition results between the inverted output signal Y2 of the second quantizer 1020 and the output signal Y1 generated by the first quantizer 1017, and a divided results of the simplified third addition results by the specific value. Conventionally, the subtraction is executed at the pre-stage of the quantizer. In contrast, according to the present invention, the quantization is executed earlier and subtraction is executed later. Because the quantized signal is a digital value, an addition can easily be substituted for subtraction by making "two's" a complement of the value. As described above, the present invention, relating an analog circuit having a quantizer and an inverter, adds the noise of first quantizer and that of second quantizer. Accordingly, the circuit has the complete second-order noise shaping characteristics. Other objectives and advantages of the present invention will be become apparent from the detailed description to follow taken in conjunction with the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Fig. 1 is a block diagram showing an example of the concept of the present invention; Fig. 2 is a block diagram showing a signal flow of the noise shaping circuit according to the first embodiment of the present invention; Fig. 3 is a block diagram showing a signal flow of the noise shaping circuit according to the second embodiment of the present invention; Fig. 4 is a circuit diagram of the noise shaping circuit according to the second embodiment of the present invention; Fig. 5 is a block diagram showing a signal flow of the noise shaping circuit according to the third embodiment of the present invention; Fig. 6 is a circuit diagram of the noise shaping circuit according to the third embodiment of the present invention; Fig. 7 is a block diagram showing a signal flow of the noise shaping circuit according to the fourth embodiment of the present invention; Fig. 8 is a circuit diagram of the noise shaping circuit according to the fourth embodiment of the present invention; Fig. 9 is a block diagram showing the signal flow of the conventional noise shaping circuit utilizing the MASH technique; Fig. 10 is a circuit diagram of the conventional second order Δ-Σ noise shaping circuit; Fig. 11 is a block diagram showing the principle configuration of the fifth embodiment of the present invention; Fig. 12 is a circuit diagram of the noise shaping circuit according to the fifth embodiment of the present invention; Fig. 13 is a circuit diagram of the noise shaping circuit according to a modification of the fifth embodiment of the present invention; Fig. 14 is a circuit diagram of the noise shaping circuit according to another modification of the fifth embodiment of the present invention; Fig. 15 is a block diagram showing the principle configuration of the sixth embodiment of the present invention; Fig. 16 is a circuit diagram of the noise shaping circuit according to the sixth embodiment of the present invention; Fig. 17 is a block diagram showing the conventional noise shaping digital circuit; and Fig. 18 is a chart of frequency characteristic showing the noise shaping effect concerning the quantize noise Q. DESCRIPTION OF THE PREFERRED EMBODIMENTS First embodiment Fig. 2 shows the signal flow of a noise shaping circuit concerning the first embodiment of the present invention. In the drawing, components corresponding to those of Fig. 9 are attached with the same symbols. In Fig. 2, the input signal X is imparted to the subtractor 13 via the input terminal 11. Meanwhile, the output signal Y is supplied to the one-sampling delay 18, whereby the output signal Y having the one-sampling delay is supplied to the subtractor 13. The subtractor 13 subtracts the output signal Y having the one-sampling delay from the input signal X and supplies the subtraction results to the integrator 15. The integrator 15 integrates the subtraction results supplied therein. The integrator 15 then supplies the output signal N to the subtractor 19. The subtractor 19 subtracts the input signal X from the output signal N of the integrator 15, and supplies the subtraction results to the integrator 16. The integrator 16 integrates the subtraction results supplied therein and supplies the integration results to the an adder 14. The adder 14 adds the output signal N of the integrator 15 and the output signal M of the integrator 16, and generates the addition result P to the quantizer 17. The quantizer 17 quantizes the addition result P so as to generates the output signal Y . The aim of the configuration shown in Fig. 2 is to obtain the output signal Y by means of subtracting the input signal X from the output signal N of the integrator 15, of adding the output signal N of the integrator 15 and the output signal M of the integrator 16, and of supplying the addition results to the quantizer 17. The configuration shown in Fig. 2, i.e. the output signal N of the integrator 15, the output signal M of the integrator 16, the addition results P of the adder 14 and the output signal Y of first quantizer 17, can be expressed by the following formulae (16) to (19) in the z-function. N = 1 1 - z -1 (X - YZ -1 ) M = 1 1 - z -1 (N - X) P = N + M Y = P + Q When the above formulae (16) to (19) are solved for the output signal Y , the following formula (20) concerning the output signal Y is obtained. Y = X + (1 - z -1 ) 2 Q The formula (20), having a similar configuration to the formulae (4) and (13), expresses the second order noise shaping characteristics. Furthermore, when the above formulae are solved for the output signals N and M of the integrators 15 and 16, the following formulae (21) and (22) are obtained. N = X - z -1 (1 - z -1 )Q ≒ ¦X¦ M = -z -1 Q ≒ ¦Q¦ Accordingly, the output signals N and M can be considered as the approximate value of the input signal X and the output signal Q of the quantizer respectively. Furthermore, because there is a correspondence "X>>(1 - z -1 )Q" in the signal frequency band, the maximum value of the output signal N of the integrator 15 becomes ¦X¦, and the maximum value of the output signal M of the integrator 16 becomes ¦Q¦. According to the conventional configuration shown in Figs. 9 and 12, the maximum values of the output signals of the integrators become ¦X¦+¦Q¦. In contrast, according to the first embodiment of the present invention, the maximum value of the output signal N of the integrator 15 is reduced by ¦Q¦, and that of the output signal M of the integrator 16 is reduced by ¦X¦. Second embodiment Fig. 3 shows a signal flow of the noise shaping circuit according to the second embodiment of the the present invention. In the drawing, components corresponding to those of Fig. 2 are attached with the same symbols. The shaping circuit according to the second embodiment of the present invention comprises inverters 70 1 , 70 2 and 70 3 in order to invert the signs of signals. The inverters 70 1 and 70 2 are respectively provided in the next stages of the integrators 71 and 72, and the inverter 70 3 is provided in the prior stage of the one-sampling delay 18. The adder 14 and the first quantizer 17 composes a quantizer 73. The signal flow of the second embodiment is similar to that of the first embodiment. Fig. 4 shows the circuit diagram of the noise shaping circuit of a practical example of the composition shown in Fig. 3, according to the second embodiment of the present invention. In the drawing, the subtractors 13 and 19 are exchanged by adders realized by resistors R 1 and R 2 respectively. The integrator 71 is realized by a circuit comprised of an inverting amplifier 215 and a capacitor 61, which inverts the sign of the input signal thereto and amplifies the inverted signal. Similarly, the integrator 72 is realized by an inverting amplifier 216 and a capacitor 62. The quantizer 73 is realized by a differential comparator 200, having both functions of the adder 14 and first quantizer 17, which executes the quantization in response to the output signal of the inverting amplifier 215 and that of the amplifier 216. Furthermore, the delay part 74 comprised of the one-sampling delay 18 and the inverter 70 3 , is realized by a D-to-A converter 274 which includes an inverter. As described above, when the noise shaping circuit according to the second embodiment is adopted for the A-to-D converter, the circuit can be realized by commonplace analog devices. Third embodiment Fig. 5 shows a signal flow of the noise shaping circuit according to the third embodiment of the the present invention. According to the third embodiment, a multiplier 81 for multiplying a coefficient J by the signal imparted thereto, and a multiplier 82 for multiplying a coefficient K by the signal imparted thereto, are provided at the next stage of the integrators 15 and 16, respectively. If the coefficients J and K are less than "1", the multipliers 81 and 82 can be embodied by dividing resistors. Fig. 6 shows a practical example of the noise shaping circuit according to the third embodiment of the present invention. In the drawing, components corresponding to those of Fig. 4 are attached with the same symbols. The circuit shows the example wherein the coefficient K is "0.5", and coefficient J is "1". The resistors R 2 and R 3 shown in Fig. 4 are doubled in Fig. 6 in order to set the coefficient K at "0.5". Fourth embodiment Fig. 7 shows a signal flow of the noise shaping circuit according to the fourth embodiment of the the present invention. According to the fourth embodiment, a first-order Δ-Σ circuit and MASH technique are added to the configuration according to the first embodiment, so as to obtain the third order noise shaping characteristics. More specifically, the circuit according to the first embodiment is adopted for the first stage of the noise shaping circuit concerning the MASH technique shown in Fig. 12. If the conventional second order Δ-Σ noise shaping circuit shown in Fig. 9 is adopted for the first stage of the circuit shown in Fig. 12 so as to obtain the third-order noise shaping characteristics, the output signal M of the integration circuit in Fig. 9 should be supplied to the second stage. However, according to the above formula (6), the output signal M of the integration circuit should be the sum of the input signal X and the quantize noise Q . Therefore, the input voltage thereto should be enlarged. In contrast, according to the fourth embodiment, concerning the above formula (22), the input signal to the second stage is only the quantize noise Q . Therefore, the fourth embodiment is advantageous where a required dynamic range can be made comparatively narrower than that of the above described combination. Furthermore, the circuit according to the present invention can also be adopted for the second stage so as to obtain the fourth-order noise shaping characteristics. Fig. 8 shows a circuit diagram, which is a practical example of the composition shown in Fig. 7, of the noise shaping circuit according to the fourth embodiment of the present invention. The circuit configuration of this embodiment is similar to that shown in Fig. 4, further comprising the first-order Δ-Σ circuit. The circuit utilizing the Δ-Σ oversampling technique receives the output signal of the integrator 216. The signal generated by a comparator 218 is delayed for one-sampling period by means of D-to-A converter 175, and subtraction is executed by resistors R 5 and R 6 . The signal created by an integrator 217 and a capacitor 63 is supplied to the comparator 218. Furthermore, the output signal of the comparator 218 is twice differentiated by the differentiators 95 and 95', and the differential of second order is supplied to an adder 96. The adder 96 generates the addition results, as the output signal Y , of the output signal of the comparator 200 and that of the differentiator 95'. Fifth embodiment Fig. 11 shows a principal configuration of the fifth embodiment of the present invention. In the drawing, components corresponding to those of Fig. 2 are attached with the same numeral added to "1000". However, the subtractors 13 and 19 shown in Fig. 2 are exchanged by adders 1013 and 1019 shown in Fig. 11. The configuration of this embodiment is similar to that shown in Fig. 2, further comprising a second quantizer 1020. Furthermore, according to the embodiment, the delay relating to the adder 14 is contained in loop circuits. In the drawing, the numeral 1050 designates a sign inverter which inverts the sign of signal supplied thereto. The adder 1014 adds the output signal Y1 of the first quantizer 1017 with the output signal Y2 , inverted by the sign inverter 1050, of the second quantizer 1020, and supplies the addition results to the one-sampling delay 1018. The adder 1013 adds the output signal, delayed for one-sampling period, of the one-sampling delay 1018 with the input signal X , and supplies the addition results to the first integrator 1051. The first integrator 1051 consists mainly of a sign inverter 1050 and an integrator 1015 which integrates the input signal thereto and supplies the integrated results to the sign inverter 1050. The sign inverter 1050 inverts the sign of the signal supplied thereto and supplies the inverted signal to the adder 1019 in the way of the output signal N . The adder 1019 adds the input signal X with the signal N generated by the first integrator 1051, and supplies the addition results to the second integrator 1052. The second integrator 1052 consists mainly of an integrator 1016 and a sign inverter 1050'. The integrator 1016 integrates the signal supplied by the adder 1019, and supplies the integrated results to the sign inverter 1050'. The sign inverter 1050' inverts the sign of the signal input thereto and supplies the inverted results to the second quantizer 1020 as the output signal M . Meanwhile, the output signal N of the first integrator 1051 is supplied to the first quantizer 1017. Therefore, the adder 1014 receives the output signal Y1 of the first quantizer 1017 and the output signal Y2 inverted via the inverter 1050, and generates the addition results of the two signals in the way of the output signal Y . Fig. 12 shows a first practical example of the fifth embodiment according to the present invention. The first integrator 1051 mainly consists of the integrator 1015 and the sign inverter 1050 in Fig. 11 is embodied by an RC integrator 10151. Similarly, the second integrator 1052 consists mainly of the integrator 1016 and the sign inverter 1050' and is embodied by an RC integrator 1152. The first and second quantizers 1017 and 1020 are embodied by comparators 1074 and 1074' respectively, to which a standard voltage 1070 is respectively applied. The one-sampling delay 1018 is embodied by a digital to analog converter 1071 which converts digital signals to analog signals. The sign inverter 1050 and the adder 1014 shown in Fig. 11, are embodied by a digital inverter 1072 and a digital adder 1073, respectively. Furthermore, analog addition can be embodied only by connecting the input resistances in parallel. Because the output signal of the quantizer 1017 is a digital value, the digital-to-analog converter 1071 is utilized for feeding back the signal to the input terminal of the integrator, for converting the signal to the analog value, and, simultaneously, for delaying the signal for a one-sampling period. Fig. 13 shows a second practical example of the fifth embodiment according to the present invention. In the drawing, the output signal of the first quantizer (comparator 1074) and that of the second quantizer (comparator 1074 and inverter 1072) are respectively multiplied by a specific value, "1/2" in this example, in a coefficient multiplier 91. Needless to say, the specific value does not need to be limited to "1/2". According to the circuit shown in Fig. 13, if the specific value is less than "1", the amplitude of the output signal of the digital-to-analog converter 1071 can be made small. Fig. 14 shows a third practical example of the fifth embodiment according to the present invention. In the drawing, a multi-stage noise shaping technique is adopted for the circuit shown in Fig. 12 so as to obtain the third order noise shaping characteristics. According to the circuit, only an additional digital differentiator 1101 and associated components are required, but no special analog component is required. Sixth embodiment Fig. 15 shows a principal configuration of the sixth embodiment of the present invention. In the drawing, components corresponding to those of Fig. 11 are attached with the same symbols. The composition shown in Fig. 15 is similar to that shown in Fig. 11, and also provides a one-sampling delay 1018 in addition to the delay 1018. The composition further providing an adder 1021 for adding the output signal of the first sampling delay 1018 with that of the second sampling delay 1018', and for supplying the addition results to the adder 1013. The adder 1014 similar to the first embodiment, adds the output signal Y1 of the first quantizer 1017 and the output signal Y2 of the second quantizer 1020. However, the sixth embodiment is advantageous because the adder 1014 is not contained in any loop circuit. The details of the sixth embodiment will be described next. The input signal X imparted to the input terminal 1011 is supplied to the first integrator 1051 and the adder 1019. The first integrator 1051 integrates and inverts the input signal X , and supplies the inverted signal N to the adder 1019. The adder 1019 adds the input signal with the output signal of the first integrator 1051, and supplies the addition results to the second integrator 1052. The second integrator 1052 integrates and inverts the output signal of the adder 1019, and supplies the inverted signal M to the second quantizer 1020. The second quantizer 1020 quantizes the supplied signal thereto and supplies the quantized signal to the sign inverter 1050. The sign inverter 1050 inverts the sign of the quantized signal and supplies the inverted signal Y 2 to the adder 1014 and the second sampling delay 1018'. The adder 1021 adds the output signals respectively supplied by the first and second one-sampling delay 1018 and 1018', and supplies the addition results to the adder 1013. Furthermore, the output signal Y1 of the first quantizer 1017 and output signal Y2 of the second quantizer 1020 are respectively supplied to the adder 1014. The adder 1014 adds the two signals supplied thereto and generate the addition results as the output signal Y . The above described circuit can be expressed by the following formulae (23) to (26), with the proviso that Q 1 and Q 2 respectively designate the quantize noise of first and second quantizers 1017 and 1020, Y 1 designates the output signal of the first quantizer 1017, and Y 2 designates the inverted output signal of the second quantizer 1020. N = -1 1 - z -1 (X +(Y 1 Z -1 + Y 2 Z -1 )) M = -1 1 - z -1 (N - X) Y 1 = N + Q 1 , Y 2 = -(N + Q 2 ) Y = Y 1 + Y 2 When the above formulae (23) to (26) are solved for Y , the following formula (27) will be obtained. Y = X + (1 - z -1 ) 2 (Q 1 + Q 2 ) Accordingly, though the quantize noise becomes Q 1 +Q 2 , the formula (27) has a similar configuration to formulae (9) and (20). Hence, it is understood that the circuit shown in Fig. 15 has the complete secondary noise shaping characteristics. Fig. 16 shows the practical example of the noise shaping circuit according to the sixth embodiment of the present invention. In the drawing, one-sampling delays 1018 and 1018' are embodied by digital to analog converters 1071 and 1071', respectively which are connected in parallel. As described above, according to the circuit, the digital adder 1073 is not contained in any loop. Therefore, signal delay, due to the adder 1073, will not affect the loops. As a result, the phase margin will be enlarged and the stability will be improved. As described above, the sixth embodiment is advantageous, when compared with the other embodiments shown in Figs. 2 and 20, at realizing an A-to-D converter by means of an analog circuit having the second quantizer 1020 and the inverter 1050. Furthermore, according to the sixth embodiment, the characteristics and performances as similar to those of the first to fourth embodiment can be obtained. Therefore, it is possible to widen the dynamic range of the input signal and to improve the S/N ratio. Furthermore, this embodiment, having only the adder 1014 as an analog component, is advantageous for realizing in LSI circuits. Incidentally, the output signals of the quantizers, being in the form of digital signal, can be inverted by the digital inverter with ease.

Claims: A noise shaping method comprising the steps of : obtaining a first difference between an input signal and a delayed output signal ; integrating the first difference to obtain a first integration result ; obtaining a second difference between the first integration result and the input signal ; integrating the second difference to obtain a second integration result ; multiplying the first integration result by a first coefficient ; multiplying the second integration result by a second coefficient ; obtaining addition results by adding the first integration result multiplied by the first coefficient, and the second integration result multiplied by the second coefficient ; and quantizing the addition results to obtain the output signal. A noise shaping circuit comprising : an input terminal receiving an input signal ; an output terminal for delivering an output signal ; at least one delay means (3) for delaying said output signal for one sampling period to obtain a delayed signal ; first subtraction means (1) for subtracting the delayed signal from the input signal so as to obtain first subtraction results ; first integration means (2) for integrating the first subtraction results so as to obtain first integration results ; second subtraction means (4) for subtracting the input signal from the first integration results so as to obtain second subtraction results ; second integration means (5) for integrating the second subtraction results so as to obtain second integration results ; adding means (7) for adding the first and second integration results so as to obtain addition results ; at least one quantizer means (6) for quantizing the addition results to obtain the output signal ; and feedback means for feeding back the output signal to the first subtraction means (1) through the delay means (3) . A noise shaping circuit according to claim 2 further comprising : first multiplier (81) for multiplying the first integration results by a first coefficient (J) ; and second multiplier means (82) for multiplying the second integration results by a second coefficient (K). A noise shaping circuit according to claim 2, wherein said first integrating means (15) and second integrating means (16) are followed by inverters (70 1 , 70 2 ) and wherein said delay means (18) is preceded by an inverter (70 3 ). A noise shaping circuit according to claim 2, wherein said first subtraction means and said second subtraction means are constituted by respectively first (1013) and second adders (1019). A noise shaping circuit according to claim 2, wherein each of said first integration means and second integration means comprises an inverting amplifier (215, 216) and a capacitor (61, 62). A noise shaping circuit according to claim 2, wherein said quantizer means comprise a differential comparator (200). A noise shaping circuit according to claim 2, further comprising : third subtraction means (91) for subtracting the output of said second integration means (16) and a delayed signal from second delay means (94) so as to obtain third subtraction results, third integration means (92) for integrating said third subtraction results, second quantizer means (93) for quantizing the signal provided by said third integration means (2), said second delay means (94) for delaying an output signal of said second quantizer means (93) for one sampling period, at least one differentiator (95, 95 1 ) connected to said second quantizer means (93), an adder (96) connected to said differentiators (95, 95 1 ) and to said first quantizer and generating addition results to the terminal (12).

Inventors: MATSUYA YASUYUKI, MATSUYA, YASUYUKI
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1992
Main classification: H03M3
IPC codes: H04B14, H03M3