Driver circuit with FET and bipolar transistors

Abstract: A driver circuit provides a high output current at a fast slew rate to a low impedance load. The driver circuit (20) has an output circuit including a first bipolar transistor (23) having a collector emitter path between a voltage supply line (22) and a node (15) for connection to a load. The output circuit also includes a first FET (27) having its source-drain path connected between the voltage supply line (24) and the base of the first bipolar transistor (23), and its gate connected to an input node (28). An additional circuit supplies drive current to the base of the first bipolar transistor (23) only to assist the first bipolar transistor turn-on, so that the additional circuit does not add extra voltage drop across the first bipolar transistor (23) during turned on operation. In one embodiment, the first and second bipolar transistors (23-30) are NPN transistors, and the first and second FETs (27,32) are p-channel FET devices.

Description: This invention relates to improvements in electronic circuits, and more particularly to improvements in electronic driver circuits of the type for driving low impedance loads with high currents at fast slew rates. In the past, circuits for providing driving voltages, for example to low impedance loads have been proposed. One such low impedance load application, for instance, is a multi-phase dc motor in which drive voltages are switchably applied in accordance with a commutation sequence of the stator coils of the motor. It is important in such applications to provide a driving voltage which increases to the required operating voltage as rapidly as possible in response to the input turn-on signal. (The rate at which the output voltage of the driver changes for a step-signal input is referred to herein as the "slew rate" of the driver.) The problem is exacerbated when, in addition to the normal drive voltage switching requirements, power saving techniques such as PWM techniques are employed in which the drive circuits are rapidly switched on and off during peak operating conditions in addition to their normal commutation switching. This has also been a particular problem in other applications, for example, in which the voltage across a capacitive load is required to swing in a very short time. In such applications, fast output rise and fall times are required in order to enable the proper high speed operation envisioned. However, driver circuits used in the past have not been totally successful in providing such fast slew rate requirements. For example, a typical prior art driver circuit 10 is shown in Figure 1, which includes a high gain NPN output transistor 11 and a single p-channel FET 12 pre-driver. The NPN transistor 11 has its collector connected to a supply voltage on line 15, and its emitter connected to an output node 16, which is connected in operation to the desired load. The pre-driver p-channel FET 12 has its source connected to the supply voltage on line 15, and its drain connected to the base of the NPN transistor 11. The input to the circuit 10 is applied to the gate of the p-channel FET 12 from input node 17. Usually the input signal has a step function waveform having a very rapid commutation, or falling edge time. Ideally, the waveform of the output signal delivered to the load also has a rapid rise time, tracking the input waveform; however, the capacitive elements in the circuit, notably the capacitance of the base electrode of the NPN transistor 11, need to be charged before the NPN transistor 11 can be turned on. The single p-channel FET 12, on the other hand, can only supply a fixed amount of drive current to charge the base of the transistor 11, thereby defining the rate at which the transistor 11 can be turned on, or switched into conduction. Patent Abstracts of Japan Vol. 10, No. 75 (E-390) (2132) 25th March 1986 and JP-A-60-220 621 disclose a driver circuit arrangement similar to that of Figure 1. One solution to address this problem has been to cascade additional bipolar transistors in Darlington-like configurations to achieve a higher current gain to thereby provide higher drive current to the output transistor. The problem with such solutions is that the voltage drop across the driver transistor is increased for each additional stage which is added. In light of the above, it is therefore an object of the invention to provide a driver circuit which has a very fast slew rate. It is another object of the invention to provide a driver circuit of the type described which does not produce multiple voltage drops across the output driver transistor in order to provide sufficient drive current for rapid operation. It is another object of the invention to provide a driver circuit of the type described that is suitable to provide rapidly switched driver voltages to low impedance loads, such as inductive loads, capacitive loads, or the like. It is another object of the invention to provide a driver circuit of the type described which can be realized in BiCMOS technology. It is another object of the invention to provide a driver circuit of the type described which can easily be integrated onto a single isolated tub or well of an integrated circuit chip using BiCMOS technologies. European Patent Application Publication No. 0416933 shows a driver circuit for a large capacity switching element which is capable of providing an additional current during start-up. A monostable multivibrator is controlled to initially deliver current to the switching element. After a fixed period of time the monostable multivibrator will cease to operate and the switching element 1 will only have a small current delivered to it. US Patent No. 4,590,395 shows a driver circuit for fast switching. A capacitor charges rapidly into the base of a transistor to turn it on. Once the capacitor has discharged, a constant current is provided to the transistor. European Patent Application Publication No. 0212004 discloses an inverting circuit having a bipolar transistor for rapidly processing input/output signals. It also shows an inverter with a PMOS transistor and a bipolar transistor connected in parallel for supplying an output current. European Patent Application No. 0099100 discloses a high-speed operation, low-power consumption gate circuit structure, in which a resistor is connected between base and emitter electrodes of a driver bipolar transistor. Patent Abstracts of Japan, vol. 13, no. 235, (E-776) [2132], 30th May 1989 and JP-A-64-39817 disclose a four terminal complementary output circuit for reducing the skew between complementary outputs in a low power environment according to the preamble of claim 1. Two bipolar transistors are shown connected in a Darlington configuration. When the output circuit is enabled, one of the bipolar transistors assists to turn on the other transistor, and after the initial turn on period thereafter is switched off. When the output circuit is disabled, the potentials at the base and emitters of such bipolar transistor are discharged to ground. According to the present invention there is provided a driver circuit having a high output current and fast slew rate, comprising: a bipolar output transistor having an output for connection to a load, and a control electrode responsive to a drive current to turn the bipolar output transistor on and off; a drive current FET connected to the control electrode of said bipolar output transistor, and having a control electrode connected to an input node of the driver circuit, said drive current FET being connected to supply the drive current to said bipolar output transistor; a turn-on drive current bipolar transistor having an emitter electrode connected to the control electrode of said bipolar output transistor and having a current path connected in parallel with said drive current FET for supplying additional drive current to the control electrode of said bipolar output transistor only to assist said bipolar output transistor turn-on; and an input FET having a current path connected to a control electrode of said turn-on drive current bipolar transistor, said input FET having a control electrode connected to said input node, characterised in that said driver circuit is a three-terminal driver circuit having a bias resistor directly connected between base and emitter electrodes of the turn-on drive current bipolar transistor to turn off said turn-on driver current bipolar transistor when said bipolar output transistor is turned on. The bipolar output transistor and the turn-on drive current transistor are bipolar NPN transistors, and the main drive current transistor and the input transistor are p-channel FET devices. The transistors, therefore, can be fabricated in a single isolation well of an integrated circuit chip. The invention is illustrated in the accompanying drawings, in which: Figure 1 is an electrical schematic diagram of a power driver circuit, in accordance with the prior art. And Figure 2 is an electrical schematic diagram of a power driver circuit, in accordance with a preferred embodiment of the invention. A driver circuit 20, in accordance with a preferred embodiment of the invention is shown schematically in Figure 2. The circuit includes a high current output driver NPN transistor 23, having its collector connected to a line 24 to which a supply voltage, V cc , is connected, and having its emitter connected to an output node 25 to which a load can be connected. The load (not shown) can be, for example, a low impedance load, and may include resistive, inductive, or capacitive elements, or some combination thereof. A p-channel FET 27 has its source connected to the supply voltage line 24 and its drain connected to the base of the NPN transistor 23. The gate of the p-channel FET 27 is connected to a driver circuit input node 28. The p-channel FET 27 serves as a main drive current transistor, providing a circuit to control the drive current signals to the output driver NPN transistor 23 both during and after its turn-on. The circuit described so far is similar to the circuit described above with regard to the prior art circuit of Figure 1. In accordance with the invention, a second NPN transistor 30, serving as a turn-on drive current transistor, is connected in a Darlington configuration in conjunction with the first NPN transistor 23, having its collector connected to the voltage supply line 24, and its emitter connected to the base of the first NPN transistor 23. A second p-channel FET 32 is provided to serve as an input transistor. The second p-channel FET 32 is of standard configuration, and operates to boost the turn-on current to the second NPN transistor 30. The second FET 32 has its source connected to the voltage supply line 24, its drain connected to the base of the second NPN transistor 30, and its gate connected to the input node 28. A high value bias resistor 33 is connected between the base and emitter of the second NPN transistor 30. The second NPN transistor 30 and the second p-channel FET 32 serve as a turn-on circuit to provide additional current drive to the output NPN transistor 23 only during its turn-on. In operation, the circuit including the second NPN transistor 30 and the second FET 32 supplies a large turn-on current to rapidly turn-on the first NPN output driver transistor 23 in response to a rapidly decreasing input waveform, such as a step function, square wave, or the like. The second NPN transistor 30 provides a high current which charges the capacitance of the base of the output driver transistor 23, enabling its turn-on significantly faster than the prior art circuit above described. Moreover, once the output driver transistor 23 is turned on, the bias voltage between the base and the emitter of the second NPN transistor 30 is reduced, turning off the second NPN transistor 30. The second NPN transistor 30, therefore, does not contribute any voltage drop to the output of the circuit 20, the only voltage drop being the V DE drop produced by the output driver NPN transistor 23 plus the voltage drop on the drain and source of the FET 27. Although the second FET 32 is not turned off, its effect on the circuit 20 is minimal due to the very high value of the resistor 33 in the source drain path of the second FET 32. When the drive voltage produced by the circuit 20 is to be turned off, the second NPN transistor 30 has already been turned off. Thus, any capacitive discharge effects due to the existence of the second NPN transistor 30 in the circuit which may otherwise exist do not adversely affect the turn off time of the circuit. It will also be appreciated that since the circuit embodiment illustrated employs only p-channel FET devices and NPN transistors, the circuit embodiment can easily be constructed in a single isolated integrated circuit well or tub, using standard BiCMOS technologies. It will also be appreciated by those skilled in the art that although the embodiment described uses NPN transistors and p-channel FET devices, n-channel devices, or bipolar transistors of different conductivity types can be equally advantageously employed to realize the effects of the invention. Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the scope of the invention, as hereinafter claimed.

Claims: A driver circuit having a high output current and fast slew rate, comprising: a bipolar output transistor (23) having an output (25) for connection to a load, and a control electrode responsive to a drive current to turn the bipolar output transistor on and off; a drive current FET (27) connected to the control electrode of said bipolar output transistor, and having a control electrode connected to an input node (28) of the driver circuit, said drive current FET being connected to supply the drive current to said bipolar output transistor; a turn-on drive current bipolar transistor (30) having an emitter electrode connected to the control electrode of said bipolar output transistor and having a current path connected in parallel with said drive current FET for supplying additional drive current to the control electrode of said bipolar output transistor only to assist said bipolar output transistor turn-on; and an input FET (32) having a current path connected to a control electrode of said turn-on drive current bipolar transistor, said input FET having a control electrode connected to said input node, characterised in that said driver circuit is a three-terminal driver circuit having a bias resistor (33) directly connected between base and emitter electrodes of the turn-on drive current bipolar transistor to turn off said turn-on drive current bipolar transistor when said bipolar output transistor is turned on. The driver circuit of claim 1 wherein said bipolar output transistor (23) has an emitter as its output (25), a base as its control electrode, and a collector connected to a supply voltage (Vcc). The driver circuit of claim 2 wherein said drive current FET (27) has a drain connected to the control electrode of said bipolar output transistor, a gate as its control electrode, and a source connected to the supply voltage (Vcc). The driver circuit of claim 1, 2 or 3 wherein said turn-on drive current bipolar transistor (30) has a base as its control electrode. The driver circuit of any one of the preceding claims wherein said input FET (32) has a gate as its control electrode. The driver circuit of any preceding claim wherein said bipolar output transistor (23) is a NPN transistor. The driver circuit of any one of the preceding claims wherein said turn-on drive current bipolar transistor (30) and said bipolar output transistor (23) are bipolar NPN transistors. The driver circuit of any one of the preceding claims wherein said drive current FET (27) and said input FET (32) are p-channel devices. The driver circuit of any one of the preceding claims wherein said bipolar output transistor (23), said drive current FET (27), said turn-on drive current bipolar transistor (30) and said input FET (32) are all contained in a single isolated region of a single semiconductor chip. The driver circuit of any one of the preceding claims when coupled to a load comprising inductive and/or capacitive elements.

Inventors: CAROBOLANTE FRANCESCO, CAROBOLANTE, FRANCESCO
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1992
Main classification: H03K17
IPC codes: H03K17