An H-shaped bridge circuit with protection against crossover conduction during the reversal of the current in the load

Abstract: The circuit includes two output terminals (OUT1, OUT2) for connection to the terminals of a load (L), first and second pairs of electronic power switches (Q1, Q4; Q2, Q3) which are connected between the output terminals (OUT1, OUT2) and the two poles of a direct-current voltage supply (Vs) so as to form an H-shaped structure with the load (L), and a driver circuit (C1, C2) for selectively making the electronic power switches of the first pair (Q1, Q4) of the second pair (Q2, Q3) order to cause a current to flow through the load (L) in one direction or the other respectively, and for preventing the electronic switches (Q1, Q3; Q2, Q4) which are connected between the same output terminal (OUT1; OUT2) and the two poles of the voltage supply (Vs) from conducting simultaneously.

Description: The present invention relates to an H-shaped bridge circuit of the type defined in the preamble of Claim 1. A prior-art H-shaped bridge circuit is shown in Figure 1 of the appended drawings. The circuit shown has an input terminal In and two output terminals Outl and Out2 between which a load L is connected. Four bipolar transistors Q1, Q2, Q3 and Q4, of which the first two are of the pnp type and the second two are of the npn type, are connected between the output terminals Out1 and Out2 and the two poles of a direct-current voltage supply Vs in the manner shown. In the embodiment illustrated, the negative pole of the supply is connected to earth. The bases of the transistors Q1 and Q4 are connected to two outputs of a first control circuit C1, the input of which is connected to the input terminal In. The bases of the transistors Q2 and Q3 are connected to corresponding outputs of a second control circuit C2 which is structurally identical to C1 and the input of which is connected to the terminal In by means of an inverter INV. In operation, when a level-"1" signal is applied to the input In, the control circuit C1 makes the power transistors Q1 and Q4 conductive and the control circuit C2 keeps the power transistors Q2 and Q3 cut off. In this situation, a current I L flows through the load L in the direction indicated by the arrow in Figure 1. When a level-"0" signal is applied to the input In, the control circuit C1 cuts off the power transistors Q1 and Q4 and the control circuit C2 makes the transistors Q2 and Q3 conductive. A current I L thus flows through the load L in the direction opposite that indicated by the arrow of Figure 1. In a bridge circuit of the type described above with reference to Figure 1, it is of fundamental importance that current should not be conducted simultaneously in the two electronic power switches which are connected to the same output terminal. Should this occur, a very large current would be drawn from the supply with a serious risk of damage to the power switches, both as a result of the high intensity of the current passing through them and because of the related thermal effects. Some bridge circuits have circuitry for slowing the reversal of the voltage (current) in the load. In these solutions, the problem of preventing an upper power switch and the adjacent lower power switch from conducting simultaneously is more complex since the conductive power switches remain conductive throughout the time taken by the voltage in the load to change from its initial value to its final value. In order to take account of the time taken by the transition of the voltage in the load, it is therefore necessary further to delay the change to the conductive condition of the power switch which was originally cut off. A solution commonly used to prevent the simultaneous conduction of current in the two power switches which are connected to the same output terminal in upper and lower positions consists of the introduction of a delay between the switching-off of one switch and the switching-on of the other. Since it is difficult to determine very precisely the duration of the delay, for safety, it has to be suitably oversized. If the bridge circuit also has means for limiting the speed of the reversal of the voltage in the load, the delay has to be increased further to take account of the voltage-transition time and the related uncertainty with which that time is determined. In any case, long delay times limit the maximum frequency at which the current in the load can be reversed. Moreover, in bridge circuits produced in the form of integrated circuits, there is a considerable increase in the area of silicon needed. In bridge circuits in which, after switching, the current is recirculated by the same power switch which supplied the load before switching, the other power switch must be switched on only after the time taken by the recirculation has elapsed-. Since the recirculation time depends on the characteristics of the load, the provision of a given delay limits the use of the bridge circuit in question to loads cf certain types. An H-shaped bridge circuit of the kind according to the preamble of claim 1 is disclosed in US-A-3 538 353. In this prior art circuit, a simultaneous conduction in two power switches connected to a same output terminal is prevented by means of auxiliary switches associated each to a respective power switch. Each power switch is connected between an output terminal and one pole of a direct-current power supply. Each auxiliary switch is a bipolar transistor connected between the input terminal of the associated power switch and a pole of a separate bias voltage supply which, in operation, provides a d.c. bias voltage whose voltage magnitude is different from and specifically higher than that provided by said d.c. power supply. The arrangement is such that when a power switch belonging to one half-bridge is on, it causes a forward bias voltage to be applied to the base-emitter junction of the associated auxiliary switch, which thus also turns on and prevents a power switch of the other half-bridge from conducting. The object of the present invention is to provide an improved H-shaped bridge circuit of the type specified above which, in a very reliable manner, prevents the simultaneous conduction (crossover conduction) of two electronic power switches connected to the same input terminal. According to the invention, this object is achieved by an H-shaped bridge circuit having the features defined in claim 1. Further characteristics and advantages of the invention will become clear from the detailed description which follows with reference to the appended drawings, provided purely by way of non-limiting example, in which: Figure 1, which has already been described, shows an H-shaped bridge circuit of the prior art, Figure 2 is a circuit diagram of an H-shaped bridge circuit according to the invention, and Figure 3 is a circuit diagram of one embodiment of two circuits which are included in the bridge circuit of Figure 2 for controlling the switching. In Figure 2, parts and elements already described with reference to Figure 1 have again been indicated by the same alphanumeric reference symbols. In the circuit according to the invention shown in Figure 2, respective auxiliary transistors, indicated Q9-Q12, are associated with the power transistors Q1-Q4. In particular, the transistors Q9 and Q10 are pnp transistors as are the respective power transistors Q1 and Q2 with which they are associated, and the transistors Q11 and Q12 are npn transistors as are the corresponding power transistors Q3 and Q4. The base and the emitter of each of the auxiliary transistors Q10-Q11 are connected respectively to the base and the emitter of the corresponding power transistor Q1 - Q4. The collectors of the auxiliary transistors Q10 and Q11 are connected to corresponding inputs of the control circuit C1 which drives the bases of the power transistors Q1 and Q4 and the bases of the associated auxiliary transistors Q9 and Q12. The collectors of the auxiliary transistors Q9 and Q12 are connected to corresponding inputs of the second control circuit C2 which drives the bases of the power transistors Q2 and Q3 and the bases of the associated auxiliary transistors Q10 and Q11. In Figure 2, the currents for driving the bases of the power transistors Q1-Q4 and the associated auxiliary transistors Q9-Q12 are indicated Ib1, Ib2, Ib3 and Ib4. The collector currents in the four auxiliary transistors Q9-Q12 are indicated Ien1-Ien4. The control circuits C1 and C2 have identical internal structures, for example, the structure shown in Figure 3, which will now be described with reference to the circuit C1. In Figure 3, the alphanumeric reference symbols given in brackets apply to the control circuit C2. With reference to Figure 3, therefore, the control circuit C1 includes a first current generator I1 between the collector of Q10 and earth. In the embodiment illustrated, the generator I1 generates a current which is directed towards earth. The collector of Q10 is also connected to an inverter INV1, the output of which is connected to a first input of a NAND logic gate G. A second current generator I2 is connected between the positive pole of the voltage supply Vs and the collector of Q11. The latter is also connected to a second input of the logic gate G. A third input of this gate is also connected to the input terminal In. The output of the logic gate G is connected to the base of an npn transistor Q17 by means of a resistor R5. The emitter of the transistor Q17 is connected to the earth and its collector is connected to that of an npn transistor indicated Q18. A current generator I3 is connected between the supply Vs and the collector of Q18. The base of the transistor 18 is connected to its own collector and to the base of a further npn transistor, indicated Q19. The emitter of Q18 is connected to the base of Q4 by means of a resistor R6. The collector of the transistor Q19 is connected to the base of Q1 and its emitter is connected to the base of Q4 by means of a resistor R7. The bridge circuit described above with reference to Figures 2 and 3 can conveniently be produced in the form of a monolithic integrated circuit on a single substrate of semiconductor material, particularly silicon, and operates in the following manner. When a level-"1" signal is applied to the input In, the control circuit C1 absorbs a current Ib1 and generates a current Ib4 such as to keep the power transistors Q1 and Q4 saturated. The control circuit C2 keeps the power transistors Q2 and Q3 switched off, that is, cut off. In this situation, since the base-emitter voltages of Q1 and Q9 are the same, the collector current, indicated Ienl, of Q9 is n times smaller than I L , where n = A(Q1)/A(Q9) and where A(Q1) is much greater than A(Q9), A(Q1) and A(Q9) being the areas of silicon of the emitters of the transistors Q1 and Q9, respectively. Similarly, Ien4 = I L /m, where m = A(Q4)/A(Q12) and A(Q4) is much greater than A(Q12). In order to reverse the direction of the current I L in the load L, a level-"0" logic signal is applied to the input In. The output of the logic gate G of the control circuit C1 thus immediately goes to the level "1"; the transistor Q17 becomes conductive and the transistor Q19 is cut off. The currents Ib1 and Ib4 thus cease. The appearance of a level-"0" signal at the input In does not, however, cause the power transistors Q2 and Q3 to become conductive immediately. In fact (see Figure 3), in this case, a level-"1" signal is applied to the input In of the control circuit C2 but the signals at the other inputs of that gate remain at the level "0" until the currents Ien1 and Ien4 fall below the currents generated by the generators I1 and I2. The currents produced by these generators thus represent the minimum current thresholds below which the output currents of the auxiliary transistors Q9 and Q12 (which currents, as has been seen, represent fractions of the output currents of the power transistors Q1 and Q4) must fall in order for the output of the logic gate G of the control circuit C2 to cut off the transistor Q17 of that control circuit and thus cause its transistor Q19, and hence the power transistors Q2 and Q3, to become conductive. In view of the perfect symmetry of the bridge circuit and of the control circuits C1 and C2, the foregoing description relating to the stage in which Q2 and Q3 are made conductive after Q1 and Q4 have been cut off applies in a similar manner to the stage in which the transistors Q2 and Q3 are cut off and the transistors Q1 and Q4 become conductive again. Although, in the embodiment described above, auxiliary transistors are associated with all four power transistors Q1-Q4, clearly the use of auxiliary transistors could be limited to two (for example Q9 and Q10) associated with two power transistors which are intended to be switched on and off in opposition. The solution shown, which has four auxiliary transistors, prevents any problems resulting from the difference between the times taken by pnp and npn transistors to switch off. With few components, and hence with the use of a moderate area of silicon, the bridge circuit according to the invention provides effective protection against simultaneous conduction in the two electronic power switches connected to the same output terminal. The solution described prevents any problems relating to the creation of delay times which, in the prior-art circuits, have to be long and precise. The circuit according to the invention also has greater flexibility of usage since it can operate even when the switching-off times of the power transistors are different. The fact that a power transistor cannot be switched on until the power transistor connected to the same output terminal has been switched off prevents peaks in the current drawn from the battery during switching which could, however, occur if, for example, the switching-on of one power transistor were to cause the switching-off of the other. The fact that one power transistor is switched on as soon as the other power transistor connected to the same output terminal is switched off enables the load always to be driven with a low impedance (there is no situation in which both the power transistors are switched off). This is advantageous if, in suitable circuits, the output voltage is used, for monitoring the operation of the system. The use of the proposed solution in a bridge circuit in which the speed of the reversal of the voltage in the load is limited is particularly advantageous as regards the minimising of the number of components used, since it is free of delay times in the switching-on of the power switches. Since, in some cases, the voltage in the load intentionally takes a long time to change, the provision of a delay to take account of the uncertainty in determining this time might otherwise be too difficult, particularly in the case of integrated circuits. Another application in which the solution according to the invention is very advantageous is when the bridge circuit drives an inductive load and the power switches which supply the load before switching are also used for recirculating the current after switching.

Claims: An H-shaped bridge circuit including: first and second output terminals (OUT1, OUT2) for connection to the terminals of a load (L), first and second pairs of electronic power switches (Q1, Q4; Q2, Q3) which are connected between the output terminals (OUT1, OUT2) and the two poles of a direct-current voltage supply (Vs) so as to form an H-shaped structure with the load (L), and driver circuit means (C1, C2) for selectively making the electronic power switches of the first pair (Q1, Q4) or of the second pair (Q2, Q3) conductive in order to cause a current to flow through the load (L) in one direction or the other, respectively, and for preventing the electronic power switches (Q1, Q3; Q2, Q4) which are connected between the same output terminal (OUT1, OUT2) and the two poles of the voltage supply (Vs) from conducting simultaneously, the driver circuit means (C1, C2) having a drive input (In, In ) for receiving a two-state signal for controlling the switching; the driver circuit means also including: at least one first and one second auxiliary electronic switch (Q9, Q12; Q10, Q11) which are connected respectively to an electronic power switch of the first pair (Q1, Q4) and to an electronic power switch of the second pair (Q2, Q3) so that, in operation, the current flowing through each auxiliary electronic switch depends on the current flowing through the associated electronic power switch, and comparator and enabling circuitry (G, I1, I2) connected to the auxiliary electronic switches (Q9-Q12) for supplying a signal to enable current to be conducted through an electronic power switch of one pair (Q1, Q4; Q2, Q3) only when the current flowing through the auxiliary switch (Q9, Q12; Q10, Q11) associated with a power switch of the other pair (Q2, Q3; Q1, Q4) has fallen below a predetermined value; characterised in that said auxiliary electronic switches (Q9, Q12; Q10, Q11) are each connected to the same pole of said voltage supply (V s ) to which the associated power switch (Q1, Q4; Q2, Q3) is connected, in such a manner that the current flowing through each auxiliary switch (Q9-Q12) is a predetermined constant fraction (n, m) of that flowing through the associated power switch (Q1-Q4); the driver circuit means (C1, C2) including first and second control circuits (C1, C2) which are coupled to control inputs of both the power switches of the first pair (Q1, Q4) and, respectively, to control inputs of both the power switches of the second pair (Q2, Q3), each of said control circuits (C1, C2) having: a conduction-controlling circuit (Q17-Q19; I3) having two outputs connected to the control inputs of the associated pair of electronic power switches (Q1, Q4; Q2, Q3), at least one comparator circuit connected to the auxiliary switch associated with the other pair of electronic power switches (Q2, Q3) and to a reference current generator (I1, I2) for comparing the current (Ien1, Ien2, Ien3, Ien4) flowing in said auxiliary switch withd reference current; and an enabling logic circuit (G) having its output connected to the input of the conduction-controlling circuit (Q17-Q19; I3) and at least a first input connected to the drive input (In, In ) and a second input connected to the output of the comparator circuit. A circuit according to Claim 1, characterised in that the driver circuit means include two pairs of auxiliary electronic switches (Q9, Q12; Q10, Q11), each auxiliary switch being connected to an associated electronic power switch (Q1-Q4) so that, in operation, the current flowing though each auxiliary switch is a predetermined constant fraction (n, m) of the current flowing through the associated power switch, and in that the comparator and enabling logic circuits (C1, C2; G, I1, I2) is arranged to supply a signal for enabling current to be conducted through one of the pairs of power switches (Q1, Q4; Q2; Q3) only when the currents flowing in both the auxiliary switches (Q10, Q11; Q9, Q12) associated with the other pair of power switches (Q2, Q3; Q4, Q1) have fallen below predetermined values. A circuit according to Claim 1 or Claim 2, formed as a monolithic integrated circuit on a single substrate of semiconductor material, characterised in that the electronic power switches (Q1-Q4) and the auxiliary electronic switches (Q9-Q12) are transistors, the area of semiconductor material occupied by each auxiliary switch (Q9-Q12) being a fraction of the area occupied by the associated electronic power switch (Q1-Q4). A circuit according to any one of the preceding claims, characterised in that the electronic power switches (Q1-Q4) and the auxiliary electronic switches (Q9-Q12) are bipolar transistors, the base and the emitter of each auxiliary transistor (Q9-Q12) being connected respectively to the base and to the emitter of the associated power transistor (Q1-Q4), its collector being connected to the driver circuit means (C1, C2). A circuit according to Claim 2, characterised in-that the comparator and enabling logic circuits also include a second comparator circuit, the input of which is connected to the other auxiliary electronic switch associated with the other pair of electronic power switches and the output of which is connected to a further input of the enabling logic circuit (G). A circuit according to Claim 1, characterised in that the enabling circuit (G) is of the NAND type.

Inventors: MORELLI MARCO, POLETTO VANNI, POMA ALBERTO, MORELLI, MARCO, POLETTO, VANNI, POMA, ALBERTO
Applicants: MAGNETI MARELLI SPA, ST MICROELECTRONICS SRL, MAGNETI MARELLI S.p.A., STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H03K17
IPC codes: H03K17, H02M1