Video signal encoding apparatus using a block shuffling technique

Abstract: A video signal encoding apparatus for compressing and encoding a digital video signal comprises block structuring means (41) for structuring the video signal into a matrix array of blocks, transformation means (2) for performing an orthogonal transform on each of the structured blocks, and encoding means (5), wherein unit structuring means (41) for structuring units each comprising a plurality of blocks, prior to the orthogonal transform by said transformation means, by shuffling the blocks in such a manner that any given shuffling unit and four shuffling units most adjacent to said given shuffling unit belong to different units.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a video signal encoding apparatus for compressing and encoding a video signal by dividing it into blocks and performing an orthogonal transform on each block. Description of the Prior Art If video data converted to digital signals is directly recorded on tape or other recording medium, the volume of data will be so great that it will usually exceed the limit of the data amount that the recording medium can hold. Therefore, when recording a digital video signal on tape or other recording medium, it is necessary to compress it so that the data volume does not exceed the limit. To achieve this, it has been known to compress the video signal by using a high-efficiency encoding apparatus. One example of such high-efficiency encoding that has been widely used is the orthogonal transform encoding method in which transform coefficients obtained by orthogonal-transforming the original signal are quantized for encoding. This method is known to provide high encoding efficiency. In encoding a video signal by this method, the video signal is first divided into blocks each consisting of n × n pixels (where n is an integer), an orthogonal transformation is performed on each block to transform it into a transform coefficient representing n × n frequency regions, and then the transform coefficient is quantized. However, when all blocks are quantized with the same number of bits, adequate image quality can be obtained for the video blocks in flat areas, but noise appears in the video blocks including edge areas since errors are dispersed in the vicinity of the edge areas. An example of an encoding apparatus that overcomes the above problem is disclosed in Japan Patent Application Laid-Open No. JP-A-2 105 792. Fig.1 shows a block diagram of the encoding apparatus disclosed in the Patent Publication. The encoding apparatus shown is described below with reference to Fig.1. A video signal is inputted to a blocking circuit 51 where it is divided into blocks, each block then being supplied to an orthogonal transforming circuit 52 for orthogonal transformation. The transform coefficient obtained by the orthogonal transformation is quantized by a quantizing circuit 53. The quantizing circuit 53 has the ability to perform quantization using a variable number of quantization bits. An edge area detecting circuit 54 is provided to detect the edges of the video signal, while a flat area detecting circuit 55 is provided to determine whether the block represents a flat area. Based on the outputs from the edge area detecting circuit 54 and the flat area detecting circuit 55, a block identifying circuit 56 determines whether the block includes an edge area as well as a flat area, the result of which is fed to the quantizing circuit 53 to determine the number of quantization bits. When the whole block is flat or when the whole block has a complicated structure, it is decided to use a smaller bit code for quantization since noise is not appreciably visible. On the other hand, if the block includes an edge area as well as a flat area, it is decided to use a higher bit code for quantization to prevent the generation of noise in the flat area. Thus, in the encoding apparatus disclosed in the above Patent Publication, in order to overcome the aforementioned problem, the transform coefficients for blocks including both edge and flat areas are quantized using a higher bit code to reduce the noise and thereby improve the image quality after decoding. The determining factors used to detect the edge or flat areas in a block include a variance within the block, the maximum value of the block, the dynamic range of the block, etc. These factors are collectively referred to as the activity index. In the above prior art encoding apparatus, the number of quantization bits (quantization level) is selected for each block on the basis of the activity index. The output of the quantizing circuit 53 of Fig.1 is encoded, usually using entropy encoding such as Huffman encoding, into a variable-length code for transmission. The bit length of one block after variable-length encoding varies from block to block, and in the case of a recording medium such as a helical scan digital video tape recorder (VTR) having a fixed track length, it is convenient to grasp the number of data blocks to be recorded per track. Therefore, it is a usual practice to predetermine at least the number of data blocks to be recorded per track. Also, when block correcting codes (e.g., BCH codes, Reed-Solomon codes, etc.) are employed as error-correcting codes, it may be practiced to fix the data length of variable-length code for each error-correcting block. Usually, in encoding of video signals, one field or frame is divided into N segments (where N is an integer), each segment serving as a unit, and the maximum data amount is set for each of the N units. However, in a channel, such as a digital VTR, in which the data length for the variable-length codes is fixed, the data length of variable-length code may vary from code to code after variable-length encoding depending on the kind of the image processed, and the total code length after variable-length encoding may exceed the fixed length of the channel, resulting in an overflow. If this happens, the transmission will be cut off because of dataflow, and therefore, not only overflown data but also the subsequent data will not be transmitted. This presents the problem of an inability to correctly perform the decoding of the original signal. Variable-length encoding of a television image is usually performed in sequence from left to right and from top to bottom of the television screen. Therefore, the problem is that the above-mentioned cutoff is likely to occur in the center of the television screen where the feature elements of the image are contained. IEEE TRANSACTIONS ON ACOUSTICS AND SPEECH AND SIGNAL PROCESSING; vol. 37, no. 11, November 1989, NY, US, pages 1743-1749, NGAN et al.: "Adaptive Cosine Transform Coding of Images in Perceptual Domain" already discloses a video signal encoding apparatus for compressing and encoding a digital video signal to obtain coded data compressed within a predetermined data amount. This apparatus comprises means for structuring blocks each consisting of a plurality of pixels in the video signal, means for performing an orthogonal transformation on each of the structured blocks to obtain a transform coefficient, means for quantizing the transform coefficient, means for encoding the quantized data to obtain coded data, means for storing the obtained coded data, and means for controlling the quantizing means on the basis of the amount of the coded data stored in the storage means. PAJP, vol. 12, no. 124 (E 601) shows a picture signal transmission system which obtains a smooth reproducing moving image with improved visual characteristic by dividing both surfaces into plural areas, applying priority to the respective areas and transmitting more information of the area of the higher priority than the information of the area of the lower priority. PAJP. vol. 12, no. 355 (E 661) describes a picture compressing device which in order to reduce the number of quantizing errors and to shorten the operating time comprises a preprocessing means which pre-processes original picture data and a rearranging section which rearranges an orthogonally transformed output in blocks of the same frequency component. Further, EP-A-0 322 955 refers to a receiver for a high definition television signal in which the signal prior to transmission is sub-sampled on a block-by-block basis according to the movement. The received sub-sampled signal is applied to a shuffler which shuffles the pixels of blocks in a manner which is the inverse to that performed prior to transmission. SUMMARY OF THE INVENTION It is the object of the invention to provide a video signal encoding apparatus capable of fixing the encoded data length to a predetermined length wherein distortions resulting from transmission cutoffs are not easily visible even when the code length of the data to be transmitted is fixed. According to a first embodiment of the present invention a video signal encoding apparatus for compressing and encoding a digital video signal comprises block structuring means for structuring the video signal into a matrix array of blocks each consisting of a plurality of pixels, transformation means for performing an orthogonal transform on each of the blocks to obtain a transform coefficient, and encoding means for encoding the obtained transform coefficient to obtain coded data, which apparatus is characterized by unit structuring means for structuring units each comprising a plurality of blocks, prior to the orthogonal transform by said transformation means, in such a manner that any given block and four blocks most adjacent to said given block belong to different units being the size that the blocks of said chrominance signal occupy on the screen. According to a preferred embodiment the digital video signal contains a chrominance signal, and said unit structuring means comprises shuffling means for structuring units by shuffling the blocks in such a manner that any given block and four blocks most adjacent to said given block belong to different units, the size of the shuffling unit depending on the size that the blocks of said chrominance signal occupy on a screen. According to a further preferred embodiment the video signal encoding apparatus comprises decision means for deciding the order in which the blocks are to be encoded, the order within each unit being such that encoding is performed starting with the blocks nearer to the center of the screen and then proceeding to the blocks nearer to the sides of the screen; and control means for controlling the amount of coded data on a unit-by-unit basis. The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the configuration of a prior art video signal encoding apparatus. Fig. 2 is a diagram showing the configuration of a video signal encoding apparatus comprising a variable length encoding circuit and a buffer memory. Fig. 3 is a diagram showing an example of encoding during the process. Fig. 4 is a diagram showing the scanning sequence during encoding. Fig. 5 is a diagram showing an alternative configuration of the apparatus of Fig. 2. Fig. 6 is a graph showing code length variations equalized by shuffling. Fig. 7 is a diagram showing shuffling units for a sample ratio of 4:1:1. Fig. 8 is a diagram showing shuffling units for a sample ratio of 4:2:0. Fig. 9 is a diagram showing an example of shuffling. Fig. 10 is a diagram showing shuffling units for a sample ratio of 4:1:0. Fig. 11 is a diagram showing the configuration of a video signal encoding apparatus in accordance with a first embodiment of the invention. Fig. 12 is a diagram explaining the operation of shuffling in the first embodiment. Fig. 13 is a diagram explaining the principle of shuffling in the first embodiment. Fig. 14 is a diagram showing an example of shuffling in the first embodiment. Fig. 15 is a diagram showing another example of shuffling in the first embodiment. Fig. 16 is a diagram showing still another example of shuffling in the first embodiment. Fig. 17 is a diagram showing the configuration of a shuffling circuit in the first embodiment. Fig. 18 is a diagram showing the configuration of a video signal encoding apparatus in accordance with a second embodiment of the invention. Fig. 19 is a diagram showing an alternative configuration of the second embodiment. Fig. 20 is a diagram showing an example of shuffling in the second embodiment. Fig. 21 is a diagram showing another example of shuffling in the second embodiment. Fig. 22 is a diagram showing still another example of shuffling in the second embodiment. Fig. 23 is a diagram showing yet another example of shuffling in the second embodiment. Fig. 24 is a diagram showing a further example of shuffling in the second embodiment. Fig. 25 is a diagram showing a still further example of shuffling in the second embodiment. In Fig. 2, the reference numeral 1 indicates a blocking circuit for dividing the input digital video signal into blocks each consisting of plurality of pixels. Each block is fed from the blocking circuit 1 to a DCT circuit 2. The DCT circuit 2 performs a discrete cosine transform (DCT) on each block and supplies the obtained transform coefficient (DCT coefficient) to a weighting circuit 3. The weighting circuit 3 performs a weighting to each DCT coefficient and supplies the weighted DCT coefficient to a quantizing circuit 4. The quantizing circuit 4 quantizes the weighted DCT coefficient with the number of quantization bits determined by a controller 8, and supplies the quantized DCT coefficient to a variable-length encoding circuit 5 through a switch 7. The variable-length encoding circuit 5 encodes the quantized DCT coefficient into a variable-length code and transfers the variable-length encoded data to a buffer memory 6. The buffer memory 6 is constructed from a RAM or the like and has the storage capacity equivalent to the data length of one track. The switch 7 turns on and off the data input to the variable-length circuit 5. The controller 8 controls the number of quantization bits for the quantizing circuit 4, as well as the switching operation of the switch 7, on the basis of the amount of data stored in the buffer memory 6. The operation will now be described. The data obtained by sampling the video signal is divided by the blocking circuit 1 into blocks each consisting of, for example, eight pixels in both horizontal and vertical directions. The DCT circuit 2 performs a DCT on each block, and the obtained DCT coefficient is then performed a weighting by the weighting circuit 3. At this time, the weighting is performed so that weighting factors for DCT coefficients in higher frequency regions will be smaller values. This is because the visual resolution drops for higher frequency regions, allowing high-efficiency encoding without noticeable degradation. Next, the weighted DCT coefficient is quantized by the quantizing circuit 4. Quantized n-bit data may be expressed as shown in Fig.3, for example. This data is encoded by the variable-length encoding circuit 5 into a variable-length code by performing one-dimensional scanning as shown in Fig.4. The variable-length encoding circuit 5 is a circuit for encoding data into a code whose length depends, for example, on the string of zeros (zero run length) and nonzero value, and usually, the Huffman encoding and like methods are widely used. The output of the variable-length encoding circuit 5 is stored in the buffer memory 6 for transfer to the transmission channel. However, the length of the variable-length code outputted from the variable-length encoding circuit 5 varies according to the image pattern and, depending on the situation, may exceed or may not reach the maximum transmissible code length. The controller 8 predicts an occurrence of excess data by comparing the address value being written in the buffer memory 6 with the limit data length, and outputs signals to control the number of quantization bits for the quantizing circuit 4 and the switching operation of the switch 7. Therefore, even if the data volume instantaneously increases at a particular portion of the image on the television screen, the buffer memory 6 can provide a sufficient capacity for data storage, and there arises no situation that results in an overflow or that causes the controller 8 to direct transmission cutoff. Fig. 5 is a block diagram showing an alternative configuration. In this alternative configuration, the controller 8 controls only the switching operation of the switch 7. When recording data on a VTR tape, the code amount greatly varies depending on the image pattern to be recorded. It is convenient to fix the data length to a length calculated by dividing the track length by an integer. It is usually most convenient to fix the data length by dividing one field or one frame or m frames into n units. Fig. 6, for example, shows the generated code amount when one frame is divided into 10 units. The symbol - Δ - in Fig. 6 represents the code amount. As shown, four out of the 10 units largely exceeds the transmissible limit, while the other six units are far below the limit. When a cutoff control is exercised on the four units to a large extent, the code amount has to be reduced, sacrificing the signal-to-noise ratio to a certain degree, while on the other hand, an improvement in the signal-to-noise ratio is expected for the remaining six units with the addition of additional data, etc. When the code amount is controlled between the units, such a bias in the code amount distribution can be desregarded since the code amount overflown from the four units can be transmitted using the other six units (actually, using units in the next frame). However, processing covering too many units only serves to complicate the hardware configuration and does not provide worthwhile advantages. It is therefore important to devise so that the processing will be completed within each unit. That is, it is important to minimize the bias in the code amount within each unit. One approach to this is to equalize the generated code amount between the units by shuffling the blocks so that any given DCT block and four DCT blocks most adjacent to the given DCT block belong to different units. The code amount generated as a result of such shuffling is shown by the symbol - ○ - in Fig. 6. As can be seen from Fig. 6, the shuffling has served to substantially equalize the generated code amount. Controlling the code amount within each unit after equalizing is extremely advantageous in terms of the following points. Since the code amount control is performed only within each unit, the hardware is very simple in construction. Even when the code amount control is performed within each unit, there occurs no need to reduce the rate for a particular portion within one frame, as a result of which degradation in the signal-to-noise ratio is prevented from concentrating on a particular portion on the screen. When special replay modes are considered, it will be more convenient if the code amount is controlled after performing the above-mentioned shuffling by grouping together DCT blocks of the chrominance signal having a fewer number of samples. More specifically, when the sample ratio between the luminance and chrominance signals is 4:1:1, for example, four horizontally successive CDT blocks as shown in Fig. 7 are grouped into a shuffling unit and shuffling is performed on this unit, after which the code amount is controlled within this unit. In the case of special replay modes, some blocks may not be reproducible, but when shuffling is performed on the above configured unit, reproduction is possible with both the luminance and chrominance signals balanced. Without such shuffling, the second DCT block from left of the luminance signal, for example, may be dropped, resulting in serious degradation in special replay mode image quality. Further, when the sample ratio between the luminance and chrominance signals is 4:2:0 (color line sequential processing), for example, the above-described shuffling is performed by grouping two horizontally adjacent and two vertically adjacent DCT blocks into one shuffling unit. With this grouping, the area size that one DCT block of the chrominance signal takes on the screen becomes equal to the shuffling unit of the luminance signal. With this as one shuffling unit, the shuffling as shown in Fig. 9 is performed. Fig. 9 shows an example of shuffling in the case of the shuffling unit shown in Fig. 8 when the sample ratio between the luminance and chrominance signals is 4:2:0 and when one field is divided into five units. Fig. 10 is an example of shuffling when the sample ratio between the luminance and chrominance signals is 4:1:0. The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. (Embodiment 1) When a plurality of blocks is grouped into a unit, it has been a usual practice to perform encoding unit by unit starting from a particular position on the screen (e.g. from the upper left of the screen). Therefore, the code amount varies largely from unit to unit, and there arises the problem that the transmission efficiency decreases when the upper limit of data amount is set to match the units having a larger code amount. The first embodiment and the subsequent second embodiment of the invention are provided aiming at overcoming such a problem. Fig.11 is a block diagram showing the configuration of a video signal encoding apparatus in accordance with the fifth embodiment of the invention. In Fig.11, the reference numerals 2, 3, 4, and 5 designate a DCT circuit, a weighting circuit, a quantizing circuit, and a variable-length encoding circuit, respectively. These circuits are identical to those shown in Fig. 5. At the front stage of the DCT circuit 2, there is provided a blocking/shuffling circuit 41 for dividing a digital video into blocks of a plurality of pixels and shuffling the thus obtained blocks. The block data is supplied from the blocking/shuffling circuit 41 to the DCT circuit 2. The quantizing circuit 4 quantizes the weighted DCT coefficient with the number of quantization bits decided by a quantization bit number deciding circuit 43 and supplies the quantized DCT coefficient to the variable-length encoding circuit 5. The variable-length encoding circuit 5 encodes the quantized DCT coefficient into a variable-length code and supplies the variable-length code data to a buffer memory 42. The operation will now be described. A digital video signal is inputted in scanning line sequence to the blocking/shuffling circuit 41 where the signal is divided into blocks of n × n pixels within one field or one frame and then shuffled in accordance, for example, with the shuffling format shown in Fig.12. One block in Fig.12 corresponds to one DCT block and the outer frame corresponds to that of the television screen. When the luminance signal conforming to the NTSC system is sampled at a rate of 13.5MHz, for example, the effective scanning area per frame covers 720 pixels in the horizontal direction and 486 pixels in the vertical direction. When one frame is divided into blocks of 8 × 8 pixels, for example, there remain six pixels each in the vertical direction; therefore, it is supposed here to encode the picture signal for 720 × 480 pixels, discarding the data for the three horizontal scanning lines from the top and bottom of the screen. Since the video signal is divided into blocks of 8 × 8 pixels, this means 90 × 60 blocks, i.e., 5,400 blocks in total. That is, when the block address in the horizontal direction within one frame is denoted as i and that in the vertical direction as j, i is expressed as 1≦i≦90 and j as 1≦j≦60. Furthermore, the 5,400 blocks are grouped into N units. In Fig.12, N = 5, and the alphabetic characters in A1, B1, etc. assigned to each block indicate the names of the units. Since N = 5, there are five unit names A to E. The numeric parts in A1, B1, etc. are numbers indicating the encoding sequence within each unit. In Fig.12, encoding is performed, as a general rule, from left to right and from top to bottom of the screen. In the example shown, since there are 90 blocks in the horizontal direction, the second line from top in Fig.12 begins with the number 19 which is given by dividing 90 by N (= 5) and adding 1 to the quotient. Therefore, the block address (i, j) for the kth encoding in the uth unit can be expressed by the following equation (1) (provided that (1, 1) indicates the top left corner of the screen and (90. 60) the bottom right corner). .pa [a]: Largest integer not exceeding a For example, when u = 2 and k = 20, the block address is given by: i = 5 × mod(20 - 1, 18) + mod [2 + [(19 × 5)/90] - 1, 5] + 1 = 5 × 1 + mod(2, 5) + 1 = 5 + 2 + 1 = 8 j = [(19 × 5)/90] + 1 = 2 Thus, the block address (8, 2) is obtained. Also, u = 2 indicates the unit name is B, and in Fig. 12, the address (8, 2) designates the block B20. Likewise, the address of the block C57, for example, can be found as follows: i = 5 × mod(57 - 1, 18) + mod [3 + [(56 × 5)/90] - 1, 5] + 1 = 5 × 2 + mod(3 + 3 - 1, 5) + 1 = 10 + 0 + 1= 11 j = 4 which gives the address (11, 4). That is, Fig.12 shows the arrangement of blocks after performing shuffling as expressed by the equation (1). After the above shuffling, each block is sequentially fed to the DCT circuit 2 for a DCT transform and is then performed a weighting by the weighting circuit 3. The quantization bit number deciding circuit 43 calculates the activity index of each block, on the basis of which the number of quantization bits is decided for the block, the information being fed to the quantizing circuit 4. The weighted DCT coefficient is quantized by the quantizing circuit 4 using the number of quantization bits thus decided, and the quantized data is then encoded by the variable-length encoding circuit 5 using such methods as Huffman encoding, the encoded data being transferred to the buffer memory 42 for storage therein. As the above shuffling, the patterns represented by the blocks to be coded are randomly dispersed, and therefore, the code length is equalized between the units when the number of blocks is greater than a certain degree. According to the simulation conducted by the inventor, it has been found that, when the units are assigned by shuffling as shown in Fig. 12, the dispersion value indicating the dispersion of the code amount is reduced to 1/5 to 1/10, compared to when a particular position on the screen is grouped together in a unit without shuffling. Next, the features of this shuffling will be considered. When considering the effects that the shuffling has on the code amount, the point is to avoid concentrating the blocks of the same pattern in the same unit, which leads to the following point when considered in conjunction with pixels. Blocks neighboring an attention block often have similar patterns, therefore, processing is performed to assign neighboring blocks to different units. This processing is described below using the concept of neighborhood. Each of the nine squares in Fig.13 represents a DCT block. There are eight blocks (A to F in Fig.13) that neighbors an attention block. These blocks are referred to as the eight neighboring blocks, of which the four blocks A, B, C, and D that are most adjacent to the attention block are called the four neighboring blocks. Referring back to Fig.12, it can be seen that when attention is given to a given block, none of its four neighboring blocks belong to the same unit as the attention block. Of its eight neighboring blocks, there are only two blocks that belong to the same unit. The four neighboring blocks that are spatially most adjacent to the attention block are thus made to belong to different units in order to prevent similar patterns from being concentrated in one unit. This serves to equalize the code amount. This effect can be achieved not only by the equation (1) but by many other methods. Figs. 14 to 16 show only a few examples of the many methods. In the examples of shuffling shown in Figs. 14 to 16, there are no four neighboring blocks that belong to the same unit. The block address (i, j) in Fig. 14 is expressed by the following equation. .pa i = [ mod(k - 1, 90) N ] × N + [ N + 1 2 ] + (-1) mod(k, N) × [ mod(k, N) 2 ] j = mod(mod(k - 1, 90) + u - 1, N) + 1 + N × [ k - 1 90 ] For example, to find the address of the block D98, since u = 4 and k = 98, i = [{mod(97, 90)}/5] × 5 + 3 + (-1) 3 × [{mod(98, 5)}/2] = 5 + 3 - 1 = 7 j = mod (7 + 4 - 1, 5) + 1 + 5 × 1 = 0 + 1 + 5 = 6 which gives the address (7, 6). The block address (i, j) in Fig. 15 is expressed by the following equation. i = mod(mod(k - 1, 90) + u, N) + [ mod(k - 1, 90) N ] × N j = [ k - 1 90 ] × N + [ N + 1 2 ] + (-1) mod(k-1, N) × [ mod(mod(k - 1, 90) ,N) + 1 2 ] For example, to find the address of the block E102, since u = 5 and k = 102, i = mod(11 + 5, 5) + [11/5] × 5 = 1 + 10 = 11 j = 1 × 5 + 3 + (-1) × [{mod(11, 5) + 1}/2] = 5 + 3 - 1 = 7 which gives the address (11, 7). Likewise, there exists an equation that realizes the shuffling shown in Fig. 16 along with various other equation that achieve various other shuffling formats. The circuit that performs the above shuffling operations can be implemented in the configuration shown in Fig. 17. In the figure, the reference numeral 46 designates a block address calculating circuit for calculating the block horizontal address (i) and the block vertical address (j) using the above given equations, and the block address obtained by the block address calculating circuit 46 is supplied to a write/read address generating circuit 45. On the basis of the supplied block address, the write/read address generating circuit 45 outputs a writw/read address to a RAM 44. In the RAM 44, each block is arranged according to the address, thus achieving the shuffling as shown in Figs. 12, 14, 15, and 16. (Embodiment 2) With the above shuffling, the code amount is substantially equalized between the units within one field or one frame, but in the case of a time-varying image, the image pattern may completely change after several seconds, causing the code amount of each unit within one field or one frame to increase or decrease. If the code amount increases in each unit, it may exceed the maximum transmissible data amount. This presents a serious problem, particularly in the case of a helical scan VTR, since, as previously described, each track is divided into lengths so that each length is the result of dividing the track length by an integer, each limited fixed amount being assigned to codes for a fixed number of blocks. The second embodiment of the invention is devised to overcome this problem. The following describes the second embodiment. Figs. 18 and 19 are block diagrams each showing the configuration of a video signal encoding apparatus in accordance with the second embodiment. In Fig.18, the quantizing circuit 4 and the variable-length encoding circuit 5 are controlled using the information on the memory usage in the buffer memory 42. In Fig.19, the quantization bit number deciding circuit 43 and the variable-length encoding circuit 5 are controlled using the information on the memory usage in the buffer memory 42. The buffer memory 42 has the capacity to store data of the volume that matches the limit code amount. When the buffer memory 42 nears its full capacity, the probability increases that codes will be generated that may exceed the transmissible limit, and therefore, control is performed to reduce the number of quantization bits, cut off the variable-length encoding, etc. However, such control only succeeds in reducing the code amount by sacrificing the image quality after decoding. As a result of the aforementioned shuffling, there is a possibility, for example, that such control may be effected while processing the center portion of the screen. Since the probability is high that such control is performed on the blocks near the end of each unit, the blocking/shuffling circuit 41 operates in such a manner that the blocks entered near the end of each block are positioned at the edge of the screen. An example of such shuffling is shown in Fig. 20. In Fig. 20, it can be seen that blocks with smaller numbers are clustered nearer to the center of the screen, while blocks with larger numbers are clustered on both sides of the screen. Furthermore, in Fig. 20, which shows the shuffling with N = 5, none of any attention block and the four neighboring blocks belong to the same unit. When the block address of the kth block in the uth unit is denoted as (i, j), the shuffling shown in Fig. 20 is expressed by the following equation. For example, to find the address of the block C134, since u = 3 and k = 134, i = 45 - (-1) 11 × [6] = 45 + 6 = 51 j = ([65/10] - 1] × 5 + 1 - (-1) 1 × 5 × 1 + mod(11 + 3 -1, 5) = 26 + 5 + 3 = 34 which gives the address (51, 34). There are many examples of such shuffling, other than that described above, some of which are shown in Figs. 21 to 25. In Figs. 23 to 25, the block vertical address starts from the top of the screen; it has been confirmed by simulation that distortion is likely to occur on both sides of the screen, as in the case of Fig. 20, The shuffling of Fig. 24 is similar to that of Fig. 23, except that N = 10, providing 10 units names A to K (I is not used as it can be confused with 1). Also, the shuffling of Fig. 25 is similar to that of Fig. 23, except that N = 3. The shuffling such as shown in Fig. 23 is expressed by the following equation. i = 90 2 - (-1) [{(k-1)·N}/60] × [ [ k-1 · N 60 ] + 1 2 ] j = N × mod(k - 1, 60 N ) + 1 + mod [ (k - 1) · N 60 ] + u - 1, N For example, in Fig. 23, to find the address of the block E147, since u = 5 and k = 147, i = 45 - (-1) 12 × [(12 + 1)/2] = 45 - 6 = 39 j = 5 × 2 + 1 + mod(12 + 5 - 1, 5) = 11 + 1 = 12 which gives the address (39, 12). With the above-described shuffling, distortion resulting from the code amount control is driven to both sides of the screen. In the above equation, when N = 2, the possibility may arise that some of four neighboring blocks belong to the same unit, but this is the problem that arises as a result of the shuffling so performed as to position the blocks nearer to the sides of the screen as k increases. Since such blocks appear only on limited portions of the screen, they do not substantially affect the distribution of the code amount. In an ordinary digital VTR, this does not present any problems in actual use since N is usually set at 3 or a greater number considering special replay modes, etc. In any of the above figures illustrating the shuffling, the operation is based on divisions with N as the modulus, but it will be appreciated that similar effects can be obtained when the divisions are performed by taking an integral multiple of N or a quotient of an integer by an integer of N as the modulus. For example, when N = 10, usually 10 is taken as the modulus, but either 20 or 5{10 × (1/2)] may be taken as the modulus. In the above first and second embodiments, shuffling is performed in units of blocks, but alternatively, shuffling may be performed by, for example, grouping (t × s) blocks into one unit. In the above embodiments, orthogonal transform has been described by taking the DCT as an example, but it will be appreciated that other orthogonal transforms than the DCT, such as Hadamard transform, K-L transform, etc. may also be used. Also, the weighting circuit 3 may be omitted in a configuration in which the quantization width of the quantizing circuit 4 is made to vary depending on the frequency.

Claims: A video signal encoding apparatus for compressing and encoding a digital video signal, comprising: block structuring means (41) for structuring the video signal into a matrix array of blocks each consisting of a plurality of pixels; transformation means (2) for performing an orthogonal transform on each of the structured blocks to obtain a transform coefficient; and encoding means (5) for encoding the obtained transform coefficient to obtain coded data, characterized by unit structuring means for structuring units each comprising a plurality of blocks, prior to the orthogonal transform by said transformation means (2), in such a manner that any given block and four blocks most adjacent to said given block belong to different units. A video signal encoding apparatus according to claim 1, wherein the digital video signal contains a chrominance signal and said unit structuring means comprises shuffling means for structuring units by shuffling the blocks in such a manner that any given block and four blocks most adjacent to said given block belong to different units, the size of the shuffling unit depending on the size that the blocks of said chrominance signal occupy on a screen. A video signal encoding apparatus according to claim 1, further comprising: decision means for deciding the order in which the blocks are to be encoded, the order within each unit being such that encoding is performed starting with the blocks nearer to the center of the screen and then proceeding to the blocks nearer to the sides of the screen; and control means for controlling the amount of coded data on a unit-by-unit basis.

Inventors: MISHIMA HIDETOSHI, MISHIMA, HIDETOSHI, Mishima, Hidetoshi, c/o Mitsubishi Denki K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N7
IPC codes: H04N5, G06T9, H04N7