METHOD AND APPARATUS FOR ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK

Abstract: Reactive congestion control in an asynchronous transfer mode (ATM) network where the network is formed by the interconnection of nodes each including a forward path (8-OF, 8-2F, 8-(C)F) for transfer of information from source (4-(S)) to destination (4-(D)) through the network and a return path (8-(C)R, 8-(C-1)R, 8-1R, 8-OR) for returning congestion control signals. Each source includes a modifiable issue rate unit which issues forward information signals at different rates for virtual channels in response to the presence and absence of congestion signals received on the return path. A segmentation communication unit segments packets into a plurality of cells concurrently for a plurality of channels for transmission over the ATM network. A reassembly communication unit reassembles cells received from the ATM network concurrently for the plurality of channels. Pipelined processing units are employed for segmentation and for reassembly.

Description: METHOD AND APPARATUS .FOR ASYNCHRONOUS TRANSFER MODE (AIM) NETWORK BACKGROUND OF THE INVENTION A portion of the disclosure of this patent document contains • material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The present invention relates to communication systems and more particularly to asynchronous transfer mode (ATM) communica¬ tion networks. A communication network functions to interconnect many network users. Each user is connected to the network at a port. Typically, the network is formed by a number of interconnected nodes where information (from a user at a source) is input at an input port, is passed by the input port from node to node through the network, and is output at an output port (to a user at a destination) . Information can be communicated through a communication network in various forms. For example, time-sensitive voice, video and circuit emulation information is typically transmitted in constant bit rate (CBR) form while computer and other non- time-sensitive information is typically packetized and communi¬ cated in variable bit rate (VBR) form. In communication networks, each node switches incoming information at input ports to outgoing information at output ports. For time-sensitive information, the communication through the ATM network is in CBR (constant bit rate) form and for packetized information the communication through the ATM network is in VBR (variable bit rate) form. Fast packet switches typically can transfer hundreds of thousands of packets per second at every switch port in a communication network. Each switch port is typically designed to transfer information at a rate from 50 Mbits/s to 600 Mbit/s for broadband integrated service digital networks (ISDN) . Switch sizes range from a few ports to thousands of ports. The term "fast packet switch" includes switches capable of handling both variable-length packets of information and fixed- length packets of information. Fixed-length packets of informa¬ tion are desirable since they simplify the . switch design. Fast packet switches using short, fixed-length packets (called "cells") are referred to as asynchronous transfer mode (ATM) switches. ATM switches connected together form an ATM network. For ATM networks and switches, the term "packet" refers to variable-length information. Typically, a packet is hundreds and sometimes thousands of 8-bit bytes in length. For ATM networks and switches, the term "cell" refers to short (relative to packets of maximum length), fixed-length information. Typically, a cell is 53 8-bit bytes in length. Fast packet switches are capable of handling different types of communications services in a single integrated communication network including the time-sensitive voice, video and circuit emulation information in constant bit rate (CBR) form and including computer and other non-time-sensitive information in variable bit rate (VBR) form. Although voice and video services can tolerate only a limited amount of delay and delay variance through a communication network, ATM switches are suitable for such services since they minimize delay and delay variance. ATM networks are suitable for concurrently transmitting both CBR time-sensitive and VBR non-time-sensitive information * from sources to destinations through an ATM network having many differnt users. The ATM standard for broadband ISDN networks defines a cell having a length of 53 bytes with a header of 5 bytes and data of 48 bytes. Broadband ISDN defines two transmission bit rate standards of 155M bit/s and 622M bits/s so that the cell clock periods are 2.7 microseconds and 0.68 microseconds, respective- ly, and the cell clock rates are 0.36M cells/sec and 1.47M cells/sec, respectively. In a.typical ATM switch, the cell processing functions are performed within the nodes of a network. Each node is an ATM switch which includes input controllers (IC's), a switch fabric (SF), output controllers (OC's) and a node control (C) . The node control is used for functions including connection establishment and release, bandwidth reservation, congestion control, maintenance and network management. In each switch, the input controllers are typically synchronized so that all cells from input controllers arrive at the switch fabric at the same time and so that cells can be accepted or rejected according to their priority. The traffic through the switch fabric is slotted and the switch fabric delay equals the sum of the timeslot duration, pipeline delay, and the queueing delay. The node control communicates with the input controllers and the output controllers either by a direct communication path which by-passes the switch fabric or via control cells trans¬ mitted through the switch fabric. External connections to the • switch are generally bi¬ directional. Bidirectional connections are formed by grouping an input controller (IC) and an output controller (OC) together to form a port controller (PC) . The input sequence of cells in a virtual channel is preserved across the switch fabric so that the output sequence of cells on each virtual channel is the same as the input sequence. Cells contain a virtual channel identifier VCI in the cell header which identifies the connection to which the cell belongs. Each incoming VCI identifier in the header of each cell is translated in an input controller to specify the outgoing VCI identifier. This translation is performed in the input controller typically by table look-up using the incoming VCI identifier to address a connection table. This connection table also contains a routing field to specify the output port of the switch fabric to which the connection is routed. Other information may be included in the connection table on a per connection basis such as the priority, class of service, and traffic type of the connection. In an ATM switch, cell arrivals are not scheduled. In a typical operation, a number of cells may arrive simultaneously at different input ports each requesting the same output port. Operations in which requests exceed the output capacity of the output port are referred to as output contention (or conflict) . Since an output port can only transmit a fixed number (for example, one) cell at a time, only the fixed number of cells can be accepted for transmission so that any other cells routed to that port must either be discarded or must be buffered in a queue. Different methods are employed for routing cells through a switch module, for example, self-routing and label routing. A self-routing network operates with an input controller prefixing a routing tag to every cell. Typically, the input controller uses a table lookup from a routing table to obtain the routing tag. The routing tag specifies the output port to which the cell is to be delivered. Each switching element is able to make a fast routing decision by inspecting the routing tag. The self-routing network ensures that each cell will arrive at the required destination regardless of the switch port at which it enters. A label routing network operates with a label in each cell referencing translation tables in each switching element. The label is translated in each switching element and hence any arbitrary network of switching elements may be employed. Switches have two principal designs, time-division and space division. In a time-division switch fabric, all cells flow through a single communication channel shared in common by all input and output ports. In a space division switch, a plurality of paths are provided between the input and output ports . These paths operate concurrently so that many cells may be transmitted across the switch fabric at the same time. The total capacity of the switch fabric is thus the product . of the bandwidth of each path and the average number of paths that can transmit a cell concurrently. When the traffic load exceeds the available system resources in a network, congestion is present and performance degrades. When the number of cells is within the carrying capacity of the network, all cells can be delivered so that the number of cells delivered equals the number of cells sent without congestion. However, if cell traffic is increased to the level that nodes cannot handle the traffic, congestion results. Congestion can be brought about by several factors. If nodes in a network are too slow to perform the various tasks required of them (queueing buffers, updating tables, etc.), queues build up, even though excess line capacity exists. On the other hand, even if nodes are infinitely fast, queues will build up whenever the input traffic rate exceeds the capacity of the output traffic rate for any particular group of outputs. If a node has no free buffers for queuing cells, the node must discard newly arriving cells. For packet data traffic, when a cell is discarded, the packet from which the discarded cell came will be retransmitted, perhaps many times, further aggravating the congestion. A difference exists between congestion control and flow control. Congestion control relates to insuring that each part of the network is able to carry the offered traffic. Congestion control is a network-wide consideration involving the behavior and carrying capacity of each part of the network at the time that traffic is offered to each part of the network. Flow control, in contrast, relates to the point-to-point traffic between a given source and a given destination. Flow control insures that a source does not continually transmit data faster than the destination can receive it. Flow control generally involves direct feedback from the destination to the source to signal the source as to the availability of the destination to receive transmissions from the source. Packet Congestion Control Algorithms Congestion control algorithms for packet switches have included preallocating resources, packet discarding, packet restricting, flow control, and input choking. The preallocating of resources avoids a congestion problem for virtual channels. When a virtual channel is set up, a call request travels through the network making table entries at each node that control the route to be followed by subsequent traffic. With preallocating, each call request reserves one or more data buffers in each node unless all the buffers are already reserved. If all buffers are reserved, another route is found or a "busy signal" is returned to the source. If buffers are reserved for each virtual channel in each node, there is always a place to store any incoming packet to that node. The problem with preallocation is that substantial buffer resources are allocated to specific virtual channel connections, whether or not there is any traffic over the virtual channel. An inefficient use of resources results because resources not being used by the connection to which they are allocated are nevertheless unavailable to other virtual channels. With packet discarding, if a packet arrives at a node and there is no place to store it, the node discards it. Congestion is resolved by discarding packets at will. A copy of the packet is kept elsewhere and retransmitted later. Discarding packets at will, if carried too far, results in inefficient operation since the retransmission tends to increase traffic in an already congested network. Packet restricting limits the number of packets at any location in a network to avoid congestion since congestion only occurs when there is an excessive number of packets at a particular location in the network. Packet restricting is performed in one method by issuing permits. Whenever a node requests sending a packet, the node must first obtain a permit. When the destination finally receives the packet, the permit is again made available for reuse. Although the permit method guarantees that the network as a whole will never become congested, it does not guarantee that a given node will not become swamped with packets. Also, the permit distribution mechanism is difficult to implement without suffering long delays. Flow control has been used in some networks (for example, ARPANET) in an attempt to eliminate isolated congestion. For example, flow control has been used by the transport layer to keep one host from saturating another host and by one node to prevent that node from saturating its neighbor node. However, flow control has not been effective to solve network-wide congestion. Input choking has been used to control congestion. Whenever congestion is detected, a choke packet is sent back to the source to choke off input packets. To determine congestion, each newly arriving packet at a node is checked to see if its output line is congested. When congestion is detected at a node, the node sends a choke packet back to the source identify¬ ing the destination having congestion. When a source receives a choke packet, the source reduces by some factor the traffic sent to the specified destination. Other packets having the same destination that are already under way generate additional choke packets that are ignored by the source for a first time period. After that first time period has expired, the source looks for more choke packets for a second time period. If during the second time period a choke packet arrives indicating that the line is still congested, the source reduces the flow still more and repeats the process. If no choke packets arrive during a subsequent second time period, the source increases the flow again. The feedback in this protocol tends to prevent congestion but does not throttle flow until congestion is detected. Several variations on the input choking algorithm have been proposed for packet switches. In one variation, the nodes maintain two congestion thresholds. Above the first threshold but below the second, choke packets are sent back. Above the second threshold, incoming traffic is discarded, it being assumed by the second threshold that the host has received notification of the congestion. Another input choking variation is to use queue lengths instead of line utilization as the trigger signal for conges¬ tion. Another choking variation has nodes propagate congestion information along with routing information, so that the conges¬ tion trigger is not based on information from only one node, but on information that somewhere along the path there is conges¬ tion. By propagating congestion information in the network, choke packets can be sent at an early time, before too many more packets are under way, thus preventing congestion from building up. The above-identified application entitled METHOD AND APPARATUS FOR REACTIVE CONGESTION CONTROL IN AN ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK discloses a method and apparatus for reactive congestion control in an asynchronous transfer mode (ATM) network where the network is formed by the interconnection of nodes. Each of the nodes includes a forward path for transfer of information from source to destination through the network and a return path for returning explicit congestion control signals. Each source includes a modifiable issue rate unit which issues forward information signals at different rates for virtual channels in response to the presence and absence of congestion signals received on the return path. A variable issue rate unit has an exponential rate for reducing the issue rate in response to receipt of congestion signals. The variable rate source has an exponential increase in the issue rate in the absence of congestion control signals after the issue rate has been reduced. There is a further need for practical components for use in ATM networks that are capable of processing cells for a plurality of virtual channels. SUMMARY OF THE INVENTION The present invention is a method and an apparatus for concurrently processing packets in an asynchronous transfer mode (ATM) network. Packets that are to be transmitted are segmented into a plurality of cells, concurrently for a plurality of channels, and the cells are transmitted over an asynchronous transfer mode (ATM) channel. Cells received from the asysnch- ronous transfer mode (ATM) channel are reassembled into packets concurrently for the plurality of channels. The present invention employs pipelined processing units for segmentation and for reassembly that concurrently process cells for packets for the plurality of channels. A pipelined segmentation unit includes a pipelined segmentation processor, control memory, and data memory where the segmentation unit receives the packet inputs for two or more channels and provides ATM cell outputs concurrently for the two or more channels . A pipelined reassembly unit includes a pipelined reassembly processor, control memory, and data memory where the reassembly unit receives the ATM cell inputs for the two or more channels and provides packet outputs concurrently for the two or more channels. The pipelined segmentation unit includes a control memory storing two-dimensional queues of descriptors. Each descriptor stores information about a single packet for use in segmentation or reassembly. First dimension rate queues are provided for queueing descriptors for packets of different channels having cells to be transmitted at the same peak rate. Second dimension channel queues are provided with one channel queue for each channel having a descriptor in the rate queue. Each channel queue queues descriptors for packets of the same channel. Each channel queue is associated with one channel. A plurality of rate queues are provided, one for each transmission rate. Each rate queue is a linked list of descriptors, each descriptor in the rate queue identifies a packet from a different one of the channels having cells to be transmitted at the rate for the particular rate queue. The linked list of descriptors for the rate queue identifies a different packet for each of the channels having a cell to be transmitted at the rate for the particular rate queue. A plurality of channel queues are provided, one for each channel having a descriptor in a rate queue. Each channel queue is a linked list of descriptors, each descriptor identifying a packet to be transmitted, for an associated one of the channels, where the linked list of descriptors for the channel queue identifies all the packets, for the associated one of the channels, to be transmitted. The present invention employs average rate metering in combination with reactive rate control. The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a block diagram of communication system including a source communication unit connected by an ATM network to a destination communication unit. FIG. 2 depicts a block diagram of the FIG. 1 system in which the source includes a segmentation unit and the destination includes a reassembly unit. FIG. 3 depicts a schematic block diagram of a plurality of source/destination (S/D) users connected through a multinode ATM networ . FIG. 4 depicts a schematic representation of a circuit with one S/D user connected to another S/D user through a sequence of nodes in the network of FIG. 3. FIG. 5 depicts a schematic representation of the FIG. 4 circuit with a virtual channel connection of the source (S) sending information in a forward direction (F) to a destination (D) and with a reverse direction (R) for transmitting control signals to the source (S) . FIG. 6 depicts a schematic representation of a typical one of the nodes (N) in the FIG. 3 network. FIG. 7 depicts further details of one embodiment of the typical node of FIG. 5. FIG. 8 depicts a schematic block diagram of a plurality of source/destination (S/D) users connected through a wide-area multinode network formed of a plurality of local networks . FIG. 9 depicts timing diagrams representative of the operation of a source in response to congestion. FIG. 10 depicts a schematic block diagram of the source of FIG. 1. FIG. 11 depicts a schematic block diagram of the destination of FIG. 1. FIG. 12 depicts a representation of the two-dimensional rate queues used in the segmentation unit in the source of FIG. 10. FIG. 13 depicts a timing diagram representing the pipelining operation of the segmentation unit in the source of FIG. 10. FIG. 14 depicts a timing diagram representing the pipelining operation of the reassembly unit in the destination of FIG. 11. FIG. 15 depicts timing diagrams representative of the operation of a network with the segmentation unit in the source of FIG. 9 and the reassembly unit in the destination of FIG. 11. FIG. 16 depicts a timing diagram representing the cell clock for the segmentation unit of FIG. 10. FIG. 17 depicts a timing diagram representing the Data_Req- uest_Transmit (DRT) queue for the segmentation processing unit of FIG. 10. FIG. 18 depicts a timing diagram representing the TIQ signal from the TI counter. FIG. 19 depicts a timing diagram representing the Cell_Ctr signal for the segmentation unit of FIG. 10. FIG. 20 depicts a timing diagram representing the Data- transmit signal for the segmentation processing unit of FIG. 10. DESCRIPTION OF THE PREFERRED EMBODIMENTS Source/Destination ATM System - FIGS. 1 and 2 In FIG. 1, a source communication unit 4-S transmits cells over an asynchronous transfer mode (ATM) network 1 to a destina¬ tion communication unit 4-D. The geographical area of ATM network 1 can extend between local hosts (backplane connection) , can be a local-area network (LAN) , a wide-area network (WAN) and, in general, can extend to any size ATM network. In FIG. 1, the source communication unit 4-S and the destination communication unit 4-D are typical of the many sources and destinations that commiunicate through ATM network 1. In FIG. 1, sources and destinations are typically organized in pairs and S such pairs are designated as sources/destinations (S/D) 4-1, ... , 4-(S-l). In FIG. 2, further details of the source 4-S and destination 4-D of FIG. 1 are shown that are typical of the sources/des¬ tinations (S/D) 4-1, ..., 4-(S-l) of FIG. 1. In FIG. 2, the source and destination communication units each include a host unit (101 and 101'), a cell unit (103 and 103') and common memory (102 and 102'). In the source 4-S, the cell unit (103) is a segmentation processing unit for segmenting packets for transmission on ATM path 108 over an asysnchronous transfer mode (ATM) network 1 to ATM path 109 to destination 4-D. Packets from the host to be transmitted are segmented into a plurality of cells concurrently for a plurality of channels and the cells are transmitted over the asysnchronous transfer mode (ATM) network 1. Cells received from the asysnchronous transfer mode (ATM) network 1 are reassembled concurrently for the plurality of channels in the destination 4-D by the cell unit 103'. In the destination, the cell unit 103' is a reassembly processing unit that reassembles the packets concurrently for the plurality of channels. The cell units 103 and 103' are pipelined processing units for segmentation and for reassembly, respectively, of packets. In FIG. 2, the source 4-S includes a host unit 101, a common memory 102, and a cell unit 103. The common memory 102, in a preferred embodiment, is a dual ported memory having a port for the host unit 101 and having a port for the cell unit 103. The host unit 101 includes a host memory .interface 106, for interfacing to one of the ports of memory 102. Similarly cell unit 103 includes a cell unit memory interface 107 for interfac¬ ing to the other one of the dual ports of the dual port memory 102. The dual ported memory 102 of the source 4-S of FIG. 1 allows packet information from the host unit 101 to be stored into the common memory 102. The cell unit 103 retrieves the packet information from the common memory 102, segments the packets into cells, and transmits the cells over the ATM path 108 to the ATM network 1 over the ATM path 109 to the destina¬ tion 4-D. In FIG. 2, the destination 4-D includes a host unit 101', a common memory 102', and a cell unit 103'. In a preferred embodiment, the common memory 102' is a dual ported memory which connects through one port to the host unit 101' and through the other port to the cell unit 103'. The host unit 101' includes a host memory interface 106' and the cell unit 103' includes a cell unit memory interface 107'. The cell unit 103' receives the cells from the segmented packets on the ATM path 109 and reassembles those cells into packets for a plurality of channels. The cell unit 103' deposits the cells into the common memory 102' where they become available to the host unit 101' as packets for a plurality of channels. In FIG. 2, the common memory 102 is partitioned into a control memory 81 and a packet memory 83. Similarly, the control memory 102' is partitioned into a control memory 81' and a packet memory 83'. In a preferred embodiement, each of the control memories 81 and 81' is a separate dual ported memory and each of the packet memories 83 and 83' is also a separate dual ported memory. The cell unit memory interface 107, therefore, includes a cell unit control memory interface 82 which connects the cell unit to the control memory 81 and includes a cell unit packet memory interface 84 which connects the cell unit 103 to the packet memory 83. The cell unit 103 also includes a cell interface 126 which connects the cell unit 103 to the ATM path 108. In the destination 4-D, the cell unit 103' includes a cell interface 126' for receiving over the ATM path 109 cell data from the source 4-S. The cell unit 103' includes a cell unit control memory interface 82' which connects cell unit 103' to the control memory 81' in the common memory 102' . Also, the cell unit 103' includes a cell unit packet memory interface 84' for connecting the cell unit 103' to the packet memory 83' of the common memory 102'. In FIG. 2, each of the cell processing units 103 and 103' includes four interfaces. Namely, processing unit 103 includes the host interface 127, control memory interface 82, the packet memory interface 84, and the cell interface 126. Similarly, the control unit 103' includes the four interfaces, namely the host interface 127', the control memory interface 82', the packet memory interface 84', and the cell interface 126' . In accordance with one preferred embodiment of the present invention, each of the cell units 103 and 103' is a pipelined processing unit which operates to present information concur¬ rently at each of the four interfaces (host interfaces 127 and 127', control memory interfaces 82 and 82', packet memory interfaces 84 and 84', cell interfaces 126 and 126'). In addition to the segmentation and reassembly processing of the FIG. 2 cell units, the source 4-S typically includes variable issue rate means which varies the rate at which cells are issued to the ATM network 1. In one preferred embodiment, the issue rate is controlled within the source 4-S in accordance with reactive congestion signals received from the ATM network 1 as described in connec¬ tion with the above-identified application METHOD AND APPARATUS FOR REACTIVE CONGESTION CONTROL IN AN ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK. Overall Network - FIG. 3 In FIG. 3, a plurality of network users are represented as the source/destination (S/D) 4. Each user typically sends information as a source (S) and receives information as a destination (D) . The source (S) of an S/D unit 4 will send information to the destination (D) of some other S/D unit 4. In order for information to be transferred from a source to a destination, each S/D unit 4 connects through a multinode (N) network 1. The network 1 includes many nodes (N) 5. The nodes are connected from node to node so that, in general, any particular one of the S/D units 4 can connect to any one of the other S/D units 4 by forming a virtual channel connection across a chain of nodes 5 in the network 1. In general, the links between the S/D units 4 and a node 5, and the links between nodes 5, are by bi-directional links 8 which enable information to be transferred in both directions. In FIG. 3, the number of nodes (N) 5 shown is for clarity a relatively small number, but the network may include hundreds or more nodes. Also, the S/D units 4 include the S users 4- 0, 4-1, 4-2, 4-3, 4-4, ..., 4-(S-2), 4-(S-l). The value of S can be any integer where S is typically equal to hundreds or higher. In a typical embodiment, the FIG. 3 communication system is an ATM network in which the unit of transfer of information is a cell. A plurality of cells form packets of information. The network 1 communicates cells and packets so as to support different types of information including images, voice and data. Virtual Channel - FIG. 4 In FIG. 4, the S/D unit 4-x connects through a plurality C of nodes (N) 5-0, 5-1, ..., 5-(C-l) to the S/D unit 4-y. In FIG. 4, the S/D unit 4-x is typical of any of the S/D units 4 of FIG. 3. For example, the S/D unit 4-x may represent the S/D unit 4-2 in FIG. 3. Similarly, the S/D unit 4-y in FIG. 4 may represent any of the S/D units 4 in FIG. 3. For example, S/D unit 4-y may represent the S/D unit 4-4 in FIG. 4. In such an example, the nodes 5-0, 5-1, ..., 5-(C-l) represent the C nodes in the network 1 of FIG. 3 which are used to connect the S/D unit 4-2 to the S/D unit 4-4. In FIG. 4, the bi-directional links 8-0, 8-1, ..., 8-(C-l), 8-(C) connect from the S/D unit 4-x through the nodes 5-0, 5-1, ..., 5-(C-l) to the S/D unit 4-y. In FIG. 4, information may be transferred from the source (S) in the S/D unit 4-x to the destination (D) in the S/D unit 4-y. Similarly, information from the source (S) in the S/D unit 4-y can be transferred to the destination (D) in the S/D unit 4-x. While information may be transferred in either direction in FIG. 4, it is convenient, for purposes of explanation to consider transfers between a source (S) and a destination (D) whether that be from the S/D unit 4-x to the S/D unit 4-y or from the S/D unit 4-y to the S/D unit 4-x. Regardless of the direction, each transfer is from a source (S) to a destination (D). S to D Transfers - FIG. 5 In FIG. 5, a schematic representation for a source (S) to destination (D) transfer in the virtual channel of FIG. 4 is shown. In FIG. 5, the source unit 4-(S) in the S/D unit 4-x of FIG. 4 connects to the destination unit 4-(D) in the S/D unit 4-y of FIG. 4. In FIG. 5, each of the links 8-0, 8-1, ..., 8-(C-l), 8-(C) includes a forward (F) channel for transferring information in the forward direction and a reverse (R) channel for transferring information in the reverse direction. The reverse channel in FIG. 5 is associated with the transfer of information from the source unit 4-(S) to the destination unit 4-(D). The reverse channel in FIG. 5 is for the purpose of sending control informa¬ tion used in connection with congestion control within the network of FIG. 4. The reverse channel (R) is distinguished from the forward channel (F) used for the transfer of informa¬ tion in the forward direction from S/D unit 4-y to S/D unit 4-x, as discussed in connection with FIG. 4. Both the forward (F) and the reverse (R) channels are associated with the source unit 4-(S) transfer to the destination unit 4-(D) . Each of the nodes in FIG. 5 includes forward (F) circuitry 6 and reverse (R) circuitry 7. In FIG. 5, the forward channels 8-OF, 8-1F, ..., 8-(C-l)F connect as inputs respectively to the forward circuits 6-0, 6-1, ..., 6-(C-l). The forward channel 8-(C)F connects from the forward circuit 6-(C-l) to the D unit 4-(D) . Similar¬ ly, the reverse channels 8-OR, 8-1R, ..., 8-(C-l)R connect from the reverse circuits 7-0, 7-1, ..., 7-(C-l). The reverse channel 8-(C)R connects from the D unit 4-(D) to the reverse circuit 7-(C-l) . In FIG. 5, each of the nodes 5 has a feedback connection 9 connecting from the forward (F) circuit 6 to the reverse (R) circuit 7. Specifically, the feedback channels 9-0, 9-1, ..., 9-(C-l) connect from the forward (F) circuits 6 to the reverse (R) circuits 7 in the nodes 5-0, 5-1, ..., 5-(C-l), respective¬ ly. In the FI.G 5 circuit, a virtual channel connection is made along the forward channel setting up a communication path in the forward direction between the S unit 4-(S) and the D unit 4-(D) . Because other virtual channels are also established in the network 1 of FIG. 3, congestion may arise at any node or destination including the nodes of FIG. 5. The feedback channels 9 are utilized to send back an explicit congestion signal using the reverse (R) channels 8-0.R, 8-1R, . . . 8-(C- 1)R, 8-(C)R and reverse circuits 7. When the source (S) unit 4-(S) receives an explicit congestion signal on the reverse channel 8-0R, source unit 4-(S) takes corrective action to reduce the congestion in the network. Specifically, in accordance with the present invention, source unit 4-(S) reduces the rate at which data is inserted over the forward channel through channel 8-0F from the assigned rate (Maximum Channel Peak Cell Rate) to some lower rate (Current Channel Peak Cell Rate) . After a time period such that congestion is likely to have cleared, the source unit restores the insertion rate of information in the forward channel over the link 8-OF to its original maximum rate. Since the FIG. 5 virtual channel is typical of all of the virtual channels established in the network of FIG. 3, the combined operation of all the virtual channels in an ATM system is to dynamically control the insertion rate of input informa¬ tion, and specifically to reduce the insertion rate in the presence of congestion in the network and to restore the insertion rate in the absence of congestion in the network. Each virtual channel, like the FIG. 4 virtual channel, functions with a feedback control for controlling the insertion rate of information into the network. In order for the feedback control in FIG. 5 to have a good response time, the delay in time from the detection of congestion until the source unit takes corrective action should be small. In general, the feedback delay value has two basic components . The first component of delay is the circuit path delay for each node to node transfer required from the point of congestion back to the source. The second component of the delay is the signal processing time required in each node including generation of the congestion signal in each reverse circuit 7 in each node in order to transmit the explicit congestion signal through the node. The total feedback delay is, therefore, the sum of the node-to-node reverse signal transfer times and the sum of the reverse signal processing times. For any given system, the reverse signal transfer time from node to node is not readily changed and is substantially fixed for any particular system. The present invention causes the reverse signal processing time to be much less than the reverse signal transfer time. Therefore, substantially all of the feedback delay is a result of the reverse signal transfer time and the feedback processing time is small or negligible. Single Node Embodiment - FIG. 6 In FIG. 6, one typical embodiment of a node having the feedback control reverse signal paths of FIG. 5 is shown. In FIG. 6, the node 5 includes N links 18-0, 18-1, ..., 18-n, ..., lδ-(N-l). Each of the links 18 of FIG. 6 are analogous to the bi-directional links 8 of FIG. 4. In FIG. 6, the links 18-0, 18-1, ..., 18-n, ..., 18-(N-1) connect to port controllers 11-0, 11-1, ..., 11-n, ..., ll-(N-l). The node of FIG. 6 is used in connection with the information transfer of FIG. 4, for example, by having one of the links 18, for example, input link 18-0 in FIG. 6, connect through switch fabric 10 to another one of the links 18, for example, link 18-n. In the example described, the switch fabric 10 functions to connect the link 18-0 to the link 18-n. In an example where the node of FIG. 6 represents the node 5-1 in FIG. 4, the link 8-1 in FIG. 4 is the link 18-0 in FIG. 6 and the link 8-2 in FIG. 4 is the link 18-n in FIG. 6. With such a connection, the node of FIG. 6 connects information in' one direction, for example, from link 18-0 to link 18-n, and connects information in the opposite direction from the link 18-n to the link 18-0. The links 18-0 and 18-n were arbitrarily selected for purposes of explanation. Any of the N links 18 might have been selected in the FIG. 4 circuit for connection to any of the other links 18. When the node of FIG. 6 is used in the virtual channel connection of FIG. 4 with the source (S) on the left and the destination (D) on the right, then for purposes of explanation it is assumed that the link 18-0 is an input to the node 5 in the forward direction and the link 18-n is output from the node in the forward direction. In FIG. 6, port controllers (PC) 11-0, 11-1, ..., 11-n, ..., ll-(N-l) have input controllers 14-0, 14-1, ..., 14-n, ..., 14-(N-1), respectively and have output controllers (OC) 15-0, 15-1, ..., 15-n, ..., 15-(N-1), respectively. In FIG. 6, forward information cells from the source 4-(S) of FIG. 5 sent to the destination 4-(D) of FIG. 5 connect from the bus 18-01 through the input controller 14-0 to the bus 20-01 through the switch fabric 10 to the bus 20-nI through the output controller 15-n to the bus 18-nO. If congestion is detected at the node 5, then an explicit congestion signal is connected, for example, from the output controller 15-n to the input controller 14-n to the bus 20-nI back through the switch fabric 10 to the bus 20-00 to the output controller 15-0 to the output bus 18-0O. NODE - FIG. 7 In FIG. 7, a more detailed embodiment of the node of FIG. 6 is shown. In FIG. 7, the port controller 11-0 is shown typical of all of the port controllers 11 of FIG. 6. Similarly, the port controller 11-n is typical of all of the port control¬ lers 11 of FIG. 6. In FIG. 7, the port controller 11-n is identical to the port controller 11-0 except that the images in port controller * ll-n are flipped about 180° in order to provide symmetry in the drawing. As indicated in connection with FIG. 6, in the virtual channel of FIG. 4, the controller 11-0 of FIG. 7 serves as an input for forward going cells while the control¬ ler ll-n functions as an output for forward going cells. In FIG. 7, the port controllers 11-0 and ll-n include input controllers (IC) 14-0 and 14-n each having a selector 50, a translator 51 and a reverse signal queue 52. The port control¬ lers 11-0 and ll-n also include an output controller (OC) 15-0 and 15-n each having a selector (SEL) 53, a queue (Q) 54 and a reverse marker (RM) 49. The operation of the FIG. 7 node in connection with the virtual channel of FIG. 4 is as follows. Forward transmitted cells appear on the bus 18-01 input to the selector 50 of the input controller 14-0. Selector 50 normally is set to select the input bus 18-01 unless the reverse queue 52 has congestion control information which must be returned in connection with the operation of some other virtual channel. If the not empty (N-EMT) signal is asserted indicating that congestion informa¬ tion is stored in the queue 52, selector 50 selects the output from queue 52 but otherwise selects the forward cells on bus 18-01. The translator 51 for each cell translates the value of the incoming virtual channel identifier (VCI) for the cell to an outgoing VCI for the cell, directs the cell to an outgoing link, and marks the priority of the cell. For example, the translator is implemented as a table storing values where the table is addressed by the incoming VCI. The cell information together with the translated VCI appear on the bus 20-nO to the selector 53 in the output controller 15-n. Selector 53 normally selects the bus 20-n© for connection to the queue 54. If queue 54 is filled beyond a threshold as indicated by the Ql signal selector 53 copies the VCI and control information to the queue 52 through the reverse marker unit 49. Reverse marker unit 49 marks the VCI label with a reverse signal indication so that reverse signals can be distinguished from forward signals. The threshold signal Ql indicating the fullness of queue 54 is a congestion signal that is transmitted back to the source 4-(S) of FIG. 5. If queue 52 has any information stored, it issues the N-EMT signal indicating a not empty condition to the selector 50 in the input controller 14-n. Selector 50 connects its output to the translator 51. Translator 51 translates the return signal VCI back to the original value (which appeared on the input bus 18-01) so that switch fabric 10 receives the return path congestion signal on the bus 20-00 input to the selector 53. Selector 53, assuming that the queue 54 is hot full, connects the return signal to the queue 54 for output on the return bus 18-00. Accordingly, the translator 51 in the input controller 14-n reverses the translation done in the translator 51 in the input controller 14-0. Wide-Area Network Formed By Plural Local Networks - FIG. 8 In FIG. 8, a wide-area communication system employing networks of the FIG. 3 type is shown. The FIG. 8 system is comprised of a group of generally local communication systems including the networks 1-0, 1-1, ..., l-(L-l). Each of the local networks of FIG. 7 includes source and destination units of the type previously described in connection with the FIG. 3 network. Specifically, local communication systems are formed by the local network 1-0 together with the local source/des¬ tination (S/D) units 4(0,0), ..., 4(0,S 0 -1), the local network 1-1 together with the local the S/D units 4(1,0), ..., 4- (l^-l), and the local network 1-2 together with the local S/D units 4(2,0), ..., 4(2,S 2 -1) and the local network l-(L-i) together with the local the S/D units 4(L-1,0), ..., 4(L-1, S w -1). In FIG. 8, the wide-area system includes a wide-area source 4-0 connected to local network 1-0 and a wide-area destination 4'-(L-l) connected to local network l-(L-l). In FIG. 8, the local networks 1 are connected together by links 8 and specifically link 8(0/1) connects local networks 1-0 and 1-1, link 8(1,2) connects local networks 1-1 and 1-2 and so on such that local network l-(L-l) is connected through links 8 and local networks to local network 1-0. In this manner, wide-area source 4-0 is connected to wide-area destination 4'-(L-l). The wide-area S/D units 4-0 and 4'-(L-l) are typical of many such units which, for clarity, are not shown in FIG. 8. In FIG. 8, the links 8(0,1), 8(1,2), 8(2,_), ..., 8(_,L-1) between local networks are the same as the links 8 between local S/D units except that they are typically longer in length. In FIG. 8, a plurality of virtual channels are established between wide-area S/D units and local S/D units. Accordingly, a virtual channel is established, for example, between S/D unit 4-0 and S/D unit 4'-(L-l). The operation of the FIG. 8 network is described in connection with FIG. 9 in which it is assumed that the cell transmission interval (CTI) is short. This short cell transi¬ tion interval is evident since the transmitted cell at XR 1 3 results in a congestion signal, Cong_Signal 1 at a time XR_,3+, only a short time after the cell is transmitted. Accordingly, the forward transmission of the cell at XR^ originated (with reference to FIG. 5) at the source 4-(S) and is transmitted into the network along the virtual channel (FIG. 4) possibly as far as the node 5-(C-l) or the destination 4(D). When conges¬ tion is encountered, a return cell is transmitted along the return path 8-R (FIG. 5) so as to arrive back at the source 4-(S) in a fraction of a Channel Cell Interval (CCI). In FIG. 9, for virtual channel 1, the CCI interval is the interval between each Xmit_Rate 1 time, for example, between XR.,0 and XR 1 1. Accordingly, the reactive control operation in reducing the transmission rate in the FIG. 9 example is very fast. In FIG. 9, the return transmission interval for a congestion signal returning from a congested node to the source is short and in particular is less than a single CCI as measured from the time that the original cell is transmitted from the source in the forward direction. The return transmission interval, therefore, includes both the forward path delay (from the source to the node having congestion) and the return path delay (from the node having congestion back to the source) . Also included within the return transmission interval is the delay resulting from the return cell processing time required for converting forward cells to return cells and processing the return cell ' s. While the FIG. 9 example has a return transmission interval of less than one CCI, return transmission intervals of less than approximately 10 CCI are still considered short so that the issue rate unit can reactively modify the transmission rate and thereby reduce congestion. In order to keep the return transmission interval short, the return cell processing time must also be kept short and is desireable much less than the return transmission interval. In the FIG. 8 system, it is contemplated that the distance between the local network 1-0, for example, and the local network l-(L-l) may be very far so that the delay time that may be encountered by a source 4-0 associated with network 1-0 in cell transmissions to a destination, for example, 4'- (L-l) associated with a network l-(L-l) may be much longer than a Channel Cell Interval. The longer the transmission time from a source to a destination and the return time from the destina¬ tion back to the source, the less effective becomes the reactive control mechanism. If all communications in a very long network are from the source at one end of the network to a destination at the far end of the network, then the effectiveness of reactive control for very long distance networks is reduced. However, experience "indicates that a large percentage (for example, 80%) of data traffic in a large network tends to be local and not the full long distance of the network. For example, if the traffic for the network ' 1-0 between the S/D units 4(0,0), ..., 4(0,S 0 -1) is principally local, then the reactive control mechanism is effective for controlling the congestion by controlling the transmission issue rate of the local sources for the network 1-0. Similarly, for each of the other local networks such as networks 1-1 and 1-2 of FIG. 8, the local traffic in each of those networks is controlled by controlling the issue rate and the sources for local traffic in those networks. Since the entire network of FIG. 8 is composed of groups of local networks and each local network is effective to control congestion by controlling the local traffic issue rates, congestion is effectively controlled for the entire network of FIG. 8, The issue rates in sources are controlled by variable rate units in each source. In FIG. 8, each source (like source 4-S in FIG. 2) in the S/D units 4 typically includes a variable rate unit. A typical variable rate unit (VRU) is described in greater* detail in the above-identified application entitled METHOD AND APPARATUS FOR REACTIVE CONGESTION CONTROL IN AN ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK. In the present specification, the variable rate unit is included within the segmentation unit 103 of FIG. 2 which is described hereinafter in further detail in connection with FIG. 10. When congestion is present in the network of FIG. 8, a congestion signal (for example, on reverse path 8-0 of FIG. 5 for a typical virtual channel) is received in a return cell by a reassembly unit (like reassembly unit 103' in FIG. 2 and FIG 11). The return cell has a return indicator for indicating congestion on the virtual channel. The reassembly unit detects the congestion and indicates the presence of that congestion in a return cell. The return cell causes a rate control signal to be output to rate control output 87' in a reassembly unit (see FIG. 11). The rate control output 87' inturn causes a rate control input to rate control input unit 87 of a corresponding segmentation unit (see FIG. 10) . The rate control input (unit 87 in FIG. 10) provides the rate control input signal to a control unit in the segmentation unit control unit 116 in FIG 10). The rate control signal includes a pointer for pointing to a virtual channel identifier, Cong_Signal_VCI, which identifies the virtual channel which has experienced congestion. The variable rate unit as part of the segmentation unit 1O3 of FIG. 2 includes a packet memory 83 and a direct memory access (DMA) control 84. During normal operation, the DMA control 84 obtains cells from the packets in packet memory 83 and outputs those cells to the cell buffer 86 for transmission in the forward direction on the forward link from buffer 86 (the forward link corresponds to link 8-OF in FIG. 5). The output rate on the forward link is the rate from the from the DMA controller 84 and that rate will normally be at the maximum cell rate for each virtual channel in the absence of a return cell indicating congestion received back on the return link (the return link corresponds to the link 8-0R in FIG. 5). The variable rate unit also utilizes the control memory 81 and a control memory interface 82 of FIG. 2. Control memory 81 stores control information about each virtual channel that is established to send information from packet memory 83 to the output channel (for example, link 8-0F in FIG. 5). The control information stored for each channel includes a congestion level value, Cong_Level, indicating the level of the reduced rate of transmission due to congestion on the virtual channel. The control information stored for each channel includes a recovery rate value, RC_Mode, indicating the rate of recovery of transmission rate after the rate has been reduced due to congestion on the virtual channel. The control information stored for each channel includes a counter field, Recovery_- Count, for counting cells during congestion periods and a control field, RC_Inhibit, for controlling changes in rate during congestion periods. Upon receipt of a congestion signal, the control rate for the virtual channel is modified along with the transmission rate used for that particular channel. After the congestion signals no longer exist for a particular virtual channel, the rate of transmitting the information for the virtual channel which was previously experiencing congestion is modified. The apparatus for and the methods of operation of source units having packet memories and DMA controllers are described in greater detail in the above-identi ied application entitled METHOD AND APPARATUS FOR REACTIVE CONGESTION CONTROL IN AN ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK. The operation of such sources is explained with reference to a number of terms. Terms For Automatic Rate Control Algorithm "Virt_Chan" identifies one of a number of virtual channels, where each virtual channel transmits ATM cells at a selected one of a number of Xmit_Rate rates unless, in response to an explicit congestion signal for that virtual channel, the transmission rate is modified by a congestion rate modification value, Cong_Level. "Rate_Queue" is a list of virtual channel identifiers that identify virtual channels that are to be transmitted at a particular rate. "Xmit Rate" defines a number of transmission rates where each Xmit_Rate is the rate to transmit cells used by all of the virtual channels in a Rate_Queue. "Xcount" defines a number of 4-bit counts, one for each Rate_Queue, where each Xcount for the corresponding Rate_Queue is incremented to count the number of cell transmission opportunities at the full Xmit_Rate rate for that corresponding Rate_Queue. "Xmit_Time" defines a number of state bits, one for each Rate_Queue, where each Xmit_Time state bit indicates when it is time to service the corresponding Rate_Queue. Each Xmit_Time state bit is set to the active state each time the Xcount is incremented for the corresponding Rate_Queue. "Cong_Level" defines a number of 3-bit congestion level values, one for each virtual channel, where each value for the corresponding virtual channel is used to reduce the transmission rate of that corresponding virtual channel below the normal non-reduced Rate_Queue rate. "RC_Mode" defines a number of 3-bit exponents, one for each virtual channel, where each exponent for the corresponding virtual channel is used to control the rate of restoring the transmission rate of that corresponding virtual channel back to the normal Rate_Queue rate after the transmission rate of that virtual channel has been reduced because of congestion. The rate of restoring is determined by a- Recovery__Value = 2 RC - Mode . "RC_Inhibit" defines a number of state bits, one for each virtual channel, where each RC_Inhibit state bit for the corresponding virtual channel is used to inhibit changes in Cong_Level during a period existing after a change in Cong__Level for that corresponding virtual channel and before a cell has been transmitted over that corresponding virtual channel. "Recovery_Count" defines a number of 4-bit count values, one for each virtual channel, where each Recovery_Count value for the corresponding virtual channel is used for counting trans- mitted cells for that corresponding virtual channel as measured from the time that the last Cong_Signal was detected for that virtual channel. Recovery_Count is compared with Recovery_Value for the corresponding virtual channel to control restoring the transmission rate of cells for that corresponding virtual channel. When Recovery_Count equals Recovery__Value for the corresponding virtual channel, Cong_Level is decremented to thereby increase the transmission rate for the corresponding virtual channel. "Cong_Signal" indicates the presence of one or more Cong_Signal_VCI identifiers stored in a queue for processing where the presence of Cong_Signal is used to trigger the decrementing of the transmission rate of cells for the virtual channels identified by the Cong_Signal_VCI identifiers in the queue. "Cong_Signal_VCI" are virtual channel identifiers, one for each virtual channel on which a cell has been returned to indicate congestion. "Pkt_Loss_Signal" indicates the presence of one or more Pkt_Loss_VCI identifiers stored in a queue for processing where the presence of Pkt_Loss_Signal is used to trigger the dec¬ rementing of the transmission rate of cells for the virtual channels identified by the Pkt_Loss_VCI identifiers in the queue. "Pkt__Loss_VCI" are virtual channel identifiers, one for each virtual channel on which the loss of cells has occurred and has been interpreted as an indication of congestion. The variable rate unit within each source like source 4-S of FIG. 2 (explained in greater detail hereinafter in connec¬ tion with FIG. 10) uses a counter which is clocked to provide timing. The clock signals establish different transmission rates, Xmit_Rate, one for each Rate_Queue, for transmitting cells over the virtual channels in that Rate_Queue. A number of different rates can be established and in one embodiment, Q rates Xmit_Rate 0 , Xmi^Rate,, ..., Xmit_Rate Q .. | are established from counter 88. Each one of the Q Xmit_Rates is associated with a 4-bit Xcount which is incremented as a counter by the corresponding Xmit_Rate. Accordingly, the Xcount 0 , Xcount,, ..., Xcount Q. , counts are incremented by Xmit_Rate 0 , Xmit_Rate.,, ..., X i^Rate^ rates, respectively. Each of the Q Xmit_Rates is associated with a corresponding queue, Rate_Queue, for storing virtual channel identifiers that identify virtual channels that have cells to be transmitted at the Xmit_Rate of the corresponding Rate_Queue. Accordingly, for uncontested normal operation, the virtual channels having identifiers stored in the Rate_Queue 0 , Rate_Queue,, ..., Rate_- Queuβ Q. , queues are serviced for transmitting cells over virtual channels at the Xmit_Rate 0 , Xmit_Rate.,, ..., rates, respectively. Each of the Q Xmit_Rates and the corresponding Q Rate_Queues is associated with a state bit, Xmit_Time, for indicating when it is time to service the Rate_Queue. Accordingly, for uncontested normal operation, the Rate_Queue 0 , Rate_Queue 17 ... , Rate_Queue Q.1 queues are serviced whenever the corresponding Xmit_Time 0 , Xmit_Time. | , ..., Xmit^ime Q ., state bits are set, respectively. Each Xmit_Time state bit is set to the active state each time the Xcount is incremented for the corresponding Rate_Queue. The variable rate unit is constructed with conventional logic circuits which implement an automatic rate control algorithm. Although the logical functions can also be performed by programed processors, such programmed processors are generally too slow for high speed operations required for ATM systems. The logic for the variable rate unit is included within the following TABLE 1-1 and TABLE 1-2. TABLE 1-1 defines the parameter values for the automatic rate control algorithm. TABLE 1-2 defines the automatic rate control algorithm using pseudo code. The operation of the variable rate unit is further described in connection with FIG. 9. The times when Xmit_ rime., are active for Xmi^Rate, are shown in FIG. 9 as times XR,0, XR,1, XR,2, XR ~j 3, and so on. For purposes of explanation, it was assumed that after transmitting cells by virtual channel 1 with Xmi^C ll, at XR,0, XR-,1, XR-.2, and XR,3, an explicit congestion signal Cong_Signal 1 was returned at XR 1 3+ so that no cell was transmitted at XR,4 due to a decrease in the transmission rate. The operation continues thereafter in FIG. 9 both to further decrease the transmission rate and to thereafter recover the rate when congestion stops after XR 1 9+. FIG. 9 also depicts another virtual channel transmitting at another rate, Xmit_Rate 2 , which is at one- half the rate of Xmit_Rate t . One congestion signal, Cong_Signal 2 is received at XIR- j l-i- causing the cell transmission of Xmit_Cell 2 to be at one half the Xmit_Rate 2 rate. For clarity, recovery has been assumed to be disabled (RC_Mode = 101 - Disable_Recovery) for this virtual channel. In FIG. 9, the ATM_Out line represents the sum of the Xmit^Cell, and the Xmit_Cell 2 lines and is the output from the variable rate generator. It will be apparent from FIG. 9 that the variable rate unit decreases the issue rate (for example, Xmit CelL, rate) exponen¬ tially in response to a congestion signal. The PROCEDURE Rate Adjust is a means for decreasing the issue rate exponentially. Similarly, the Xmit Rate Recovery Routine is a means for increasing the issue rate exponentially in response to the absence of a congestion signal. The rate of increasing the transmission rate, after it has been decreased in response to congestion, is less than the original rate used to decrease the transmission rate in response to congestion. Making the increasing and decreasing rates different tends to avoid oscillation in the transmission rate and improve the reactive control. The overall operation of an ATM network, using variable rate sources of the type described, is characterized using the following terms. "Bit" is a binary unit of information. "Byte" is a fixed number of bits, typically 8 bits. "Packet" is a communication message formed of bytes, typically of variable length from 40 to 10,000 bytes. "Cell" is a fixed length communication message formed of bytes, typically 53 bytes (5 byte header/48 byte data). "Bit Rate" (BiR) is rate at which a communication system transmits bits. "Byte Rate" (ByR) is rate at which a communication system transmits bytes. "Cell rate" (CR) is rate at which a communication system transmits cells. "Cell Interval" (CI) is period from one cell to the next cell. "Channel Cell Interval" (CCI) is the cell interval for a virtual channel transmitting at the Channel Peak Cell Rate. "Maximum Channel Peak Cell Rate" (MCPCR) is the cell rate assigned to a particular channel in the absence of congestion. "Current Channel Peak Cell Rate" (CCPCR) is the current cell rate at a particular time for a virtual channel and may equal the Maximum Channel Peak Cell Rate in the absence of congestion and may be less than the Maximum Channel Peak Cell Rate when congestion is present. "Communication Interval" (CI) is a time period in a network, typically measured as a number of cell intervals. "Average Cell Rate" (ACR) is the average number of cells transmitted over a communication interval in a virtual channel. "Cell Transmission Interval" (CTI) is the average period of time for _a cell to travel from one location in a network to another location in the network. "Modification Interval" (MI) is the period of time required to modify a communication parameter. Segmentation Unit - FIG.10 In FIG. 10, the segmentation unit 103, the memory unit 102 and the host 101 are typical for a source such as source 4-S in the communication system of FIG. 1 and FIG. 2. In FIG. 10, the common memory unit 102 includes a control memory 81 and a packet memory 83. The segmentation unit 103 includes a control memory interface (CM IF) 82, a packet memory interface (PM IF) 84, a host interface 127, and a cell interface 126. The cell interface includes an output cell buffer 86 and a rate control input 87. The segmentation unit 103 includes a core processor 128 which includes a logic control unit 117, a register array 114, and a counter 88. The counter 88 is stepped by an external clock 89. The control memory interface 82 connects the core processor 128 with the control memory 81. The control memory interface includes an address generator 113, an address register 110, a control unit 111 and a data register 112. The address generator 113 provides addresses to the address register 110 under control of information from the register array 114. The address from address register 110 addresses the control memory 81 to provide data into the data register 112 from memory 81 or to receive data from the data register 112 for storage in control memory 81. The control 111 connects with the logic control unit 117 for providing control signals to and from the control memory 81. The control unit 111 provides convention¬ al read and write signals to the control memory 81 under control of the logic control unit 117. In FIG. 10, the packet memory interface includes an address generator 123 connected to receive address data from the register array 114 for providing addresses into the address register 120. Address register 120 provides addresses for addressing the packet memory 83 for reading or writing informa¬ tion into or from the packet memory 83 under control of the control unit 121. The control unit 121 provides conventional read and write signals to the packet memory 83 under control of the logic control unit 117. The data register 122 provides data to the input cell buffer 86 for being processed by the cyclically redundancy code unit (CRC) 115. The data for the output cell is stored in the data register 122 from the packet memory 83 or from the constant bit rate (CBR) input 134. The operation of the FIG. 10 source is to provide packetized cells or CBR information to the ATM link as an output to the output cell buffer 86. The header information for each cell in buffer 86 is received from the data register 112. The logic control unit 117 controls the logical operations necessary to , segment the packets in the packet memory 83 into cells for output to buffer 86 or alternatively to output information from the CBR input. The details of the logic control unit 117 in the core processor 128 are shown in the following tables TABLE 1-1 and TABLE 1-2. TABLE 1-2 is a representation of pseudo code that defines, in a conventional manner, circuits in semiconduc¬ tor chip technology. The pseudo code can be directly trans¬ formed into VHDL circuit specifications standardized by the IEEE. TABLE 1-1 Segmentation Processor Terms © COPYRIGHT 1992 Adapative Corporation Preset operation mode (.for entire network) Congestion_Indicator : 0 - Return_Cell /* Congestion indicated by a return cell */ 1 — Packet_Loss /* Congestion indicated by packet loss * */ TIQ : 6-bit value - Time Interval Quota; CQ : 6-bit value - Cell Quota; State variables (in the chip) Current_Descriptor : 13-bit value - The descriptor number that acts as a pointer to the descriptor table. Previous_Descriptor : 13-bit value — Descriptor previous to the Current_Descriptor in the rate queue. This has no meaning if Current Descriptor = Start Desc Num. State variables (for each rate queue) - Start_Desc_Num : 13—bit value — Starting descriptor number of the rate queue. 0 • => no descriptors are queued on the rate queue. TABLE 1-1 Segmentation Processor Terms © COPYRIGHT 1992 Adapative Corporation State variables ( for each virtual channel) Cong_Level: 000 - normal /* Full Rate_Queue Xmit_Rate */ 001 - half /* 1/2 Rate_Queue Xmit_Rate */ 010 - quarter /* 1/4 Rate_Queue Xmit_Rate */ 011 - eighth /* 1/8 Rate_Queue Xmit_Rate */ 100 - sixteenth / * -< 1/16 Rate_Queue Xmit_Rate -•'/ 101 - zero /* no cell transmission */ RC_Inhibit: 0 - Inhibit_Inactive 1 - lnhibit_Active Recovery_Coun : 4-bit count TI_Ctr : 6-bit count - Time Interval Counter; Cell_Ctr : 11-bit count - Cell Counter; Last_Desc_Num : 13-bit value - Last descriptor in the Virt_Chan chain. 0 => no descriptors are queued on this Virt Chan. State variables (for each Descriptor) Virt_Chan : 16-bit value - Virtual Channel the descriptor is associated with. Next_Desc_in_RQ : 13-bit value - Next descriptor in the Rate Queue chain. 0 => This is the last descriptor on the rate queue. Next_Desc_in_VC : 13-bit value - Next descriptor in the Virt_Chan chain. TABLE 1-1 Segmentation Processor Terms © COPYRIGHT 1992 Adapative Corporation . 0 => This is the last descriptor on the Virt_Chan chain. Packet_Address 24-bit value : Address pointer to the Buffer from which the packet is - being segmented. Packet_Length : 16-bit value - Length of the packet in number of cells Residual_CRC : 32— bit value : Contains the running CRC of the packet Incoming Constant Bit Rate (CBR) traffic interface signal CBR_Xmit_S ignal : 0 - No_Cell_Waiting 1 — CBR cell ready for transmission State variables (for CBR traffic) CBR_Chan : 16-bit value - Virtual Channel the CBR cell is associated with. Incoming congestion signals Cong_Signal: 0 - No_Cell_Waiting /* No return cell waiting */ 1 - Cell Waiting /* Return cell waiting for processing */ Cong_Signal_VCI: identifier /* Virtual channel identifier of return cell, typically 10 to 16 bits */ Pkt_Loss_Signal.* 0 - No_Signal_Waiting /* No Pkt_Loss_Signal waiting */ 1 - Signal Waiting /* Packet loss signal waiting for processing •'/ Pkt Loss VCI: TABLE 1-1 Segmentation Processor Terms © COPYRIGHT 1992 Adapative Corporation identifier . /* Virtual channel identifier of Pkt_Loss_Signal , 10 to 16 bits typical*/ Signals from timers (for each Rate_Queue) Xmit_Time: 1 - Active / ■ * *■ Time to service this Rate_Queue */ 0 - Inactive /* Not time to service this Rate_Queue */ X_count: 4-bit count /-•' Count from X-counter */ Communication Queues (In Memory) Packet__Ready_Queue: Circular Queue in memory (of descriptor numbers) loaded by the host to enqueue descriptors for segmentation. Transfer_Comp_Queue: Circular Queue in memory (of descriptor numbers) loaded to enqueue descriptors after the packets have been segmented. TABLE 1-2 Segmentation Processor Logic © COPYRIGHT 1992 Adapative Corporation /* Scheduler */ i-REPEAT •—FOREACH Rate_Queue EIF (Xmit_Time [Rate_Queuel = Active) THEN Service_Rate_Queue (Rate_Queue) ENDIF; i—IF (CBR_Xmit_Signal = Active) /* CBR Transmission*/ l-THEN Xmit_Cell (CBR_Chan) I-ENDIF; Check_Cong_Signal; Liπk_New_Descriptor; "-ENDFOREACH; ■ ENDREPEAT; /* Check for congestion signal waiting for processing */ •—PROCEDURE Check_Cong_Signal; —IF (Congestion_Indicator = Return_Cell) L-E /* Modify identified virtual channel rate upon receiving cong signal */ | —PROCEDURE Rate_Adjust (Virt_Chan) ; READ for Vir _Chan (RC_Mode, RC_Inhibit, Recovery_Count, Cong_Level); AND (RC_Inhibit !=Inhibit_Active) WRITE for Virt_Chan (RC_Inhibit, Recovery_Count, Cong_Level); ENDPROC; TABLE 1-2 Segmentation Processor Logic © COPYRIGHT 1992 Adapative Corporation /* Service each virtual channel in rate queue */ PROCEDURE Service_Rate_Queue (Rate_Queue) ; Current_Descriptor = Start_Desc_Num ; Previous_Descriptor = 0 WHILE (Current_Desc_Num > 0 ) READ for Current_Descriptor (Virt_Chan, ' /* Step RCD */ Next_Desc_in_RQ Next_Desc_in_VC, Packet_Length, Packet_Address, Residual_CRC) ; READ for Virt_Chan (RC_Mode, RC_Inhibit, /* Step RVc */ Recovery_Count , Cong_Level 3 TIQ, CQ, TI_Ctr, Cell_Ctr, Last_Desc_Num) ; /* Average Metering Routine */ /*Step Calc */ /* Xroit Cell Routine */ TABLE 1-2 Segmentation Processor Logic © COPYRIGHT 1992 Adapative Corporation Packet_Address, Residual_CRC); -ENDIF; RC Inhibit := Inhibit Inactive; Λ Xmit Rate Recovery Routine */ /* Step WVc */ WRITE for Virt_Chan (RC_Inhibit, Recovery_Count, Cong_Level, TI_Ctr, Cell_Ctr) ; ENDIF; "-ENDIF; Previous_Descriptor=Current_Descri tor; Current_Descriptor = Next_Desc_in_RQ ; EIF (CBR_Xmit_Signal = Active) /* CBR Transmission */ THEN Xmit_Cell (CBR_Chan) ENDIF; Check_Cong_Signal; L, Link New Descriptor; -ENDWHILE; • ENDPR0C; TABLE 1-2 Segmentation Processor Logic © COPYRIGHT 1992 Adapative Corporation /* Transmission of a cell */ • PROCEDURE Xmit_Cell ; -WHILE (Xmit_Cell_Header = Not_Done) /* Step XCH */ Wait ; -END WHILE; Read for Virt_Chan (CellJHeader) ; /* Step RVH */ Load_Buffer_from_Packet_Memory; /* Step LBPMem -WHILE ((Load_Buffer_from_Packet_Memory = Not_Done) or (Read for Virt_Chan = Not Done)) Wait ; -END WHILE; Cell_Available_for_Transmission; ■ ENDPROC; /* Link new descriptor for transmission */ • PROCEDURE Link_New_Descriptor; • ENDPROC; TABLE 1-2 Segmentation Processor Logic © COPYRIGHT 1992 Adapative Corporation /* De-Linking of a descriptor after transmission has been completed */ —PROCEDURE Delink_Descriptor (Virt_Chan, Current_Descriptor, Next_Desc__in_RQ, Next_Desc_in_VC, Last_Desc_Num, Previous_Descriptor) ; —IF (Current_Descriptor = Start_Desc_Num) -ENDPROC; Reassembly Unit - FIG. 11 In FIG. 11, the reassembly unit 103', the memory unit 102' and the host 101' are typical for a destination such as destination 4-D in the communication system of FIG. 2. In FIG. 11, the common memory unit 102' includes a control memory 81' and a packet memory 83' . The .reassembly unit 103' includes a control memory interface (CM IF) 82', a packet memory interface (PM IF) 84', a host interface 127', and a cell interface 126'. The cell interface includes an input cell buffer 86' and a rate control output 87' . The reassembly unit 103' includes a core processor 128' which includes a logic control unit 117, a register array 114', and a counter 88'. The counter 88' is stepped by an external clock 89'. The control memory interface 82' connects the core processor 128' with the control memory 81'. The control memory interface includes an address generator 113', an address register 110', a control unit 111' and a data register 112' . The address generator 113' provides addresses to the address register 110' under control, of information from the register array 114' . The address from address register 110' addresses the control memory 81' to provide data into the data register 112' from memory 81' or to receive data from the data register 112' for storage in control memory 81'. The control 111' connects with the logic control unit 117 for providing control signals to and from the control memory 81'. The control unit 111' provides conventional read and write signals to the control memory 81' under control of the logic control unit 117. In FIG. 11, the packet memory interface includes an address generator 123' connected to receive address data from the register array 114' for providing addresses into the address register 120'. Address register 120' provides addresses for addressing the packet memory 83' for reading or writing information into or from the packet memory 83' under control of the control unit 121'. The control unit 121' provides conven¬ tional read and-write signals to the packet memory 83' under control of the logic control unit 117. The data register 122' receives data from the input cell buffer 86' after being processed by the cyclically redundancy code unit (CRC) 118. The data from the input cell is stored in the data register 122' for input to the packet memory 83 r - or for output to the constant bit rate (CBR) output 134'. The operation of the FIG. 11 destination is to receive packetized cells or CBR information from the ATM link as an input to the input cell buffer 86' . The header information from each cell in buffer 86' is input to the logic control 117. The logic control unit 117 controls the logical operations necessary to reassemble the cells from buffer 86' into packets in the packet memory 83* " or alternatively to output the cell informa¬ tion on the .CBR output. The details of the logic control unit 117 in the core processor 128 ' are shown in the following tables TABLE 2-1 and TABLE 2-2. TABLE 2-2 is a representation of pseudo code that defines, in a conventional manner, circuits in semiconductor chip technology. The pseudo code can be directly transformed into VHDL circuit specifications standardized by the IEEE. TABLE 2-1 Reassembly Processor Terms /* Reassembly algorithm for pipeline architecture */ Preset Control variables Cell Type : One of the four types of the ATM cell. BOM : Beginning Of Message COM : Continuation Of Message EOM : End Of Message SSM : Single Segment Message Initial_CRC_Value : 32-bit value : Value the CRC checker is initialized to (All 'l's). Virt_Chan : Virtual Circuit Index extracted from the cell header State variables (in the chip) VC_Sel : Virtual Channel range select. Packet_Aging_Timer : Timer used to determine the time interval for checking the state of packet in reassembly. Age_VCI : Index of the Virtual Circuit that is checked for aging packets. State variables (for each cell) Header_VCI : Virtual Circuit Index contained in the Header of the ATM cell. BASize : Buffer Allocation size: This is carried in the BOM/SSM cells & can be used to obtain the correct size buffer. State variables (for each Virt_Chan) Status : Inactive i.e., no packet is being reassembled on this Virt_Chan Active i.e., packet is being reassembled on this Virt_Chan Buffer_Descriptor : 13-bit value - The descriptor number associated with the buffer that the packet is being reassembled in. Packet_Age_Limit : TABLE 2-1 Reassembly Processor Terms The initialization value for Packet_Timeout counter that is used to age packets. State variables (for each Buffer_Descriptor) Residual_CRC . 32-bit value : Contains the running CRC of the packet Packet_Address 24—bit value : Address pointer to the Buffer in which the packet is being reassembled in. Packet_Length 16—bit value : Length of the packet received in bytes. Buffer_Capacity 16—bit value : Number of free locations left in the buffer in bytes. Packet_Timeout : 8-bit value : Indicates the time interval that the packet has been active (during reassembly) . Signals from the Input FIFO Cells_In_FIF0 : 1 - Available /* At least one cell is available in the FIFO */ 0 - Empty /* The FIFO is empty or has less than one cell */ Outgoing congestion signal Cong_Signal_VCI: identifier /* Virtual channel identifier of return cell */ TABLE 2-2 Reassembly Processor Logic © COPYRIGHT 1992 Adapative Corporation /* Scheduler */ -REPEAT e) Overflow) -ENDREPEAT /* Step RCH */ the VC */ tor, /* Step RVc */ )) ) TABLE 2-2 Reassembly Processor Logic © COPYRIGHT 1992 Adapative Corporation CWHILE (Read for Buffer Descriptor = Not_Done) Wait ; END WHILE; */ */ */ Packet_Timeout = Packet_Age_L m t ; TABLE 2-2 Reassembly Processor Logic © COPYRIGHT 1992 Adapative Corporation Li ENDIF; Write for Buffer_Descriptor (Packet_Address, Packet_Length, Buffer_Capacity, Residual_CRC, Packet_Timeout) ; /* WDesc */ = SSM)) (Buffer_Descriptor) ; Write for Virt_Chan (Status, Buffer_Descriptor) ; /* WVc */ ENDPROC; TABLE 2-2 Reassembly Processor Logic © COPYRIGHT 1992 Adapative Corporation -PROCEDURE * Age_Packet ; - Age_VCI = Age_VCI + 1; /* Mapping function for the VC */ l -IF (VC_Sel = 000) THEN Virt_Chan = Age_VCI mod 2**16- ELSEIF (VC_Sel 001) THEN Virt_Chan Age_VCI mod 2**15 ELSEIF (VC_Sel 010) THEN Virt_Chan Age_VCI mod 2**14 ELSEIF (VC_Sel 011) THEN Virt_Chan Age_VCI mod 2**13 ELSEIF (VC Sel 100) THEN Vir _Chan = Age_VCI mod 2**12 ELSEIF (VC_Sel = 101) THEN Virt_Chan = Age_VCI mod 2**11 ELSEIF (VC_Sel = 110) THEN Virt_Chan = Age_VCI mod 2**10 ELSE THEN Virt_Chan = Age_VCI mod 2**9 ; "-ENDIF; Read for Virt_Chan (Status, Buffer_Descriptor) ; pWHILE (Read for Virt_Chan -= Not_Done) Wait ; -END WHILE; • -ENDPROC; Operation Of Core Processing Unit The core processor 128 of FIG. 10 as defined by TABLE 1-2 is a processing unit for controlling the processing of cells for each of the one or more virtual channels. The core processing unit 128 is defined by TABLE 1-2. TABLE 1-2 includes a variable issue rate unit .that is described in detail in the above-identified application entitled METHOD AND APPARATUS FOR REACTIVE CONGESTION CONTROL IN AN ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK. In addition to variable issue rate unit, additional functions and units are added in the present specification which relate to two-dementional queueing, pipelining, packet aging and constant bit rate transmission. Overall, the core processing unit 128 is under control of the scheduler circuits defined by lines 1 through 12 in TABLE 1-2. The basic timing of the core processing unit 128, as it appears in the segmentation unit of FIG. 10 is controlled by the Xmit_Time[Rate_Queue] of line 3 of TABLE 1-2. If the transmit time is active for the particular Rate_Queue (for example, the rate queue of FIG. 12), then the Service_Rate_Queue procedure at line 46 of TABLE 1-2 is entered. The service rate queue ■procedure services each virtual channel on the rate queue and carries out a number of routines including the average metering routine in lines 61 through 71, the transmit (Xmit) cell routine in lines 74 through 100 and lines 124 through 126, the transmit rate recovery routine in lines 102 through 120. After the procedure ends, a return is made to the scheduler where in line 6 a check is made to see whether or not a CBR transmission signal is active and if so, then a CBR cell is transmitted on a CBR channel. -The procedure for transmitting the cell appears in lines 134 through 145. If thereafter a return is made where in line 9 of the scheduler a check is made for a congestion signal which is the procedure from lines 16 through 27. Thereafter, a return is made to line 10 of the scheduler where a Link_New_Descript- or procedure is called which appears at lines 148 through 171. The core processor 128 of TABLE 1-2 is a processing unit for controlling the processing of cells for each of the one or more virtual channels. The core processor includes control logic for controlling the processing of control information and data logic for controlling the processing of data. The control logic and the data logic operate to concurrently process data and control information for sustained transmission of cells in the ATM network up to the cell clock rate for each of the one or more virtual channels. Referring to TABLE 1-2, the data logic includes part of the Xmit_Cell procedure starting at line 134. The data logic makes the cell available at the cell interface for transmission on the ATM link at line 144. The cell trasnmitted includes the cell header read at line 138 using the control logic and the control memory interface. The cell trasnmitted includes the cell payload read at line 139 using the data logic and the packet memory interface. Two Dimentional Queues - FIG. 12 In FIG. 12, an example of the rate queue and the channel queue structures that are created in the control memory of FIG. 10 are shown. The rate queue which appears in the vertical direction in FIG. 12 includes a descriptor for each packet that is to be transfered over the ATM network with the same rate. The channel queue which appears in the horizontal direction in FIG. 12 includes a descriptor for each packet for the same virtual channel that is to be transfered over the ATM network with the same rate. Referring to FIG. 12-1 each of the rectangles represensts a descriptor, X, and includes two pointers, a vertical pointer, v, and a horizontal pointer, h. Additionally, each descriptor includes other control information asscociated with a packet including for example, a length field, 1, indicating the number of bits (or cells) in the packet. In the packet descriptor, X indicates the identity of the particular packet being processed by the queue of FIG. -10. For each descriptor, X, an associated rate queue pointer, v, identifies the next-in-order descriptor in the rate queue (vertical chain) that forms a linked list of packets having the same transmission rate. In FIG. 12-1, Descriptor6 (X = 6) is at the tail of the rate queue since the next-in-order vertical packet is DescriptorO, thar is v=0 for Desσriptorδ. Descriptor1 is at the head of the linked list. Descriptorl has a vertical pointer 3 pointing to the next-in- order packet 3. Deεcriptor3 has a pointer 4 (v=4) which points to Descriptor4. Descriptor4 has a pointer 6 which points to the tail of the queue Descriptor6. The rate queue in the vertical direction includes Descriptor!, Descriptor3, Descripτ_or4 and Descriptor6. In addition to the rate queue, one or more channel queues are shown in the horizontal direction. Descriptorl has a horizontal pointer 2 which points to Descriptor2. Descriptor2 has a horizontal pointer, h=0, and a vertical pointer that is blank. Accordingly, Desσriptor2 is at the tail of the horizon¬ tal channel queue which includes Descriptorl and Descriptor2 and which represent one virtual channel. In a similar manner, Descriptors is at the tail of the channel queue that includes Descriptor^ and Descriptors. Similarly, Descriptor? is at rhe tail of the channel queue that includes Descriptor6 and Descriptor?. In FIG. 12-2, the queue structure of FIG. 12-1 is modified by the addition of an additional descriptor, De_'crip * cor8, co the channel queue including tne Descripτ_or4 and Descriptcr5. Note that the addition of Descriptors causes the h pointer in Descriptors to be changed from a 0 as it appeared in FIG. 12-1 to an 8 as it appears in FIG. 12-2. The 8 is a pointer to the Descriptorδ added to the channel queue of Descriptor4 and Descriptors. In FIG. 12-3, Descriptor3 is removed from the rate queue. Removal of Descriptor3 is accompanied by changing the v pointer in Descriptorl from a 3 as it appeared in FIG. 12-2 to a 4 as it appears in FIG. 12-3 thereby pointing to the next-in-order Descripto 4. In FIG. 12-4, the Descriptor4 of FIG. 12-3 is removed. This removal is accompanied by changing the pointer in Descriptorl as it appeared in FIG. 12-3 from a 4 to a 5 as it appears in FIG. 12-4. Similarly, Descriptors has its vertical pointer changed from a blank to a 6 to thereby point to Descriptorδ which is at the tail of the rate (vertical) queue. FIG. 12 is an example of one of possibly many rate queues concurrently processed by core processing unit 128 of FIG. 10. The core processing unit 128 of FIG. 10 adds and removes packet descriptors from the queues. In operation, the core processing unit 128 is controlled by the scheduler circuits defined by lines 1 through 12 in TABLE 1-2. Referring to TABLE 1-2, the linking of a new descriptor for either the vertical rate queue or the horizontal channel queue is controlled by the Link_New_Descriptor procedure starting at line 148 in TABLE 1-2. The insertion at the head of the vertical rate queue commences at line 154 and the insertion at the tail of the horizontal channel queue commences at line 162. In TABLE 1-2, the delinking of a descriptor from either the vertical rate queue or the horizontal channel queue is con¬ trolled by the Delink_Descriptor procedure starting at line 174 in TABLE 1-2. The removal to collaspe the vertical rate queue commences at line 182 or line 195 and the removal to shrink the horizontal channel queue commences at line 187 or line 200. Segmentation Unit Pipelined Operation - FIG. 13 Referring to ' FIG. 13, an example of the pipelined operation of the segmentation core processor 128 of FIG. 10 is repres¬ ented. The processing for the cell interface, the control memory interface, the host interface and the packet memory interface, together with internal calculations for the processor are shown for a current cell N, for a prior cell N-l and for a next cell N+l. In FIG. 13, the straight lines opposite the cell interface, the control memory interface, and the packet memory interface represent processing that occurs by those interfaces, respect¬ ively! In FIG. 13, the curved lines between straight lines of the cell interface, the control memory interface, and the packet memory interface represent timing dependences between those interfaces. A proceess ending at the beginning of a curved arrow along one interface must complete before the process beginning at the end of the curved arrow at another interface. It is apparent from FIG. 13 that the cell processing for cell N-l overlaps the cell processing for cell N and similarly that the processing for cell N overlaps the processing for cell N+l. By this pipelined overlapping of the processing for different cells, the cell rate of transmission is maximized. In FIG. 13, the prefix W generally refers to a write operation, the prefix R generally refers to a read operation and the prefix X generally refers to a transmit operation. The legends in FIG. 13 are correlated to the comment fields in TABLE 1-2 to show the correlation between the TABLE 1-2 circuit specification logic and the pipelined operation thereof as indicated in FIG. 13. Through pipelining the processing of information for cells for operations at each of the cell interfaces, the core processing unit 128 in the source of FIG. 10 is able to to concurrently process data and control informa¬ tion for sustained transmission of cells in the ATM network up to the cell clock rate for each of the one or more virtual channels. Referring to FIG. 13, each cell transmitted has a header portion and a payload portion. For the cell N, the header portion is determined at the control memory interface by the read virtual header (RVH) operation of cell N. Concurrently with the reading of the header for cell N by the control memory interface, the payload information for cell N is read by the packet memory interface during the load LBP em operation for cell N. While the header and payload for cell N are being read by the control memory interface and the packet memory interface, during the RVH and LBPmen operations for cell N, respectively, the data transmission for the N-l cell payload is being concurrently processed by the cell interface during the XCPyld operation for cell N-1. After these operations are complete for cell N, the header for cell N is transmitted during the XCH operation which is then followed by the payload transmitted in the XCPyld operation for cell N. At the same time that the header and payload are transmitted by the cell interface, the control memory interface is performing concurrently the WCD, WVc, RCD, and RVC opera¬ tions. In this manner it can be seen that the pipelined operations over the various interfaces including the cell interface the control memory interface and the packet memory interface are concurrently operating. Reassembly Unit Pipelined Operation - FIG. 14 Referring to FIG. 14, the pipelined processing of the core processor 128 ' in the reassembly unit 103' of FIG. 11 is shown. The processing in the the core processor 128' is pipelined in that the processing of cell N-l is concurrent with the process¬ ing for cell N and the processing for cell N is concurrent with the processing for cell N+l. The legends in FIG. 14 are correlated to the comment fields in TABLE 2-2 to show the correlation between the TABLE 2-2 circuit specification logic and the pipelined operation thereof as indicated in FIG. 14. Through pipelining the processing of information for cells for operations at each of the cell interfaces, the core processing unit 128' in the destination of FIG. 11 is able to to concur¬ rently process data and control information for sustained reception of cells in the ATM network up to the cell clock rate for each of the one or more virtual channels . Combined Segmentation And Reassembly Operation - FIG. 15 Referring to FIG. 15, a schematic representation of the segmentation operation is a source and the corresponding operation in a destination is shown for a typical packet. Each packet in FIG 15 like the Descriptorl packet 141 includes * a plurality of cells shown as C(l,l), C(l,2), ..., C(l,n). In a similar manner, the additional Descriptor2 and Descriptor3 packets 142 and 143 in FIG. 15 have Descriptor2 cells and Descriptor3 cells. The Descriptor2 cells are C(2,l), C(2,2), ..., C(2,n). Similarly, the Descriptor3 cells are C(3,l), C(3,2), ..., C(3,n). The initial cells on the ATM link occur, for example, as as C(l,l), C(2,l), C(3,l), and so forth up to C(n+1). These initial cells are then subsequently followed by cells 0(1,2), C(2,2), C(3,2), and so forth up to C(3,n). In this way, outgoing cells from different packets are interleaved on the ATM link. The cells from each packet are received at the reassembly processor in the destination in the same order that they are sent by the segmentation processor in the source. The interleaved cells in the reassembly operation are reassembled into the packets so that the cells in the packet 140' at the destination are in the same order after the reassembly namely C(l,l), C(l,2), ... , C(l . n). Average Rate Metering - FIGs. 16-20 Referring to FIG. 16, the cell clock has cell periods from 0 through 31 which establish the cell clock rate. In FIG. 17, a request on a particular channel to send a cell occurs as an Xmit_Cell request in TABLE 1-2. At time 0 of the cell clock in FIG. 16, two requests to transmit cells were pending. With the average rate metering routine in TABLE 1-2, on average only one cell can be transmitted for each timeout of the TI counter. Referring to FIG. 18, the TI counter counts down from the maximum count (TIQ) to the minimum count (0) during the 0 to 4 clocks and resets on clock 5 to the maximum count (4 in the particular example shown) . The TI counting operation is shown in the average metering routine on lines 61- 71 of TABLE 1-2. In FIG. 19, the cell counter is an accumulator that accumulates the number of opportunities that are available to transmit cells. The cell counter is incremented each time the TI counter is counted down to 0. The cell counter is dec¬ remented each time a cell transmission occurs. A data transmis¬ sion is shown in FIG. 20. Referring to FIG. 19, at time 4, the cell counter is incremented at the time that the TI counter is decremented to 0. Cell counter time 4 indicates that one cell can be transmitted in accordance with the average metering routine. Accordingly, because a data request is pending as shown by FIG. 17 data is actually transmitted at time 5 in FIG. 20 thereby causing the cell counter to be decremented at T5 and reducing the data request to transmit to one as shown in FIG. 17. Similarly, the cell counter of FIG. 19 is incremented again at time 9 when the TI counter times out at time 9 as shown in FIG. 18. Since a request is pending as indicated in FIG. 17 a data cell is transmitted at time 10 as shown in FIG. 20 and the cell counter is decremented back to 0. At that time as shown in FIG. 17, no more data requests to transmit are pending and at time 14 when the TI counter times out, the cell counter is again incremented. Again .at time 19 when the TI counter decre¬ ments to 0, again no data request to transmit is pending and hence the cell counter is incremented to two at time 19. Similarly at time 24 when the TI counter times out the cell counter is incremented to a count of three. Thereafter when a data request to transmit occurs * for a request to transmit 4 cells, cells are transmitted at times 26, 27 and 28 for a total of 3 cells. Similarly, the cell counter is decremented from its value of 3 to 0 corresponding to the transmission of the 3 cells at times 26, 27, and 28 in FIG. 20. At time 28, the cell counter is at 0 meaning that the fourth cell to be transmitted by the data request is still pending but cannot be sent at time 29. However, when at time 29 when the TI counter again is decremented to 0, the cell counter of FIG. 19 is incremented to one thereby allowing a further data transmission at time 30 to occur so that the data request queue is reset to 0 after time 31 with no further requests pending, Referring to TABLE 1-2, the operation of the TI counter is as follows. If as in line 62 the TI_Ctr counter is equal to 0 then in line 64 the TI counter is reset to the maximum value of TIQ. If it is greater then 0, then the TI counter is decremen¬ ted by 1. If the TI counter is equal to 0 then the cell counter is incremented by 1 up to a maximum value of CQ. The operation continues in line 84 of TABLE 1-2 where in line 84 if the cell counter is greater than 0, then the cell counter is decremented by 1 and in line 87, a transmission of a cell occurs on the virtual channel. In TABLE 1-2, issue rate unit includes in lines 61 through 71 means for establishing an average rate, in lines 102 to 115 for the Xmit rate recovery routine means to restore the transmission rate in response to the absence of congestion signals, and in line 84 means to prevent the average transmis- sion rate from exceeding the average rate. Pac e Agin-? The operation of the reassembly processor of TABLE 2-2 is controlled by the scheduler and lines 1 through 9. Whenever input data occurs in the buffer from the ATM link, then the Receive_Cell procedure is called ' in line 4 where the procedure appears in lines 11 through 104. When not busy carrying out the receive cell operation, and sufficient time has elapsed so that the packet aging timer of line 5 has overflowed, then the age- packet routine of lines 106 through 148 is called. The time 5 packet aging timer is a common timer used for all packets . Although the timer is common, each packet can have a different aging time. Referring to the lines 89 through 92, each cell that is received is examined to determine if it is a beginning of message (BOM) cell and if it is then the packet time out for that packet is set to the packet age limit. The packet age limit is the starting count which is then incremented each time the age packet routine is executed. The packet timeout value set in line 91 for a particular cell is written in line 93 into the control memory (WDesc operation in FIG. 14.). In the age packet procedure, the package timeout is incremented by one in line 136 and the incremented packet timeout is written into the buffer descriptor. If the packet timeout has been incremented to the overflow condition then the packet is discarded by setting the status in line 140 to inactive and writing the inactive status for the virtual channel in line 141 into the status and buffer descriptor fields. Finally in line 142 the Write for Packet_Complete_Queue makes the packet available to the host unit. Further and Other Embodiments While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention. What is claimed is:

Claims: CLAIMS 1. A communication system having reactive congestion control comprising, a plurality of sources, each source including a modifiable issue rate unit which transmits forward information signals at different transmission rates in response to congestion signals, said issue rate unit decreasing the transmission rate in response to congestion signals, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting the sources to the destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the node, said network having a plurality of virtual channels, where, or each virtual channel, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in response to congestion signals over the virtual channel, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the congestion signal generating means in one of said nodes generates said congestion signals for the virtual channel in response to congestion in said one of said nodes. 2. The communication system of Claim 1 wherein said issue rate unit increases the transmission rate in response to the absence of congestion signals. 3. The communication system of Claim 1 wherein the transmission interval for a congestion signal returning from a congested node to the source is short thereby enabling the issue rate unit to reactively modify the transmission rate and thereby reduce congestion. 4. The communication system of Claim 1 wherein the transmission interval for a congestion signal returning from a congested node to the source is less than the interval between information signals transmitted over the virtual channel whereby the issue rate unit reactively responds to modify the transmission rate to reduce congestion. 5. The communication system of Claim 1 wherein the transmission interval for congestion signal returning from a congested node to the source is less than ten intervals between information signals transmitted over the virtual channel whereby the issue rate unit reactively responds to modify the transmission rate to reduce congestion. 6. The communication system of Claim 1 wherein the processing time required to generate congestion signal at each node is much less than said transmission interval for congestion signal. 7. The communication system of Claim 1 wherein said issue rate unit has means for decreasing said transmission rate exponen¬ tially in response to a congestion signal. 8. The communication system of Claim 7 wherein said issue rate unit, after decreasing said transmission rate, has means for increasing said transmission rate exponentially in response to the absence of a congestion signal. 9. The communication system of Claim 8 wherein the rate of increasing said transmission rate is less than the rate of decreasing said transmission rate. 10. The communication system of Claim 1 wherein said forward information is fragmented into cells, each cell including a virtual channel identifier, and wherein each node includes a switching element, each switching element including, a switch fabric, a plurality of port controllers interconnected by said switch fabric, each of said port controllers including, an input controller, an output controller, congestion detection means for detecting congestion in the node, reversing means for copying a cell, having a virtual channel identifier, from the forward path to the return path to thereby generate a congestion signal on said return path. 11. The communication system of Claim 10 wherein said reversing means includes reverse marker means for marking copied cells with a return path indicator whereby return cells are distin¬ guished from forward cells. 12. The communication system of Claim 10 wherein each of said port controllers includes selector means for selecting cells from one virtual channel for the forward path or from another virtual channel for the return path. 13. The communication system of Claim 12 wherein said selector means grants priority to cells from the return path whereby congestion signals are given priority in the network. 14. The communication system of Claim 10 wherein said forward paths include queues for storing cells in the forward direction, each of said queues including means for providing a queue-level signal, as a function of the fullness of the queue, to form the congestion signal. 15. The communication system of Claim 1 wherein said forward information is fragmented into cells, each cell including a virtual channel identifier, and wherein each node includes a switching element, each switching element including, a switch fabric, a plurality of port controllers interconnected by said switch fabric, each port controller connected to a communication link and each port controller including, an input controller for said link including a transla¬ tor for receiving the virtual channel identifier of incoming cells on the link and responsively translating the input virtual channel identifier of incoming cells to an output virtual channel identifier of outgoing cells for another link for another port controller connected to said switch fabric, an output controller for said link, congestion detection means for detecting congestion in the node, reversing means for copying a cell, having a virtual channel identifier, from the forward path to the return path to thereby generate a congestion signal on said return path, said reversing means connecting said output virtual channel identifier to be reverse translated to said input virtual channel identifier whereby the virtual channel identifiers for cells in the forward path and in the return path over the link are the same. 16. The communication system of Claim 15 wherein said port controller includes one or more queues connected in parallel for queueing cells for the forward path and the return path of a link, said queues providing queue-level signals indicating the fullness of the queues and including selection means for selecting cells from said queues. 17. The communication system of Claim 16 wherein said selector means grants priority to cells from the return path whereby congestion signals are given priority in the network. 18. The communication system of Claim 15 wherein said reversing means includes reverse marker means for marking copied cells with a return path indicator whereby, return cells are distin¬ guished from forward cells. 19. The communication system of Claim 15 wherein each of said port controllers includes selector means for selecting cells from one virtual channel for the forward path or from another virtual channel for the return path. 20. The communication system of Claim 15 wherein said selector means grants priority to cells from the return path whereby congestion signals are given priority in the network. 21. The communication system of Claim 15 wherein said forward paths include queues for storing cells in the forward direction, each of said queues including means for providing a queue-level signal, as a function of the fullness of the queue, to form the congestion signal. 22. A wide-area communication system having local reactive congestion control comprising, a plurality of local communication systems, each local communication system including, a plurality of local sources, each local source including a modifiable issue rate unit which transmits forward information signals at different transmission rates, said issue rate unit decreasing the transmission rate in response to the presence of congestion signals and increas¬ ing the transmission rate in response to the absence of congestion signals, a plurality of local destinations, one or more local nodes forming an asynchronous transfer mode (ATM) local network connecting the sources to the destinations, each local node including, a forward path for transfer of information at different selectable transmission rates in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the local node, said network having a plurality of virtual channels where, for each virtual channel, one of said plurality of local sources is linked to one of said plurality of local destina¬ tions through said local network by linking forward paths from one or more local nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in response to congestion signals over the virtual channel, said one of said plurality of local destina¬ tions is linked to said one of said plurality of local sources through said network by linking return paths from said one or more nodes, the congestion signal generating means in one of said local nodes generates said congestion signals for the virtual channel in response to congestion in said one of said local nodes, one or more wide-area sources connected to one of said local networks, one or more wide-area destinations connected to another one of said local networks, a plurality of local network links interconnecting two or more local networks to form a wide-area network, said wide-area network having a plurality of virtual channels where, for each virtual channel, one of said plurality of wide-area sources is linked to one of said plurality of wide-area destinations through a plurality of said local networks over said local networks and said local network links. 23. A communication system of one or more virtual channels having reactive congestion control comprising, a plurality of sources, each source including a modifiable issue rate unit which transmits forward information signals at different transmission rates in response to congestion signals, said issue rate unit transmitting, for each of one or more channels, at a maximum-channel-peak-cell-rate in the absence of congestion and at a rate below the maximum-channel-peak-cell- rate for each channel experiencing congestion, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting sources to destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the node, for each of one or more virtual channels in the network, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in response to congestion signals over the virtual channel, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the congestion signal generating means in one of said nodes generates said congestion signals for the virtual channel in response to congestion in said one of said nodes. 24. A multiple issue rate source for use in a communication system of one or more virtual channels having reactive control where said system includes, one or more of said multiple issue rate sources, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting sources to destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the networ , a return path for returning control signals in a reverse direction through the network toward a source, control signal generating means for generating control signals in response to congestion in the node, for each of one or more virtual channels in the network, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the control signal generating means in one of said nodes generates said control signals for the virtual channel in response to congestion in said one of said nodes, said multiple issue rate source comprising, a modifiable issue rate unit having means to transmit forward information signals at different transmission rates in response to control signals, said issue rate unit having an output for transmitting, for each of one or more virtual channels, at a maximum- channel-peak-cell-rate in the absence of a control signal and at a rate below the maximum-channel-peak- cell-rate for each channel providing a control signal. 25. A multiple issue rate source for use in a communication system where the communication system has one or more multiple issue rate sources connected through one or more channels to a plurality of destinations and has control signal generating means for generating control signals for the channels for reactively controlling the transmission rates over the channels, said multiple issue rate source comprising, a modifiable issue rate unit having means to transmit information signals at different transmission rates in response to control signals, said issue rate unit having an output for transmitting, for each of one or more channels, at a maximum-channel-peak-cell-rate or at a rate below the maximum-channel-peak-cell-rate as a function of the control signals for each channel. 26. A communication unit for use in an asynchronous transfer mode (ATM) network where a host unit processes packets for communication over one or more virtual channels in the network, where each packet is segmented into a plurality of associated cells for transmission over the network at a cell clock rate, where each packet has data and control information, and where memory means stores control information and data for packets and for cells associated with the packets for each of the one or more virtual channels, said communication unit comprising, a memory interface for interfacing the communicatiion unit to the memory means, a cell interface for interfacing the communication unit to the ATM network, core processor means for controlling the processing of cells for each of the one or more ' virtual channels, said core processor means including control logic means for controlling the processing of control information and data logic means for controlling the processing of data, said control logic means and said data logic means operating to concurrently process data and control information for sustained transmission of cells in the ATM network up to the cell clock rate for each of the one or more virtual channels. 27. The communication unit of Claim 26 wherein said communication processing unit is a segmentation unit wherein packets to be transmitted are segmented into a plurality of cells. 28. The communication unit of Claim 25 wherein said communication processing unit is a reassembly unit wherein cells transmitted are reassembled into packets. 29. The communication unit of Claim 28 wherein said logic control means includes, for each packet, means for storing a packet age value indicating the length of time that the packet has been active in transmission in the ATM network, means for discarding packets that have a packet age value exceeding an age limi . 30. The communication unit of Claim 26 wherein said communication processing unit includes a host interface for connection to said host unit and provides information at said memory interface, said cell interface, and said host interface for each of the one or more virtual channels. 31. The communication unit of Claim 26 wherein common memory includes a control memory and a data memory and wherein said memory interface includes a control interface and a data interface for interfacing said communication processing unit to said control memory and said data memory, respectively. 32. The communication unit of Claim 31 wherein said communication processing unit is a pipelined processing unit that concurrently processes cells for packets for a plurality of channels and concurrently provides cell information at said control interface, said data interface, and said cell interface. 33. The communication unit of Claim 26 wherein said logic control means includes means for storing two-dimensional queues of descriptors in said control memory including, means for storing first-dimension rate queues for queueing descriptors for cells of different channels having cells to be transmitted, and means for storing second-dimension channel queues, one channel queue for each channel having a descriptor in the rate queue where each channel queue queues descriptors for cells of the same channel. 34. The communication unit of Claim 33 wherein said logic control means includes means for storing a different rate queue for each transmission rate. 35. The communication unit of Claim 34 wherein said logic control means includes means for storing a plurality of different channel queues for each rate queue. 36. The communication unit of Claim 34 wherein said logic control means includes means for storing each rate queue as a linked list of descriptors, each descriptor in the rate queue identifying a descriptor from a different one of the channels having cells to be transmitted at the rate for the particular rate queue. 37. The communication unit of Claim 35 wherein said logic control means includes means for storing each channel queue as a linked list of descriptors, each descriptor identifying a packet to be transmitted, for an associated one of the channels, where the linked list of descriptors for the channel queue identifies all the packets, for the associated one of the channels, to be transmitted. 38. The communication unit of Claim 26 wherein said logic control means includes means for controlling the issue rate of cells to the ATM network based on average rate metering. 39. A communication system having reactive congestion control comprising, a plurality of sources, each source including a modifiable issue rate unit which transmits forward information signals at different transmission rates in response to congestion signals and in response to average rate metering, said issue rate unit decreasing the transmission rate in response to congestion signals, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting the sources to the destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the node, said network having a plurality of virtual channels where, for each virtual channel, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in response to congestion signals over the virtual channel, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the congestion signal generating means generates said congestion signals for the virtual channel in response to congestion. 40. The communication system of Claim 39 wherein said issue rate unit includes means for establishing an average rate, means to restore the transmission rate in response to the absence of congestion signals, and means to prevent the average transmis¬ sion rate from exceeding the average rate. 41. The communication system of Claim 39 wherein the transmission interval for a congestion signal returning from a congested node to the source is short thereby enabling the issue rate unit to reactively modify the transmission rate and thereby reduce congestion. 42. The communication system of Claim 39 wherein the transmission interval for a congestion signal returning from a congested node to the source is less than the interval between information signals transmitted over the virtual channel whereby the issue rate unit reactively responds to modify the transmis¬ sion rate to reduce congestion. 43. The communication system of Claim 39 wherein the transmission interval for congestion signal returning from a congested node to the source is less than ten intervals between information signals transmitted over the virtual channel whereby the issue rate unit reactively responds to modify the transmis¬ sion rate to reduce congestion. 44. The communication system of Claim 39 wherein the processing time required to generate congestion signal at each node is much less than said transmission interval for congestion signal. 45. The communication system of Claim 39 wherein said issue rate unit has means for decreasing said transmission rate exponentially in response to congestion signals. 46. The communication system of Claim 45 wherein said issue rate unit includes means for establishing an average rate, means for decreasing said transmission rate due to congestion signals, and means for increasing said transmission rate exponentially in response to the absence of congestion signals, and means to prevent the average transmission rate from exceeding the average rate. 47. The communication system of Claim 46 including means for increasing said transmission rate at a rate less than the rate of decreasing said transmission rate. 48. The communication system of Claim 39 wherein said forward information is segmented into cells, each cell including a virtual channel identifier, and wherein each node includes a switching element, each switching element including, a switch fabric, a plurality of port controllers interconnected by said switch fabric, each of said port controllers including, an input controller, an output controller, congestion detection means for detecting congestion in the node, reversing means for copying a cell, having a virtual channel identifier, from the forward path to the return path to thereby generate a congestion signal on said return path. 49. The communication system of Claim 48 wherein said reversing means includes reverse marker means for marking copied cells with a return path indicator whereby return cells are distinguished from forward cells. 50. The communication system of Claim 48 wherein each of said port controllers includes selector means for selecting cells from one virtual channel for the forward path or from another virtual channel for the return path. 51. The communication system of Claim 50 wherein said selector means grants priority to cells from the return path whereby congestion signals are given priority in the network. 52. * The communication system of Claim 48 wherein said forward paths include queues for storing cells in the forward direction, each of said queues including means for providing a queue-level signal, as a function of the fullness of the queue, to form the congestion signal. 53. The communication system of Claim 52 wherein said forward information is segmented into cells, each cell including a virtual channel identifier, and wherein each node includes a switching element, each switching element including, a switch fabric, a plurality of port controllers interconnected by said switch fabric, each port controller connected to a communication link and each port controller including, an input controller for said link including a transla¬ tor for receiving the virtual channel identifier of incoming cells on the link and responsively translating the input virtual channel identifier of incoming cells to an output virtual channel identifier of outgoing cells for another link for another port controller connected to said switch f bric, an output controller for said link, congestion detection means for detecting congestion in the node, reversing means for copying a cell, having a virtual channel identifier, from the forward path to the return path to thereby generate a congestion signal on said return path, said reversing means connecting said output virtual channel identifier to be reverse translated to said input virtual channel identifier whereby the virtual channel identifiers for cells in the forward path and in the return path over the link are the same. 54. The communication system of Claim 48 wherein said port controller includes one or more queues connected in parallel for queueing cells for the forward path and the return path of a link, said queues providing queue-level signals indicating the fullness of the queues and including selection means for selecting cells from said queues. 55. The communication system of Claim 54 wherein said selector means grants priority to cells from the return path whereby congestion signals are given priority in the network. 56. The communication system of Claim 53 wherein said reversing means includes reverse marker means for marking copied cells with a return path indicator whereby return cells are distinguished from forward cells. 57. The communication system of Claim 53 wherein each of said port controllers includes selector means for selecting cells from one virtual channel for the forward path or from another virtual channel for the return path. 58. The communication system of Claim 53 wherein said selector means grants priority to cells from the return path whereby congestion signals are given priority in the network. 59. The communication system of Claim 53 wherein said forward paths include queues for storing cells in the forward direction, each of said queues including means for providing a queue-level signal, as a function of the fullness of the queue, to form the congestion signal. 60. A wide-area communication system having local reactive congestion control comprising, a plurality of 'local communication systems, each local communication system including, a plurality of local sources, each local source including a modifiable issue rate unit which transmits forward information signals at different transmission rates, said issue rate unit decreasing the transmission rate in response to the presence of congestion signals and increas¬ ing the transmission rate in response to the absence of congestion signals and in response to average rate metering, a plurality of local destinations, one or more local nodes forming an asynchronous transfer mode (ATM) local network connecting the sources to the destinations, each local node including, a forward path for transfer of information at different selectable transmission rates in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the local node, said network having a plurality of virtual channels where, for each virtual channel, one of said plurality of local sources is linked to one of said plurality of local destina¬ tions through said local network by linking forward paths from one or more local nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in response to congestion signals over the virtual channel, said one of said plurality of local destina¬ tions is linked to said one of said plurality of local sources through said network by linking return paths from said one or more nodes, the congestion signal generating means generates said congestion signals for the virtual channel in response to congestion, one or more wide-area sources connected to one of said local networks, one or more wide-area destinations connected to another one of said local networks, a plurality of local network links interconnecting two or more local networks to form a wide-area network, said wide-area network having a plurality of virtual channels where, for each virtual channel, one of said plurality of wide-area sources is linked to one of said plurality of wide-area destinations through a plurality of said local networks over said local networks and said local network links. 61. A communication system of one or more virtual channels having reactive congestion control comprising, a plurality of sources, each source including a modifiable issue rate unit which transmits forward information signals at different transmission rates in response to congestion signals, said issue rate unit transmitting, for each of one or more channels, at a maximum-channel-peak-cell-rate in the absence of congestion and at a rate below the maximum-channel-peak-cell- rate for each channel experiencing congestion and transmitting under control of average rate metering, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting sources to destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the node, for each of one or more virtual channels in the network, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in. response to congestion signals over the virtual channel, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the congestion signal generating means generates said congestion signals for the virtual channel in response to congestion. 62. A communication system having one or more virtual channels each having reactive control and average rate metering where said system includes, one or more multiple issue rate sources, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting sources to destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the network, a return path for returning control signals in a reverse direction through the network toward a source, control signal generating means for generating control signals in response to congestion, for each of one or more virtual channels in the network, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the control signal generating means in one of said nodes generates said control signals for the virtual channel in response to congestion, said multiple issue rate source comprising, a modifiable issue rate unit having means to transmit forward information signals at different transmission rates in response to control signals and average rate metering, said issue rate unit having an output for transmitting, for each of one or more virtual channels, at a maximum-channel-peak-cell-rate in the absence of a control signal and at a rate below the maximum-channel-peak-cell-rate for each channel providing a control signal. 63. A multiple issue rate source for use in a communication system where the communication system has one or more multiple issue rate sources connected through one or more channels to a plurality of destinations and has control signal generating means for generating control signals for the channels for reactively controlling the transmission rates over the channels and for controlling the transmission rates over the channels with average rate metering, said multiple issue rate source comprising, a modifiable issue rate unit having means to transmit information signals at different transmission rates in response to control signals, said issue rate unit having an output for transmitting, for each of one or more channels, at a maximum-channel-peak-cell-rate or at a rate below the maximum-channel-peak-cell-rate as a function of the control signals for each channel. 64. A communication unit for use in an asynchronous transfer mode (ATM) network where a host unit processes packets for communication over one or more virtual channels in the network, where each packet is segmented into a plurality of associated cells for transmission over the network at a cell clock rate, where each packet has data and control information, and where memory means stores control information and data for packets and for cells associated with the packets for each of the one or more virtual channels, said communication unit comprising, a memory interface for interfacing the communication unit to the memory means, a cell interface for interfacing the communication unit to the ATM network, core processor means for controlling the processing of cells for each of the one or more virtual channels, said core processor means including control logic means for controlling the processing of control information and data logic means for controlling the processing of data, said control logic means and said data .logic means operating to concurrently process data and control information for sustained transmission of cells in the ATM network up to the cell clock rate for each of the one or more virtual channels. 65. A communication unit for use in an asynchronous transfer mode (ATM) network where a host unit processes packets for communication over one or more virtual channels in the network, where each packet is segmented into a plurality of associated cells for transmission over the network at a cell clock rate, where each packet has data and control information, and where memory means stores control information and data for packets and for cells associated with the packets for each of the one or more virtual channels, and where constant bit rate information is provided for transmission over one or more of the virtual channels, said communication unit comprising, a memory interface for interfacing the communication unit to the memory means, a cell interface for interfacing the communication unit to the ATM network, core processor means for controlling the processing of cells for each of the one or more virtual channels, said core pre essor means including control logic means for controlling the processing of control information and data logic means for controlling the processing of data, said control logic means and said data logic means operating to concurrently process data and control information for sustained transmission of cells in the ATM network up to the cell clock rate for each of the one or more virtual channels, said core processing means including constant bit rate means for selecting constant bit rate information for transmission in said ATM network up to the cell clock rate . 66. A communication system having reactive congestion control comprising, a plurality of sources, each source including a modifiable issue rate unit which transmits forward information signals at different transmission rates in response to congestion signals and includes average rate metering means for insuring that the transmission rate does not exceed an average rate, said issue rate unit decreasing the transmission rate in response to congestion signals, a plurality of destinations, one or more nodes forming an asynchronous transfer mode (ATM) network connecting the sources to the destinations, each node including, a forward path for transfer of information in a forward direction toward a destination through the network, a return path for returning congestion signals in a reverse direction through the network toward a source, congestion signal generating means for generating congestion signals in response to congestion in the node, said network having a plurality of virtual channels where, or each virtual channel, one of said plurality of sources is linked to one of said plurality of destinations through said network by linking forward paths from one or more nodes, and wherein said issue rate unit transmits forward information signals at different transmission rates in response to congestion signals over the virtual chann l, said one of said plurality of destinations is linked to said one of said plurality of sources through said network by linking return paths from said one or more nodes, the congestion signal generating means in one of said nodes generates said congestion signals for the virtual channel in response to congestion in said one of said nodes.

Inventors: BUCKLEY CLIFFORD JAMES, GLOVER WILLIE T, GUPTA AMAR, NEWMAN PETER, SINGH GURURAJ, BUCKLEY, CLIFFORD, JAMES, GLOVER, WILLIE, T., GUPTA, AMAR, NEWMAN, PETER, SINGH, GURURAJ
Applicants: ADAPTIVE CORP, ADAPTIVE CORPORATION
Application year: 1992
Main classification: H04J3
IPC codes: H04L12, H04Q11