High voltage CMOS circuit with nand configurated logic gates and a reduced number of N-MOS transistors requiring drain extension

Abstract: In a CMOS logic circuit destined to function at a relatively high supply voltage such as to require the formation of graded diffusions in the structure of N-MOS transistors, a NAND configuration is used which comprises a staked pair of N-MOS transistors (N₃,N₄). This permits to restrict the number of graded diffusions to be formed in N-MOS structures only to the drain regions which are directly connected to an output node. In clocked CMOS circuitry where transfer transistors are normally used between gates, the advantages in terms of enhanced speed and ability of the circuit to be compacted by cutting the number of N-MOS structures necessarily provided with drain extension regions as in prior art circuits, are remarkable.

Description: FIELD OF THE INVENTION The present invention relates to CMOS logic circuits and more in particular to a way to solve the problem of protecting N-MOS transistors from aging and/or failure caused by the phenomenon of impact ionization which occurs under particular conditions of operation at relatively high voltage in CMOS logic gates. BACKGROUND OF THE INVENTION The mechanism of the aging and/or failure of N-MOS transistors caused by the phenomenon of impact ionization taking place under particular bias conditions of the gate of the transistor versus its source while the drain is biased at a relatively high voltage in respect to the source potential, is well known and debated in literature. This problem occurs every time an N-MOS transistor having its drain biased at the supply voltage by a preceding switching on of the P-MOS transistor portion of a CMOS inverter, switches on as a consequence of a raising of the gate voltage. The flow of electrons crossing the channel region of the transistor is accelerated by a synergistic combination of electric fields due to the "summing" of the effects of the V GS and V DS voltages. This causes additional carriers to be driven to the drain coming from electron-hole pairs generated by the impact of high kinetic energy electrons with orbitant electrons of the atoms of the crystal lattice in the drain region. This mechanism generates an additional current known as substrate current which adds to the drain-source current. This additional current is highly dangerous because even if of a low level (in the order of few µA) may produce locally a direct biasing of the substrate in respect to the source region of the transistor, sistor, thus triggering on a parasitic bipolar transistor in parallel to the real N-MOS. The V DS voltage to which this parasitic bipolar transistor switches on is known in literature as the SNAP-BACK voltage. This phenomenon may be destructive for the metallic connections (contacts) of the N-MOS, which must convey a far augmented current than the design current. Even where complete failure is avoided, the mechanism at the base of the SNAP-BACK phenomenon is such as to cause in time a degradation of the electrical characteristics of the N-MOS transistor. This degradation (aging) due to the presence of high energy electrons in the channel, is cumulative in time, thus producing a progressive loss of functionality of the N-MOS transistors which is even more feared than an istantaneous failure, because the "microscopic" behaviour of the integrated circuit varies with time due to the alterations which have occurred at the level of single N-MOS devices, the threshold voltage (V th ) and transconductance (gm) of which tend to subtly change with time. The document JP-A-62286265 of the publication "Patent Abstracts of Japan", and in the document US-A-5,016,077 claiming the priority date of the former document, describe micronized insulated-gate type semiconductor devices manufactured with transistors of reduced channel length, wherein the N-channel portions of typical NAND logic gates is realized by forming a lightly doped drain only in the drain region of the N-MOS transistor that is connected to the output node, in order to reduce the ON resistance of the N-channel portion of the gate, for increased speed of operation. The document JP-A-60169219 of the publication "Patent Abstracts of Japan" describes a tristatable output CMOS stage controlled by a complementary pair of clock signals. It is known that impact ionization and its negative effects may be countered by forming graded drain diffusions (known also as drain extensions). These graded drain diffusions or junctions may be obtained by forming a second diffused region having a lower dopant concentration than that commonly used for the drain region proper, which is formed within said second (drain extension) region having a reduced concentration, with the result of increasing the V DS voltage to which the SNAP-BACK phenomenon takes place and reducing the aging process caused by impact ionization, by determining, during the switching on the N-MOS transistor, an electric field of reduced intensity near the drain region of the transistor by virtue of the grading of the diffusion. Frequently in certain circuit applications, it is necessary for the same prevention reasons to form also the source diffusion in a similarly graded manner, i.e. provide the N-MOS transistor with "bilateral" (drain) extensions. The raising of the SNAP-BACK voltage thus obtained is paid by a reduction of the electrical performance of the N-MOS transistor so provided of drain extensions, in terms of reduced speed and increased ON-resistance. Moreover, under the aspect of the fabrication technology of these devices, the necessary use of a dedicated "drain extension" mask, beside complicating the fabrication process, makes the N-MOS transistors more cumbersome in terms of layout and more sensitive to misalignment problems and therefore more difficult to be reduced in size through compacting technologies, also known as "shrinkage processes", toward which any circuit evolves in time for exploiting the improvements that the photolitographic techniques and apparatuses constantly go through. All the above-mentioned problems are most frequently encountered in mixed analog-digital integrated CMOS circuits, wherein two different supply voltages are normally present: a low supply voltage (5V) for the logic circuitry which interacts with the external world, and a high supply voltage (10V) for the internal logic circuitry which interface with the analog portions of the integrated circuit operating at such a higher supply voltage in order to ensure a large dynamic voltage swing. The logic circuits operating at high supply voltage are therefore potentially sensitive to said SNAP-BACK problems consititute parts of the integrated circuit which, because of the large use of graded junctions, raise remarkable problems of increased criticity when attempting a compacting of the integrated circuit for exploiting at best improved fabrication techniques which may have become available. Therefore, there is a need of logic circuits, i.e. for CMOS logic gates capable of operating at a relatively high supply voltage and wherein the need of forming graded diffusions in the structure of N-MOS transistors be as minimum as possible in order to maintain characteristics of high speed for the propagation of data through the logic gates and ensuring a low internal ON-resistance of the same transistors. The present invention provides an effective solution to this specific technical problems. SUMMARY OF THE INVENTION According to the present invention, the CMOS logic gates, i.e. the CMOS logic circuits which are destined to operate at a supply voltage as high as to require the formation of graded diffusions in the structures of N-MOS transistors in order to increase the voltage between source and drain (V DS ) at which the switching on of the intrinsic parasitic bipolar transistor in parallel to each real N-MOS transistor takes place, have a NAND configuration comprising two staked (i.e. connected in electrical series) N-MOS transistors to which only the N-MOS transistor whose drain is connected to an output terminal of the logic gate is provided with a graded diffusion, solely in the drain region thereof. The solution proposed by the present invention is based upon an intuition that the so-called substrate effect, which is intrinsic to any MOS device, whose source is not connected to the substrate, could be exploited for achieving the sought objective. It is known in fact that the ability of a MOS transistor to transfer a signal is tied to its threshold voltage. The latter is in turn a function of the substrate voltage in respect to the source voltage. By referring to a functional illustration of an N-MOS transistor shown in Fig. 1, the threshold voltage of the transistor is given by: V th (V S ) = V tho + K BE ( V S + 2 F - 2 F ) where:  F = Fermi's potential K BE = √ 2q e ε Si N B / C ox where: ε Si is the dielectric constant; N B is the dopant concentration in number of dopant atoms per cm 3 in the substrate; C ox is the capacitance of the sandwich formed by the polycristalline silicon gate/the silicon dioxide gate isolation layer/the semiconductor (substrate); and where V S ≡ V BS (i.e. the reverse bias voltage of the substrate, positive in an N-MOS transistor). In practice the following mechanism may be assumed: low state (0) : the capacitance associated with the drain region of the transistor charges to the voltage V D which coincides with the supply voltage (V CC ). The gate voltage V GS = 0V, therefore the N-MOS transistor T1 is OFF and the capacitance C2 has no charge (ground). high state (1) : the gate voltage V GS raises in time from 0V up to a maximum value: V GS = V CC . The N-MOS transistor T1 switches on and the capacitance C2 charges to a voltage V S , the end value of which is a function of the threshold voltage of the N-MOS transistor, according to the following expression: V S = V D - V th (V S ) = V CC - V tho - K BE ( V S + 2 F - 2 F ) Therefore it may be said that the ability of the N-MOS transistor to tranfer a voltage signal is a function of the bias voltage of the substrate. Viceversa, in a NAND type configuration of two N-MOS transistors connected in series, that is circuitally "staked" one on top of the other, as depicted in Fig. 2, the voltage V S (which coincides with the drain voltage of the transistor T2) is reduced in respect to the voltage V S of the circuit of Fig. 1, by a quantity given by the following expression: V tho + K BE ( V BS + 2 F - 2 F ) Therefore, when the transistor T2 is forced to commute by the voltage V GS2 passing from OV to V CC′ its drain voltage will no longer reach the dangerous level V D = V CC′ which would make necessary to form graded junctions (i.e. drain extension regions), viceversa because of the voltage level reduction due to the body effect, the transistor T2 may be designed without graded junctions. Therefore, by employing NAND configured logic gates which comprise two staked N-MOS transistors and by exploiting the attendant substrate (body) effect, it is possible to restrict the use of graded junctions in N-MOS structures of logic circuits destined to function at a relatively high supply voltage, only to the N-MOS transistor whose drain is connected to an output terminal of the logic gate and limitatively to the sole drain region of the transistor, i.e. making the respective source diffusion in a normal manner without grading it. In this way, the speed of propagation of data through the logic gate is no longer appreciably reduced because of the presence of only a single graded junction of the drain region of the N-MOS transistor having its drain connected to an output of the logic gate and the whole logic circuit may be more easily compacted through so-called "shrinkage techniques" exploiting advanced fabrication processes. BRIEF DESCRIPTION OF THE DRAWINGS The different aspects and advantages of the invention will become more evident through the following description of several embodiments and reference to the attached drawings, wherein: Figure 1 is a schematic functional illustration of an N-MOS transistor, as described above; Figure 2 is a schematic functional illustration of a NAND configured gate comprising two staked N-MOS transistors, as described above; Figure 3 shows a common CMOS inverter circuit with a transfer device, made according to a known technique; Figure 4 shows a functionally equivalent circuit of the inverter with a transfer device of Fig. 3, made according to the present invention. DESCRIPTION OF BEST EMBODIMENTS The technical solution provided by the present invention as an alternative to a burdensome use of graded diffusions in the structure of N-MOS transistors for countering the aging mechanism thereof, has a great utility especially in the case of logic circuits employing shift registers and more in general in logic circuits wherein the output is sampled by means of a transfer transistor. In Fig. 3 a typical inverter circuit with transfer transistor, which is widely used in logic circuits is shown. The use of an N-MOS transistor as a transfer device requires the formation of graded implantations of both the diffused drain and source junctions because drain and source are substantially interchangeable in the charging/discharging processes of the output/input capacitances. In the circuit of Fig. 3 , the junctions requiring graded diffusions for enabling the circuit to work at a relatively high supply voltage ( V CC ), are identified by the letters DE . The strong penalization on the transfer speed characteristics of the circuit due to the large number of graded junctions, is evident. According to the present invention, a circuit functionally equivalent to the circuit of Fig. 3 may be realized by employing a NAND configuration which comprises two staked N-MOS transistors, N1 and N2 , respectively, for the first inverter and N3 and N4 , respectively, for the second inverter, while forming a graded diffusion only in the drain region which is connected to the output of the respective inverter, of the two pairs of N-MOS transistors, i.e. N1 and N3 . The circuit of Fig. 4 , made according to the present invention, requires only two N-MOS transistors to have a single graded drain junction. By contrast, the circuit of Fig. 3 , according to the prior art, required two N-MOS transistors provided with bilateral graded junctions (both source and drain regions) and two N-MOS transistors provided with at least a graded drain junction. The advantages in terms of enhanced performance and ability to be more easily compacted of the circuit made in accordance with the present invention as compared with the equivalent circuit according to the prior art are evident. The present invention is useful both for designing logic circuits destined to operate at a relatively high supply voltage integrated in a P -type substrate ( P-well ) as well as in circuits integrated in an N -type substrate ( N-well ). In fact, in both cases, the logic circuit realized in accordance with the present invention offers advantages both in terms of readuced area requirement, speed, and may be easily compacted.

Claims: A CMOS logic circuit having at least two clocked logic gates coupled in cascade, comprising: a first P-MOS transistor (P2) having a drain, a gate and a body and a second P-MOS transistor (P1) coupled in a stacked configuration with the first P-MOS transistor (P2) and having a gate, a source and a body; a first N-MOS transistor (N1) having a drain, a gate and a body and a second N-MOS transistor (N2) coupled in a stacked configuration with the first N-MOS transistor (N1), and having a source, a gate and a body, the drain of the first N-MOS transistor (N1) being coupled to the drain of the first P-MOS transistor (P2), the gate of the first N-MOS transistor (N1) receiving a first clock signal (CK), the gate of the first P-MOS transistor (P2) receiving a second clock signal ( CK ) which is binary complemented of the first clock signal (CK), the gate of the second P-MOS transistor (P1) being coupled to the gate of the second N-MOS transistor (N2) through which an input signal (IN) is operably received; a third P-MOS transistor (P2') having a drain, a gate and a body, and a fourth P-MOS transistor (P1') coupled in a stacked configuration with the third P-MOS transistor (P2') and having a gate, a source and a body, a third N-MOS transistor (N3) having a drain through which an output signal (OUT) is operably transmitted, a gate and a body and a fourth N-MOS transistor (N4) coupled in a stacked configuration with the third N-MOS transistor (N3) and having a source, a gate and a body, the drain of the third N-MOS transistor (N3) being coupled to the drain of the third P-MOS transistor (P2'), the gate of the third N-MOS transistor (N3) receiving the second clock signal ( CK ), the gate of the third P-MOS transistor (P2') receiving the first clock signal (CK), the gate of the fourth P-MOS transistor (P1') being coupled to the gate of the fourth N-MOS transistor (N4) and to the drain of the first N-MOS transistor (N1) and the source of the first P-MOS transistor (P2) to receive the output of the first N-MOS transistor (N1), the drain of the first N-MOS transistor (N1) and the drain of the third N-MOS transistor (N3) each including a graded drain extension (DE) and the drain of the second N-MOS transistor (N2) and the drain of the fourth N-MOS transistor (N4) not including a graded drain extension and being respectively connected in common with the source of the first N-MOS transistor (N1) and the source of the second N-MOS transistor (N3).

Inventors: DALLAVALLE CARLO, DALLAVALLE, CARLO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H03K19
IPC codes: H03K19, H01L21, H01L27