Microcomputer with test mode switching function

Abstract: This microcomputer provided with test mode switching function comprises execution controller (10) to control the operation of the operation unit (30) using microprogram, bus controller (40) connected via an internal bus (39) to the operation unit (30) and the execution controller (10) and test mode controller (20) to control the switching to test mode. The execution controller (10) has micro address generator (14) capable of generating a particular address to execute the microinstruction which separates the operation unit (30) from the internal bus (39) according to the test mode specification signal from the test mode controller (20). Alternatively, the execution controller (50) has instruction register (52) capable of outputting to the micro address generator (54) the instruction code of the microinstruction which separates the operation unit (70) from the internal bus (79).

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION This invention relates to a microcomputer comprising LSI and other similar devices, and particularly relates to a microcomputer which operates under microprogram control and is provided with test mode switching function. DESCRIPTION OF THE PRIOR ART In recent years, the application range of microcomputers (including one-chip microcomputers and one-chip microprocessors) consisting of LSI (large scale integrated circuit) or other similar devices is becoming more and more wider and covers office automation applications and home appliances. Under such circumstances, LSI for microcomputers is desired to have higher reliability. Conventionally, a test circuit for operation test is in advance incorporated into an LSI for effective and prompt selection of acceptable LSI devices. Recent LSI usually has its internal hardware divided into a plurality of functional blocks to be tested one by one so as to improve defect detection ratio and ensure high reliability. Particularly, in case of an LSI for microcomputers with various functions and complicated operation, it is necessary to test the internal blocks under a plurality test modes with switching the modes one by one. For this, an LSI requires a signal switching circuit to switch between usual operation and test, and the number of test circuits incorporated into the blocks tend to increase naturally. An example of a microcomputer with basic configuration and test mode switching is now briefly explained. Generally, a microcomputer comprises an execution controller to decode the instruction codes to be executed and control the sequence operation related to instruction execution using the internal microprogram, an operation unit for arithmetic logical operation such as addition or subtraction under control of the execution controller, a bus controller to input or output the instruction code and processing data to be processed at the execution controller and the operation unit via external bus terminals, and a test mode controller. These components are connected via internal buses. In such a microcomputer, for switching to the test mode to test the bus controller, for example, mode specification signal is sent from the test mode controller to entirely disable input of control signal from the execution controller and forcibly stop the operation of the operation unit. Under such condition, test vector is input and the execution result is output via external bus terminal and internal bus so as to test the bus controller. The number of control signal groups generated by microprogram at the execution controller in a microcomputer as mentioned above is over 100. Among them, several tens of signals are to specify the drive from the operation unit to the internal bus. In other words, even limiting to the signals which need disabling control for test, the number counts several tens. For example, when testing the bus controller, to prevent adverse affect on the test vector input to and the result output from the bus controller due to operation of the operation unit, hardware connected to the internal bus in the operation unit should be disabled to be driven on the bus. For this purpose, several tens of gate circuits need to be prepared in the test circuit corresponding to the number of control signals to suppress the control signal with the test mode signal. With complication of control for hardware function in a microcomputer, control signals as described above tend to increase more and more, causing the problem of overhead for the circuits required for tests. In addition, under the condition where the operation clock frequency is becoming higher and higher, delay of signal caused by insertion of gate circuits for test is another drawback. Thus, a test technique with reduced overhead for both hardware scale and performance is desired. EP-A-0 347 905 discloses a masking circuit which is inserted between a microinstruction register and a microinstruction decoder, causing the generation of NOP instructions in a test mode to stop any signals which could interfere with the testing of other circuit blocks. SUMMARY OF THE INVENTION It is an object of the present invention to provide a microcomputer which enables switching among test modes using the functions originally given to the microcomputer with eliminating the need of gate circuits to disable various control signals generated according to microinstructions and prevents the performance deterioration due to test circuit incorporation. Another object of the present invention is to provide an economic microcomputer with wide applications which is capable of test control irrespective of the number of control signals according to the microinstruction and which can realize a test circuit with minimum hardware even for high performance and for complicated control. According to a preferred embodiment of the present invention to attain the objects, a microcomputer is provided as claimed in claim 1. According to another preferred embodiment, microinstruction executed by the particular address data makes the control signals from the execution control unit to the operation means non-active. According to still another embodiment, the micro address generating means comprises an instruction decoder to decode the instruction code from the instruction register and gate circuits of which the number corresponds to the number of bits contained in the generated address, and output of the instruction decoder is input to the input terminal at an end of the gate circuit and the test mode signal is input to the input terminal on the other end of the gate circuit. Another preferred embodiment is provided as claimed in claim 4. According to another preferred embodiment, the instruction code output from the instruction register is a code corresponding to the microinstruction which makes the control signals from the execution control unit to the operation means non-active. According to still another embodiment, the instruction register has flip-flops of which the number corresponds to the number of bits contained in the instruction code and the test mode signal is input to the reset terminal of the flip-flop. Other objects, characteristics and effects of the present invention will be clarified in the detailed description below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram to show the configuration of a microcomputer provided with test mode switching function according to a first embodiment of the present invention; Fig. 2 is a schematic diagram to show a specific configuration example of the micro address generator; Fig. 3 is a flowchart to illustrate the operation of the microprogram performed by the inter-register addition instruction of the first embodiment. Fig. 4 is a flowchart of the operation in test mode according to the first embodiment; Fig. 5 is a block diagram to show the configuration of a specific configuration example of a microcomputer provided with test mode switching function according to a second embodiment of the present invention; Fig. 6 is a schematic diagram to show a specific configuration example of an instruction register according to the second embodiment; and Fig. 7 is a flowchart of the operation in test mode according to the second embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Figs. 1 to 7, preferred embodiments of the present invention are described below. Fig. 1 shows the configuration of a microcomputer having test mode switching function according to a first embodiment of the present invention. In Fig. 1, a microcomputer of this embodiment comprises an execution controller 10 to decode the instruction code to be executed and control the sequence operation related to instruction execution using internal microprogram, an operation unit for arithmetic and logical operation such as addition and subtraction under control by the execution controller 10, a bus controller 40 to input and output the instruction codes and processing data to be processed at the execution controller 10 and the operation unit 30 via an external bus terminal 42, and a test mode controller 20. The execution controller 10, the operation unit 30 and the bus controller 40 are mutually connected via an internal data bus 39. The operation unit 30 and the bus controller 40 are provided with usual operation mode and test mode. The execution controller 10 comprises an instruction register 12 to store the instruction code which is being executed, a control storage unit 13 to store microprogram where processing procedures of various instructions such as data transfer and arithmetic and logical operation are described with microinstructions (ROM or RAM, for example), a micro address generator 14 to one after another generate addresses in the control storage unit 13 of microinstructions to be executed according to the value in the instruction register 12 and a micro decoder 15 to decode the output from the control storage unit 13 and convert the microinstructions therein to signals to control the hardware units in the operation unit 30. The output from the control storage unit 13, i.e. some of the microinstructions may be used for address qualification at the micro address generator 14 for certain purposes including branch control of microprograms. The operation unit 30 comprises an ALU (Arithmetic and Logical Unit) 31 for arithmetic and logical operation, a general-purpose register group 32 to store processing data for user programs, a PSW (Program Status Word) storage unit 33 to store instruction execution statuses and operation result statuses, a PC (Program Counter) 34 to indicate the address of the instruction which is being executed and a temporary register group 35 used for processing of instruction according to the microinstructions. These components are connected to the internal data bus 39. The micro decoder 15 outputs control signals supplied to the hardware units in the operation unit 30. Specifically, they are control signal S12, control signal S13, control signal S14, control signal S15 and control signal S16, which respectively specify the internal status of the ALU 31, the general-purpose register group 32, the PSW storage unit 33, the PC 34 and the temporary register group 35 as the operation driven to the internal data bus 39 when the logical value is "1". Control signals (not shown) to the operation unit 30 in addition to these, signals for ALU 31 to specify the operation form such as addition and subtraction, selection signals for the general-purpose register group 32 and selection signals for the temporary register group 35 using several tens of signal lines. In Fig. 1, only five control signals from S12 to S16 are shown for the sake of convenience. The bus controller 40 is connected to the instruction register 12 of the execution controller 10 via an instruction bus 41. The instruction code fetched from an external memory or main storage (not shown) via the external data bus terminal 42 is stored in the instruction register 12. The bus controller 40 is also connected to the internal data bus 39. Processing data in the external memory are accessed with the control signal from the execution controller 10 via the bus controller 40. The test mode controller 20 decodes the status of a mode specification terminal group 21 and generates a test mode signal S22 to specify either of usual instruction execution mode or test mode. The test mode signal S22 is given to the micro address generator 14 in the execution controller 10. When the logical value of the test mode signal S22 is "0", the micro address generator 14 enters the usual instruction execution mode and generates the micro address to invoke from the control storage unit 13 the microinstruction to be executed according to the value from the instruction register 12. When the logical value of the test mode signal S22 is "1", it generates a particular micro entry address to invoke a particular microinstruction as described later irrespective of the instruction code from the instruction register 12. Fig. 2 shows a specific configuration example of this micro address generator 14. In the configuration shown in the figure, eight bit instruction code is input from the instruction register 12 and nine bit micro address is generated. The micro address generator 14 comprises an instruction decoder 140 to decode the instruction code from the instruction register 12 and a special address output unit 141 to generate the particular micro entry address as mentioned above. The special address output unit 141 consists of OR circuits 143 and AND circuits 144, the number of which corresponds to the bit length of the address as shown in the figure. To these OR circuits 143 and AND circuits 144, both the output from the instruction decoder 140 and the test mode signal S22 above are input and the OR/AND circuits output the logical sum or logical product of those input data. The terminal for input of the test mode signal S22 in AND circuits 144 is a low active input terminal. In this configuration, when the test mode signal S22 has a logical value of "0", the output of the instruction decoder 140 is output to the control storage unit 13 as it is. When the test mode signal S22 has a logical value of "1", a particular micro entry address "1EOH" (H indicates that this value is given in hexadecimal notation) is always output irrespective of the value at the instruction decoder 140. The particular micro entry address is "1EOH" in this embodiment, but it is not limited to this value. The special address output unit 141 may be designed to output a different address value. Referring to the flowchart of Fig. 3, an example where the above microcomputer is operated by microprogram of register addition instruction is described below. Suppose the instruction code of the register addition instruction is "88H" (H indicates that this value is in hexadecimal notation) and the micro address generator 14 generates "088H" as the entry address according to the value of the instruction code stored in the instruction register 12. Thereafter, the micro address generator 14 increases the address by an increment of 1 for each step execution and generates micro addresses "089H", "08AH" ... In Step 30 with the micro address "088H", the value of the register R0, which belongs to the general-purpose register group 32, is read out to the internal data bus 39 and set to the first input ALU (A) of the ALU 31. Similarly, in Step 31 with the micro address "089H", the value of the 32 is register R1 in the general-purpose register group 32 is set to the second input ALU (B). Then, in Step 32 with the micro address "08AH", the microinstruction "ADD" specifies addition to the ALU 31 for operation execution. After that, in Step 33 with the micro address "08BH", the result of addition is rewritten to the register R1 in the general-purpose register group 32 via the internal data bus 39, and upon completion of the processing, the microinstruction "END" specifies the address generation operation with the value in the instruction register 12 for next instruction execution. Switching to test mode is now described. When the test mode signal S22 from the test mode controller 20 has a logical value "1", as described above, the micro address generator 14 generates "1E0H" as a micro entry address. Fig. 4 is a flowchart of the operation in test mode. In Step 34 with the micro entry address "1E0H", all the control signals S12 to S16 and others generated by the micro decoder 15 are made to be non-active by execution of the microinstruction "NOP" (No operation). After that, by withholding any execution of microinstruction, the execution of Step 34 continues without any new execution of instruction. Therefore, in test mode, all of the above control signals S12 to S16 and other control signals to instruct the operation unit 30 what to drive to the internal data bus 39 have a logical value "0", which results in no driving from the operation unit 30 to the internal data bus 39. Similarly, the control signal (not shown) connected to the bus controller 40 becomes non-active. However, the operation of the bus controller 40 is controlled by test vectors input from outside via the external bus terminal 42 in test mode, and these control signals cannot be used with switching to the external terminal 42. As described above, the control signals S12 to S16 and other control signals become non-active in test mode, which results in separation of the operation unit 30 from the internal data bus 39. With this, the bus controller 40 can be independently tested without suffering from affect from the operation unit 30. Here, the microinstruction "NOP" in the flowchart of Fig. 4 is identical to the NOP instruction the microprogram originally has. The micro entry address for test mode is "1E0H" in this embodiment, but it is needless to say that any address may be assigned. Fig. 5 is a block diagram to show the configuration of a microcomputer according to a second embodiment of the present invention. A microcomputer of this embodiment comprises, similarly to the embodiment of Fig. 1, an execution controller 50, an operation unit 70, a bus controller 80 and a test mode controller 60. The execution controller 50, the operation unit 70, the bus controller 80 are mutually connected via an internal data bus 79. The operation unit 70 and the bus controller 80 are provided with usual operation mode and the test mode. The execution controller 50 comprises an instruction register 52 to store the instruction code, a control storage unit 53 to store microprogram where processing procedures of various instructions are described with microinstructions, a micro address generator 54 to generate addresses of microinstructions to be executed according to the values of the instruction register 52 and a micro decoder 55 to decode the output from the control storage unit 53 and convert the microinstruction therein to signals to control the hardware units in the operation unit 70. The output from the control storage unit 53, i.e. some of the microinstructions may be used for address qualification at the micro address generator 54 for certain purposes including branch control. The operation unit 70 comprises an ALU 71 for arithmetic and logical operation, a general-purpose register group 72 to store processing data for user programs, a PSW (Program Status Word) storage unit 73 to store instruction execution statuses and operation result statuses, a PC (Program Counter) 74 to indicate the address of the instruction which is being executed and a temporary register group 75 used for processing of instructions according to microinstructions. These components are connected to the internal data bus 79. The micro decoder 55 outputs control signals supplied to the hardware units in the operation unit 70. Specifically, they are control signal S52, control signal S53, control signal S54, control signal S55 and control signal S56, which respectively specify the internal status of the ALU 71, the general-purpose register group 72, the PSW storage unit 73, the PC 74 and the temporary register group 75 as the operation driven to the internal data bus 79 when the logical value is "1". Control signals (not shown) to the operation unit 70 in addition to these include signals for ALU 71 to specify the operation form such as addition and subtraction, selection signals for the general-purpose register group 72 and selection signals for the temporary register group 75 using several tens of signal lines. In Fig. 5, only five control signals from S52 to S56 for the sake of convenience. The bus controller 80 is connected to the instruction register 52 of the execution controller 50 via an instruction bus 81. The instruction code fetched from an external memory or main storage (not shown) via the external data bus terminal 82 is stored in the instruction register 52. The bus controller 80 is also connected to the internal data bus 79. Processing data in the external memory are accessed with the control signal from the execution controller 50 via the bus controller 80. The test mode controller 60 decodes the status of a mode specification terminal group 61 and generates a test mode signal S62 to specify either of usual instruction execution mode or test mode. The test mode signal S62 is given to the instruction register 52 in the execution controller 50. When the logical value of the test mode signal S62 is "0", the instruction register 52 of the execution controller 50 enters the usual instruction execution mode and outputs to the micro address generator 54 the value of the instruction code fetched via the instruction bus 81. Fig. 6 shows a specific configuration example for this instruction register 52. In the figure, eight bit instruction code sent from the bus controller 80 via the instruction bus 81 is input. The instruction register 52 comprises, as shown in the figure, D-type flip-flops 152 of which the number corresponds to the number of bits in the instruction code (8). To the reset terminal R of this D-type flip-flops 152, the test mode signal S62 is input. In this configuration, when the test mode signal S62 has a logical value "0", the bits corresponding to the instruction code from the instruction bus 81 are output to the micro address generator 54. When the test mode signal S62 has a logical value "1", D-type flip-flops 152 are reset and, irrespective of the instruction code value from the instruction bus 81, the value "00H" (H means that this value is given in hexadecimal notation) is always output as a particular instruction code (NOP instruction code). Operation of this embodiment for usual instruction execution mode where the micro address generator 54 generates entry address of micro program according to the value stored in the execution register 52 is the same as in the first embodiment, and detailed description is omitted. When the test mode signal S62 has the logical value of"1", the instruction register 52 switches the instruction code for output stored inside and outputs "00H", which is an instruction code for the microinstruction "NOP" of microprogram. The micro address generator 54 generates "000H" as the micro entry address for the microprogram of microinstruction "NOP" correspondingly. Fig. 7 is a flowchart illustrating the operation of "NOP instruction". In Step 70 where the micro entry address is "000H", the microinstruction "NOP" invoked from the control storage unit 53 makes all control signals S52 to S56 generated by the micro decoder 55 and other control signals non-active. At the same time, the microinstruction "END" is executed so that the address generation operation is specified to the micro address generator 54 using the value at the instruction register 52 in order for execution of the next instruction. While the test mode signal S62 has a logical value "1", the instruction register 52 continues to output the instruction code "00H" which cause the microinstruction "NOP" is continuously executed in test mode. By continuation of the microinstruction "NOP", all of the control signals S52 to S56 and other control signals mentioned above has the same logical value "0", which results in no driving from the operation unit 70 to the internal data bus 79. The control signals (not shown) connected to the bus controller 80 are also made to be non-active. However, in test mode, the operation of the bus controller 80 is controlled by the test vectors input from the external terminal 82, and these signals are not used with switching to the external terminal 82. As described above, as in the first embodiment, the operation unit 70 is separated from the internal data bus 79 in test mode. This enables independent testing of the bus controller 80. In this embodiment, the instruction code and the micro entry address is "00H" and "000H" respectively, but any number can be assigned. As described above, this invention provides a microcomputer where signals can be made non-active by the operations originally furnished in the unit without adding gate circuits to disable various control signals generated according to microinstructions requiring high-speed operation and eliminates the deterioration of performance caused by test circuit incorporation. In addition, this invention realizes control for test irrespective of the number of control signals according to microinstructions, which enables preparation of test circuits with minimum hardware even with microcomputers with high performance and complicated control so that economic and general-purpose microcomputers can be provided. Obviously many modifications and variations of the present invention are possible.

Claims: A microcomputer provided with test mode switching function comprising: operation means (30; 70) for performing arithmetic and logical operations and selectively accessing an internal bus (39; 79) depending upon a control signal (S12 to S16; S52 to S56); execution control means (10; 50) to control the operation of said operation means (30; 70) using a microprogram; bus control means (40; 80) which are connected via said internal bus (39; 79) to said operation means (30; 70) and said execution control means (10; 50) and which input or output various instructions and processing data; and test mode control means (20; 60) to control switching for test mode, said execution control means (10; 50) being provided with a control storage unit (13; 53) to store the microprogram and with a micro decoder (15; 55) for outputting said control signal (S12 to S16; S52 to S56) depending upon the microprogram read out from said control storage unit (13; 53); CHARACTERIZED BY said execution control means (10; 50) further containing an access unit (12, 14; 52, 54) comprising an instruction register (12; 52) storing the instruction to be executed, micro address generating means (14; 54) for generating a micro address signal for said control storage unit (13) depending upon said instruction, a special data output unit (141,152) being connected either to the instruction register (12; 52) or to the micro address generating means (14; 54) responsive to a test mode signal (S22; S62) from said test mode control means (20; 60) for generating a predetermined test instruction or micro address in the access unit (12, 14; 52, 54) irrespective of the normal operation instruction or micro address; said control signal (S12 to S 16; S52 to S56) being set in a predetermined logical state when the microdecoder (15; 55) receives predetermined microprogram instructions read out of the control storage unit (13; 53) in response to said predetermined test instruction or micro address; wherein said predetermined logical state does not trigger any action in said operation means and thus inhibits access of said operation means (30; 70) to said internal bus (39; 79). A microcomputer provided with test mode switching function of Claim 1 wherein said access unit (12, 14) comprises an instruction register (12) storing instruction to be executed; micro address generating means (14) for generating said address signal for said control storage means (13) depending upon said instruction, wherein said test mode control means (20) are connected to said micro address generating means (14), and said micro address generating means (14) are responsive to said mode signal (S22) and generating said predetermined address signal irrespective of said instruction for supplying to said control storage means (13). A microcomputer provided with test mode switching function of Claim 2 wherein said micro address generating means (14) comprises an instruction decoder (140) to decode the instruction code from said instruction register (12) and gate circuits (143,144) of which the number corresponds to the number of bits contained in the generated address, and output of said instruction decoder (140) is input to the input terminal at an end of said gate circuit (143,144) and said test mode signal is input to the input terminal on the other end of said gate circuit (143,144). A microcomputer provided with test mode switching function of Claim 1 wherein said access unit (52, 54) comprises an instruction register (52) storing instruction to be executed; micro address generating means (54) for generating an address signal for said control storage means (53) depending upon said instruction; wherein said test mode control means (60) are connected to said instruction register (52); said instruction register (52) is reset by said mode signal (S62) and converting the stored instruction into a predetermined first instruction and storing the first instruction to said micro address generating means (54); and said micro address generating means (54) generating the address signal depending upon said first instruction and supplying said control means (60). A microcomputer provided with test mode switching function of Claim 4 wherein said instruction code output from said instruction register (52) is a code corresponding to the microinstruction which makes the control signals from said execution control means (50) to said operation means non-active. A microcomputer provided with test mode switching function of Claim 4 wherein said instruction register (52) has flip-flops (152) of which the number corresponds to the number of bits contained in the instruction code and said test mode signal is input to the reset terminal of said flip-flop (152).

Inventors: KATSUTA HIROSHI, KATSUTA, HIROSHI, KATSUTA, HIROSHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G06F11
IPC codes: G06F11, G06F9, G06F15