Echo cancellation system

Abstract: A circuit architecture suitable for use in a television receiver which effectively performs a ghost or echo cancellation procedure on post-echo components and pre-echo components occurring within the transmission channel. The apparatus features a filter circuit architecture which can be configured under programmed control so as to partition groups of its filter sections to form IIR filters and FIR filters. The filter architecture is suitable for use in multi-circuit configurations and can be used with clustering algorithms to increase the efficiency and optimize the use of the available circuit architecture.

Description: The invention relates to an echo cancellation system in which an information signal comprising a ghost cancellation reference (GCR) signal is received from a transmission path having a distortion characteristic which adds at least one echo component to the information signal. In 1979 the IEEE published an article which has become a basic reference in the field of television echo (or "ghost") elimination. The article is entitled "A Tutorial On Ghost Cancellation In Television Systems" and was written by Walter Ciciora, Gary Sgrignoli and William Thomas. Although the Ciciora article described the fundamental principles, apparatus and algorithms applicable to ghost cancellation, the state of the art has only recently progressed to the point of providing practical ways to implement and improve these basic concepts. The European Patent Application EP-A-0,448,352, published 25.09.91, discloses a transversal equalizer having first and second transversal filters each including a plurality of adders and a set of multipliers, each of which equalizes input sample values based on tap coefficients applied to the multipliers and outputs the resulting signal, a switch which connects the first output signal from the first transversal filter to either the input of the second transversal filter or to a combining circuit in the second transversal filter, the combining circuit combining any signal from the switch with the signal being processed in the second transversal filter. The European Patent Application EP-A-0,417,861 provides an example of a signal processor architecture which can be programmed to perform varied filter and other complex digital processing operations utilizing programmed sequences of coefficients and control words. The non-prepublished European Patent Application EP-A-0,450,720, published 09.10.91, describes an echo cancellation apparatus which can effectively be implemented with the instant invention. There are two main steps to the echo cancellation process. First the characteristics of the communication channel (which include the echo artifacts, if any) must be determined at the receiver. Once the channel characteristics are calculated, filters are used to implement the inverse channel to perform the echo cancellation. Because the channel characteristics may include more than one type of echo, each of being preferably processed differently, a need exists for a circuit architecture, which among other things, provides the ability to programmably optimize a desired filter architecture for the derived channel characteristics with the speed necessary to be effective in a real time communication system. It is therefore an object of the invention, to provide a circuit architecture which lends itself to rapid filter array configuration under programmed control. A received video signal contains echoes which are comprised of superimposed copies of the originally transmitted signal, which have different delay times and amplitudes. The strongest signal component represents the originally transmitted, or "main" signal component. Looking in the time domain, any copy component occurring before the main signal component is called a "pre-echo" component and any copy component occurring after the main signal component is called a "post-echo" component. An infinite impulse response (IIR) filter is inherently causal in nature and therefore cannot be used to cancel pre-echoes. An IIR filter can, however, effectively be used to substantially cancel post-echoes. A finite impulse response (FIR) filter, can be both causal and non-causal. The non-causality allows cancellation of pre-echoes. An FIR filter however, cannot perform ideally unless it is of infinite length. A practical (i.e. finite length) FIR filter will therefore only suppress, but not completely cancel, the pre-echoes. The longer the FIR filter however, the better the pre-echo will be suppressed. A practical echo cancellation circuit should include therefore, an FIR filter to suppress the pre-echoes followed by an IIR filter to suppress the remaining post-echoes. It is therefore another object of the invention to provide an echo cancellation circuit which includes both IIR and FIR filters for effective cancellation of both post-echoes and pre-echoes. The bandwidth of a standard television channel, for example an NTSC channel, is about 4.2 MHz. Any digital processing therefore has to be done at a rate of 8.4 MHz or more in order to meet the Nyquist sampling criterion. Often the processing of composite baseband NTSC signals is done at a 14.32 MHz rate, which is four times the frequency of the color subcarrier. All echoes, for the most part, fall in a range of - 3.5 µs to + 45 µs with respect to the main signal component in the time domain. For third order cancellation of pre-echoes therefore, the FIR filter should span about 10.5 µs and the IIR filter should span about 45 µs. At the 14.32 MHz sample rate for example, this would require the FIR filter to have 150 taps and the IIR filter 645 taps. These would be large and expensive filters. Fortunately, there is a tendency for the dispersed echo components to "cluster" and this property permits the design and use of filters (known as "sparse" filters) which do not require filters at every tap. Since echoes are dispersive, several taps are required to cancel them. Echoes with a phase shift in the RF domain, and echoes that do not exactly coincide with sample moments, also require multiple taps to be cancelled effectively. Taking advantage of the tendency of the dispersed echoes to cluster, each echo can be cancelled by a cluster of filter taps. It is therefore another object of the invention to provide an architecture suitable for the implementation of sparse filters. The instant invention comprises a circuit architecture which is suitable for use as an echo (ghost) cancellation circuit in conjunction with, or as part of, a television receiver. Principal aspects of the invention are set out in Claims 1 and 2, while advantageous embodiments are set out in the subclaims. One feature of the circuit architecture of the invention, is that it consists of a number of filter taps and a number of programmable delay lines which are assigned under programmed control. Still another feature of the circuit architecture is that the taps can be clustered and positioned in time, to coincide with an echo component in order to substantially cancel it. Another feature of the circuit architecture of the invention is that both FIR and IIR filters can be configured and a flexible FIR/IIR boundary can be configured under programmed control. Still another feature of the circuit architecture of the invention is that the FIR/IIR boundary can be changed in real time so that the resources of the architecture are always optimally used. Still another feature of the invention is that dual input and output busses are provided which enable the various filter sections to be assigned to either an FIR or IIR function. Yet another feature of the circuit architecture of the invention is a common delay line. Another feature of the circuit architecture of the invention is that it provides means for implementing a scaling algorithm in the calculation of coefficients to allow for greater bit accuracy in the filter processing. The invention also comprises a method for selecting the coefficients for a clustered filter which is suitable for use with an embodiment of a sparse filter utilizing the circuit architecture of the invention. These and other objects and aspects of the invention will be more apparent from and elucidated with reference to the embodiments described hereinafter. In the drawings: Figure 1 is a block diagram of an echo cancellation subsystem utilizing both FIR and IIR filters; Figure 2 is a block diagram of a color television receiver comprising an echo cancellation subsystem; Figure 3 is a block diagram of an embodiment of an echo cancellation subsystem comprising the invention; Figure 4 is a block diagram of the circuit architecture of the echo cancellation filter shown in Figure 3; Figure 5 is a block diagram of the final adder circuit shown in Figure 4; Figure 6 is a block diagram of the interface and global register circuit shown in Figure 4; Figure 7 is a block diagram of the global delay circuit shown in Figure 4; Figure 8 is a block diagram of the select circuit shown in Figure 4; Figure 9 is a block diagram of a filter stage shown in Figure 4; Figure 10 is a block diagram of one of the taps of the filter stage shown in Figure 9; and Figure 11 is a block diagram of an embodiment of the filter circuit shown in Figure 4 utilizing two circuit blocks. Because of the complex environment associated with terrestrial television broadcasting, the characteristics associated with echo phenomena can consist of a main signal component, a number of pre-echo signal components and a number of post-echo signal components. Because the number and variety of echo signal components change subject to changes within the communication channel and are therefore not easily predicted, an effective echo cancellation subsystem must be adaptive in nature and must be able to periodically configure itself to meet the specific requirements of the echo pattern. Figure 1 describes in block diagram form, an echo cancellation subsystem which includes both FIR and IIR filters. The FIR filter 15 is used to cancel pre-echo signal components and close post-echo components and the IIR filter 20 is used to cancel post-echo signal components. Video signals are received and digitized in A/D converter 10 and a ghost cancellation reference signal (GCR), periodically sent (during the vertical blanking interval for example), is extracted and processed by the buffer 30 and processor 25 using an algorithm designed to provide the appropriate inverse channel coefficients to filters 15 and 20. The non-prepublished US Patent US-A-5,047,859 (published on 10 September 1991) describes a preferred method and apparatus for calculating the appropriate coefficients. Processor 25 is also used to configure the taps of the filter circuits 15 and 20 in order to more efficiently match the clustered nature of the echo signal phenomenal. The analysis of the channel characteristics and the calculation of the necessary filter coefficients takes place each time the apparatus comprising the invention is turned on, each time the channel being received is changed and periodically after the GCR signals from a number of fields of the video signals are received and averaged. This can be every eight fields for example. After the channel coefficients are calculated, a subset of the coefficients is chosen to reflect the clustering of the echo signals. A preferred clustering algorithm is detailed hereinbelow. Each time the channel characteristics are analyzed, the respective numbers of pre and post-echo components are determined and the filter section resources of the filter circuit of the cancellation subsystem, in accordance with the instant invention, are optimized for maximum cancellation and efficiency by providing configuration data which adapts the subsystem architecture into the required number of FIR and IIR filters. After the configuration data and the coefficients are determined, they are sent to the filter circuit (as described more completely below). Figure 2 describes in block diagram form, a color television receiver which includes an echo cancellation subsystem 100. An antenna on CATV signal from input 139 is applied to an RF tuner 140 and subsequently to an IF stage 141. If stage 141 supplies sound signals to a sound processor 142 and CVBS (video) signals to an echo cancellation subsystem 100. The echo cancellation subsystem applies filtered CVBS signals to a color decoder 143 and to a vertical and horizontal deflection and high voltage circuit 144. Outputs of the decoder 143 and the circuit 144 are coupled to a color picture tube 145. Figure 3 is a block diagram of a preferred embodiment of the echo cancellation subsystem 100 shown in Figure 2. As described in connection with Figure 3, a color baseband video signal including a periodic GCR signal is provided to buffer 151 from RF/IF demodulation stages 140 and 141 shown in Figure 2. Sync signals from the video signal are processed in known fashion by PLL 158 to provide a sampling clock signal for A/D converter 10 which receives the clamped and low pass filtered analog video signal from clamp and LPF circuits 153 and 154. An echo cancellation filter circuit 200 having an architecture in accordance with the invention, and preferably in the form of an integrated circuit, is used to provide the FIR and IIR filter sections. Filter circuit 200 is periodically reloaded with coefficients calculated by processor 25 which can be a microprocessor or digital signal processor (DSP). The algorithms used to derive the coefficients are stored in a memory which can be part of the processor 25. The processor also provides control words which configure and implement the functions of the filter circuit 200 as described in more detail below. Processor 25 further receives clock signals from PLL 158 and synchronizing data (odd/even) from sync circuit 160, whose input is coupled to buffer circuit 151. Memory 155 is used to store the GCR during the calculation of the coefficients. Although memory 155 is shown at the output of filter circuit 200, the GCR in its unprocessed form is made available to the processor 25 by periodically bypassing the filter circuit 200. Placing the memory 155 at the filter circuit output allows the processed version of the GCR to be accessible to processor 25 as well. The output of filter circuit 200 is provided to D/A converter 35 and LPF/buffer 156. Figure 4 is a detailed block diagram of the filter circuit 200 comprising an integrated circuit architecture in accordance with one embodiment of the invention. The filter circuit 200 comprises nine filter sections indicated as Sect 0-8. Each filter section comprises a section configuration register 600, an input select circuit 700 and a filter stage 800 comprising a plurality of taps (e.g. twenty). An interface circuit 900 receives data from processor 25 which includes coefficient data and configuration data, and provides control words and coefficients to the rest of the filter circuit 200. Final adder circuit 400 provides circuit input, output, summation and scaling functions for the filter circuit 200, under the control of control words provided by interface circuit 900. A global delay circuit 500 provides fixed delays for the FIR and IIR inputs as discussed in more detail below. Filter circuit 200 operates alternatively in two modes under the control of processor 25. The first mode is the configuration mode during which configuration data and coefficients derived by processor 25 are loaded into filter circuit 200, and the second mode is the filter mode which is the normal operating mode in which echo cancellation takes place. When a device comprising the invention, for example a television receiver, is first turned on, when the channel selector is activated, and periodically (i.e. every eight fields) during the operation of the device, the averaged GCR signal in memory 155 (Figure 3) is processed by processor 25. Coefficients are calculated by the processor 25 together with configuration data determining, among other things, which of the filter sections will be configured to form an FIR filter and which of the filter sections will be configured to form an IIR filter. The setting of time delays for each of the filter stages 200 is also controlled by the derived control data, so as to affect the placement in time of each of the limited number of taps in order to coincide with the pre- and post-echo components generated by the channel disturbances. During the configuration mode, configuration data and the coefficients are loaded into the filter stages. Once this is finished, the filter circuit is switched to the filter mode. Configuration data as well as coefficients are provided to interface circuit 900 by processor 25 on two busses; an address bus labelled A <2;0> and a data bus labelled DATA <7:0>. A number of other inputs are provided to the interface circuit 900 to provide the necessary communication with other integrated circuits in the subsystem. The purpose of these inputs are summarized as follows: The READ input specifies if the microprocessor cycle is a read or a write. This input is sampled, for example, at the rising edge of the STROBE signal. The CS and CHIP-No. inputs are used in conjunction with the signal on one bit of A <2:0> to select one filter circuit 200 in a multi-circuit configuration. The CHIP-No. input is used to differentiate between the main and a cascade filter circuit 200 in multi-circuit implementations, shown for example in Figure 11. The CHIP-No. input is asserted for one of the circuits and deasserted for the other. These inputs are all sampled, for example, on the rising edge of the STROBE signal. A particular filter circuit 200 is selected only if CS is asserted and A <2> is equal to the CHIP-No. of the selected filter circuit. If this chip is selected, then A <1:0> specifies which internal register of interface circuit 900 is read or written to. The RESET signal resets the internal state of the chip, and the clock generators. All filter section configuration registers 600 are reset to a known state, and the input clock generator is reset and waits for the first CLK before starting up. All microprocessor requests in progress are aborted and ignored. The STROBE signal clocks all the signals input to the interface circuit 900 except for RESET. The active edge of this clock is the rising edge, for example. The configuration and operation of the filter circuit 200 will now be explained in the following example wherein three of the Sections (6-8) are configured to form a FIR filter and six of the Sections (0-5) are configured to form an IIR filter. FILTER MODE As shown in Figure 5, the video signal X from A/D converter 10 enters the filter circuit at the input 209 of final adder circuit 400, as a nine bit signed value. One sample is provided each sample clock time as generated by clock 158 (Figure 3). In order to conserve chip real estate the illustrated embodiment processes video input samples as eight bit words. For greater accuracy, it can however utilize a nine-bit sample input. To do so, input signal X is rounded and its range is limited in rounding and limiting circuits 401 and 403 respectively, so as to convert its nine bit signed value to an eight bit signed value. The eight bit value is then provided at output 211 and designated as a . Signal a is fed to global delay line 500 (Figure 4) shown in more detail in Figure 7. In Figure 7, FIR delay line 511 processes signal a and provides two outputs, one being signal a with no delay, and one being a delayed version of signal a having a fixed delay of 64 sample times. The zero delay output appears on the first eight bits (203a) of bus 203 and the delayed output appears on the last eight bits (203b) of bus 203. As shown in Figure 8, the delayed and non-delayed FIR input signals are provided to multiplexer 705 of input select circuit 700 (Figure 4). As discussed in more detail below, control word e comprises twelve control bits provided by the interface circuit 900 (Figure 4), to each section configuration register 600 (Figure 4). One control bit of control word e selects one of the two FIR input signals to multiplexer 705 to provide either a delayed or an undelayed signal a to a first input of multiplexer 707. The second input to multiplexer 707 is the IIR signal output (as discussed in more detail below). As shown in Figure 4, each input select circuit 700 provides an input signal d to its respective filter stage 800. Signal d is a delayed version of the output of multiplexer 707 (Figure 8) which is selected by another control bit of control word e . The output of multiplexer 707 is coupled to local delay line 704 which provides an additional delay of from zero to 63 samples, selected by six control bits of control word e . Output signal d of local delay line 704 therefore is the sample X which has been rounded and limited an provided with a total amount of delay determined by the fixed delay provided by global delay line 500 (Figs. 4,7) and a programmable delay provided by delay line 704 (Figure 8). The effective delay for each of the filter sections 6, 7 and 8 may be different. As stated above, the instant invention can be configured to perform both FIR and IIR filter functions. The boundary between the respective groups of filter sections, i.e. between section 5 and section 6 in the instant example is set by choosing a zero value as a sum or coefficient input 806 to the first filter stage (tap 0) of the 20 filter stages 810 of filter section 6 as shown in Figure 9. The filter stages 810 filter the samples d supplied from delay 704 of Figure 8, as shown in more detail in Figure 10 described below. Multiplexer 805 has two inputs. The first input 801 is either a coefficient provided during the configuration load mode or the cascade output 807 from the preceding filter section. The second input 811 to multiplexer 805 is a zero value. The output of multiplexer 805 is selected by another control bit of control word e . In the instant example, the output of filter section 6 provided at its cascade/coefficient output 807 is coupled to cascade/coefficient input 801 of section 7 and the cascade/coefficient output 807 of filter section 7 is coupled to the cascade/coefficient input 801 of section 8. The sum or coefficient output 812 of the last filter stage of filter section 6 is provided to the cascade/coefficient output 807 and to gates 813 and 814. Gate 813, when enabled by another control bit of control word e , passes the output to the FIR Sum bus 207. Sections 6, 7 and 8 thus form a continuous FIR filter with a total of 60 taps (20 each from sections 6, 7 and 8). As shown in Figure 5, FIR Sum bus 207 is coupled to sealer 407 of final adder 400. During the sampling of the video signal, known scaling techniques can be used to increase the effective bit accuracy of the coefficients. Scaler 407, under the control of control word g , provides a compensating factor (as described in more detail below) to restore each sample to its proper level. Scaler 420 performs the same function on the IIR sum bus signal under the control of control word g . The sealer 407 can be simple barrel shifter which functions as a multiplier. Its setting depends on the level of actual coefficients. The output of scaler 407 can then be added to a sealed version of the signal provided by the IIR Sum bus 205 (Figure 4) and the output of unity gain delay 405, in summer 408. The output of summer 408 is then rounded off and limited in circuits 409 and 410 respectively and provided as one input to multiplexer 415 which provides the nine bit output of filter circuit 200, Y <8:0>. If in rounding out the signal the result is out of range this condition will be indicated by asserting a chip signal overflow flag OVERFL. In Figure 4, filter sections 0 through 5 are configured to form an IIR filter. The output signal from summer 408 (Figure 5) is rounded off and limited in circuits 421 and 422 to form signal b which is coupled to IIR delay line 515 (Figure 7) of global delay circuit 500. Signal b , as provided by summer 408, provides the feedback loop necessary for an IIR filter. As shown in Figure 7, delay line 515 provides eight fixed delay versions of signal b on bus 201, each having a different delay time from O to 448 samples. Bus 201 which provides the IIR input, is coupled to multiplexer 717 (Figure 8) of each input select circuit 700. In the instant example, sections O through 5 (Figure 4) are arranged as an IIR filter. This, in effect, causes a clustering of the taps wherein the separation of the clusters will be determined by the difference in the effective delay values. The choice of delay is made by multiplexer 717 under the control of three control bits of control word e . As shown in Figure 9, as in the case for the FIR filter sections, the first of the IIR sections, i.e. filter section 0, must have a zero value as a sum or coefficient input 806 to its first filter stage 810 (tap 0). As described above with respect to filter section 6 of the FIR filter, multiplexer 805 selects either the cascade/coefficient input 801 or a zero value 811, as the sum or coefficient input to tap 0 filter stage 810 of filter section 0, in response to a control bit of control word e . The sum or coefficient output 812 of filter section 5 is coupled to cascade coefficient output 807 and to gates 813 and 814. Gate 814, when enabled by another control bit of control word e , passes the output of filter section 5 to the IIR sum bus 205. The sum or coefficient output of filter section O feeds the sum or coefficient input of filter section 1 and so on in order to form, in this example, an IIR filter with 120 taps. As shown in Figure 5, the IIR sum bus 205 is coupled to scaler 420 of the final adder 400 where it is sealed and added to the output of the FIR sealer 407 and the output of unity gain delay 405 in summer 408. An input unity gain delay 405 consists of a delay which enables the setting of a position of a coefficient of value one. This position is considered the so-called unity gain tap in the FIR. The unity gain tap allows the use of a large scaler factor at the output of the FIR sum bus by removing the only large coefficient in the FIR filter. Multiplexer 415, under the control of a control bit of control word g , can be used to output an unprocessed but delayed version of the input video signal from input unity gain delay 405. CONFIGURATION MODE As shown in Figure 4 and described above, interface circuit 900 provides configuration data to each section configuration register 600 on bus 918 as well as to the final adder 400. It also provides coefficient data to each of the filter stages 800 on bus 915. Figure 6 shows a more detailed version of interface circuit 900 consisting of a plurality of registers providing 8 bits of coefficient data, 12 bits of configuration data and 4 bits of address data. As viewed by a programmer, there are two levels of registers in the filter circuit 200. The first level consists of three registers 902, 904 and 906 which have respectively register addresses 0, 1 and 2. A fourth register 908 is also provided in the illustrated embodiment but is, at present, unused. The address provided at the A <2:0> port of interface circuit 900 determines which of these registers the data provided on the data port DATA <7:0> are written into. In a multi-circuit system such as the one illustrated in Figure 11, one bit (A <2>) selects the filter circuit 200, and the remaining bits (A <1:0>) selects the register (902, 904, 906 or 908). All registers 902-908 are coupled to a chip interface CIF. The second level of registers in filter circuit 200 comprises: (a) a first group of registers comprising each register 815 present in each of the taps 810 (Figure 10) in each of the filter sections. Each register 815 actually comprises a plurality of holding registers (for example 180) for storing coefficients to be loaded into each tap (as explained in greater detail below); (b) a single global configuration register 910 (Figure 6) which is part of the interface circuit 900, which stores the configuration data forming control words h and g; and (c) a second group of registers comprising the nine section configuration registers 600, one for each filter section, which store the configuration data forming control word e . Table I describes the addressing and bit assignment for registers 902 through 908. The registers 902 through 908 each store eight bits of data. Address A <1:0> Name Bits Usage of bits 0 Coefficient <7:0> Signed coefficient values 1 Configuration-Low <7:0> Low 8 bits of 12 bit configuration data 2 Configuration-High <3:0> Top 4 bits of 12 bit configuration data Global/Configuration Register Address <7:4> Internal address for selecting global or configuration register (*see Table II) 3 Test Miscellaneous use Register 902 holds eight bits of coefficient data provided to each of the filter stages 800 (Figure 4) as a coefficient input 815 on bus 915. Coefficient data is made available to interface circuit 900 at its DATA <7:0> port, from processor 25. The address provided at A <2:0> by the processor 25, selects register 902 as the destination for the coefficient data. Configuration data is provided to eight bit registers 904 and register 906 from processor 25 through the DATA <7:0> port. Register 904 holds eight bits of configuration data and register 906 holds four bits of configuration data and an additional four address bits to select which of the second group of section coefficient registers 600 or the global register 910 receives the twelve bits of configuration data as described in Table II. <7:4> Selected Configuration Register 0 Filter section 0 configuration register 1 Filter section 1 configuration register 2 Filter section 2 configuration register 3 Filter section 3 configuration register 4 Filter section 4 configuration register 5 Filter section 5 configuration register 6 Filter section 6 configuration register 7 Filter section 7 configuration register 8 Filter section 8 configuration register 9 ---- miscellaneous ---- 10 ---- miscellaneous ---- 11 ---- miscellaneous ---- 12 ---- miscellaneous ---- 13 ---- miscellaneous ---- 14 Global configuration register 15 All (0 to 8) section configuration registers The global register 910 provides control words g and h . Control word g provides the control bits to configure the final adder 400. Control word h , comprising the "md" and "ld-coef" signals, is provided to each of the filter taps 810 (as described below with reference to Figure 10). Control words g and h control the filter circuit functions as described in Table III below. Bit Usage Control Word <2:0> FIR scale factor (1/1 to 1/16) fig. 5-g (FIR scale 407) <5:3> IIR scale factor (1/1 to 1/16) fig. 5- g (IIR scale 420) <6> Select bypassed output fig. 5- g (bypass) <7> 8-bit filter enable <8> signed samples <9> Load coefficient mode fig. 10-md} <10> Load coefficient strobe fig. 10-ld-coef} h <11> ---- miscellaneous---- Each of the configuration registers 600 provides a separate control word e to its respective filter section 800 thereby setting the mode of operation and value of parameters that are local to each of the filter sections as shown in Table IV. Bit Usage Control Word e <5.0> Input delay value (0-63 samples) fig. 8 (delay value 704) <6> FIR - select global delay source fig. 8 (fir inp sel.) <8:6> IIR-select global delay source fig. 8(iir inp sel.) <9> FIR Enable fig. 8 (fir/irr sel.) <10> Output Enable fig. 9 (enable 207 Σ FIR) fig. 9 (enable 205 Σ IIR) <11> Enable cascade Figure 9 (mux 805) The configuration mode of the filter circuit 200 is activated when a device comprising the circuit (for example a television receiver) is turned on. It also is activated each time the receiver is tuned to a different channel or when the periodic processing in processor 25 of the averaged GCR signal detects a change in the channel characteristics. How often the configuration mode is activated is directly related to the speed at which the processor can determine the channel characteristics and calculate the necessary configuration data and coefficients. One advantage of the invention as embodied in filter circuit 200 is that it can respond very quickly to changes in the channel characteristics determined by the processor 25. When the receiver is first turned on, the GCR signals carried on a number of fields of the received signal are averaged and compared to a stored version of the transmitted GCR, by processor 25. The processor 25, using techniques known to those skilled in the art, processes and conditions the averaged GCR signal as required by the type of GCR signal being used. The channel characteristics are then determined using time domain analysis algorithms such as those described in the references incorporated herein, or others known in the art, in order to determine the location in time of the pre-echo components and post-echo components present in the received signal. This information determines the allocation of the filter sections in filter circuit 200 to FIR and IIR functions. The processor 25 also calculates the coefficients needed to create an ideal inverse channel characteristic. Since the number of filter stages available in each filter section is limited, the processor must perform a clustering procedure which apportions the limited number of filter stages by effectively taking advantage of the tendency of the echo components to cluster in time. The procedure can use a preferred clustering algorithm such as the one described below. Other clustering algorithms which can also be used are known to those skilled in the art. The clustering algorithm creates a subset of the calculated coefficients and selects the necessary time delays, implemented in filter circuit 200, to select the filter stages 810 so as to coincide with the clustered echo components. After the clustering procedure, a sequence of configuration data words including the necessary control words needed to set the FIR/IIR boundary, the scaling parameters (if used by the processor 25 in calculating the coefficients) and the delay parameters, are loaded into filter circuit 200 in order to configure it as required using the information provided in the Tables in conjunction with the example described above. The coefficients are then loaded into filter circuit 200 as follows: 1. A configuration data word is written into each of the section configuration registers 600 setting its Enable Cascade bit (see Table IV). All of the section configuration registers 600 are addressed by providing an address of fifteen on bits <7:4> of register 906 (see Table II). The contents of each section configuration register 600 thereby provides the set bit, i.e. bit eleven of control word e (see Table IV), as a sum select signal to multiplexer 805 to each filter stage 800 thereby connecting the "cas in /coef in" input to the "Σ in/coef in" input of the first filter tap 810 of each filter stage 800 so as to form a pipeline of all of the filter taps (i.e. 180 taps). 2. A configuration data word is written into the global configuration register 910 setting its load Coefficient Mode bit (see Table III). The global configuration register is addressed by providing an address of fourteen on bits <7:4> of register 906 (see Table II). The contents of the global configuration register 910 thereby provides the md (coefficient mode) bit of control word h to each filter tap 810. As shown in Figure 10, when set, the md bit selects the input provided to each multiplier 819. This selection is made in multiplexer 816 which has as one input the video samples provided by d during the filter mode and as another input, a stored zero value which is the input selected by the md bit in the configuration mode. The md bit is also coupled to multiplexer 818 which selects as a clock input to sum register 820, the clock signal from 158 during the filter mode and a "coef clk" signal during the configuration mode. The coef clk signal is used to toggle the coefficients into the pipelined filter stages as described below, and is derived by "ANDing" the STROBE signal provided to interface circuit 900 and a write signal to register 902 (which provides the coefficient data). 3. The coefficients are then sequentially written to register 902 and sequentially fed to the 180 pipelined filter taps 810. For example, a new coefficient is shifted into the filter tal O (i.e. tap O in filter section O) when the coefficient register 902 is written to, and all other coefficients are shifted upward. The shifting of coefficients is accomplished by using register 820 in each filter tap which is clocked by the coef clk signal. After all of the coefficients are loaded, the holding register 815 of each filter tap 810 stores the coefficient to be loaded into the multiplier 819 of the respective filter stage. Note that the pipeline of 180 coefficient holding registers 815, needs no internal address select. Repeated writes to register 902 cause the data to move down the pipeline until all coefficients are initialized. 4. A configuration data word is written into the global configuration register 910 setting its Load Coefficient Strobe bit (see Table III). The global configuration register is addressed by providing an address of fourteen on bits <7:4> of register 906 (see Table II). The contents of the global configuration register 910 thereby provides the ld-coef (coefficient strobe) bit of control word h to each filter tap 810. As shown in Figure 10, the ld-coef bit when set, toggles register 815 and thereby provides the stored coefficient to the respective multiplier 819. Adder 817 adds the output of multiplier 819 to the Σ in/coef in signal and applies the sum to sum register 820. 5. A configuration data word is written into the global configuration register 910 resetting the Load Coefficient Strobe bit. 6. A configuration data word is written into the global configuration register 910 resetting the Load Coefficient Mode bit. 7. All of the filter section configuration registers are again loaded with the configuration data to set them to the desire configuration and parameters, as described in step 1. Figure 11 describes the use of two filter circuits 301 an 302 (which are the same as filter circuit 200) connected in series ("cascaded") in order to create a larger filter circuit 300 with the resulting ability to provide a greater number of filter taps, i.e. 360 instead of 180 and the resulting expanded ability for IIR/FIR allocation and improved echo cancellation. The main circuit 301 of this multi-circuit embodiment has as its X <8:0> input the output from the A/D converter 10. The second circuit 30 has as its X <8:0> input, eight bits (Y <8:1>) of the filter output Y <8:0> and the single bit CASCADE X <O> output of the main circuit 301. The CASCADE-X <O> output is used to convey rounding information to the cascade chips of multi-circuit implementations. The CASCADE X <O> output is provided by logic circuit 425 of final adder 400 (Figure 5) of the main circuit 301. Circuit 425 has as inputs, the outputs of rounding circuits 409 and 421. The function of the logic circuit is to determine whether it is necessary to round out the data being transferred to the second circuit 302. This is done according to the following truth table where a 1 indicates that rounding occurred in the respective rounding circuit and a 0 indicates that no rounding was necessary. Rounding Circuit X<O> 409 421 0 0 0 0 1 1 1 0 0 1 1 0 The CASCADE DATA <17:0> bidirectional port of second circuit 302 provides the feedback input to the CASCADE DATA <17:0> bidirectional port of main circuit 301 and the full nine bit Y <8:0> output of main circuit 301 provides the output of the multi-circuit filter circuit. Clustering Algorithm A N-taps full FIR filter has the following transfer function: As mentioned above, the circuit architecture of the invention can be more efficiently used by exploiting the fact that non-zero coefficients and thus multipliers are only required where there are echoes. This suggests a filter consisting of clusters of taps which can be randomly positioned relative to C f (0) ("tap zero"). That can be achieved by preceding each cluster of taps with a programmable delay line. The architecture of the invention described above provides the means for providing the necessary delay. Given C clusters of M taps each (C and M being integers), the transfer function of a clustered FIR filter becomes where Δp is the delay achieved by the p-th delay line and Cl c (p,q) is the q-th coefficient in the p-th cluster. Alternatively, (1) can be written as where From (3), it follows that when there are no overlapping clusters (i.e. |Δa - Δb| > = M, for each a,b), each coefficient C2 c (j) corresponds to a single coefficient Cl c (p,q). When there is overlap however, coefficient C2 c (j) may be the sum of several coefficients Cl c (p,q). Since the clustered filter will have fewer taps than the full filter (CM < N), it is an approximation of the latter. Finding the best approximation is an optimization problem which can be formalized as follows: Given: C f [O..N-1] = coefficients for the full filter. Wanted : Δ 1..c and Cl c (1..C,O..M-1) = delay values and coefficients for the clustered filter, such that is minimum. Here, e(a,b) is some error function of a and b. For example, when e = (a-b)², (3) gives the Mean Square Error between C f and C2 c . Solving (4) mathematically is rather difficult. It would require a substantial computation effort, which is not desired in a real time system. The invention provides a practical rather than a mathematical solution, which combines the benefits of simple computations and excellent performance. Solving (4) means finding the best location for each of the C available clusters. That translates into finding the best values of A 1...c . It can be shown that there are ways to position C clusters of M taps over a total of N taps (N > CM). Since the desired cancellation range for video requires N to be rather large, the number of possible solutions is enormous. When for instance N=512, C=15, M=8, substitution in (5) shows there are 8 * 10²⁶ different settings of Δ 1..15 . Below we describe a method for approximating the optimum delay settings which can be implemented in processor 25, for example. It has shown to be fast and give good results. The method is described in simplified form by means of pseudoprogramming language. It's basic operation is to locate the peaks in C f and then center the available clusters in Cl c around these peaks. The foregoing disclosure and description of the invention is illustrative and explanatory thereof and various changes in the design and configuration, and the algorithms therewith, may be made within the scope of the appended claims.

Claims: A television receiver for receiving a television signal comprising a plurality of frames each comprising a ghost cancellation reference signal, from a transmission path having a distortion characteristic which adds first and second types of echo components to said television signal, said receiver comprising: means (10) for receiving said television signal; means (25) for periodically analyzing said ghost cancellation reference signal, and for calculating a plurality of filter coefficients defining the inverse distortion characteristic of said transmission path and a plurality of control signals related to said first and second echo components; and a plurality of filter sections (Sect0 .. Sect8) which are configurable, in response to said control signals, into an FIR filter (15) and an IIR filter (20) for together substantially cancelling said first and second types of echo components. A digital signal processing apparatus for receiving a television signal comprising a ghost cancellation reference signal, from a transmission path having a distortion characteristic which adds at least one echo component to said television signal, said digital signal processing apparatus comprising: means (25) for periodically analyzing said ghost cancellation reference signal and for calculating a plurality of filter coefficients defining the inverse distortion characteristic of said transmission path and a plurality of control signals related to said at least one echo component; and a plurality of filter sections (Sect0 .. Sect8) coupled to said analyzing means (25) and configurable, in response to said control signals, into an FIR filter (15) and an IIR filter (20) for together substantially cancelling said at least one echo component. A digital signal processing apparatus as claimed in Claim 2, wherein said apparatus further comprises adding means (400) comprising an unprocessed sample input (209) coupled to receive a plurality of signal samples of said television signal, first (ΣIIR) and second (ΣFIR) processed sample inputs, and first (a) and second (b) sample outputs; and wherein said filter sections (Sect0 .. Sect8) comprise: means (707) controllably coupled (705, 717) to said first (a) and second (b) sample outputs, for selecting as filter section input samples (d), one of said first (a) and second (b) sample outputs under the control of a second control signal (e); delay means (704) coupled to said selecting means (707), for providing a delay to said filter section input samples (d); a filter stage (800) comprising a plurality of taps, a first filter input (d) coupled to said delay means (704) for receiving said delayed filter section input samples (d), a first stage output (807), a second stage output (205) controllably coupled (814) to said first processed sample input (ΣIIR) under the control of a first control signal (e), a third stage output (207) controllably coupled (813) to said second processed sample input (ΣFIR) under the control of a second control signal (e), and a second filter input (801) controllably coupled (805) to the first stage output (807) of an adjacent filter stage (800). A digital signal processing apparatus as claimed in claim 2, wherein said adding means (400) comprise means (425) for coupling said apparatus (301) to a second (302) said apparatus.

Inventors: GREENBERG CRAIG BRADLEY, GREENBERG, CRAIG BRADLEY
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H04N5
IPC codes: H04B3, H03H17, H04N5