Demodulator for digital modulation signals

Abstract: A phase demodulator is described, which employs a frequency detector (1) followed by an integrate and dump circuit (2), and a feedback device (4,5,6,7) for compensating for phase noise in the received signal. Means are also provided for using preceding and following data bits to derive the phase error signal.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a demodulator for digital modulation signals such as phase modulation and frequency modulation signals incorporated in a modem for digital data transmission through a cable or a radio system. (2) Description of the Related Art Demodulators for digital modulation signals such as phase modulation and frequency modulation signals including frequency detectors and integral discharge filters have the advantage over the demodulators including coherent detectors in reducing circuits. Fig. 1 is a block diagram of a conventional demodulator for the digital modulation signals through MSK (Minimum Shift Keying) and QPSK (Quadrature Phase Shift keying). The paper "Digital Cellular System with Linear Modulation" published in the Proceedings of the 39th IEEE Vehicular Technology Conference 1989 describes in detail such a demodulator. In general terms, the demodulator of Fig. 1 comprises a frequency detector 41, an integral discharge filter 42, and a decision device 43. The integral discharge filter 42 includes an integrator 44 and a discharge control circuit 45. The frequency detector 41 and integral discharge filter 42 constitute a phase detector which outputs phase deviation signals. The frequency detector 41 outputs frequency detection signals to the integral discharge filter 42 upon receiving the digital modulation signals, and in turn, the integral discharge filter 42 outputs phase deviation signals to the decision device 43 which outputs demodulation data. More precisely, having detected frequencies of the digital modulation signals, the frequency detector 41 outputs the frequency detection signals by means of the voltage depending on the deviation thereof to the integral discharge filter 42, which integrates the frequency detection signals for each time slot (transmission time per symbol), meaning that the integrator 44 discharges an electrical charge stored therein as a result of a preceding integration upon receiving a reset signal outputted every time slot from the discharge control circuit 45, and subsequently integrates the frequency detection signals for the following time slot. Thus, the integral discharge filter 42 serving as the phase detector with the frequency detector 41 outputs phase deviation signals to the decision device 43, which discriminates the polarity and/or magnitudes thereof using several thresholds in order to output demodulation data. The demodulator demodulates the frequency modulation signals by detecting the phase deviation based on the frequency modulation signals. For the digital modulation signals through MSK, the decision device 43 outputs binary demodulation data by means of a voltage corresponding to 0 deviation as a threshold, because their carrier phase deviation is either +π/2 or -π/2. For the digital modulation signals through π/4-shift-QPSK, the decision device 43 outputs quaternary demodulation data by means of voltages corresponding to +π/2, 0, and -π/2 deviation as thresholds, because their carrier phase deviation is one of +3π/4, +π/4, -π/4, and -3π/4. Fig. 2 shows a block diagram of a conceivable demodulator for digital modulation signals through GMSK (Gaussian Filtered Minimum Shift Keying) with large intersymbol interference due to Gaussian filters. The demodulator comprises a frequency detector 51, an integral discharge filter 52, a subtracting device 53, a decision device 54, a shift register 55, and a generator 56 for interference signals from preceding data(hereinafter, simply referred to as the interference signals generator 56). The integral discharge filter 52 includes integrators 57 and 58 for 2-bit transmission time(hereinafter, simply referred to as the integrators 57 and 58), an integrator control circuit 59, and a switch 60. The frequency detector 51 outputs frequency detection signals to the integral discharge filter 52 which outputs phase deviation signals to the subtracting device 53, and the subtracting device 53 subtracts therefrom interference signals from preceding data produced with the shift register 55 and interference signals generator 56, then outputs subtraction results to the decision device 54 which outputs demodulation data. More precisely, having detected frequencies of digital modulation signals, the frequency detector 51 outputs the frequency detection signals by means of the voltage depending on the deviation thereof to the integral discharge filter 52, which integrates the frequency detection signals for each 2-bit transmission time, meaning that the each integrator 57 and 58 integrates the frequency detection signals for 2-bit transmission time by turns upon alternately receiving a reset signal outputted every 1-bit transmission time from the discharge control circuit 59. The switch 60 controlled by the discharge control circuit 59 switches back and forth, whereby the integral discharge filter 52 outputs phase deviation signals, or the frequency detection signals integrated for 2-bit transmission time, to the subtracting device 53. Since the modulation signals through GMSK are affected by intersymbol interference caused by the filters of transmitters and receivers, the interference should be removed prior to the input into the decision device 54. For instance, phase deviation signals X n on the n'th transmission data S n can be expressed as follows: [Form 1] X n = A x S n-2 + B x S n-1 + B x S n + A x S n+1 Here, noise affection is not taken into consideration, and S n-2 and S n-1 , and S n+1 represent the data preceding and succeeding to S n , respectively, and each data becomes either +1 or -1. Capital letters A and B represent constant values, such as corresponding values to π/8 and 3π/8 deviation, respectively, which indicate affection on S n from the preceding and succeeding data and are determined by modulation methods or filter characteristics. The generator 56 outputs the interference signals from preceding data expressed as A x S n-2 + B x S n-1 by means of the voltage depending on the interference to the subtracting device 53, which subtracts the interference signals from preceding data from the phase deviation signals X n , thereby outputting substantially interference-free signals X n ' expressed as B x S n + A x S n+1 to the decision device 54. The interference signals from the succeeding data A x S n+1 can not be removed from the signals X n' because S n+1 are unknown. Subsequently, the decision device 54 discriminates the polarity and/or magnitudes thereof using a given threshold in order to output demodulation data to outer apparatuses as well as to the shift register 55, which shifts the demodulation data to a bit clock maintaining them for 2-bit transmission time, thereby outputting S n-2 and S n-1 to the interference signals generator 56, enabling it to produce the interference signals A x S n-2 + B x S n-1 . However, the demodulators described as above do not circumvent the problem of phase lags due to the noise in the digital modulation signals such as a heat noise and a cross talk, which affect the precise operation of decision device 43 and 54, therefore increasing BER (bit error rate) thereof. In those demodulators, the phase deviation signals X k of the k'th transmission data include a phase noise a k expressed as follows: [Form 2] a k = e k - e k-1 Here, e k refers to a phase noise element causing a phase lag between an ideal phase on the k'th transmission data and phase deviation signals X k , while e k-1 refers to a phase noise element by a phase lag between an ideal phase on the preceding transmission data, or the k-1'th transmission data, and preceding phase deviation signals X k-1 outputted either from the integral discharge filter 42, and in the integral discharge filter 52, e k-1 refers to a phase noise element by a phase lag between an ideal phase on the preceding transmission data, or the k-2'th transmission data, and preceding phase deviation signals X k-2 . Demodulators having coherent detectors have a phase noise consisting of e k only, while demodulators having the frequency detectors and integral discharge filters have a synthesized phase noise consisting of e k and e k-1 , therefore retaining higher BER. SUMMARY OF THE INVENTION The present invention has an object to provide a demodulator for digital modulation signals including a frequency detecting device and an integral discharge filter which is capable of minimizing BER. Accordingly, in one aspect the present invention provides a demodulator for digital modulation signals, including a frequency detector outputting frequency detection signals by detecting frequencies of the digital modulation signals, an integral discharge filter outputting phase deviation signals by integrating the frequency detection signals for a given interval, and discrimination means outputting demodulation data by discriminating the deviation of the digital modulation signals based on the phase deviation signals, characterised by feedback means for noise-compensating signals and generation means for noise-compensating signals, wherein the feedback means is set between the integral discharge filter and the discrimination means and generates compensated phase deviation signals to be inputted into the discrimination means by feeding back noise-compensating signals generated by the generation means to the phase deviation signals from the integral discharge filter and the generation means generates the noise-compensating signals based on the compensated phase deviation signals and the demodulation data. With the above construction, the noise-compensating signals based on the demodulation data are fed back to the phase deviation signals from the frequency detecting device and the integral discharge filter, thereby accumulating noise elements of the digital modulation signals. By such an accumulation, noise affection from the preceding data is reduced, improving precise operation of the discrimination device, and therefore minimising BER. In a further aspect, the present invention provides a demodulator for digital modulation signals, including a frequency detector outputting frequency detection signals by detecting frequencies of the digital modulation signals, an integral discharge filter outputting phase deviation signals by integrating the frequency detection signals for a given interval, and discrimination means outputting demodulation data by discriminating the deviation of the digital modulation signals based on the phase deviation signals, characterised by feedback means for noise-compensating signals and compensation means for interference from preceding data, both provided between the integral discharge filter and the discrimination means, and generation means for noise-compensating signals connected to the feedback means, wherein the feedback means outputs compensated phase deviation signals to the discrimination means by feeding back noise-compensating signals generated by the generation means to the phase deviation signals from the integral discharge filter, the compensation means outputs interference-compensated phase deviation signals to the discrimination means by removing the interference from the preceding demodulation data from the compensated phase deviation signals sent from the feedback means, and the generation means generates the noise-compensating signals based on the compensated phase deviation signals and the demodulation data. Constructed as above, outputting the noise-compensating signals based on the interference-compensated phase deviation signals, demodulation data, and succeeding demodulation data through the feedback makes it possible to remove intersymbol interference of the digital modulation signals, thereby enhancing precise operation of the discrimination device, and therefore minimizing BER. The invention extends to a demodulator for digital modulation signals, including a frequency detector outputting frequency detection signals by detecting frequencies of the digital modulation signals, an integral discharge filter outputting phase deviation signals by integrating the frequency detection signals for a given interval, and discrimination means outputting demodulation data by discriminating the deviation of the digital modulation signals based on the phase deviation signals, characterised by error accumulation means for accumulating errors included in the phase deviation detected by the integral discharge filter while multiplying the accumulated errors with a positive number less than 1 at each accumulation, wherein the accumulated errors accumulated by the error accumulation means and the phase deviation detected by the integral discharge filter are inputted into the discrimination means and the discrimination means outputs demodulation data by discriminating the phase deviation ofthe digital modulation signals based on the accumulated errors and the phase deviation. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate specific embodiments of the invention. In the drawings: - Fig. 1 is a block diagram of a conventional demodulator for digital modulation signals; Fig. 2 is a block diagram of a conventional demodulator for digital modulation signals with large intersymbol interference; Fig. 3 is a block diagram of a demodulator for digital modulation signals in Embodiment I; Fig. 4 shows phase and frequency characteristics of signals outputted in Embodiment I; Fig. 5 is a block diagram of a demodulator for digital modulation signals in Embodiment II; Fig. 6 is a block diagram of a demodulator for digital modulation signals in Embodiment III; Fig. 7 is a block diagram of a demodulator for digital modulation signals in Embodiment IV; and Fig. 8 shows BER characteristics to Eb/No (Bit energy to noise power spectral density). DESCRIPTION OF THE PREFERRED EMBODIMENTS (EMBODIMENT I) A demodulator for digital modulation signals through MSK or QPSK is described hereunder with referring to Fig. 3. The demodulator comprises a frequency detector 1 such as a ratio detector, an integral discharge filter 2, a decision device 3, a generator 4 for an ideal phase deviation signals(hereinafter, simply referred to as the generator 4, a subtracting device 5, a delaying circuit 6, a multiplying device 7 with a constant value (hereinafter, simply referred to as the multiplying device 7), and an adding device 8. The integral discharge filter 2 includes an integrator 9 and a discharge control circuit 10. The frequency detector 1 and integral discharge filter 2 constitute a phase detector which outputs phase deviation signals. The decision device 3 includes at least one comparator. The delaying circuit 6 includes a switched capacitor, delaying lines, and the like for delaying analogue signals and the multiplying device 7 includes an attenuator. Constructed as above, the demodulator outputs the demodulation data on the digital modulation signals as follows. Having detected frequencies of the digital modulation signals, the frequency detector 1 outputs frequency detection signals by means of the voltage depending on their deviation to the integral discharge filter 2, which integrates the frequency detection signals for each time slot, meaning that the integrator 9 discharges an electrical charge stored therein as a result of a preceding integration upon receiving a reset signal outputted every time slot from the discharge control circuit 10, and subsequently integrates the frequency detection signals for the following time slot. Thus the integral discharge filter 2 serving as the phase detector with the frequency detector 1 outputs phase deviation signals to the adding device 8. The demodulator demodulates the frequency modulation signals by detecting the phase deviation based on the frequency modulation signals. Then, in order to remove a noise causing a phase lag, the adding device 8 feeds back noise-compensating signals based on the demodulation data from the multiplying device 7 to the phase deviation signals, thereby outputting noise-compensated phase deviation signals to the decision device 3. The decision device 3 discriminates the polarity and/or magnitudes thereof using at least one threshold in order to output the demodulation data to outside apparatuses as well as to the generator 4, which outputs ideal phase deviation signals, or ideal voltages based on the demodulation data, to the subtracting device 5. For instance, the decision device 3 outputs the digital modulation signals through MSK in binary demodulation data by means of a voltage corresponding to 0 deviation as a threshold, because their carrier phase deviation is either +π/2 or -π/2. Subsequently, the generator 4 outputs an ideal deviation signals by means of a voltage corresponding to +π/2 or -π/2 deviation. Or the decision device 3 outputs the digital modulation signals through π/4-shift-QPSK in quaternary demodulation data by means of the voltages corresponding to +π/2, 0, and -π/2 deviation as thresholds, because their carrier phase deviation is one of +3π/4, +π/4, -π/4, and - 3π/4. Subsequently, the generator 4 outputs ideal deviation signals by means of a voltage corresponding to +3π/4, +π/4, -π/4, and -3π/4 deviation. Upon receiving the ideal phase deviation signals, the subtracting device 5 outputs error signals to the delaying circuit 6 by subtracting the ideal phase deviation signals from the noise-compensated phase deviation signals from the adding device 8. The delaying circuit 6 delays the error signals to the multiplying device 7 for 1 time slot, which outputs the noise-compensating signals to the adding device 8 by multiplying the delayed error signals with a given constant value α, thus, enabling the adding device 8 to output the noise-compensated phase deviation signals to the decision device 3. In Fig. 4, phase and frequency characteristics of aforementioned signals are shown, in which a dashed line refers to a signal without a noise. The inputted digital modulation signals (a) are outputted as frequency signals (b) and the integrated frequency detection signals are outputted as the phase deviation signals (c). Here, the phase deviation signals X k on the k'th transmission data include a phase noise a k expressed as follows: [Form 3] a k = e k - e k-1 In Form 3, e k refers to a phase noise element causing a phase lag between an ideal phase on the k'th transmission data and phase deviation signals X k , while e k-1 refers to a phase noise element caused by a phase lag between an ideal phase on the preceding transmission data, or the k-1'th transmission data, and preceding phase deviation signals X k-1 from the integral discharge filter 2. As previously mentioned, the adding device 8 outputs the noise-compensated phase deviation signals (d) by adding the phase deviation signals (c) and the delayed error signals for 1 time slot expressed as b k-1 (e) multiplied with the constant value α, therefore, the error signals b k in the noise-compensated phase deviation signals are expressed as: [Form 4] b k = a k + α x b k-1 With Forms 3 and 4, the error signals b k are further expressed as: It is apparent from Form 5 that when the absolute value of the constant value α is a number less than 1, the error signals b k converges, therefore, reducing affection of other phase noise elements such as e k-1 . Moreover, it is preferable to have a positive number as α. Generally all the phase noise elements are independent and random variables, therefore the average thereof is 0. Then when these elements have dispersion of σ 2 , the dispersion V b of the error signals b k are expressed as: When the noise-compensating signals expressed as α x b k-1 are not fed back to the phase deviation signals X k , the dispersion V b is 2σ 2 from Form 3, meaning that when the noise-compensated signals are fed back to the phase deviation signals X k , the dispersion V b becomes one (1 + α)th compared with the one without the feedback. From Forms 5 and 6, it can be said that it is most preferable to have a positive number less than 1 as α. It should be noted therefore that feeding back the noise-compensating signals to the phase deviation signals makes it possible to obtain smaller dispersion of the error signals, thereby improving the precise operation of the decision device 3, further resulting in minimizing BER. Although any positive number less than 1 can be α, it is preferable to have a smaller number when constant error signals of circuits incorporated in the demodulator are large for the prevention of the dispersion, while a large number, or substantially 1, is preferable when the constant error signals of circuits incorporated in the demodulator are small for the further prevention effect. In the embodiment, the generator 4 includes a multiplying device for multiplying the demodulation data by a given value in order to output the ideal phase deviation signals, or the ideal voltages, however, it may comprise a D/A convertor or a voltage generator and an analogue switch for controlling the outputs therefrom in accordance with the demodulation data. (EMBODIMENT II) A demodulator for digital modulation signals through GMSK with large intersymbol interference due to Gaussian filters or the like is described hereunder with referring to Fig. 5. The demodulator, as the one in Embodiment I, can minimize BER by feeding back the error signals to the phase deviation signals, in addition, it is constructed so that appropriate error signals can be fed back in order to remove the intersymbol interference in the modulation digital signals. The demodulator comprises a frequency detector 21, an integral discharge filter 22, a first subtracting device 23, a decision device 24, a shift register 25, a generator 26 for interference signals from preceding data (hereinafter, simply referred to as the generator 26), a generator 27 for ideal phase deviation signals (hereinafter, simply referred to as the generator 27), a second subtracting device 28, a delaying circuit 29, a generator 30 for interference signals from succeeding data(hereinafter, simply referred to as the generator 30), a third subtracting device 31, a multiplying device 32 with a constant value (hereinafter, referred to the multiplying device 32), and an adding device 33. The integral discharge filter 22 include integrators 34 and 35 for 2-bit transmission time (hereinafter, simply referred to as the integrators 34 and 35), an integrator control circuit 36, and a switch 37. Constructed as above, the demodulator outputs the demodulation data on the digital modulation signals as follows. Having detected frequencies of digital modulation signals, the frequency detector 21 outputs frequency detection signals with the voltage depending on the deviation thereof to the integral discharge filter 22, which integrates the frequency detection signals for each 2-bit transmission time, meaning that each integrator 34 and 35 integrates the frequency detection signals for 2-bit transmission time by turns upon alternately receiving a reset signal outputted every 1-bit transmission time from the discharge control circuit 36. The switch 37 controlled by the discharge control circuit 36 switches back and forth, whereby the integral discharge filter 22 outputs phase deviation signals, or the frequency detection signals integrated for 2-bit transmission time, to the adding device 33. The adding device 33 outputs noise-compensated phase deviation signals to the first subtracting device 23 by adding the phase deviation signals and noise-compensating signals from the multiplying device 32 based on the demodulation data. The first subtracting device 23 subtracts therefrom interference signals from the preceding data and outputs the subtraction results to the decision device 24. For instance, the n'th transmission data S n outputted as phase deviation signals X n can be expressed as Form 1 in the Description of the Related Art. The generator 26 outputs the interference signals from preceding data by means of the magnitudes depending on the interference expressed as A x S n-2 + B x S n-1 to the first subtracting device 23, which subtracts the interference signals from the preceding data from the phase deviation signals X n , thereby outputting signals X n' expressed as B x S n + A x S n+1 to the decision device 24. The interference signals from the succeeding data A x S n+1 can not be removed from the signals X n' because S n+1 are unknown. Subsequently, the decision device 24 discriminates the polarity and/or magnitudes thereof using a given threshold in order to output demodulation data to outer apparatuses such as receivers as well as to the shift register 25, and generator 27. The shift register 25 shifts the demodulation data to a bit clock maintaining them for 2-bit transmission time, thereby outputting S n-1 to the generator 30 as well as outputting S n-2 and S n-1 to the generator 26, enabling it to produce the interference signals A x S n-2 + B x S n-1 with two multiplying circuits and an adding circuit included therein. The generator 27 having the same construction as the generator 4 in Embodiment I outputs ideal phase deviation signals by means of an ideal voltage based on the demodulation data, or B x S n , to the second subtracting device 28. The second subtracting device 28 subtracts the ideal phase deviation signals from the signals X n' from the first subtracting device 23, thereby outputting the first error signals including A x S n+1 to the delaying circuit 29. The delaying circuit 29 delays the first error signals for 2-bit transmission time to the third subtracting device 31. In the mean time, the shift register 25 outputs signals based on S n-1 to the generator 30, whereby the generator 30 including an adding device outputs signals by means of a voltage depending on the interference signals A x S n-1 to the third subtracting device 31. Then, the third subtracting device 31 subtracts the interference signals A x S n-1 outputted from the generator 30 from the first error signals including A x S n+1 delayed for 2-bit transmission time from the delaying circuit 29, thereby outputting the subtraction results to the multiplying device 32 as second error signals, which are not affected by the interference from the preceding and succeeding data to S n . The multiplying device 32 outputs noise-compensating signals to the adding device 33 by multiplying the second error signals with a constant value α. Thus, forms 5 and 6 can be applied to Embodiment II, meaning that having a positive a less than 1 makes it possible to attenuate the phase noise element e k-1 as well as to obtain smaller dispersion of the error signals, further improving the precise operation of the decision device 24, and resulting in minimizing BER. (EMBODIMENT III) A demodulator for digital modulation signals including an frequency offset is shown in Fig. 6. The modulator has the same construction as the one of Embodiment I except that a high-pass filter 70 is installed between the multiplying device 7 and adding device 8 in order to attenuate direct-current elements to 1/β. In this modulator, the phase deviation signals have constant error signals expressed as T x f, provided that T refers to integral time in the integral discharge filter 2, and f refers to an offset of the frequency detection signals. For instance, the phase deviation signals of the k'th transmission data have error signals c k , which are produced by adding the constant error signals T x f to the multiple of the error signals on the preceding data c k-1 by α/β, thus, expressed as: [Form 7] c k = T x f + (α/β) x c k-1 Therefore, a constant value E of the error signals c k is expressed as: [Form 8] E = T x f / (1 - α/β) As previously mentioned, although α is a positive number less than 1, affection of frequency offset due to the feedback can be prevented by making β larger. In addition, it is particularly effective in reducing the phase noise affection to use a high-pass filter 70 having lower cut-off frequency compared with transmission bit rate. (EMBODIMENT IV) Another demodulator for digital modulation signals including an frequency offset is shown in Fig. 7. The demodulator has the same construction as the one of Embodiment II except that a high-pass filter 70 is installed between the multiplying device 32 and adding device 33 in order to attenuate direct-current elements to 1/β. Like the demodulator of Embodiment III, the demodulator is also able to decrease phase noise affection as well as restrain the frequency offset affection. Fig. 8 shows a correlation between BER characteristics and Eb/No (Bit energy to Noise power density). Here, α is 0.7, β is a value which is large enough to cut off direct-current elements. The digital data are modulated through GMSK with a low-pass filter having the product BT of 0.25 at the modulation speed with 32kbit/sec. In Fig. 8, a curve (a), a curve (b), and a curve (c) represent the demodulator of Embodiment IV, a demodulator without the error signals feedback, and a demodulator including an coherent detector, respectively. Data source for curve (c) is "Transmission Characteristics by GMSK" by Murata/Hirade, Denshi-Tsushin Gakkai Ronbunshyu (B), J64-B, Vol.10 and Vol. 11, pages 23 to 1130. October, 1981. It is apparent from Fig. 8 that BER characteristics of the demodulator of the present invention is superior to that of the one without the error signals feedback by approximately 2db, whereas it is similar to that of the one including the coherent detector while maintaining the construction compact. Although the digital modulation signals through MSK, QPSK, and GMSK are demodulated in the above embodiments, other modulation method which do not reduce amplitude such as 4-level FM is applicable to the present invention. The noise-compensating signals are not necessarily fed back to the phase deviation signals, and the delaying circuit can be connected to any place as long as the demodulator has construction to accumulate the noise-compensating signals. Also, current can be applied instead of voltage. Although the present invention has been fully described by way of example with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Therefore, unless otherwise such changes and modifications depart from the scope of the present invention, they should be construed as being included therein.

Claims: A demodulator for digital modulation signals, including a frequency detector (1) outputting frequency detection signals by detecting frequencies of the digital modulation signals, an integral discharge filter (2) outputting phase deviation signals by integrating the frequency detection signals for a given interval, and discrimination means (3) outputting demodulation data by discriminating the deviation of the digital modulation signals based on the phase deviation signals, characterised by feedback means (8) for noise-compensating signals and generation means (4-7) for noise-compensating signals, wherein the feedback means is set between the integral discharge filter (2) and the discrimination means (3) and generates compensated phase deviation signals to be inputted into the discrimination means (3) by feeding back noise-compensating signals generated by the generation means (4-7) to the phase deviation signals from the integral discharge filter (2) and the generation means (4-7) generates the noise-compensating signals based on the compensated phase deviation signals and the demodulation data. A demodulator for the digital modulation signals of claim 1, wherein the feedback means (8) for noise-compensating signals includes adding means for outputting the compensated phase deviation signals by adding the phase deviation signals and the noise-compensating signals. A demodulator for the digital modulation signals of claim 1, wherein the generation means (4-7) for noise-compensating signals includes: generation means for ideal phase deviation signals (4) for outputting ideal phase deviation signals depending on the phase deviation based on the demodulated data; phase error selection means (5) for outputting error signals by subtracting the ideal phase deviation signals from the compensated phase deviation signals; and multiplying means (7) for outputting the noise-compensating signals by multiplying the error signals with a positive number less than 1. A demodulator for the digital modulation signals of claim 3, wherein the generation means (4-7) for noise-compensating signals further includes delaying means (6) for outputting delayed error signals by delaying the error signals from the phase error selection means (5) for integral time necessary for the integral discharge filter (2) and subsequently for outputting the delayed error signals to the multiplying means (7). A demodulator for the digital modulation signals of claim 3, the demodulator further comprising a high-pass filter (70) installed between the phase error selection means (5) and the feedback means (8) for noise-compensating signals in order to cut off direct-current elements. A demodulator for digital modulation signals, including a frequency detector (21) outputting frequency detection signals by detecting frequencies of the digital modulation signals, an integral discharge filter (22) outputting phase deviation signals by integrating the frequency detection signals for a given interval, and discrimination means (24) outputting demodulation data by discriminating the deviation of the digital modulation signals based on the phase deviation signals, characterised by feedback means (33) for noise-compensating signals and compensation means (25, 26, 23) for interference from preceding data, both provided between the integral discharge filter (22) and the discrimination means (24), and generation means (27-32) for noise-compensating signals connected to the feedback means (33), wherein the feedback means (33) outputs compensated phase deviation signals to the discrimination means (24) by feeding back noise-compensating signals generated by the generation means (27-32) to the phase deviation signals from the integral discharge filter (22), the compensation means (25, 26, 23) outputs interference-compensated phase deviation signals to the discrimination means (24) by removing the interference from the preceding demodulation data from the compensated phase deviation signals sent from the feedback means (33), and the generation means (27-32) generates the noise-compensating signals based on the compensated phase deviation signals and the demodulation data. A demodulator for the digital modulation signals of claim 6, wherein the feedback means (33) for noise-compensation signals includes adding means for outputting the compensated phase deviation signals by adding the phase deviation signals and the noise-compensating signals. A demodulator for the digital modulation signals of claim 6, wherein the compensation means (25, 26, 23) for interference from preceding data comprises: a shift register (25) for shifting the demodulation data from the discrimination means (24) according to a given clock while withholding them for a given period as preceding data; and generation means (26) for interference signals from preceding data for outputting interference signals from preceding data depending on the interference withheld by the shift register (25), wherein the compensation means (25, 26, 23) for interference from preceding data outputs interference-compensated phase deviation signals by subtracting the interference signals from preceding data from the noise-compensated phase deviation signals. A demodulator for the digital modulation signals of claim 6, wherein the generation means (27-32) for noise-compensating signals comprises: generation means (27) for ideal phase deviation signals for outputting ideal phase deviation signals depending on the phase deviation based on the demodulation data; generation means (30) for interference signals from succeeding data for outputting interference signals from succeeding data depending on the interference based on the succeeding data; phase error selection means (29, 31) for outputting error signals by subtracting the ideal phase deviation signals and interference signals from succeeding data from the interference-compensated phase deviation signals, and multiplying means (32) for outputting noise-compensating signals by multiplying the error signals with a positive number less than 1. A demodulator for the digital modulation signals of claim 9, wherein the phase error selection means (29, 31) comprises delaying means (29) for delaying signals obtained by subtracting the ideal phase deviation signals based on demodulation data from the interference-compensated phase deviation signals for integral time necessary for the integral discharge filter (22), and wherein the phase error selection means (29, 31) outputs error signals by subtracting the interference signals from succeeding data from the delayed signals. A demodulator for the digital modulation signals of claim 9, the demodulator further comprising a high-pass filter (70) installed between the phase error selection means (29, 31) and the feedback means (33) for noise-compensation signals to cut off direct-current elements. A demodulator for digital modulation signals, including a frequency detector (21) outputting frequency detection signals by detecting frequencies of the digital modulation signals, an integral discharge filter (22) outputting phase deviation signals by integrating the frequency detection signals for a given interval, and discrimination means (24) outputting demodulation data by discriminating the deviation of the digital modulation signals based on the phase deviation signals, characterised by error accumulation means (28, 32, 33) for accumulating errors included in the phase deviation detected by the integral discharge filter (22) while multiplying the accumulated errors with a positive number less than 1 at each accumulation, wherein the accumulated errors accumulated by the error accumulation means (28, 32, 33) and the phase deviation detected by the integral discharge filter (22) are inputted into the discrimination means (24) and the discrimination means outputs demodulation data by discriminating the phase deviation of the digital modulation signals based on the accumulated errors and the phase deviation. A demodulator for digital modulation signals of claim 12, wherein the discrimination means (24) outputs the demodulation data actually by comparing the size of a sum of the phase deviation detected by the integral discharge filter (22) and the accumulated errors by the error accumulation means with a given threshold. A demodulator for digital modulation signals of claim 12, wherein the error accumulation means (28, 32, 33) adds the differences between the phase deviation detected by the integral discharge filter (22) and the ideal phase deviation depending on the phase deviation based on the demodulation data and the accumulated errors, while multiplying the accumulated errors with a positive number less than 1. A demodulator for digital modulation signals of claim 12, the demodulator further comprises delaying means (29) for delaying the accumulated errors accumulated by the accumulation means (28, 32, 33) for an integral time necessary for the integral discharge filter (22), wherein the discrimination means (24) outputs the demodulation data by discriminating the phase deviation of the digital modulation signals based on the phase deviation detected by the integral discharge filter (22) and the delayed accumulated errors by the error accumulation means (28, 32, 33) and delaying means (29). A demodulator for digital modulation signals of claim 12, the demodulator further comprising: a high-pass filter (70) for cutting direct-current elements of the accumulated errors accumulated by the error accumulation means (28, 32, 33), wherein the discrimination means outputs the demodulation data by discriminating the phase deviation of the digital modulation signals based on the phase deviation detected by the integral discharge filter, and the errors accumulated by the error accumulation means (28, 32, 33) and cut off the direct-current elements by the high-pass filter (70).

Inventors: NEZU TOSHIKAZU, TANAKA KOICHIRO, NEZU, TOSHIKAZU, TANAKA, KOICHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: H04L27
IPC codes: H04L27