Miniature electronic device aligner using capacitance techniques

Abstract: A method and structure permit the precision alignment in the packaging of optical components (10), such as lasers, detectors, lenses and waveguides. The technique involves capacitance measurements of an array of plates placed on the optoelectronic device chip and its package substrate (12). The technique uses phase sensitive detection to sense the total current capacitively coupled into a passive plate (14) on the device chip (10) from two overlapping plates (16, 18) located on the package substrate. When the device chip (10) is properly aligned with respect to the package substrate (12), the summed current sensed with a third overlapping plate (22) on the package substrate is a null.

Description: The present invention generally relates to the manufacture of miniature electronic devices and, more particularly, to a method and structure for the precision alignment of an integrated circuit (IC) chip on a package substrate. Such devices are typically a few microns to a tenth of micron in size and pose a critical problem in precise alignment during manufacture. The invention has particular application to the manufacture of optoelectronic (OE) devices. The technique permits, for example, precision laser-to-fiber or waveguide alignment in miniature OE devices. The manufacture of miniature optoelectronic (OE) devices requires the precision alignment of optical devices such as lasers, detectors and lenses to optical fibers or waveguides. Such devices are in increasing demand in a variety of applications including communications and instrumentation. However, as optical devices are made increasingly smaller, the ability to quickly and easily align the optical components with precision has become increasingly difficult. Generally, the prior art involves active or optical alignment steps in the assembly of an optoelectronic module. This type of operation requires that the device chip be electrically contacted and powered which is not possible in certain packaging configurations. Examples of the prior art techniques are disclosed in US-A-4 807 956 to Tournereau et al., US-A-4 764 983 to Walter, US-A-4 756 590 to Forrest et al., and US-A- 4 755 017 to Kapany and in Japanese Patent No. 1-88404 to Hiroshiwada issued April 3, 1989. Other approaches have been taken in the prior art that do not require electrical connection to the device chip. One such approach is illustrated by US- 4 650 276 to Lanzisera et al. which describes a package that employs a cylindrical geometry to assist with alignment. Another approach is described in US-A- 4 841 225 to Meyer. Meyer uses a digital capacitance system involving many electrodes resulting in a relatively complex structure which requires contact to both parts. Another approach is described in EP 0 304 118 . There one uses the electrical contact of solder blocks on a device with solder pads on a substrate for alignment of the device relative to the substrate. The method requires a controlled amount of solder for accurate alignment. It is therefore an object of the present invention to provide a technique for the precision alignment of miniature electronic components during their manufacture. In particular the invention is aimed to provide a technique for the precision alignment of optoelectronic components, such as lasers, detectors, lenses and waveguides, on a package substrate and especially to provide a structure which permits the precision alignment of optical components in the manufacturing and packaging of optoelectronic devices. Further the invention is particularly aimed to provide a method of precision alignment of optical components that does not require a device chip to be electrically contacted and powered. This and other objects are advantageously solved basically by applying the features laid down in the independent claim. The invention provides a method and structure for the precision alignment in the packaging of miniature electronic components and, in particular, optoelectronic components, such as lasers, detectors, lenses and waveguides, and greatly enhances the precision of the manufacture of optoelectronic (OE) devices. Capacitance measurements of an array of plates placed on the optoelectronic device chip and its package are used to position the parts. The technique uses phase sensitive detection to sense the total current capacitively coupled into a plate located on the device chip from two overlapping plates located on the package which are driven at 180° relative phase. When the parts are properly aligned, the summed current sensed with a third overlapping plate on the package is zero. By locating the plates precisely with respect to the optical structures using lithographic techniques, precision optical alignment of device structures to light guides is possible. The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawing in which: Figure 1 is an exploded isometric view showing a laser chip and its package illustrating the basic principles of the capacitance alignment technique according to the invention; Figure 2 is an electrical schematic diagram of the circuit model of the capacitance alignment structure shown in Figure 1; Figure 3 is a plan view of a specific embodiment of a device chip and package substrate showing the pattern of capacitive plates; Figure 4 is a graph showing a plot of the measured values using the experimental device chip and package substrate showing data as displacement as a function of signal; and Figure 5 is a plan view showing the application of the alignment technique according to the invention to positioning in two dimensions. Referring now to the drawing, and more particularly to Figure 1, there is shown a flipped device chip 10, such as a laser chip or a detector chip, for mounting face down on a package substrate 12. A single capacitor plate 14 on the device chip is located precisely with respect to the device. The package substrate 12 has two differentially driven(±V₀sinωt) capacitor plates 16 and 18 aligned to a fiber groove 20. The capacitor plates 16 and 18 partially overlap the device capacitor plate 14 when the device chip 10 and the package substrate 12 are brought together forming two capacitors C⁺ and C⁻: C ± = ε i ε 0 ℓ x 0 ± x d , where ℓ is the overlap of the plates in the z direction, x₀ ± x are the overlaps in the x direction, and ε i is the relative dielectric constant of the insulator and ε₀ is the permitivity of free space. The third plate 22 on the substrate package completely overlaps the chip device plate 14 forming capacitor C c , which couples the summed current to a detector. When x = 0, C⁺ = C⁻ and the summed current or detected signal is zero. The sensitivity of the technique can be modeled using the circuit shown in Figure 2. The drive plates are assumed to be sinusoidally driven: V ± = ± V 0 sinω t . The imbalance in the current coupled to the device plate 14 is partially coupled through C c and is detected as a voltage drop across the 50 Ω input impedance, R, of the lock-in detector. The remainder of the current is capacitively coupled to ground through the parasitic capacitance, C p , formed by the device plate 14, an insulating layer and the grounded package substrate 12. While the parasitic capacitance, C p , reduces the sensitivity, it does not shift the nulled position. In practice, an air gap is maintained with stand-offs between the parts so that the effective gap, d eff , of the capacitors formed when the parts are put together is: d eff = d i +ε i d air . With the air gap between the parts, the voltage, V d , at the detector is: Here, A c and A p are the areas of the capacitors C c and C p , respectively, and d i is the thickness of the device substrate insulator. The sensitivity of the technique scales linearly with drive voltage and frequency. Experimental data has been developed to demonstrate the operation of the invention. Test parts were fabricated on silicon substrates using silicon dioxide and epoxy as the insulating layers. The actual plate pattern is shown in Figure 3 and was designed to reduce the sensitivity to tilt of the device with respect to the substrate package. More specifically, the two drive plates 16 and 18 are placed close together in order to minimize the space between these plates. This geometry minimizes the sensitivity of the measurement to tilt. The detector coupling plate 22 can be placed at any convenient location on the device. It is only necessary that the device coupling plate 14 be overlapped by the drive plates 16 and 18 and the detector coupling plate 22. In the example shown, this is accomplished by the "U" shaped geometry of the device coupling plate 14 wherein one leg of the "U" is overlapped by the drive plates 16 and 18 and the other leg overlies the detector coupling plate 14. Although the sensitivity to tilt is greatly reduced with this geometry, there is no trade-off in sensitivity, only initial placement accuracy. In the implemented example illustrated in Figure 3, the device coupling plate 14 occupied an area of 460 µm x 480 µm on the device 10. Stand-off rails were patterned in epoxy and measured with a Dektak profiler. The resulting air gap should have been between 0.8 µm and 1.0 µm, but could have been greater due to imperfections in the spun-on epoxy films. The parts were brought into alignment with micro-positioners and displaced along the x axis to measure the sensitivity of the system. The drive plates 16 and 18 were driven with 0.35 V rms signals at 1 MHz. The detected signal was amplified with a PARC 5202 lock-in amplifier. Measurements of displacement as a function of the detected voltage are shown in Figure 4. A straight line fit to the data yields a sensitivity of 66 µ m µ V which, according to the sensitivity model, corresponds to an air gap of 1.4 µm. The noise level of the instrumentation is 0.01 µV, so it is possible to resolve displacements of less than 1 µm under these conditions. The capacitances C⁺ and C⁻ depend strongly on any air gap between the parts. Differences in their gaps will result in a misalignment which is proportional to the amount of tilt. For example, a tilt (rotation about the z axis) of 0.5 µm across the 500 µm part produces a gap difference of 0.07 µm between C⁺ and C⁻. This could produce a misalignment of 1 µm for the experimental geometry. For a given tilt angle, the amount of error can be reduced by increasing the air gap (at the expense of sensitivity) or by reducing the distance between the drive plates. The ultimate constraint on the latter is the initial accuracy to which the parts are placed. For the experimental geometry, a ±50 µm initial placement is required. Optimizing the design and reducing the placement to ±25 µm reduces the misalignment to 0.25 µm without a loss of sensitivity. The invention is capable of permitting precise alignments in two dimensions as well as one. An embodiment which allows this is shown in Figure 5. A first pair of drive plates 32, 34 perpendicular to the x-axis are used to position the device in that axis, while second pair of drive plates 36, 38 perpendicular to the z-axis are used to position the device in that axis. The drive plates 32, 34 are driven by signals ±Vsinω₂t (i.e., 180° out of phase with one another), and the drive plates 36, 38 are driven by signals ±Vsinω₁t (i.e., 180° out of phase with one another). The frequencies f₁ and f₂ (where ω=2π f ) are chosen so that detectors, tuned to the two different frequencies, each sense the off-null current arising from displacement in one direction only. In the embodiment shown in Figure 5, only a single detector coupling plate 40 is required. This minimizes the area on the package substrate dedicated to the capacitive plate patterns. This same economy of area is also realized on the device, as indicated by the outline of the device coupling plate 42. It will, of course, be understood that this geometry may be modified without losing the benefit of the overall design. Further, it will be observed that this particular geometry, like that of Figure 3, has reduced sensitivity to tilt, but now in two dimensions rather than just one as before. The capacitance technique according to the invention has been demonstrated to be capable of resolving one micron displacements. Since the sensitivity of the technique scales linearly with drive voltage and frequency, improvement factors of twenty or more in sensitivity should be achievable. Insulators used in these devices should withstand 5 V and the frequency of the lock-in used extends to 50 MHz. The measurements reported represent a design point with displacement resolution of better than 1 µm and with systematic errors of about 1 µm, assuming a gap variation of 0.5 µm in 500 µm. By increasing the air gap, the drive voltage and the frequency, it should be possible to achieve sub-micron alignments. A combination of features provides a practical solution to the problem of optoelectronic device alignment. The use of a passive coupling plate on the device chip allows the chip to be mounted face down. This confers a significant advantage over the obvious capacitive coupling schemes which require direct electrical contact to both the device chip and the package substrate. The addition of the detector coupling plate to capacitively couple to the device chip is the feature that allows this to be done. The use of two differentially driven drive plates eliminates most of the sources of systematic error that plague typical capacitance measurement methods, such as parasitic capacitance and dependance on gap. The last remaining systematic error of any practical significance is a higher order effect from the tilt of the device with respect to the package substrate. The novel features of this invention that greatly reduce this are best illustrated by the preferred embodiments shown in Figures 3 and 5. The layout of the plates is chosen to minimize the spatial separation of the drive plates of the capacitors C⁺ and C⁻ . A given amount of tilt will produce an alignment error that is proportional to this separation, so smaller separations are better. Two key concepts that allow for very small separations are the close proximity of the drive plates on the package (by moving the detector plate from between them) and minimizing the amount of overlap of the device coupling plate to the drive plates. The overlap dictates the size of the effective capacitor plates which, in turn, affects the center-to-center separation of the pair. The amount of overlap determines the dynamic range of motion that can be accommodated and is constrained by the initial device placement tolerance. Reduction of the overlap is counter intuitive in a capacitance transducer because it reduces signal. However, in this invention, the relevant signal is actually proportional to the derivative of the capacitance with respect to position and not the capacitance itself. Another important design principle of this invention is the addition of an air gap to reduce tilt sensitivity even further. A given amount of tilt will produce an alignment error proportional to the gap difference of C⁺ and C⁻ divided by the nominal gap. Thus, large gaps reduce tilt sensitivity. This is not an obvious addition to a capacitive transducer design because increasing the gap reduces signal. The extra air gap is one of the novel features that allows the achievement of lower systematic errors by trading off absolute sensitivity, which is higher than required. While the invention has been described in terms of preferred embodiments which allow the precise alignment of miniature parts in one and two dimensions, it is possible to extend the teaching of the invention to three dimensions.

Claims: A structure for miniature electronic device alignment comprising a package substrate (12) and a device chip (10) which is adapted for mounting face down on the package substrate (12), in particular for alignment of a laser chip being the device chip (10) in correspondence to a fiber groove (20) provided in the package substrate (12). wherein on the device chip (10) and the package substrate (12) electrodes are provided to electrically sense the alignment of the device chip (10) relative to the substrate (12), characterized in that an electrode on the device chip (10) is a passive capacitive device coupling plate (14; 42) located precisely on the face of the device chip (10) provided to be directed towards the package substrate (12), in that two electrodes on the package substrate (12) are first and second capacitor drive plates (16, 18; 32, 34) , arranged to overlap the device coupling plate (14; 42) , when the device chip (10) is positioned for mounting on the package substrate (12), in that another electrode on the package substrate (10) is a detector coupling plate (22, 40), which at least partially overlaps the device coupling plate (14; 42) , when the device chip (10) is positioned for mounting on the package substrate (12), in that means are provided to drive the first and second capacitive drive plates (16, 18; 32, 34) with alternating voltages of opposite phase, wherein the voltages are coupled via capacitances (C+, C-) of the first and second capacitor drive plates (16, 18; 32, 34) to the device coupling plate (14; 42) and generate a current in the detector coupling plate (22; 40) via a capacitance (Cc) between the device coupling plate (14; 42) and detector coupling plate (22; 40) , when the device chip (10) at least partially overlaps the package substrate (12), and in that first and second drive plates (16, 18, 32, 34) , device coupling plate (14; 42) and detector coupling plate (22; 40) are arranged such that the current in the detector coupling plate (22; 40) is zero when the device chip (10) is properly aligned with the package substrate (12) . Structure according to claim 1, characterized by third and fourth drive plates (36, 38) on the package substrate (12) which are oriented perpendicular to the first and second drive plates (32, 34) and arranged to generate a current in the detector coupling plate (40) by capacitive coupling via the device coupling plate (42) when alternating voltages of opposite phase are supplied to the third and fourth drive plates (32, 34), the device coupling plate ( 42) at least partially overlapping the third and fourth drive plates (36, 38) , and further being arranged such that this current is zero when the device chip (10) is properly aligned with the package substrate (12), means for supplying the first and second drive plates (32, 34) with alternating voltages of a first frequency (w1) and means for supplying the third and fourth drive plate (36, 38) with alternating voltages of a second frequency (w2) different to the first frequency (w1), and sensing means sensitive to the both frequencies (w1, w2)for sensing currents. Structure according to claim 1 or 2, wherein the detector coupling plate (22) is located intermediate the first and second drive plates (16, 18; 32, 36) and, if provided intermediate the third and fourth drive plates (36, 38) . Structure according to claim 1 or 2, characterized in that the first and second drive plates (32, 34) are positioned immediately adjacent to each other and if provided, the third and fourth drive plates (36, 38) are positioned immediately adjacent to each other, each with minimum spacing to minimize sensitivity to tilt, in that the detector coupling plate (40) is located apart from the driving plates (32, 34; 36, 38) , and in that the device coupling plate (42) on the device chip (12) has a geometry conforming to the placement of the drive plates (32, 34; 36, 38) and the detector coupling plate (40) . Structure according to anyone of claims 1 to 4, characterized by means to establish an air gap between the drive plates (16, 18; 32, 34, 36, 38) and the device coupling plate (14; 42) to further minimize sensitivity to tilt. Method for alignment of a device chip (10) face down with respect to a package substrate (12), wherein device chip (10) and package substrate (12) exhibit a structure according to any one of claims 1 to 5, characterized by positioning the device chip for mounting on the package substrate so that the device coupling plate is overlapped by the first and second drive plates, applying alternating voltages of opposite phase to the first and second drive plates (16, 18; 32, 34), and displacing the device chip (10) until the current on the detector coupling plate (22) is zero. Method according to claim 6 using a structure according to claim 2, characterized by applying alternating voltages of opposite phase to the third and fourth drive plates (36, 38) and of a frequency (w1) different from the frequency (w2) of the alternating voltages applied to the first and second drive plates (32, 34) sensing currents in the detector coupling plate (40) at the two frequencies (w1, w2), and displacing the device chip (12) in corresponding directions of current components of the two frequencies (w1, w2) until the current on the detector coupling plate (40) is zero. Method according to claim 6 or 7, characterized by the step of establishing an air gap between the first and second drive plates (16, 18; 32, 34) and the device capacitive coupling plate (14; 42) and, if provided, between third and fourth drive plates and the passive capacitive coupling plate (22; 42) to minimize sensitivity to tilt.

Inventors: FLINT EPHRAIM BEMIS, YARMCHUK EDWARD JOHN, FLINT, EPHRAIM BEMIS, YARMCHUK, EDWARD JOHN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1992
Main classification: G02B6
IPC codes: H01L33, G01B7, G02B6, G02B7