Monolithic integrated bridge transistor circuit and corresponding manufacturing process

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type. The invention also relates to an associated process for manufacturing said bridge circuit.

Description: This invention relates to a monolithically integrated, transistor bridge circuit and a method for the manufacture thereof. More particularly, the invention relates to a bridge circuit made up of power transistors operated at a high voltage which may exceed 250 volts, although the description which follows will make reference to an application of this kind merely for convenience of illustration. As it is known, bridge circuits are widely used for a large number of applications on account of their ability to equalize currents being supplied to an electric load. For such specific applications, integrated circuits, both incorporating bipolar transistors and field-effect transistors in a half-bridge configuration have been provided in the past. A circuit of that type is described, for example, in Italian Patent No. IT 1204522 by this Applicant. Another known technical solution is described in European Patent Application No. 91830513.7 (EP-A-0 544 048) which relates to a bridge circuit of the integrated type designed to optimize power losses. The last-mentioned approach has proved advantageous by virtue of its high conversion efficiency and its ability to operate on high currents, but does not provide for integration of all the power components on a single chip. To avoid this disadvantages it has been provided a prior art solution disclosed in the article of Miyazaki et al. entitled 'A Novel High Voltage Three-Phase Monolithic Inverter IC with Two Current Levels Sensing', 3 RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, published on April 22, 1991. The Miyazaki article relates to a monolithically integrated transistor bridge circuit, being of a suitable type for power application comprising six lateral IGBTs, having common emitters and collectors which are located at the surface. Another prior art solution is disclosed in the Japanese Patent Application No. 30 70 477 which relates to a drive power supply circuit for insulated-gate semiconductor device (IGBT). The underlying technical problem of this invention is to provide a transistor bridge circuit which has such structural and functional features as to enable monolithic integration of high-voltage elements, while overcoming the current limitations of prior art embodiments. The technical problem is also concerned with the manufacturing process of said bridge circuit. The solutive idea on which this invention stands is one of incorporating high current-carrying IGBT devices to the integrated circuit. Based on this solutive idea, the technical problem is solved by a bridge circuit as previously indicated and defined in Claim 1. The technical problem is also solved by a manufacturing process of this bridge circuit, as defined in Claim 8. The features and advantages of a bridge circuit according to the invention will become apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a diagramatic representation of a bridge circuit according to the invention; Figure 2 shows, schematically and drawn to an enlarged scale, a vertical section through the structure of a monolithic semiconductor device incorporating the bridge circuit of this invention; Figure 3 is a diagramatic detail view of a modified embodiment of the device shown in Figure 2; and Figure 4 illustrates schematically an exemplary application of the variation shown in Figure 3. With reference to the drawing figures, generally and schematically shown at 1 is a bridge circuit embodying this invention in the mixed bipolar/MOS technology and being integrated monolithically on a wafer of semiconductor silicon. The circuit 1 comprises two opposing input nodes A, B and two opposing output nodes C, S. Connected between the first output node C and each of the input nodes A and B, is a corresponding bipolar transistor T1, T2. In a similar manner, between the second output node S and each of the input nodes A, B is a corresponding power electronic device M1, M2. More particularly, each device M1, M2 is an insulated-gate bipolar transistor, commonly known by the acronym IGBT (Insulated-Gate Bipolar Transistor), which is constructed in the MOS technology. The respective gate terminals of such IGBT transistors M1, M2 are denoted by the references G1 and G2, while the respective base terminals of the bipolar transistors T1, T2 are denoted by the references B1, B2. The upper portion of the bridge 1, comprising the bipolar transistors T1 and T2, is connected to the lower portion, comprising the IGBT devices M1, M2, through respective connections of the emitters E1, E2 of the first transistor pair to the drain terminals D1, D2 of the second pair. The collectors C1, C2 of the first transistor pair T1, T2 are connected together into the first output node C. The source terminals S1, S2 of the second transistor pair M1, M2 are connected together into the second output node S. With specific reference to the example shown in Figure 2, shown therein are the details of the monolithic structure of this circuit 1 as yielded by the manufacturing process of this invention. Provided over the semiconductor wafer is a monocrystalline silicon substrate 3, being doped N+ and having an epitaxial layer 4 with conductivity N- formed thereon. Formed within this epitaxial layer 4 is a P-doped isolation well 5 adapted to receive and hold the IGBT transistors M1 and M2. To create such transistors M1, M2, the well 5 is provided with two discrete epitaxial regions 6 and 7, doped N-. In each of said regions 6 and 7, two discrete areas, doped P+, are diffused. These areas have been referenced 8 and 9 for transistor M1 and 18 and 19 for transistor M2. The areas 8 and 18 constitute the so-called deep bodies of the two transistors, M1 and M2, while the areas 9 and 19 are the respective drain active areas of each transistor M1, M2. Associated with the areas 8 and 18 are also the related bodies doped P-. Two additional discrete regions, doped N, are formed, as by diffusion, within each of the two bodies 8 and 18. These regions represent source active areas of the IGBT devices. Indicated at 10 are two sources of transistor M1, and at 20 two sources of transistor M2. Between each respective source area 10, 20 and drain area 9, 19, the gate terminal G1, G2 of the associated transistor is formed in a manner known per se. By providing two source active areas in each body 8, 18, the perimeter of the channel region can be doubled. In fact, terminals G1a and G2a are provided which are connected in parallel with each gate G1, G2. Each of the gate terminals G1, G1a, G2, G2a is formed by a layer 13 of polycrystalline silicon deposited over an insulating oxide layer 12. Also provided is a shorting link between the source regions 10 and 20 and the corresponding body 8, 18 of the associated transistor. As shown in Figure 2, a metallization layer 27 interconnects the body/source shorts and the well 5, to be then run to the output node 8. It matters to observe that, with the structure just described and illustrated, two lateral conduction IGBT devices M1, M2 are provided which are characterized by having their drain terminals 9, 19 at the semiconductor surface. The circuit 1 structure is completed by the provision of the bipolar transistors T1, T2 located at the sides of the well 5 which encloses and isolates the IGBT devices. The transistors, T1 and T2, are formed in a manner known per se using a conventional process. The transistors T1 and T2 are each formed of a base region 25, doped P, wherein a corresponding emitter region E1 or E2, doped N+, is diffused. Advantageously, each emitter E1, E2 is connected, through a metallization 26, to the corresponding drain terminal 9, 19 of the IGBT transistor, as also illustrated by the diagram in Figure 1. In the interest of a simplification of the structure herein, a modified embodiment of the inventive circuit is depicted, to a slightly enlarged scale, in Figure 3 which has a single body region 16 in common with an isolation well 15. It should be noted that in the embodiment of Figure 3, elements with the same construction and operation as in the previously described embodiment are denoted by the same references. A single isolation well 15 accommodates both the first IGBT transistor and the second. Formed within the well 15 are the two epitaxial regions 6 and 7. The drain 9 of the first transistor M1 is diffused through the first region 6, whilst the second region 7 accommodates the drain 19 of the second transistor M2. A single diffused body region 16 is, on the other hand, shared by the two transistors and connected to the well 15 through a region 30 (Figure 3) bounded by the epitaxial regions 6 and 7. Formed within the last-mentioned body region 16 are the sources 10 and 20, each on the side of the corresponding transistor M1 or M2. The gate terminals G1 and G2 are formed conventionally between the respective drain and source terminals, 9-10 and 19-20, of each transistor M1, M2. This, the second, embodiment affords IGBT integrated transistors of a specially compact design, thereby minimizing the silicon area occupied by the integrated circuit. Advantageously, since the IGBT transistors are to pass high currents, the structure described with reference to Figure 3 may be duplicated to connect in parallel several transistors of one type. Shown in Figure 4 is an embodiment wherein each transistor, M1 or M2, is constructed by associating two of the semiconductor devices shown in Figure 3, in parallel together. To summarize, the drain regions 9 and 19, doped P+, and the source regions 10 and 20, have been adequately connected together. This basic structure is, moreover, duplicated such that each of the transistors M1 and M2 is composed of another two IGBT transistors parallel connected together. To this aim, a double metallization level can be employed as shown in Figure 4. To summarize the process steps which are implemented by the bridge circuit of this invention, the essential steps involved in the manufacturing process will be suitably listed sequentially herein below. Subsequently to growing the epitaxial layer 4 over the substrate 3, the process sequence includes the formation of the buried layer, doped P, which is to provide the well 5 and base regions 25 for the bipolar transistors T1, T2. Thereafter, the buried layers, doped N+, for the emitters E1, E2 are formed, followed by the growth of a second epitaxial layer 31 and the definition, within this epitaxial layer 31, of isolation regions 32 which bound the portions 6 and 7 of said epitaxial layer 31. At this stage, a series of oxide deposition, phototechnique and chemical etching operations are performed to define the deep body areas 8 and 18, and the drain active areas 9, 19 bounded by field oxide. The semiconductor is then covered with a layer 12 of polycrystalline silicon wherein pits are defined to provide the source active areas 10 and 20, doped N+. Subsequently, the body regions doped P- are defined. Conventional final steps of contact opening, metallization and passivation complete the manufacturing sequence. The bridge circuit of this invention does solve, in all of its embodiments, the technical problem, and achieves a number of advantages, foremost of which is that it can ensure a high current flow to the load. Another advantage resides in the smaller integrated circuit area occupied and consequent savings in layout. It should be additionally noted that the solution provided by this invention can operate effectively at high voltages, even in excess of 250 volts, and still be highly stable in operation.

Claims: A monolithically integrated, transistor bridge circuit, being of a suitable type for power applications and comprising a first bipolar transistor pair (T1, T2) having collectors (C1, C2) in common in an epitaxial semiconductor layer (4) and an underlying semiconductor substrate (3) and a second transistor pair (M1,M2) of the IGBT type being laterally conducting, said IGBT second transistor pair (M1, M2) having the respective source terminals (S1,S2) connected together and respective drain terminals (D1, D2) connected to corresponding emitters (E1, E2) of the first bipolar transistor pair (T1, T2), wherein said IGBT second transistor pair( M1, M2) is formed within a single isolation well (5) in said epitaxial layer (4), said well including epitaxial regions (6,7) in which said drain (9,19) and source (10,20) active regions of each transistor (M1,M2) are formed, with the drain regions of the second transistor pair being (9,19) formed on the semiconductor surface of said epitaxial regions. A bridge circuit according to Claim 1, characterized in that the source regions (10,20) of each transistor (M1,M2) are contained in a corresponding single body region (8, 18). A bridge circuit according to Claim 2, characterized in that the source regions (10,20) and corresponding body regions (8,18) are shorted to each other. A bridge circuit according to Claim 2, characterized in that it comprises a single, diffused body region (16) containing said source regions (10,20), said body region being connected to said isolation well. A bridge circuit according to Claim 4, characterized in that said single body region (16) is connected to said well through a region (30) bounded by said epitaxial regions (6,7). A bridge circuit according to Claim 1, characterized in that he bipolar transistors (T1,T2) of said first pair are formed in said epitaxial semiconductor layer and laterally spaced from said isolation well (5). A bridge circuit according to Claim 1, characterized in that it comprises at least one further pair of IGBT transistors formed within an isolation well (15) wherein one IGBT of the further pair is connected in parallel to one IGBT of the second pair and wherein the other IGBT of the further pair is connected in parallel to the other IGBT of the second pair. A process of manufacturing a monolithically integrated, transistor bridge circuit according to claim 1 including the step of growing a first epitaxial layer (4) over a semiconductor substrate (3), forming an isolation well (5) adapted to accommodate at least one pair of IGBT transistors (M1,M2), said well (5) being obtained by forming a buried layer with a first type of dopant and subsequently growing respective epitaxial portions (6,7) with an opposite dopant type, each adapted to accommodate one of the transistors (M1,M2) of said IGBT pair, isolation regions (32) being defined to bound said epitaxial portions (6, 7). A process according to Claim 8, characterized in that it comprises a subsequent step of diffusing a single body region (16) extending to the isolation well (15).

Inventors: PALARA SERGIO, ZAMBRANO RAFFAELE, PALARA, SERGIO, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1992
Main classification: H01L27
IPC codes: H01L27