Video signal processing apparatus

Abstract: A video signal processing apparatus for processing a video signal having: a memory circuit for receiving a video signal and storing received video signal; a synchronization signal separation (12) circuit for separating a synchronization signal included by the received video signal, and transmitting the synchronization signal; a first counter (13) for transmitting count data by performing a counting operation in synchonization with the synchronization signal transmitted from the synchronization signal separation circuit or by spontaneously performing the counting operation; a second counter (16) for transmitting count data by spontaneously performing the counting operation; a memory control circuit (14) for controlling writing or reading of the video signal to and from the memory circuit in accordance with the count data transmitted from the first counter; a first decoder (15) for resetting the second counter in accordance with a value denoted by the count data transmitted from the first counter; and a second decoder (17) for resetting the first counter in accordance with a value denoted by the count data transmitted from the second counter, so that a video signal can be formed while preventing disorder of the synchronization signal.

Description: The present invention relates to a video signal processing apparatus for processing a video signal by using a memory thereof. Fig. 1 illustrates the schematic structure of a conventional video signal processing apparatus. Referring to Fig. 1, a video floppy disk 1 is rotated by a motor 1a at a predetermined speed of rotation so that a video signal recorded to the video floppy disk 1 is reproduced by a head 2 and it is then amplified by a pre-amplifier 3. Then, the frequency component of brightness signal Y and that of composite synchronization signal S are extracted by a high-pass filter (HPF) 4, while the frequency component of color difference line sequential signal B-Y/R-Y is extracted by a band-pass filter (BPF) 6. Signals denoting the extracted frequency components are respectively subjected to a variety of processes such as the FM demodulation and the de-emphasis processes in reproduction signal processing circuits 5 and 7 so that the signals are restored to the signal Y·S and the color difference line sequential signal B-Y/R-Y. Then, they are converted into digital signals by A/D converters 8 and 9, and then the digital signals are stored by a memory 19. The color difference line sequential signal B-Y/R-Y, which has been converted into the digital signal by the A/D converter 9, is delayed by a 1H delay line 10 by a degree of 1H (a horizontal period), and then it is stored by the memory 19. A composite synchronization signal is separated from the signal Y·S which has been restored by the reproduction signal processing circuit 5, the composite synchronization signal being separated by a synchronization signal separation circuit 11. Furthermore, a vertical synchronization signal is separated from the composite synchronization signal by a vertical synchronization signal separation circuit 12. An H·V counter 13 counts the composite synchronization signals and the vertical synchronization signals and additionally controls an address control circuit 14 in accordance with the result of the counting operation. The address control circuit 14 controls operations of writing and reading data to and from the memory 19. In accordance with the result of the counting operation performed by the H·V counter 13, a decoder 15 generates composite synchronization signal C-SYNC, a burst flag BF denoting the period in which a burst signal is added and a variety of timing signals such as composite blanking signal C-BLNK which denotes a period in which no image is present in a retrace-line deletion period. The burst flag BF and the composite blanking signal C-BLNK are supplied to a video signal processing circuit 20, while the composite synchronization signal C-SYNC is supplied to an adder 24a. A variety of data items read from the memory 19 are subjected to various processes such as the blanking process and the burst addition process in the video signal processing circuit 20. The signal Y processed by the video signal processing circuit 20 is converted into an analog signal by a D/A converter 22 before it is supplied to the adder 24a. On the other hand, the digital color difference signals B-Y and R-Y are subjected to an orthogonal two phase modulation process by a digital orthogonal two phase modulation circuit 21 so that they are modulated to digital chroma signals. Then, they are converted into analog signals by a D/A converter 23 before they are supplied to a buffer 26 and an adder 24b. The adder 24a adds the signal Y supplied from the D/A converter 22 and the composite synchronization signal C-SYNC supplied from the decoder 15 to each other so as to transmit an addition signal (signal Y·S) to a buffer 25 and the adder 24b. The adder 24b adds the signal Y·S supplied from the adder 24a and the chroma signal supplied from the D/A converter 23 to each other so as to transmit a composite video signal via a buffer 27. The aforesaid operations are controlled by a system control unit 28a. Fig. 2 illustrates the schematic structure of another conventional video signal processing apparatus. The apparatus shown in Fig. 2 is so arranged that a V-servo circuit 29 is additionally provided for the apparatus shown in Fig. 1 but the other structures are the same as those of the apparatus shown in Fig. 1. The apparatus shown in Fig. 2 is arranged in such a manner that the video floppy disk 1 is rotated in synchronization with the vertical synchronization signal V-SYNC transmitted from the decoder 15 at the time of the operation of reading data from the memory 19 by controlling the rotation of the motor 1a by the V-servo circuit 29. Then, a video signal recorded to another track of the video floppy disk 1 is reproduced, and the H·V counter 13 is reset at every 1H in synchronization with the horizontal synchronization signal, which has been, by a horizontal synchronization separation circuit 11a, separated from the Y·S signal of the video signal reproduced consecutively so that ensuing data is written to the memory 19. The above-mentioned operations are controlled by a system control unit 28b. Fig. 3 illustrates the schematic structure of another conventional video signal processing apparatus. The apparatus shown in Fig. 3 is so arranged that an FIFO (First In First Out) memory 19a is used as the memory 19 of the apparatus shown in Fig. 1. Since the FIFO memory 19a is able to individually control the writing address and the reading address, the structure is so arranged that the operations of writing and reading data to and from the FIFO memory 19a are performed independently by controlling address control circuits 14a and 14b by an H·V counter 13a for writing and an H·V counter 13b for reading which are provided respectively. The above-mentioned operations are controlled by a system control unit 28c. However, since the video signal processing apparatus shown in Fig. 1 is so arranged that the H·V counter 13 is reset in response to the synchronization signal (refer to Fig. 4(b)) restored by the reproduction signal processing circuit 5 as shown in Fig. 4, a problem arises in that a discontinuous point (Fig. 4(a)) of the synchronization signal of the transmitted video signal is generated in a case where a new video data is written to the memory 19 consecutively to an operation of reading data from the memory 19 and therefore the reproduced image becomes disordered in the case where the image is displayed on a monitor device on the like. On the other hand, the conventional video signal processing apparatus shown in Fig. 2 is arranged in such a manner that the operation of reproducing the next track is started by rotating the video floppy disk 1 in synchronization with the vertical synchronization signal V-SYNC at the time of the operation of reading the data from the memory 19, and writing of next data to the memory 19 is performed. Therefore, writing and reading of data to and from the memory 19 can be performed consecutively. As a result, the above-mentioned problem can be overcome. However, it is difficult to completely continuously perform the data writing operation and the data reading operation to and from the memory 19 in each horizontal synchronization period. What is worse, too long a time is taken to start the data writing operation and servo control must be always performed because the rotation servo control of the video floppy disk 1 must be performed prior to the writing operation. Furthermore, the necessity of supplying electricity to a drive apparatus for the video floppy disk 1 simultaneously with the operation of reading data from the memory 19 causes the electric power consumption to increase excessively. Although the conventional video signal processing apparatus shown in Fig. 3 is able to maintain the continuity of the synchronization signals because the FIFO memory 19a is capable of independently controlling the data writing address and the reading address, the FIFO memory 19a is expensive when compared with the general-purpose memory 19. A concern of the present invention is to provide a video signal processing apparatus capable of overcoming the above-mentioned problems. In accordance with the present invention there is provided a video signal processing circuit as set out in claim 1. Features and advantages of the invention will now be described by way of example and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram which illustrates the schematic structure of a conventional video signal processing apparatus; Fig. 2 is a block diagram which illustrates the schematic structure of another conventional video signal processing apparatus; Fig. 3 is a block diagram which illustrates the schematic structure of another conventional video signal processing apparatus; Fig. 4 is a timing chart of main signals for the video signal processing apparatus shown in Fig. 1; Fig. 5 is a block diagram which illustrates an embodiment of a video signal processing apparatus according to the present invention; and Fig. 6 is a timing chart of main signals for the video signal processing apparatus shown in Fig. 5. BRIEF DESCRIPTION OF PREFERRED EMBODIMENTS A preferred embodiment of the present invention will now be described with reference to the drawings. Fig. 5 is a block diagram which illustrates an embodiment of a video signal processing apparatus according to the present invention. Fig. 6 is a timing chart of main signals of the video signal processing apparatus shown in Fig. 5. Referring to Fig. 5, the same elements as those shown in Figs. 1 to 4 are given the same reference numerals. Referring to Fig. 5, the video floppy disk 1 is, similarly to the conventional apparatus, rotated by the motor 1a at a predetermined speed of rotation so that a video signal recorded to the video floppy disk 1 is reproduced by the head 2 and it is then amplified by the pre-amplifier 3. Then, the frequency component of brightness signal Y and that of composite synchronization signal S are extracted by the high-pass filter (HPF) 4, while the frequency component of color difference line sequential signal B-Y/R-Y is extracted by the bandpass filter (BPF) 6. Signals denoting the extracted frequency components are respectively subjected to a variety of processes such as the FM demodulation and the de-emphasis processes in the reproduction signal processing circuits 5 and 7 so that the signals are restored to the signal Y·S and the color difference line sequential signal B-Y/R-Y. Then, they are converted into digital signals by the A/D converters 8 and 9, and then the digital signals are stored by the memory 19. The color difference line sequential signal B-Y/R-Y, which has been converted into the digital signal by the A/D converter 9 is delayed by the 1H delay line 10 by a degree of 1H (a horizontal period), and then it is stored by the memory 19. Composite synchronization signal Csync is separated from the signal Y·S which has been restored by the reproduction signal processing circuit 5, the composite synchronization signal being separated by the synchronization signal separation circuit 11. Furthermore, a vertical synchronization signal Vsync is separated from the composite synchronization signal Csync by the vertical synchronization signal separation circuit 12. As will be described later, the H·V counter 13 counts the synchronization signals Csync and Vsync and controls the address control circuit 14 in accordance with the result of counting at the time of writing data. On the other hand, when data is read from memory 19 the H·V counter acts spontaneously to control the address control circuit 14 in accordance with the result of this counting operation. In accordance with the result of the counting operation performed by the H·V counter 13, a decoder 15 generates composite synchronization signal C-SYNC, a burst flag BF denoting the period in which a burst signal is added and a variety of timing signals such as composite blanking signal C-BLNK which denotes a period in which no image is present in a retrace-line deletion period. Furthermore, the decoder 15 generates a reset signal for resetting an H·V counter 16 at the time of transition from a moment data is read from the memory 19 to a moment data is written to the same as described later. The H·V counter 16 starts counting after it has been reset in response to a reset signal generated by the decoder 15 at the time of transition from the moment at which data is read from the memory 19 to the moment at which data is written to the same. In accordance with the result of the counting operation performed by the H·V counter 16, a decoder 17, as will be described later, generates the composite synchronization signal C-SYNC, the burst flag BF and a variety of timing signals such as composite blanking signal C-BLNK. Furthermore, the decoder 17 generates a reset signal for resetting the H·V counter 13 at the time of transition from a moment at which data is read from the memory 19 to a moment at which data is written to the same as described later. The burst flag BF and the composite blanking signal C-BLNK supplied from the decoder 15 or the decoder 17 are supplied to a video signal processing circuit 20 via a selection circuit 18. On the other hand, the composite synchronization signal C-SYNC is supplied to the adder 24a. Therefore, a variety of data items read from the memory 19 are subjected to various processes such as the blanking process and the burst addition process in the video signal processing circuit 20. The signal Y processed by the video signal processing circuit 20 is converted into an analog signal by the D/A converter 22 before it is supplied to the adder 24a. On the other hand, the digital color difference signals B-Y and R-Y are subjected to an orthogonal two-phase modulation process by the digital orthogonal two phase modulation circuit 21 so that they are modulated to digital chroma signals. Then, they are converted into analog signals by the D/A converter 23 before they are supplied to the buffer 26 and the adder 24b. The adder 24a adds the signal Y supplied from the D/A converter 22 and the composite synchronization signal C-SYNC supplied from the selection circuit 18 so as to transmit an addition signal (signal Y·S) to the buffer 25 and the adder 24b. The adder 24b adds the signal Y·S supplied from the adder 24a and the chroma signal supplied from the D/A converter 23 so as to transmit a composite video signal via the buffer 27. The aforesaid operations are controlled by a system control unit 28 as will be described later. Then, the operation for transmitting the video signal to be performed (in period A shown in Fig. 6) after data has been read from the memory 19 will now be described with reference to Figs. 5 and 6. The rotation of the video floppy disk 1 by the motor 1a is inhibited during the aforesaid operation, and as well as the operations of the following elements which are required only at the time of writing data to the memory 19 are inhibited so that the electric power consumption is reduced: the pre-amplifier 3, the HPF 4, the reproduction signal processing circuits 5 and 7, and BPF 6, the A/D converters 8 and 9, the synchronization signal separation circuit 11 and the vertical synchronization signal separation circuit 12. During the aforesaid operation, the H·V counter 13 is controlled in accordance with an instruction issued from the system control unit 28 so that it acts spontaneously independently of the synchronization signal separation circuit 11. Furthermore, the selection circuit 18 is controlled to select the various timing signals transmitted from the decoder 15. Therefore, the data reading address of the memory 19 is controlled by the address control circuit 14 which is controlled in accordance with the result of the counting operation performed by the H·V counter 13 so that data is sequentially read from the memory 19. In accordance with the result of the counting operation performed by the H·V counter 13, the decoder 15 generates the composite synchronization signal C-SYNC, the burst flag BF and the various timing signals such as the composite blanking signal C-BLNK. Hence, the burst flag BF and the composite blanking signal C-BLNK transmitted from the decoder 15 are supplied to the video signal processing circuit 20 via the selection circuit 18, while the composite synchronization signal C-SYNC is supplied to the adder 24a via the selection circuit 18. Therefore, data read from the memory 19 is subjected to a variety of processes by ensuing circuits 21 to 27 before it is transmitted. Then, the operation to be performed in a case where the operation of reading data from the memory 19 is stopped so as to realize the mute or blank state (B in Fig. 6) will now be described. During this operation, the decoder 15 resets the H·V counter 16 in response to a reset signal generated in accordance with the result of the counting operation performed by the H·V counter 13a. On the other hand, the selection circuit 18 is controlled so as to select the various timing signals transmitted from the decoder 17. The H·V counter 16 is so reset in response to a reset signal generated by the decoder 15 that the timing continuity of the composite synthronization signal C-SYNC, the burst flag BF and the various timing signals such as the composite blanking signal C-BLNK transmitted from the decoder 15 is maintained. Therefore, the burst flag BF and the composite blanking signal C-BLNK transmitted from the decoder 17 for mute are supplied to the video signal processing circuit 20 via the selection circuit 18. On the other hand, the composite synchronization signal C-SYNC is supplied to the adder 24a via the selection circuit 18. Hence, all of the video periods are subjected to the blanking process in the video signal processing circuit 20 in the mute state and they are subjected to the various processes in the ensuing circuits 21 to 27 before they are transmitted. Then, the operation to be performed in a case where data corresponding to the signal reproduced from the video floppy disk 1 in the mute state is written (C in Fig. 6) to the memory 19 will now be described. In the aforesaid operation state, the rotation of the video floppy disk 1 is started by the motor 1a. Furthermore, the following elements which are required to write data to the memory are operated: the pre-amplifier 3, the HPF 4, the reproduction signal processing circuits 5 and 7, the BPF 6, the A/D converters 8 and 9, the synchronization signal separation circuit 11 and the vertical synchronization signal separation circuit 12. The H·V counter 13a causes the address control circuit 14 to control the data writing address of the memory 19 so as to write data so that both of the count in the vertical period and the count in the horizontal period are reset in response to the various synchronization signals separated from the reproducing signal Y·S by the synchronization signal separation circuit 11 and the vertical synchronization signal separation circuit 12 in accordance with the instruction issued from the system control unit 28. Finally, the operation to be performed in a case where the operation of reading data from the memory 19 (D in Fig. 6) is again performed by cancelling the mute state after the operation of writing data to the memory 19 will now be described. In this operation, the H·V counter 13a is reset in response to the reset signal generated by the decoder 17. On the other hand, the selection circuit 18 is controlled so as to select the various timing signals transmitted from the decoder 15 in accordance with an instruction issued from the system control unit 28. Furthermore, the H·V counter 13a is so reset in response to the reset signal generated by the decoder 17 that the timing continuity of the composite synchronization signal C-SYNC, the burst, flag BF and the various timing signals such as the composite blanking signal C-BLNK transmitted from the decoder 17 for mute is maintained. The aforesaid embodiment is arranged in such manner that the H·V counter 16 is reset in response to the reset signal, which is generated by the decoder 15 in accordance with the count made by the H·V counter 13a, in a case where the operation of reading data from the memory 19 is transited to the operation of writing data to the same. During the operation of writing data to the memory 19, the H·V counter 13a is operated in synchronization with the synchronization signal, which has been separated from the reproduction V·S signal by the synthronization signal separation circuit 11 and the vertical synchronization signal separation circuit 12, so that data is written to the memory 19 in accordance with the count made by the H·V counter 13a. In a case where the operation of writing data to the memory 19 is transited to the operation of reading data from the same, the H·V counter 13a is reset in response to the reset signal, which has been generated by the decoder 17 in accordance with the count made by the H·V counter 16. During the operation of reading data from the memory, the H·V counter 13a is operated spontaneously so as to read data from the memory 19 in accordance with the count made by the H·V counter 13a. As a result of the thus arranged structure, a video signal can be formed while preventing disorder of the synchronization signal. Furthermore, the servo circuit 29 and the FIFO memory 19a shown in Figs. 2 and 3 are omitted from the structure according to this embodiment, so that a video signal can be formed by a structure the cost of which can be reduced.

Claims: A video signal processing circuit for processing a video signal which includes a synchronization signal, the apparatus comprising: a memory circuit (19) for receiving and storing the video signal; a synchronization signal separation circuit (11) for separating the synchronization signal from the video signal; and an address control circuit (14) for controlling the writing of the video signal to the memory circuit in response to the separated synchronization signal; and characterised in that the apparatus further includes a first counter (13) for transmitting to the address control circuit count data generated by, in a first mode, performing a counting operation in synchronisation with said separated synchronisation signal, said first counter further being adapted to, in a second mode, perform a counting operation independently of said separated synchronisation signal, said address control circuit during a writing operation generating video signal writing addresses for said memory in accordance with the count data generated by said synchronous counting operation of said first mode and transmitted from said first counter; a first decoder (15) for generating additional synchronisation signals independently of said separated synchronisation signal for said video signal processing means in accordance with the value of the count data transmitted from said first counter in said second mode, and further characterised in that the address control circuit is adapted to control the reading of video data from the memory circuit in response to the count data transmitted from the first counter in said second mode, and further comprising a second counter (16) adapted to count independently of said separated synchronization signal and to transmit count data to a second decoder (17) so that said second decoder can generate timing signals for said video signal processing means in response to count data from said second counter during blank periods of the video signal, and a selection circuit (18) for selecting between the outputs of said first and second decoders and wherein said first decoder (15) resets said second counter in response to a predetermined value of said first counter and said second decoder (17) resets said first counter in response to a predetermined value of said second counter. Apparatus according to claim 1 further comprising reproducing means (2) for reproducing and transmitting the video signal from a recording medium in which the video signal including the synchronization signal is recorded, said memory circuit being arranged to receive and store the video signal transmitted from said reproducing means. Apparatus according to either claim 1 or claim 2 and including means (20) for carrying out video signal processing on data read from said memory under the control of said address generating circuit. Apparatus according to any one of the preceding claims, wherein said first decoder is operative to reset said second counter at the time of transition between data being read from said memory and data being written into said memory, and said second decoder is operative to reset said first counter. Apparatus according to any one of the preceding claims and including an addition circuit (24a) adapted to combine a timing signal generated by one of said decoders with an output of said video signal processing circuit.

Inventors: SAKAEGI YUJI, SAKAEGI, YUJI, SAKAEGI, YUJI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N9
IPC codes: H04N9, H04N5