Image processing apparatus

Abstract: When enlargement processing is performed, binary image data inputted from a data line 100 is subjected to contour smoothing by a contour smoothing and enlarging circuit 2 and the data is enlarged by a factor of n (where n is an integer) in the main scanning direction and m (where m is an integer) in the subordinate scanning direction. When reduction processing is performed, the binary image data is outputted as is from a selector 6 to a multivalue-converting circuit 3 via a signal line 200. In the multivalue-converting circuit 3, the binary image is stored temporarily in a memory, the image data of any area is extracted, image data of multivalued density is calculated based upon a window outputted from a weighting table upon making reference to an area comprising a pixel of interest and its peripheral pixels, and the multivalued data is outputted to a variable-power circuit 4 via a signal line 300. In the variable-power circuit 4, the multivalued-density image data is zoomed down to any size by thinning-out processing of an image clock and line synchronizing signal, and the resulting data is outputted to a binarizing circuit 5 via a signal line 400. The binarizing circuit 5 converts the image data of multivalued density into binary data and outputs this data on a data line 500.

Description: This invention relates to an image processing apparatus. More particularly, the invention relates to an image processing apparatus for executing zoom processing which changes binary image data to any magnification and outputting binary image data having a different pixel density. A selected pixel coding method, logical product method, projection method and segmentation-by-nine method are known as methods of converting the pixel density of a binary image expressed by black-and-white binary data. These methods of converting pixel density are for application to characters and line drawings. In a facsimile or word processor, the construction of the apparatus is simple and therefore pixel-density conversion processing, based upon simple thinning-out of pixels and overlay processing and typified by the SPC method, is carried out. Further, a technique for obtaining a moirè pattern-free image of changed magnification (a zoomed image) by zooming based upon simple thinning-out and overlay processing every matrix has been provided as a pixel-density converting method for application to a textured dither image. In the prior art mentioned above, a comparatively good image can be obtained for characters and line drawings in a case where use is made of simple thinning-out and overlay processing every pixel. However, when the above-mentioned processing is applied to a pseudo-half-tone image in which density is expressed by the density of black pixels in a fixed area, the pattern of the black pixels is disturbed, a disturbance in tonality occurs and moirè patterns are produced. For example, when simple thinning-out and overlay processing every pixel is applied to a pseudo-half-tone image obtained by the error-diffusion method, tonality is disturbed and a noisy image is obtained. Similarly, when this processing is applied to a dither image, the period interferes and the moirè pattern is produced owing to the period of the dither matrix and the thinning-out and overlay processing. On the other hand, in thinning-out and overlay processing in which a dither matrix serves as the unit, the dither image expresses density in dither-matrix units, therefore it is possible to obtain a comparatively good zoomed image in which tonality is preserved. However, the conversion magnification is limited and images capable of being handled are limited to pseudo-half-tone images based upon the dither method. Another drawback is that the difference in level of diagonal lines becomes conspicuous with regard to the characters or line drawings in an enlarged image. An image processing apparatus for enlarging or reducing an image is described in EP-A-0264059. As described therein, multi-value image data, e.g. 4-bit data representing 16 gradations, is enlarged by linear interpolation using a ROM look-up table, or is reduced, and the processed multi-value data is then binarised. An alternative apparatus is described in IEEE TRANSACTIONS ON PATENT ANALYSIS AND MACHINE INTELLIGENCE, Vol.4, No.3, pages 331-335, ULICHNEY ET AL: "Scaling Binary Images with the Telescoping Template". The apparatus described therein includes a channel in which input binary data is converted to an analogue signal, interpolated by a filter and binarised, and then resampled. In another channel the input binary data is enlarged using a telescoping template and then resampled. It is mentioned that EP-A-0392701 discloses an image reduction apparatus in which input binary data is converted to multivalue image data and smoothed, then binarised and reduced. In the apparatus of the present invention, as defined by claim 1 appended, a pattern of input binary image data is detected and is used to smooth edge portions of an image as the input binary image data is expanded, each pixel being replaced by a plurality of sub-pixels. The expanded data is then converted to multi-value data, the multi-value data is then reduced and binarised. In embodiments of the present invention it is possible to carry out various kinds of processing, which are used conventionally in multivalued images, by converting a binarised image into density data, wherein an image of changed magnification (a zoomed image) which excels in preservation of density is obtained through similar processing even with regard to an image in which character images and pseudo-half-tone images are mixed. Embodiments of the present invention perform contour smoothing and enlarging processing which decides individual density values following enlargement from the density values of a pixel of interest and pixels peripheral thereto at the time of enlargement, wherein a difference in level of diagonal portions in characters and line drawings can be smoothed by interpolation. In embodiments of the present invention the blurring of edge portions of a character image, which tends to occur when a multivalued conversion is made, can be prevented by varying a window when making a conversion from a binary value to multivalued density. The occurrence of moirè patterns and pseudo-contours in pseudo-half-tone images is suppressed at the same time, whereby a high-quality image that has undergone a pixel-density conversion can be obtained. In the preferred embodiments described hereinbelow, any original image, such as a character image or pseudo-half-tone image, can be changed in magnification at a high quality. With regard to a pseudo-half-tone image, an original image inputted as binary data is converted into density data and changed in magnification, whereby an image which excels in preservation of density can be obtained. In addition, with regard to character images and line drawings, window size is changed in dependence upon the ratio of the change in magnification, thereby making it possible to prevent the blurring of edges, which tends to occur at the time of a multivalued conversion. By performing contour smoothing and enlarging at the time of enlargement, it is possible to obtain an image that has undergone a pixel-density conversion, in which a difference in the level of diagonal portions is smoothly interpolated. Other features and advantages of the present invention and its embodiments will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flowchart showing zoom processing in a first embodiment of the invention; Fig. 2 is a block diagram showing the construction of a pixel density converting apparatus in the first embodiment; Figs. 3 and 4 are block diagrams showing the construction of a contour smoothing and enlarging circuit depicted in Fig. 2; Fig. 5 is a diagram showing the construction of a density-value deciding circuit depicted in Fig. 4; Fig. 6 is a timing chart showing the operation of the counter smoothing and enlarging circuit; Fig. 7 is a diagram illustrating the correspondence between referential pixels and subdivided pixels in contour smoothing and enlargement; Figs. 8, 9 and 10 are diagrams showing patterns for deciding the density values of subdivided pixels from 5 x 5 peripheral-pixel density values; Figs. 11 and 12 are diagrams showing patterns for deciding the density values of subdivided pixels from 5 x 3 peripheral-pixel density values; Figs. 13 and 14 are block diagrams showing the construction of a multivalue-converting circuit depicted in Fig. 2; Fig. 15 is a diagram for describing the relationship between 4 x 4 image data and coordinates; Fig. 16 is a diagram showing the weighting rates of a window for a multivalued conversion; Fig. 17 is a block diagram showing the construction of a timing control circuit depicted in Fig. 2; Fig. 18 is a diagram showing the positional relationship between an original image and a converted image in a magnification-changing circuit; Fig. 19 is a diagram for describing clock thinning at the time of reduction at any magnification rate; Fig. 20 is a timing chart for describing reduction in the main scanning direction; Figs. 21 and 22 are block diagrams for describing the construction of a circuit which obtains reduced pixel density by an arithmetic operation; Fig. 23 is a diagram for describing weighting when reduction zooming is performed; Fig. 24 is a block diagram showing the construction of a binarizing circuit depicted in Fig. 2; Fig. 25 is a diagram showing the relationship between a pixel of interest and pixels which distribute error; Fig. 26 is a block diagram showing the construction of an error-distribution control circuit depicted in Fig. 24; Fig. 27 is a flowchart showing zoom processing in a second embodiment; Fig. 28 is a block diagram showing the construction of a pixel density converting apparatus in the second embodiment; Fig. 29 is a block diagram showing the construction of a binary enlarging circuit depicted in Fig. 28; and Figs. 30 and 31 are timing charts for describing the operation of the binary enlarging circuit. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings. <Description of processing (zoom processing) for changing magnification (Fig. 1)> The flow of processing for changing magnification according to this embodiment will be described in detail with reference to Fig. 1. Fig. 1 is a flowchart illustrating the processing for applying a change in magnification so that binary data of x pixels in the main scanning direction and y pixels in the subordinate scanning direction is changed to binary data of X pixels in the main scanning direction and Y pixels in the subordinate scanning direction. At step S1 of the flowchart, it is determined whether enlargement processing is to be applied regardless of the main or subordinate scanning direction. If enlargement processing is not applied, i.e., if reduction processing is to be applied, the program proceeds to step S3. In case of enlargement processing, the program proceeds to step S2. (1) Enlargement processing If enlargement processing is to be applied, processing for smoothing and enlarging contour is executed at step S2. According to this processing, the binary digital data of x pixels in the main scanning direction and y pixels in the subordinate scanning direction is converted, by pixel-density conversion processing that accompanies the contour smoothing and enlarging processing, into binary data of (nx × my) pixels by changing the magnification by a factor of n in the main scanning direction (n = [X/x], where [a] represents an integer not smaller than a) and m in the subordinate scanning direction (m = [Y/y], where Y>y). Next, at step S3, the binary data obtained at step S2 is scanned pixel by pixel using a window conforming to the ratio of the change in magnification, multivalued-density data is calculated from the pixel pattern of the binary image within the window, and this data is converted into image data of multivalued density of (nx × my) pixels. This is followed by step S4, at which the image data of multivalued density of the (nx × ny) pixel size obtained by the conversion at step S3 is subjected to thinning-out processing by a clock and line synchronizing signal, the data is zoomed down to any size and is converted into image data of multivalued density of (X × Y) pixels. Next, at step S5, the image data of multivalued density of (X × Y) pixels is subjected to binarizing processing, whereby (X × Y)-pixel binary image data of changed magnification is obtained. (2) Reduction processing In case of reduction processing, step S3 is executed, where the (x × y) pixel binary data is scanned pixel by pixel using a window conforming to the ratio of the change in magnification, multivalued-density data is calculated from the pixel pattern of the binary image within the window, and this data is converted into image data of multivalued density of (x × y) pixels. This is followed by step S4, at which the image data of multivalued density of the (x × y) pixel size obtained by the conversion at step S3 is subjected to thinning-out processing by a clock and line synchronizing signal, the data is zoomed down to any size and is converted into image data of multivalued density of (X × Y)-pixels. Next, at step S5, the image data of multivalued density of (X × Y) pixels is subjected to binarizing processing, whereby (X × Y) pixel binary image data of changed magnification is obtained. In the flow described above, window scanning is performed in which the referential pixels differ depending upon the ratio of magnification when the binary image is converted into the multivalued-density image data. At the time of enlargement processing, the binary image is converted into the multivalued-density image data once the enlargement processing has been applied to the data in binary form. As a result, it is possible to obtain a zoomed image in which blurring of edge portions of the image, which occurs at the time of the conversion to the multivalued data, is suppressed to the maximum degree. In addition, by executing the contour smoothing and enlarging processing at the time of enlargement, differences in the level of diagonal lines, which occur when repeated enlarging is performed, can be smoothly interpolated so that it is possible to obtain a high-quality character image. <Description of circuit arrangement (Fig. 2)> Fig. 2 is a block diagram showing the construction of an apparatus for converting pixel density according to this embodiment. The circuit elements will now be described in sequence. In Fig. 2, numeral 100 denotes a data line for inputting data to the apparatus. Specifically, black-and-white binary digital data expressed by one bit (in which "1" represents black and "0" represents white) enters the apparatus on data line 100. In the case where enlargement processing is executed, the binary data inputted from line 100 is enlarged by a factor of n (an integer) in the main scanning direction and m (an integer) in the subordinate scanning direction by contour smoothing and enlargement in a contour smoothing and enlarging circuit 2. The resulting binary data, in which differences in the level of diagonal-line portions are smoothly interpolated by the aforementioned processing, is outputted from a selector 6 to a multivalue-converting circuit 3 (both of which will be described later) via a signal line 200. In the case where a reduction in magnification is carried out, the binary data inputted from the signal line 100 is inputted as is from the selector 6 to the multivalue-converting circuit 3. The selector 6 selects the binary data inputted from signal line 200 at the time of enlargement processing and the binary data inputted from signal line 100 at the time of reduction processing. The selected data is fed into the multivalue-converting circuit 3. In the multivalue-converting circuit 3, the data is temporarily stored in a memory (not shown) and image data in any desired region is extracted. While reference is made to the region, which comprises a pixel of interest and its peripheral pixels, multivalued-density image data (e.g., "0" ∼ "63" in the case of a six-bit output, wherein "0" and "63" represent white and black, respectively) is calculated based upon a window outputted from a weighting table, and the multivalued data is outputted to a variable-power circuit 4 via a signal line 300. Next, the variable-power circuit 4 performs zooming to reduce the multivalued-density image data, which has been outputted by the multivalue-converting circuit 3, to any desired size by the thinning-out processing of an image clock and line synchronizing signal. The resulting image data is outputted to a binarizing circuit 5 via a signal line 400. The binarizing circuit 5 converts the multivalued data outputted by the variable-power circuit 4 into binary data and outputs the binary data on a data line 500. The details of construction of the pixel-density converting apparatus having the foregoing configuration will be set forth with reference to the related diagrams. <Description of contour smoothing and enlarging circuit (Figs. 3 ∼ 12)> Figs. 3 and 4 are diagrams showing the specific construction of the contour smoothing and enlarging circuit depicted in Fig. 2. In this embodiment, a case will be described in which data is enlarged by a factor of two (doubled) in the main and subordinate scanning directions. It should be noted that enlargement by a factor of n in the main scanning direction and and m in the subordinate scanning direction also is possible by combining a plurality of these circuits. In addition, to raise resolution by subdivision and to enlarge are taken to have the same meaning. In this circuit, subdivision is performed when inputted binary image data is outputted, and the densities of pixels obtained by subdividing the pixel of interest are decided in dependence upon the pattern of the peripheral pixels, whereby the contour smoothing of diagonal lines is performed with regard to character images and line drawings. Image clocks CLK1, CLK2 and line synchronizing signals DB1, DB2, where are inputted to the circuit, enter from a timing control circuit 1, described later. In a case where the image clock CLK1 and line synchronizing signal DB1 are subjected to enlarging processing by a factor of n in the main scanning direction and m in the subordinate scanning direction, the result of frequency-dividing the image clock CLK2, following multiple processing, by n and the result of frequency-dividing the line synchronizing signal DB2 by m are selectively inputted by a selector 120 (Fig. 17) of the timing control circuit 1. Shown in Figs. 3 and 4 are line memories 211 - 215 for holding inputted binary image data, shift registers 22A - 22Y, a density-value deciding circuit 230 for deciding individual pixel densities, after the execution of subdivision processing, from inputted matrix data, and a line selector 240 for extracting the individual pixel data, which is inputted in parallel from the density-value deciding circuit 230, upon synchronizing this data to the image clock CLK2 line by line. The operation of this circuit will now be described in detail with reference to the drawings. First, one line of binary image data in the main scanning direction is read in the line memory 211 of the line memory group, and this data is shifted, in line units, in the subordinate scanning direction in the following manner: line memory 212 → 213 → 214 → 215. The image data from the line memories 211 - 215 is read out in synchronization with CLK1 outputted by the timing control circuit 1 so that five pixels of parallel data in the subordinate scanning direction are shifted to respective ones of the shift registers 22Y, 22T, 220, 22J, 22E. The five pixels of image data in the subordinate direction thus shifted in are shifted successively through the shift registers in synchronization with CLK1. Here matrix data of 5 lines x five pixels is extracted from the shift registers 22A - 22Y, and this data is inputted to the density-value deciding circuit 230. The density-value deciding circuit 230 outputs pixel data M11 - M22, which is obtained by subdividing or breaking up a pixel of interest (the data in shift register 22M in this example), which is located at the center of the 5 x 5 array, into four parts and performing interpolation processing. The outputted data enters the line selector 240 in parallel fashion. The line selector 240 selects the image data of the output line and outputs the subdivided image data in synchronization with the output image clock CLK2. Figs. 5 and 6 illustrate the details of the line selector 240. In Fig. 5, the interpolated pixel data M11, M12, M21, M22 from the density-value deciding circuit 230 enters multiplexers 241, 242 in synchronization with the image clock CLK1 of the pixel prior to subdivision. The pixel data (M11, M12 in this example) of the outputted line is selected by multiplexers 241, 242, and the selected pixel data enters AND gates 243, 244. The pixel data (e.g., M11, M12) whose density has been doubled in the main scanning direction is successively selected in accordance with CLK1 by a selector constructed by the AND gates 243, 244 and an OR gate 245. The selected pixel data is finally delivered to a D-type flip-flop 246 which, in synchronization with the pixel clock CLK2, outputs subdivided image data of the kind shown at OUT in Fig. 7. Whenever one line of image data is read in the line memory 221 in synchronization with DB1, the multiplexers 241, 242 are changed over sequentially in synchronization with DB2 to extract two lines of subdivided pixel data, whereby image data subdivided by a factor of two in the subordinate scanning direction can be obtained. In the density-value deciding circuit 230, a flag is inputted from image discriminating means. The latter is for determining whether the pixel of interest is a character or line-drawing area or whether it is a pseudo-half-tone area. In case of a pseudo-half tone, the arrangement is such that the input data from the shift register 22M, which is that of the pixel of interest, is outputted as is to M11 through M22. Thus, if it is determined that the pixel of interest is that of a pseudo-half-tone image, the foregoing processing makes it possible to output the subdivided-pixel data without interpolating it. As a result, the deleterious side-effects of contour smoothing and enlargement on pseudo-half tones can be prevented. Furthermore, by repeating similar processing using the output of the density-value deciding circuit 230 as new matrix data, it is possible to obtain a high-density converted image whose density has been multiplied four-fold in the main and subordinate directions or eight-fold in the main and subordinate directions, etc. Next, the relationship between the matrix data inputted to the density-value deciding circuit 230 and the outputted subdivided image data will be described in detail. Fig. 7 is a diagram showing referential pixels and subdivided pixels according to this embodiment. In Fig. 7, M represents the pixel of interest, A through Y represent referential pixels, and M11 through M22 represent subdivided pixels. Figs. 8, 9 and 10 illustrate patterns for deciding the density values of the individual subdivided pixels versus the density values of the referential pixels. In Figs. 8 through 10, no reference is made to the pixels crossed out. In the patterns which decide the density values, the referential pixels determine whether the pixel of interest is part of a diagonal line, a portion which indicates a right angle, or some other portion. In Figs. 8 and 9, (a) through (l) illustrate patterns for performing interpolation processing in a case where the pixel of interest is a white pixel. In case of (a), the referential pixels H and L in Fig. 7 are black and the referential pixels I and Q are white, wherein it is judged that the pixel of interest is part of a black diagonal line whose inclination is tan = 1. The density of M11 is reversed from white to black. Similarly, in case of (b) through (d), the pattern (a) is rotated successively 90° each time from symmetry. In case of (e), the referential pixels H, I and L in Fig. 7 are black and the referential pixel Q is white, wherein it is judged that the pixel of interest is part of a black diagonal line whose inclination is tan = 1/2. The densities of the two pixels M11 and M12 are reversed from white to black. In case of (f) through (h), the pattern (e) is rotated successively 90° each time from symmetry. In (i) through (l), the pattern (e) is flipped over and then rotated successively 90° each time. On the other hand, (m) through (t) illustrate patterns for performing interpolation processing in a case where the pixel of interest is a black pixel. In case of (m), the referential pixels G, H, I, J and L in Fig. 7 are white and the referential pixel Q is white, wherein it is judged that the pixel of interest is part of a white diagonal line whose inclination is tan = 1/3. The densities of the two pixels M11 and M12 are reversed from black to white. Similarly, in case of (n) through (p), the pattern is rotated successively 90° each time from symmetry. In case of (q) through (t), the pattern is flipped over and then rotated successively 90° each time. The individual actions of the interpolation processing in each pattern will now be described. (1) Detection of right angles In case of a pattern other than those described above, density is not reversed and the density of each subdivided pixel is made a density identical with that of the original image. As a result, when the pixel of interest is white and the referential pixels H, I, L, Q are black, for example, it is determined that a right-angle portion is present, interpolation processing is not executed and the right-angle portion is reproduced clearly. (2) Detection of inclination of diagonal lines In a case where the pixel of interest is a white pattern, as in patterns (a) through (l), the number of subdivided pixels reversed in density from white to black in patterns (a) through (d) differs from that in patterns (e) through (l). By thus detecting the inclination of a diagonal line and changing the number of pixels which undergo a reversal in density depending upon a difference in inclination, an image whose contours are smoothed more effectively with regard to steeply inclined diagonal lines and gently inclined diagonal lines can be obtained. Similarly, in a case where the pixel of interest is a black pattern, as in patterns (m) through (t), two pixels undergo a density reversal from black to white so that more effective contour smoothing can be applied to steep diagonal lines and gently diagonal lines. (3) Preventing the cancellation of the interpolating effect in slanted lines having inclinations of tan = 1, 1/2, 2 The inclination of the diagonal-line detection pattern which undergoes density reversal in a situation where the pixel of interest is a white pattern as in (a) through (1) differs from that in a situation where the pixel of interest is a black pattern as in (m) through (t). When a pattern in which white and black are reversed with respect to individual pixels in the patterns (a) through (l) is used in a situation where the pixel of interest is a white pattern, the interpolation processing is cancelled out with regard to diagonal lines tan = 1, 1/2, 2. As a result, the steps of the diagonal lines are merely shifted and the effect of interpolation is lost. Consequently, by changing the angle of diagonal-line detection (performing processing with respect to tan = 1/3 when the pixel of interest is black) between the case where the pixel of interest is a white pattern (a) through (l) and a case where the pixel of interest is a black pattern (m) through (t), it is possible to apply effective contour smoothing to diagonal lines tan = 1, 1/2, 2 as well. (4) Preventing missing black diagonal lines owing to a fine diagonal-line judgment In a case where the pixel of interest is a black pattern, as in patterns (m) through (t), reference is made to G, I, Q, S shown in Fig. 7. However, when the pixel of interest is a white pattern, as in patterns (a) through (1), no reference is made to G, I, Q, S. In other words, contour smoothing is applied effectively to black diagonal lines composed of connected individual dots, and no interpolation processing is applied to white diagonal lines composed of connected individual dots. As a result, it is possible to prevent missing connections in fine, black diagonal lines, which is a side effect of the contour smoothing of white diagonal lines. A circuit in which the above-described patterns are formed by logic circuitry is the density deciding circuit 230. This circuit is constructed as a logical operation unit for pixel density conversion. An example of another method is to use a ROM in which the outputs of the registers A through Y are adopted as 25-bit address inputs and the densities of M11 through M22 have been written in as data. Though a case has been described in which doubling is performed in both the main and subordinate scanning directions, processing is executed in the same manner also when doubling in the subordinate scanning direction or in the main scanning direction. Figs. 11 and 12 are patterns showing the relationship among the pixel of interest, the peripheral pixels and pixels obtained by subdividing the pixel of interest in a case where enlargement is performed by a factor of two in the subordinate scanning direction. In a case where enlargement is performed by a factor of two in the subordinate scanning direction, it will suffice to divide the pixel of interest in half in the subordinate scanning direction and decide the subdivided-pixel density in accordance with the relationships shown in Figs. 11 and 12. In the case of patterns other than these, the corresponding pixel of interest is adopted as the density value of the subdivided pixels. In a case where doubling is performed in the main scanning direction, it will suffice to use the results obtained by rotating Figs. 11 and 12 by 90°. Furthermore, by making various combinations of doubling in the main scanning direction and doubling in the subordinate scanning direction, contour smoothing and enlargement by a factor of m in the main scanning direction and n in the subordinate scanning direction becomes possible. <Description of multivalue-converting circuit (Figs. 13 - 16)> The specific construction of the multivalue-converting circuit 3 shown in Fig. 2 will now be described with reference to Figs. 13 and 14. The multivalue-converting circuit 3 according to this embodiment comprises line memories 31a - 31d, a shift-register group 320, a weighting table 330, a data selecting multiplexer 340, a gate group 350, an adder 360, a data line 370 on which data is outputted from the weighting table 330, and a data line 380 for selecting a data group from the weighting table 330 in dependence upon the rate of change in magnification. On the basis of the inputted binary data, reference is made to an area comprising the pixel of interest (i,j) and its peripheral pixels, average density weighted by a weight mask (in this embodiment, matrix data outputted by the weighting table 330) corresponding to each pixel within the area is calculated, and this is outputted as multivalued density data (having a maximum value of 63 in the case of six bits). The operation of the multivalue-converting circuit 3 will now be described in detail. First, in a case where enlargement processing is performed in either the main or subordinate scanning direction, the binary image data is inputted from the input line 200 in synchronization with the image clock CLK2 and line synchronizing signal DB2. In case of reduction processing, binary image data is inputted from input line 100 as is in synchronization with the image clock CLK2 = CLK1 and line synchronizing signal DB2 = DB1. The inputted binary image data first is read in line memory 31a of the line-memory group 310, and the data is sequentially shifted through the line memories in the manner 31b → 31c → 31d in the subordinate scanning direction line by line in synchronization with the line synchronizing signal DB2. Four pixels of parallel data in the subordinate scanning direction are read out of the line memories 31a - 31d in synchronization with the image clock CLK2, and this data is shifted into the shift-register group 320. In the shift-register group 320, the image data is successively shifted in synchronization with the image clock CKL2, image data having a matrix of four pixels by four lines is extracted, and this data is inputted to the gate group 350 as matrix data composed of 16 bits. If the data latched in shift register C3 is adopted as the pixel of interest (i,k), then, as shown in Fig. 15, each of the peripheral pixels will be data in which A1 is (i-2,j-2), A2 is (i-1,j-2), A3 is (i,j-2) and A4 is (i+1,j-2) and, in similar fashion, B1 is (i-2,j-1), B2 is (i-1,j-1), B3 is (i,j-1), B4 is (i+1,j-1), C1 is (i-2,j), C2 is (i-1,j), C4 is (i+1,j), D1 is (i-2,j+1), D2 is (i-1,j+1), D3 is (i,j+1) and D4 is (i+1,j+1). Several types of matrix data of size 4 x 4 are stored in the weighting table 330 in advance. The sum of the matrix data outputted to the gate-group 350 is normalized in the weighting table 330 so as to attain the maximum value of the multivalued output (a maximum of 63 in the case of a six-bit output). Fig. 16 illustrates an example of weighting applied to individual pixels of the weighting table 330. For example, in case of a 90% reduction rate, a 3 × 3 window (the window size is made 3 × 3 by making "0" the weights of the pixels peripheral to the 3 × 3 window) having a large specific gravity with respect to the pixel of interest is used, as shown in (b) of Fig. 16. In case of a large reduction rate, a flat window of the kind shown in (c) of Fig. 16 is used. In case of a reduction rate of less than 50%, the window size is enlarged in dependence upon the reduction rate. Address data for selecting a window conforming to the ratio of the change in magnification is inputted to the data multiplexer 340 via signal line 380, one of the matrix-data groups of the weighting table 330 is selected in dependence upon the address data, and the selected data is inputted to the gate group 350. Next, in a case where the image data extracted from the latches A1 through D4 is indicative of a black pixel, the gates in the gate group 350 which correspond to the individual latches open and the numerical data outputted by the data selecting multiplexer 340 is outputted to the adder 360. In case of image data indicative of a white pixel, the gates corresponding to the individual latches close and "0" is outputted to the adder 360. The sum of the data outputted by the gate group 350 is calculated by the adder 360, and the sum is outputted on the signal line 300 as multivalued data of the pixel of interest. The signal line 380 in this embodiment inputs data in dependence upon the ratio of the change in magnification. However, a multivalued image having greater picture quality can be obtained by storing windows, which have appropriate weights for a character or line diagram or for a pseudo-half-tone image, in the weighting table 330 in advance, inputting data to which has been added the results of discrimination from an image discriminating circuit which discriminates whether the pixel of interest is a pseudo-half-tone area or a character/line-drawing area, and selecting separate matrix data with respect to individual image areas. In this embodiment, the referential-pixel area for calculating the multivalued data is composed of 4 pixels × 4 lines. However, this does not impose a limitation, for the referential-pixel area can be increased or decreased with ease by increasing or decreasing the line memories, shift registers, gates and weighting table. <Description of the variable-power circuit (Figs. 17 through 23)> The details of the variable-power circuit 4 for subjecting multivalued image data to reduction processing will now be described. First, processing for reducing an image by means of the variable-power circuit 4 is performed by thinning out of the image clocks and line synchronizing signals. Owing to simplicity of construction, this processing will described taking as an example the SPC (selected pixel coding) method, in which the converted image takes on the values of pixels closest to the original pixels. Before proceeding with the description, reference will be had to Fig. 17 to describe the details of the timing control circuit 1, which outputs an image clock signal CLK3 and a line synchronizing signal DB3 following reduction processing. In Fig. 17, numeral 110 denotes a quartz oscillator for generating a reference clock, 120 a selector, which selects an image clock and a line synchronizing signal, for outputting the image clocks CLK1, CLK2 and line synchronizing signals DB1, DB2, numeral 130 a main-scanning image clock control circuit for performing any desired clock thinning in dependence upon the reduction ratio of the variable-power circuit in the main scanning direction, and 140 a subordinate scanning-line synchronizing signal control circuit for performing any desired clock thinning in dependence upon the reduction ratio of the variable-power circuit in the subordinate scanning direction. In the foregoing arrangement, the selector 120, on the basis of an externally inputted reference clock CLK0, selects and outputs image clocks CLK1, CLK2, which are obtained by frequency-dividing the reference clock in dependence upon the ratio of magnification, in the main scanning direction, of the contour smoothing and enlargement circuit 2, and line synchronizing signals DB1, DB2 similarly decided by the ratio of magnification, in the subordinate scanning direction, in the contour smoothing and enlargement circuit 2. The outputted image clock CLK2 enters the main-scanning image clock control circuit 130, where the input image clock CLK2 is subjected to thinning processing in dependence upon the reduction ratio of the variable-power circuit 4, thereby outputting the image clock CLK3 of the reduced image data. Similarly, thinning processing of the line synchronizing signal DB2, which is reduction processing in the subordinate scanning direction in the variable-power circuit 4, is executed in the subordinate scanning-line synchronizing signal control circuit 140, whereby a line synchronizing signal DB3 of image data of the changed magnification is outputted. The details of operation of the main-scanning image clock control circuit 130 will now be described with reference to Fig. 18. By way of example, in a case where the main scanning direction is reduced to γ x /R x (where γ x , R x represent arbitrary integers decided by the rate of reduction), the converted pixels will be disposed at intervals of distance R x if the original pixels are disposed as intervals of distance γ x , as shown in Fig. 18. If we let ΔX = R x - γ x hold and the coordinates of the first original pixel and of the first converted pixel are made to coincide with the origin, ΔX is added to each original pixel such that the difference between the distances of the second original pixel and converted pixel is Δx and the difference between the distances of the third original pixel and converted pixel is 2ΔX. Whenever the result of addition becomes greater than the distance γ x between the original images, the distance γ x is subtracted from the result of addition, at which time the coordinates of the original image are advanced by one. When the differences between the distances of the original image and converted image are thus calculated and the coordinates of the original image are thus advanced in dependence upon the results of calculation, the original image is advanced at a certain fixed rate in dependence upon the rate of reduction. Thinning processing in conformity with the ratio of reduction is carried out by making the remaining pixels the converted pixels. When similar processing is performed taking 2/γx as the difference between the distances of the original image and converted image at the origin, thinning out of the original image is performed in such a manner that pixels of the converted image that are closest to the original image are selected. This is the equivalent of the SPC (selected pixel coding) method. Reference will be had to Figs. 19 and 20 to describe in detail the operation of the main-scanning image clock control circuit 130 for a case where the pixel size of the original image in the main scanning direction is γ x = 256. In Fig. 19, numerals 410, 420 denote D-type flip-flops, 430 an eight-bit output adder having a carry-signal line, and 440 a gate circuit which gates the clock CLK2. As shown in Fig. 19, ΔX is inputted to the adder 430 in synchronization with CLK2. Here ΔX is a value decided in dependence upon the ratio of the change in magnification. For example, in case of reduction to 8/11, we have ΔX = 256 × 11/8 - 256 = 96. The output of the adder 430 at the time of reset is γ x /2 = 128. The result of the addition processing outputted on signal line 405 enters the D-type flip-flop 420 and is inputted to the adder 430 in synchronization with CLK2. The values outputted by the D-type flip-flops 420 and 430 are added by the adder 430 in synchronization with the image clock CLK2, so that ΔX is successively added to the immediately preceding results of addition. Only eight bits of data from the output of the adder 430 are returned to the D-type flip-flop 420 via the signal line 405. Accordingly, whenever the result of addition exceeds γx (256), subtraction of γx is carried out. The image clock CLK2 inputted to the gate 440 is subjected to masking processing by the carry signal of adder 430 outputted on the output line 406, and the image clock CLK3 obtained by thinning out the clock CLK2 is outputted. As illustrated in Fig. 20, the image data inputted in synchronization with the image clock CLK2 is sampled by CLK3, whereby thinning-out processing in the main scanning direction is performed. The subordinate scanning-line synchronizing signal control circuit 140 is constructed in the same manner as the main-scanning image clock control circuit 130, thinning-out processing is applied to the line synchronizing signal DB2, and DB3 is outputted. Reduction in the subordinate scanning direction is performed by thinning out the line synchronizing signal in the same manner as in the main scanning direction. In this embodiment, a case is described in which the original image is thinned out and reduced by thinning out the image clock and line synchronizing signal using the variable-power circuit 4. However, it is also possible to obtain a converted image by processing using the original image data and perform processing for changing magnification. The processing for changing magnification in this case will now be described. As set forth above, the difference between the distances of the original image and converted image can be obtained as an output from the main-scanning image clock control circuit 130 and subordinate scanning-line synchronizing signal control circuit 140. Accordingly, the weighting of image data in the vicinity of the converted pixels is carried out from the positional relationship between the original image and the image whose magnification has been changed, and the converted-image density is calculated, whereby it is possible to obtain multivalued density data, whose magnification has been changed, from the SPC method, which data excels in terms of density preservation. As for the weighting method, use can be made of the distance inverse-proportion method. It is also possible to use the rate of area occupancy, namely the area which the converted pixel occupies in the original pixels. The portion enclosed by the broken line in Fig. 23 represents the original pixels, and the portion enclosed by the solid line represents the converted pixels. Figs. 21 and 22 are block diagrams illustrating the construction of a density calculating circuit for the case where the rate of area occupancy is used. Shows in these drawings are a line-memory group 610 composed of line memories 610a, 610b, 610c, a shift-register group 620, a weighting-coefficient calculating circuit 630 for calculating the weights of individual pixels from the positional relationship between converted pixels and original pixels, a multiplier group 640 composed of a plurality of multipliers 640a, 640b, 640c, 640d, 640e, 640f, 640g, 640h, 640i, and an adder 650. In this arrangement, data indicative of the original pixels (peripheral pixels) in the vicinity of the converted pixel (the pixel of interest) can be obtained by the line-memory group 610 and shift-register group 620 in the same manner as the case illustrated by the multivalue-converting circuit 3. In this embodiment, an example is illustrated in which, when reduction in excess of 50% is performed, the fact that the converted pixel receives the influence of a maximum of nine pixels with regard to the original pixels is taken into consideration, and matrix data of 3 pixels × 3 lines is extracted by the aforementioned circuit. It is possible for the referential pixels to be taken arbitrarily, in the same manner as the case illustrated by the multivalue-converting circuit 3. A method of calculating weighting coefficients outputted by the weighting-coefficient calculating circuit 630 will now be described. As illustrated in Fig. 23, the lengths (R X -Δxx, γ X , Δxx-γ X , R Y -Δyy, γ Y , Δyy-γ Y ) of individual sides of the converted pixel divided by the original pixels are obtained using the results of addition and the carry signals (Δxx, Δyy) outputted by the main-scanning image clock control circuit 130 and subordinate scanning-line synchronizing signal control circuit 140. Here Δxx, Δyy are the differences between the distances of the original pixels and the converted pixel inclusive of the carry signal. In a case where the converted pixel does not span three pixels of the original pixels, the lengths of the individual sides are represented by R X -Δxx, Δxx, R Y -Δyy, Δyy. Next, the area which the converted pixel occupies in the original pixels is calculated from the lengths of the sides. For example, the area a which the converted pixel occupies in an original pixel A is (R X -Δxx) × (R Y -Δyy), and the area b which the converted pixel occupies in an original pixel B is γ X × (R Y -Δyy). Areas c, d, e, f, g, h and i are subsequently calculated in the same manner. The individual areas a, b, c, d, e, f, g, h and i are normalized by the area of the converted pixel, and the results are used as the weighting coefficients of the corresponding pixels. The weighting is uniquely defined by the differences Δxx, Δyy between the distances of the original image and converted image outputted by the main-scanning image clock control circuit 130 and subordinate scanning-line synchronizing signal control circuit 140. Therefore, it will suffice to store the weighting data in a ROM table using Δxx, Δyy as the addresses of the table, and use this ROM in place of the weighting-coefficient calculating circuit 630. An arrangement using a ROM in this manner is possible also in the case of the distance inverse-proportion method. Next, weighting of original pixel density is carried out with regard to the weighting data obtained by the weighting-coefficient calculating circuit 630. In this processing, a product i with regard to the original pixel density value is obtained by multipliers 640a through 640i, the sum of the outputs from the individual multipliers is obtained by the adder 650, and the sum is eventually outputted as the density value of the pixel of interest. <Description of binarizing circuit (Figs. 24 - 26)> Fig. 24 is a diagram showing a specific example of the construction of the binarizing circuit 5 illustrated in Fig. 2. The binarizing circuit 5 converts the image data, which has been converted into multivalued data in the multivalue-converting circuit 4, back into binary data and outputs binary data the magnification of which has been changed. All binarizing methods, such as the dither method or the mean error minimizing method can be utilized as the binarizing method. Here use is made of the error diffusion method, through which it is possible to obtain a zoomed image having excellent density preservation, by performing binarization upon diffusing, to the peripheral pixels, the error produced when binarization is carried out. The details of the binarizing circuit 5 using error diffusion processing will now be described with reference to the drawings. Shown in Fig. 24 are D-type flip-flops 51a - 51d which latch data, adders 52a - 52d, a line memory 530 for a one-line delay, a comparator 540, and an error allocating control circuit 560. In the above-described arrangement, image data of multivalued (e.g., "0" ∼ "63" in the case of six bits) density outputted by the variable-power circuit 4 is inputted via signal line 400 in synchronization with the image clock CLK3 and line synchronizing signal DB3. Here the inputted multivalued density data [the multivalued density data of the original image corresponding to the position (i,j) of the pixel of interest] is added, by adder 52d, to the sum of the errors allocated to this pixel position, and the resulting signal is outputted to the comparator 540 and error allocating control circuit 560. The comparator 540 compares the data on the signal line with a fixed threshold value TH (e.g., "32" in case of six-bit data). If the value of the data on the signal line is greater than the threshold value TH, "1" (black) is outputted on signal line 500 in synchronization with the image clock CLK3 and line synchronizing signal DB3. If the value of the data on the data line is less than TH, "0" (white) is outputted on the signal line 500 in synchronization with these signals. Next, in dependence upon the results of binarization, the error allocation control circuit 560 calculates error quantities 56a - 56d, which are allocated to the peripheral pixels, with the data inputted from signal line 550 serving as the error if the the output is white, and the difference between signal line 550 and a constant T ("63" in case of six-bit data) serving as the error if the output is black. When position of the pixel of interest is (i,j), as shown in Fig. 25, the error-quantity signals 56a - 56d are added, by the respective adders 52a - 52d, to the error quantities already allocated to the peripheral pixels (i-1, j+1), (i, j+1), (i+1, j+1), (i+1, j). Though the number of pixels to which the error is allocated are the four pixels of the pixel of interest, this does not impose a limitation; the number readily be increased or decreased. The details of construction of the error allocating circuit 560 will now be described with reference to Fig. 26. Shown in Fig. 26 are a subtractor 561, a selector 562 and multipliers 563a - 563d for performing prescribed multiplication operations. First, the subtractor 561 calculates the difference (signal 550 constant T) between the signal 550 of correction density, obtained by adding the allocated error to the original image density, and the signal (constant T = 63) from signal 570, and outputs this difference to the selector 562. In dependence upon the binarized result inputted from the signal line 500, the former (signal 550) is selected if the binarized result is "0" (white), and the latter (signal 550 - T) is selected if the binarized result is "1" (black). The selected item is outputted to the multipliers 563a - 563d. As shown in Fig. 25, the multipliers 563a - 563d correspond to the peripheral pixels (i-1, j+1), (i, j+1), (i+1, j+1), (i+1, j) having the respective weights w 1 - w 4 with respect to the pixel of interest (i,j). The following multiplication operations are performed in dependence upon the weight, and the results are outputted on signal lines 56a, 56b, 56c and 56d: By virtue of the binarizing method described above, it is possible to obtain a binary image, which excels in preservation of density, with regard to pseudo-half tones. In accordance with this embodiment, as described above, regardless of whether the inputted binary digital image is a pseudo-half tone or character image, processing for conversion from a binary value to multiple values is performed, the individual pixels are converted into multivalued densities, and then zoom processing for changing magnification is carried out, whereby a high-quality image of any zoom magnification can be obtained. At the time of enlargement processing, a character or line drawing is subjected to contour smoothing and enlargement decided by the pixel of interest and its peripheral pixels. As a result, it is possible to smoothen the differences in level of diagonal-line portions, which tend to become conspicuous when a character or line drawing is enlarged. A second embodiment according to the invention will now be described with reference to the drawings. In the first embodiment set forth above, contour smoothing and enlargement is carried out as enlargement processing. In the second embodiment, enlargement processing is executed by enlarging a binary value by a factor of an integral number. <Description of zoom processing (Fig. 27)> The flow of processing for changing magnification according to this embodiment will be described in detail with reference to Fig. 27. Fig. 27 is a flowchart illustrating the processing for applying a change in magnification so that binary data of x pixels in the main scanning direction and y pixels in the subordinate scanning direction is changed to binary data of X pixels in the main scanning direction and Y pixels in the subordinate scanning direction. At step S11 of the flowchart, it is determined whether enlargement processing is to be applied regardless of the main or subordinate scanning direction. If enlargement processing is not applied, i.e., if reduction processing is to be applied, the program proceeds to step S13. In case of enlargement processing, the program proceeds to step S12. (1) Enlargement processing If enlargement processing is to be applied, processing for binary enlargement by a factor of an integral number is executed at step S12. According to this processing, the binary digital data of x pixels in the main scanning direction and y pixels in the subordinate scanning direction is converted, by overlay processing, into binary data of (nx × my) pixels by zooming by a factor of n in the main scanning direction (n = [X/x], where [a] represents an integer not smaller than a) and m in the subordinate scanning direction (m = [Y/y], where Y>y). Next, at step S13, the binary data obtained at step S12 is scanned pixel by pixel using a window conforming to the ratio of the change in magnification, namely the zoom ratio, multivalued-density data is calculated from the pixel pattern of the binary image within the window, and this data is converted into image data of multivalued density of (nx × my) pixels. This is followed by step S14, at which the image data of multivalued density of the (nx × ny) pixel size obtained by the conversion at step S13 is subjected to thinning-out processing by a clock and line synchronizing signal, the data is zoomed down to any size and is converted into image data of multivalued density of (X × Y) pixels. Next, at step S15, the image data of multivalued density of (X × Y) pixels is subjected to binarizing processing, whereby (X × Y)-pixel binary image data of changed magnification is obtained. (2) Reduction processing In case of reduction processing, step S13 is executed, where the (x × y) pixel binary data is scanned pixel by pixel using a window conforming to the ratio of the change in magnification, multivalued-density data is calculated from the pixel pattern of the binary image within the window, and this data is converted into image data of multivalued density of (x × y) pixels. This is followed by step S14, at which the image data of multivalued density of the (x × y) pixel size obtained by the conversion at step S13 is subjected to thinning-out processing by a clock and line synchronizing signal, the data is zoomed down to any size and is converted into image data of multivalued density of (X × Y) pixels. Next, at step S15, the image data of multivalued density of (X × Y) pixels is subjected to binarizing processing, whereby (X × Y)-pixel binary image data of changed magnification is obtained. In the flow described above, window scanning is performed in which the referential pixels differ depending upon the ratio of magnification when the binary image is converted into the multivalued-density image data. At the time of enlargement processing, the binary image is converted into the multivalued-density image data once the enlargement processing has been applied to the data in binary form. As a result, it is possible to obtain a zoomed image in which blurring of edge portions of the image, which occurs at the time of the conversion to the multivalued data, is suppressed to the maximum degree. <Description of circuit arrangement (Fig. 28)> Fig. 28 is a block diagram showing the construction of an apparatus for converting pixel density according to this embodiment. The circuit elements will now be described in sequence. In Fig. 28, numeral 100 denotes the data line for inputting data to the apparatus. Specifically, black-and-white binary digital data expressed by one bit (in which "1" represents black and "0" represents white) enters the apparatus on data line 100. In the case where enlargement processing is executed, the binary data inputted from line 100 is enlarged by a factor of n (an integer) in the main scanning direction and m (an integer) in the subordinate scanning direction by overlay processing in a binary enlarging circuit 7. The resulting data is outputted from the selector 6 to the multivalue-converting circuit 3 via a signal line 700. In the case where a reduction in magnification is carried out, the binary data inputted from the signal line 100 is inputted as is from the selector 6 to the multivalue-converting circuit 3. The selector 6 selects the binary data inputted from signal line 700 at the time of enlargement processing and the binary data inputted from signal line 100 at the time of reduction processing. The selected data is fed into the multivalue-converting circuit 3. In the multivalue-converting circuit 3, the data is temporarily stored in a memory (not shown) and image data in any desired region is extracted. While reference is made to the region, which comprises a pixel of interest and its peripheral pixels, multivalued-density image data (e.g., "0" ∼ "63" in the case of a six-bit output, wherein "0" and "63" represent white and black, respectively) is calculated based upon a window outputted from a weighting table, and the multivalued data is outputted to the variable-power circuit 4 via the signal line 300. Next, the variable-power circuit 4 changes magnification to reduce the multivalued-density image data, which has been outputted by the multivalue-converting circuit 3, to any desired size by the thinning-out processing of an image clock and line synchronizing signal. The resulting image data is outputted to the binarizing circuit 5 via a signal line 400. The binarizing circuit 5 converts the multivalued data outputted by the variable-power circuit 4 into binary data and outputs the binary data on a data line 500. The details of construction of the pixel-density converting apparatus having the foregoing configuration will be set forth with reference to the related diagrams. The timing control circuit 1, multivalue-converting circuit 3, variable-power circuit 4, binarizing circuit 5 and selector 6 are the same as in the first embodiment and need not be described again. <Description of binary enlarging circuit (Figs. 29 - 31)> Fig. 29 is a block diagram illustrating the construction of the binary enlarging circuit 7 shown in Fig. 28. As illustrated in Fig. 29, the binary enlarging circuit 7 comprises a line buffer 710, a line-buffer controller 720 and a D-type flip-flop 730. Simple repeated processing is performed by control of the image clocks CLK1, CLK2 and line synchronizing signals DB1, DB2, whereby the binary image is enlarged. First, binary image data, in which one pixels is represented by one bit, is inputted to the line buffer 710 in synchronization with the image clock CLK1 and line synchronizing signal DB1 outputted by the timing control circuit 1. In the case where the image clock CLK1 and line synchronizing signal DB1 are enlarged by a factor of n in the main scanning direction and m in the subordinate scanning direction, the result of frequency-dividing the image clock CLK2, following overlay processing, by n and the result of frequency-dividing the line synchronizing signal DB2 by m are selected by the timing control circuit and inputted to the binary enlarging circuit. Next, the binary image data inputted from signal line 100 is written in the line buffer 710 by the line-buffer controller 720 in synchronization with the image clock CLK1 and line synchronizing signal DB1. At the same time, binary image data is read out and outputted on signal line 740 in synchronization with CLK1 and DB2. By virtue of the relationship between DB2 and DB1, data is read out m times whenever one line of image data is written in, and enlargement processing by a factor of m is performed in the subordinate scanning direction. As an example, a case in which processing for enlargement by a factor of two in the subordinate scanning direction is illustrated in Fig. 30. As shown, image data inputted in synchronization with DB1 is read out of the memory in synchronization with DB2 and data on the same line is outputted twice. The image data outputted from the line buffer 710 in synchronization with the image clock CLK1 enters the D-type flip-flop 730 via the signal line 740 and is sub-sampled by the image clock CLK2. That is, one bit of binary data inputted in synchronization with CLK1 is sampled n times by CLK2, whereby enlargement is performed by a factor of n in the main scanning direction. Fig. 31 is a timing chart showing a case in which enlargement is performed by a factor of two in the main scanning direction. In accordance with this embodiment, as described above, regardless of whether the inputted binary digital image is a pseudo-half tone or character image, processing for conversion from a binary value to multiple values is performed, the individual pixels are converted into multivalued densities, and then processing for changing magnification is carried out, whereby a high-quality pseudo-half-tone image can be obtained. In addition, when the binary data is converted into multivalued data, the binary data is enlarged as is at the time of enlargement processing, thereby suppressing the blurring of character and line-drawing edges. Similarly, a high-quality binary image of changed magnification can be obtained by changing the weighting, at the time of multivalued conversion, by the zoom ratio. As many apparently widely different embodiments of the present invention can be made without departing from the scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: An image processing apparatus for executing enlargement processing which is to change the magnification of binary image data representing an image to another magnification and to output binary image data having a different pixel density, comprising: input means (100) for inputting binary image data; enlarging means (2) for converting the binary image data input by said input means into second binary image data comprising a plurality of respective sub-pixels in place of respective pixels of the input binary image data, thereby enlarging the image, said enlarging means (2) being adapted to detect a pattern of plural pixels of the input binary image data to decide a condition of the second binary image data comprising the plurality of sub-pixels so as to smooth edge portions of the image, in accordance with the detected pattern; multivalue-converting means (3) for converting the second binary data from said enlarging means into multivalue image data; reduction means (4) for executing thinning-out processing on the multivalue image data to produce reduced multivalued image data of another magnification; and binary-value converting means (5) for converting the reduced multivalue image data into binary image data. Apparatus according to claim 1, wherein said enlarging means (2) is adapted to decide a condition of the second binary image data so as to smooth edge portions of the image in a case where the input binary image data is a character-image, or to enlarge the input binary image data by a factor of a predetermined integer number in a case where the input binary image data is a pseudo half-tone image. Apparatus according to claim 1 including selector means (6) for applying the input binary image data directly to said multi-value-converting means (3) in a case where said image processing apparatus is to perform reduction processing of the input binary image data. Apparatus according to claim 1, wherein said multivalue-converting means is adapted to change window size and weighting of binary data, which is referred to when a multivalue-conversion is performed, in dependence upon ratio of change in image size. Apparatus according to claim 1 wherein said multivalue-converting means is adapted to change window size and weighting of binary data, which is referred to when a multi-conversion is performed, in dependence upon whether the respective pixel of interest is contained in a character-image area or a pseudo half-tone area. The apparatus according to any preceding claim, wherein said binary-value converting means is adapted to convert the multivalue image data produced by said reduction means into binary image data by using an error diffusion method.

Inventors: BANNAI YUICHI, USHIDA KATSUTOSHI, YAMAMOTO KUNIHIRO, BANNAI, YUICHI, USHIDA, KATSUTOSHI, YAMAMOTO, KUNIHIRO, BANNAI, YUICHI, C/O CANON KABUSHIKI KAISHA, USHIDA, KATSUTOSHI, C/O CANON KABUSHIKI KAISHA, YAMAMOTO, KUNIHIRO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N1
IPC codes: H04N1, G06T3