MOS operational amplifier circuit

Abstract: An operational amplifier circuit is composed of a differential amplifier circuit for delivering a signal which is obtained by amplifying a difference between voltage levels of two signals; a level shift circuit for shifting and delivering the voltage level of the signal delivered from the differential amplifier circuit; a first amplifier circuit for amplifying and delivering the signal from the level shift circuit; and a second amplifier circuit for amplifying and delivering the voltage level of the signal delivered from the differential amplifier circuit, and a CMOS output circuit whose conductive state is controlled in accordance with voltage levels of the signals delivered from the first and second amplifier circuits.

Description: BACKGROUND OF THE INVENTION 1) Field of the Invention The present invention relates to an operational amplifier circuit, and in particular to an operational amplifier circuit suitably used for a MOS integrated circuit. 2) Description of the Related Art MOS operational amplifiers have been widely used for adding and subtracting analog signals and so forth. For example, a prior art reference "MOS Operational Amplifier Design A Tutorial Overview", IEEE Journal of Solid-State Circuits, VOL. SC-17, No. 6, December 1982, Pages 969 to 981, discloses a conventional MOS operational amplifier circuit. A typical MOS operational amplifier circuit is composed of a differential amplifier circuit, a level shift circuit and an output circuit. This operational amplifier circuit serves as an AB operational amplifier which applies a large current to a load connected to its output when a signal is delivered thereto, but decreases a current running through the output stage when no signal is delivered. However, the conventional MOS operational amplifier circuit sometimes delivers an output signal having a distortion in a transient zone in which one of two MOS FETs that constitute the output stage and are connected in series, is turned on from its turned off condition since this one of MOS FETs is normally turned on. Further, It has been required that the conventional MOS operational amplifier circuit applies a large current to a small output load resistor so as to generate an output signal at a power source voltage level. Accordingly, it raise a problem in that large scale integration with a high density is difficult since the ratio W/L (where W is gate width and L is gate length) of the MOS FETs which constitute the output stage should be large. SUMMARY OF THE INVENTION An object of the present invention is to provide an operational amplifier circuit which can deliver an output waveform having a less distortion. The other object of the present invention is to provide an operational amplifier circuit which is suitable for an integrated circuit. The other object of the present invention is to provide an operational amplifier circuit which has less current consumption. In order to attain the above-mentioned object, the present invention provides an operational amplifier circuit according to the appended independent claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram illustrating an embodiment of an operational amplifier circuit according to the present invention; and Fig. 2 is a view illustrating signal waveforms at nodes in the operational amplifier circuit according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 1 which is a circuit diagram illustrating an embodiment of an operational amplifier circuit according to the present invention, the operational amplifier circuit is preferably composed of a complementary metal oxide semiconductor (CMOS). This operational amplifier circuit comprises a differential amplifier circuit 50 for amplifying an input voltage applied to a normal phase input terminal 51 in accordance with a voltage difference between the normal phase input terminal 51 and a reverse phase input terminal 52, and then applying the thus amplified voltage to a node N1; a level shift circuit 60 for shifting the level of the voltage applied to the node N1 and then applying the thus shifted voltage to a node N2; a first amplifier circuit 70 for amplifying the voltage applied to the node N2 and then applying the same to a node N3, a second amplifier circuit 80 for amplifying the voltage applied to the node N1 and then applying the same to a node N4; an output circuit 90 connected to an output terminal, for applying an output voltage to the output terminal in accordance with the voltages applied to the nodes N3, N4, and a first and a second phase compensation circuit for preventing oscillation. The first phase compensation circuit is composed of a first source follower circuit 100 and a capacitor 103, and controls the voltage at the node N1 in accordance with the voltage at the node N3 (through feed-back operation). The first source follower circuit 100 is connected between the node N1 and the node N3 through the intermediary of the capacitor 103 and comprises an NMOS transistor 101 and an NMOS transistor 102. The NMOS transistor 101 has a gate connected to the node N3, a drain connected to a positive power source terminal 120 and a source connected to a drain of the NMOS transistor 102. Further, the substrate of the NMOS transistor 101 is connected to the drain of the NMOS transistor 102. The NMOS transistor 102 has a gate connected to a bias terminal 124, a source connected to a negative power source terminal 122, and the drain connected to the source of the NMOS 101. Further, the capacitor 103 is connected to the node N1 and the source of the NMOS transistor 101. The second phase compensation circuit 110 comprises a second source follower circuit 110 and a capacitor 113, and controls the voltage at the node N1 in accordance with the voltage at the node N4. The second source follower circuit 110 is connected between the nodes N1, N4 through the intermediary of the capacitor 113, and comprises PMOS transistors 111, 112. The PMOS transistors 111 has a gate connected to a bias terminal 126 applied with a bias voltage Vb2, a source connected to the positive power source terminal 120, and a drain connected to a source of the PMOS transistor 112. The PMOS transistor 112 has a gate connected to the node N4, a drain connected to the negative power source terminal 122, and the source connected to the drain of the PMOS transistor 111. Further, the capacitor 113 is connected to the node N1 and the source of the PMOS transistor 112. The differential amplifier circuit 50 is connected between the positive power source terminal 120 applied with a positive source power (+V) and the negative power source terminal 122 applied with a negative source power (-V), and comprises input NMOS transistors 53, 54, an NMOS transistor 55 constituting a low current source, PMOS transistors 56, 57 constituting a load. The NMOS transistor 53 has a gate connected to the normal phase input terminal 51, a drain connected to a drain of the PMOS transistor 56, and a source connected to a drain of the NMOS transistor 55. The NMOS transistor 54 has a gate connected to a reverse phase input terminal 52, a drain connected to a drain of the PMOS transistor 57 and a source connected to a drain of the NMOS transistor 55. The NMOS transistor 55 has a gate connected to the bias terminal 124 applied with a bias voltage Vb1, the drain connected commonly to the sources of the NMOS transistor 53 and the NMOS transistor 54, and a source connected to the negative power source terminal 122. The PMOS transistors 56, 57 have sources commonly connected to the positive power source terminal 120 and gates commonly connected to the drain of the NMOS transistor 53. The level shift circuit 60 is connected to the differential amplifier circuit 50, and comprises NMOS transistors 61, 62. The NMOS transistor 61 has a gate connected to the node N1, a drain connected to the positive power source terminal 120, and a source connected to the node N2. Further, the substrate of the NMOS transistor 61 is connected to the node N2. The NMOS transistor 62 has a gate connected to the bias terminal 124, a source connected to the negative power source terminal 122, and a drain connected to the node N2. The first amplifier circuit 70 is connected to the level shift circuit 60, and comprises PMOS transistors 71 and an NMOS transistor 72. The PMOS 71 has a source connected to the positive power source terminal 120, and a drain and a source connected to the node N3. Further, the PMOS transistor 71 serves as a load. The NMOS transistor 72 has a gate connected to the node N2, a gate connected to the negative power source terminal 122, and a drain connected to the node N3. The second amplifier circuit 80 is connected to the differential amplifier circuit 50, and comprises a PMOS transistor 81 and an NMOS transistor 82. The PMOS transistor 81 has a source connected to the positive power source terminal 120, and a drain connected to the node N4. The NMOS transistor 82 has a gate and a drain connected to the node N4, and a source connected to the negative power source terminal 122. The NMOS transistor 82 severs as a load. The output circuit 90 has a PMOS transistor 91 and an NMOS transistor 92. The PMOS transistor 91 has a gate connected to the node N3, a source connected to the positive power source terminal 120, and a drain connected to the output terminal 93. The NMOS transistor 92 has a gate connected to the node N4, a source connected to the negative power source terminal 122, and a drain connected to the output terminal 93. It is noted that the PMOS transistor 91 has a threshold voltage which is equal to that of the PMOS transistor 71. Further, the NMOS transistor 82 has a threshold voltage which is equal to that of the NMOS transistor 92. Then, explanation will be made of operation of the operational amplifier circuit according to the present invention shown in Fig. 1. (a) Operation of Current Supply to Load connected to Output Terminal: Referring to Fig. 2 which is a view illustrating the relationship between signal waveforms at the nodes in the operational amplifier circuit according to the present invention, and potential level, and in which the ordinate exhibits voltage level and the abscissa exhibits signal waveform configuration at the nodes. The waveform configuration at each node is shown with a time t0 as a reference. It is estimated that the level of a signal applied to the reverse phase input terminal 52 is at a signal input midpoint. An input signal having a positive voltage level with respect to the reverse phase input terminal 52 (signal input midpoint potential level) is applied to the normal phase input terminal 51. This input signal is amplified and applied to the node N1 by the differential amplifier circuit 50 with the same phase as that of the input signal. The input signal applied to the node N1 is shifted in the positive direction by a degree corresponding to a variation in voltage at the node N1, and is applied to the node N2 by the level shift circuit 60. It is noted that the level shift circuit 50 has a voltage gain of 1, and accordingly, the input signal applied to the node N1 is not amplified thereby. The input signal applied to the node N2 and level-shifted, is amplified by the first amplifier circuit 70 with a reverse phase by a degree corresponding to a variation in voltage at the node N2, and is then applied to the gate of the PMOS transistor 91 through the intermediary of the node N3. Then, the gate-source voltage of the PMOS transistor 91 becomes higher so that the PMOS transistor 91 is activated. Accordingly, a current from the power source is fed to the load connected to the output terminal 93. Further, upon activation of the PMOS transistor 91, the voltage at the node N3 is impedance-converted by the first source follower circuit 100, and is then fed back to the node N1 through the intermediary of the capacitor 103. Accordingly, it is possible to surely prevent the operational amplifier circuit from oscillating. Meanwhile, the input signal applied to the node N1 is amplified with reverse phase by a degree corresponding to a variation in voltage produced at the node N1, and is applied to the gate of the NMOS transistor 92 through the intermediary of the node N4 by the second amplifier circuit 80. Then, the gate-source voltage of the NMOS transistor 92 becomes lower so that the current at the drain of the NMOS transistor 92 decreases. However, since the NMOS transistor 82 is provided, the voltage at the node N4 is maintained at the threshold voltage inherent to the NMOS transistor 82. Accordingly, the NMOS transistor 92 having a characteristic the same as that of the NMOS transistor 82 is not completely turned off. (b) Operation of Absorption of Current from Load connected to Output Terminal: An input signal having a negative voltage level with respect to the reverse phase input terminal 52 is applied to the normal phase input terminal 51 by the differential amplifier circuit 50. This input signal is amplified and is applied to the node N1 with the same phase as that of the input signal. The input signal applied the node N1 is amplified by the second amplifier circuit 80 by a degree corresponding to a variation in voltage produced at the node N1 with reverse phase, and is then applied to the gate of the NMOS transistor 92 through the intermediary of the node N4. Accordingly, the NMOS transistor 92 is activated, contrary to that mentioned above. Thus, it is possible to absorb a current from the load connected to the output terminal 93. Further, since the voltage at the node N3 increases, contrary to that mentioned above, the PMOS transistor 91 is turned off. However, since the PMOS transistor 71 is provided, the voltage at the node N3 is maintained at the threshold voltage inherent to the PMOS transistor 71. Accordingly, the PMOS transistor 91 having a characteristic the same as that of the PMOS transistor 71, is not completely turned off. Further, upon activation of the NMOS transistor 91, the voltage at the node N4 is impedance-converted by the second source follower circuit 110, and is then fed back to the node N1 through the intermediary of the capacitor 113. Accordingly, it is possible to prevent the operational amplifier circuit from oscillating. As mentioned above, according to the present invention, the voltage applied to the output terminal 93 is shifted smoothly from the positive direction to the negative direction or from the negative direction to the positive direction since the voltages with which the PMOS transistor 91 and the NMOS transistor 92 constituting the output circuit 90 are not completely turned off, are applied to the gates of these transistors 91, 92, a distortion (crossover distortion) in the waveform produced at the output terminal 93 can be reduced. Further, according to the present invention, a large current can be applied to the load connected to the output terminal 93 even though the W/L ratio of the MOS transistor constituting the output circuit is increased. Accordingly, the operation amplifier circuit can have a large degree of integration. Further, it is possible to reduce current consumption at the time when no signal is inputted.

Claims: An operational amplifier circuit composed of MOS FETs comprising: a first power supply terminal (120) applied to a first voltage level (V + ); a second power supply terminal (122) applied to a second voltage level (V - ); a first node (N1), a second node (N2), a third node (N3) and a fourth node (N4); a first input terminal (51) and a second input terminal (52); an output teminal (93); a differential amplifier circuit (50) coupled to said first and second power supply terminals (120, 122), said first and second input terminals (51, 52) and said first node (N1) for outputting a first signal having a voltage level proportional to the difference between the voltage level applied to said first input terminal (51) and the voltage level applied to said second input terminal (52) to said first node (N1); a level shift circuit (60) coupled to said first and second power supply terminals (120, 122) and said first and second nodes (N1, N2) for outputting to said second node a second signal which is obtained by shifting the voltage level of said first signal; a first amplifier circuit (70) coupled to said first and second power supply terminals (120, 122) and said second and third nodes (N2, N3) for amplifying said second signal and for outputting a third signal corresponding to said amplified second signal to said third node (N3) and including a first MOS FET (71) of a first conductivity type having a source connected to said first power supply terminal (120), a gate and a drain commonly connected to said third node (N3); a second amplifier circuit (80) coupled to said first and second power supply terminals (120, 122) and said first and fourth nodes (N1, N4) for amplifying said first signal and for outputting a fourth signal corresponding to said amplified first signal to said fourth node (N4) and including a second MOS FET (82) of a second conductivity type having a source connected to said second power supply terminal (122), a gate and a drain commonly connected to said fourth node (N4); and an output circuit (90) coupled to said first and second power supply terminals (120, 122), said third and fourth nodes (N3, N4) and said output terminal (93) including a third MOS FET (91) of the first conductivity type having a source connected to said first power supply terminal (120), a gate connected to said third node (N3) and a drain connected to said output terminal (93) and a fourth MOS FET (92) of the second conductivity type having a source connected to said second power supply terminal (122), a gate connected to said fourth node (N4) and a drain connected to said output terminal (93) for outputting a fifth signal to said output terminal (93) in response to said third and fourth signals, respectively, wherein said third and fourth MOS FETs (91, 92) are adapted to be completely or incompletely turned on in dependency on the respective voltage levels of said third and fourth signals, wherein said first MOS FET (71) has a threshold voltage level which is equal to a threshold voltage level of said third MOS FET (91) and said second MOS FET (82) has a threshold voltage level which is equal to a threshold voltage level of said fourth MOS FET (92). An operational amplifier circuit according to claim 1, wherein said first and fourth MOS FETs (71, 92) of the first conductivity type are NMOS transistors and said second and third MOS FETs (82, 91) of the second conductivity type are PMOS transistors. An operational amplifier circuit according to claim 1 or 2, wherein said level shift circuit (60) comprises a fifth n-type MOS FET (61) having a drain connected to said first node (N1) and a source connected to said second node (N2) and a sixth n-type MOS FET (62) having a drain connected to said second node (N2), a source connected to said second power supply terminal (122) and a gate connected to a bias terminal (124) applied to a predetermined voltage. An operational amplifier circuit according to any of the preceding claims, wherein said first amplifier circuit (70) further comprises a seventh n-type MOS FET (72) having a drain connected to said third node (N3), a source connected to said second power supply terminal (122) and a gate connected to said second node (N2). An operational amplifier according to any of the preceding claims, wherein said second amplifier circuit (80) further comprises an eighth p-type MOS FET (80) having a drain connected to said fourth node (N4), a source connected to said first power supply terminal (120) and a gate connected to said first second node (N2). An operational amplifier circuit according to any of the preceding claims, wherein said third signal has a voltage level ranging from said second voltage level (V - ) to the threshold voltage level of said first MOS FET (71). An operational amplifier circuit according to any of the preceding claims, wherein said fourth signal has a voltage level ranging from said first voltage level (V + ) to the threshold voltage level of said second MOS FET (82). An operational amplifier circuit according to any of the preceding claims, wherein said operational amplifier circuit further comprises: a first feedback circuit (100, 103) connected between said first node (N1) and said third node (N3) for feeding back the voltage level of said third node (N3) to said first node (N1); and a second feedback circuit (110,113) connected between said first node (N1) and said fourth node (N4) for feeding back the voltage level of said fourth node (N4) to said first node (N1).

Inventors: OKAMOTO SEIJI, OKAMOTO, SEIJI, Okamoto, Seiji, c/o Oki Electric Ind. Co., Ltd.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1992
Main classification: H03F3
IPC codes: H03F3