Logarithmic amplification circuit

Abstract: A logarithmic amplification circuit is provided which comprises a differential amplifier (A1...An), a full-wave rectifier (B0...Bn) including two half-wave rectifiers connected so as to have their input signals reverse in phase to each other and respectively receiving an input signal and output signal of said differential amplifier, and an adder (ADD) for adding the output signals of said full-wave rectifier. It is preferable that each of the half-wave rectifiers forming said full-wave rectifier (B0...Bn) includes a differential transistor (Q₁,Q₂,Q₃,Q₄) pair only one transistor of which has an emitter resistor (RE). In this case, two sets of differential transistor pairs of said two half-wave rectifiers are arranged so that the transistors (Q₂,Q₃) each having an emitter resistor (RE) have their collectors connected with each other, the transistors (Q₁,Q₄) not having an emitter resistor have their collectors connected with each other, one of an output signal and input signal of said differential amplifier is applied to the base of one of the transistors each having an emitter resistor and one of the transistors each not having an emitter resistor, the other of an output signal and input signal of said differential amplifier is applied to the base of the other of the transistors each having an emitter resistor (RE) and the other of the transistors each not having an emitter resistor, and the transistors of each pair are connected respectively to constant current sources (I₀). In the preferred embodiments of this invention, said differential amplifier (A1...An) is provided plurally in a series connection and the input signals or output signals of these plural differential amplifiers are inputted to a plurality of rectifiers (B0...Bn) in a respective manner.

Description: This invention relates to a logarithmic amplification circuit. A logarithmic amplification circuit shown in Fig. 1 is well-known as a conventional one, which is a logarithmic amplification circuit described in the Plessey Corporation's Catalogue SL521, and comprises a differential amplifier consisting of transistors TR1 and TR2 as a first stage and a half-wave rectifier consisting of a differential transistor pair TR4 and TR5 only one transistor of which has an emitter resistor RE ( the emitter resistor RE is connected to the transistor TR5 in Fig. 1) as a second stage. The operational principle thereof will be explained below. In Fig. 1. if an electric current flowing into a resistor R1 is expressed as I0, a voltage to be applied between the transistors TR4 and TR5 is expressed as VB4.5. base voltages of the transistors TR4 and TR5 are respectively expressed as VBE4 and VBE5. collector currents of the transistors TR4 and TR5 are respectively expressed as Ic4 and Ic5 and its current amplification factor is expressed as α F, the following equation is established; VB4,5 + VBE4 + (Ic5/αF)RE - VBE5 = 0 In Eq. (1), if kT/q = VT, where k is Boltzmann's constant, T is anabsolute temperature, and q is a unit electron charge, then, there exists the following relations between the VT and the base voltages VBE4 and VBE5 of respective transistors TR4 and TR5 as; VBE4 >> VT, VBE5 >> VT. In addition, if saturation currents of the differential transistor pair TR4 and TR5 are respectively expressed as Is4 and Is5, the following equations are satisfied as; VBE4 = VT.ln(Ic4/Is4) VBE5 = VT.ln(Ic5/Is5) Here, by substituting Eqs. (2) and (3) into Eq. (1) and supposing as Is4 = Is5, Eq. (1) may be explained as follows; VB4,5 + VT.ln(Ic4/Ic5) + (Ic5/αF)RE = 0 On the other hand, there exists the following relation between the current I0 to be flowed into the resistor R1 and the collector currents Ic4 and Ic5; αF·I0 = Ic4 + Ic5 Hence, by eliminating Ic4 using Eq. (5), Eq. (4) may be explained below; VB4,5 + VT·ln[(αF·I0/Ic5) - 1] + (Ic5/αF)RE = 0 Next, in order to obtain the slope of a curve showing the change of the collector current Ic5 with the inter-base voltage VB4,5 of the differential transistor pair TR4 and TR5, the Ic5 in Eq. (6) is differentiated with respect to VB4,5, and the following equation may be obtained;. dIc5 dVB4,5 = - 1 VT Ic5(α F · I0 - Ic5) α F · I 0 + RE α F The absolute value of Eq. (7) can be maximized when the denominator becomes minimum, that is, in case of being established the following equation ( the same manner may be used with respect to Ic4); Ic5 = Ic4 = (1/2) αF·I0 Thus, the maximum absolute value may satisfy the following equation; An inter-base voltage VB4,5 in this case becomes as follows; VB4,5 = (-1/2)RE.I0 Fig. 2 shows a relation of a voltage between the bases VB4,5 and the collector current Ic5. As seen from Fig. 2, in order to obtain a half-wave rectification characteristic in the conventional logarithmic amplification circuit as described above, the inter-base voltage VB4,5 is required to be provided with a voltage offset of about 4VT (about 100 mV). Therefore, the conventional logarithmic amplification circuit is unavoidably necessary to have a circuit for providing a voltage offset to the differential input voltage (VB4,5), which means that there exists such a problem that not only the input circuit is complicated, but also the dynamic range is difficult to be expanded. In addition, it utilizes the half - wave rectification characteristic, resulting in arising a problem that amplification is difficult to be carried out with high accuracy. EP-A-0 248 428 discloses a bipolar logarithmic amplifier having half-or full-wave rectifiers consisting of unbalanced emitter-coupled transistor pairs whose emitter areas are different from each other. The emitter area difference adds an input offset voltage to the emitter-coupled pair. Therefore, the emitter-coupled pair whose emitter area ratio is K (K > 1) is a half-wave rectifier. Also, the cross-coupled, emitter-coupled transistor pair whose emitter area ratio is K operates as a full-wave rectifier. To make the rectification characteristic of the rectifier different from each other, a very large value of K and an emitter resistor are required. US-A-4 990 803 discloses a similar bipolar logarithmic amplifier. The difference between the two amplifiers is that an input offset voltage is produced outside the transistor pair in EP-A-0 248 428, and that the input offset voltage is produced within the transistor pair in the amplifier of US-A-4 990 803. JP-A-2-265310 discloses a logarithmic compression amplifier with cascade-connected half-wave rectifiers and an adder without any differential amplifier and which has a pseudo - logarithmic half-wave rectifier characteristic. EP-A-0 484 139 discloses a logarithmic amplifying circuit, and it is cited here because it falls under Art. 54(3) EPC. Thus, an object of this invention is to provide a logarithmic amplification circuit which has a simple input circuit and a wide dynamic range as compared with conventional ones. Another object of this invention is to provide a logarithmic amplification circuit capable of performing high accuracy amplification. These objects are solved with the features of the claims. By utilizing the full-wave rectifier according to the invention, a voltage offset can be eliminated, so that an input circuit can be made simple in structure, and by lowering the lower limit, the dynamic range can be further widened. Thus, by utilizing two sets of differential transistor pair, the characteristic dispersion of the components of the circuit can be set off, making it possible to effect high accuracy amplification. Further in the preferred embodiments, a logarithmic full-wave rectifier is used as the full-wave rectifier. In this invention, the logarithmic full - wave rectifier comprises two sets of differential transistor pair only one transistor of which has an emitter resistor. A plurality of logarithmic full-wave rectifiers as shown above are provided so as to be different in the product of a resistance value of the emitter resistor and a current value of the constant current source from each other and connected in series to each other. As a result, even if the number of stages of the differential amplifiers is reduced, a wide dynamic range and high accuracy amplification can be provided. The invention will be described in detail in connection with the drawings in which Fig. 1 is a block diagram of a conventional logarithmic amplification circuit, Fig. 2 is a characteristic diagram showing a relation of an inter-base voltage VB4,5 and a collector current Ic5 of the conventional circuit shown in Fig. 1, Fig. 3 is a block diagram of a logarithmic amplification circuit according to one embodiment of this invention, Fig. 4 is a block diagram of a full-wave rectifier to be used in the circuit shown in Fig. 3 according to the embodiment of this invention, Fig. 5 is a characteristic diagram showing the relations of an input voltage Vi, output currents I1 and I2 and collector currents Ic1, Ic2, Ic3 and Ic4 of the full-wave rectifier shown in Fig. 4, Fig. 6 is a characteristic diagram showing a relation of the absolute value of an input voltage V1 and an output current difference (I1-I2) of the full-wave rectifier shown in Fig. 4, Fig. 7 is a block diagram of another example of the logarithmic full-wave rectifier to be used in the circuit shown in Fig. 3 according to the embodiment of this invention, Fig. 8 is a characteristic diagram showing the relations of an input voltage Vi, output currents I1 and I2, and collector currents Ic2, Ic2', Ic2'', Ic3, Ic3' and Ic3'' of the logarithmic full-wave rectifier shown in Fig. 7, Fig. 9 is a characteristic diagram showing a relation of an input voltage Vi and an output current IOUT of a logarithmic amplification circuit using the logarithmic full-wave rectifier shown in Fig. 7. Preferred embodiments of this invention will be described below while referring to Figs. 3 to 9. Fig. 3 schematically shows a logarithmic amplification circuit according to one embodiment of this invention. The logarithmic amplification circuit shown in Fig. 3 comprises n differential amplifiers A1 to An (gains GV1 to GVn) connected in series, (n+1) full-wave rectifiers B0 to Bn respectively receiving input signals to or output signals from the differential amplifiers A1 to An for rectification, and an adder ADD for adding the output currents IOUT0 to IOUTn from the (n+1) full-wave rectifiers B0 to Bn. The rectifier B0 receives an input signal to be inputted to the differential amplifier A1, the rectifiers B1 to Bn receive output signals outputted from the differential amplifiers A1 to An, respectively. The adder ADD adds the outputs IOUT0 through IOUTn outputted respectively from the (n+1) rectifiers B0 to Bn and outputs an output current IOUT. The full-wave rectifiers B0 to Bn each is arranged as shown in Fig. 4. In Fig. 4, transistors Q1 and Q2 form a first differential transistor pair whose emitters are connected with each other through an emitter resistor, and transistors Q3 and Q4 form a second differential transistor pair whose emitters are connected with each other through an emitter resistor. In these first and second transistor pairs, each ofthe transistors Q2 and Q3 only has an emitter resistor. The collectors of the transistors Q2 and Q3 each having an emitter resistor are connected with each other, while the collectors of the transistors Q1 and Q4 each not having an emitter resistor are also connected with each other. The bases of the transistor Q1 not having an emitter resistor and the transistor Q3 having an emitter resistor and the bases of the transistor Q2 having an emitter resistor and the transistor Q4 not having an emitter resistor are connected with each other, respectively, and a differential input voltage Vi which is an input signal to or an output signal from said differential amplifier is applied between the common bases. The differential transistor pairs Q1, Q2 and Q3, Q4 are connected respectively to constant current sources I0. As seen from Fig. 4, this full-wave rectifier includes two differential transistor pairs, wherein only one of the transistors of each pair has an emitter resistor, the differential transistor pair each has the same structure as the circuit shown in Fig.1, and their inputs are connected inversely to each other. Namely, these are arranged so that an input signal of the second differential transistor pair Q3 and Q4 is made inverse in phase to an input signal of the first differential transistor pair Q1 and Q2. As a result, respective collector currents Ic1, Ic2, Ic3, and Ic4 of the transistors Q1, Q2, Q3 and Q4 are varied equally to those shown in Fig. 2 (see Fig. 5). Thus, if the output signals of the first and second transistor pairs are expressed as I1 and I2, the following are established; I1 = Ic1 + Ic4 I2 = Ic2 + Ic3 As a result, the changes of the output currents I1 and I2 with the input voltage Vi will become as shown in Fig. 5. Referring to Fig. 5, the output currents I1 and I2 each has such a characteristic that is turned back at the point of the input voltage Vi = 0 (symmetric characteristic), which means that the circuit shown in Fig. 4 has a full-wave rectification characteristic and yet has no existing offset existed. In addition, it can be found from Fig. 5 that there exist the relations as shown in Fig. 6 between the absolute value of the input voltage Vi (in dB unit) and the output current difference (I1 - I2). Fig. 7 shows another arrangement of the (n+1) full-wave rectifiers B0 to Bn shown in Fig. 3. The circuit shown in Fig. 7 is a pseudo logarithmic full-wave rectifier including a plurality of full-wave rectifiers shown in Fig. 4 connected in parallel, which respectively have emitter resistor having different resistance values RE, RE', RE'', ········ from each other, and constant current sources having different current values I0, I0', I0'', ..... from each other. For the sake of convenience, in Fig. 7, a first full-wave rectifier including a differential transistor pair Q1 and Q2 and a differential transistor pair Q3 and Q4, a second full-wave rectifier including a differential transistor pair Q1' and Q2' and a differential transistor pair Q3' and Q4', and a third full-wave rectifier including a differential transistor pair Q1'' and Q2'' and a differential transistor pair Q3'' and Q4'' are shown. The input voltage Vi is applied between the common bases of each full - wave rectifier, that is, in the first rectifier, it is applied between the common base of the transistors Q1 and Q3 and the common base of the transistors Q2 and Q4, in the second rectifier, it is applied between the common base of the transistors Q1' and Q3' and the common base of the transistors Q2' and Q4', and in the third rectifier, it is applied between the common base of the transistors Q1'' and Q3'' and the common base of the transistors Q2'' and Q4''. With the circuit shown in Fig. 7, if the product of a resistance value of the emitter resistor and a current value of the constant current source in the rectifier at each stage is set to be larger than that at the preceding stage, namely, set to be as (RE·I0) < (RE'·I0') < (RE''·I0'') <····, and if a current value of the constant current source in the rectifier at each stage is set similarly to the above, namely, set to be as I0 < I0' < I0'' < ····, the output currents I3 and I4 shown in Fig. 7 may be expressed by the following equations; I3 = Ic2 + Ic2' + Ic2'' + ······ I4 = Ic3 + Ic3' + Ic3'' + ······ The output currents I3 and I4 are logarithmic in characteristic and can be approximated by the dotted lines in the negative range and the positive range of the input voltage Vi, respectively (see Fig. 8). Thus, if the output current I7 is defined as; I7 = I3 + I4, the change of I7 becomes as shown in Fig. 8. This shows that the circuit shown in Fig. 7 has a logarithmic full-wave rectification characteristic. Particularly, in the range of being Vi > 4VT this rectification characteristic has the positive range and negative range of Vi symmetrical with respect to each other. In addition, if the resistance values of the emitter resistors (RE, RE', RE'' ...) and the current values of the constant current sources (I0, I0', I0'' ...) are selected appropriately, the I7 can be approximated to the logarithmic full - wave rectification characteristic even when the condition shown by Eq. (14) is not existing. The output currents I5 and I6 shown in Fig. 7 can be expressed by the following equations similar to the case of the output currents I3 and I4 as; I5 = Ic1 + Ic1' + Ic1'' + ···· I6 = Ic4 + Ic4' + Ic4'' + ···· Thus, if the output current I8 is defined as; I8 = I5 + I6 the change of I8 becomes as shown in Fig. 8. The output currents I7 and I8 are inverse in phase to each other, so that the output current I8 also can be approximated to a logarithmic characteristic similar to the case shown above. As a result, the circuit shown in Fig. 7 has a logarithmic full-wave rectification characteristic as shown in Fig. 8. In this case, the n differential amplifiers A1, A2, ····, and An connected in series shown in Fig. 3 have the gains [dB] GV1, GV2, ····, and GVn. respectively, however, if a signal having a large amplitude is inputted, the output is saturated, resulting in effecting a limiting operation. As a result, by using the full-wave rectifier as shown in Fig. 4 as each of the rectifiers B0, B1, ···· and Bn and adding the respective outputs IOUT0 to IOUTn to each other through the adder ADD, the output current IOUT thereof has a logarithmic amplification characteristic as shown in Fig. 9. Namely, the circuit shown in Fig. 3 is a logarithmic amplification circuit. This logarithmic amplification circuit can eliminate a voltage offset, so that an input circuit can be made simple, and yet the dynamic range can be widened by lowering the lower limit thereof. In addition, each of the rectifiers B0, B1, ····, and Bn uses two sets of differential transistor pair, so that a dispersion in characteristic of components can be set off to each other, being possible to effect high accuracy amplification. The logarithmic amplification characteristic of the output current IOUT of the logarithmic amplification circuit of this invention can be improved by appropriately selecting each of the gains GV1, GV2,····, and GVn of respective differential amplifiers A1, A2,····, and An, and the current value of the constant current source I0, the resistance value of the emitter resistor RE and the current amplification factor αF of each of the full-wave rectifiers B0, B1, ···, and Bn. For example, by lowering the gains GV1, GV2, ···, and GVn of respective differential amplifiers A1, A2, ···, and An, the logarithmic characteristic can be improved. On the other hand, however, this disadvantageously results in a decrease in dynamic range of the output. If the gain of each differential amplifier is selected at a level of 20 dB in general, the dynamic range of the full-wave rectifier shown in Fig. 4 is only at a level of about 10 dB as shown in Fig. 6, so that the logarithmic output IOUT becomes irregular, resulting in being inferior in linearity. As a result, by using the logarithmic full - wave rectifier shown in Fig. 7 instead of the full-wave rectifier shown in Fig. 4, the dynamic range can be expanded while improving the logarithmic characteristic. Therefore, even if the number of stages of the differential amplifiers to be used is reduced, a high accuracy logarithmic amplification circuit with a wide dynamic range can be realized.

Claims: A bipolar logarithmic amplification circuit comprising: a differential amplifier (A 1 to A n ) at least two full-wave rectifiers (B o to B n ), each including two half-wave rectifiers (Q 1 , Q 2 ; Q 3 ,Q 4 , respectively) connected so as to have their input signals inverse in phase to each other and wherein the full-wave rectifiers receive an input signal and an output signal of said differential amplifier, respectively; and an adder (ADD) for adding the output signals of said full-wave rectifiers; wherein each of said two half-wave rectifiers includes an unbalanced emitter-coupled differential transistor pair and only one transistor of each of said transistor pair has an emitter resistor (R E ). A circuit as claimed in claim 1, wherein said two sets of differential transistor pair are arranged so that the transistors each having an emitter resistor have their collectors connected with each other, the transistors each not having an emitter resistor have their collectors connected with each other, one of an output signal and an input signal of said differential amplifier is applied to the base of one of the transistors each having an emitter resistor and one of the transistors each not having an emitter resistor, the other of an output signal and an input signal of said differential amplifier is applied to the base of the other of the transistors each having an emitter resistor and the other of the transistors each not having an emitter resistor, and the transistors of each pair are connected to constant current source in a respective manner. A logarithmic amplification circuit comprising: n differential amplifiers (A 1 to A n ), n is an integer of two or more, connected in series to each other; (n+1) full-wave rectifiers (B o to B n ) each including two half-wave rectifiers whose input signals are inverse in phase to each other, wherein a first one of said (n+1) full-wave rectifiers receives an input signal to a first one of said n differential amplifiers and the other full-wave rectifiers receive output signals from said n differential amplifiers in a respective manner; and an adder (ADD) for adding the output signals from said (n+1) full-wave rectifiers; wherein each of said half - wave rectifiers includes an unbalanced emitter-coupled differential transistor pair and only one transistor of each of said transistor pairs has an emitter resistor (R E ). A circuit as claimed in claim 3, wherein said two sets of differential transistor pair are arranged so that the transistors each having an emitter resistor have their collectors connected with each other, the transistors each not having an emitter resistor have their collectors connected with each other, one of an output signal and an input signal of each of said n differential amplifiers is applied to the base of one of the transistors each having an emitter resistor and one of the transistors not having an emitter resistor, the other of an output signal and an input signal of each of said n differential amplifiers is applied to the base of the other of the transistors each having an emitter resistor and the other of the transistors each not having an emitter resistor, and the transistors of each pair are connected to constant current sources in a respective manner. A circuit as claimed in any of claims 1 to 4, wherein said full-wave rectifiers comprise a logarithmic full-wave rectifier. A circuit as claimed in claim 5, wherein said logarithmic full-wave rectifier comprises a plurality of full-wave rectifiers each including two sets of differential transistor pair only one transistor of which has an emitter resistor and constant current sources for supplying electric currents to said two sets of differential transistor pair in a respective manner, wherein said plurality of full-wave rectifiers are different in the product of resistance value of said emitter resistor and a current value of each of said constant current sources from each other and connected in parallel to each other.

Inventors: KIMURA KATSUJI, KIMURA, KATSUJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H03G7
IPC codes: H03G7, G06G7, H03G11