Control system

Abstract: In a control system, for instance forming part of a vehicle anti-lock brake system, a plurality of control processors (4, 5) provides similar or identical control signals (10, 11) of the system. An independent data correlation processor (12) compares data generated in the control processors (4, 5) for correlation and, in the absence of proper correlation, provides an indication (15) which may be used to disable anti-lock operation of the brake system.

Description: The present invention relates to a control system, for instance of the type having plurality of controllers which receive the same or similar input data and produce outputs which, during normal operation of the system, have the same or similar values. Vehicle braking systems must operate with a very high degree of reliability. In the case of anti-lock brake systems, it is essential that the braking force should only be released in response to correct detection of wheel-lock or incipient wheel-lock. In order to prevent incorrect operation of electronic anti-lock control systems from releasing the braking force as a result of faulty operation of the electronics, it has become common for anti-lock braking systems to include a plurality of controllers working in parallel. A safe data processing device having at least two channels with controllers working in parallel, is known e.g. from EP-A-0 026 734. Vehicle anti-lock brake systems are generally controlled by microprocessors or microcomputers so as to control the application of braking force in accordance with measured vehicle wheel speeds. For instance, when the measured speed of a wheel indicates that the wheel is in an incipient lock condition, braking force applied to that wheel is reduced or removed until the wheel recovers or begins to recover from wheel-lock or incipient wheel-lock. In hydraulically actuated brake systems, this is achieved by releasing the hydraulic pressure to the brake actuators. All of the controllers may receive the same input data, for instance from wheel speed sensors, and are intended to supply the same output signals for controlling anti-lock operation. The output signals may be compared with each other and, if they are not sufficiently similar, remedial action may be taken. If a faulty controller is identified and ignored, the anti-lock function can be inhibited to prevent possible loss of vehicle braking. Some form of warning is usually given to indicate to a driver that anti-lock operation is no longer available. The individual controllers may be identical but independent of each other, in which case the controller outputs should be identical (allowing for tolerances, such as small timing differences in digital systems). However, although very unlikely, it is possible that the same fault may arise in identical controllers. Accordingly, in order to provide an even greater degree of security, it is possible for the controllers to be embodied differently so that the simultaneous occurrence of a fault is less likely and, even if it does happen, the faulty outputs from the controllers will differ from each other. In controllers embodied by programmed microprocessors, it is becoming common for the individual microprocessors to be arranged to cross-check the operations of each other, as e.g. known from EP-A-322 141. In the case of systems using a plurality of identical controllers, this can be done by periodically checking that data calculated independently in the different controllers are identical (allowing for possible small differences in timing). Such a technique can be adapted for use with non-identical controllers, since even such non-identical controllers will nevertheless generally calculate some parameters, such as wheel speed, which should be substantially identical during normal operation. It has been found that such cross-checking operation consumes a significant portion of the operational capability of each controller. Thus, in order to ensure that each controller can fulfil its role as an anti-lock controller while performing cross-checking, more powerful (faster and/or larger) microprocessor controllers have to be used. This in turn leads to greater complexity which, in extreme cases, can actually reduce the reliability of the system, together with increased cost. According to the invention, there is provided a control system comprising a plurality of controllers, each of the controllers comprising a control data processor and a memory for receiving parameter data from the control data processor, and arbitration means for arbitrating between the controllers, the arbitration means comprising a data processor arranged to compare data from the controllers for correlation and to provide an indication when lack of correlation is detected, characterised in that the memory of each of the controllers has a write only part arranged to receive the parameter data automatically from the control data processor of the respective controller and a read only part arranged to contain a copy of the parameter data written in the write only part and arranged to be read only by the data processor. The controllers may be arranged to perform an automotive control function, such as anti-lock brake control for a vehicle. By removing the cross-checking or scrutinzing of data from the controllers and delegating it to a separate data processor, the controllers can concentrate, for instance, on anti-lock control. The controllers are thus not slowed down by having to perform cross-checking and need only be powerful e.g. fast, enough to perform anti-lock control. A relatively less powerful data processor may be used for the correlation checking operation while allowing more thorough comparison of data to be performed. For instance, a larger number of parameters of the controllers can be checked for correlation. In the case of controllers embodied as data processors e.g. microprocessors, the data processor is preferably arranged to check the data in the memories for correlation. The memories may be embodied independently or may form parts (defined in hardware and/or software) of a data processor memory. The memories may form part of the controllers. Each memory may comprise a write only part, arranged to receive data automatically from the corresponding controller, and a read only part arranged to contain a copy of the data written in the write only part and to be read only by the data processor. The write only and read only parts may be defined by hardware and/or software. It is thus possible to ensure that the data correlation is entirely independent of the controllers and cannot be affected by any faulty operation occurring in the controllers. It is also possible to provide a method of arbitrating between a plurality of controllers, comprising comparing in a data processor data from the controllers for correlation and providing an indication when lack of correlation is detected. The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagram of part of an anti-block brake system including an apparatus constituting a preferred embodiment of the invention; Figure 2 is a block diagram of the apparatus shown in Figure 1; and Figures 3 and 4 are flow diagrams illustrating operation of the apparatus shown in Figure 2. An anti-lock braking system for use in a road vehicle comprises four wheel speed sensors 1a to 1d which cooperate with road wheels 2a to 2d of the vehicle to provide signals representing wheel speed. For instance, each sensor may be a variable reluctance transducer cooperating with teeth which rotate with the corresponding wheel so that the sensor produces an oscillating waveform whose frequency is proportional to wheel speed. Each of the sensors 1a to 1d is connected to an interface circuit 3a to 3d for interfacing between the sensors and first and second control processors 4 and 5. Such interfaces condition the waveform from the sensors to produce outputs which are compatible with digital signal levels used by the processors 4 and 5. The outputs of the interfaces 3a to 3d are each connected to both of the control processors 4 and 5. The control processors 4 and 5 are preferably each embodied as a microcomputer or microprocessor for controlling anti-lock brake operation. The processors have other inputs shown at 6 and 7 for receiving inputs from other transducers which monitor the performance of the vehicle. The processors have monitoring inputs 8 and 9 for receiving input signals indicating the performance of actuators or the like forming part of the vehicle brake system. The processors 4 and 5 have outputs 10 and 11 which supply output demands for driving actuators, such as a debooster or modulator for releasing brake pressure in an hydraulically actuated vehicle brake system. The system further includes a data correlation processor 12 connected via buses 13 and 14 to the first and second control processors 4 and 5, respectively. The data correlation processor 12 has an output 15 which supplies failsafe drive signals, for instance for disabling the anti-lock system so as to prevent brake release resulting from faulty operation. Figure 2 is a block diagram illustrating schematically the data correlation processor 12 and n control processors (only two such processors are used in the system of Figure 1). The control processors 20 1 to 20 n have respective data memories 21 1 to 21 n in which are stored data resulting from operation of the respective processor. Such data may comprise calculated wheel speeds, calculated wheel decelerations, calculated output demands, measured vehicle parameters (such as vehicle speed, deceleration, yaw, loading, and brake lamp status), and road surface condition. The data correlation processor 12 is connected to the memories 21 1 to 21 n by respective buses 22 1 to 22 n which provide read-only access to the data memories 21 1 to 21 n , respectively. Further details of operation of the control processors shown in Figures 1 and 2 will not be given as it is of no relevance to the present invention. Operation of the data correlation processor 12 is illustrated in Figures 3 and 4 in the form of flow charts. Figure 3 shows a data correlation routine 30 which is periodically performed by the data correlation processor. At 31 and 32, the processor enters a loop until the data which it requires are available for reading in the data memories of all of the control processors. When the data are available, they are read at 33 and a data arbitration is performed at 34. Step 35 determines whether the result of the data arbitration is acceptable or not. If so, step 36 enables the anti-lock system and control is returned to step 31. If not, then the anti-lock system is disabled at 38 and an indication of system failure is provided at 39 so as to warn a vehicle driver that the brake system is functioning without the facility of anti-lock operation. An example data arbitration 34 and checking 35 is shown in more detail in Figure 4. In particular, Figure 4 illustrates arbitration in respect of wheel speed, but such arbitration may comprise several similar routines performed in sequence in respect of the various parameters for which arbitration is performed. At 40, the wheel speed in respect of the first control processor is read. The wheel speeds in respect of the second to nth processors are read at 41 and 42 and, at 43, the spread of wheel speeds is calculated, for instance as the difference between the maximum and minimum values of wheel speeds produced by the control processors. At 44, the spread is compared with an acceptable limit to determine whether it is within that limit. If so, then the step 36 is performed; if not, then the step 38 is performed. For the step 44, the acceptable limit of spread may depend on wheel or vehicle speed. For instance, the acceptable limit may be one kilometre per hour for speeds between 0 and 100 kilometres per hour, 2 kilometres per hour for speeds between 100 and 200 kilometres per hour, 3 kilometres per hour for speeds between 200 and 300 kilometres per hour, and 4 kilometres per hour for speeds above 300 kilometres per hour. In the embodiment shown in the drawings, the data correlation processor 12 has read-only access to the memories 21 1 -21 n of the control processors 20 1 -20 n . If inadequate correlation among the control processors 20 1 -20 n is detected, the data correlation processor cannot intervene in operation of the control processors 20 1 -20 n but can merely give a warning of a fault and, via its output 15, disable antilock operation of the brakes so as to prevent failure of the brake system or incorrect operation of the antilock system. In a simplified arrangement, only a warning could be given so that the data correlation processor 12 could not influence or affect the operation of the braking system. Various modifications may be made within the scope of the invention as defined in the appended claims. For instance, in a system where, at any particular time, a flag is set to indicate which of the control processors 20 1 -20 n is in command of antilock operation, the data correlation processor 12 may be arranged to have write access to setting of the flags, for instance in the memories 21 1 -21 n of the control processors. When the data correlation processor 12 detects a discrepancy among the control processors, it is arranged to control setting of the flags so as to determine which of the control processors assumes command. For instance, if all of the control processors except one agree, the data correlation processor can ensure that the one processor is not selected for command of the antilock system. Data correlation and arbitration can therefore be performed without impinging on operation of the control processors. The speeds and/or sizes of the control processors do not therefore need to be increased in order to perform correlation. The data correlation processor can be embodied as a relatively simple processor, such as a microcomputer or microprocessor. Thus, the capabilities of the system can be augmented while ensuring that effective arbitration is provided so as to improve the reliability of operation of the system.

Claims: A control system comprising a plurality of controllers (4, 5, 20 1 -20 n ), each of the controllers (4, 5, 20 1 -20 n ) comprising a control data processor and a memory (21 1 -21 n ) for receiving parameter data from the control data processor, and arbitration means for arbitrating between the controllers (4, 5, 20 1 -20 n ), the arbitration means comprising a data processor (12) arranged to compare data from the controllers (4, 5, 20 1 -20 n ) for correlation and to provide an indication when lack of correlation is detected, characterised in that the memory (21 1 -21 n ) of each of the controllers (20 1 -20 n ) has a write only part arranged to receive the parameter data automatically from the control data processor of the respective controller (20 1 -20 n ) and a read only part arranged to contain a copy of the parameter data written in the write only part and arranged to be read only by the data processor. A control system as claimed in Claim 1, characterised in that the controllers (4, 5, 20-20 n ) are arranged to perform an automotive control function. A control system as claimed in Claim 2, characterised in that the controllers (4, 5, 20 1 -20 n ) are arranged to perform anti-lock brake control for a vehicle. A control system as claimed in any one of the preceding claims, characterised in that the data processor (12) is arranged to receive the parameter data from the memories (21 1 -21 n ) and to check the parameter data for correlation.

Inventors: AINSWORTH ANTHONY JOHN, BOLTON JOHN ANTHONY, PHILLIPS MARK IAN, AINSWORTH, ANTHONY JOHN, BOLTON, JOHN ANTHONY, PHILLIPS, MARK IAN
Applicants: LUCAS IND PLC, LUCAS INDUSTRIES PUBLIC LIMITED COMPANY
Application year: 1992
Main classification: G06F11
IPC codes: G06F11, G05B9, B60T8, G05B7, B60W50