Control circuit for dual port memory

Abstract: A control circuit for use with a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the ports. Such port snoops the main memory bus, and a cache tag hit for such port during a write operation to the main memory bus indicates that the snoop valid bit should be reset. In order to avoid errors in resetting the snoop valid bit which can occur due to signal propagation delay, the control circuit resets the snoop valid bit only after a preselected internal delay period.

Description: The present application contains subject matter in common with European Patent Application EP-A-0 439 952 filed 21 December 1990. This application is also related to European Patent Application No EP-A-0 514 049 (based on US Serial No 693670) filed contemporaneously with this application. The present invention relates generally to integrated circuit memory devices, and more specifically to a circuit and method for preventing incorrect writing of data in a dual port cache tag memory which utilizes a snoop valid bit. One type of memory used in computer systems is a cache memory. This is a relatively small, fast memory which resides in the system between the central processor and main system memory. Cache memories include data memory fields for storing data cached from system memory, and tag memory fields for storing the addresses corresponding to the data stored in the data cache. Patent Abstracts of Japan vol 12, No 480 (P-801) 15 December 1988 & JP-A-63 195 752 discloses a two port cache memory having an address tag memory area and a valid memory area. A B-port address tag comparator is provided in addition to an A-port address tag comparator so that the tag address registered into the tag memory area is monitored. Thus the addresses can be read out of both areas and sent to both comparators independently from each other. The A-port comparator compares the tag address designated by a processor with the tag address read out of the tag memory area. While the B-port comparator compares the tag address which is referred to by another cache memory with the tag address read out of the tag memory area. A valid memory clearing circuit invalidates the contents of the tag address. Patent Abstracts of Japan, vol 14, no 585 (P-1148), 27 December 1990 and JP-A-25,2041 discloses a delay circuit in which a delay signal arrives at a memory in accordance with the timing of a synchronising control circuit. EP-A-0404128 on which the precharacterising portion of claim 1 is based discloses a multi-processor system having two processors connected to a shared memory via a shared bus where each processor has an inside and an outside cache connected in series between the processor and the bus. Each inside cache has a memory array where each row comprises an upper address and a valid flag and each row is selected by a lower address. When data is updated in the shared memory the address on the bus is used to invalidate the inside caches. The inside cache selects a row of the memory array using the lower address on the shared bus. The resulting read upper address is compared with the upper address on the shared bus, and if they are the same and the valid bit is valid, then the valid bit is rewritten as invalid. The Art of Digital Design: An Introduction to Top-Down Design (1980) pages 172-174, by Winkel/Prosser, teaches that having a flip-flop state dependent upon the exact timing of the flip-flop input changes is intolerable and should be avoided by synchronising inputs using a D flip-flop clocked by the system clock. Some cache tag memory devices, such as that described in the application entitled DUAL-PORT CACHE TAG MEMORY, cited above, have two ports which can access a memory array asynchronously. In devices designed specifically for use as cache tag memories, one of the data ports can write data to a single bit of an entry in the array. This bit is known in the art as a "snoop valid bit", and is used to indicate that the contents of a local processor cache memory have been invalidated by processing occurring elsewhere in the computer system. When another processor or other device in the system writes data to a memory location stored in a local processor cache, that entry is no longer current. The entry is therefore marked invalid by resetting the snoop valid bit for that entry to zero. In designs such as used by the above-cited application, the snoop valid bit for an entry can be reset to 0 only by the port which snoops the main memory bus, and once reset cannot be set to a value of 1 again until that entry is later reloaded with a new value. Thus, invalidation of an entry is an irreversible act. If invalidation occurs incorrectly, valid cache entries will be marked as invalid, causing a cache miss the next time such entries are referenced. When cache tag memory chips are connected to provide wider entries as described in the cited application, a signal indicating a match must be communicated between the chips. If this signal is delayed in reaching the snoop bit invalidation circuitry due to parasitic capacitances, the snoop valid bit could be erroneously reset to 0. It would therefore be desirable to provide a control circuit for dual port cache tag memories which ensures that a snoop valid bit is not erroneously reset to 0. It would be further desirable for such a control circuit to be simple to construct, and not add complexity to a memory cycle for the memory. It is therefore an object of the present invention to provide a circuit for resetting a snoop valid bit in a cache tag memory when a cache hit occurs on the device's snoop port. It is another object of the present invention to provide such a circuit which is simple in design and does not require complex cycle timing. It is a further object of the present invention to provide such a circuit which does not add externally seen complexity to the memory cycle for the device, and which does not increase the cycle time when two or more memory devices are used together. Therefore, a control circuit for use with a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the ports. Such port snoops the main memory bus, and a cache tag hit for such port during a write operation to the main memory bus indicates that the snoop valid bit should be reset. In order to avoid errors in resetting the snoop valid bit which can occur due to signal propagation delay, the control circuit resets the snoop valid bit only after a preselected internal delay period. According to the present invention there is provided a control circuit for a dual port memory having a plurality of memory entries, each entry including a snoop valid bit (20), the control circuit comprising: comparator means (31) for detecting a match between one of said memory entries and an address on a system bus, and generating a match signal (32) when a match is detected; and characterised by further comprising: a buffer (60) for writing a first preselected value to the snoop valid bit (20) of said one of said memory entries, the buffer (60) having a control input connected to an enable circuit (52) constructed for enabling the buffer to write to the snoop valid bit (20) of said one of said memory entries; said enable circuit (52) being connected to receive through a delay circuit a control signal for inhibiting receipt of the match signal at the control input (62) of the buffer (60); and wherein the control signal indicates that a write operation is taking place on the system bus and is delayed by the delay circuit (64) for a period of time at least as great as an expected worst case delay of all signals affecting the generation of the match signal (32) by the comparator means (31) so that the buffer (60) is enabled only during a system bus write cycle in which a match signal (32) is generated. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figure 1 is a block diagram of a cache tag memory which can utilize a control circuit according to the present invention; and Figure 2 is a block diagram illustrating a preferred snoop valid bit control circuit for use with the cache tag memory of Figure 1 . Figure 1 is a block diagram of a cache tag memory for use in which the parity checking scheme of the present invention is suitable. The device 10 of the preferred embodiment is a dual port cache tag memory suitable for use in a computer caching system. This device contains a bit, referred to as a snoop valid bit, for each entry in the memory. The snoop valid bit is reset to indicate that an entry is no longer valid whenever another device in the system, other than a local processor, writes data to a memory location which is stored in the cache. Additional details of such a cache tag memory, and its use in a multiprocessor computer system are described in co-pending European Patent Application No EP-A-0 439 952 and entitled DUAL - PORT CACHE TAG MEMORY . The device 10 includes a memory array 12 . In the preferred embodiment, the memory array 12 is 12 bits wide, but it will be appreciated by those skilled in the art that various sized arrays 12 may be used in accordance with the principles of the present invention. In the preferred embodiment, 9 bits of tag data 14 are stored for each entry in the array. Each entry in the array 12 also includes a valid bit 16 , a parity bit 18 , and a snoop valid bit 20 . The valid bit 16 is used by the system to reset the entire memory array 14 . Whenever an entry has a value of 0 in the valid bit field 16 , that entry is considered to be invalid. According to principles known in the art, clearing of the entire memory array 12 is accomplished by simultaneously resetting all of the valid bits 16 for all entries in the array, thereby invalidating all cache entries in a single cycle. This operation is often referred to as a "flash clear". None of the memory locations in the tag data field 14 are reset when the memory is cleared. In the illustration of Figure 1 , the memory array 12 is a dual-port memory. This means that it may be accessed simultaneously and asynchronously by two different ports. Port A is connected to a local processor and is addressed by the local processor to determine whether a memory location to be accessed is contained within the cache memory. Port B is connected to a system bus and is used by the device 10 to "snoop" data being written on the system bus. To determine whether an address being accessed by the local processor is contained within the data cache, the least significant bits of the local address are applied to Port A to address an entry of the memory array 12 , as known in the art. The number of least significant address bits which are used to index into the array 12 is determined by the number of entries in the array 12 . When an entry is addressed by the Port A least significant address bits, the tag data field 14 contains the most significant bits of the address location stored at the corresponding location in the data cache (not shown). These most significant bits are read out of the memory array 12 on signal lines 22 , and compared in comparator 24 to the most significant bits of the Port A address. If the most significant bits of the Port A address match the data on signal lines 22 , then the data of the memory location being addressed on Port A currently resides in the data cache corresponding to the device 10 . The indication of whether or not such a match exists is generated on signal line 26 . If either the valid bit 16 or the snoop valid bit 20 have a value of 0, the entry is invalid. The same process works for addresses connected to the device 10 through Port B, which are coming from the system bus. The least significant bits of the Port B address are applied to the memory array 12 , and the corresponding tag data field 14 is read out on signal line 28 . As is the case with signal lines 22 , signal line 28 represents a number of individual lines equal to the number of bits in the tag data field 14 , plus the valid bit, parity bit, and snoop valid bit. The value on signal line 28 is compared to the most significant bits of the Port B address in a comparator 30 , and a signal indicative of whether or not a match is found is generated on signal line 32 . As before, no match is signalled if either of the valid or snoop valid bits have a value of 0, regardless of the contents of the tag data field 14 . In the case of Port B, if a match is found in comparator 30 , the snoop valid bit 20 corresponding to the tag memory entry which is addressed by the least significant of the Port B address is reset to a value of 0. The snoop valid bit 20 is reset only if such a match occurs during a system memory bus write cycle. Whenever a new value is stored into the memory array 12 from Port A corresponding to loading a new memory location into the cache memory, parity generator 34 generates the appropriate parity bit corresponding to the remaining bits. Whenever an entry is written into the memory 12 the snoop valid bit 20 for that entry is always set to a value of 1. The valid bit 16 is generally set to a 1 by the user when writing a new entry into the array 12 , unless some special condition warrants otherwise. New entries can be written into the memory array 12 only through Port A, which is the port connected to the local process. When a comparison is being made through Port A, a parity detect circuit 36 reads all of the bits of the entry, including the valid bit 16 , parity bit 18 , and snoop bit 20 , and generates a signal on line 38 indicating whether parity is valid for that entry. If a parity error occurs, various recovery techniques can be performed by the system. Since data can be written into the memory array 12 only through Port A, no parity generation circuitry is required for Port B. However, a parity detect circuit 40 is required to check the parity for entries which are addressed through Port B. A signal is then put on line 42 to indicate whether parity is valid for an entry addressed through Port B. Port B is used to "snoop" main memory locations being accessed on the system bus. Each time a memory location is accessed on the system bus, the corresponding entry is read from memory array 12 and compared to the most significant bits of the system bus address. If a match is found, then a memory location being accessed over the system bus is already stored in the local processor cache. If a read operation is being performed on the system bus (Port B), no conflicts arise and nothing is done within the cache tag memory. However, if data is being written to the matching main memory location on the system bus, then the data stored in the cache memory is no longer valid. In this instance the snoop valid bit for the entry selected through Port B is reset to the value of 0. This 0 value indicates that the entry is invalid, and such entry will generate a cache miss when later accessed through either Port A or Port B. This resetting of the snoop valid bit is the only situation in which Port B can write data to the memory array 12 . Figure 2 illustrates a preferred control circuit for resetting the snoop valid bit through port B. Comparator 31 compares the tag data 14 for an entry addressed on port B with the most significant bits of the port B address. The valid bit 16 for the entry is checked in the comparator 31 to ensure that it has a value of 1. A logical 1 is generated by the comparator 31 if the entry in the array matches, indicating that an entry stored in the cache is being accessed over the system bus. The output of comparator 31 is connected to AND gate 50 . The snoop valid bit 20 for the entry addressed on port B is also connected to AND gate 50 . The output of AND gate 50 provides the MATCH B signal on line 32 described above. The MATCH B signal is connected to an input of AND gate 52 . The other input of the AND gate 52 is connected to the output of a delay circuit 64 . Delay circuit 64 provides a preselected delay period for a control signal provided on signal line 66 , and may include a simple inverter delay chain as known in the art. This control signal is preferably derived from the system write signal. When a system bus write cycle completes, the signal on line 66 goes from a logical 0 to 1 for a short period, then returns to 0. During a system bus read cycle, the signal on line 66 remains low. A gated buffer 60 has a control input 62 connected to the output of AND gate 52 . Gated buffer 60 is enabled when its control input 62 has a value of 1, and is disabled otherwise. When buffer 60 is enabled, it writes a logical 0 into the snoop valid bit 20 for the currently addressed entry over signal line 68 . When disabled, buffer 60 has no effect on the value of the snoop valid bit 20 . In operation, the circuitry shown in Figure 2 has no effect on the snoop valid bit 20 for the currently addressed entry during a system read cycle. During a system write cycle, the gated buffer 60 will be disabled when a cache miss occurs. Such a miss can occur because the address stored in the tag ram data field 14 does not match, or because the snoop valid bit 20 for the addressed entry was previously marked invalid. Therefore, the buffer 60 will be enabled only during a system bus write cycle in which a cache hit is generated. The buffer 60 will be enabled at the end of the system bus memory cycle as controlled by the delay generated by circuit 64 . For fast devices, only a few nanoseconds of delay may be required. The minimum required delay is at least as great as the expected worst case delays of all signals which can affect the generation of the match signal. If several separate chips are expected to be connected so as to determine the logical state of the match signal, off-chip propagation delays must be considered. In the preferred embodiment, the memory array 12 is an SRAM memory array. Such memories are fast, and do not need to be refreshed. As known in the art, SRAM memories generally require both a true and complement of a signal to be written into the array. Therefore, using known principles, the gated buffer 60 actually generates two complementary signals to write values into the array. While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein within the scope of the appended claims.

Claims: A control circuit for a dual port memory having a plurality of memory entries, each entry including a snoop valid bit (20), the control circuit comprising: comparator means (31) for detecting a match between one of said memory entries and an address on a system bus, and generating a match signal (32) when a match is detected; and characterised by further comprising: a buffer (60) for writing a first preselected value to the snoop valid bit (20) of said one of said memory entries, the buffer (60) having a control input connected to an enable circuit (52) constructed for enabling the buffer to write to the snoop valid bit (20) of said one of said memory entries; said enable circuit (52) being connected to receive through a delay circuit a control signal for inhibiting receipt of the match signal at the control input (62) of the buffer (60); and wherein the control signal indicates that a write operation is taking place on the system bus and is delayed by the delay circuit (64) for a period of time at least as great as an expected worst case delay of all signals affecting the generation of the match signal (32) by the comparator means (31) so that the buffer (60) is enabled only during a system bus write cycle in which a match signal (32) is generated. The control circuit of claim 1, wherein the enable circuit comprises: an AND gate (52) having an output connected to the control input (62) of the buffer (60), a first input for receiving the match signal (32), and a second input. The control circuit of claim 1 or 2 wherein the delay circuit (64) comprises an input for receiving the control signal (66) and an output connected to the second input of the AND gate (52). The control circuit of claim 3, wherein the delay circuit (64) comprises a plurality of inverters connected to form an inverter delay chain.

Inventors: RASTEGAR BAHADOR, RASTEGAR, BAHADOR
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1992
Main classification: G06F12
IPC codes: G06F12, G11C8