Input-weighted transversal filter

Abstract: An input-weighted transversal filter having a first input circuit for inputing a sampled input signal which is sampled at every predetermined period, registers for storing predetermined number of tap weights, the register selectively supplying the tap weights in a predetermined order, a plurality of tap weight multipliers for multiplying the sampled input signal and a tap weight supplied form the registers, a pipeline processing adder for adding the multiplied outputs from the tap weight multipliers with each other and a second input circuit for inputing signals to the pipeline processing adder, the second input circuit having at least one input coupled to the output of the pipeline processing adder.

Description: The present invention relates to a transversal filter, and more particularly to an input-weighted transversal filter which performs a realtime filtering operation for input signals. A filter which digitally processes input signals in realtime operation has been discussed in, for instance, "PERFORMANCE EVALUATIONS OF SELECTED AUTOMATIC DEGHOSTING SYSTEMS FOR TELEVISION" in "IEEE Transactions on Consumer Electronics, Vol. CE-26, February 1980". FIGURE 1 shows a conventional six taps input-weighted transversal filter (hereinafter referred to generally as a transversal filter). This transversal filter shows a part of a large-scale transversal filter provided with many taps. An input signal a = {x(i)}, sampled at every period T, is input to six tap weight multipliers 10, 11, 12, 13, 14, 15 via an input terminal 1. The tap weight multipliers 10, 11, 12, 13, 14, 15 multiply the input signal a by their associated tap weights C0, C1, C2, C3, C4, C5 and output their multiplication results to adders 20, 21, 22, 23, 24, 25, respectively. Further, a cascade input signal e = {z(i)} is input to the adder 25 through a cascade input terminal 3. The adders 20, 21, 22, 23, 24, 25 have been connected in series so that they are positioned alternately with delay elements 30, 31, 32, 33, 34 and the output from the adder 20 is led to an output terminal 2 through a last stage delay element 4. The delay elements 30, 31, 32, 33, 34, 4 are driven by a clock signal CK. An output signal {y(i)} of the last stage delay element 4 of the transversal filter is expressed by the following equation: This output signal {y(i)} will become the final output signal of the transversal filter. The cascade input terminal 3 is provided for coupling these transversal filters in series. Thus, when the transversal filter is used in a single piece, such a cascade input terminal is omitted from the circuit arrangement. The arithmetic operation shown by the equation (1) has been used in many fields. In particular, in the fields of television deghosting technique and a digital processing technique of television signals, it is used at T = 70 to 93 ns (10 -9 sec.) and to execute the equation (1) at high speed in a realtime operation, ROMs (Read Only Memories) and RAMs (Random Access Memories) have been used for the tap weight multipliers 10, 11, 12, 13, 14, 15 in addition to random logic multipliers. Now, when considering the fabrication of the transversal filter onto an integrated circuit (IC) chip, the circuit-scale of these tap weight multiplier becomes relatively large and the number of taps that can be embodied on one chip is no more than 64 taps. Normally, in deghosting devices transversal filters are used at 14.32 MHz, which is four times the color subcarrier frequency fsc at the NTSC system. Thus, the period is calculated as T = 70 ns. At this time, a 64 taps transversal filter will become 4.4 µs wide. It is generally said that the 90% of ghosts are generated in a range of delay time from -1 to 24 µs. To realize a practical deghosting device that copes with ghosts in this range, transversal filters having more than 357 taps are required. In other words, more than six identical IC chips become necessary and it becomes expensive because many component parts are required and the necessary chip-scale becomes large. As described above, conventional transversal filters enabling realtime operation at high speed have problems in that the circuit size of the tap weight multiplier becomes large and sufficient number of taps cannot be obtained even when the filter is made in IC chips. The present invention therefore seeks to provide an input-weighted transversal filter in which is capable of realizing, with a small number of taps, a transversal filter equivalent to a filter having a large number of taps. A transversal filter as set out in the preamble of claim 1 is discussed in Patent Abstracts of Japan Vol 14, No. 036(E-877) 23 January 1990 (8JP-A-1 268 305). According to the present invention there is provided an input-weighted transversal filter for filtering a sampled input signal with a sampling period comprising: register means holding a plurality of tap coefficients; a plurality of multiplier means for multiplying said tap coefficients with the sampled input signal; a pipeline processor including a plurality of adding means separated by at least one delay element from one another, the pipeline processor adding the multiplied outputs from the multiplier means; wherein during one sampling period of the input signal each multiplier means consecutively multiplies the input signal by more than one tap coefficient supplied to the multiplier by the register means in a specific order; characterised in that during a part of each sampling period of the input signal an output signal from the pipeline processor is selected by selection means as an input to the pipeline processor. The tap weight multipliers of the present invention operate on the basis of time-division multiplexing and multiply input signals sampled at every period T by a tap weight by changing it over n (n is a natural number not less than 2) times during the period T. These outputs from the tap weight multipliers are added up by the pipeline processing adder and the output from this pipeline processing adder is output as a filtered output signal sampled at every period T described above. At the same time, part of the output from this pipeline processing adder is input to the input selecting means provided at the input of the pipeline processing adder itself. This input selecting means is so constructed that it changes over the output from the pipeline processing adder or another adding input at least twice during the period T. Further, the pipeline processing adder is equipped with a plurality of adders to which outputs from a plurality of tap weight multipliers described above are input and delay means consisting of n delay elements each of which has a delay time (T/n) connected in series between the plurality of adders. As the tap weight multipliers are used on the basis of time-division multiplexing during the period T, a plurality of tap weight multiplication results can be obtained from the delay elements of the pipeline processing adder during the period T. A part of the multiplication results which has an insufficient delay time is again applied to the input of the pipeline processing adder and passes through the delay element line again and thus, a properly filtered output signal with sufficient delay time can be obtained. As described above, a tap weight multiplier has the function of a plurality of conventional tap weight multipliers and a required number of the tap weight multipliers can be reduced. Further, if a large number of the tap weight multipliers are used, it becomes possible to increase the number of taps exceptionally. For a better understanding of the present invention and many of the attendant advantages thereof, reference will now be made by way of example to the accompanying drawings, wherein: FIGURE 1 is a circuit diagram showing a conventional input-weighted transversal filter; FIGURE 2 is a circuit diagram showing a first embodiment of the input-weighted transversal filter according to the present invention; FIGURE 3 is a timing chart for explaining the operation of the circuit shown in FIGURE 2; FIGURE 4 is a modification of the circuit diagram of FIGURE 2 for explaining the operation of the first embodiment; FIGURE 5 is a timing chart for explaining the operation of the circuit shown in FIGURE 4; FIGURE 6 is a circuit diagram showing a second embodiment of the input-weighted transversal filter according to the present invention; FIGURE 7 is a timing chart for explaining the operation of the circuit shown in FIGURE 6; FIGURE 8 is a circuit diagram showing a third embodiment of the input-weighted transversal filter according to the present invention; and FIGURE 9 is a timing chart for explaining the operation of the circuit shown in FIGURE 8. The present invention will be described in detail with reference to the FIGURE 2 through FIGURE 9. Throughout the drawings, reference numerals or letters used in FIGURE 1 will be used to designate like or equivalent elements for simplicity of explanation. Referring now to FIGURES 2 to 4, a first embodiment of the input-weighted transversal filter according to the present invention will be described in detail. FIGURE 2 shows a first embodiment of an input-weighted transversal filter according to the present invention. The first embodiment is illustrated such that the scale of 6 taps, similar to the conventional transversal filter as shown in FIGURE 1, is realized by two times time-division multiplexing. An input signal a = {x(i)}, sampled at every period T, is input to the input terminal 101. This input signal a is input to the tap weight multipliers 110, 111, 112. The tap weight multipliers 110, 111, 112 are provided with tap weights from registers 190, 191, 192, respectively. These tap weights are changed between two values in the respective tap weight multipliers during the period T. Tap weights C0, C3 are selected in the register 190, the tap weights C1, C4 in the register 191, and the tap weights C2, C5 in the register 192. The registers 190, 191, 192 select the tap weights with smaller suffixes (C0, C1, C2) when the selecting signal S is "1" and the tap weights with larger suffixes (C3, C4, C5) when the signal S is "0". The outputs of the tap weight multipliers 110, 111, 112 are input to the adders 120, 121, 122, respectively. Between the adders 120, 121 the delay elements 130, 131 each having the delay time (T/2 = T/n) are connected in series. Also, between the adders 121, 122 the delay elements 132, 133 each having the delay time (T/2 = T/n)-are connected in series. The delay circuit from the adder 120 to the adder 122 forms the pipeline processing adder 170. The output of this pipeline processing adder 170 is input to the delay element 150 having the delay time (T/2 = T/n). The output of the delay element 150 is input to the last stage delay element 104 having the delay time T. The output of this last stage delay element 104 is connected to the output terminal 102. Further, the output of the pipeline processing adder 170 is input to the delay element 160 having the delay time (T/2 = T/n). The cascade input signal e = {z(i)}, sampled at every period T, is input to the cascade input terminal 103. This sampling series signal e is input to the selector 180. The sampled signal e and the output of the delay element 160 are supplied to the selector 180 where these two kinds of signals are selected during the period T. The selector 180 selects the output of the delay element 160 when the selecting signal S is "1", while the sampled signal e is selected when the selecting signal S is "0". The output from the selector 180 is connected to the adder 122 in the pipeline processing adder 170. FIGURE 3 is a timing chart for explaining the operation of the first embodiment of the transversal filter. Before explaining the time chart of FIGURE 3, the basic operation of the first embodiment will be explained with reference to FIGURES 4, 5. FIGURE 4 is a modified circuit diagram of FIGURE 2 for explaining in detail the first embodiment of the present invention shown in FIGURE 2. FIGURE 4 is entirely the same as FIGURE 2 except that a connection between the output of the delay circuit 160 and the input of the selector 180, which presents in FIGURE 2, is omitted. Then, the delay element 160 has a virtual output terminal 105, while the selector 180 has a virtual input terminal 106 for receiving a virtual input signal k = {α(i)}. The small input signal k is provided to be input to the selector 180 only when the selecting signal S of the selector 180 is "1". Since the operations of the components, signals and assigned symbols are all the same as those shown in FIGURE 2, the explanations of the components etc., will be omitted hereinafter. FIGURE 5 is a timing chart for explaining the operation in FIGURE 4. As shown in FIGURE 5, the selecting signal S and the clock signal CK1 used in the last stage delay element 104 have the period T and the clock pulse CK2 has the period (T/2 = T/n). In the present invention, it is assumed that a period of CK1 is equally divided into n sections by the second clock signal CKn having n times (n is an integer not less than 2) the frequency of the clock signal CK1, and the n sections are called Phase 1, Phase 2, ... Phase n in regular order of time. FIGURES 2, 4 show a particular case having two sections, Phase 1 and Phase 2. As the input signal a is sampled at the period T, the data of the input signal a changes in the following order at the period T of the clock signal CK1 and signal S x(i-2), x(i-1), x(i), x(i + 1),.... As the tap weights being selected by the period (T/2), the outputs d, c, b of the tap weight multipliers 110, 111, 112 change in following orders. In case of the output d of the tap weight multiplier 110; C0·x(i-2), C3·x(i-2), C0·x(i-1), C3·x(i-1), C0·x(i), C3·x(i), C0·x(i+1), C3·x(i+1), .... In case of the output c of the tap weight multiplier 111: C1·x(i-2), C4·x(i-2), C1·x(i-1), C4·x(i-1), C1·x(i), C4·x(i), C1·x(i+1), C4·x(i+1), .... In case of the output b of the tap weight multiplier 112: C2·x(i-2), C5·x(i-2), C2·x(i-1), C5·x(i-1), C2·x(i), C5·x(i), C2·x(i+1), C5·x(i+1), .... Further, as the cascade input signal e is being sampled at the period T, the data content of the signal e changes in the following order, at the period of the clock signal CK1 and signal S. z(i-2), z(i-1), z(i), z(i+1), .... As to the virtual input signal k, as the signal {α(i)} sampled at every period T being input when the selecting signal S is "1", the data content of the virtual input signal k changes in the following order, at the periods of the "1" and "0" of the selecting the clock signal CK1 and signal S. α(i-2), *, α(i-1), *, α(i), *, α(i+1), *, .... where the contents of the data * are not cared. As the selector 180 is being operated at the period (T/2), the output f of the adder 122 changes in the following order. C2·x(i-2) + α(i-2), C5·x(i-2) + z(i-2), C2·x(i-1) + α(i-1), C5·x(i-1) + z(i-1), C2·x(i) + α(i), C5·x(i) + z(i), C2·x(i+1) + α(i+1), C5·x(i+1) + z(i+1), .... When adding the outputs d, c, b of the tap weight multipliers 110, 111, 112 in the pipeline processing adder 170, if the time difference between the outputs d, c, b of the tap weight multipliers 110, 111, 112 is set by n (2 in this embodiment) Periods of the delay elements for the number (n) of tap weights which are selected in each of the tap weight multipliers, a first output sum ΣS of the outputs is obtained in Phase 1 with the tap weights with smaller suffixes and alternately the output sum ΣL of the outputs is obtained with the tap weights with larger suffixes. For instance, when taking the period (i-1)T as example, in Phase 1 of the period (i -1 )T, the first output sum ΣS as follows appears as the output g of the adder 120; ΣS = C0·x(i-1) + C1·x(i-2) + C2·x(i-3) + α(i-3) In Phase 2 the second output sum ΣL as follows appears as the output g of the adder 120; ΣL = C3·x(i-1) + C4·x(i-2) + C5·x(i-3) + z(i-3) If the first output sum ΣS is delayed by (T/2) by the delay element 150 of the period (T/2) and further, it is held in the last stage delay element 104 for the period T, the second output sum ΣL is ignored and the final output h appears at the output terminal 102 as shown in FIGURE 5 the following signal is obtained as the output signal {y'(i)}: y'(i) = C0·x(i-1) + C1·x(i-2) + C2·x(i-3) + α(i-3) In the output g of the adder 120, if the second output sum ΣL is advanced by (T/2), it becomes the same phase as the first output sum ΣS. So, if the second output sum ΣL is added to the first output sum ΣS by delaying 2.5T and' further, the virtual input signal k (= {α(i)}) is made 0, the equation (2) will become the same form as the equation (1), as shown in the following equation: If the output g is established in the adder 120 and then this output g is delayed by (T/2) by the delay element 150 having the period (T/2) and held in the last stage delay element 104 for the period T, the following output signal {y'(i)} is obtained as the final output h from the This is equivalent to the required output of the transversal filter shown by the equation (1). In other words, to get a required output of the transversal filter, it is necessary to extend the second output sum ΣL by 2.5T more than the first output sum ΣS. Now, if the virtual output terminal 105 is connected to the virtual input terminal 106 for coupling the output of the delay element 160 to the selector 180, α(i) = ΣL is established when the second output sum ΣL is delayed for the period (T/2) by the delay element 160 . In this condition, the arrangement shown in FIGURE 4 becomes equivalent to the arrangement in FIGURE 2. Now when α(i) = ΣL is substituted for the equation (2), the following equation is established. That is, in the circuit arrangement shown in FIGURE 2, by conforming the phase of the second output sum ΣL with that of the first output sum ΣS through the delay element 160 and by compensating an insufficient delay time of the second output sum ΣL while adding it to the first output sum ΣS by the pipeline processing adder 170, a desired output of the transversal filter can be obtained. The principle operation of the transversal filter in the circuit arrangement shown in FIGURE 2 has been so far explained referring to FIGURE 4. Hereinafter, the operation of the transversal filter in the circuit arrangement shown in FIGURE 2 is briefly explained again referring to FIGURE 3, which is the timing chart of FIGURE 2. The selecting signal S and the clock signal CK1 which is used for the last stage delay element 104 have the period T, while the clock signal CK2 has the period (T/2 = T/n). The input signal a, the outputs b, c, d of the tap weight multipliers 110, 111, 112 and the cascade input signal e are entirely the same as those explained in reference to FIGURE 5. Therefore, explanations for the signals will be omitted hereafter. The selecting operation of the selector 180 is operated at the period (T/2 = T/n) Thus, by substituting the virtual input k in FIGURE 5 by the virtual input k as expressed in the following equation; α(i) = C3·x(i-1) + C4·x(i-2) + C5·x(i-3) + z(i-3) the output f of the adder 122 is expressed as the following equation (see FIGURE 3); C2·x(i-2) + C3·x(i-3) + C4·x(i-4) + C5·x(i-5) + z(i-5), C5·x(i-2) + z(i-2), C2·x(i-1) + C3·x(i-2) + C4·x(i-3) + C5·x(i-4) + z(i-4), C5·x(i-1) + z(i-1), C2·x(i) + C3·x(i-1) + C4·x(i-2) + C5·x(i-3) + z(i-3), C5·x(i) + z(i), C2·x(i+1) + C3·x(i) + C4·x(i-1) + C5·x(i-2) + z(i-2), C5·x(i+1) + z(i+1), ....... Also, by substituting the virtual input k in FIGURE 5 by the virual input as expressed in the following equation; α(i) = C3·x(i-1) + C4·x(i-2) + C5·x(i-3) + z(i-3) The output g of the adder 120 becomes the signal as indicated in FIGURE 3. Here, when considering Phase 1 of the output g having the expression indicated in FIGURE 3, the output g contains the factors of all of the tap weights C0, C1, C2, C3, C4, C5 as well as the factor of the input signal a = {x(i)}. Thus an equation the same as the equation (1) is established in the first embodiment as shown in FIGURE 2. Now, delaying Phase 1 of the output g of the adder 120 by (T/2) through the delay element 150 with the period (T/2), and furthermore holding the output g for the period T in the last stage delay element 104, the required output signal h = {y(i)} is obtained at the output terminal 102. FIGURE 6 shows a second embodiment of the present invention. The second embodiment is embodied in that the scale of 6 taps is also realized by 2 times time-division multiplexing, similar to the first embodiment. However, the tap weight selecting order is reversed to that of the first embodiment. The circuit arrangement shown in FIGURE 6 is almost the same as that shown in FIGURE 2. The large difference is that the registers select the tap weights with larger suffixes (C3, C4, C5) when the selecting signal S is "1" and the tap weights with smaller suffixes (C0, C1, C2) when the selecting signal S is "0". Thus, the transversal filter in the circuit arrangement in the second embodiment can be realized by regulating the delay of the feedback loop from the output of the pipeline processing adder 170 to own input and the delay between the output of the pipeline processing adder 170 to the last stage delay element 104. That is, the delay element 150 shown in FIGURE 2 is omitted in the second embodiment, while the output of the adder 120 is connected directly to the input of the last stage delay element 104. Further, the output of the adder 120 is connected to the input of the selector 180 through the delay elements 260, 261 and 262 having the period (T/2 = T/n) and connected in series. The outputs of the sampled signal e and the delay element 262 are supplied to the selector 180 and these 2 signals are selected in the period T. The selector 180 selects the sampled signal e when the selecting signal S is "1" and selects the output of the delay element 262 when the selecting signal S is "0". As to other points, the circuit arrangement shown in FIGURE 6 is entirely the same as that shown in FIGURE 2 and the reference numerals assigned to the elements in FIGURE 6 are also the same as those in FIGURE 2 and therefore, detailed explanations of the arrangement of FIGURE 6 will be omitted hereafter. Shown in FIGURE 7 is a timing chart to explain the operation of the second embodiment shown in FIGURE 6. As shown in FIGURE 7, the selecting signal S and the clock signal CK1 used for the last stage delay element 104 have the same period T, while the clock signal CK2 has the period (T/2 = T/n). As the input signal a is sampled at the period T, the data content of the input signal a changes in the following order. x(i-2), x(i-1), x (i), x (i+1),... As the tap weights being selected by the period (T/2), the outputs d, c, b of the tap weight multipliers 110, 111, 112 change in following orders. In case of the output d of the tap weight multiplier 110; C3·x(i-2), C0·x(i-2), C3·x(i-1), C0·x(i-1), C3·x(i), C0·x(i), C3·x(i+1), C0·x(i+1), .... In case of the output c of the tap weight multiplier 111: C4·x(i-2), C1·x(i-2), C4·x(i-1), C1·x(i-1), C4·x(i), C1·x(i), C4·x(i+1), C1·x(i+1), .... In case of the output b of the tap weight multiplier 112: C5·x(i-2), C2·x(i-2), C5·x(i-1), C2·x(i-1), C5·x(i), C2·x(i), C5·x(i+1), C2·x(i+1), .... Further, as the cascade input signal e being sampled at the period T, the data content of the signal e changes in the following order, at the period of the clock signal CK1 and the "1" and "0" of the selecting signal S. z(i-2), z(i-1), z(i), z(i+1), ... The output g of the adder output 120 is input to the selector 180 through the series connection of the delay elements 260, 261, 262 each with delay period (T/2). As the selector 180 alternately selects the cascade input signal e and the output g of the adder 120 delayed by the period 1.5T, at the period (T/2), the output f of the adder 122 changes in the following order. C5·x(i-2) + z(i-2), C2·x(i-2) + C3·x(i-3) + C4·x(i-4) + C5·x(i-5) + z(i-5), C5·x(i-1) + z(i-1), C2·x(i-1) + C3·x(i-2) + C4·x(i-3) + C5·x(i-4) + z(i-4), C5·x(i) + z(i), C2·x(i) + C3·x(i-1) + C4·x(i-2) + C5·x(i-3) + z(i-3), C5·x(i+1) + z(i+1), C2·x(i+1) + C3·x(i) + C4·x(i-1) + C5·x(i-2) + z(i-2), .... The output g of the adder 120 is also indicated in FIGURE 7. Now, when considering Phase 2 of the output g shown in FIGURE 7, the output g contains the factors of all of the tap weights C0, C1, C2, C3, C4, C5 as well as the factor of the input signal a = {x(i)}. Thus an equation the same as the equation (1) is established in the second embodiment as shown in FIGURE 6. When the transversal filter is operated to hold Phase 2 in the last stage delay element 104 for the period T, the desired output signal h = {y(i)} can be obtained at the output terminal 102. Thus, the second embodiment is almost the same as the first embodiment except that the tap weight selecting order is changed, and then the number of delay elements is adjusted to fit the selecting order of the selector 180 for returning the output g to the pipeline processing adder 170. Thus, the second embodiment is one of variations from the present invention having a scale of 6 taps, similar to the first embodiment as described above with two times time-division multiplexing. FIGURE 8 shows a third embodiment of the transversal filter according to the present invention. The third embodiment of the transversal filter shows a case where the number of taps k is 6, like the first and the second embodiments as described above, with three times time-division multiplexing for tap weights . The input signal a = {x(i)}, sampled at every period T, is input to the input terminal 101. This input signal a is then applied to the tap weight multipliers 310, 311. To these tap weight multipliers 310, 311, tap weights from the tap weight registers 390, 391 are supplied, respectively. In each registor three tap weights are selectively applied to the associated multiplier, during the period T. That is, tap weights C0, C2, C4 are selected in the tap weight register 390. Also, tap weights C1, C3, C5 are selected in the tap weight register 391. The tap weight registers 390, 391 are driven by a third clock signal CK3 of the period (T/3) and output the tap weights C0, C1, respectively, at the beginning phase of the sampling clock for the input signal a = {x(i)}. The tap weights C2, C3 are output at the intermediate phase of the sampling clock. The tap weights C4, C5 are output at the end phase of the sampling clock. Hereinafter, these three phases are called Phase 1, Phase 2 and Phase 3. The output of the tap weight multiplier 310 is supplied to the adder 320, while the output of the tap weight multiplier 311 is supplied to the adder 321. Between the adders 320, 321, three delay elements 330, 331, 332 each having the delay time (T/3) are connected in series. The adders 320, 321 and the delay circuit including the delay elements 330, 331, 332 forms a pipeline processing adder 370. The output of the pipeline processing adder 370 is input to the delay elements 350, 351 each having the delay time (T/3) and connected in series. The output of the delay element 350 is input to the last stage delay element 104 having the delay time T. The output of this last stage delay element 104 is connected to the output terminal 102. Further, the output of the pipeline processing adder 370 is input to the selector 380 after passing through two feedback loops. One of these feedback loops to the selector 380 passes through delay elements 360, 361 which have the delay time (T/3), respectively, and are connected in series. Another feedback loop to the selector 380 passes through the delay elements 362, 363 which have the delay time (T/3) and are connected in series. All of these delay elements 330, 331, 332, 350, 351, 360, 361, 362, 363 are driven by the clock signal CK3. The last stage delay element 104 is driven by the clock signal CK1. The cascade input signal e = {z(i)}, sampled at every period T, is input to the cascade input terminal 103. This sampled signal e is input to the selector 380. To this selector 380, the sampled signal e and the outputs of the delay elements 361, 363 are supplied. However, during the period T, these three kinds of signals are each selected once, for a third of the period T. The selector 380 selects the output of the delay element 363 at Phase 1, the output of the delay element 361 at Phase 2 and the sampled signal e at Phase 3. The output of the selector 380 is connected to the adder 321 in the pipeline processing adder 370. Shown in FIGURE 9 is a timing chart for explaining the operation of the transversal filter of the third embodiment according to the present invention. As shown in FIGURE 9, the clock signal CK3 for selecting the tap weights from the tap weight registers 390, 391 has the period equal to the 1/3 of the sampling period T. Accordingly, the input signal a is multiplied with the tap weights from the tap weight registers on the basis of the time-division multiplex. As a result, signals n, m as shown in FIGURE 9 are output from the multipliers 310, 311. Therefore, similar to the first embodiment, the outputs of the adders 321, 320 will become as shown by signals p, q shown in FIGURE 9 respectively. Thus, the output q of the adder 320 at Phase 3 is added to the output p of the adder 321 at Phase 2 through the delay elements 360, 361. Similarly, the output q of the adders 320 at Phase 2 is added to the output p of the adder 321 at Phase 1 through the delay elements 362, 363. So, if the output q of the adder 320 at every Phase 1 is delayed by (2T/3) in the delay elements 350, 351 each having the period (T/3), and then held in the last stage delay element 104 for the period T, a desired output signal h = {y(i)} can be obtained from the output terminal 102. Hereinabove, three embodiments of the present invention have been explained. However, the present invention is not limited to these three embodiments. For instance, the first and second embodiments have the same number of taps k, i.e., 6 and the same factor of time-division multiplexing, i.e., 2 times, while they differ from each other in the tap selecting order in the tap weight registers 190, 191, 192. The third embodiment has the number of taps k, which is also 6, and 3 times time-division multiplexing. In the third embodiment, the tap weight selecting order can be changed in various ways. In this case, similar to the case of the 2 times time-division multiplexing, the transversal filter of the third embodiment shown in FIGURE 8 can be realized by regulating the delay : of the two feedback loops between the output and input terminals of the pipeline processing adder 370, the selecting order in the selector 380 for the feedback loops and the delay between the output of the pipeline processing adder 370 and the last stage delay element 104. In the third embodiment shown in FIGURE 8, the two feedback loops have the same arrangements, but this agreement merely occurs in this case. Further, in the first embodiment shown in FIGURE 2, the delay elements 150, 160 are separated in these two elements. However, this is merely made to explain the principle of the present invention. Thus, the output of the delay element 150 may be connected to the selector 180, but not passing through the delay element 160. Further, in FIGURE 6 it is clearly understood that the delay elements 260, 261, 262 can be replaced by two pieces of delay elements in total, one having the period (T/2) and the other having the period T. In FIGURE 8, the first feedback loop having the delay elements 360, 361 and the other feedback loop having the delay elements 362, 363 are separated from each other, and further the selector 380 has three inputs to be selected. However this is also made to facilitate the explanation of the present invention. That is, it is possible to obtain the same result without separating them. Further, it is possible to eliminate the delay elements 360, 361, 362, 363 by applying the output of the delay 350 to the selector 380. Further, for setting the delay of the feedback loop, appropriate delay elements may be provided between the selector 380 connected to the feedback loop and the input end of the pipeline processing adder 370. Further, in the present invention, the cascade input terminal 103 is not compulsory, and it is clearly understood that the circuit arrangement can be made more simple,when regarding the cascade input signal e = 0. How these tap weight selecting order and delay amount should be treated or how actual circuits should be constructed are the design matters easy to those in the art. According to the present invention it is possible to realize a transversal filter having an arbitrary number of taps k (k is a natural number not less than 2) using a proper times n of time-division multiplexing. It is needless to say that the present invention can be implemented in many various manners within the range of the spirit of the present invention. According to the present invention, when the same number of taps used in the conventional techniques are required, the number of tap weight multipliers which takes a large scale of circuit arrangement in realtime operation filter components can be reduced exceptionally. Therefore, if the transversal filter is fabricated in IC chips, the chip area becomes small and cost per the same function is reduced. Further, when the transversal filter is allowed the same scale of circuit arrangement as conventional filters, the number of taps can be increased substantially so that it becomes possible to realize effective hardware, especially by using the filter in deghosting devices, etc. As described above, the present invention can provide an extremely preferable input-weighted transversal filter. While there have been illustrated and described what are at present considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the appended claims. In addition, many modifications may be made to adapt a particular situation or material to the teaching of the present invention without departing from the scope of the claims. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the present invention, but that the present invention include all embodiments falling within the scope of the appended claims.

Claims: An input-weighted transversal filter for filtering a sampled input signal with a sampling period comprising: register means (190-192, 390, 391) holding a plurality of tap coefficients; a plurality of multiplier means (110-112, 310, 311) for multiplying said tap coefficients with the sampled input signal; a pipeline processor (170, 370) including a plurality of adding means (120-122, 320, 321) separated by at least one delay element (130-133, 330-332) from one another, the pipeline processor adding the multiplied outputs from the multiplier means, wherein during one sampling period of the input signal each multiplier means (110-112, 310, 311) consecutively multiplies the input signal by more than one tap coefficient supplied to the multiplier by the register means (190-192, 390, 391) in a specific order; characterised in that during a part of each sampling period of the input signal an output signal from the pipeline processor is selected by selection means (180, 380) as an input to the pipeline processor (170, 370). An input-weighted transversal filter as claim 1 wherein the output signal which is selected is delayed and the delay depends upon the order of tap coefficients supplied to the multiplier means by the register means. An input-weighted transversal filter as claimed in claim 1 or 2 where the signal selected by the selection means is subject to further delay before being input to the pipeline processor. An input-weighted transversal filter as claimed in any preceding claim wherein each adding means in the pipeline processor corresponds to one of the plurality of multipliers, and the output of each multiplier means serves as one input to the corresponding adder. An input-weighted transversal filter as claimed in any preceding claim wherein each tap coefficient supplied by the register means to the multiplier means is supplied once, and each multiplier means is supplied with equal numbers of tap coefficients, in a specified order. An input-weighted transversal filter as claimed in claim 5 wherein the number of delay elements, each having the same delay time, located between two consecutive adding means of the pipeline processor is equal to the number of tap coefficients supplied to each multiplier means, and wherein the total delay effected by the delay elements between two consecutive adder means is equal to the sampling period of the input signal. An input-weighted transversal filter as claimed in any preceding claim wherein, during a further part of each period of the input signal, a second input signal is selected by the selection means as an input to the pipeline processor and the output signal from the pipeline processor is supplied to an output of the filter. An input-weighted transversal filter as claimed in any preceding claim, further comprising feedback means for supplying the output signal of the pipeline processor to the selection means with a delay of T/n wherein n is an integer greater than 1, and T is the sampling period of the input signal. An input-weighted transversal filter as claimed in claim 8, wherein the plurality of adding means which add the tap weighted signals to the pipeline signal and are connected in series by a plurality of delay means, each of the delay means being connected in series between two adjacent adders of the plurality of adders, wherein the delay means includes n delay elements connected in series, each of the delay elements having a delay period of T/n. An input-weighted transversal filter as claimed in one of claims 1-7, further comprising feedback means for inputting a selected signal to an input of the pipeline processor, the feedback means including a selector for selectively inputting the selected signal to the predetermined input of the pipeline processor for at least a time interval of 1/n within the sampling period of the input signal wherein n is an integer greater than 1.

Inventors: NISHIKAWA MASAKI, NISHIKAWA, MASAKI, NISHIKAWA, MASAKI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: H03H17
IPC codes: H03H15, H03H17, H04B3