Chip type solid electrolytic capacitor

Abstract: According to this invention, a chip type solid electrolytic capacitor includes a capacitor element (1), an insulating sheathing resin layer (4a), two anode terminals (2a), and a cathode terminal (9a). The capacitor element is obtained by sequentially forming an oxide film, a solid electrolytic layer, and a cathode conductive layer (5) on an anode body consisting of a valve metal in which anode leads (2a) are extracted from two opposite end faces. The insulating sheathing resin layer (4a) is coated on an entire outer surface except for both anode lead extraction end faces and a predetermined portion of one surface. The two anode terminals (2a) are formed on both the anode lead extraction end faces and peripheral portions thereof. The cathode terminal (9a) is formed the cathode conductive layer exposed from said insulating sheathing resin layer (4a).

Description: The present invention relates to a chip-type solid electrolytic capacitor according to the introductory portion of claim 1. In IBM Technical Disclosure Bulletin, Vol. 28, No. 3, August 1985, pages 1310-1311 "Non-Reversible Surfache-Mounted Chip Capacitor" a three-element connector arrangement of a capacitor element of the above-mentioned kind is disclosed. As conventional chip type solid electrolytic capacitors, for example, there are a resin-molded capacitor and a simple resin-sheathed capacitor. In the resin-molded capacitor, external anode and cathode leads 12 and 13 are connected to both the terminals of a capacitor element 11 manufactured by the well-known technique as shown in Fig. 5, and an insulating sheathing resin layer 14 is formed by externally coating these leads 12 and 13 with a molding resin. In the simple resin-sheathed capacitor, a capacitor element 11 is simply coated with an electrostatic powder resin 24 or the like to form an insulating sheathing resin layer 24, and external terminals 22 and 23 are directly connected to both the terminals of the capacitor electrode 11 without using anode and cathode leads. In each of the conventional chip type solid electrolytic capacitors, the capacitor element 11 has rectifying characteristics. For this reason, when a chip is mounted on a printed wire board with its terminals being connected to erroneous polarities, a backward voltage is applied to the chip, and the following problems are posed. That is, breakdown occurs in the capacitor element 11, a large short-circuit current flows, and the temperature of the capacitor element 11 is increased to cause burnout of the capacitor element 11. It is an object of the present invention to provide a chip type solid capacitor capable of preventing breakdown caused by erroneous polarity confirmation when a polarized capacitor chip is mounted on a printed board. It is another object of the present invention to provide a chip type solid capacitor capable of improving its workability by omitting polarity confirmation of a polarized capacitor chip. In accordance with the present invention, said objects are obtained with the features of the characterizing part of claim 1. Preferred embodiments of the invention are mentioned in the subclaims. Fig. 1 is a sectional view showing a chip type solid electrolytic capacitor according to an embodiment of the present invention; Fig. 2 is a perspective view showing the lower portion of the embodiment shown in Fig. 1 according to the present invention; Fig. 3 is a sectional view showing a chip type solid electrolytic capacitor according to another embodiment of the present invention; Fig. 4 is a perspective view showing the chip type solid electrolytic capacitor shown in Fig. 3 according to the present invention; Fig. 5 is a sectional view showing a conventional chip type solid electrolytic capacitor; and Fig. 6 is a sectional view showing another conventional chip type solid electrolytic capacitor. Description of the Preferred Embodiments The present invention will be described below with reference to the accompanying drawings. Fig. 1 shows a chip type solid electrolytic capacitor according to an embodiment of the present invention, and Fig. 2 shows the lower portion of the chip type solid electrolytic capacitor shown in Fig. 1. An oxide film and a solid electrolytic layer are sequentially formed on an anode body consisting of a valve metal in which anode leads 2 are extracted from the two opposite end faces (left and right end faces in Fig. 1) of the anode body, and a repellent resin layer 3 is formed on each of both anode lead proximal portions 2a of the anode body. Thereafter, in a capacitor element 1 on which a cathode conductive layer (not shown) is formed by the well-known technique, the upper end of the repellent resin layer 3 is removed by a cutting operation, the anode leads 2 and the center portion of one surface (lower surface in Fig. 1), on which a cathode terminal is formed, of the four remaining surfaces (upper, lower, front, and rear surfaces in Fig. 1) adjacent to anode lead extraction end faces 1a are masked, and electrostatic powder coating is performed on the resultant structure, thereby forming an insulating sheathing resin layer 4a on an entire outer surface of the element except for the masked portions. A silver paste is baked at 150°C for 30 minutes on the cathode conductive layer of the capacitor element 1 which is exposed by the masking operation so as to form a conductive layer 5 having a thickness almost equal to the thickness of the insulating sheathing resin layer 4a. A butyl acetate solution containing palladium-amine compound is coated on the insulating sheathing resin layer 4a of the anode lead extraction end faces and the peripheral portions thereof and baked at 85°C for 10 minutes, thereby depositing palladium serving as a metal catalyst to the anode portions. Plating layers 6 are formed on the anode portions to which palladium is deposited and on the conductive layer 5 formed on the lower surface of the capacitor element 1, and a solder layer 7 is formed on each of the plating layers 6. The plating layer 6 and solder layer 7 on the conductive layer 5 are used as a rectangular cathode terminal 9a as shown in Fig. 2, and the anode leads 2 are cut to form anode terminals 8 each having a shape for covering an end face of the capacitor element 1, thereby arranging a chip type solid electrolytic capacitor. Fig. 3 and 4 show a chip type solid electrolytic capacitor according to another embodiment of the present invention. In a capacitor element 1 formed following the same procedures as in Fig. 1, the upper end of a repellent resin layer 3 is removed by a cutting operation, and anode leads 2 and a ribbon-like central portion extending through the four surfaces adjacent to anode lead extraction end faces are entirely masked, and electrostatic powder coating is applied to the resultant structure to form an insulating sheathing resin layer 4b on an entire outer surface of the element except for the masked portions. A silver paste is baked at 150°C for 30 minutes on the exposed cathode conductive layer of the capacitor element 1 to form a conductive layer 5 having a thickness almost equal to the thickness of an insulating sheathing resin layer 4a, and a butyl acetate solution containing palladium-amine compound is coated on the insulating sheathing resin layer 4a of each of the anode lead extraction end faces and on a peripheral portions thereof and baked at 185°C for 10 minutes, thereby attaching palladium serving as a metal catalyst to anode portions. Plating layers 6 are simultaneously formed on the anode portions to which palladium is deposited and on the conductive layer 5 formed on the capacitor element 1, and a solder layer 7 is formed on each of the plating layers 6. A ring-like cathode terminal 9b is formed by the plating layer 6 and the solder layer 7 on the conductive layer 5 as shown in Fig. 4, and the anode leads 2 are cut to form anode terminals 8, thereby arranging a chip type solid electrolytic capacitor. In this embodiment, since the cathode terminal 9b is formed on the entire outer surface of the chip, any one of the four surfaces adjacent to the anode lead extraction end faces can be used as a surface to be mounted on a printed board. As described above, in a chip type solid electrolytic capacitor according to the present invention, a cathode terminal is formed on the central portion of a chip, and two anode terminals are formed on both the ends of the chip. For this reason, the chip type solid electrolytic capacitor is symmetrical, and polarities of the capacitor do not depend on the direction of the chip. Therefore, the following accident can be prevented. That is, the chip is mounted on a printed board with its terminals being connected to erroneous polarities, and the capacitor has failed by being applied with a backward voltage. In addition, since a cathode terminal may be formed on the entire outer surface of the chip, any one of four surfaces adjacent to anode lead extraction end faces can be used as a surface to be mounted on the printed board.

Claims: A chip-type solid electrolytic capacitor comprising a capacitor element (1) having two opposite end faces and side surfaces extending between said end faces two opposite anode leads (2a) extending from said end faces; two opposite anode terminals (8) formed on said end faces and on connecting peripheral portions thereof, said anode terminals being connected to said anode leads; and a cathode terminal (9a; 9b) on said side surfaces of said capacitor element, characterized in that said capacitor element comprising an anode body consisting of a valve metal with an oxide film, a solid electrolytic layer and a cathode conductive layer sequentially formed on said anode body; said both anode leads (2a) consist of a continuous common lead (2) extending through said capacitor element (1); an insulating sheathing resin layer (4a; 4b) coated on the entire outer surface of said capacitor element except said opposite end faces and a predetermined portion of said side surface; said cathode terminal (9a, 9b) formed on a central portion of at least one of said side surfaces of said cathode conductive layer (5) exposed from said insulating sheathing resin layer, said conductive layer having a thickness equal to the thickness of said insulating sheathing resin layer. A capacitor according to claim 1, wherein said anode and cathode therminals (8; 9a; 9b) consist of sequentially formed plating layer (6) and solder layer (7). A capacitor according to claim 1, wherein said capacitor element (1) having a rectangular shape with said two opposite end faces and four side surfaces. A capacitor according to claim 3, wherein said cathode terminal (9a) is formed on a central portion of one of said four side surfaces and having a rectangular shape. A capacitor according to claim 3, wherein the cathode terminal is extending over said four side surfaces forming a ring-like terminal (9b).

Inventors: TANIGUCHI HIROMICHI C O NEC CO, TANIGUCHI, HIROMICHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01G9
IPC codes: H01G9