Method and circuit arrangement for movement detection in a television picture

Abstract: A method and a circuit arrangement for movement detection in a television picture, whereby the video signal is in digital form and the picture is divided into blocks (BL) with the size of more than one picture element (PIX). The video signal sample is cut, and a code word is generated using the cut video signal sample and compared with the code word of the corresponding block (BL) of a previous picture in order to make the movement decision.

Description: The invention relates to a method and a circuit arrangement for movement detection in a television picture, wherein the video signal is in digital form and the picture is divided into blocks comprising more than one picture element, and wherein a code word is generated for each block, the code word being compared with the code word of the corresponding block of a previous picture in order to make the movement decision. A television picture comprises two half pictures or fields which are scanned in an interlaced mode. Thus the lines of different half pictures will not coincide. If the picture contains straight horizontal boundaries having a strong contrast, then 25 Hz flicker will occur there. In the PAL standard, the interlaced fields of the picture are scanned at a frequency of 50 Hz. When the picture is dark, the 50 Hz frame rate does not appear as disturbing, whereas the eye will clearly perceive flicker in brighter parts of the picture, and the flicker problem is emphasized, if the picture area is large and the viewing angle is wide. It is possible to reduce the flicker in the picture or to remove it completely by storing a field in a field memory and displaying it, either as such or slightly modified, twice during the same period. Then the field rate increases to 100 Hz and the flicker is not anymore disturbing. The appearance of the line structure in the picture and the disadvantages due to interlacing can be reduced by using progressive scanning. This means that both fields are first written into a memory and read therefrom at alternating lines. Thus the whole picture is scanned in one operation. The method requires the doubling of the line rate. The original field rate is retained in this method. So called movement adaptive methods can be used both to increase the line rate, line rate upconversion (LRU), and to increase the field rate, field rate upconversion (FRU). The movement adaptive methods switch between two algorithms, optimized for a static and a moving picture, depending on whether the picture contains movement or not. Movement detection is thus required in the movement adaptive methods. Known and previously used movement detection methods in most cases are based on difference signals calculated between two pictures and on decisions made from these whether the picture is moving or stationary. A disadvantage of these known methods is their sensitivity to noise. The noise can cause exceptionally large changes in luminance differences, which can cause a wrong movement decision. A wrong movement decision without exception causes degradation of the picture quality in all movement adaptive methods. Usually the methods require at least two field memories. The US-A-3 582 546 discloses a method and circuit arrangement according to the preambles of claims 1 and 6, in particular a redundancy reduction system for video signals wherein the amplitude samples of each picture element are digitized and wherein a code word is generated for blocks of the picture, each block comprising more than one picture element. The code word is generated by subtracting the absolute magnitude of the difference of the amplitudes of the first and second sample of a block from the amplitude of the third sample of the block, whereupon the absolute magnitude of the result of this subtraction is subtracted from the magnitude of the forth sample of the block and so on. Only the least significant bits of the final result formed in this manner for a block are used as a code word for this block, and the code words for the same block in successive pictures are compared and used as an indication for a movement in the television picture. In view of the fact that only the least significant bits of the result of the above subtraction method are evaluated, this method is rather sensitive to noise and digitalization errors. From the JP-A-127 380 (patent abstracts of Japan, Vol. 13, No. 216E760, 3564, 19-05-89), an inter-frame coding system is known wherein 8-bit picture element data is inputted to binarizing circuits wherein bit values of a Laplacian filter are multiplied with each picture element. The result of multiplication is compared with a threshold value and a binary '1' is produced when the result is larger than the threshold value, whereas a binary '0' is produced when the result is smaller than the threshold value. All results are stored in a respective frame memory. The object of the present invention is to provide a method and apparatus for movement detection which is reliable, has a very good noise tolerance and reduces the manufacturing cost of the circuits for performing the method. According to one aspect of the present invention as defined in claim 1, a method for movement detection in a television picture is provided, wherein the video signal is in digital form and the picture is divided into blocks having the size of more than one picture element, each picture element being represented by a digital video signal sample comprising a plurality of bits and wherein a code word is generated for each block, the code word being compared with the code word of the corresponding block of a previous picture in order to make the movement decision. This method is characterized by the fact that a predetermined number of the most significant bits of each digital video signal sample of the picture elements of a block is used for generating the code words. According to a preferred embodiment, the predetermined number equals 1, i.e. only the most significant bit of each digital video sample is used for generating the code words. According to a further aspect of the present invention as defined in claim 6, a circuit arrangement is provided for performing the above method, said arrangement comprising: a memory block in which the picture is divided into blocks having the size of more than one picture element and containing at least one line memory and at least two delays; means for generating a code word for each block; a comparison block in which the code word generated for the block is compared with the code word of the corresponding block of the previous picture and containing a RAM memory into which the previous picture is stored; and circuits to perform the comparison. Said arrangement is characterized by the fact that it comprises: a thresholding block, to which the digital video signal sample is supplied and from which a predetermined number of the most significant bits of each video signal sample of the picture elements of a block is supplied to the memory block, and a coding block, to which the signal is supplied from the memory block and where a code word is generated for the blocks using said predetermined number of the most significant bits of the digital video signal samples of a respective block and which comprises shift-and-add circuits and from which said code word is supplied to the comparison block. The method for movement detection of the present invention is not sensitive to noise and can be realized using less field memory than with prior known methods. With the present invention, the digital video signal sample is cut, i.e. only one or more of the most significant bits are used, and the code word is generated using the cut video signal samples. With the present invention, video signal samples of several bits are cut in a thresholding block, whereupon with the aid of line memories and delays, blocks having the size of several picture elements are generated from the picture, the movement detection being performed on these blocks. A code word is generated for each block with the aid of a shift-and-add circuit, the code word containing for each picture element a number of bits corresponding to the length of the cut video signal sample. Finally the corresponding code words of two pictures are compared in the comparison block. The code words of the previous picture are obtained from a RAM memory. If the code words differ, there was a movement, and if they are equal, then there was no movement. The invention is described in further detail below with reference to the enclosed drawings, in which Fig. 1 shows a block diagram of a circuit realizing the method of the present invention, Fig. 2 shows the division of a picture into blocks of 2*2 elements, and Fig. 3 shows a more detailed construction of a circuit for performing the method of the present invention. Fig. 1 shows a block diagram of a circuit for performing the method. The video signal is in a digital form and it is processed with the methods of digital signal processing. Below is explained as an example the cutting of an 8-bit video signal sample into a 1-bit signal in the thresholding block 1. The video signal sample may contain any number of bits in the method according to the invention and it can also be cut into a signal which contains more than one bit after the cutting. Cutting the 8-bit sample into a 1-bit signal corresponds to the thresholding of a picture with 256 shades into a picture with 2 shades. The cutting can be made because the most significant bit of the sample provides sufficient information for the detection of a movement. Blocks of e.g. 2*2 picture elements in the horizontal and vertical directions are formed of the picture after the cutting, the detection being performed on these blocks. The blocks are generated in the memory block 2 containing a line memory LT and two delays T with the length of one sample. As a result of the block generation the resolution of the movement detector is also 2*2 picture elements. Then a code word is generated in the coding block 3 for each block of 2*2 picture elements. The code word for each picture element contains a number of bits corresponding to the length of the cut sample, i.e. in this example the code word contains one bit for each picture element, whereby the code word representing one block contains a total of four bits. Two corresponding code words of two pictures are compared in the comparison block 4. If the code words differ, there was a movement, and if they are equal, then there was no movement. Fig. 2 shows as an example a 2*2 block BL comprising four picture elements PIX. The figure also shows the factors PIX 1 , PIX 2 , PIX 3 and PIX 4 for the generation of the code word according to the expression 2 0 PIX 1 + 2 1 PIX 2 + 2 2 PIX 3 + 2 3 PIX 4 . The factors PIX 1 , PIX 2 , PIX 3 , PIX 4 obtain as values the value of the cut video signal sample, i.e. 1 or 0, so that a code word contains one bit for each picture element PIX. The method provides a movement decision for each Block BL, which means that the movement decisions for the four adjacent picture elements PIX always are equal. The resolution of the movement detector is thus reduced to one quarter of the conventional. This was not found to affect the quality of the picture. Because the number of picture elements PIX in the block BL is not limited to four and the cut video signal sample can be longer than 1, the code word can be formed according to the more general expression below: where k is the length of the cut video signal sample, n is an integer, N is the number of picture elements PIX contained in the block BL, and PIX n represents the picture elements PIX of the block BL and obtains as a value the value of the cut video signal samples. Fig. 3 shows a more detailed construction of a circuit realizing the method. In the figure it is seen that the 8-bit video signal sample is supplied to the thresholding block 1, where it is cut to a 1-bit signal. Then in the memory block 2 the picture is divided into blocks BL of 2*2 elements PIX 1 , PIX 2 , PIX 3 and PIX 4 , the memory block containing a line memory LT and two delays T. A code word is generated for the blocks BL in the coding block 3, formed by shift-and add circuits SHIFT and ADD. The 4-bit code word formed of the picture is compared with the code word of the corresponding block BL of the previous picture in order to make the movement decision. The code words of the previous picture are obtained from the RAM memory RAM, which is written and read at the half sampling frequency. The comparison is made in the comparison circuit COMP, which may comprise e.g. AND-circuits. If the comparison result is md = 1, then there was no movement. If the result is md = 0, then there was movement between the pictures. The movement decision provided by the method was found reliable. The method has a very good noise tolerance, as there is a high threshold before the detection. The change of shades caused by the noise has no effect at this order. The circuit realizing the method is very simple, which reduces the manufactoring costs of the circuit. Instead of the conventional two field memories only a half field memory (720 * 288 * 4 bit) is needed when the video signal sample is cut into a 1-bit signal. Multiplications are not required at all. The invention can be applied in IDTV (Improved Definition Television) and in HDTV IDTV (High Definition Television) receivers, where it can be used to increase both the line rate and the field rate.

Claims: A method for movement detection in a television picture, wherein the video signal is in digital form and the picture is divided into blocks (BL) having the size of more than one picture element (PIX), each picture element being represented by a digital video signal sample comprising a plurality of bits and wherein a code word is generated for each block, the code word being compared with the code word of the corresponding block (BL) of a previous picture in order to make the movement decision, characterized in that a predetermined number of the most significant bits of each video signal sample of the picture elements of a block is used for generating the code words. Method according to claim 1, characterized in that each video signal sample comprises 8 bits. Method according to claim 1 or 2, characterized in that only the most significant bit of each video signal sample is used for generating said code words. Method according to any previous claim, characterized in that each block (BL) comprises 2*2 picture elements. Method according to any previous claim, characterized in that each code word is formed according to the expression: where k is the number of bits of the video signal sample used for generating the code word, n is an integer, N is the number of picture elements (PIX) contained in each block (BL), and PIX n represents the picture elements (PIX) of the block (BL) and having as a value the value of the predetermined number of bits of the video signal samples. Circuit arrangement for performing the method according to any of the claims 1 - 5, the arrangement comprising: a memory block (2) in which the picture is divided into blocks (BL) having the size of more than one picture element (PIX) and containing at least one line memory (LT) and at least two delays (T); means for generating a code word for each block; a comparison block (4) in which the code word generated for the block (BL) is compared with the code word of the corresponding block (BL) of the previous picture and containing a RAM memory (RAM) into which the previous picture is stored; and circuits (COMP) to perform the comparison, characterized in that it comprises: a thresholding block (1), to which the digital video signal sample is supplied and from which a predetermined number of the most significant bits of each video signal sample of the picture elements of a block is supplied to the memory block (2), and a coding block (3), to which the signal is supplied from the memory block (2) and where a code word is generated for the blocks (BL) using said predetermined number of the most significant bits of the digital video signal samples of a respective block and which comprises shift-and-add circuits (SHIFT, ADD) and from which said code word is supplied to the comparison block (4). A circuit arrangement according to claim 6, characterized in that the adding circuit of the coding block (3) has four inputs, and that the first input receives from the thresholding block (1) via the line memory (LT) and a delay (T) the bit of the PIX 1 factor of the code word, the second input receives from the thresholding block (1) via the line memory (LT) and a shift circuit (SHIFT) the bit of the PIX 2 factor of the code word, the third input receives from the thresholding block (1) via a delay (T) and two shift circuits (SHIFT) the bit of the PIX 3 factor of the code word, and the fourth input receives from the thresholding block (1) via three shift circuits (SHIFT) the bit of the PIX 4 factor of the code word, wherein PIX 1 , PIX 2 , PIX 3 , PIX 4 factors represent the picture elements (PIX) of the block (BL) and have as a value the value of the predetermined number of bits of the video signal sample. A circuit arrangement according to claim 6, characterized in that the RAM memory (RAM) of the comparison block (4) comprises a half field memory (720 * 288 * 4 bit).

Inventors: KOIVUNEN TERO, KOIVUNEN, TERO
Applicants: SALORA OY
Application year: 1992
Main classification: H04N5
IPC codes: H04N5