Liquid crystal display device with reduced cell gap variation and method of manufacturing the same

Abstract: Variations in the individual liquid crystal cells and cross-talk between adjacent pixels are reduced, stable operation is maintained and the aperture and the S/N ratio are increased by providing a transistor and an interconnection layer therefor on one surface of an insulating layer while providing an electrode for applying a voltage to a liquid crystal on the other surface thereof. One major electrode portion of the transistor and the liquid crystal voltage applying electrode are connected to each other using an electrode via an opening. Also, the electrode for connecting the major electrode portion 3 to the liquid crystal voltage applying electrode is provided on the other surface of the insulating layer such that it shield the transistor from light.

Description: The present invention relates to a liquid crystal image display device, a method of manufacturing the same, and an electrode bearing substrate for use therein. In recent years, liquid crystal image display devices have been attracting attention as providing thin and lightweight devices intended to replace cathode ray tube image displays. A cross-sectional view of a cell portion of a conventional liquid crystal image display device is shown in Fig. 1 in which reference numeral 100 denotes a driving transistor for driving a liquid crystal; 101 denotes a glass substrate; 102, 103 and 104 respectively denote a source electrode, a drain electrode and a gate electrode of the driving transistor 100, a signal voltage to be applied to a liquid crystal layer being applied to a transparent electrode 106 via an interconnection 105 to the driving transistor 100; 107 and 109 denote insulating layers; 108 denotes a liquid crystal layer which is driven when a difference in voltage is applied between a transparent electrode 110 and the transparent electrode 106; and 111 denotes a glass substrate on which a light blocking layer 112 is formed to prevent light from illuminating the driving transistor 100. The typical liquid crystal cell in Fig. 1 has problems in that (1) there are variations in the thickness of the liquid crystal layer as well as an unstable alignment of the liquid crystal molecules,and (2) there is light leakage from the adjacent individual pixels which can cause cross-talk. These problems are explained in more detail below. (1) Variations in the liquid crystal layer thickness and unstable alignment of the liquid crystal molecules. As can be seen from Fig. 1, the liquid crystal layer 108 is provided on the driving transistor 100 and the interconnection layer 105. Both the driving transistor 100 and the interconnection layer 105 define "shoulders" where the thickness of the liquid crystal layer 108 between the transparent electrodes 106 and 110 serving as the display electrodes varies in each pixel, as indicated by intervals 113, 114 and 115 in Fig. 1. This makes impossible applying a uniform electric field to the liquid crystal layer 108. In a colour display device, for example, the alignment of the liquid crystal changes slightly and thus generates an undesirable change in colour Furthermore, due to problems related to the production process, there are variations in the shoulders of individual pixels such that the display characteristics of the individual pixels differ, generating a fixed pattern noise. These shoulders cause problems even in a display device with pixel dimensions as large as 60 x 89 µm. To overcome this deficiency, the effective portion may be provided by a flat area alone. However, this reduces the aperture ratio and thus darkens the display screen. Furthermore, in a desirable display device in which the number of pixels has been increased from several ten thousands used currently to a range of from several hundred thousands to one million, the pixel size is further reduced to a range of from 20 x 30 µm 2 to several tens µm 2 , practically eliminating the flat area. The shoulders may be reduced also by increasing the thickness of the insulating layers 107 and 109. However, this weakens the electric field effectively applied to the liquid crystal layer, and thus necessitates a corresponding increase in the driving voltage. Since the liquid crystal driving voltage is some 5 v higher than that applied to a normal semiconductor device, any further increase is disadvantageous in terms of the maximum voltage that the driving transistor can withstand. Thus, the reduction in the deleterious effect of the shoulders cannot easily be attained in practice. Since the thickness of the liquid crystal layer 108 is particularly small in a ferroelectric liquid crystal display device, even a slight change in the thickness of the ferroelectric liquid crystal layer may greatly affect the display characteristics, making high-definition display difficult. Furthermore, in a display device in which the electrical capacitance of the liquid crystal (the "liquid crystal capacitance") is not sufficiently large or in which the effective resistance parallel-connected to the liquid crystal capacitance is low, a storage capacitance must be parallel-connected to the liquid crystal capacitance. However, the voltage may also be reduced by increasing the storage capacitance parallel-connected to the liquid crystal capacitance, reducing the aperture ratio and degrading the reliability of the insulating film which forms the storage capacitance. In the aforementioned conventional structure shown in Fig. 1, since the interconnection layer connected to the source 103 and gate 104 of the thin-film transistor is present on the same surface as that of the display electrode 16, the capacitive coupling between the interconnection and the display electrode is large, thus causing disturbance of the display electrode potential due to cross-talk and deteriorating the display quality of the liquid crystal display device. To reduce cross-talk, the distance between the interconnection layer and the display electrode may be increased. However, this reduces the aperture ratio. Reduction in cross-talk may also be achieved by increasing the thickness of the interlayer film provided between the interconnection layer and the display electrode. However, this increases the magnitude of the shoulders. Additionally, the liquid crystal molecules are normally aligned to the substrate layer by rubbing. Rubbing is performed by mechanically rubbing the surface of the substrate. However, it is difficult to uniformly rub the entire area of the substrate having interconnections providing a large number of shoulders. Thus, the liquid crystal molecules may not be aligned uniformly, causing a display failure or a difference in the characteristics. (2) Light leakage from among the individual pixels As shown in Fig. 1, the light-blocking layer 112 is formed separately from the driving transistor 100. Consequently, when light enters the liquid crystal cell from above as viewed in Fig. 1, oblique or diffracted light may enter adjacent pixels, generating cross-talk. Furthermore, light illuminating the driving transistor 100 generates unnecessary carriers in the driving transistor 100, resulting in an occasional malfunction. Therefore, in order to eliminate- this problem of light leakage, the size of the light-blocking layer is increased. This greatly reduces the effective aperture ratio, as in the case of the aforementioned problem (1). Furthermore, where the light-blocking layer 112 is provided, it has been necessary to provide both the light-blocking layer and an insulating layer, in addition to the interconnection layer. This can further increase the magnitude of the shoulders. Japanese Patent Application JP-A-2-154232 discloses a liquid crystal image display device having the features of the display device recited in the preamble of claim 1 attached. Reference may also be made to German Patent Application DE-A-3720469 which discloses a device of similar structure to the above, differing in having a mirror coated voltage applying electrode. Also reference may be made to German Patent Application DE-A-3015936 concerning the structure of an electroluminescent device. In each of the devices above the transistor is located on an opposite side of an insulating layer to the voltage applying electrode. This arrangement is advantageous in that short circuits between transistor interconnections are avoided and variations of liquid crystal or electroluminescent layer thickness are reduced due to reduction in the stepped structure of the substrate surface. The second problem, that of light leakage, mentioned above has also been solved by providing a -light shield over the transistor. In Japanese Patent Application JP-A-2-154232 other liquid crystal image display devices are described in which a light shielding film is spaced from the transistor by an insulating layer which also covers the voltage applying electrode, or alternatively it is located at the other side of the liquid crystal film. The problems with these arrangements have been discussed above. Japanese Patent Application JP-A-60-236267 and German Patent Application DE-A-3315671 each disclose a liquid crystal device in which the source or drain contact electrode is of light shielding material and the contact electrode is extended over the channel of the transistor. The liquid crystal image display device as defined in claim 1 attached is intended as a solution to both the problems (1) and (2) mentioned above. A specific feature of this display device is a light shielding electrode provided-on the same surface of an insulating film as a transparent voltage applying electrode, and which is interposed between the transistor and the transparent electrode. A method of producing this image display device, and an electrode bearing substrate adapted for use in this image display device are also the subject of the claims attached. Other objects and advantages of the invention will become apparent from the following description given with reference to the accompanying embodiments of which: Fig. 1 is a schematic cross-sectional view of a cell portion of a conventional liquid crystal image display device; Fig. 2 is a schematic cross-sectional view of a cell portion of a liquid crystal image display device; Fig. 3 schematically shows an anodisation apparatus; Figs. 4 through 11 show the steps of a method of manufacturing the liquid crystal cell portion shown in Fig. 2; and Figs. 12 through 14 are respectively schematic cross-sectional views of other liquid crystal image display devices, those shown in figs. 13 and 14 each embodying the present invention. The following description is given by way of example. Whereas a switching transistor, an interconnection layer and a voltage applying electrode are formed on the same surface of an insulating layer (or an insulator) in the conventional image display device of Fig. 1, in an image display device embodying the present invention, the switching transistor and the interconnection layer are formed on one of the surfaces of the insulating layer (insulator) which is remote from the liquid crystal layer while the liquid crystal voltage applying electrode is formed on the other surface of the insulating layer close to the liquid crystal layer. That is, the switching (driving) transistor and the interconnection layer are formed separately from the voltage applying electrode on another surface of the (insulating) substrate. One major electrode of the transistor and the voltage applying electrode are connected to each other via an opening in the insulating layer. In the aforementioned structure, since the switching transistor and the interconnection layer are not formed on the surface of the insulating layer which is closer to the liquid crystal layer, even when the pixel size is reduced, the liquid crystal layer can be formed on a relatively flat layer, reducing variations in the liquid crystal cells and making stable operation possible. In the image display device embodying the present invention, since the liquid crystal layer and the transistor are disposed on different surfaces of the insulating layer, it is possible to provide a light-blocking layer near to the transistor. Consequently, the aperture ratio can be increased, cross-talk among the adjacent pixels can be reduced, and the S/N ratio can be increased. Preferably, the interconnect electrically connecting the major electrode portion of the transistor to the voltage applying electrode is embedded in the opening of the insulating layer, so that it does not make the insulating layer surface, adjacent to the liquid crystal layer, more irregular. Furthermore, the electrode connecting the major electrode portion of the transistor to the voltage applying electrode is formed on the other side of the insulating layer. Therefore, the connecting electrode shields the transistor from light and so, providing another light-blocking layer is not necessary. A comparative example will be described first with reference to figures 2 to 11 of the accompanying drawings. In Fig. 2, reference numeral 1 denotes a transparent substrate which serves as a protective member; 2, 3 and 4 respectively denote a source electrode, a drain electrode (both constituting major electrodes) and a gate of a transistor 18 for driving a liquid crystal; 5 denotes an interconnection which is connected to the source portion 2 and by which a driving voltage is applied to a transparent electrode 13 via the driving transistor 18; 6 denotes a light-blocking layer; 7 denotes an interlayer insulator; 8 denotes a liquid crystal layer; 9, an adhesive layer for adhering the transparent substrate 1 to the driving transistor 18, the interconnection layer and so on; 10 denotes a flat insulating layer (an insulating substrate) provided below the driving transistor 18; 11 denotes a via hole through which the drain 3 of the driving transistor 18 is connected to the transparent electrode 13; 12 is an interconnection provided in the hole 11 to electrically connect the drain 3 to the transparent electrode 13; 13 and 16 are transparent electrodes (where transparent electrode 13 is the so-called voltage applying electrode); 14, 15 and 19 are insulating layers; and 17 denotes a transparent substrate. In the structure of the liquid crystal cell portion shown in Fig. 2: (1) The driving transistor 18, the interconnection 5 and so on are provided on the flat insulating layer 10, and the liquid crystal layer 8 is provided on the side of the rear surface of the insulating layer 10. Since the transparent electrode 13 for applying an electric field to the liquid crystal layer 8 is provided on the surface of the flat insulating layer 10, the electric field between the transparent electrodes 13 and 16 can be made uniform. The liquid crystal cell portion having this structure is advantageous to a fine cell structure because the number or degree of shoulders does not increase even when the pixel size is reduced. (2) Since the liquid crystal layer 8 is not present on the driving transistor portion 18, the light-blocking layer 6 is provided close to the upper portion of the driving transistor portion 18. Although the light-blocking layer 6 has shoulders due to the presence of the driving transistor portion 18 and so on, since the liquid crystal layer 8 is not disposed on the driving transistor portion 18, the magnitude of the shoulders does not affect the characteristics of the liquid crystal device. that is, providing the light-blocking layer 6 close to the driving transistor portion 18 reduces cross-talk caused by light leakage among the adjacent pixels and thus increases the S/N ratio. A manufacturing method of the aforementioned liquid crystal cell portion will be described below. First, porous Si which is used in the manufacturing process of the liquid crystal cell portion will be explained for ease of the understanding of the method. Porous Si was discovered by Uhlir et al in the researching process of the electrolytic polishing of semiconductors in 1956. Unagami et al studied the dissolution reaction of Si in anodization, and reported that anodization of Si in a HF solution requires electron holes and is carried out in the following manner (T. Unagami, J. Electrochem. Soc., Vol. 127, No. 476 (1980): Si + 2HF + (2-n)e + → SiF 2 + 2H + + ne - SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or Si + 4HF + (2-λ)e + → SiF 4 + 4H + + λe - SiF 4 + 2HF → H 2 SiF 6 where e + and e - are respectively an electron hole and an electron, and n and λ are respectively the number of electron holes required for a Si atom to dissolve, porous Si being formed under the condition of n > 2 or λ > 4. As mentioned above, manufacture of porous Si requires electron holes, and P type Si is more easily changed into porous Si than is N type Si. However, it is known that N type Si also changes into porous Si by the injection of electron holes (R. P. Holmstrom and J. Y. Chi. Appl. Phys. Lett. Vol. 42, 386 (1983)). Whereas the single crystal Si has a density of 2.33 g/cm 3 , the density of porous Si can be changed to a range from 1.1 to 0.6 g/cm 3 by changing the concentration of the HF solution from 20 to 50%. It can be observed with a transmission type electronic microscope that the porous Si layer has pores having an average diameter of about 60 nm (600Å) As stated above, though the porous Si layer has a density which is half the density of single crystal Si, it has a single crystal structure and thus allows for a single crystal Si layer to be grown thereon by the epitaxial process. Also, since the porous Si layer has a large number of pores therein and thus has a density which is half the density of a non-porous layer, the surface area thereof is greatly increased relative to the volume thereof, thus greatly increasing the chemical etching rate thereof as compared with that of a non-porous Si layer. Next, the method of forming a porous Si layer by anodization will be described. First, a P type single crystal silicon substrate 200 is prepared. The substrate 200 is setin an apparatus such as that shown in Fig. 3. That is, the substrate 200 is brought into contact with a hydrofluoric acid solution 202, and a negative electrode 203 is disposed on one side of the solution 202 while a positive electrode 201 is disposed on the other side thereof. The portion of the substrate 200 which is in contact with the hydrofluoric acid solution and which is located near the negative electrode is first made porous. Generally, concentrated (49%) hydrofluoric acid solution is used as the hydrofluoric acid solution 202. For the purpose of effectively removing bubbles generated from the surface of the substrate 202 during anodization, alcohol, such as methanol, ethanol, propanol or isopropanol, may be added as the surface-active agent. A stirring device may be used in place of the surface-active agent. Alternatively, both the surface-active agent and the stirring device may be used. The electrodes 201 and 203 are made of a material which cannot be corroded by the hydrofluoric acid solution, such as gold (Au) or platinum (Pt). The current value for anodization ranges from several hundreds A/cm 2 and the minimum is any non-zero value. It is set to a value which ensures that a good quality epitaxial layer can be grown on the surface of the silicon substrate which is made porous by this anodization in a subsequent process. Generally, as the current value increases, the anodization speed increases and the density of the porous silicon layer increases, i.e., the volume of the pores increases, thus changing the epitaxial growth conditions. The method of manufacturing the liquid crystal cell portion will now be described below with reference to Figs. 4 through 11. First, a P type single crystal Si substrate 21 is prepared, as shown in Fig. 4. Next, a 50 µm-thick porous layer 22 is formed on the surface of the P type Si substrate 21 by the aforementioned anodizing process, as shown in Fig. 5. Thereafter, a single crystal low-concentration P type epitaxial layer 23 is formed to a thicknessof 500nm (5000Å) on the porous layer 22, as shown in Fig. 6. Epitaxial growth is performed by the vacuum CVD process under the following conditions: Drain gas : SiH 4 Carrier gas : H 2 Growth temperature : 850 °C Pressure 1 Pa (1 x 10 -2 Torr) Growth rate : 3.3 nm/sec Thereafter, a 50nm (500Å) thick oxide layer 24 is formed on the surface of the epitaxial layer 23, thus completing a wafer 25 which is to be laminated to another wafer. A wafer 26 which is to be pasted to the wafer 25 has a SiN film (a silicon film which contains nitrogen) 28 on a single crystal Si substrate 27, and a silicon oxide film 29 on theSiN film 28, as shown in Fig. 27. Both of the films 28 and 29 have a thickness of about several µm. These two wafers 25 and 26 are laminated with surfaces indicated by 30 opposing each other under the following conditions. First, both of the wafers 25 and 26 are washed first by a pure water and then by a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide, a mixture of hydrochloric acid and hydrogen peroxide, hydrofluoric acid, a mixture of hydrofluoric acid and hydrogen peroxide, an ammonia aqueous solution, a pure water or a combination of any of these solutions. Next, the oxide layers 24 and 29 are laid one on top of another. At that time, the oxide layers 24 and 29 are adhered to each other without conducing heat treatment and without applying external stress. This adhesion is accomplished by hydrogen bonding on the interface between the oxide layers 24 and 29. Next, heat treatment is conducted for laminating the wafers which are adhered to each other by hydrogen bonding. Heat treatment is conducted in an atmosphere of oxygen, nitrogen, hydrogen or a diluted gas, such as helium or argon, at a temperature of 600 °C or above. Generally, the higher the temperature of the heat treatment, the higher the bonding force on the interface, because the hydrogen bonded hydrogen and oxygen atoms are removed in the form of H 2 O at a temperature of about 200 C or above, and condensated silanol bonds (Si-O-Si) remain. However, as long as H 2 O remains in the form of voids or the like near the interface, the bonding force is not at a maximum. The bonding force is maximized when the voids are diffused and thereby completely disappear. The bonding force is saturated at about 900 °C. In this example, annealing is conducted in an annealing furnace for 2 hours at 1000 °C in an atmosphere of nitrogen. After laminating, if the P type Si substrate 21 remains, it is removed by polishing, for example, until the porous layer 22 is exposed. Thereafter, the porous layer 22 is removed by etching using an etchant which exhibits a high selection ratio for Si and porous Si. Examples of suitable etchants used in this embodiment include hydrofluoric acid, buffered hydrofluoric acid and a mixture of hydrofluoric acid/buffered hydrofluoric acid, alcohol (such as ethylalcohol or isopropyl alcohol) and/or hydrogen peroxide. Adding alcohol instantaneously removes bubbles of gas produced by etching from the etching surface without agitating them, thus encouraging uniform and effective etching of the porous Si. Adding hydrogen peroxide increases the oxidation speed of Si, thus increasing the reaction speed as compared with the case in which no hydrogen peroxide is added. A change in the proportion of hydrogen peroxide changes the reaction speed thereof. The concentration and temperature of the solution are set such that they allow hydrofluoric acid, buffered hydrofluoric acid, hydrogen peroxide or alcohol to have their effect and such that they assure an etching speed which can be practically obtained in the manufacturing process. In this example, the porous layer 22 is etched by immersing the pasted substrates in a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (having a mixture ratio of 10 : 6 : 50) at an ambient temperature (without stirring the mixture. The 50 µm-thick porous layer 22 is etched in about 1 minute, thus completing a SOI wafer in which the oxide film 10 and the P - epitaxial film 23 are provided on the Si substrate 27 with the SiN film 28 therebetween, as shown in Fig. 8. Next, as shown in Fig. 9, the P - epitaxial film 23 is removed by etching except for the driving transistor portion 18. After gate oxidation, the n + polysilicon gate electrode 4 is formed. Subsequently, the source electrode 2 and the drain electrode 3 are formed by performing As or P ion injection and annealing by the normal self-alignment procedures using the gate portion 4 as a mask. Next, as shown in Fig. 10, the insulating layer 19, the interconnection electrode 5 to be connected to the source portion 2 and the insulating layer 7 are formed by the normal semiconductor device manufacturing process, and then the metal layer 6 is formed to shield the driving transistor portion 18 from light. The metal layer 6 has shoulders having a large magnitude due to the presence of the driving transistor portion 18, the interconnection 5 and so on below the metal layer 6. However, in the present structure, since the liquid crystal layer is not provided on the surface of the metal layer 6, there is no problem. The transparent substrate 1 is pasted with surfaces indicated by 31 opposing each other by placing adhesive on the surface of the metal layer 6. Next, as shown in Fig. 10, the Si substrate 27 is removed using a hydrofluoric acid type etchant. This etching can be carried out without affecting the oxide layer 10 because the SiN film 28 acts as an etch stop layer. Subsequently, the SiN film 28 alone is removed using a phosphoric acid-type etchant having a large selection ratio for SiO 2 and SiN. Next, as shown in Fig. 11, the hole (opening) 11 through which contact to the drain portion 3 can be provided is formed, and then the interconnection 12 is extended to the rear surface of the insulating layer 10. Thereafter, the ITO layer serving as the transparent electrode and the insulating layer are formed in sequence, and a liquid crystal is disposed at that area to manufacture the image display device shown in Fig. 2. As will be understood from the foregoing description, the insulating layer 10 is formed on the surface of the flat Si wafer, and is thus flat. As a result, the electric field applied to the liquid crystal layer 8 can be made uniform. Another comparative example will be described below with reference to Fig. 12. Since reference numerals in Fig. 12 common to those used in Figs. 2 through 11 represent similar or identical elements, description thereof is omitted. This embodiment is also manufactured by utilizing the SOI technology, as in the aforementioned example. This example differs from the previous example in that a metal interconnection 52 for connecting the drain portion 3 of the driving transistor portion 18 to the transparent electrode 13 on the rear surface of the oxide film 10 is completely embedded in the hole 10, making the surface of the transparent electrode 13 and that of the insulating layer formed on the transparent electrode 13 flatter. Consequently, the electric field applied to the liquid crystal layer 8 can be made more uniform, and stable operation can be achieved. The technique for completely embedding the metal may be Al-CVD, which will be described below. The Al-CVD process is carried out under a pressure of about 10 -1 to 10 5 Pa (10 -3 to 760 Torr) and at a substrate temperature of 60 to 450 °C using alkyl aluminum hydride diluted by H 2 gas. The details of the Al-CVD process have been disclosed in European Patent Application EP-A-0425084. According to this process, it is possible to selectively deposit Al on the surface made of an electron donative material. Al-CVD will be described below in detail. An electron donative material is one in which free electrons are present or intensively produced in a substrate, e.g., a material having a surface which allows chemical reaction to be accelerated by exchange of electrons with the material gas molecules attached to the surface of the substrate. Generally, metals and semiconductors correspond to this electron donative material. Examples of such an electron donative material include semiconductors, such as single crystal silicon, polycrytal silicon and amorphous silicon, binary, ternary or quadri III - V compound semiconductors obtained by combining a III group element, such as Ga, In or Al with a V group element, such as P, As or N, metals, such as tungsten, molybdenum, tantalum, tungsten silicide, titanium silicide, aluminum, aluminum silicon, titanium aluminum, titanium nitride, copper, aluminum silicon copper, aluminum palladium, titanium, molybdenum silicide and tantalum silicide, alloys and silicides of alloys. Dimethyl aluminum hydride ("DMAH", or (CH 3 ) 2 AlH) or monomethyl aluminum hydride ("MMAH 2 ", or CH 3 AlH 2 ) can be used as the alkyl aluminum hydride (DMAH has a dimer structure at ambient temperatures). In a reaction system in which Al reacts with the material gas and H 2 , Al is deposited on the substrate made of any of the aforementioned substances by simple heat reaction alone. In a reaction system in which Al reacts with (CH 3 ) 2 AlH and H 2 , for example, it is considered that heat reaction be basically as follows: It is impossible to deposit Al on the material other than those described above, for example, a highly insulating material, such as SiO 2 , Si 3 N 4 , SiC, BN, diamond, Al 2 O 3 , TaO 2 , by the vacuum CVD process which employs alkyl aluminum hydride diluted by H 2 gas. Thus, when the insulating layer (SiO 2 layer) 10 made of a non-electron donative material is opened to expose the single crystalline (the drain portion 3) surface which is the electron donative surface, as in the case of this embodiment, it is possible to deposit Al on the single crystalline surface alone and to prevent deposition of Al on the insulating layer (SiO 2 layer) 10. A first embodiment of the present invention will be described below with reference to Fig. 13. Those reference numerals in Fig. 13 used previously in Figs. 2 through 12 represent similar or identical elements, therefore, description thereof is omitted. This embodiment is also manufactured by utilizing the SOI technology, as in the case of the aforementioned example. This embodiment differs from the example shown in Fig. 2 in that the under surface of the driving transistor 18 is shielded from light by utilizing an interconnection 53 and an electrode 54 for connecting the drain 3 to the transparent electrode 13 provided on the rear surface of the insulating layer 10. Thus, whereas the illumination light enters the device from above as viewed in the figures in the aforementioned two examples, the illumination light is incident on the device from below as viewed in Fig. 13 in this embodiment. This embodiment has advantages in that: (1) The parasitic capacitance of the interconnection 5 is reduced, making a high-speed transmission of signals possible. (2) The magnitude of the shoulders of the upper structure (including the driving transistor, the interconnection and so on) of the insulating layer 10 is reduced, facilitating the adhesion of the transparent substrate 1 and improving the positioning accuracy and gate accuracy. (3) Whereas the light blocking metal layer is provided in the aforementioned two examples, provision of such a metal layer is not required in this embodiment. This simplifies the manufacturing process. Still another embodiment of the present invention will be described below with reference to Fig. 14. Since reference numerals in this figure were used previously in Figs. 2 through 13 and represent similar or identical elements, description thereof is omitted. This embodiment is also manufactured by utilizing the SOI technology, as in the case of the aforementioned embodiment. This embodiment differs from the embodiment shown in Fig. 13 in that an additional capacitance is connected to the drain portion 3 by means of transparent electrodes 55 and 57. The liquid crystal layer 8 is characterized in that the capacitance value thereof varies with time by the application of a voltage. Thus, even when a desired voltage is applied to the liquid crystal layer 8 from the drain portion 3, if the gate portion 4 is off and the liquid crystal portion 8 is thus in a floating state, the voltage applied to the liquid crystal layer 8 varies due to the variable capacitance thereof, adversely affecting the image quality. The voltage also varies through the parasitic capacitance by the signal voltage applied to the adjacent cells. This problem may be solved by providing an additional capacitance sufficiently larger than the capacitance of the liquid crystal layer 3 and the parasitic capacitance by the interconnections on the drain portion 3. In this embodiment display of high-quality images is achieved by providing such an additional capacitance on the insulating layer 10. That is, in this embodiment, the additional capacitance is formed by sequentially laminating the transparent electrode 57, an insulating layer 56 and the transparent electrode 55 on the insulating layer 10 in that order. The insulating layer 56 may be a SiO 2 or SiN film. In both of the above-described embodiments, the transparent substrate 1 is provided and adhered by the adhesive layer 9. However, the transparent substrate 1 may be eliminated and only a resin layer made of, for example, an acrylic resin, polycarbonate, polyethylene or polyvinyl chloride or a resin layer made of a substance other than those may be provided if there is no problem in terms of an optical image display or if a sufficient protection of the image display device from an external force can otherwise be obtained. The transparent substrate 1 may be made of an inorganic material, such as glass or quartz glass, a resin, such as an acrylic resin, polycarbonate resin or any other plastic, or a combination of the inorganic material and the resin. As will be understood from the foregoing description, in an image display device embodying the present invention, the transistor and the interconnection layer therefor are formed on one surface of the insulating layer, while the liquid crystal voltage applying electrode for applying a voltage to the liquid crystal is formed on the other surface of the insulating layer, and one of the major electrode portions of the transistor and the liquid crystal voltage applying electrode are connected to each other by an electrode via the opening in the insulating layer. Consequently, the liquid crystal voltage applying electrode can be provided on the flat surface of the insulating layer, making the electric field applied to the liquid crystal layer uniform. This allows the stable operation to be maintained. Even if the pixel size is reduced, the magnitude of the shoulders does not increase. This makes the structure suitable for use as a fine cell structure. Furthermore, since the light-blocking layer can be provided close to the upper surface of the transistor, cross-talk caused by light leakage from among the adjacent pixels can be improved, increasing the aperture ratio and S/N ratio. In the aforementioned image display device, when the electrode for connecting the major electrode portion of the transistor to the liquid crystal voltage applying electrode is embedded in the opening in the insulating layer, the connecting electrode does not generate irregularities on the surface of the insulating layer. This makes the electric field applied to the liquid crystal layer more uniform, making stable operation possible. In the aforementioned image display device, when the electrode for connecting the major electrode portion of the transistor to the liquid crystal voltage applying electrode is formed on the other surface of the insulating layer so that it shields the transistor, the parasitic capacitance of the interconnection is reduced, and a high-speed transmission of signals is thus achieved. Also, since it is not necessary for another light-blocking layer to be formed, the manufacturing process is simplified, and the magnitude of the shoulders of the upper structure (including the driving transistor, the interconnections and so on) of the insulating layer is reduced. This makes adhesion of the transparent substrate easy and increases the positioning accuracy and gate accuracy. In the aforementioned image display device, when the first transparent electrode is connected to the major electrode of the transistor while the second transparent electrode is formed on the first transparent electrode with the insulating layer therebetween, a capacitance larger than that of the liquid crystal layer or that of the interconnections can be added to restrict variations in the voltage due to the variable capacitance characteristics and parasitic capacitance of the liquid crystal. Furthermore, the pixel driving thin-film transistor and the driving interconnection therefor are provided on one surface of the insulating film while the display electrode connected to the drain region of the pixel thin-film transistor is provided on the other surface thereof. Consequently, the deflection of the voltage of the display electrode due to cross-talk can be reduced, and the display quality of the liquid crystal display device can thus be improved. The invention described above in the context of the preferred embodiments shown in the accompanying drawings is not to be so limited but is rather to be constructed broadly within the scope set out in the appended claims.

Claims: A liquid crystal image display device comprising first and second electrode bearing substrates (1-14,15-17) located on opposite sides of a layer (8) of liquid crystal material with their electrode bearing surfaces arranged facing one another, said first electrode bearing substrate (1-14) having a voltage applying transparent electrode (13) on the surface of one side of an insulating layer (10) and a thin-film transistor (2-4) on the other side of said insulating layer (10), said transparent electrode (13) being connected to one (3) of two major electrodes (2,3) of said thin film transistor (2-4) via a contact hole or opening (11) in said insulating layer (10), the other one (2) of the two major electrodes (2,3) of said thin-film transistor (2-4) being connected to an interconnection layer (5) on said other side of said insulating layer (10); characterised by: a light-shielding electrode (54), also on the surface of said one side of said insulating layer (10), extending across said thin-film transistor (2-4) to shield light therefrom, arranged between said one (3) of the two major electrodes (2,3) of said thin film transistor (2-4) and said transparent electrode (13). A device according to claim 1 wherein said light-shielding electrode (54) and said one (3) of the two major electrodes (2,3) of said thin film transistor (2-4) are interconnected by an interconnection member (53) wholly embedded in said contact hole or opening (11) in said insulating layer (10). A device according to either preceding claim having: a second transparent electrode (57), on said other side of said insulating layer (10), connected to said one (3) of the two major electrodes (2,3) of said thin film transistor (2-4), arranged opposite said voltage applying transparent electrode (13); and a third transparent electrode (55) arranged opposite and spaced from said second transparent electrode (57) by a second insulating layer (56) on said other side of said insulating layer (10). A device according to any preceding claim having a protective transparent substrate (1) affixed on said other side of said insulating layer (10) by an adhesive layer (9). A device according to claim 4 wherein said transparent substrate (1) is of inorganic material. A device according to claim 5 wherein said transparent substrate (1) is of glass or quartz glass. A device according to claim 4 wherein said transparent substrate (1) is of organic material. A device according to claim 7 wherein said transparent substrate (1) is of acrylic resin, polycarbonate resin, or other resin, or plastic. A device according to claim 4 wherein said transparent substrate (1) is of a material that is a combination of inorganic material and resin. A device according to any of claims 1 to 3 comprising a resin layer on said other side of said insulating layer (10). A device according to claim 10 wherein said resin layer is of acrylic resin, polycarbonate, polyethylene or polyvinyl chloride. A method of manufacturing the image display device of claim 1 comprising the steps of: providing a first substrate base (25) by anodising the surface of a base (21) of single crystal silicon to form a porous layer (22), forming an epitaxial layer (23) of single crystal silicon on said porous layer (22) and forming a silicon oxide film (24) on the surface of said epitaxial layer (23); providing a second substrate base (26) by forming a nitrogen-containing silicon film (28) on the surface of a base (27) of single crystal silicon and forming a silicon oxide film (29) on said nitrogen containing silicon film (28); laying said oxide films (24,29) one upon the other and applying heat to couple said first and second substrate bases (25,26) together; removing said porous layer (22); removing part of said epitaxial layer (23) to leave a transistor forming region thereof; forming a thin-film transistor (2-4) at said transistor forming region of said epitaxial layer (23); forming an interconnection layer (5) in contact with one (2) of the two major electrodes (2,3) of said thin film transistor (2-4); removing said base (27) of single crystal silicon of said second substrate base (26); forming an opening (11) in said nitrogen-containing silicon film (28) and said silicon oxide films (24,29;10) exposing the other one (3) of the two major electrodes (2,3) of said thin-film transistor (2-4); forming on the surface of said nitrogen-containing silicon film (28) a light shielding electrode (54) extending across said thin-film transistor (2-4) to shield light therefrom, which light shielding electrode (54) is interconnected to said other one (3) of the two major electrodes (2,3) of said thin film transistor (2-4); forming on the surface of said nitrogen-containing silicon film (28), and on the surface of said light shielding electrode (54), a transparent electrode (13); forming an insulating layer (14) on said transparent electrode (13); providing an electrode bearing substrate (15-17) and arranging it with its electrode bearing surface facing said transparent electrode (13); and introducing liquid crystal material into the space between said electrode bearing substrate (15-17) and said transparent electrode (13) to form a liquid crystal layer (8) therebetween. A method according to claim 12 wherein an embedded interconnection member (53) is formed in said opening (11) of nitrogen-containing silicon and silicon oxide films (28,10) prior to said step of forming said light shielding electrode (54). A method according to claim 13, wherein said interconnection member (53) embedded in said hole or opening (11) is formed by a CVD process. A method according to claim 14, wherein said CVD process uses alkyl aluminium halide. A method according to any of claims 12 to 16, wherein said heating is performed at a temperature of 600°C or above. A method according to any of claims 12 to 16, wherein said heating is performed in an oxygen, nitrogen, hydrogen or diluted gas atmosphere. A method according to any of claims 12 to 17, wherein said first and second substrate bases (25,26) are washed using a mixture of sulphuric acid and hydrogen peroxide, a mixture of hydrochloric acid and hydrogen peroxide, hydrofluoric acid, a mixture of hydrofluoric acid and hydrogen peroxide, an aqueous ammonia solution, or a pure water prior to said step of laying said silicon oxide films (24,29) one upon the other. A method according to any of claims 12 to 18, where said single crystal silicon on said second base is removed using a solution containing hydrofluoric acid. A method according to any of claims 12 to 19, wherein said porous layer (22) is formed using hydrofluoric acid, buffered hydrofluoric acid, or a mixture containing at least two of hydrofluoric acid, buffered hydrofluoric acid, alcohol and hydrogen peroxide. An electrode bearing substrate for use in the liquid crystal image display device of claim 1 comprising electrode bearing substrates (1-14,15-17) located on opposite sides of a layer (8) of liquid crystal material with their electrode bearing surfaces arranged facing one another, said electrode bearing substrate (1-14) having a voltage applying transparent electrode (13) on the surface of one side of an insulating layer (10) and a thin-film transistor (2-4) on the other side of said insulating layer (10), said transparent electrode (13) being connected to one (3) of two major electrodes (2,3) of said thin film transistor (2-4) via a contact hole or opening (11) in said insulating layer (10), the other one (2) of the two major electrodes (2,3) of said thin-film transistor (2-4) being connected to an interconnection layer (5) on said other side of said insulating layer (10); characterised by: a light-shielding electrode (54), also on the surface of said one side of said insulating layer (10), extending across said thin-film transistor (2-4) to shield light therefrom, arranged between said one (3) of the two major electrodes (2,3) of said thin film transistor (2-4) and said transparent electrode (13).

Inventors: KONDO SHIGEKI, KOUCHI TETSUNOBU, MIYAWAKI MAMORU, NAKAMURA YOSHIO, KONDO, SHIGEKI, KOUCHI, TETSUNOBU, MIYAWAKI, MAMORU, NAKAMURA, YOSHIO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: G02F1
IPC codes: G02F1, H01L21