Method of forming a multilayer wiring structure on a semiconductor device

Abstract: In a process for manufacturing a semiconductor device having a multi-layer wiring structure, a silicon oxide film (8) is deposited on the surface of second level wiring conductors (7) formed on a power supply layer (5,6) for electroplating, and then, the deposited silicon oxide film is etched back so that the silicon oxide film (8) remains only on the side surfaces of the second level wiring conductors (7). Thereafter, the power supply (5,6) layer is removed by the sputter etching, and the silicon oxide film (8) is etch-removed together with the metal deposit adhered to the surface of the silicon oxide film (8) at the time of the sputter etching.

Description: Background of the Invention Field of the invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of forming a multi-layer wiring structure in the process for manufacturing a semiconductor device. Description of related art In one typical conventional method for manufacturing a semiconductor device having a multi-layer wiring structure, a first level level wiring conductor is formed on a silicon oxide film formed on a silicon substrate, and the first level level wiring conductor is coated with an interlayer insulator film having a planarized upper surface. A contact hole is formed in the interlayer insulator film at a positioned of the first level wiring conductor. Thereafter, a power supply layer for electroplating is formed to cover all exposed surfaces. Then, a photoresist layer is deposited on the power supply layer, and then, patterned so as to form grooves for formation of a second level wiring conductor. Some of the grooves is composed to include the contact hole. Then, a second level metal layer is deposited on the power supply layer by an electroplating process using the patterned photoresist layer as a mask. Thereafter, the photoresist layer is removed so as to form second level wiring conductors, and then, the power supply layer is removed by a sputter etching using the second level wiring conductors as a mask. In the above mentioned conventional method for manufacturing a semiconductor device, after the second level wiring conductor layer is formed by the electroplating, the sputter etching is performed in order to remove an unnecessary portion of the power supply layer for electroplating. In this process, a portion of a removed metal of the power supply layer is deposited on side surfaces of the second level wiring conductors. A portion of the removed metal deposit adhered to the side surfaces of the second level wiring conductors peels off from the side surfaces of the second level wiring conductors in succeeding processes. As a result, adjacent second level wiring conductors are often short-circuited, with the result that the fabrication yield and the reliability of the products falls down. A method of manufacturing a semiconductor device having a multi-layer wiring and a power supply layer, and using an electroplating process, is known from EP-A-0 405 659. Summary of the Invention Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a method of manufacturing a semiconductor device, which method is capable of preventing short-circuiting of adjacent second level wiring conductors so that the fabrication yield and the reliability of the products can be improved. The above and other objects of the present invention are achieved by the method according to claim 1, of manufacturing a semiconductor device having a multi-layer wiring structure. including the steps of forming a power supply layer for electroplating on an interlayer insulator layer, forming a patterned second level wiring conductor on said power supply layer, depositing an insulator film on the surface of said second layer wiring conductor, etching back said insulator film so that said insulator film remains only on the side surfaces of said second level wiring conductor, characterised by including the further steps of removing said power supply layer by etching using said remaining insulator film and said second level wiring conductor as a mask, and etch-removing said remaining insulator film. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the inventions with reference to the accompanying drawings. Brief Description of the Drawings Figures 1A to 1F are sectional views of a semiconductor device, for illustrating the process of the first embodiment of the present invention; and Figure 2 is a sectional view of at semiconductor device, for illustrating the process of the second embodiment of the present invention. Description of the Preferred embodiments Referring to Figures 1A to 1F, there are shown sectional views of a semiconductor device, for illustrating the process of the first embodiment of the present invention. As shown in Figure 1A, an aluminum layer is deposited on a silicon oxide film 2 formed on a silicon substrate 1, and the deposited aluminum layer is patterned so as to form a plurality of lower level wiring conductors 3 having a width of 2µm and a thickness of 0.5µm. Furthermore, an organic film such as a polyimide film mixed with powdered silica is deposited on a surface of the silicon oxide film 2 including a surface of the wiring conductors 3 by means of a coating process, so as to form an interlayer insulator film 4 having a planarized upper surface. Then, the interlayer insulator film 4 is selectively perforated so as to form a contact hole 10 on one of the wiring conductors 3. Thereafter, a barrier metal layer 5 such as a Ti-W layer and a gold layer 6 having a thickness of 0.1µm, respectively, are formed in the named order on a surface of the interlayer insulator film 4 including a surface of the contact hole 10 by sputtering, so that a power supply layer for electroplating is formed. Next, as shown in Figure 1B, a photoresist layer 9 is deposited on the gold layer 6, and then, patterned so as to form grooves for formation of a wiring conductor pattern, some of the grooves being composed to include the contact hole 10. Then, a gold layer is deposited on the power supply layer (5+6) by an electroplating process using the patterned photoresist layer 9 as a mask. Thereafter, as shown in Figure 1C, the photoresist layer 9 is removed so as to form upper level wiring conductors 7. Furthermore, as shown in Figure 1D, a silicon oxide film 8 having a thickness of 0.2µm is deposited on a surface of the power supply layer (5+6) including a surface of the wiring conductors 7, by a plasma CVD process. Then, as shown in Figure 1E, the deposited silicon oxide film 8 is etched back by an anisotropic etching, so that the silicon oxide film 8 excluding a portion deposited on side surfaces of the wiring conductors 7 is removed. Thereafter, the gold layer 6 and the barrier metal layer 5 are removed in the named order by a sputter etching using an inert gas such as Ar, using the wiring conductors 7 and the remaining silicon oxide film 8 as a mask. In this process, it is in some cases that a portion of the removed metal is adhered to the surfaces of the silicon oxide film 8 remaining on the side surfaces of the wiring conductors 7. Thereafter, as shown in Figure 1F, the remaining silicon oxide film 8 to which the metal deposit may be adhered in some cases, is etch-removed by use of a dilute hydrofluoric acid. In the above mentioned embodiment, in place of the silicon oxide film 8, a silicon nitride film can be deposited by a plasma CVD process. This modification is advantageous in that the silicon nitride film remaining on only the side surfaces of the wiring conductors 7 can be easily removed together with the metal deposit adhered thereto, by an isotropic dry etching using CF 4 gas or others. In addition, in place of the gold layer deposited by the plating, the wiring conductors 7 can be formed of a copper layer deposited by the plating. Figure 2 is a sectional view of a semiconductor chip for illustrating a second embodiment of the method of the present invention. The process of the second embodiment is the same as that of the first embodiment until the step shown in Figure 1E. After the gold layer 6 and the barrier metal layer 5 are removed in the named order by a sputter etching using the upper level wiring conductors 7 and the remaining silicon oxide film 8 as a mask as shown in Figure 1E, the gold layer 6 is wet-etched by aqua regia, and the barrier metal layer 5 is wet-etched by H 2 O 2 solution, as shown in Figure 2, so that a most portion of the metal deposit adhered to the silicon oxide film 8 is etch-removed. Thereafter, the remaining silicon oxide film 8 is removed by a wet etching (dilute hydrofluoric acid or the like), together with the metal deposit adhered thereto. The metal deposit produced by the sputter etching can be removed more completely than the first embodiment. As seen from the above, the method of the present invention is characterized in that after an insulator film is formed on side surfaces of the upper level wiring conductor formed by the electroplating process, the power supply layer for electroplating is removed by the sputter etching, and thereafter, the insulator film on which the metal deposit produced by the sputter etching may be deposited, is etch-removed. Namely, the metal deposit can be removed at the same time as the insulator film is removed. Therefore, it is possible to prevent short-circuiting of adjacent wiring conductors which is caused because the metal deposit peels off in succeeding processes. Accordingly, the fabrication yield and the reliability can be elevated. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A method of manufacturing a semiconductor device having a multi-layer wiring structure, including the steps of forming a power supply layer (5+6) for electroplating on an interlayer insulator layer (4), forming a patterned second level wiring conductor (7) on said power supply layer by an electroplating process, depositing an insulator film (8) on the thus obtained semiconductor device surface, etching back said insulator film (8) so that said insulator film (8) remains only on the side surfaces of said second level wiring conductor (7), characterised by including the further steps of removing said power supply (5+6) layer by etching using said remaining insulator film (8) and said second level wiring conductor (7) as a mask, and etch-removing said remaining insulator film (8). A method according to Claim 1, wherein said interlayer insulator layer (4) is formed on a semiconductor substrate (1); said pattered second level wiring conductor (7) is formed by depositing on said power supply layer (5+6) a patterned photoresist layer (9) having at least one groove; depositing a metal layer on said power supply layer (5+6) by an electroplating process using said patterned photoresist layer (9) as a mask so that said wiring conductor is formed within the or each of said grooves and removing said photoresist layer (9); and wherein the upper surface of said power supply layer (5+6) is exposed on etching back said insulator film (8). A method claimed in Claim 2 wherein after formation of said interlayer insulator layer (4), a contact hole (10) in alignment with a lower level wiring conductor (3) formed under said interlayer insulator layer (4) is selectively formed in said interlayer insulator layer (4) and then said patterned photoresist layer (9) having a plurality of grooves is deposited on said power supply layer (5+6) in such a manner that at least one of said grooves is in alignment with said contact hole (10). A method claimed in any one of the preceding claims wherein said deposited insulator film (8) is etched back by an anisotropic etching, so that said deposited insulator film excluding a portion deposited on side surfaces of said wiring conductors (7) is removed. A method claimed in any preceding claim wherein said power supply layer is formed of a barrier metal layer (5) deposited on said interlayer insulator film (4) and a gold layer (6) deposited on said barrier metal layer (5), and wherein said power supply layer is removed by removing said gold layer (6) and said barrier metal layer (5) in the named order by a sputter etching using an inert gas such as Ar, using said wiring conductor (7) and the remaining deposited insulator film (8) as a mask. A method claimed in any preceding claim wherein said deposited insulator film (8) is formed of a silicon oxide film, and said etch-removal of said remaining deposited insulator film formed of the silicon oxide film is performed by a dilute hydrofluoric acid. A method claimed in any one of Claims 1 to 5 wherein said deposited insulator film (8) is formed of a silicon nitride film, and said etch-removal of said remaining deposited insulator film formed of the silicon nitride film is performed by an isotropic dry etching. A method claimed in any of the Claims 1 to 4 wherein said power supply layer is formed of a barrier metal layer (5) deposited on said interlayer insulator film (4) and a gold layer (6) deposited on said barrier metal layer, and wherein after said power supply layer is removed using said wiring conductor (7) and the remaining deposited insulator film as a mask, said gold layer (6) is wet-etched by aqua regia, and said barrier metal layer (5) is wet-etched by H 2 O 2 solution, so that a most portion of the metal deposit which might be adhered to the remaining deposited insulator film is etch-removed, and thereafter, the remaining deposited insulator film is removed by a wet etching. A method according to Claim 3, wherein the interlayer insulator layer (4) has a planarized upper surface.

Inventors: INABA TAKASHI, INABA, TAKASHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L23