Semiconductor memory device

Abstract: A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices and, specifically, to a clock synchronized type semiconductor memory device which operates in synchronization with externally applied clock signals. More specifically, the present invention relates to a structure of a semiconductor memory device containing a cache, in which a dynamic random access memory (DRAM) having a large storage capacity serving as a main memory, and a static random access memory (SRAM) having small storage capacity serving as a cache memory are integrated on the same semiconductor chip. Description of the Background Art Historical Review on Memory Environment in a Conventional Data Processing System (i) Usage of standard DRAM as a main memory Operation speed of recent 16-bit or 32-bit microprocessing unit (MPU) has been so much increased as to have operation clock frequency as high as 25MHz or higher. In a data processing system, a standard DRAM (Dynamic Random Access Memory) is often used as a main memory having large storage capacity, since cost per bit is low. Although access time in the standard DRAM has been reduced, the speed of operation of the MPU has been increased much faster than that of the standard DRAM. Consequently, in a data processing system using the standard DRAM as a main memory, increase of wait state is inevitable. The gap in speed of operation between MPU and the standard DRAM is inevitable because the standard DRAM has the following characteristics. (1) A row address and a column address are time divisionally multiplexed and applied to the same address pin terminals. The row address is taken in the device at a falling edge of a row address strobe signal/RAS. The column address is taken in the device at a falling edge of a column address strobe signal/CAS. The row address strobe signal/RAS defines start of a memory cycle and activates row selecting circuitry. The column address strobe signal/CAS activates column selecting circuitry. Since a prescribed time period called "RAS-CAS delay time (tRCD)" is necessary from the time the signal/RAS is set to an active state to the time the signal/CAS is set to the active state, there is a limit in reducing the access time, namely, there is a limit derived from address multiplexing. (2) When the row address strobe signal/RAS is once raised to set the DRAM to a standby state, the row address strobe signal/RAS cannot fall to "L" again until a time period called a RAS precharge time (tRP) has lapsed. The RAS precharge time is necessary for surely precharging various signal lines in the DRAM to predetermined potentials. Due to the RAS precharge time TRP, the cycle time of DRAM cannot be reduced. In addition, when the cycle time of the DRAM is reduced, the number of charging/discharging of signal lines in the DRAM is increased, which increases current consumption. (3) The higher speed of operation of the DRAM can be realized by circuit technique such as improvement of layout, increase of degree of integration of circuits, development in process technique and by applicational improvement such as improvement in the method of driving. However, the speed of operation of the MPU is increased at much faster rate than DRAM. The speed of operation of semiconductor memories is hierarchical. For example, there are high speed bipolar RAMs using bipolar transistors such as ECLRAMs (Emitter Coupled RAM) and Static RAM, and relatively low speed DRAMs using MOS transistors (insulated gate type field effect transistors). It is very difficult to expect the operation speed (cycle time) as fast as several tens ns (nano seconds) in a standard DRAM formed of MOS transistors. There have been various applicational improvements to stop the gap between speed of operations of the MPU and the standard DRAM. Such improvements mainly comprise the following two approaches. (1) Use of high speed mode of the DRAM and interleave method (2) External provision of a high speed cache memory (SRAM). The first approach (1) includes a method of using a high speed mode such as a static column mode or a page mode, and a method of combining the high speed mode and the interleave method. In the static column mode, one word line (one row) is selected, and thereafter only the column address is changed successively, to successively access memory cells of this row. In the page mode, one word line is selected, and then column addresses are successively taken by toggling the signal/CAS to successively access memory cells connected to the selected one word line. In either of these modes, memory cells can be accessed without toggling the signal/RAS, enabling higher speed accessing than the normal access using the signals/RAS and/CAS. In the interleave method, a plurality of memories are provided in parallel to a data bus, and by alternately or successively accessing the plurality of memories, the access time is reduced in effect. The use of high speed mode of the DRAM and combination of the high speed mode and the interleave method have been known as a method of using the standard DRAM as a high speed DRAM in a simple and relatively effective manner. The second approach (2) has been widely used in a main frame art. A high speed cache memory is expensive. However, in the field of personal computers in which high performance as well as low cost are desired, this approach is employed in some parts of the field with a sacrifice of cost. There are three possible ways to provide the high speed cache memory. Namely, (a) the high speed cache memory is contained in the MPU itself; (b) the high speed cache memory is provided outside the MPU; and (c) the high speed cache memory is not separately provided but the high speed mode contained in the standard DRAM is used as a cache (the high speed mode is used as a pseudo cache memory). When a cache hit occurs, the standard DRAM is accessed in the high speed mode, and at the time of a cache miss, the standard DRAM is accessed in the normal mode. The above mentioned three ways (a) to (c) have been employed in the data processing systems in some way or other. In most MPU systems, the memories are organized in a bank structure and interleaving is carried out on bank by bank basis in order to conceal the RAS precharge time (TRP) which is inevitable in the DRAM, in view of cost. By this method, the cycle time of the DRAM can be substantially one half that of the specification value. The method of interleave is effective only when memories are sequentially accessed. When the same memory bank is to be continuously accessed, it is ineffective. Further, substantial improvement of the access time of the DRAM itself cannot be realized. The minimum unit of the memory must be at least 2 banks. When the high speed mode such as the page mode or the static column mode is used, the access time can be reduced effectively only when the MPU successively accesses a certain page (data of a designated one row). This method is effective to some extent when the number of banks is comparatively large, for example 2 to 4, since different rows can be accessed in different banks. When the data of the memory requested by the MPU does not exist in the given page, it is called a "miss hit" (cache miss). Normally, a group of data are stored in adjacent addresses or sequential addresses. In the high speed mode, a row address, which is one half of the addresses, has been already designated, and therefore possibility of "miss hit" is high. When the number of banks becomes as large as 30 to 40, data of different pages can be stored in different banks, and therefore the "miss hit" rate is remarkably reduced. However, it is not practical to provide 30 to 40 banks in a data processing system. In addition, if a "miss hit" occurs, the signal/RAS is raised and the DRAM must be returned to the precharge cycle in order to re-select the row address, which sacrifices the characteristic of the bank structure. In the above described second method (2), a high speed cache memory is provided between the MPU and the standard DRAM. In this case, the standard DRAM may have relatively low speed of operation. Standard DRAMs having storage capacities as large as 4M bits or 16M bits have come to be used. In a small system such as a personal computer, the main memory thereof can be formed by one or several chips of standard DRAMs. External provision of the high speed cache memory is not so effective in such a small system in which the main memory can be formed of one standard DRAM. If the standard DRAM is used as the main memory, the data transfer speed between the high speed cache memory and the main memory is limited by the number of data input/output terminals of the standard DRAM, which constitutes a bottleneck in increasing the speed of the system. When the high speed mode is used as a pseudo cache memory, the speed of operation thereof is slower than the high speed cache memory, and it is difficult to realize the desired system performance. (ii) Consideration on a conventional cache containing DRAM Provision of the high speed cache memory (SRAM) in the DRAM is proposed as a method of forming a relatively inexpensive and small system, which can solve the problem of sacrifice of system performance when the interleave method or the high speed operation mode is used. More specifically, a single chip memory having a hierarchical structure of a DRAM serving as a main memory and a SRAM serving as a cache memory has been conceived. The one-chip memory having such a hierarchical structure is called a cache DRAM (CDRAM). The CDRAM will be described with reference to Figs. 1 through 4. Fig. 1 shows a structure of a main portion of a conventional standard 1 megabit DRAM. As shown in Fig. 1, the DRAM comprises a memory cell array 500 including a plurality of memory cells MC arranged in a matrix of rows and columns. A row of memory cells are connected to one word line WL. A column of memory cells MC are connected to one column line CL. Normally, the column line CL is formed by a pair of bit lines. A memory cell MC is positioned at a crossing of one of the pair of bit lines and one word line WL. In a 1M DRAM, the memory cells MC are arranged in a matrix of 1024 rows x 1024 columns. Namely, the memory cell array 500 includes 1024 word lines WLs and 1024 column lines CLs (1024 pairs of bit lines). The DRAM further comprises a row decoder 502 which decodes an externally applied row address (not shown) for selecting a corresponding row of the memory cell array 500; a sense amplifier which detects and amplifies data of the memory cell connected to the word line selected by the row decoder 502; and a column decoder which decodes an externally applied column address (not shown) for selecting a corresponding column of the memory cell array 502. In Fig. 1, the sense amplifier and the column decoder are denoted by one block 504. If the DRAM has a x 1 bit structure in which input/output of data is effected bit by bit, one column line CL (a bit line pair) is selected by the column decoder. If the DRAM has a x 4 bit structure in which input/output of data is effected 4 bits by 4 bits, 4 column lines CL are selected by the column decoder. One sense amplifier is provided for each column line (bit line pair) CL in the block 504. In memory access for writing data to or reading data from the memory cell MC in the DRAM, the following operation is carried out. First, a row address is applied to the row decoder 502. The row decoder 502 decodes the row address and raises the potential of one word line WL in the memory cell array 500 to "H". Data of the 1024 bits of memory cells MC connected to the selected word line WL are transmitted to corresponding column lines CL. The data on the column lines CL are amplified by sense amplifiers included in the block 504. Selection of a memory cell to which the data is written or from which the data is read out of the memory cells connected to the selected word line WL is carried out by a column selection signal from the column decoder included in the block 504. The column decoder decodes column address signals (more accurately, internal column address signals), and generates a column selecting signal for selecting the corresponding column in the memory cell array 500. In the above described high speed mode, column addresses are successively applied to the column decoder included in the block 504. In the static column mode operation, column addresses applied at predetermined time intervals are decoded as new column addresses by the column decoder, and the corresponding memory cell out of the memory cells connected to the selected word line WL is selected by the column line CL. In the page mode, new column address is applied at every toggling of the signal /CAS, and the column decoder decodes the column address to select the corresponding column line. In this manner, one row of memory cells MC connected to the selected word line WL can be accessed at high speed by setting one word line WL at a selected state and by changing the column addresses only. Fig. 2 shows a general structure of a conventional 1M bit CDRAM. Referring to Fig. 2, the conventional CDRAM comprises, in addition to the components of the standard DRAM shown in Fig. 1, SRAM 506 and a transfer gate 508 for transferring data between one row of the memory cell array 500 of the DRAM and the SRAM 506. The SRAM includes a cache register provided corresponding to each column line CL of the memory cell array 500 so as to enable simultaneous storage of data of one row of the DRAM memory cell array 500. Therefore, 1024 cache registers are provided. The cache register is formed by a static memory cell (SRAM cell). In the structure of the CDRAM shown in Fig. 2, when a signal representing a cache hit is externally applied, the SRAM 506 is accessed, enabling access to the memory at high speed. At the time of a cache miss (miss hit), the DRAM portion is accessed. A CDRAM as described above having a DRAM of a large storage capacity and a high speed SRAM integrated on the same chip is disclosed in, for example, Japanese Patent Laying-Open Nos. 60-7690 and 62-38590. In the above described conventional CDRAM structure, column lines (bit line pairs) CL of the DRAM memory cell array 500 and column lines (bit line pairs) of the SRAM (cache memory) 506 are connected in one to one correspondence through a transfer gate 508. More specifically, in the above described conventional CDRAM structure, data of the memory cells connected to one word line WL in the DRAM memory cell array 500 and the data of the same number of SRAM cells as memory cells of one row of the memory cell array 500 are transferred bi-directionally and simultaneously, through the transfer gate 508. In this structure, the SRAM 506 is used as a cache memory and the DRAM is used as a main memory. The so called block size of the cache is considered to be the number of bits (memory cells) the contents of which are rewritten in one data transfer in SRAM 506. Therefore, the block size is the same as the number of memory cells which are physically coupled to one word line WL of DRAM memory cell array 500. As shown in Figs. 1 and 2, when 1024 memory cells are physically connected to one word line WL, the block size is 1024. Generally, when the block size becomes larger, the hit rate is increased. However, if the cache memory has the same size, the number of sets is reduced in inverse proportion to the block size, and therefore the hit rate is decreased. For example, when the cache size is 4K bits and the block size 1024, the number of sets is 4. However, if the block size is 32, the number of sets is 128. Therefore, in the conventional CDRAM structure, the block size is made too large, and the cache hit rate cannot be very much improved. A structure enabling reduction in block size is disclosed in, for example, Japanese Patent Laying-Open No. 1-146187. In this prior art, column lines (bit line pairs) of the DRAM array and the SRAM array are arranged in one to one correspondence, but they are divided into a plurality of blocks in the column direction. Selection of the block is carried out by a block decoder. At the time of a cache miss (miss hit), one block is selected by the block decoder. Data are transferred only between the selected DRAM block and the associated SRAM block. By this structure, the block size of the cache memory can be reduced to an appropriate size. However, there remains the following problem unsolved. Fig. 3 shows a standard array structure of a 1M bit DRAM array. In Fig. 3, the DRAM array is divided into 8 memory blocks DMB1 to DMB8. A row decoder 502 is commonly provided for the memory blocks DMB1 to DMB8 on one side in the longitudinal direction of the memory array. For each of the memory blocks DMB1 to DMB8, (sense amplifier + column decoder) blocks 504-1 to 504-8 are provided. Each of the memory blocks DMB1 to DMB8 has the capacity of 128K bits. In Fig. 3, one memory block DMB is shown to have 128 rows and 1024 columns, as an example. One column line CL includes a pair of bit lines BL, /BL. As shown in Fig. 3, when the DRAM memory cell array is divided into a plurality of blocks, one bit line BL (and/BL) becomes shorter. In data reading, charges stored in a capacitor (memory cell capacitor) in the memory cell are transmitted to a corresponding bit line BL (or/BL). At this time the amount of potential change generated on the bit line BL (or/BL) is proportional to the ratio Cs/Cb of the capacitance Cs of the memory cell capacitor to the capacitance Cb of the bit line BL (or/BL). If the bit line BL (or/BL) is made shorter, the bit line capacitance Cb can be reduced. Therefore, the amount of potential change generated on the bit line can be increased. In operation, sensing operation in the memory block (memory block DMB2 in Fig. 3) including the word line WL selected by the row decoder 502 is carried out only, and other blocks are kept in a standby state. Consequently, power consumption associated with charging/discharging of the bit lines during sensing operation can be reduced. When the above described partial activation type CDRAM is applied to the DRAM shown in Fig. 3, a SRAM register and a block decoder must be provided for each of the memory blocks DMB1 to DMB8, which significantly increases the chip area. In this structure, only SRAM cache registers corresponding to the selected block operate, and therefore, efficiency in using the SRAM cache registers is low. Further, the bit lines of the DRAM array and of the SRAM array are in one to one correspondence, as described above. When direct mapping method is employed as the method of mapping memories between the main memory and the cache memory, then the SRAM 506 is formed by 1024 cache registers arranged in one row, as shown in Fig. 2. In this case, the capacity of the SRAM cache is 1K bits. When 4 way set associative method is employed as the mapping method, the SRAM array 506 includes 4 rows of cache registers 506a to 506d as shown in Fig. 4. One of the 4 rows of cache registers 506a to 506d is selected by the selector 510 in accordance with a way address. In this case, the capacity of the SRAM cache is 4K bits. As described above, the method of memory cell mapping between the DRAM array and the cache memory is determined dependent on the internal structure on the chip. When the mapping method is to be changed, the cache size also must be changed. In both of the CDRAM structures described above, the bit lines of the DRAM array and the SRAM array are in one to one correspondence. Therefore, the column address of the DRAM array is inevitably the same as the column address of the SRAM array. Therefore, full associative method in which memory cells of the DRAM array are mapped to an arbitrary position of the SRAM array is impossible in principle. Another structure of a semiconductor memory device in which the DRAM and the SRAM are integrated on the same chip is disclosed in Japanese Patent Laying-Open No. 2-87392. In this prior art, the DRAM array and the SRAM array are connected through an internal common data bus. The internal common data bus is connected to an input/output buffer for inputting/outputting data to and from the outside of the device. Selected memory cells of the DRAM array and the SRAM array can be designated by separate addresses. However, in this structure of the prior art, data transfer between the DRAM array and the SRAM array is carried out by an internal common data bus, and therefore the number of bits which can be transferred at one time is limited by the number of internal data bus lines, which prevents high speed rewriting of the contents of the cache memory. Therefore, as in the above described structure in which the SRAM cache is provided outside the standard DRAM, the speed of data transfer between the DRAM array and the SRAM array becomes a bottleneck, preventing provision of a high speed cache memory system. (iii) Consideration on a general clock synchronized type semiconductor device for the problems of which the present invention includes the solution. A semiconductor memory device of an application specific IC (ASIC) or for pipe line usage operates in synchronization with an external clock signal such as a system clock. Operation mode of a semiconductor memory device is determined dependent on states of external control signals at rising or falling edge of the external clock signal. The external clock signal is applied to the semiconductor memory device no matter whether the semiconductor memory device is being accessed or not. In this structure, in response to the external clock signal, input buffers or the like receiving the external control signals, address signals and data operate. In view of power consumption, it is preferred not to apply the external clock signal to the semiconductor memory device when the semiconductor memory device is not accessed, or to elongate period of the external clock signal. Generally, a row address signal and the column address signal are applied multiplexed time divisionally to the DRAM. The row address signal and the column address signal are taken in the device in synchronization with the external clock signal. Therefore, when the conventional DRAM is operated in synchronization with the external clock signal, it takes long time to take the row address signal and the column address signal. Therefore, if low power consumption is given priority, the DRAM can not be operated at high speed. If the conventional semiconductor memory device is operated in synchronization with the external clock signal, the speed of operation is determined solely by the external clock signal. If the semiconductor memory device is to be used where low power consumption is given priority over the high speed operation with the speed defined by the external clock signal, the conventional clock synchronized type semiconductor memory device can not be used for such application. In a clock synchronized type semiconductor memory device, control signals and address signals are taken inside in synchronization with the clock signal. The control signals and address signals are taken inside by buffer circuits. Each buffer circuit is activated in synchronization with the clock signal and generates an internal signal corresponding to the applied external signal. In a standby state or the like, valid control signals and valid address signals are not applied. However, external clock signals are continuously applied, causing unnecessary operations of the buffer circuits. This prevents reduction in power consumption during standby state. If the cycle period of the external clock signal becomes shorter, the number of operations of the buffer circuits is increased, causing increase of power consumption during standby period. This is a serious problem in realizing low power consumption. (iv) Consideration on the problems in refreshing operation in a conventional RAM If the semiconductor memory device includes dynamic memory cells (DRAM cells), the DRAM cells must be periodically refreshed. The refresh mode of a DRAM generally includes an auto refresh mode and a self refresh mode, as shown in Figs. 5 and 6. Fig. 5 shows waveforms in the auto refresh operation. In the auto refresh mode, a chip select signal *CE is set to "H" and an external refresh designating signal *REF is set to "L". In response to a fall of the external refresh designating signal *REF, an internal control signal int. *RAS for driving row selecting circuitry falls to "L". In response to the internal control signal int. *RAS, a word line is selected in accordance with a refresh address generated from a built-in address counter, and memory cells connected to the selected word line are refreshed. In the auto refresh mode, the timing of refreshing the semiconductor memory device is determined by the externally applied refresh designating signal *REF. Therefore, whether or not refreshing is being carried out in the semiconductor memory device can be known outside the memory device. Fig. 6 shows waveforms in the self refresh operation. In the self refresh mode, the chip select signal *CE is set to "H" and the external refresh designating signal *REF is set to "L". When the external refresh designating signal *REF falls to "L", the external control signal int. *RAS is generated, and a word line is selected in accordance with the refresh address from the built-in address counter. Thereafter, sensing operation and rewriting of the memory cells connected to the selected word line are carried out, and the memory cells connected to the word line WL are refreshed. The first cycle of self refreshing is the same as that of auto refreshing. When the chip select signal *CE is at "H" and the refresh designating signal *REF is kept at "L" for a predetermined time period TF or longer, a refresh request signal is generated from a built-in timer. In response, the internal control signal int. *RAS is generated, the word line is selected and the memory cells connected to the selected word line are refreshed. This operation is repeated while the refresh designating signal *REF is at "L". In the refreshing operation in the self refresh mode, the timings of refreshing are determined by a timer contained in the semiconductor memory device. Therefore, timings of refreshing can not be known from the outside. Normally, data can not be externally accessed in the self refresh mode. Therefore, in the normal mode, self refreshing is not carried out. The self refresh mode is generally carried out at a standby for retaining the data. Different semiconductor chips have different upper limits of refresh period necessary for retaining data (see NIKKEI ELECTRONICS, April 6, 1987, p. 170, for example). Generally, a guaranteed value for retaining data is measured by testing the semiconductor memory device, and period of a timer defining the self refresh cycle is programmed in accordance with the guaranteed value, for carrying out self refreshing. When auto refresh mode and self refresh mode are selectively used, the guaranteed value for retaining data must be measured in order to determine the self refresh cycle. As shown in Fig. 6, in the self refresh mode, an operation similar to that in the auto refreshing is carried out in response to the external refresh designating signal *REF, and then refreshing operation in accordance with the timer is carried out. Therefore, in an accurate sense, the self refresh cycle means a cycle carried out after a lapse of a prescribed time period TF successive to the auto refreshing. In the self refresh cycle, the refresh timing is determined by the contained timer, as described above, and the timings of refreshing can not be known from the outside. Therefore, the self refresh cycle can not be used as a method of hidden refreshing, for example, in a normal operation mode. (v) Consideration on Array Arrangement in CDRAM and data transfer between CDRAM and MPU (burst mode) In a semiconductor memory device containing a DRAM array and a SRAM array, it is preferred to transfer data at high speed from the DRAM array to the SRAM array, so as to enable high speed operation. When data are transferred from the DRAM array to the SRAM array, a row (word line) is selected, data of the memory cells connected to the selected word line are detected and amplified, and then a column is selected in the DRAM array. Generally, a row address signal and a column address signal are applied multiplexed to the DRAM. Therefore, increase of the speed of data transfer from the DRAM array to the SRAM array is limited by this address multiplexing. In this case, it is possible to apply the row address and the column address simply in accordance with a non-multiplex method to the DRAM. However, in that case, the number of terminals for inputting DRAM addresses are increased significantly. When the number of terminals is increased, the chip size and the package size are increased, which is not preferable. In addition, data transfer from the DRAM array to the SRAM array must be done after detection and amplification of the memory cell data by the sense amplifiers. Therefore, data transfer from the DRAM array to the SRAM array can not be carried out at high speed. Further, some external operational processing units such as a CPU (Central Processing Unit) include a data transfer mode called a burst mode for carrying out data transfer at high speed. In the burst mode, a group of data blocks are transferred successively. A block of data is stored at successively adjacent address positions. Since the burst mode is a high speed data transfer mode, the data blocks are stored in the cache memory in the semiconductor memory device containing a cache. A semiconductor memory device containing a cache which can be easily connected to an operational processing unit having burst mode function has not yet been provided. In order to implement a CDRAM, DRAM array and SRAM array are integrated on the same semiconductor chip. The semiconductor chip is housed in a package. The layout of DRAM array and SRAM array as well as the geometrical figures thereof on the chip are determined by the geometrical figure and the physical dimensions of the housing package. DRAM array and its associated circuitry occupy a major area of a chip in CDRAM because DRAM is employed as a large storage capacity memory. Thus, the size and figure of DRAM array are substantially determined by the size and shape of the housing package. In order to efficiently use the chip area, SRAM array should be arranged or laid out on the chip efficiently. However, no consideration has been made on the configuration of SRAM array for implementing efficient chip area utilization and for housing CDRAM in a package of an arbitrary shape and size. An embodiment of the present invention provides a novel CDRAM with various operational functions and efficient chip layout. US Patent Specification No. 4970418 discloses optimising access times to computer memories using a finite state machine to adapt control pulses so that they are optimally matched to the memory elements being switched. In accordance with the present invention there is provided a semiconductor memory device as set out in claim 1. Another embodiment of the present invention provides a clock synchronized type semiconductor memory device in which power consumption at standby mode can be significantly reduced. A still further embodiment of the present invention provides a semiconductor memory device which operates at high speed even if the period of external clock signals is made longer. Yet another embodiment of the present invention provides a clock synchronized type semiconductor memory device which surely operates even if the period of the external clock signal is made longer or even if the external clock signal is generated intermittently. The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS This application includes a large number of the drawing figures, and we first classify the figures according to the embodiments for the reader's convenience. Figs. 1 through 6 are related to a conventional memory device. Figs. 7 through 31 represent an array arrangement of CDRAM of the present invention. Fig. 32 represents an overall view of a functional construction of the CDRAM. Fig 33 shows an overall construction of another CDRAM according to the present invention. Figs 34 through 46 are related to high speed and low power operation modes. Now, respective figures are described in the following. Fig. 1 shows a structure of a memory array in a conventional dynamic semiconductor memory device. Fig. 2 shows a structure of an array portion in a conventional semiconductor memory device containing a cache. Fig. 3 shows, as an example, a layout of the cache and the DRAM array in the conventional semiconductor memory device containing a cache. Fig. 4 shows a structure of a cache when 4 way set associative method is realized by the conventional semiconductor memory device containing a cache. Fig. 5 is a diagram of signal waveforms showing the operation in the automatic refreshing in the conventional semiconductor memory device. Fig. 6 is a diagram of signal waveforms showing self refreshing operation in the conventional semiconductor memory device. Fig. 7 schematically shows a structure of a memory array portion of the semiconductor memory device according to an embodiment of the invention. Fig. 8 shows detailed structure of the memory array shown in Fig. 7. Fig. 9 shows another example of the structure of the array arrangement in the semiconductor memory device according to an embodiment of the invention. Fig. 10 shows array arrangement of a semiconductor memory device containing a 4M bit DRAM and a 16K bit SRAM. Fig. 11 shows layout of DRAM array signal lines in one memory block of the semiconductor memory device shown in Fig. 10. Fig. 12 schematically shows structures of a bit line and a word line related to a memory cell of the DRAM shown in Fig. 10. Fig. 13 schematically shows a structure of a word line in the semiconductor memory device of Fig. 10. Fig. 14 shows layout of signal lines in the semiconductor memory device shown in Fig. 10. Fig. 15 shows a structure of an SRAM array of the semiconductor memory device shown in Fig. 5. Fig. 16 shows a structure of a conventional SRAM cell. Fig. 17 is a diagram of signal waveforms showing the operation of the SRAM cell shown in Fig. 16. Fig. 18 shows an example of a shape of a package for a semiconductor memory device containing a cache, and SRAM array and DRAM array arrangements contained therein. Fig. 19 shows problems of the general SRAM array. Fig. 20 is a diagram showing problems of the general SRAM array arrangement. Fig. 21 shows a principle of the SRAM array arrangement of the present invention. Fig. 22 shows, in comparison, the arrangement of the SRAM array of the present invention and the prior art arrangement. Fig. 23 shows a pattern layout of the SRAM cell shown in Fig. 21. Fig. 24 shows an SRAM array structure of the semiconductor memory device containing a cache in accordance with one embodiment of the present invention. Fig. 25 shows an example of a transfer gate circuit structure shown in Fig. 24. Fig. 26 shows an example of a specific structure of the selecting circuit shown in Fig. 25. Fig. 27 shows a structure of the SRAM array arrangement and a structure of a transfer gate circuit employed for that SRAM arrangement. Fig. 28 shows a specific structure of a transfer path from the SRAM array to the DRAM array of the transfer gate circuit shown in Fig. 27. Fig. 29 shows a detailed structure of the data transfer path from the DRAM array to the SRAM array of the transfer gate circuit shown in Fig. 27. Fig. 30 is a diagram of signal waveforms showing the operation of the transfer gate circuit shown in Figs. 27 to 29. Fig. 31 shows a pin arrangement and a package for containing the semiconductor memory device shown in Fig. 5. Fig. 32 shows functionally the whole structure of a semiconductor memory device containing a cache in accordance with one embodiment of the present invention. Fig. 33 functionally shows a structure of a semiconductor memory device in accordance with an embodiment of the present invention. Fig. 34 is a diagram of waveforms showing timings for taking DRAM addresses of the semiconductor memory device shown in Fig. 33. Fig. 35 shows effects provided by an address generating circuit included in the semiconductor memory device shown in Fig. 33. Fig. 36 shows another effect of the address generating circuit shown in Fig. 33. Fig. 37 shows a specific structure of the address generating circuit shown in Fig. 33. Fig. 38 shows a specific structure of a row address strobe signal generating circuit shown in Fig. 37. Fig. 39 shows a specific structure of a column address strobe signal generating circuit shown in Fig. 37. Fig. 40 shows a specific structure of a row address latch shown in Fig. 37. Fig. 41 shows a specific structure of a column address latch shown in Fig. 37. Fig. 42 shows a structure for setting timings for taking addresses of the circuit shown in Fig. 37. Fig. 43 illustrates high speed operation of the address generating circuit shown in Fig. 37. Fig. 44 illustrates an operation at a low power consumption mode of the address generating circuit shown in Fig. 37. Fig. 45 shows another structure of the column address strobe signal generating circuit shown in Fig. 37. Fig. 46 is a diagram of signal waveforms showing the operation of the circuit shown in Fig. 45. DESCRIPTION OF THE PREFERRED EMBODIMENTS Array arrangement of DRAM and SRAM arrays in CDRAM are described with reference to Figs. 7 through 23. In the arrangement, DRAM array includes a plurality of blocks to implement partial activation type operation. DRAM array includes local IO lines provided for respective blocks, and global IO lines each provided for blocks arranged in a row direction. SRAM array includes a plurality of SRAM cells arranged in a matrix. Data transfer of a plurality of bits between DRAM array and SRAM array is made through bidirectional transfer gate circuit and global IO lines. DRAM address and SRAM address can be set independently of each other. This arrangement allows first data transfer in any mapping scheme between DRAM array and SRAM array, as the blocks arranged in a column direction are simultaneously activated to communicate data with corresponding global IO lines through local IO lines. Now, detailed explanation will be made on specific DRAM and SRAM array arrangements. [Array Arrangement 1] Fig. 7 schematically shows a structure of a memory array portion of the semiconductor memory device in accordance with one embodiment of the present invention. Referring to Fig. 7, the semiconductor memory device comprises a DRAM array 1 including dynamic memory cells arranged in a matrix of rows and columns, a SRAM array 2 including static memory cells arranged in a matrix of rows and columns, and a bi-directional transfer gate circuit 3 for transferring data between DRAM array 1 and SRAM array 2. DRAM array 1 includes, assuming that it has storage capacity of 1M bit, 1024 word lines WL and 1024 pairs of bit lines BL and/BL. In Fig. 7, the DRAM bit line pair is denoted by DBL. DRAM array 1 is divided into a plurality of blocks along the row and column directions. In Fig. 7, DRAM array 1 is divided into 8 blocks MBi1 to MBi8 (i = 1 to 4) along the column direction and divided into 4 blocks MB1j to MB4j (j = 1 to 8) along the row direction, namely, it is divided into a total of 32 memory blocks as an example. 8 blocks Mbi1 to Mbi8 divided in the column direction constitute a row block 11. 4 blocks MB1j MB4j divided in the row direction constitute a column block 12. The memory blocks Mbi1 to Mbi8 included in one row block 11 share the same word line WL. The memory blocks MB1j to MB4j included in the same column block 12 shares a column selecting line CSL. A sense amplifier +IO block 13 is provided for each of the memory blocks MB11 to MB18. The structure of sense amplifier +IO block 13 will be described later. Column selecting line CSL simultaneously selects two columns (two pairs of bit lines). The semiconductor memory device further comprises a row decoder 14 responsive to an address for selecting a corresponding one row from DRAM array 1, and a column decoder 15 responsive to an applied column address for selecting one column selecting line CSL. Column blocks 12 are connected to the bi-directional transfer gate circuit 13 through two pairs of I/O lines 16a and 16b which are independent and separate from each other. SRAM array 2 includes 16 pairs of bit lines SBL which are connected to 16 pairs of I/O lines through the bi-directional transfer gates circuit 3, respectively. If SRAM array 2 has the capacity of 4K bit, it includes 16 pairs of bit lines and 256 word lines. Namely, in SRAM array 2, one row is comprised of 16 bits. SRAM array 2 is associated with a SRAM row decoder 21 for decoding a row address applied to the SRAM for selecting one row of SRAM array 2, a SRAM column decoder 22 for decoding an applied column address and for selecting a corresponding column in SRAM array 2, and a sense amplifier circuit 23 for amplifying and outputting data of the memory cell selected by SRAM row decoder 21 and SRAM column decoder 22 in data reading. The SRAM bit line pair SBL selected by SRAM column decoder 22 is connected to a common data bus, and input/output of data with the outside of the device is effected through an input/output buffer (not shown). Addresses applied to DRAM row decoder 14 and DRAM column decoder 15 are independent of addresses applied to SRAM row decoder 21 and SRAM column decoder 22, and are applied to mutually different address pin terminals from those for SRAM addresses. Data transfer operation of the semiconductor memory device shown in Fig. 7 will be briefly described. The operation of the DRAM portion will be described. First, in accordance with an externally applied row address, row decoder 14 carries out a row selecting operation and raises potential of one word line DWL to "H". Data are read to corresponding 1024 bit lines BL (or/BL) from memory cells connected to the selected one word line DWL. Then, sense amplifiers (included in the block 13) of row block 11 including the selected word line DWL are activated at one time, and differentially amplify potential difference between each bit line pair. Only one of the four row blocks 11 is activated to reduce power consumption associated with charging/discharging of the bit lines during the sensing operation. (This operation, in which only the row block including the selected row is activated, is called partial activation method.) In accordance with an externally applied column address, DRAM column decoder 15 carries out a column selecting operation and one column selecting line CSL is set to the selected state in each column block 12. The column selecting line CSL selects two pairs of bit lines, and the two pairs of bit lines are connected to two pairs of I/O lines 16a and 16b provided corresponding to the block. Consequently, a plurality of bits (16 bits in this embodiment) of data are read to the plurality of I/O line pairs 16a and 16b from DRAM array 1. Operation of the SRAM portion will be described. In accordance with an externally applied row address, SRAM row decoder 21 carries out row selecting operation and selects one word line from SRAM array 2. As described above, 16 bits of memory cells are connected to one SRAM word line. Therefore, by the selection of one word line, 16 static memory cells (SRAM cells) are connected to 16 pairs of bit lines SBL. After 16 bit data have been transmitted to I/O line pairs 16a and 16b for DRAM array 1, bi-directional transfer gate circuit 3 is turned ON, and 16 pairs of I/O lines 16a and 16b are connected to 16 pairs of bit lines SBL of the SRAM. Consequently, data which have been transmitted to 16 pairs of I/O lines 16a and 16b are written to the 16 bits of memory cells which have been selected in SRAM array 2. A sense amplifier circuit 23 and column decoder 22 provided in the SRAM are used to transfer data between the memory cells in SRAM array 2 and an input/output buffer for inputting/outputting external data. It is possible to set addresses for selecting SRAM cells in SRAM array 2 completely independent from addresses for selecting dynamic memory cells (DRAM cells) in DRAM array 1. Therefore, it is possible for the 16 bits of memory cells selected in DRAM array 1 to exchange data with memory cells at an arbitrary position (row) of SRAM array 2. Therefore, all of the direct mapping method, set associative method and full associative method can be realized without changing the structure, or the array arrangement. The principle of simultaneous transfer of 16 bits of data from the DRAM to the SRAM has been described. Simultaneous transfer of 16 bits of data from SRAM array 2 to DRAM array 1 is carried out in the same manner, except that the direction of data flow through the bi-directional transfer gate circuit 3 is reversed. The structure and operation of the semiconductor memory device containing a cache in accordance with the present invention will be described in detail. Fig. 8 shows a specific structure of a main portion of the semiconductor memory device shown in Fig. 7. Fig. 8 shows, as a representative, a portion related to data transfer of one memory block MBij of DRAM array. Referring to Fig. 8, DRAM memory block MBij includes a plurality of DRAM cells DMCs arranged in rows and columns. DRAM cell DMC includes one transistor Q0 and one capacitor C0. A constant potential Vgg is applied to one electrode (cell plate) of memory capacitor C0. The memory block MBij further includes DRAM word lines DWL to each of which one row of DRAM cells DMCs are connected, and DRAM bit line pairs DBL to each of which a column of DRAM cells DMCs are connected. The DRAM bit line pair DBL includes two bit lines BL and/BL. Signals complementary to each other are transmitted to bit lines BL and/BL. A DRAM cell DMC is arranged at a crossing of a DRAM word line DWL and a DRAM bit line pair DBL. A DRAM sense amplifier DSA for detecting and amplifying potential difference on a corresponding bit line pair is provided for each of the DRAM bit line pairs DBL. Operation of DRAM sense amplifier DSA is controlled by a sense amplifier activating circuit SAK which generates sense amplifier driving signals SAN and/SAP in response to sense amplifier activating signals SANE and/SAPE. DRAM sense amplifier DSA includes a first sense amplifier portion having p channel MOS transistors cross coupled for raising a bit line potential which is higher in a bit line pair to operational supply potential Vcc level in response to the signal /SAP, and a second sense amplifier portion having n channel MOS transistors cross coupled for discharging potential of a bit line in the pair which is at lower potential to, for example, the potential Vss of the ground potential level, in response to the signal SAN. The sense amplifier activating circuit SAK includes a sense amplifier activating transistor TR1 which is turned on in response to sense amplifier activating signal/SAPE for activating the first sense amplifier portion of DRAM sense amplifier DSA, and a sense amplifier activating transistor TR2 which is turned on in response to sense amplifier activating signal SANE for activating the second sense amplifier portion of DRAM sense amplifier DSA. Transistor TR1 is formed by a P channel MOS transistor, while the transistor TR2 is formed by an n channel MOS transistor. When turned on, transistor TR1 transmits a driving signal/SAP of the operational supply potential Vcc level to one supply node of each sense amplifier DSA. When turned on, transistor TR2 transmits a signal SAN of the potential Vss level to the other supply node of DRAM sense amplifier DSA. Between a signal line/SAP and the signal line SAN to which signals /SAP and SAN are output from sense amplifier activating circuit SAK, an equalize transistor TEQ is provided for equalizing both signal lines in response to an equalize designating signal EQ. Therefore, in the standby state, sense amplifier driving signal lines /SAP and SAN are precharged to an intermediate potential of (Vcc + Vss)/2. Signal lines and signals transmitted thereto are represented by the same reference characters. For each of the DRAM bit line pairs DBL, a precharge/equalize circuit PE which is activated in response to a precharge equalize signal EQ for precharging and equalizing bit lines of the corresponding bit line pair to a predetermined precharge potential Vb1 is provided. DRAM memory block MBij further comprises a column selecting gate CSG provided for each of the DRAM bit line pairs DBL and turned on in response to a signal potential on column selecting line CSL for connecting the corresponding DRAM bit line pair DBL to a local I/O line pair LIO. A column selecting line CSL is commonly provided for two pairs of DRAM bit lines, and therefore, two DRAM bit line pairs DBL are selected simultaneously. In order to receive data from the simultaneously selected two pairs of DRAM bit lines, two pairs of local I/O lines, that is, LIOa and LIOb are provided. Memory block MBij further comprises IO gates IOGa and IOGb responsive to a block activating signal BA for connecting the local I/O line pairs LIOa and LIOb to global I/O line pairs GIOa and GIOb, respectively. Column selecting line CSL extends in the row direction over one column block shown in Fig. 7, and global I/O line pair GIOa and GIOb also extend in the row direction over one column block. Local I/O line pair LIOa and LIOb extend only in the column direction in one memory block. I/O lines 16a and 16b in Fig. 7 correspond to local I/O line pair LIOa and LIOb, IO gates IOGa and IOGb, and global I/O line pairs GIOa and GIOb, respectively. SRAM comprises SRAM word lines SWL to each of which one row of SRAM cells SMCs are connected, SRAM bit line pairs SBL to each of which a column of SRAM cells SMCs are connected, and SRAM sense amplifiers SSA provided corresponding to the SRAM bit line pairs SBL for detecting and amplifying potential difference between the corresponding bit line pair. Bi-directional transfer gate circuit 3 comprises bi-directional transfer gates BTGa and BTGb provided between SRAM bit line pair SBL and global I/O line pair GIO. Both of bi-directional transfer gates BTGa and BTGb transfer data between SRAM bit line pair SBL and global I/O line pairs GIOa and GIOb in response to data transfer designating signals TSD and TDS. Data transfer designating signal TSD designates data transfer from SRAM portion to DRAM portion, while data transfer designating signal TDS designates data transfer from DRAM portion to SRAM portion. [Array Arrangement 2] Fig. 9 shows another example of the structure of the array arrangement. In the array arrangement of Fig. 9, an SRAM column decoder 22 is provided between DRAM array 1 and SRAM array 2. An input/output buffer 274 is connected to a column selected by SRAM column decoder 22 through an internal data line 251. In the structure shown in Fig. 9, the column selected by DRAM array 1 is connected to internal data line 251 through the bi-directional transfer gate. The connection between DRAM array 1 and internal data line 251 through bi-directional transfer gate circuit 3 may be effected by the column selecting gate provided in the bi-directional transfer gate by a column selecting signal from column decoder 15 of the DRAM. The connection between DRAM array 1 and internal data line 251 and connection between SRAM array 2 and internal data line 251 will be described in detail later. An address buffer 252 takes an address signal Aa applied externally in response to a chip enable signal E and generates an internal row·column address signal int-Aa for designating a row·column of DRAM array 1. Address buffer 252 takes an externally applied address signal Ac in response to chip enable signal E and generates an internal row·column address signal int-Ac for designating a row and a column of SRAM array 2. External address signal Aa for DRAM array and address signal Ac for SRAM array are applied to address buffer 252 through separate terminals. In this structure shown in Fig. 9, internal address int-Ac applied to the row decoder 21 and column decoder 22 of SRAM and internal address int-Aa applied to row decoder 14 and column decoder 15 of DRAM are applied through independent paths. Therefore, by this structure, addresses of memory cells in SRAM array 2 and DRAM array 1 can be independently designated. In the structure shown in Fig. 9, a SRAM column decoder 22 is provided between bi-directional transfer gate circuit 3 and SRAM array 2. SRAM column decoder 22 may be provided between bi-directional transfer gate circuit 3 and DRAM array 1. Alternatively, a corresponding I/O line pair of DRAM array may be selected from I/O line pairs 16a, 16b of DRAM array 1 by an output from DRAM column decoder 15 to connect the same to internal common data bus 251, and SRAM bit line pair SBL may be connected to internal data transmitting line 251 by SRAM column decoder 22. [Array Arrangement 3] Fig. 10 shows a layout of an array in a semiconductor memory device in accordance with another embodiment of the present invention. A CDRAM shown in Fig. 10 includes a 4M bit DRAM array and a 16K bit SRAM array. More specifically, the CDRAM of Fig. 10 includes 4 CDRAMs shown in Fig. 7 or 9. Referring to Fig. 10, the CDRAM includes four memory mats MM1, MM2, MM3 and MM4 each having the storage capacity of 1M bit. Each of the DRAM memory mats MM1 to MM4 includes a memory cell arrangement of 1024 rows (word lines) by 512 columns (bit line pairs). Each of the DRAM memory mats MM1 to MM4 is divided into 32 memory blocks MBs each having a structure of 128 columns (bit line pairs) x 256 rows (word lines). One memory mat MM is divided into 4 memory blocks in the row direction, and into 8 blocks in the column direction. As shown in Fig. 10, a 1M bit memory mat is divided into 8 blocks in the column direction and 4 blocks in the row direction, different from the arrangement of the DRAM of Fig. 7, in order to house the device in a rectangular package, as will be described later. Sense amplifiers DSA for DRAMs and column selecting gates CSG are arranged corresponding to respective bit line pairs DBL at the central portion in the column direction of the respective memory blocks MB. A memory block MB is divided into an upper memory block UMB and a lower memory block LMB with the sense amplifier DSA and column selecting gate CSG positioned at the center. In operation, either the upper memory block UMB or the lower memory block LMB is connected to the sense amplifier DSA and to the column selecting gate CSG. Whether the upper memory block UMB or lower memory block LMB is to be connected to sense amplifier DSA and column selecting gate CSG is determined by an address. Such a structure in which one memory block MB is divided into upper and lower two memory blocks UMB and LMB and one of the two blocks is connected to sense amplifier DSA and to column selecting gate CSG is commonly used in DRAMs having shared sense amplifier structure having the storage capacity equal to or larger than 4M bit. One memory mat MM includes two activation sections AS. One word line is selected in one activation section. Different from the structure shown in Fig. 7, one word line is divided into two portions and allotted to respective activation sections in the structure of Fig. 10. Namely, selection of one word line in one memory mat MM is equivalent to selection of one word line in each activation section AS. The semiconductor device (CDRAM) further comprises 4 DRAM row decoders DRD1, DRD2, DRD3 and DRD4 for selecting one word line from each of four DRAM memory mats MM1 to MM4. Therefore, in the CDRAM shown in Fig. 10, 4 word lines are selected at one time. DRAM row decoder DRD1 selects one row from corresponding activation sections AS of the memory mats MM1 and MM2. DRAM row decoder DRD2 selects one row from lower activation sections AS of memory mats MM1 and MM2. DRAM row decoders DRD3 and DRD4 select one row from upper activation sections AS of DRAM memory mats MM3 and MM4 and from lower activation sections AS of this memory mat, respectively. The CDRAM further comprises DRAM column decoders DCD for selecting two columns (bit line pairs) from each of the column blocks of memory mats MM1 to MM4 of the DRAM. Column selection signal from the DARM column decoder DCD is transmitted to a column selection line CSL shown in Fig. 8. A column selection line CSL extends to be shared by the upper and lower activation sections AS. Therefore, in the structure shown in Fig. 10, 4 columns are selected from one column block (in Fig. 10, a block including 8 memory blocks MBs divided in the column direction), by the column selection signal from DRAM column decoder DCD. Columns selected by column decoder DCD are connected to corresponding global I/O line pairs GIO. Two pairs of global I/O lines GIO extend in the column direction in each column block in one activation section. Connection between the global I/O line pair GIO and local I/O line pair LIO in each column block will be described in detail later. CDRAM shown in Fig. 10 further includes SRAM array blocks SMA1 to SMA4 each formed of SRAM cells having the capacity of 4K bit. Row decoders SRD1 and SRD2 for SRAM are provided at a middle portion between 2 SRAM array blocks to be shared by two SRAM array blocks. SRAM row decoder SRD1 is commonly used by SRAM array blocks SMA1 and SMA3. SRAM row decoder SRD2 is commonly used by SRAM array blocks SMA2 and SMA4. Details of the structure of SRAM array block SMA will be described in detail later. The CDRAM includes 4 input/output buffer circuits IOB1, IOB2, IOB3 and IOB4 for carrying out input/output of data 4 bits by 4 bits. Input/output buffer circuits IOB1 to IOB4 are connected to blocks SCDA of sense amplifiers and column decoders for SRAM, through common data buses (internal data buses), respectively. In the structure shown in Fig. 10, input/output of data are shown to be carried out through the sense amplifier and column decoder block SCDA for the SRAM. However, input/output of data may be carried out through the portion of bi-directional transfer gates BTG. In operation, one word line is selected in each activation section AS. Only the row block including the selected word line is activated. Other row blocks are maintained at the precharge state. In the selected row block, only a small block UMB (or LMB) including the selected word line is connected to the sense amplifier DSA and column selecting gate CSG for DRAM, and the other small memory block LMB (or UMB) in the selected block is separated from sense amplifier DSA and column selecting gate CSG for DRAM. Therefore, as a whole, activation (charge/discharge) of 1/8 of bit lines is effected. By this partial activation, power consumption in charging/discharging of the bit lines can be reduced. In addition, by dividing one memory block MB into an upper memory block UMB and a lower memory block LMB and by arranging a sense amplifier DSA at the center therebetween, the bit line can be made shorter, the ratio Cb/Cs of bit line capacitance Cb to memory capacitor capacitance Cs can be reduced, and sufficient reading voltage can be obtained at high speed. In each activation section AS, sensing operation in 4 small blocks UMB (or LMB) in the row direction is carried out. In each activation section AS, two pairs of bit lines are selected in one column block by a column selection signal from DRAM column decoder DCD. Global I/O line pair GIO extends in the column direction to be shared by column blocks in each activation section AS. Two pairs of bit lines are selected from each column block in each activation section AS and connected to corresponding two pairs of global I/O lines GIO. 4 pairs of global I/O lines GIO are connected to one bi-directional transfer gate BTG. 4 bi-directional transfer gates BTG are provided for one memory mat MM. Therefore, 16 pairs of global I/O lines GIO can be connected to SRAM bit line pairs SBL of the corresponding SRAM array from one memory mat MM. Layout of the global I/O lines will be described. Fig. 11 shows arrangement of global I/O lines for one memory mat. Referring to Fig. 11, the global I/O line pair GIO includes an upper global I/O line pair UGIO provided for an upper activation section UAS and a lower global I/O line pair LGIO provided for a lower activation section LAS. The upper global I/O line pair UGIO and the lower global I/O line pair LGIO are arranged in parallel. Lower global I/O line pair GIO passes through upper activation section UAS but is not connected to local I/O line pair LIO in the upper activation section UAS. Global I/O line pair GIO and local I/O line pair LIO are connected through an IO gate IOG which is a block selecting switch. Only an IO gate IOG provided in the row block including the selected word line is turned on by a block selecting signal BA and connects the corresponding local I/O line pair LIO to the corresponding global I/O line pair GIO. Since DRAM sense amplifier DSA and column selecting gate CSG are arranged at the central portion in the column direction of the memory block MB, local I/O line pair LIO is arranged along the row direction at the central portion in the column direction of memory block MB. A word line shunt region WSR is provided in the column direction between adjacent column blocks. A word line shunt region WSR is used to provide a contact between a word line formed of polysilicon having relatively high resistance and an aluminum interconnection having low resistance. The word line shunt region will be described briefly. Fig. 12 schematically shows a cross sectional structure of a selecting transistor Q0 (see Fig. 11) included in a DRAM cell. Referring to Fig. 12, the selecting transistor Q0 includes impurity regions IPR formed at a surface of a semiconductor substrate SUB, a bit line BL connected to one impurity region IPR, and a polysilicon layer PL formed on the surface of the semiconductor substrate between the two impurity regions IPR. When a word line driving signal DWL (the signal line and the signal transmitted thereon are represented by the same reference character) is transmitted to the polysilicon layer PL, a channel is formed at the surface of the semiconductor substrate between the impurity regions IPR, and the selecting transistor Q0 is turned on. Polysilicon has relatively high resistance. If word line DWL has high resistance, a signal delay is generated due to the resistance of polysilicon. In order to lower the resistance of the word line DWL, an aluminum interconnection AL having low resistance is provided in parallel to the polysilicon layer PL. By periodically connecting the aluminum interconnection AL and the polysilicon layer PL at predetermined intervals, the resistance of the word line DWL can be reduced. Aluminum interconnection AL is formed above the bit line BL. Therefore, a region for providing contact between polysilicon layer PL and aluminum interconnection AL must be provided at a region where there is no bit line BL (/BL), that is, a region where memory cell is not arranged. For this purpose, a word line shunt region is provided between column blocks. The manner of connection is shown in Fig. 13. Referring to Fig. 13, aluminum interconnection AL having low resistance is provided in parallel to polysilicon layer PL having relatively high resistance serving as a word line. Word line driving signal DWL is transmitted to aluminum interconnection AL. Aluminum interconnection AL and polysilicon layer PL are periodically connected to each other by a contact layer CNT in word line shunt region WSR. By periodically providing contacts between aluminum interconnection AL and polysilicon layer PL through contact region CNT, the resistance of polysilicon layer PL can be effectively reduced. Therefore, even if a word line is very long, the word line driving signal WL can be transmitted to the terminal end of the word line at high speed. Fig. 14 schematically shows a layout of global I/O lines and column selecting lines CSL. In Fig. 14, layout of these lines for two memory blocks MB only is shown. In Fig. 14, global I/O line pair GIO is arranged in word line shunt region WSR. DRAM word lines DWL are arranged in a direction orthogonally crossing the global I/O line pair GIO. In Fig. 14, aluminum interconnection AL and polysilicon layer are arranged in parallel to each other, and in this plan view, they are overlapped with each other. Therefore, they are shown as the same word lines DWL. Column selecting lines CSL for transmitting column selection signal from DRAM column decoder are arranged in a direction orthogonally crossing DRAM word lines DWL. Although the bit line pairs DBL of DRAM are not shown in this layout, the bit line pairs are arranged in parallel to column selecting lines CSL. Aluminum interconnection AL (see Fig. 12) for DRAM word lines DWL is formed by a first layer aluminum interconnection. Column selecting lines CSL are formed by a second layer aluminum interconnection. Global I/O lines are formed by the same aluminum interconnection as the column selecting lines CSL. By providing global I/O line pair GIO in word line shunt region WSR, chip area is not increased even if I/O lines for connecting DRAM array and bi-directional transfer gates are adapted to have hierarchical structure of local I/O lines and global I/O lines. Fig. 15 schematically shows a structure of SRAM array block SMA shown in Fig. 10. Referring to Fig. 15, a SRAM array block SMA includes 16 pairs of bit lines SBL and 256 SRAM word lines SWL. SRAM cells SMC are arranged at crossings of SRAM bit line pairs SBL and SRAM word lines SWL. As shown in Fig. 10, in order to have the SRAM array block SMA accordant with a rectangular chip layout, SRAM bit line pairs SBL are arranged in the row direction of DRAM array and SRAM word lines SWL are arranged in column direction of DRAM array. SRAM word lines SWL are connected to SRAM row decoder SRD. SRAM bit line pairs SBL must be connected to global I/O line pair GIO through bi-directional transfer gate BTG. Therefore, SRAM bit line pairs SBL must be connected to bi-directional transfer gate BTG on the lower side as viewed in Fig. 15 (or upper side of Fig. 15: determined by the arrangement of the memory array). For this purpose, in the structure shown in Fig. 15, SRAM bit line taking lines SBLT are arranged in parallel to SRAM word lines SWL. The number of SRAM bit line taking lines SBLT is the same as the number of bit line pairs SBL of the SRAM array block SMA, and the taking lines are connected to corresponding SRAM bit line pairs SBL. If SRAM bit line taking lines SBLT are formed by the same interconnection layer as SRAM word lines SWL, SRAM bit line taking lines SBLT can be implemented easily without additionally providing interconnection layers formed by additional step of manufacturing. The SRAM row decoder SRD decodes a row address for SRAM to select one of the 256 SRAM word lines SWL. 16 bits of SRAM cells SMC connected to the selected SRAM word line SWL are connected to corresponding SRAM bit line pair SBL and to SRAM bit line taking line SBLT. In data transfer, the bit line taking lines SBLT are connected to global I/O line pair GIO through bi-directional transfer gate BTG. By employing such a layout as shown in Figs. 11 and 15, a structure as shown in Fig. 10 can be realized, in which DRAM arrays are arranged divided into upper and lower portions as viewed in the figure, SRAM arrays are collectively arranged between the upper and lower DRAM array blocks, and input/output buffer circuits IOB1 to IOB4 are provided near SRAM arrays formed at the central portion of the semiconductor memory device (chip). Such structure having SRAM arrays collectively formed at the central portion of the chip and input/output of data are effected near the central portion of the chip is advantageous for CDRAM as will be described in the following. High speed access to a cache register is the first and most important characteristic of CDRAM. Arrangement of the SRAM array serving as the cache register near the input/output buffer for inputting/outputting data to and from the outside of the device results in shorter signal lines, which enables high speed input/output of data, and thus meets the demand of high speed accessing. By collectively arranging SRAM arrays at the central portion, address lines for selecting SRAM cells can be made shorter. If an address line is made shorter, interconnection resistance and parasitic resistance of the address line can be reduced, SRAM cells can be selected at high speed, and therefore it is suitable for high speed accessing to the cache register. In the architecture shown in Fig. 10, interconnections connecting the DRAM array and SRAM array may be longer, lowering the speed of data transfer between the DRAM array and SRAM array. However, data transfer is carried out between DRAM array and SRAM array only when a cache miss (miss hit) occurs. In that case, access speed as low as that of the standard DRAM is sufficient, and it is not very much desired to increase this access speed. Therefore, this is not a problem in practical use. In this case also, writing/reading of data can be carried out at high speed by using the data transfer apparatus which will be described later. [Another Arrangement of SRAM Array] In this section, reference is made on Figs. 16 to 30. SRAM array is arranged to implement any shape with storage capacity fixed. Each row of SRAM array has a plurality of word lines associated therewith. One of word lines is selected. One row corresponds effectively to a plurality of rows. Data transfer between DRAM array and SRAM array of multiplicate word line arrangement be also described. Fig. 16 shows a structure of the SRAM cell. Referring to Fig. 16, the SRAM cell SMC includes MOS (insulated gate type) transistors SQ1, SQ2, SQ3 and SQ4 constituting an inverter latch. P channel MOS transistor SQ1 and n channel MOS transistor SQ3 are complementary connected between operational supply potential Vcc and the other supply potential (ground potential), forming one inverter circuit. P channel MOS transistor SQ2 and n channel MOS transistor SQ4 are complementary connected between the operational supply potential Vcc and the ground potential, forming the other inverter circuit. Transistors SQ1 and SQ3 have their gates connected to an node SN1, and transistors SQ2 and SQ4 have their gates connected to an node SN2. Node SN1 is an output node of one inverter circuit (transistors SQ1 and SQ3), and node SN2 is an output node of the other inverter circuit (transistors SQ2 and SQ4). SRAM cell SMC further includes n channel MOS transistors SQ5 and SQ6 rendered conductive in response to a signal on SRAM word line SWL for connecting nodes SN1 and SN2 to bit lines SBL and *SBL. Diode connected n channel MOS transistors SQ7 and SQ8 are provided on bit lines SBL and *SBL. MOS transistors SQ7 and SQ8 clamp the potential of "H" on bit lines SBL and *SBL at a potential Vcc-Vth and "L" thereon at VL1 (described later). The character Vth represents the threshold voltage of the transistors SQ7 and SQ8. Data writing and reading operations of the SRAM cell will be briefly described. In data writing, data complementary to each other are transmitted to bit line SBL and complementary bit line *SBL. Assume that a potential at "H" is transmitted to bit line SBL and a potential at "L" is transmitted to complementary bit line *SBL. Potential on word line SWL is at "H" and nodes SN1 and SN2 are connected to bit lines SBL and *SBL through conductive transistors SQ5 and SQ6, respectively. The potential of node SN1 is applied to the gates of transistors SQ2 and SQ4, so that transistor SQ4 is rendered conductive and transistor SQ2 is rendered non-conductive. The potential at "L" on node SN2 is applied to the gates of transistors SQ1 and SQ3, so that transistor SQ1 is rendered conductive, and transistor SQ3 is rendered non-conductive. Consequently, the potential at node SN1 is set to "H", the potential on node SN2 is set to "L" and these potentials are latched by the inverter latch circuits formed of transistors SQ1 to SQ4. By the fall of the potential on SRAM word line SWL to "L", writing of data is completed. In data reading, the potential of the SRAM word line SWL rises to "H" and transistors SQ5 and SQ6 are rendered conductive. The stored data (potential) which has been latched at nodes SN1 and SN2 are transmitted to bit lines SBL and *SBL, respectively. Complementary data of "H" and "L" are transmitted to bit lines SBL and *SBL. The signal potentials on bit lines SBL and *SBL are amplified by a sense amplifier, not shown, and thus data is read out . Fig. 17 is a diagram for illustrating the functions of transistors SQ7 and SQ8 shown in Fig. 16. The operation of the transistors SQ7 and SQ8 will be described with reference to Figs. 16 and 17. Transistors SQ7 and SQ8 are diode connected, and clamp the potentials on bit lines SBL and *SBL to Vcc-Vth. More specifically, the "H" potential level of the potential amplitude of bit lines SBL and *SBL is set to Vcc-Vth. The data of "H" latched in node SN1 has the potential at Vcc level. When the latched data of "H" is transmitted to bit line SBL, the level of this data attains Vcc-Vth, because of signal loss by transistor SQ5. The "L" level potential VL1 of the potential amplitude of bit line SBL (or *SBL) is determined by resistive division of transistors SQ4, SQ6 and SQ8 (or SQ3, SQ5 and SQ7). The potential VL1 of "L" level of the bit line potential amplitude is higher than the ground potential Vss. Namely, transistors SQ7 and SQ8 have also a function of raising potential of "L" of bit lines SBL and *SBL. Assume that transistors SQ7 and SQ8 are not provided. In that case, the "L" level potential VL2 of bit lines SBL and *SBL are discharged by transistors SQ6 and SQ4 (or SQ5 and SQ3) to the ground potential Vss to be approximately at the ground potential level. The "H" level potential of bit line SBL (or *SBL) is provided as Vcc-Vth even when transistors SQ7 and SQ8 are not provided. In this case, it is assumed that the "H" level applied to word line SWL is at the level of operational supply voltage Vcc, and that there is a loss of the threshold voltage Vth of transistor SQ5 or SQ6 in transistor SQ5 (or SQ6). Assume that the potential on SRAM word line SWL rises to "H" at time TWL in Fig. 17. When transistors SQ7 and SQ8 are provided, data stored in SRAM cell SMC is transmitted to bit lines SBL and *SBL, and potentials "H" and "L" on bit lines SBL and *SBL cross at time T1. When transistors SQ7 and SQ8 are not provided, the potentials "H" and "L" of bit lines SBL and *SBL cross at time T2. Data on respective bit lines SBL and *SBL are established after the time of crossing of potentials "H" and "L" on bit lines SBL and *SBL. Therefore, by the provision of transistors SQ7 and SQ8, logic amplitude of bit lines SBL and *SBL can be made smaller and the access time can be made shorter. Different from the DRAM, the SRAM does not need RAS precharge time, and therefore it can be accessed at high speed. However, in SRAM array, one memory cell always exists at a crossing of an SRAM word line and a bit line. One memory cell is connected to bit line SBL and complementary bit line *SBL. A SRAM cell includes 6 transistors as shown in Fig. 16, and therefore compared with a DRAM cell including one transistor and one capacitor, it occupies larger area. Therefore, to provide a CDRAM which is highly integrated with high density, SRAM array should be effectively arranged in as small an area as possible. Assume that the CDRAM is to be housed in a rectangular package 550 as shown in Fig. 18. Package 550 has a longer side direction represented by X and a shorter side direction represented by Y in Fig. 18. For packaging in such a rectangular package, a DRAM array 560 having large storage capacity is arranged in a rectangular so as to match with the shape of package (or chip) 550. Here, it should be noted that the chip having DRAM array and CDRAM array integrated thereon has the same shape as the package. Data are transferred bi-directionally through transfer gate 570 between DRAM array 560 and SRAM array 580. In such arrangement, the SRAM array 580 should have the same length as the shorter side length of the DRAM array, in view of effective chip area occupation or array layout. Assume that DRAM array 560 and SRAM array 580 can transfer data of 16 bits at one time, as shown in Fig. 19 and described previously. In this case, cache size is 16 bit. 16 pairs of SRAM bit lines SBL and *SBL are arranged for one SRAM word line SWL. SRAM array 580 has a structure of 256 rows x 16 columns. When 256 SRAM word lines SWL1 to SWL256 are arranged along the longer side of package 550 as shown in Fig. 19, SRAM array 580 becomes long in the long side direction (X direction). If so, it can not be arranged in the area allotted to SRAM array 580 of package 550. If SRAM word lines SWL1 to SWL256 are arranged in the short side direction (Y direction) of package 550 as shown in Fig. 20, the length in the long side direction (X direction) in Fig. 18 can be reduced, but it becomes longer in the short side direction (Y direction). Therefore, in this case also, it can not be arranged in the area allotted to SRAM array in package 550. The size of SRAM array is determined uniquely when the number of bit line pairs and the number of SRAM word lines are determined. Therefore, the shape of SRAM array can not be flexibly changed. In SRAM array, when a memory cell is selected, current always flows through the selected memory cell. Therefore, in view of current consumption, the number of memory cells connected to one word line should preferably be as small as possible. If the number of word lines are increased to reduce the number of memory cells connected to one word line, the bit line becomes longer. This in turn causes a problem that parasitic capacitance of the bit line is increased and access time is increased. The shape of the DRAM array can be changed to be suited for the package relatively easily, by employing block divided arrangement, shared sense amplifier structure and the like. Therefore, it is preferred to provide a semiconductor memory device containing a cache occupying small area to realize an SRAM array structure whose shape can be flexibly changed corresponding to the shape of the DRAM array. The arrangement of the DRAM array and the SRAM array in the rectangular area as described previously is required to house a 4M CDRAM in a rectangular package. The SRAM array SMA is arranged between DRAM arrays MMs as shown in Fig. 10. SRAM array SMA is arranged in a rectangular region which is short in the long side direction (X direction) of the chip and long in the short side direction (Y direction) of the chip. SRAM array SMA has a storage capacity of 4K bits, and transfers 16 bits of data at one time to and from the corresponding DRAM array MM through a bi-directional transfer gate circuit BTG. In this embodiment, SRAM array SMA includes 256 word lines and 16 pairs of bit lines. The SRAM array structure for effectively arranging SRAM array in the rectangular area will be described. Fig. 21 shows in principle the structure of the SRAM array in accordance with an embodiment of the present invention. Fig. 21 shows two SRAM word lines SWL1 and SWL2 and two pairs of bit lines SBL1, *SBL1, SBL2 and *SBL2, as representatives. SRAM cells SMC1 and SMC2 are arranged in one row. SRAM word lines SWL1 and SWL2 are commonly provided for the row in which SMC1 and SMC2 are arranged. Word line SWL1 is connected to memory cell SMC1. Word line SWL2 is connected to memory cell SMC2. SRAM memory cell SMC1 is connected to bit line pair SBL1, *SBL1. Memory cell SMC2 is connected to bit line pair SBL2, *SBL2. Clamping transistors SQ7, SQ8, SQ15 and SQ16 are provided for clamping "H" and "L" level potential of the bit line potential for bit lines SBL1, *SBL1, SBL2 and *SBL2. Memory cells SMC1 and SMC2 have the same structure as the SRAM cell SMC shown in Fig. 16 and has a structure of a latch type storing element. SRAM cell SMC1 includes p channel MOS transistors SQ1 and SQ2 and n channel MOS transistors SQ3, SQ4, SQ5 and SQ6. Transistors SQ5 and SQ6 are rendered conductive in response to a signal potential on word line SWL1 and connect nodes SN1 and SN2 to bit lines SBL1 and *SBL1, respectively. Transistors SQ1, SQ2, SQ3 and SQ4 constitute an inverter type latch circuit. SRAM cell SMC2 includes p channel MOS transistors SQ9 and SQ10 and n channel MOS transistors SQ11, SQ12, SQ13 and SQ14. Transistors SQ13 and SQ14 are rendered conductive in response to a signal potential on SRAM word line SWL2, and connect nodes SN3 and SN4 to bit lines SBL2 and *SBL2. Transistor SQ9, SQ10, SQ11 and SQ12 constitute an inverter type latch circuit. In the array arrangement shown in Fig. 21, memory cells existing on even numbered columns (SMC2 and the like) of memory cells arranged in one row are connected to word line SWL2, while memory cells existing on odd numbered columns (SMC1 and the like) are connected to word line SWL1. The number of memory cells connected to word line SWL1 is the same as the number of memory cells connected to the word line SWL2. In this structure, an SRAM array having an arbitrary shape can be easily realized, as will be made clear later. Figs. 22A and 22B shows a comparison between the conventional SRAM array arrangement and the SRAM array arrangement of the present invention. Referring to Fig. 22A, one word line SWL is arranged for one row of memory cells. In this case, memory cells SMCs are arranged in M rows x N columns. Meanwhile, as shown in Fig. 22B, two word lines SWLa and SWLb are provided for one row of memory cells SMC, and one row of memory cells SMCs are connected alternately to word lines SWLa and SWLb. In this case, memory cells SMCs are arranged in M/2 rows x 2N columns. In both array arrangements shown in Figs. 22A and 22B, N memory cells SMCs are connected to one word line. In the structure of Fig. 22B, when three or more word lines are arranged for one row of memory cells and memory cells are connected alternatively to respective word lines, an SRAM array having an arbitrary shape can be provided. This increases degree of freedom in designing the structure and arrangement of the SRAM array in chip lay out. Fig. 23 shows a pattern of memory cell arrangement shown in Fig. 21. The structure of the memory cell will be described briefly with reference to Fig. 23. Supply line Vcc, SRAM word lines SWL1 and SW2 and a ground line GND are arranged in parallel and formed by a second layer aluminum interconnection (second aluminum interconnection). Bit lines SBL1, *SBL1, SBL2 and *SBL2 are formed by a first layer aluminum interconnection (first aluminum interconnection). Gates of transistors SQ1 to SQ16 are formed by a first layer polysilicon interconnection (first poly interconnection). The respective transistors are connected by a fourth layer polysilicon interconnection (fourth poly interconnection), and word lines are connected to the gates of the transistors by the first layer aluminum interconnection. Memory cells SMC1 and SMC2 have the same pattern layout. In the following, connection of memory cell SMC1 will be described. Clamping transistor SQ7 has its drain connected to bit line SBL1 through a contact hole CX1, its gate and source connected to the first layer aluminum interconnection through contact holes CX3 and CX2, and this first aluminum interconnection is connected to supply line Vcc through a contact hole CX6. Transistor SQ8 has its drain connected to bit line *SBL1 formed of the first layer aluminum interconnection through a contact hole CX5, and its gate and source connected to the first layer aluminum interconnection layer through contact holes CX4 and CX2, and this first layer aluminum interconnection layer is connected to supply line Vcc through contact hole CX6. Transistor SQ1 has its drain connected to the first layer aluminum interconnection through a contact hole CX8, and this first layer aluminum interconnection is connected to the fourth layer polysilicon interconnection through a contact hole CX9. This fourth layer polysilicon interconnection connected to contact hole CX9 provides node SN1. Node SN1 is connected to gate electrodes of transistors SQ2 and SQ4 through the fourth layer polysilicon interconnection and contact hole CX11. This fourth layer polysilicon interconnection of node SN1 is connected to the drain of transistor SQ3 and to one conduction terminal of transistor SQ5 through contact hole CX16. Transistor SQ1 has its gate connected to node SN2 through contact hole CX10 and through the fourth layer polysilicon interconnection. Transistor SQ1 has its source connected to supply line Vcc through contact hole CX7, the first layer aluminum interconnection and contact hole CX6. Transistor SQ2 has its drain connected to the first layer aluminum interconnection through a contact hole CX23, and this first layer aluminum interconnection is connected to the fourth layer polysilicon interconnection through a contact hole CX22. The fourth layer polysilicon interconnection connected to contact hole CX22 provides node SN2. Transistor SQ1 has its gate connected to the fourth layer polysilicon interconnection providing node SN1, through contact hole CX11. Transistor SQ3 has its drain connected to the fourth layer polysilicon interconnection through contact hole CX16 and connected to node SN1. Transistor SQ3 has its gate connected to the fourth polysilicon interconnection layer through contact hole CX10 and to node SN2. Transistor SQ3 has its source connected to the first layer aluminum interconnection through contact hole CX18, and the first layer aluminum interconnection is connected to the ground line GND through contact hole CX17. Transistor SQ4 has its source connected to ground line GND through contact hole CX18, the first layer aluminum interconnection and contact hole CX17. Transistor SQ4 has its gate connected to node SN1 through contact hole CX11 and the fourth layer polysilicon interconnection. Transistor SQ4 has its drain connected to node SN2 through contact hole CX20 and the fourth layer polysilicon interconnection. Transistor SQ5 has its gate connected to the first layer aluminum interconnection through contact hole CX14, and this first aluminum interconnection is connected to word line SWL1 through contact hole CX12. Transistor SQ6 has its gate connected to the first layer aluminum interconnection through contact hole CX19, and to word line SWL1 through contract hole SX12. One conduction terminal of transistor SQ6 is connected to bit line SBL1 through contact hole CX21. The other conduction terminal of transistor SQ6 is connected to node SN2 through contact hole CX20 and the fourth layer polysilicon interconnection. As shown in Fig. 23, memory cells are arranged in one row, two word lines SWL1 and SWL2 can be arranged for the one row, and multiplicate word line arrangement in which a plurality of word lines are provided for memory cells arranged in one row can be easily realized. Fig. 24 shows an SRAM array arrangement in accordance with one embodiment of the present invention. The SRAM array arrangement shown in Fig. 24 is applied to the 4K bit SRAM array shown in Fig. 10. Referring to Fig. 24, the SRAM array SMA includes static memory cells (SRAM cells) arranged in 128 rows and 32 columns. Two SRAM word lines SWL are provided for SRAM cells arranged in one row. For example, two SRAM word lines SWL1 and SWL2 are provided for the first row of SRAM cells. SRAM word lines SWL3 and SWL4 are provided for the second row of memory cells. SRAM cells of the odd numbered columns are connected to odd numbered SRAM word lines (SWL1, SWL3, ...) while SRAM cells of the even numbered columns are connected to even numbered SRAM word lines (SWL2, SWL4, ...). Every other SRAM cells of the respective rows of SRAM cells are connected to corresponding SRAM word lines SWL1 to SWL256. Namely, 16 bits of SRAM cells are connected to each of SRAM word lines SWL1 to SWL256. In accessing SRAM cell, a column should be selected. The arrangement of Fig. 24 includes effectively 16 columns. In column selection, SRAM column address and word line group designating signal (a least significant SRAM row address bit, for example) are combined to generate a SRAM column select signal to connect a selected SRAM column to internal data bus. As shown in Fig. 10, an SRAM row decoder for selecting the SRAM word lines is arranged in a direction orthogonally crossing the word lines SWL1 to SWL256. Data is transferred between the DRAM array and a SRAM cell through a transfer gate circuit BTG. Data must be transferred through SRAM bit lines SBL and *SBL. Therefore, as in the case of Fig 15, bit line taking line SBLT is provided for each bit line pair SBL and *SBL. The bit line taking lines SBLT and *SBLT are formed by the second layer aluminum interconnection. One bi-directional transfer gate circuit BTG is provided for two pairs of bit lines SBL and *SBL, that is, two pairs of SRAM bit line taking lines SBLT and *SBLT. Bi-directional transfer gate circuit BTG is connected to corresponding global I/O lines GIO and *GIO. 16 bits of data are transferred at one time between DRAM array and SRAM array through bi-directional transfer gate 210. In accordance with the structure, one transfer gate circuit can be arranged for two pairs of SRAM bit line taking lines SBLT and *SBLT in the SRAM array. Consequently, pitch condition in the Y direction for transfer gate circuit BTG can be released, and therefore even a transfer gate circuit having a complicated structure can be formed with sufficient margin. Although memory cells are arranged in 128 rows and 32 columns in the arrangement of SRAM array shown in Fig. 24, the structure is substantially equivalent with the SRAM array of 256 rows x 16 columns. In this case, the dimension in Y direction can be reduced to approximately one half of the SRAM array arrangement of 256 rows x 16 columns, and therefore SRAM cells can be arranged in the rectangular SRAM array area shown in Fig. 10 or 18. In the SRAM array arrangement shown in Fig. 24, only one half of memory cells of one row of memory cells are selected, which realizes substantial block dividing operation or partial activation, and thus the SRAM can be driven with low current consumption. Now, data transfer between DRAM array of Fig. 8 and SRAM array of Fig. 24 will be described with reference to Figs. 25 through 30. Fig. 25 shows an example of the structure of the transfer gate circuit BTG shown in Fig. 24. Fig. 25 shows, as a representative, a transfer gate circuit BTG1 provided for SRAM bit line pairs SBL1, *SBL1 and SBL2 and *SBL2, that is, for SRAM bit line taking lines SBLT1, *SBLT1, SBLT2 and *SBLT2. Transfer gate circuit BTG includes a selecting circuit 9501 for selecting a pair of bit lines out of two pairs of bit lines in response to an address signal Acd for the SRAM; and a transfer circuit 9502 for connecting global I/O lines GIO1 and *GIO1 to internal nodes A and B for transferring data between nodes A and B and global I/O lines GIO1 and *GIO1. The least significant bit of the row address for the SRAM is used as the selection control signal applied to the selecting circuit 9501. When selected SRAM word line is an even numbered word line, selecting circuit 9501 selects SRAM bit line taking lines SBLT1 and *SBLT1 corresponding to the even numbered column, and otherwise it selects SRAM bit line taking lines SBLT2 and *SBLT2 corresponding to the odd numbered column. The details of the structure of transfer circuit 9502 will be described later. Any circuit having the function of bi-directional data transfer may be used. Fig. 26 shows an example of a specific structure of selecting circuit 9501 shown in Fig. 25. Referring to Fig. 26, selecting circuit 9501 includes an n channel MOS transistor GTr1 responsive to a selection control signal Acd for selecting SRAM bit line taking line SBLT1 (or *SBLT1), and a p channel MOS transistor GTr2 responsive to the selection control signal Acd for selecting SRAM bit line taking line SBLT2 (or *SBLT2). The other terminal of each of the transistors GTr1 and GTr2 is connected to node A (or B). In the structure shown in Fig. 26, when selection control signal Acd is 1 ("H" level), transistor GTr1 is rendered conductive, and SRAM bit line taking line SBLT1 (or *SBLT1) is selected and connected to node A (or B). When selection control signal Acd is 0 ("L" level), SRAM bit line taking line SBLT2 (or *SBLT2) is selected and connected to node A (or B). In the structure shown in Fig. 24, clamp transistors (indicated by the block CLP) for raising "L" level of potential amplitude are provided for the SRAM bit line pair SBL and *SBL. Therefore, the non-selected bit line pairs are maintained at the "H" clamp potential, and potential of each bit line changes only for the selected columns. In the SRAM array structure shown in Fig. 24, the clamp transistor (represented by block CLP in Fig. 24) provided for each SRAM bit line pair SBL, *SBL are always kept conductive. A structure in which function of the clamp transistor is stopped during the SRAM word line selecting operation may be used. Fig. 27 shows another structure of the SRAM array and a structure of the bi-directional transfer gate circuit used associatively. Fig. 27 shows, as representatives, SRAM bit line pairs SBL0, *SBL0, SBL1 and *SBL1. The SRAM cells are omitted for simplicity of the drawing. Accurately, SRAM bit line taking lines SBLT and *SBLT are connected to the transfer gate circuit (BTG1). However, in Fig. 27, the SRAM bit lines SBL and *SBL are shown to be directly connected to the transfer gate circuit. Referring to Fig. 27, for SRAM bit line pair SBL0 and *SBL0, p channel MOS transistors SQE1, SQE2 and SQE3 responsive to a SRAM bit line equalizing signal SBLEQ for precharging and equalizing SRAM bit lines SBL0 and *SBL0 to a predetermined potential, and p channel MOS transistors SQC1 and SQC2 responsive to a SRAM bit line clamping signal SBLCL for clamping potentials on SRAM bit lines *SBL0 and SBL0 are provided. Transistors SQE1 and SQE2 precharge SRAM bit lines *SBL0 and SBL0 to a predetermined potential (Vcc) in response to SRAM bit line equalizing signal SBLEQ. Transistor SQE3 equalizes potential on SRAM bit lines SBL0 and *SBL0 in response to SRAM bit line equalizing signal SBLEQ. Transistors SQC1 and SQC2 clamp potentials on SRAM bit lines *SBL0 and SBL0 in response to SRAM bit line clamping signal SBLCL. Transistors SQC1 and SQC2 also function as load transistors. SRAM bit line equalizing signal SBLEQ is generated at a standby of the SRAM, and SRAM bit line clamping signal SBLCL is set to the inactive state of "H" when a word line is selected in the SRAM array. For SRAM bit lines *SBL1 and SBL1, p channel MOS transistors SQE4, SQE5 and SQE6 which are rendered conductive in response to SRAM bit line equalizing signal SBLEQ, and p channel MOS transistors SQC3 and SQC4 which are rendered conductive in response to SRAM bit line clamping signal SBLCL are provided. Transistors SQE4 and SQE5 precharge SRAM bit lines *SBL1 and SBL1 at the time of standby. Transistor SQE6 equalizes potentials on bit lines *SBL1 and SBL1 at the standby of the SRAM. Transistors SQC3 and SQC4 clamp potentials on SRAM bit lines *SBL1 and SBL1. In the SRAM array arrangement shown in Fig. 27, each of the bit lines SBL and *SBL is precharged to the "H" level at the standby of the SRAM, the clamping transistor is rendered non-conductive only when the word line is being selected, and SRAM bit lines are set to the floating state. In this state, when SRAM bit lines SBL0 and *SBL0 are selected, potential change corresponding to the data stored in the selected memory cell appears on the bit lines. Meanwhile, non-selected bit line pair SBL1 and *SBL1 is maintained at "H" level of the potential having been clamped by the clamping transistors SQC3 and SQC4. In such a structure in which potentials of one pair of bit lines out of two pairs of bit lines connected to one transfer gate circuit is at the clamp potential and potential change corresponding to the stored data of the memory cell (SRAM cell) appears only on the other bit line pair, selecting circuit for selecting an SRAM bit line pair is not necessary when data is transferred from the SRAM array to the DRAM array. The structure shown in Fig. 27 utilizes the fact that the potential of one bit line pair is clamped at "H". Referring to Fig. 27, the transfer gate circuit 9600 (BTG1) includes an amplifier 9601 receiving signal potentials on SRAM bit line pairs SBL0, *SBL0 and SBL1, *SBL1 for amplifying potential of the SRAM bit lines on which potential change is generated; a first transfer circuit 9602 for transferring a signal from amplifier 9601; a latch circuit 9603 for latching signal data transferred from first transfer circuit 9602; and a second transfer circuit 9604 for transferring data latched in latch circuit 9603 to DRAM array (global IO line). Amplifier 9601, first transfer circuit 9602, latch 9603 and second transfer circuit 9604 are used for data transfer from SRAM array to DRAM array. Bi-directional transfer gate circuit 9600 further includes an amplifier 9605 for amplifying data from global IO lines GIO1 and *GIO1 from the DRAM array; a third transfer circuit 9606 for transferring data amplified by amplifier 9605; and selecting gate 9607 for transmitting data from transfer circuit 9606 by selecting corresponding SRAM bit line pair in accordance with the least significant bit Acdr of the SRAM row address. Amplifier 9605, third transfer circuit 9606 and selecting gate 9607 are used for data transfer from the DRAM array to the SRAM array. Fig. 28 shows a specific structure of the data transfer path from the SRAM array to the DRAM array. Referring to Fig. 28, amplifier circuit 9601 includes n channel MOS transistors SQA1 and SQA2 having their gates connected to SRAM bit lines SBL0 and SBL1, respectively; and n channel MOS transistors SQA3 and SQA4 having their gate connected to respective complementary SRAM bit lines *SBL0 and *SBL1. Transistors SQA1 and SQA2 are connected in series, and the other conduction terminal of transistor SQA2 is connected to ground potential Vss. Transistors SQA3 and SQA4 are connected in series, and the other conduction terminal of transistor SQA4 is connected to ground potential Vss. First transfer circuit 9602 includes n channel MOS transistors SQA5 and SQA6 which are rendered conductive in response to data transfer designating signal DTL. Transistor SQA5 is connected in series with transistor SQA1, and transistor SQA6 is connected in series with transistor SQA3. Latch circuit 9603 includes inverter circuits SIV1 and SIV2 connected in anti-parallel, and inverter circuits SIV3 and SIV4 for inverting data transferred from transfer circuit 9602. Second data transfer circuit 9604 includes a transfer gate 9604a for transmitting an output from latch circuit 9603 to global I/O line GIO1, and a transfer gate 9604b for transferring data latched in latch circuit 9603 to global I/O line *GIO1. Transfer gates 9604a and 9604b includes n channel MOS transistors SQA7 and SQA8 which are rendered conductive in response to data transfer designating signal DTA, respectively. Fig. 29 shows an example of the specific structures of the amplifier, the third transfer circuit and the selecting gate shown in Fig. 27. Referring to Fig. 29, amplifying circuit 9605 includes an n channel MOS transistor SQB1 having its gate connected to the global I/O line GIO1, an n channel MOS transistor SQB3 having its gate connected to the complementary global I/O line *GIO1, n channel MOS transistors SQB2 and SQB4 which are rendered conductive in response to data transfer designating signal DTS for transmitting signal potential amplified by transistors SQB1 and SQB3, and p channel MOS transistors SQB5, SQB6, SQB7 and SQB8 for amplifying and maintaining the signal potential transmitted from the transistors SQB2 and SQB4. Transistors SQB5 and SQB6 are connected in parallel between supply potential Vcc and node SND1. Data transfer designating signal DTS is applied to the gate of transistor SQB6. The transistor SQB5 has its gate connected to node SND2. Transistors SQB7 and SQB8 are connected in parallel between supply potential Vcc and node SND2. Transistor SQB7 has its gate connected to node SND1. Data transfer designating signal DTS is applied to the gate of transistor SQB8. Third transfer circuit 9606 includes two transfer gates 9606b and 9606a. Transfer gate 9606a includes an n channel MOS transistor SQB10 which is rendered conductive in response to data transfer designating signal DTS for transmitting data amplified by amplifier circuit 9605. Transfer gate 9606 includes an n channel MOS transistor SQB9 which is rendered conductive in response to data transfer designating signal DTS for transmitting signal potential at node SND1 of amplifier circuit 9605. Selecting gate 9607 includes two selecting gates 9607a and 9607b. Selecting gate 9607a includes an n channel MOS transistor SQB14 which is rendered conductive in response to SRAM address Acdr, and an n channel MOS transistor SQB13 which is rendered conductive in response to SRAM address *Acdr. The least significant bit (Ac4) of the row address of the SRAM array is used to generate the SRAM addresses Acdr and *Acdr. Selecting gate 9607b includes an n channel MOS transistor SQB12 which is rendered conductive in response to address signal Acdr for transmitting data from transfer gate 9606, and an n channel MOS transistor SQB11 which is rendered conductive in response to complementary address signal *Acdr for transmitting data from transfer gate transistor SQB9. When address signal Acdr is at "H", transistors SQB12 and SQB14 are rendered conductive and bit line pair SBL1 and *SBL1 is selected. When address signal Acdr is at "L", transistors SQB11 and SQB13 are rendered conductive and bit line pair SBL0 and *SBL0 is selected. Prior to the data transfer operation, the operation of the amplifier circuit 9605 will be briefly described. Assume that global I/O line GIO1 is at "H" and global I/O line *GIO1 is at "L". In this case, if the signal DTS is at "H", transistor SQB1 is conductive and transistor SQB3 is rendered non-conductive. Potential at node SND1 is discharged to ground potential Vss, while there is no discharging path for the potential at node SND2. In this case, transistor SQB7 is rendered conductive, and potential of node SND2 is charged by transistor SQB7. Therefore, the potential at node SND2 is set to "H" and potential at node SND1 is set to "L". When data transfer is to be designated, data transfer designating signal DTS rises to "H". Therefore, in data transfer, transistors SQB6 and SQB8 are rendered non-conductive, and potentials at nodes SND1 and SND2 are rapidly set at potentials corresponding to the data which is to be transferred. Normally, the signal DTS is at "L", and nodes SND1 and SND2 are maintained at "H" level by transistors SQB6 and SQB8. The data transfer operation of the transfer circuit shown in Fig. 27 will be described with reference to Fig. 30, which is a diagram of signal waveforms. In data transfer operation of transfer circuit 9600 shown in Fig. 27, data is transferred from the SRAM array to latch circuit 9603, while data is transferred from the DRAM array to the SRAM array. Thereafter, data which has been latched in latch circuit 9603 is transferred to DRAM array. The data transfer operation of transfer circuit will be described in detail later. When SRAM bit line equalizing signal SBLEQ rises to "H", SRAM enters the memory cycle. In response, precharge and equalizing transistors SQE1 to SQE6 provided for each bit line pair SBL, *SBL are rendered non-conductive. At this time, SRAM bit line clamping signal SBLCL is still at "L", and each bit line SBL, *SBL is maintained at "H" level through the clamping transistors (SQC1, SQC2, SQC3 and SQC4). Thereafter, word line selecting operation is executed in the SRAM array, and the SRAM word line rises. Approximately at the same time, the SRAM bit line clamping signal SBLCL rises to "H". Timing of rising of clamping signal SBLCL may be set earlier than the word line selecting timing in the SRAM array. Consequently, data of half of the memory cells of one row are read. Assume that word line SWL1 is selected. In this case, referring to Fig. 27, SRAM bit line pair SBL0 and *SBL0 maintain "H" level as in the standby state. Meanwhile, potentials of SRAM bit line pair SBL1 and *SBL attain the levels corresponding to the data stored in the memory cells connected thereto. In this case, referring to Fig. 28, transistors SQA1 and SQA3 are rendered conductive. Conduction/non conduction of transistors SQA2 and SQA4 is determined dependent on the data of the selected memory cell at that time. Responsive to the rise of data transfer designating signal DTL to "H", signal potentials on SRAM bit lines SBL1 and *SBL1 are latched by latch circuit 9603. In parallel to the latching operation, data transfer from the DRAM array to the SRAM array is executed. In the SRAM array, the word line is kept at the selected state. When signal potentials on global I/O lines GIO1 and *GIO1 are established, conduction/non conduction of transistors SQB1 and SQB3 is determined (see Fig. 29). Thereafter, when data transfer designating signal DTS is generated, transistors SQB2 and SQB4 are rendered conductive, data on global I/O lines GIO1 and *GIO1 are inverted and amplified to be maintained at nodes SND1 and SND2. The data at nodes SND1 and SND2 are transmitted to selecting gates 9607b and 9607a through transfer gates SQB9 and SQB10 which are already conductive in response to the signal DTS. Now, since word line SWL1 is selected and address signal Acdr is at "H", transistors SQB14 and SQB12 are rendered conductive, and data on transfer gates 9606b and 9606a are transmitted to SRAM bit line pair *SBL1 and SBL1. Consequently, data are transferred to the corresponding SRAM memory cells. In Fig. 30, the reference character Ac represents the SRAM address in data transfer from the DRAM array to the SRAM array. Then, after the data transfer from the DRAM array to the SRAM array, the DRAM is once returned to the standby state. When the DRAM array is rendered active, the data which has been latched in latch circuit 9603 is transmitted to the DRAM array (global I/O lines GIO1 and *GI01). In this case, data transfer designating signal DTA attains "H", transfer gates 9604a and 9604b are rendered conductive, and data which has been latched in latch circuit 9603 is transmitted to global IO lines GIO1 and *GIO1. During data transfer from the latch circuit 9603 to the DRAM array, the SRAM array can be independently accessed. When the SRAM word line is selected, the SRAM bit line clamping signal SBLCL is set to "H" in order to surely set the amplifying transistor included in the amplifier circuit 9601 to conductive/non-conductive state during data transfer. In this case, a structure may be used in which clamping function is set to non-operative state only during data transfer, and the clamp signal SBLCL is always kept active when the SRAM array is accessed with data transfer not being carried out. A structure for block division or partial activation in which SRAM bit line pair is selected dependent on the even/odd row address may be used for writing/reading of data of the SRAM array. Data transfer operation between DRAM array and SRAM array will be discussed in more detail later. As described above, since one row of SRAM cells are divided into a plurality of groups and a plurality of word lines are arranged corresponding to respective groups for each row, an SRAM array which can have an arbitrary shape without changing memory structure of rows and columns can be provided. Since the shape of the SRAM array can be arbitrary selected, the degree of freedom in designing the SRAM array arrangement is improved. Therefore, an SRAM array having optimal shape for the DRAM array can be arranged, and therefore a semiconductor memory device containing a cache having high density and high degree of integration effectively utilizing chip area can be provided. Since the shape of the SRAM array can be changed without changing the memory structure, a semiconductor memory device which can be contained easily in a package having an arbitrary shape can be provided. [Pin Arrangement] Fig. 31 shows an example of a pin arrangement of a package housing the CDRAM having the array arrangement [Array Arrangement 3] shown in Fig. 10. As shown in Fig. 10, the CDRAM contained in the package of Fig. 31 includes a 4M bit DRAM and a 16K bit SRAM integrated on one chip. The CDRAM is housed in a 300mil TSOP (Thin Small Outline Package) of type II with lead pitch of 0.8mm, chip length of 18.4mm and 44 pins. The CDRAM has two data input/output modes, that is, D/Q separation and masked write. D/Q separation is a mode of inputting/outputting write data D and output data Q through separate pins. Masked writing is an operation mode in which write data D and read data Q are output through the same pin terminal, and writing of external data can be masked. In order to effectively supply the supply voltage to CDRAM and to facilitate layout of power supply interconnection, three pins are provided for each of the supply potential vcc and Gnd. More specifically, external supply potential Vcc is supplied to pins of the pin numbers 1, 11 and 33. The supply potential Vcc supplied to the pins 1, 11 and 33 may have the same voltage values as the operational supply potential Vcc. Alternatively, the external supply potential Vcc supplied to the pins 1, 11 and 33 may be lowered in the device to supply the operational supply potential. The ground potential GND is supplied to the pins of the numbers 12, 22 and 34. Pins of the numbers 11, 12, 33 and 34 at the center provide operational power supply for SRAM, while pins of the numbers 1 and 22 provide power supply for DRAM. A cache inhibiting signal CI# indicating cache access inhibition is applied to a pin terminal of the number 4. When the cache inhibition signal CI# is set to "L", access to the SRAM array is inhibited, and direct access (array access) to the DRAM array is allowed. A write enable signal W# indicating data writing mode is applied to the pin of the number 5. A chip select signal E# indicating that this chip is selected, is applied to a pin of the number 18. A command register designating signal CR# for designating the special mode is applied to a pin of the pin number 23. When the command register designating signal CR# is "L", command addresses Ar0 and Ar1 applied to the pins of the numbers 2 and 3 are rendered valid, enabling setting of the special mode (selection of a register). A cache hit signal CH# indicating a cache hit is applied to a pin of the pin number 27. If the cache hit signal CH# is "L", access to the cache (SRAM) is possible. An output enable signal G# indicating an output mode is applied to a pin of the number 40. A clock signal K is applied to the pin of the number 41. A refresh designating signal REF# designating refreshing of the DRAM array is applied to a pin of the number 44. When the refresh designating signal REF# attains to "L", automatic refreshing of the DRAM array inside is carried out in the cycle. When self refreshing is designated, the pin terminal of the pin number 44 is switched to an output terminal. When self refreshing is effected, a signal BUSY# indicating execution of self refreshing is output from the pin terminal of the pin number 44. It becomes possible to know the timing of the self refreshing outside the CDRAM by this signal BUSY#, and therefore self refreshing can be utilized in a normal cycle. Different data are applied to the pins of the numbers 9, 10, 13, 14, 31, 32, 35 and 36 dependent on the two different operation modes, that is, D/Q separation and masked write. The operation modes of D/Q separation and masked write are set by a command register (which will be described later). In masked write mode, pins of the numbers 10, 13, 32 and 35 are used as common data input and output terminals for commonly carrying out data input/output. Pins of the numbers 9, 14, 31, 35 and 36 receive masked write designating data M0, M1, M2 and M3 for indicating which data applied to which input/output pins should be masked, respectively. In D/Q separation mode, pins of the numbers 9, 14, 31 and 36 are used as pins for inputting write data D0, D1, D2 and D3. Pins of the numbers 10, 13, 32 and 35 are used as data output pins for outputting read data Q0, Q1, Q2 and Q3. SRAM addresses Ac0 to Ac11 and DRAM addresses (array addresses) Aa0 to Aa9 are applied through separate pin terminals and independent from each other. In the pin arrangement shown in Fig. 31, external operation control signals generally used in a standard DRAM, that is, row address strobe signal/RAS and column address strobe signal/CAS are not used. In the CDRAM contained in the package of Fig. 31 (see Fig. 10), data and control signals are input in response to a rising edge of an external clock signal K. [Internal Function] In this section, internal functions of CDRAM are briefly described. (i) Fig. 32 is a block diagram showing internal structure of the CDRAM chip housed in a package of Fig. 31. The block arrangement shown in Fig. 31 is for the purpose of functionally showing the internal structure of the CDRAM, and it should be noted that the structure shown in this figure is not the same as the actual layout. Referring to Fig. 32, a CDRAM includes a DRAM 100 and a SRAM 200. DRAM 100 comprises a 4M bit DRAM array 101; a DRAM row decoder block 102 for decoding an applied internal row address for the DRAM and for selecting 4 rows from DRAM array 101; a DRAM column decoder block 103 for decoding applied internal column address for DRAM and for selecting one column from each of the selected 4 rows in a normal operation mode (array access); and a block 104 including DRAM sense amplifiers DSA for detecting and amplifying data of the memory cells connected to the selected rows, and selecting gates SG responsive to a column selecting signal from block 103 for selecting 16 bits of DRAM array 101 in a data transfer mode and for selecting 4 bits of memory cells in an array access mode. SRAM 200 comprises an SRAM array 201 having the capacity of 16K bits; a SRAM row decoder block 202 for decoding an internal row address for the SRAM and for selecting 4 rows from SRAM array 201; and a column decoder /sense amplifier block 203 including SRAM column decoders and SRAM sense amplifiers for decoding the internal column address for the SRAM, selecting 1 bit from each of the selected 4 rows and connect the same to an internal data bus 251, and for detecting and amplifying information of the selected SRAM cells in data reading. A bi-directional transfer gate circuit 210 is provided between DRAM 100 and SRAM 200. Referring to Fig. 32, the gate circuit 210 may be connected to an output (input) of the column decoder/sense amplifier block 203, as in the arrangement of Fig. 10. However, in Fig. 32, data input/output to and from DRAM 100 are carried out through the common data bus 251 in the array access mode, and therefore the common data bus 251 is shown as coupled to bi-directional transfer gate circuit 210. The CDRAM in accordance with the present invention further comprises a control clock buffer 250 receiving externally applied control signals G#, W#, E#, CH#, CI#,REF# and CR# to generate internal control signals G, W, E, CH, CI, REF and CR; an address buffer 252 for generating an internal address int-Aa for the DRAM and an internal address int-Ac for the SRAM; and a clock buffer 254 for buffering an externally applied clock signal K. Control clock buffer 250 takes an applied control signal and generates an internal control signal in response to a rise of an internal clock from clock buffer 254. An output from clock buffer 254 is also applied to address buffer 252. Address buffer 252 takes an externally applied addresses Aa and Ac which are applied when the internal chip enable signal E is active at a rising edge of the clock K from the clock buffer 254 and generates internal addresses int-Aa and int-Ac. The CDRAM includes a refresh circuit 290 for refreshing memory cells in DRAM array 100. Refresh circuit 290 includes a counter circuit 293 which is activated in response to internal refresh designating signal REF for generating a refresh address of the DRAM array; and an address multiplex circuit 258 for applying either a refresh address from counter circuit 256 or an internal row address from address buffer 252 to DRAM row decoder block 102 in response to a switching signal MUX from a refresh control circuit 292. Refresh control circuit 292 is driven in response to a refresh request from an automatic refresh mode detecting circuit 291. The refresh operation will be described later. The CDRAM further comprises a DRAM array driving circuit 260 responsive to the internal control signals E, CH, CI and REF for generating various control signals for driving DRAM 100; a transfer gate controlling circuit 262 responsive to the internal control signals E, CH and CI for generating signals for controlling transfer operation of bi-directional transfer gate 210; and a SRAM array driving circuit 264 responsive to internal chip select signal E for generating various control signals for driving SRAM 200. The CDRAM in accordance with the present invention further comprises a command register 270 which is activated in response to an internal control signal CR for generating a command CM for designating operation mode of the CDRAM in response to external write enable signal W# and to command addresses Ar (Ar0 and Ar1); a data input/output control circuit 272 for controlling data input/output in accordance with the internal control signals G, E, CH, CI and W and to the special mode command CM; an input/output circuit 274 formed of an input/output buffer and an output register for inputting/outputting data between common data bus 251 and the outside of the device. An output register is provided in the input/output circuit 274 for realizing a latched output mode and a registered output mode, which are the special modes of the CDRAM. Data input/output control circuit 272 sets input/output timing of data in accordance with the mode designated by the special mode command CM as well as the manner of input/output of data. In Fig. 32, manners of data input/output pins in masked write mode is shown as an example. The CDRAM further includes an additional function control circuit 299 for realizing various functions. Functions realized by additional function control circuit 299 will be described in detail later. The function includes prohibition of generation of internal clocks at the time of standby, switching between autorefresh/self refresh, switching of address generating source in burst mode, and the like. Structures of various circuits will be described in the following. Basic constructions, arrangements and operations of CDRAM of the present invention have been described. Various modifications and additional functions can be considered, which will be described as a second embodiment in the following. In the second embodiment, control signal CI# (cache access inhibiting signal) and a command set/burst enable signal CR#/BE# applied to the pin number 4 are defined as control signals CC1 and CC2. These signals have the same function as in the first embodiment described above, and only the names of the signals are changed. [low power and high speed operations modes] It is desirable to change the clock frequency according to the situation of accessing to CDRAM in terms of power consumption. For example, when only DRAM in CDRAM is successively accessed, no fast clock is needed as its operating speed is slow. So, a low clock is preferable in such situation in terms of low power consumption. If SRAM cache is successively accessed, a fast clock should be applied in terms of fast operationability. CDRAM should operate as fast as possible with least power consumption regardless of clock frequency. In order to implement such operating characteristics, DRAM address strobing timing is varied according to the clock frequency. More specifically, CDRAM is adapted to include two operation modes, i.e. low power consumption mode in which DRAM row address is latched at a leading edge of the clock K while DRAM column address is latched at the following trailing edge of the clock K, and high speed mode in which DRAM row address is latched at a leading edge of the clock K while DRAM column address is latched at another leading edge of the clock K. In the following, structure for implementing such changing of address strobe timing is described with reference to Figs. 33 through 45. Fig. 33 is a block diagram showing functionally the whole structure of the CDRAM in accordance with the second embodiment. In the CDRAM shown in Fig. 33, an address generating circuit 360 which takes external address signals Ac and Aa and generates internal addresses int-Ac and int-Aa in accordance with internal chip enable signal E, internal cache hit designating signal /CH and an internal clock signal int-K from clock buffer 254 is provided in place of address buffer 260 shown in Fig. 32. By adjusting timings of taking addresses Ac and Aa in address generating circuit 360, the CDRAM 5000 can be set to either one of low power consumption mode and high speed operation mode. A row address signal and a column address signal are externally applied time divisionally to provide the DRAM internal address signal int-Aa applied to DRAM row decoder 102 and DRAM column decoder 103. By adjusting timings for taking these address signals, the speed of operation of DRAM can be adjusted. Address generating circuit 360 generates an internal row address signal and an internal column address signal while adjusting the timing for taking the external DRAM address signal Aa in accordance with an internal control signal K (int-K) and internal control signals E and /CH. Fig. 34 is a diagram of signal waveforms showing the operation of circuitry related to the portion generating the internal address signal int-Aa for the DRAM of this address generating circuit 360. The operation of address generating circuit 360 will be described with reference to Fig. 34. An operation mode in which high speed operation is carried out with low power consumption (hereinafter referred to as a low power consumption mode) is set by setting, at time T1, the internal control signals E and CH to "H" and "L", respectively, at a rising edge of the clock signal K. At this time, address generating circuit 360 takes external address signal Aa as an internal row address signal int·Aar in response to the rising edge of the clock signal K. Then, it takes external address signal Aa in response to a falling edge of the clock K and generates an internal column address signal int·Aac. The details of this operation is as follows. At time T1, the external address signal Aa has been already applied to address generating circuit 360 at the rising edge of the external clock signal K. At this time, in accordance with the combination of the states of the signals E and CH, an internal row address strobe signal /RAS for taking a row address signal is generated and set to an active state of "L". Since internal row address strobe signal /RAS is a signal of active "L", address generating circuit 360 latches external address signal Aa and thereafter continuously generates internal row address signal int·Aar and applies the same to DRAM row decoder 102 (time T2). When internal row address strobe signal /RAS is at "L" at a falling edge of the external clock signal K at time T3, internal column address strobe signals CAL and /CAL are generated. In response, address generating circuit 360 takes and latches the external address signal Aa as an internal column address signal (time T4), and applies the same to DRAM column decoder 103. The scheme shown in Fig. 34 which DRAM row address signal int·Aar and DRAM column address signal int·Aac are taken by a single pulse of clock signal K enables faster operation of the DRAM compared with the structure of a common clock synchronized type semiconductor memory device such as shown in Fig. 35 in which operation is effected only at the rising edge of the external clock signal. Namely, as shown in Fig. 35, in the low power consumption mode, the row address signal and the column address signal for the DRAM are taken at time TA, at which the operation for the DRAM is started. If all operations are determined at the same timing (rising edge) of the clock signal K as in the conventional clock synchronized type semiconductor memory device, the column address signal for the DRAM is taken at the rising edge of the next clock signal K (time TB), and from this point of taking the column address signal, the DRAM starts its operation. Therefore, even when power consumption is given priority than the speed of operation of the CDRAM and the period of the clock signal K is made longer or the clock signal K is generated intermittently in order to reduce power consumption of the CDRAM, the start point of operation of the DRAM can be made earlier by the time period (TB-TA) between TB and TA, compared with the structure of the conventional clock synchronized type semiconductor memory device. Namely, a clock synchronized type semiconductor memory device which can be operated at high speed even in the low power consumption mode can be provided. As shown in Fig. 33, internal operations of CDRAM are all controlled by the external control signals. Internal row address strobe signal /RAS and internal column address strobe signals CAL and /CAL shown in Fig. 34 are control signals which simply determines the timing of taking DRAM addresses in address generating circuit 360. Assume that the external clock signal K is generated intermittently in order to further reduce power consumption, while period of the external clock signal K is made longer so as to meet the demand of low power consumption. In this case also, by resetting the taking operation of address generating circuit 360 by utilizing internal row address strobe signal /RAS, a CDRAM which can minimize an influence of possible noise generated in such intermittent operation can be provided. Here, the intermittent operation mode corresponds to a mode in which period of the clock signal K is made longer temporarily, or a mode in which period of the external clock signal K is variable. A margin for noise pulses generated when the period of the external clock signal is long will be described. Fig. 36 is a diagram for comparison between the conventional operation mode and the low power consumption mode. In the low power consumption mode, if a noise pulse NZ is generated in the external clock signal K, external address signal Aa is taken in the CDRAM at time TC, then external address signal Aa is taken as an internal column address signal at time TD, and the DRAM starts its operation from time TD. However, if the structure is adapted to reset address generating circuit 360 after the lapse of a prescribed time period, the operation of the DRAM terminates automatically at time TE, and malfunction caused by the noise pulse NZ can be prevented. More specifically, when external clock signal K rises at time TEa, the operation of the DRAM has been already completed and it is returned to the precharge state. Accordingly, operations in accordance with the combinations of the states of various control signals at the rising edge of the external clock signal K can be carried out, and therefore a CDRAM having sufficient margin for the malfunction of the noise pulse NZ can be provided. When the row address signal and the column address signal are to be taken only at the rising edge of the external clock signal K as in the normal mode, and if the row address signal is erroneously taken in response to a rising edge of the noise pulse NZ at time TC, the CDRAM is kept in a waiting state for the input of the column address signal until the next rising point TEa of the external clock signal K. At this time, the CDRAM takes address signal Aa, at time TEa when the accurate external clock signal K rises, as a column address signal and starts its operation. Therefore, when an accurate external clock signal K is applied, an erroneous operation is effected. Namely, because of the longer period of the external clock signal K to reduce power consumption, margin for the noise is lost in the conventional operating mode. As described above, by resetting the DRAM after the lapse of a predetermined time period (for example, time required till completion of the sensing operation in the DRAM array) from taking of the DRAM column address signal in address generating circuit 360, sufficient margin for the noise can be provided even if the external clock signal K is applied intermittently. Fig. 37 shows an example of a specific structure of address generating circuit 360 shown in Fig. 33 . Referring to Fig. 37 , address generating circuit 360 includes a row address strobe signal generating circuit 2601 responsive to control signals E and CH and to external clock signal K for generating an internal row address strobe signal /RAS; a column address strobe signal generating circuit 2602 responsive to internal row address strobe signal /RAS from row address strobe signal generating circuit 2601 and to clock signal K for generating internal column address strobe signals CAL, /CAL; a row address latch 2603 responsive to internal row address strobe signal /RAS for taking external address signal Aa to generate an internal row address signal; a column address latch 2604 responsive to internal row address strobe signal /RAS and internal column address strobe signals CAL and /CAL for taking external address signal Aa to generate an internal column address signal; and a reset signal generating circuit 2605 responsive to internal row address strobe signal /RAS for generating a reset signal after a lapse of a predetermined time period (for example, period of active state of the DRAM) to apply the same to row address strobe signal generating circuit 2601. Here, external clock signal K and internal clock signal int-K are substantially the same signal, and in the following, internal clock signal is simply referred to as K. The row address strobe signal generating circuit 2601 generates internal row address strobe signal /RAS when control signal E is at "H" and control signal CH is at "L" at a rising edge of (internal) clock signal K. Column address strobe signal generating circuit 2602 generates internal column address strobe signals CAL, /CAL in response to a falling edge of clock signal K. Column address strobe signal generating circuit 2602 is reset when internal row address strobe signal /RAS rises to inactive "H". Row address latch 2603 is set to a latch state when internal row address strobe signal /RAS attains "L" and outputs continuously the latched signal as internal row address signal regardless of the state of external address signal Aa. Column address latch 2604 takes external address Aa in response to internal row address strobe signal /RAS, and outputs applied address signal continuously as internal column address signal in response to column address strobe signals CAL, /CAL. The address generating circuit shown in Fig. 37 is related to DRAM addresses. At a time of cache hit in which SRAM array is accessed, the row address signal and the column address signal are simultaneously applied to SRAM address generating circuit (not shown). Therefore, the row address signal and the column address signal for SRAM are taken at the same timing of the external clock signal. The operation of the address signal generating circuit shown in Fig. 37 is the same as that described with reference to the diagram of signal waveforms of Fig. 106, and therefore description thereof is not repeated. Specific structure of respective circuits in Fig. 37 will be described. Fig. 38 shows a specific structure of row address strobe signal generating circuit 2601 shown in Fig. 37 Referring to Fig. 37 , row address strobe signal generating circuit 2601 includes an AND circuit 2610 receiving the clock signal K, control signal E and control signal /CH (inverted signal of CH); and an OR circuit 2611 receiving at one input, the output from AND circuit 2610, and receiving at the other input, a Q output of a flipflop (FF) 2612. Flipflop 2612 includes a set input S receiving an output from OR circuit 2611, a reset input R receiving a reset signal RS from reset signal generating circuit 2605 shown in Fig. 37, a Q output and /Q output. Q output and /Q output provide signals complementary to each other. Internal row address strobe signal /RAS is generated from /Q output from flipflop 2612. Generally, flipflop 2612 has a circuit structure including two NOR circuits cross coupled to each other. The flipflop 2612 is set when "H" signal is applied to set input S, and outputs a signal at "L" from /Q output. When a signal at "H" is applied to reset input R, it is reset and signal output from /Q attains "H". Operation of row address strobe signal generating circuit 2601 shown in Fig. 38 will be described with reference to the diagram of waveforms of Fig. 34. When control signal E is at "H" and control signal C is at "L" when clock signal K rises to "H", then the output from AND circuit 2610 attains to "H". Consequently, the output from OR circuit 2611 rises to "H" and flipflop 2612 is set. Then, internal row address strobe signal /RAS provided as an output from /Q output of flipflop 2612 falls to "L". At this time, Q output of flipflop 2612 attains "H" and output from OR circuit 2611 attains "H". After a lapse of a predetermined time period from the generation of internal row address strobe signal /RAS, a reset signal is generated from reset signal generating circuit 2605 (see Fig. 37 ), flipflop 2612 is reset and row address strobe signal /RAS rises to "H". Therefore, the row address generating circuit 360 is ready to receive the next address. When a reset signal of "H" is applied while "H" signal being applied to set input S of flipflop 2612 having NOR gates cross coupled to each other, Q output and /Q output may both attain "L". At this time, since Q output of flipflop 2612 is applied to one input of OR circuit 2611, the output of OR circuit 2611 attains "L". If reset signal RS has an appropriate pulse width, flipflop 2612 is kept at a stable reset state. In order to ensure operation of flipflop 2612 at this time, a one shot pulse signal may be generated when Q output of flipflop 2612 attains to "H" to apply the one shot pulse signal to OR circuit 2611 in place of Q output of flipflop 2612. Alternatively, a circuit generating a one shot pulse having an appropriate pulse width in response to an output from AND circuit 2610 may be provided to apply the pulse from this one shot pulse generating circuit to the set input of flipflop 2612. Fig. 39 shows an example of a specific structure of column address strobe signal generating circuit 2602 shown in Fig. 37 . Referring to Fig. 39, the column address strobe signal generating circuit 2602 includes an AND circuit 2621 receiving at its one input clock signal K; an inverter circuit 2622 receiving internal row address strobe signal /RAS; and a flipflop 2623 having a set input /S receiving an output from AND circuit 2621, a reset input /R receiving an output from inverter circuit 2622, a Q output and /Q output. /Q output of flipflop 2623 is applied to the other input of AND circuit 2621. Column address strobe signal /CAL is generated from /Q output of flipflop 2623, and column address strobe signal CAL is generated from the inverter circuit 2624 receiving /Q output of flipflop 2623. Flipflop 2623 includes two NAND circuits cross coupled to each other, for example. It is set when a signal at "L" is applied to set input /S, and it is reset when a signal at "L" is applied to reset input /R. The operation will be described. Assume that flipflop 2623 is reset. At this time, /Q output of flipflop 2623 is at "H", and output from AND circuit 2621 is at "H" in response to the rise of clock signal K. When clock signal K falls to "L", the output from AND circuit 2621 falls to "L", flipflop 2623 is set, column address strobe signal /CAL from /Q output thereof attains "L" and column address strobe signal CAL from inverter circuit 624 attains "H". Row address strobe signal /RAS attains to "L" in response to the rise of clock signal K, and output of inverter circuit 2622 attains "H". After a lapse of a predetermined time period, internal row address strobe signal /RAS rises from "L" to "H", and the output from inverter circuit 2622 falls to "L". Consequently, flipflop 2623 is reset, column address strobe signal /CAL attains "H" and column address strobe signal CAL attains "L". At this time, signals to set input /S and reset input /R of flipflop 2623 may be both "L". However, such state can be prevented by providing a structure for resetting /Q output of flipflop 2623. A circuit structure for setting Q output of flipflop 2623 as well may be provided. Alternatively, a structure for generating a one shot pulse signal having a predetermined pulse width in response to a fall of clock signal K to provide the same to set input /S of flipflop 2623 may be used as a simple method. At this time, the generated one shot pulse signal falls from "H" to "L" upon generation. Fig. 40 shows an example of a specific structure of row address latch 2603 shown in Fig. 37. Referring to Fig. 40 , row address latch 2603 includes an inverter circuit 2631 receiving external address signal Aa; a clocked inverter 2632 receiving an output from inverter circuit 2631; an inverter circuit 2633 receiving an output from clocked inverter 2632; and a clocked inverter 2634 receiving an output from inverter circuit 2633. Operation of clocked inverter 2632 is controlled by internal row address strobe signals RAS and /RAS. When internal row address strobe signal RAS is at "H" and internal row address strobe signal /RAS is at "L", clocked inverter 2632 is set to an output high impedance state, which is an inactive state. When internal row address strobe signal RAS is at "L" and internal row address strobe signal /RAS is at "H", clocked inverter 2632 is rendered active, and it inverts an output from inverter circuit 2631 and transmits the same to a node N10. Clocked inverter 2634 is rendered active when internal row address strobe signal /RAS is at "L" and internal row address strobe signal RAS is at "H" and it functions as an inverter. When internal row address strobe signal RAS is at "L" and internal row address strobe signal /RAS is at "H", clocked inverter 2634 is set to an output high impedance state, which is an inactive state. Therefore, when clocked inverter 2634 is active, inverter circuit 2633 and clocked inverter 2634 constitute a latch circuit, and continuously outputs signal potential appearing on the node N10. Internal row address signal int·Ara is generated from node N10. The operation will be described in the following. When internal row address strobe signal /RAS is at inactive "H", clocked inverter 2632 functions as an inverter. At this time, clocked inverter 2634 is at the output high impedance state. Therefore, at this time, external address signal Aa is transmitted to node N10. When clocked inverter 2632 is set to the output high impedance state, and clocked inverter 2634 is rendered active to function as an inverter. At this state, signal potential appearing at node N10 when the internal row address strobe signal /RAS has been "H" is latched by inverter circuit 2633 and clocked inverter 2634, and it is continuously output as internal row address signal int·Ara. Fig. 41 shows an example of a specific structure of column address latch 2604 shown in Fig. 37. Referring to Fig. 4L, column address latch 2604 includes an NOR circuit 2641 receiving at one input external address signal Aa and at the other input internal row address strobe signal /RAS; a clocked inverter 2642 receiving an output from NOR circuit 2641; an inverter circuit 2643 receiving an output from clocked inverter 2642; and a clocked inverter 2644 receiving an output from inverter 2643. Clocked inverter 2642 is rendered active and serves as an inverter when internal column address strobe signal CAL is at "L" and internal column address strobe signal /CAL is at "H". When internal column address strobe signal CAL is at "H" and internal column address strobe signal /CAL is at "H", clocked inverter 2642 is rendered inactive and set to the output high impedance state. Clocked inverter 2644 is rendered active and serves as an inverter when internal column address strobe signal /CAL is at "L" and internal column address strobe signal CAL is at "H". When internal column address strobe signal CAL is at "L" and internal column address strobe signal /CAL is "H", clocked inverter 2644 is rendered inactive and set to the output high impedance state. When clocked inverter 2644 is active, inverter circuit 2643 and clocked inverter 2644 constitute a latch circuit, which latches a signal potential appearing at node N20. An internal column address signal int·Arc is generated from node N20. The operation will be described. When internal row address strobe signal /RAS is at "H", an output from NOR circuit 2641 is at "L". Since internal column address strobe signals CAL and /CAL have not yet been generated at this time, clocked inverter 2642 serves as an inverter and transmits a signal at "H" to node N20. When internal row address strobe signal /RAS falls to "L", NOR circuit 2641 functions as an inverter. At this time, NOR circuit 2641 outputs an inverted signal of external address signal Aa. After a predetermined time period from a fall of the internal row address strobe signal /RAS to "L", internal column address strobe signals CAL and /CAL are generated, clocked inverter 2642 is set to the output high impedance state, and clocked inverter 2644 is rendered active and functions as an inverter. Consequently, signal potential appearing at node N20 when internal column address strobe signals CAL and /CAL are generated is continuously output as internal column address signal int•Arc. The structures shown in Figs. 40 and 41 correspond to portions related to 1 bit of external address signal Aa. The circuit shown in Figs. 40 and 41 are provided for each bit of each external address signal Aa. Reset signal generating circuit 2605 shown in Fig. 37 may have any circuit structure provided that reset pulse RS is generated after a predetermined time period from detection of a fall of internal row address strobe signal /RAS to "L". The reset signal generating circuit can be readily realized by a circuit structure including a circuit for providing a delay in row address strobe signal /RAS and a circuit for generating a one shot pulse signal in response to the output from the delay circuit. The reset signal generating circuit 2605 may have a structure that the reset signal is generated from DRAM array driving circuit 260 shown in Fig. 33. At this time, DRAM array driving circuit 260 generates a signal for activating circuitry of a portion related to row selecting operation of the DRAM array, and the reset pulse may be generated at a time point when the operation of the circuitry related to row selection is completed. For example, a structure generating reset pulse RS after a predetermined time period from the generation of a sense amplifier activating signal for sensing operation in DRAM array 101 may be employed. A structure for setting CDRAM to operation modes dependent on intended use, that is, high speed operation mode or low power consumption mode, will be described. Command registers are used for setting such modes. As shown in Fig. 42, operation mode of the CDRAM is set dependent on data values of data input pins DQ3 (D3) and DQ2 (D2) when a register WR0 is selected. When DQ3 (D3) and DQ2 (D2) are both set to "0", a first high speed mode is designated. By setting DQ3 (D3) and DQ2 (D2) to "0" and "1", respectively, a low power consumption mode is designated. When DQ3 (D3) and DQ2 (D2) are set to "1" and "0", respectively, a second high speed operation mode is designated. The input terminal is represented as DQ (D) when register WR0 is set, since pin function differs dependent on whether DQ separation mode is designated by a register RR1 or masked write mode is selected by a register RR0. Operation modes realized by data AB applied to data DQ3 (D3) and DQ2 (D2) of register WR0 will be described. Fig. 43 shows a high speed operation mode of the CDRAM. The first high speed operation mode is selected by setting upper 2 bits of data AB of register WR0 both to "0". In this state, a row address signal (ROW) is taken at first at a rising edge of the first clock signal K (#1) of the clock signal K, and then, a column address signal (COL) is taken at a rise of a third clock signal K (#3). The operation of the CDRAM is started from a falling edge of the third clock signal #3. The second high speed operation mode is selected by setting the upper 2 bits of data AB of the command register WR0 to "1" and "0". In the second high speed operation mode, row address signal (ROW) is taken at a rising edge of the first clock signal K (#1), and column address signal (COL) is taken at a rising edge of the successively applied second clock signal K1 (#2). Therefore, when the DRAM array is to be accessed at a cache miss of the CDRAM or the like, speed of operation can be set at an optimal value dependent on the intended use. Since time required for accessing the DRAM array can be set at an optimal value dependent on the object of processing, flexible system structure is enabled. Fig.44 is a diagram of signal waveforms showing an operation in which CDRAM operates in the low power consumption mode. The low power consumption mode is designated by setting upper 2 bits of AB of command register WR0 shown in Fig. 114 to "0" and "1", respectively. In the low power consumption mode, row address signal (ROW) is taken at a rising edge of clock signal K, and column address signal (COL) is taken at a falling edge of clock signal K. In this case, row and column address signals are taken responsive to a single pulse. Even if the clock signal K is generated intermittently or the period of the clock signal K is made longer temporarily and therefore the period of the clock is made longer, row and column address signals can be taken by a single clock signal. Since DRAM starts its operation immediately after the column address signal is taken, a CDRAM which operates at high speed with low power consumption can be provided. Fig. 45 shows a circuit structure for setting a timing for taking external address signal Aa dependent on the operation mode. The circuit structure shown in Fig. 35 is used as column address strobe signal generating circuit 2602 shown in Fig. 37 . More specifically, the column address strobe signal generating circuit shown in Fig. 45 is used instead of column address strobe signal generating circuit shown in Fig. 39.. The above described respective circuits may be used for other circuit structures. Referring to Fig. 45, column address strobe signal generating circuit 2602' includes an AND circuit 2701 receiving, at its one input, clock signal K; and a flipflop 2702 receiving an output from AND circuit 2701 at its set input /S1 and internal column address strobe signal /RAS at its reset input /R1 through an inverter circuit 2709. An output /Q1 of flipflop 2702 is applied to the other input of AND circuit 2701. Flipflop 2702 is set or reset when a signal at "L" is applied to input /S1 or /R1. Circuit 2602' further includes an OR circuit 2703 receiving at one input the clock signal K, an OR circuit 2710 receiving output /Q1 of flipflop 2702 and internal row address strobe signal /RAS; and a flipflop 2704 having a set input S2 receiving an output from OR circuit 2703 and a reset input R2 receiving an output from OR circuit 2710. An output Q2 of flipflop 2704 is applied to the other input of OR circuit 2703. Flipflop 2704 is set when an output from OR circuit 2703 rises to "H", and it is reset when an output from OR circuit 2710 rises to "H". Circuit 2602' further includes an AND circuit 2705 receiving, at one input, clock signal K; an AND circuit 2711 receiving an output Q2 of flipflop 2704 and internal row address strobe signal RAS from inverter circuit 2709; and a flipflop 2706 receiving at a set input /S3 an output from AND circuit 2705 and at a reset input /R3 an output from AND circuit 2711. An output Q3 of flip flop 2706 is applied to the other input of AND circuit 2705. Flipflop 2706 is set in response to a fall of a signal applied to set input /S3, and it is reset in response to a fall of a signal applied to reset input /R3. Circuit 2602' further includes an OR circuit 2707 receiving, at one input, clock signal K; an OR circuit 2712 receiving an output /Q3 of flipflop 2706 and internal row address strobe signal /RAS; and a flipflop 2708 receiving at a set input S4 an output from OR circuit 2707 and at a reset input R4 an output from OR circuit 2712. An output Q4 of flipflop 2708 is applied to the other input of OR circuit 2707. Flipflop 2708 is set in response to a rise of a signal applied to set input S4, and it is reset in response to a rise of a signal applied to reset input R4. Column address strobe signal generating circuit 2602' further includes an AND circuit 2715 receiving an Q2 output from flipflop 2704 and data B (corresponding to DQ2 shown in Fig. 42) set in register WR0; an inverter circuit 2713 receiving an output /Q1 from flipflop 2702; an AND circuit 2714 receiving an output from inverter 2713 and data A (corresponding to data DQ3 shown in Fig. 104) set in register WR0; an OR circuit 2716 receiving an output from AND circuit 1714, an output from AND circuit 2715 and an output Q4 of flipflop 2708; and an inverter circuit 2717 receiving an output from OR circuit 2716. Column address strobe signal CAL is generated from OR circuit 2716, and column address strobe signal /CAL is generated from inverter circuit 2717. The operation will be described with reference to the diagram of signal waveforms of Fig. 46 . The operation when low power consumption mode is set will be described. At this time, data A is "0" ("L"), and data B is "1" ("H"). In this state, an output from AND circuit 2714 is "L". Flipflops 2702, 2704, 2706 and 2708 are at reset state. When external clock signal K rises for the first time, an output from AND circuit 2701 attains "H". At this time, in flipflop 2702, only a signal applied to set input /S1 rises from "L" to "H", and therefore it is kept at the reset state. In response to a rise of clock signal K, internal row address strobe signal /RAS falls to "L". At this time, since flipflop 2702 is kept at the reset state, output /Q1 of flipflop 2702 is at "H", and therefore output from OR circuit 2710 is also at "H". Even when output from OR circuit 2703 rises to "H" in response to a rise of clock signal K, flipflop 2704 is set by the output from OR circuit 2710, so that the output Q2 attains "H". At this time, the output from AND circuit 2711 is at "L", and the output from OR circuit 2712 is at "H" (the output /Q3 of flipflop 2703 is at "H"), so that flipflops 2706 and 2708 are also maintained at the same state as the reset state. Therefore, in this state, an output from AND circuit 2715 is at "L" and the output from OR circuit 2716 is also at "L". When clock signal K falls to "L", the output from AND circuit 2701 falls to "L", flipflop 2702 is set, and output /Q1 of flipflop 2702 falls from "H" to "L". In response, the output from inverter circuit 2713 rises to "H". Since data B is at "H" potential level, the output from AND circuit 2715 rises to "H" in response to the fall of output /Q1 of flipflop 2702 to "L". Consequently, the output from OR circuit 2716 rises, internal column address strobe signal CAL attains "H" and internal column address strobe signal /CAL falls to "L". Consequently, low power consumption mode in which row address signal and column address signal are taken at the rising and falling edges of one pulse (#1) of clock signal K can be realized. A second high speed operation mode in which a row address signal and a column address signal are taken at rising edges of respective clock signals will be described. At this time, data A is set to 1 ("H") and data B is set to 0 ("L"). At this time, the output from AND circuit 2715 is fixed at "L". The output from AND circuit 2714 attains "H" when output Q2 of flipflop 2704 rises to "H". Output Q2 of flipflop 2704 rises to "H" when flipflop 2704 is released from the reset state and the output from OR circuit 2703 rises to "H". More specifically, flipflop 2704 is set when the output of OR circuit 2703 attains "H" in response to a rise of clock signal K (#2) which is applied after flipflop 2702 is set and /Q1 output thereof attains "L". Therefore, in the second high speed operation mode, column address strobe signal CAL is set to "H" and internal column address strobe signal /CAL is set to "L" at a rising edge of the second clock signal K (#2). Thus the second high speed operation mode is realized. A first high speed operation mode in which column address is taken at a rising edge of the third clock signal K (#3) will be described. In this case, data A and B are both set to "0". In this state, outputs from AND circuits 2714 and 2715 are both "L". Output Q2 of flipflop 2704 rises to "H" in response to the second rise (#2) of the clock signal K. Consequently, the output from AND circuit 2711 attains "H" and flipflop 2706 is released from the reset state. In response to the second fall (#2) of the clock signal K, the output from AND circuit 2705 falls to "L", flipflop 2706 is set, and output Q3 of flipflop 2706 falls to "L". Since output /Q3 of flipflop 2706 falls to "L", the output from OR circuit 2712 attains "L", and flipflop 2708 is released from the reset state. When the output from OR circuit 2707 rises to "H" at a third rise (#3) of the clock signal K, the flipflop 2708 is set, and the potential of output Q4 thereof rises to "H". Consequently, the output of OR circuit 2716 attains "H". Thus the first high speed operation in which row address signal is taken at the rise of the first clock signal K and column address signal is taken at a rise of the third clock signal K is realized. In any of the above described operation cycle modes, when internal row address strobe signal /RAS rises to "H" after a lapse of a predetermined time period, flipflops 2702, 2704, 2706 and 2708 are all reset. Flipflops 2702, 2704, 2706 and 2708 have the same structure as flipflops 2612 and 2623 shown in Figs. 110 and 111. As described above, since the CDRAM operates in synchronization with external clock signal K, delay of cycle time derived from skews of addresses and the like can be prevented, and accurate control can be effected, compared with a method in which internal clock signals are generated by using an address transition detecting circuit. In addition, by arbitrarily setting timings for taking the column address of the DRAM, a CDRAM which can flexibly corresponds to applications in which low power consumption is given priority and to applications in which high speed operation is given priority can be provided. The structure for changing timings for taking the column address is not limited to apply the CDRAM and any semiconductor memory device of address multiplexing type which operates in synchronization with clock signals can be used to provide the same effect. A structure in which a row address signal and a column address signal are applied to separate pin terminals may be used.

Claims: A semiconductor memory device including an array (101) having a plurality of memory cells (DMC) and an address generating means (360) adapted to receive an external address signal (Aa) applied from an external unit external to the memory device in synchronization with a clock signal (K) having first and second transitions between a first level and a second level to generate an internal address signal designating a memory cell in said array when enabled; the memory device comprising setting means (270) responsive to an external address incorporation timing designating signal for generating a mode select signal (A, B), and said address generating means comprises timing supply means (2601, 2602) responsive to an access instruction signal (E, /CM) from the external unit, said mode select signal and to said clock signal for supplying a timing signal (/RAS, CAL, /CAL) determining a timing for incorporating the external address signal such that said device can operate in two modes and wherein said external address signal (Aa) has column and row address signals (RAS, CAS) time-division multiplexed for application to the memory device, and wherein said timing supply means (2601, 2602) comprises first address control means (2601) responsive to a first transition from the first level to the second level of said clock signal (K), hereinafter called first first transition, and the access instruction signal (E, /CH) for supplying a first address load signal (/RAS), and second address control means (2602') receiving said clock signal and responsive to said mode select signal for supplying a second address load signal (/CAS, CAL, /CAL) responsive to one of a plurality of successive first and second transitions of said clock signal subsequent to said first first transition, and wherein said address generating means (360) includes first address latch means (2603) coupled to receive said external address signal for supplying a first internal address signal (intAra) in response to said first address load signal, and second address latch means (2604) coupled to receive said external address signal for supplying a second internal address signal in response to said second address load signal, wherein the first transition for supplying said first address load signal is predetermined. A device according to claim 1, wherein said setting means (270) includes registers (WRO) for receiving and storing said external address incorporation timing designating signal to generate said mode select signal. A device according to claim 1, wherein said clock signal has a first transition changing from a first level to a second level and a second transition changing from the second level to the first level, and wherein said address generation means (360) comprises means (2601, 2602, 2603, 2604) for incorporating external address signals at different kinds of transitions of said clock signal to generate corresponding internal address signals. A device as claimed in any preceding claim, wherein said external address signal is time-division multiplexed into only a first address signal (intAra) and a second address signal (intArc), said first and second address signals in combination designating a memory cell in said array. A device according to claim 4, wherein said array (101) has the plurality of memory cells (DMC) arranged in rows and columns, and wherein said first address signal (intAra) designates a row of memory cells in said array, and said second address signal (intArc) designates a column of memory cells in said array. A device according to claim 4, wherein said address generating means (360) incorporates the first address signal first and then the second address signal. A device according to any preceding claim, wherein said first transition is either the rise or the fall of said clock signal and said second transition is the other of said clock signal. A device according to claim 1, wherein said second address control means (2602') includes means (2702-2717) responsive to said mode select signal (A, B) and said clock signal (K) for supplying said second address load signal responsive to one of (i) a first second transition of said clock signal immediately after said first first transition, (ii) a next first transition of said clock signal immediately after said first first transition, and (iii) a second first transition of said clock signal after said first transition.

Inventors: ABE HIDEAKI, DOSAKA KATSUMI, HAYANO KOUJI, HIMUKASHI KATSUMITSU, ISHIZUKA YASUHIRO, IWAMOTO HISASHI, KONISHI YASUHIRO, KUMANOYA MASAKI, SAIKI TSUKASA, YAMAZAKI AKIRA, ABE, HIDEAKI, DOSAKA, KATSUMI, HAYANO, KOUJI, HIMUKASHI, KATSUMITSU, ISHIZUKA, YASUHIRO, IWAMOTO, HISASHI, KONISHI, YASUHIRO, KUMANOYA, MASAKI, SAIKI, TSUKASA, YAMAZAKI, AKIRA, Abe, Hideaki, c/o Mitsubishi Denki K. K., Dosaka, Katsumi, c/o Mitsubishi Denki K. K., Hayano, Kouji, c/o Mitsubishi Denki K. K., Himukashi, Katsumitsu, c/o Mitsub. Elec. Eng. Co.,, Ishizuka, Yasuhiro, c/o Mitsub. Elec. Eng. Co.,, Iwamoto, Hisashi, c/o Mitsubishi Denki K. K., Konishi, Yasuhiro, c/o Mitsubishi Denki K. K., Kumanoya, Masaki, c/o Mitsubishi Denki K. K., Saiki, Tsukasa, c/o Mitsub. Elec. Eng. Co.,, Yamazaki, Akira, c/o Mitsubishi Denki K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI ELECTRIC ENG, MITSUBISHI DENKI KABUSHIKI KAISHA, MITSUBISHI ELECTRIC ENGINEERING CO., LTD.
Application year: 1992
Main classification: G11C11
IPC codes: G11C8, G11C7, G11C11, G06F12