Apparatus for preventing computer data destructively read out from storage unit

Abstract: A data transfer control system for a computer can prevent destructive read out of data from an external storage unit during a data transfer operation. To control transfer of a series of data between a first storage unit (5) having a first storage capacity and a second storage unit (1) of a computer, having a second storage capacity typically smaller than the first storage capacity, the apparatus employs a first buffer memory (29) for temporarily storing the series of data read out from the first storage unit, a second buffer memory (29) for temporarily storing the series of data transferred from the first buffer memory means, and a buffer checking/controlling unit for checking whether or not a storage condition of the second buffer memory means corresponds to an empty state. An empty flag is set when the second buffer memory (29) becomes empty. The buffer checking/control unit also controls transfer of the series of data from the first buffer memory (21) to the second buffer memory (29) and from the second buffer memory (21) to the second storage means of the computer in such a way that if, after the series of data is read out from the first storage unit (1) to the second storage unit (1), the empty flag is not set, an abnormal data transfer signal is issued to prevent destructive data read out from the first storage unit (5). Another embodiment comprises the last words of first and second buffer memories (21, 19) and, if they fail to coincide, issues an abnormal data transfer signal. The embodiments can be used separately or together.

Description: Background of the Invention Field of the Invention The present invention generally relates to an apparatus capable of preventing destructive read out of computer data from a storage unit. More specifically, the present invention is directed to an apparatus capable of detecting an error when data are mistakenly transferred from a storage unit, having a large memory capacity, e.g., a mass storage unit such as a magnetic or optical disk unit to a main memory unit typically having a smaller memory capacity, e.g., RAM, employed in a computer system. It should be noted that, as used herein the expression "magnetic disk unit" refers to any mass storage unit including, but not limited to, magnetic disk media, magnetic tape units and optical storage media. US-A-5 068 785 (published on 26 November 1991 and family member of JP-A-2 077 863, published on 16 March 1990) describes a bus control system for a small computer system interface (SCSI) bus where a first-in-first-out (FIFO) type memory is used for transmitting information to and receiving information from the SCSI bus. In the bus control system, the memory is designed to output an empty signal when the memory is empty. The empty signal is supplied to a handshake control circuit which controls a handshake between an information transfer request signal which it receives and an information receipt acknowledge signal which it transmits. The handshake control circuit holds the information receipt acknowledge signal in an active condition after the information receipt acknowledge signal corresponding to the last information transfer has been activated and until the empty signal has been received, so that the FIFO memory cannot be used for a further phase of transmitting information until it is empty. EP-A-0 248 478 describes a sequential buffer device suitable for connection to a CD-ROM player and which contains a random access memory (RAM) to store data sequentially received at an input of the buffer device. In one embodiment, the buffer device also contains a cyclically operative error detection device which performs error detection on the data received at the input on the basis of error detection data contained in the received data and an error correction device to localize and correct errors under the control of the error detection device and on the basis of error correction data also contained in the received data. The buffer device further comprises a first-in-first-out (FIFO) memory, which is preferably a shift register. Data received by the RAM is read into the FIFO memory, thus decoupling the data output speed of the RAM (which depends on the input rate of the received data) from the data take-up speed of a device, such as a computer, connected to the FIFO memory. US-A-3 649 963 describes a data transmission system comprising a plurality of registers, data being transmitted from a first one of said plurality of registers to a second one of said plurality of registers. The accuracy of the data transmission is checked by supplying the data transmitted from the first register to a check register containing a predetermined initial pattern of bits, supplying the data received by the second register to the check register in a logically complemented form, and then determining whether the contents of the check register after the supplying operations conform to the initial predetermined pattern of bits contained in the check register before the supplying operations. Description of Prior Art In general, a data transfer operation between a main memory unit, such as a RAM, and a magnetic or optical disk unit having a larger memory capacity than that of the main memory unit in a computer data transfer system is performed in such a manner that a data stream read out from the magnetic or optical disk unit is transferred to the main memory unit via a mass storage or magnetic disk control unit, a channel unit and a transfer path of the main memory unit. To guarantee accurate transfer of the data, a parity bit is added to a data stream for each arbitrary bit length of the data stream, for instance for each data block. As a result, destructive readout, e.g., read out of changed bit data, from the magnetic or optical disk unit can be avoided. As is known in the art, since such a parity bit is added to the data stream, when a fault such as a "bit change" happens to occur in the data on the data transfer path, i.e., the magnetic disk control unit, this fault may be detected as a so-called "parity check error". This parity check error is reported to a CPU (central processing unit) provided with a host computer unit. In response to this fault report, this CPU determines that the data stream read out from the magnetic disk unit corresponds to an abnormal data stream, instructs that the abnormal data stream be discarded, and then accesses another data stream stored in a storage region of the magnetic disk unit, which is again transferred therefrom to the main memory unit. As described above, even when a fault such as a "bit change" occurs in the data to be transferred, destructive readout of the data can be prevented in the conventional computer data transfer system. However, if, for instance, a data block having a shortage of one data word is transferred from the magnetic disk unit to the main memory unit, it is particularly difficult for conventional computer data transfer systems to detect abnormal or faulty data transfer operations. Although the parity bit is added to the data stream for each arbitrary bit length in order to detect a faulty data transfer operation, the above-described parity check function is insufficient to detect an error in the conventional computer data transfer system, when, for example, one data block from which one data word had been dropped out would be mistakenly transferred from the magnetic disk unit via the above-described data transfer path to the main memory unit. This is because both the data and the parity bit are received at the same time by the parity bit checking unit of the conventional computer data transfer system. Similarly, when, for instance, one data block with one extra data word is mistakenly transferred from the magnetic disk unit via the data transfer path to the main memory unit, another problem occurs in the conventional computer data transfer system because the parity check function does not operate to correctly carry out fault detection. The present invention solves the above-described problems of the conventional computer data transfer system, and has as an object to provide a computer destructive data readout prevention apparatus capable of detecting abnormal conditions of data streams to be transferred, e.g., a data stream with an extra data word, thereby preventing destructive data readout and also improving reliability of the entire data transfer system. Another object of the present invention is to provide a computer destructive data prevention apparatus capable of judging that fault data read out from a first memory unit having a large memory capacity is mistakenly transferred to a second memory unit having a small memory capacity employed in a computer, thereby avoiding execution of such a destructive data readout prior to the data process operation in the computer. Summary of the Invention To achieve the above-described objects, in one aspect, the present invention provides an apparatus for controlling transfer of a series of data between a first storage unit and a second storage unit, comprising: a first buffer memory for temporarily storing said series of data read out from said first storage unit; a second buffer memory for receiving and temporarily storing therein said series of data from said first buffer memory; controlling means for controlling said transfer of said series of data from said first storage unit to said second storage unit via said first buffer memory and said second buffer memory; and judging means for determining if a match exists between a preselected data word contained in said series of data temporarily stored in said first buffer memory and a preselected data word contained in said series of data temporarily stored in said second buffer memory, and, if said match exists, determining a correct said series of data is available for said transfer from said second buffer to said second storage unit. In a second aspect, the present invention provides a method of controlling transfer of a series of data between a first storage unit and a second storage unit, the method comprising the steps of: receiving and temporarily storing in a first buffer memory said series of data read out from said first storage unit; receiving and temporarily storing in a second buffer memory said series of data from said first buffer memory; controlling said transfer of said series of data from said first storage unit to said second storage unit via said first buffer memory and said second buffer memory; determining if a match exists between a preselected data word contained in said series of data temporarily stored in said first buffer memory and a preselected data word contained in said series of data temporarily stored in said second buffer memory, and, if said match exists, determining that a correct said series of data is available for said transfer from said second buffer to said second storage unit. Brief Description of the Drawings For a better understanding of these and other objects of the invention, reference is made to the following detailed description of the invention. to be read in conjunction with the following drawings, in which: Figs. 1A and 1B are schematic block diagrams representing an overall arrangement of a computer destructive data readout prevention apparatus according to a first preferred embodiment of the invention; Fig. 2 shows major functions of the microprocessor 25 employed in the first computer destructive data readout prevention apparatus of Fig. 1; Fig. 3 is a flow chart illustrating overall operation of the first preferred embodiment of the destructive data readout prevention apparatus; Figs. 4A and 4B are schematic block diagrams illustrating an overall arrangement of a computer destructive data readout prevention apparatus according to a second preferred embodiment of the invention; Figs. 5A to 5C are flow charts illustrating the data transfer control operations performed by the second embodiment of the destructive data readout prevention apparatus shown in Figs. 4A and 4B; and Fig. 6 is a flow chart illustrating the data transfer control operations executed by a computer destructive data readout prevention apparatus according to a third preferred embodiment of the invention. Detailed Description of the Preferred Embodiments Before detailing various preferred embodiments, underlying principles of the invention are described. Generally, a destructive data readout prevention apparatus according to the invention may be constructed based upon the following basic principles. First, a computer destructive data readout prevention apparatus is arranged to have: a first buffer for temporarily storing a data stream to be transferred from an external storage unit, typically a mass storage device (e.g., magnetic disk unit, magnetic tape unit, optical storage media) to a main memory unit (e.g., RAM) of a computer and vice versa; a second buffer for temporarily storing the data stream to be transferred from the first buffer to either the external storage unit, or the main memory unit; and a judging unit for determining whether or not the last single data word of the data stream stored in the first buffer is coincident with the last single data word of the data stream stored in the second buffer. When the last single data word of the data stream in the first buffer is coincident with the last single data word of the data stream stored in the second buffer, a normal data transfer operation is performed. When this is not the case (the last data word in the first and second buffers are not coincident) an abnormal (fault) data transfer operation is carried out. With the above-described arrangement, by comparing the last data words of the data streams stored in the first and second buffers, respectively, if a coincidence or match exists, it can be judged that the data stream has been transferred between the external storage unit and the main memory unit under the normal condition. Conversely, if the last data word of the data stream stored in the first buffer does not match or is not coincident with that of the data stream stored in the second buffer, it can be quickly determined that an abnormal, or faulty data transfer operation has been performed between them. A second principle is that a computer destructive data readout prevention apparatus be constructed of at least first and second buffers employed in a magnetic disk control unit for controlling a magnetic disk unit, or other mass storage control unit (e.g., optical storage media), as previously described. This is an external storage unit having a large memory capacity. A data stream is transferred between the magnetic disk unit and a main memory unit having a smaller memory capacity. The first buffer is connected to the magnetic disk apparatus, so as to temporarily store a data stream read out from the magnetic disk apparatus. The second buffer is connected to receive this data stream derived from the first buffer. The computer destructive data readout prevention apparatus further includes a buffer control unit for checking whether or not the storage region of the second buffer is empty and for setting an empty flag when the storage region of the second buffer becomes empty. This buffer control unit also produces a data destruction detection signal if and when the second buffer is not empty after all of the data stream read out from the magnetic disk or other mass storage apparatus has been transferred to the main memory unit in the computer. In this computer destructive data readout prevention apparatus, after all of the data stream read out from the first buffer has been transferred via the second buffer to the main memory unit of the computer, the buffer control unit determines whether or not the storage condition of the second buffer becomes empty in response to the empty flag. When a portion of the above-described data stream is still left in the second buffer, and thus the storage condition thereof is not empty, the buffer control unit judges that a faulty data transfer operation has occurred and, in response, produces the data destruction detecting signal. It should be noted that although the coincidence check was done using the last single data word of the respective buffered data streams in the above-described first underlying principle, the present invention is not limited thereto. For instance, such a coincidence check may be performed for an arbitrary data word, and/or for a predetermined number of data words "N" ("N" being greater than 1) counted from the last single data word. A First Preferred Embodiment Figs. 1A and 1B show an overall arrangement of a destructive data readout prevention apparatus according to a first preferred embodiment of the invention. Fig. 2 illustrates the major data transfer control operations performed in the first destructive data readout prevention apparatus of Figs. 1A and 1B. It should be noted that the first destructive data readout prevention apparatus is realized employing the first underlying principle discussed above. In Fig. 1A, a main memory unit 1, such as a RAM (random access memory), employed in a computer 100 stores desired data at predetermined addresses thereof. The computer 100 further includes a system control unit 3 for controlling data access operations to this main memory unit 1. A mass storage unit, such as magnetic disk unit 5 (see Fig. 1B) in the first destructive data readout prevention apparatus, provided to transfer data to main memory unit 1, has a large quantity of data stored in its magnetic disk (not shown in detail). It should be noted that magnetic disk unit 5 can be replaced by any mass storage media, including, but not limited to, magnetic tape and optical storage media. The main memory unit 1 of the computer 100 is coupled with the magnetic disk unit 5 via a data transmission path 17, as represented in Figs. 1A and 1B. Along this data transmission path 17, there are provided, as viewed at a side of the magnetic disk unit 5, a disk I/F (interface) control board 9, a microprocessor control board 11, a channel I/F control board 13, a channel unit 15, and also a system bus 7 interfaced with a CPU (central processing unit) 200 of the computer 100. As represented in Fig. 1B, the above-described disk I/F control board 9 is connected via the data transmission path to the magnetic disk unit 5, so as to receive data read out from the magnetic disk unit 5. The disk I/F control board 9 is constructed of a disk control circuit 19, a DMA (direct memory access) data buffer 21, a buffer control circuit 22 and a parity check circuit 23. The disk control circuit 19 functions to control data read/write operations with respect to the magnetic disk of the magnetic disk apparatus 5. The DMA data buffer (i.e., a first buffer) 21 temporarily stores either the data read out from the magnetic disk under control of the buffer control circuit 22, or the data to be written into the magnetic disk under control of this buffer control circuit 22, into a predetermined memory address thereof. The parity check circuit 23 executes the normal parity check for the data transferred via the data transmission path 17 between the disk control circuit 19 and the first buffer 21. It should be noted that various commands and status signals used to control the magnetic disk unit 5 and the like are supplied from a microprocessor 25 (as discussed below) within this disk I/F control board 9. The microprocessor control board 11 controls the overall magnetic disk control unit 19, and contains the above-mentioned microprocessor 25 and a DMA control unit 27. The microprocessor 25 controls the data transfer between the magnetic disk unit 5 and the main memory unit 1 by way of a firmware function thereof. The DMA control unit 27 executes DMA (direct memory access) control in response to a DMA permission signal sent from the microprocessor 25. Returning back to Fig. 1A, the channel I/F control board 13 is coupled to a host device, e.g., CPU 200 through channel unit 15 via the system bus 7. This channel I/F control board 13 includes a DMA data buffer (second buffer) 29, a buffer control unit 31, parity check circuits 33A and 33B, and also a bus selector 35. The DMA data buffer (namely, the second buffer) 29 corresponds to such a buffer for transferring data between the main memory unit 1 and the DMA data buffer (first buffer) 21, and for storing at a predetermined memory address the data to be transferred under control of the buffer control unit 31. The former parity check circuit 33A performs the normal parity check operation for the data on the transmission path 17 between the DMA data buffer (first buffer) 21 and the DMA data buffer (second buffer) 29, whereas the latter parity check circuit 33B executes the normal parity check operation for the data on the data transmission path 17 between the second buffer 29 and the bus selector 35. The bus selector 35 performs bus select control in response to a command issued from the microprocessor 25. The channel unit 15 performs data input/output control with respect to the main memory unit 1 of the computer 100. This channel unit 15 includes a channel microprocessor 39, a DMA data buffer (third buffer) 41, a buffer control unit 43, parity check circuits 45A, 45B, and a system bus control unit 49. The third buffer 41 stores, at a predetermined address thereof, the data read from/written into the main memory unit 1 under control of the buffer control unit 43. Similarly, the former parity check circuit 45A performs the normal parity check for the data on the transmission path 17 between the third buffer 41 and the bus selector 35, while the latter parity check circuit 45B executes the normal parity check for the data on the transmission path 17 between the main memory unit 1 and the third buffer 41. The system bus control unit 49 controls the system bus 7 to which CPU 200 is connected. Fig. 2 illustrates an internal arrangement of the microprocessor 25 employed in the microprocessor control board 11. Microprocessor 25 and associated registers form a buffer checking/controlling means, as described below. The buffer/checking controlling means described herein can be implemented by other circuitry, as would be known to those of ordinary skill in this art. A data storage unit 53 inside the microprocessor 25 is constructed of a RAM (random access memory). This RAM 53 has first and second memory regions 55 and 57. In the first memory region 55, a data stream (for instance, 5 data blocks) has been stored. This data stream was read out from the magnetic disk unit 5 and then temporarily stored in the first buffer 21, and was then temporarily stored in the second buffer 29. Thereafter, this data stream was read out from the second buffer 29 and then transferred to the first memory region 55 via the data transmission path 17. In other words, the data stream which was read from the second buffer 29 has been stored in the first memory region 55. Another data stream, which was read from the first buffer 21, has been stored in the second memory region 57. The microprocessor 25 further includes a first general-purpose register 59 and a second general-purpose register 61. Both of the first and second general-purpose registers 59 and 61 are arranged as, for instance, 32-bit registers, respectively, having the same data width (i.e., 32 bits) as that of the transmission path 17. The last data word of the data stream stoked in the first memory region 55 of RAM 53 is read and then is stored in the first general-purpose register 59. The last data word of the data stored in the second memory region 57 is read and stored in the second general-purpose register 61. Under control of the firmware of the microprocessor 25, the last data word stored in the first general-purpose register 59 (i.e., data from the second buffer 29) is compared with the last data word stored in the second general-purpose register 61 (i.e., data from the first buffer 21), so as to check whether or not the data word in the first general purpose register 59 (the former data word) matches or is coincident with the data word in the second general purpose register 61 (the latter data word). If the former data word matches or is coincident with the latter data word, then the microprocessor 25 judges that all of the data stream has been completely transferred from the magnetic disk unit 5 to the main memory 1 under normal conditions. Conversely, if the former data word is not coincident with or does not match the latter data word, then the microprocessor 25 judges that the data stream has been transferred under an abnormal condition. Referring now to the flow chart shown in Fig. 3, overall operation of the first destructive data readout prevention apparatus will be described. Upon initiation of this destructive data readout prevention apparatus represented in Figs. 1A and 1B, a command is issued from the microprocessor 25 and supplied to the disk control circuit 19 in order that an indication of the size of the data stream to be transferred, e.g., 5 data blocks, be set to a counter (not shown in detail) of microprocessor 25 at step ST-100. The data transfer operation is initiated at step ST-110. Upon receipt of an initiate command, a series of desired data (e.g., 5 data blocks) is accessed by the disk control circuit 19, so that the desired data stream is derived from the magnetic disk (not shown in detail). Under control of disk control circuit 19, the desired data stream is transferred via the data transmission path 17 to the first buffer 21 and thereafter to the second buffer 29 at step ST-120. Every time a data stream is read out from the magnetic disk unit 5 and is transferred to the first and second buffers 21 and 29 under control of the disk control circuit 19, the counter is counted down. When the count value of this counter becomes zero, an interrupt command is issued from this counter under control of the microprocessor 25 at step ST-130. Upon issuance of the interrupt command, the normal parity check is carried out by the parity check circuits 23, 33A and 33B at step ST-140. The last data word of the data stream from the second buffer 29, which has been stored in the first memory region 55 of RAM 53, is read and thereafter stored into the first general-purpose register 59. The last data word of the first buffer 21, which has been stored in the second memory region 57, is read and then stored in the second general-purpose register 61. A comparison is made between these last data words in the comparing circuit 65 (see Fig. 2) at a step ST-150. At a subsequent step ST-160, a check is made to determine whether or not the former data word in general purpose register 59 is coincident with the latter data word in general purpose register 61. If "YES", then the transfer control process is advanced to step ST-170 at which a status signal indicating that a normal data transfer operation has been completed is produced from the comparison circuit 65, and accordingly, is returned to the host unit (CPU 200). If the result of the coincidence test in step ST-160 is NO, then another status signal representing the performance of an abnormal data transfer operation is produced from the comparison circuit 65 at step ST-180. Thereafter, this abnormal data transfer status signal is similarly returned to the host unit at step ST-190. As a consequence, while the data streams read out from the magnetic disk unit 5 are transferred via the data transmission path 17 to the main memory unit 1, a faulty data transfer operation, e.g., a data stream having a shortage of one data word, may be quickly detected. Thereby a destructive data readout operation may be prevented prior to further data processing operations in the computer 100. Furthermore, reliability of the entire system may be improved, as compared with a conventional data transfer control system. It should be noted that although the data read from the magnetic disk unit are transferred to the main memory unit of the computer in the above-described first preferred embodiment, other data read from the main memory may be transferred to the magnetic disk unit using this approach. Alternatively, a magnetic tape unit may be utilized instead of the above-explained magnetic disk unit. It should also be noted that although the coincidence check was done in the last data word of the respective buffered data streams in the above-described first embodiment, the present invention is not limited thereto. For instance, such a coincidence check may be performed for an arbitrary data word, and/or for a plurality of predetermined data words "N" ("N" being greater than 1) counted from the last data word. Figs. 4A and 4B illustrate an overall arrangement of a computer destructive data readout prevention apparatus. This employs the second underlying principle discussed above. It should be noted that the same reference numerals shown in Figs. 1A and 1B will be employed as those for denoting the same or similar circuit elements in the drawings of the second embodiment. The computer 100 includes the main memory unit 1, the system control unit 3, the system bus 7 and the channel unit 15. The channel unit 15 includes the channel microprocessor 39, the system bus control circuit 49, the DMA data buffer (i.e., third buffer) 41, the buffer control circuit 43, a command/status judging circuit 146, and two parity check circuits 45A and 45B. A magnetic disk control unit 400 is arranged with the channel I/F (interface) control 13 coupled to the computer 100, the microprocessor control board 11 for controlling the entire magnetic disk control unit 400 and also the disk I/F control board 9 coupled to the magnetic disk unit 5, for receiving the data read out from magnetic disk unit 5. In channel I/F control board 13, there are employed the data transfer buffer memory circuit (i.e., second buffer) 29, and a buffer check/control circuit 300. This buffer check/control circuit 300 is a feature of the second embodiment of the destructive data readout prevention apparatus. The buffer check/control circuit 300 controls the data transfer operation with respect to the data transfer buffer circuit 29, and furthermore checks the storage conditions of this second buffer circuit 29, whereby a full flag and an empty flag are produced. In addition, a command/status judging circuit 314, the parity check circuits 33A, 33B, and the bus selector 35 are employed in this channel I/F control board 13. In the microprocessor control board 11, there are provided both a microprocessor 321 for executing a control operation by a firmware, and the DMA control circuit 27. In the disk I/F control board 9, there are provided the disk control circuit 19, the read data DMA data buffer memory circuit (i.e., first buffer circuit) 21, a command/status judging circuit 333, and the parity check circuit 23. A description is now made of the overall data transfer control operations of a destructive data readout prevention apparatus. It should be noted that data are transferred through a data path 17 indicated by a solid line, whereas access commands/status signals from the microprocessor 321 are transferred through a path 18 indicated by a dotted line. Data read out from the magnetic disk unit 5 is transferred as a data stream via the data transmission path 17 as shown in Figs. 4A and 4B to the main memory unit 1 of the computer 100. As apparent from Figs. 4A and 4B, three buffer circuits (first to third buffers) 21, 29 and 41 are employed on this data transmission path 17. A readout data transfer sequence occurs as follows. The readout data flows from the magnetic disk unit 5 through the first buffer 21, the second buffer 29 and the third buffer 41 to the main memory unit 1. The data transfer control/storage check operations by the buffer check/control circuit 300 are performed in such a manner that when the second buffer circuit 29 is fully filled or stored with the data streams, a "full" flag is set, whereas when the second buffer circuit 29 becomes empty, an "empty" flag is set. These "full" and "empty" flags are readable by way of the firmware of the microprocessor 321 employed in the microprocessor control board 11. The data transfer operation may be executed by utilizing the data transfer buffer (second buffer) circuit 29. That is, when the second buffer circuit 29 commences receipt of data from the disk I/F control board 9, the data are gradually stored therein (namely in the second buffer 29), and also some of data start to be transferred to the channel unit 15. When the data transfer operation is interrupted e.g., for reasons discussed later occurring in the computer 100, the data read out from the magnetic disk unit 5 remain stored in the second buffer 29, and then the "full" flag is set by the buffer check/control circuit 300. However, at some point in time the data transfer operation is restarted at the channel unit 15 of the computer 100 unless a fault happens to occur by which the data transfer operation is interrupted. Finally, no data is left in the second buffer 29, so that the data transfer operation with respect to the desired data stream is completed. Therefore, the empty flag is set by the buffer check/control circuit 300. In other words, if a normal data transfer operation is accomplished, the storage condition of this second buffer 29 must become "empty", so that the empty flag should be set by the buffer check/control circuit 300. Assume now that a certain hardware problem happens to occur, and accordingly, for instance, five data blocks with 1 extra data word are read from the magnetic disk unit 5, the parity bits are added to the data blocks for a predetermined data length thereof, and the parity check operations are executed by the respective parity check circuits 23, 33A, 33B, 45A and 45B along the data transmission path 17. Since both the data blocks and the parity bits are simultaneously received, the parity checking function does not work at all when such an extra one data word is transferred, so that such an abnormal data transfer operation cannot be detected in these parity check circuits, as previously explained in connection with the conventional data transfer operation. Since the storage conditions of the second buffer circuit 29 are monitored by the buffer check/control unit 300 when the data transfer operation of a predetermined data stream (e.g., 5 data blocks) is completed, the above-described abnormal data transfer operation can be detected as follows. In the case of such an abnormal data transfer operation that one extra data word in addition to five data blocks are transferred from the magnetic disk unit 5 via buffer circuits 21, 29, 41 to the main memory unit 1, the one extra data word remains in the second buffer circuit 29. As a result, the storage condition of the second buffer 29 is not brought into the "empty" condition when the transfer operation of only a predetermined data stream, i.e., five data blocks, is completed. Thus, the "empty" flag cannot be set by the buffer check/control circuit 300. When the above-described data transfer operation is accomplished, a check is made to determine whether or not the "empty" flag is set under control of the firmware of the microprocessor 321. If such an empty flag has not yet been set by the buffer check/control circuit 300, the present data transfer operation should be interrupted by the microprocessor 321. Thereby, the above-described abnormal (faulty) data transfer operation for the main memory unit 1 of the computer 100 can be avoided and thus, the destructive data readout operation from the magnetic disk unit 5 can be prevented. Referring now to the flow chart shown in Fig. 5, a more detailed data transfer operation effected in the destructive data readout prevention apparatus represented in Figs. 4A and 4B will be described. At a first step ST-200 of the flow chart shown in Fig. 5A, the channel unit 15 is initiated by the CPU 200. Channel unit 15 fetches a channel instruction word of the main memory unit 1 at step ST-202. The channel instruction word is decoded by the channel unit 15 at step ST-204. Subsequently, the DMA buffer circuit (third buffer) 41 is set up to wait for a DMA command issued from the system control circuit 3 at step ST-206. Upon receipt, this DMA command is converted into an instruction word for designating a predetermined controller at step ST-208. Thereafter, this instruction word is reported from the channel unit 15 to the designated controller at step ST-210. At step ST-212, the controller seeks a desired disk address in response to the received instruction word. Accordingly, various setup operations for the DMA buffer circuit (third buffer) 41 are executed by the controller. For instance, a size of data transfer operation is set and the full/empty flags for the second buffer circuit 29 are initialized. Next, the magnetic disk unit 5 is initiated at step ST-216. Further, data read from the magnetic disk unit 5 is inputted into the first buffer 21 at a step ST-218. Referring now to the flow chart shown in Fig. 5B, further steps in the data transfer control operation are explained. At step ST-220, when the data having a predetermined data size have been stored in the first buffer circuit 21, transfer of these stored data to the second buffer circuit 29 is commenced. Since several data are entered into the second buffer 29, the empty flag is reset under control of the buffer check/control circuit 300 at step ST-222. Under such a circumstance, there are typically two states: In the first state, the data stored in the second buffer 29 starts to be transferred to the third buffer circuit 41 (see step ST-224). In a second state, the data transfer operation from the second buffer circuit 29 to the third buffer circuit 41 is temporarily interrupted for some reason, e.g., overloads of the system bus 7, but is then restarted (see the subroutine indicated by the dotted line, i.e., steps from ST-300 to ST-310, which will be described later). Referring back to the previous step ST-224, the data transfer operation from the second buffer circuit 29 to the third buffer circuit 41 is carried out. On the other hand, the data transfer operation from the magnetic disk unit 5 to the first buffer circuit 21 is completed at step ST-226. Subsequently, the data transfer operations are successively completed from the first buffer circuit 21 to the second buffer circuit 29 at step ST-228, and from the second buffer circuit 29 to the third buffer circuit 41 at step ST-230. At the next step ST-232 (shown in Fig. 5C), the microprocessor 321 employed in the microprocessor control board 11 checks the data transfer accomplishment conditions, e.g., if the transfer size is 0, and the empty flag for the second buffer circuit 29 is set. Thereafter, a status signal is produced and sent to the channel unit 15 under control of the microprocessor 321 at step ST-234. The channel microprocessor 39 checks the status signal issued from the controller at step ST-236. Next, the contents of the status signal is transferred from the channel unit 15 to CPU 200 at step ST-238, and then the contents of the status signal are reported from the channel unit 15 to CPU 200, whereby the series of second data transfer control operations is ended. Returning back to step ST-222, it is considered at subsequent step ST-300 that the data transfer operation from the second buffer circuit 29 to the third buffer circuit 41 is temporarily interrupted, e.g., for one of the above-mentioned reasons. Then, since the data transfer operation from the second buffer circuit 29 to the third buffer circuit 41 is temporarily interrupted, while the data transfer operation from the first buffer circuit 21 to the second buffer circuit 29 is continued, the data transferred from the first buffer circuit 21 continue to be gradually stored in the second buffer circuit 29 at step ST-302. Accordingly, the "full" flag is set by the buffer check/control circuit 300 at step ST-304. Then, when the reasons for the interruption in the data transfer operation are solved, the transfer operation from the second buffer circuit 29 to the third buffer circuit 41 is restarted at step ST-306. The "full" flag is reset at step ST-308, and therefore the overall data transfer operation is restarted at step ST-310. Subsequently, the data transfer process is advanced to step ST-226. In a second embodiment of a computer destructive data readout prevention apparatus (not shown in detail), a data transfer control operation is carried out based upon a combination of the above-described first and second underlying principles, i.e., both the data coincidence checking operation and the buffer storage condition checking operation. This data transfer control operation will now be described with reference to the flow chart shown in Fig. 6. The steps shown in Figure 6 begin after completion of step ST-232 shown in Fig. 5C. Thus, after the data transfer accomplishment conditions have been checked under control of the microprocessor 321, the following data coincidence checking operation shown in Figure 6 is performed. At step ST-400, the error holding circuit is investigated. A check is done to determine whether or not a parity error occurred at step ST-402. If NO, then the data transfer control process is advanced to step ST-404 at which the size of the transferred data is checked. At the next step ST-406, a further check is done to determine whether or not the accomplishment condition of the transfer size becomes 0. If NO, then the data transfer control process is advanced to step ST-408 at which the flag for the second buffer circuit 29 is checked. Subsequently, another check is made to determine whether or not the empty flag has been set at step ST-410. If YES, then the process is advanced to step ST-412 at which, for instance, five data words forming the equivalent of the last data word of a predetermined data stream are read out from the first and second buffer circuits 21 and 29, respectively. Thereafter, a further check is done to determine whether or not these five data words of the first and second buffer circuits 21 and 29 are coincident with each other at step ST-414. If YES, then it can be judged by microprocessor 321 that a normal data transfer operation is completed, and therefore, the normal end status signal is produced at step ST-416. Thus, the data transfer control process is advanced to the previous step ST-234 shown in Fig. 5C. On the other hand, if either a parity error occurs ("YES" at step ST-402), or the five data words from the first and second buffer circuits 21 and 29 are not coincident with each other ("NO" at step ST-414), then it can be judged by the microprocessor 321 that an abnormal data transfer operation is performed, and therefore the abnormal end status signal is produced at step ST-418. Upon generation of the abnormal end status signal, this status signal is sent to the channel unit 15 at step ST-234. As apparent from the foregoing descriptions, the second computer destructive data readout prevention apparatus has the advantage that, since both the data coincidence checking operation and the buffer storage condition checking operation are executed with respect to one data steam to be transferred, the data transfer conditions can be assuredly checked and an abnormal data transfer operation can be firmly prevented.

Claims: An apparatus for controlling transfer of a series of data between a first storage unit (5) and a second storage unit (1), comprising: a first buffer memory (21) for temporarily storing said series of data read out from said first storage unit (5); a second buffer memory (29) for receiving and temporarily storing therein said series of data from said first buffer memory (21); controlling means (22, 25, 31) for controlling said transfer of said series of data from said first storage unit (5) to said second storage unit (1) via said first buffer memory (21) and said second buffer memory (29); and judging means (25) for determining if a match exists between a preselected data word contained in said series of data temporarily stored in said first buffer memory (21) and a preselected data word contained in said series of data temporarily stored in said second buffer memory (29), and, if said match exists, determining a correct said series of data is available for said transfer from said second buffer (29) to said second storage unit (1). A data transfer control apparatus as recited in claim 1, wherein, if no said match exists, said apparatus produces an error indication. A data transfer control apparatus as recited in claim 2, comprising a memory for storing each said error indication. A data transfer control apparatus as recited in claim 1, wherein said judging means (25) includes: a first register (61) to receive and store said preselected data word contained in said series of data temporarily stored in said first buffer memory (21); a second register (59) to receive and store said preselected data word contained in said series of data temporarily stored in said second buffer memory (29); and a comparison circuit (65) to compare said preselected data word stored in said first register (61) with said preselected data word stored in said second register (59), thereby checking if said preselected data word stored in said first register (61) matches said preselected data word stored in said second register (59). A data transfer control apparatus as recited in claim 1, wherein said judging means includes: a first memory region (57) to temporarily store said series of data transferred from said first buffer memory (21); a second memory region (55) to temporarily store said series of data transferred from said second buffer memory (29); a first register (61) to store said preselected data word contained in said series of data stored in said first memory region (57); a second register (59) to store said preselected data word contained in said series of data stored in said second memory region (55); and a comparison circuit (65) to compare said preselected data word stored in said first register (61) with said preselected data word stored in said second register (59), thereby checking if said preselected data word stored in said first register (61) coincides with said preselected data word stored in said second register (59). A data transfer control apparatus as recited in claim 1, wherein said preselected data word from each of said first (21) and second (29) buffer memories is a single last data word contained therein. A data transfer control apparatus as recited in claim 1, wherein said judging means (25) checks matching of a plurality of preselected data words in said first (21) and second (29) buffer memories. A data transfer control apparatus as recited in claim 7, wherein said judging means (25) checks matching of a plurality of preselected data words including the single last words in said first (21) and second (29) buffer memories. A data transfer control apparatus as recited in claim 1, further comprising: first parity check means (23) for checking a parity bit contained in said series of data read out from said first storage unit (5); second parity check means (33A) for checking a parity bit contained in said data transferred to said second buffer memory (29); and third parity check means (33B) for checking a parity bit contained in said data transferred from said second buffer memory (29) to said second storage unit (1). An apparatus for controlling transfer of a series of data between a first storage unit and a second storage unit according to any one of claims 1, 4, 5, 6, 7 and 9, further comprising: buffer checking/controlling means (300), said buffer checking/controlling means determining if said second buffer memory (29) is empty after transfer of said series of data from said second buffer memory (29) to said second storage unit (1), and determining a correct transfer of data if said second buffer memory (29) is empty after said transfer. The apparatus recited in claim 10, wherein said buffer checking/controlling means (300) indicates an error if said second buffer memory (29) is not empty after said transfer. The apparatus recited in claim 10, wherein said judging means (25) indicates an error if no said match exists. A method of controlling transfer of a series of data between a first storage unit (5) and a second storage unit (1), the method comprising the steps of: receiving and temporarily storing in a first buffer memory (21) said series of data read out from said first storage unit (5); receiving and temporarily storing in a second buffer memory (29) said series of data from said first buffer memory (21); controlling said transfer of said series of data from said first storage unit (5) to said second storage unit (1) via said first buffer memory (21) and said second buffer memory (29); determining if a match exists between a preselected data word contained in said series of data temporarily stored in said first buffer memory (21) and a preselected data word contained in said series of data temporarily stored in said second buffer memory (29), and, if said match exists, determining that a correct said series of data is available for said transfer from said second buffer (29) to said second storage unit (1). The method recited in claim 13, wherein, if no said match exists, an error is indicated. A method of controlling transfer of a series of data between a first storage unit (5) and a second storage unit (1) according to claim 13, the method further comprising the step of: determining if said second buffer memory (29) is empty after said transfer of said series of data from said second buffer memory (29) and determining a correct transfer of data if said second buffer memory (29) is empty after said transfer. The method recited in claim 15, wherein an error is indicated if said second buffer memory (29) is not empty after said transfer. The method recited in claim 15, wherein an error is indicated if no said match exists. The method recited in claim 15 further comprising: counting a number of data words transferred from said first storage unit (5) to said first buffer memory (21) to arrive at a first data transfer word count; counting a number of data words transferred from said second buffer memory (29) to said second storage unit (21) to arrive at a second data transfer word count; and determining if said second buffer memory (29) is empty when said second data transfer word count equals said first data transfer word count.

Inventors: KANEKO HIROYUKI, KANEKO, HIROYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: G06F11
IPC codes: G06F3, G06F12, G11B20, G06F11