Non-linear signal processor

Abstract: An image is sampled at a given sampling frequency. For each original sample at least one additional sample delayed relative to the first sample is generated (12, 14, 16). The original samples are non-linearly processed (18) and the additional samples are non-linearly processed (20) independently of the processing (18) of the original samples. The output signals from the two processing stages are downsampled (22) back to the original sampling frequency and are filtered if required for correcting the overall amplitude and phase vs. frequency characteristic.

Description: The present invention relates to non-linear signal processing and, in particular, to the removal of undesired harmonics created by such processing. The present invention will be discussed with reference to video signal processing in TV receivers but is not limited to that field. It has wide applicability wherever signal samples are subjected to non-linear processing, as, again for example, in the medical instruments field. In TV receivers, efforts to improve video images, have, in the recent past, concentrated to a considerable extent on improving the perceived image by decreasing or eliminating line flicker and field flicker. When the television picture is an interlaced picture these problems have been attacked in two basic ways. First, to eliminate line flicker, additional lines are interpolated between consecutive lines in each field. This converts the TV images from an interlaced format to a progressive scan. To remove the field or frame flicker, fields are interpolated between the consecutive fields by utilizing data from one or the other original raster, or both, combined non-linearly by, for example, a median filter. Non-linear filters are also used for filtering in the horizontal direction, e.g. for increasing the perceived image resolution. An example of use of a median filter for field interpolation is shown in EP-A-0,192,292 (Fig. 7). Since use of the vertical median filters still causes distortion in the video picture, an analysis of the problem was undertaken with the following result. For a non-orthogonal picture pattern as illustrated in Fig. 1a, the original signal components in the vertical and horizontal direction are illustrated in Fig. 1b and Fig. 1c, respectively. Use of a median filter in the vertical direction will result in a signal pattern as illustrated in Fig. 1d. A similar artefact will be created in the horizontal direction, as illustrated in Fig. 1e. Uneven harmonics have been created, of which the third harmonic is by far the strongest. The above-mentioned harmonics constitute a first order effect which, however, is not as disturbing as a second order effect resulting from the beat frequency or alias components between the above-mentioned odd harmonics and the frequency at which the signal is sampled in the horizontal direction, for example to permit digital signal processing. As shown in Fig. 1f, if a signal having a third harmonic compenent is sampled at three times the fundamental frequency, a DC level shift will occur, thus changing the average luminance value of the signal. A realistic example of a situation in which this kind of beat frequency can occur is the following. A PAL video signal includes undesired remainders of the color subcarrier at 4.43 MHz which form a diagonal pattern. The third harmonic of this pattern will be at 13.3 MHz. If now this signal is sampled in the horizontal direction at 13.5 MHz, the resulting beat frequency will be 200 KHz. If the color carrier traces extend over the whole picture, a pattern having 10 periods per line results, which is very disturbing. The problem arises because the sampling frequency is chosen so that the frequency spectrum of the video signal extends to 1/2 of the sampling frequency. This results in the greatest economy with respect to required memory and also in the lowest operating speed. Thus signal components of 1/3 of the sampling frequency may well lie within the spectrum of the video signal. In general, a solution to this problem has been to increase the sampling frequency so that the spectrum of the video signal remains well below 1/3 of the sampling frequency. This is not an economical solution since, for example, the capacity of the field memories or frame memories has to be increased by 50% and circuits have to operate at the higher frequency. It is inter alia an object of the present invention to decrease or remove the distortions mentioned above, without incurring the cost inherent in use of an overall higher sampling frequency. According to one aspect of the invention, a television signal processing apparatus which receives television signal samples sampled at a given sampling frequency and which are to be processed by non-linear processing means, is characterized in that upsampling means are provided for upsampling the received television samples to create higher frequency signal samples prior to application to the non-linear processing means. Further, downsampling means are coupled to the non-linear processing means for downsampling the output signal thereof back to the given sampling frequency. More detailed aspects of the invention are set out in claims 1 and 5. It is noted that EP-A-0,396,229 discloses an apparatus for spatially interpolating between lines of a digital video signal, to produce interpolated lines. The apparatus comprises a supersampler that horizontally interpolates between samples of the video signal to produce a supersampled signal comprising the original samples and at least one interpolated sample located between each adjacent pair of original samples. Block matching circuits each determine, for each sample of the supersampled signal, the extent of matching between two blocks of N x M samples of the supersampled signal (where N is the number of lines and M is the number of samples), the two blocks being vertically offset from one another in opposite directions with respect to a line to be interpolated, and being horizontally offset from one another in opposite directions with respect to a predetermined sample position. Each block matching circuit operates as set forth for a respective different horizontal offset, including zero offset and offsets on opposite sites of zero, whereby a respective value of the extent of matching is produced for each horizontal offset. A selector is responsive to the respective values produced by the block matching circuits to select, for each sample of the line to be interpolated, from a plurality of gradient vectors each associated with a respective one of the different horizontal offsets, the gradient vector associated with the horizontal offset that produces the greatest extent of matching between the two blocks. A variable direction spatial interpolator spatially interpolates the video signal. The direction of interpolation of the spatial interpolator is controlled, for each sample it generates, in accordance with the gradient vector selected for said predetermined sample position corresponding to that generated sample. It appears from the description of this prior art document (page 6, lines 17-43) that the number of horizontal samples on each line is doubled by the supersampling operation in order to be able to detect more gradients and hence to obtain a better match. No mention is made of undesired harmonics, so that those skilled in the art searching for a method to remove undesired harmonics will have no reason to apply the teaching of this prior art document. It is also noted that EP-A-0,360,509 discloses a video switcher used to combine input video signals to provide an output signal representing a picture composed partly of the image represented by one video signal and partly of the image represented by the other video signal. The combination of the two input video signals may be accomplished by means of a wipe, in which the switcher provides an output signal that changes from one input signal to the other in response to a wipe signal, which defines a predetermined wipe pattern. More specifically, the wipe signal is applied to a clip and gain circuit to provide a key signal. It is, however, possible for all wipe signal sample values on two or more consecutive lines to be outside the linear region of the clip and gain circuit. If that occurs, the waveform of the key signal is the same on the multiple lines. Accordingly, the desired sloping boundary between the two images is rendered as a succession of vertical segments joined by horizontal or near horizontal segments. The resulting jaggies may be visually disturbing. To solve this problem, EP-A-0,360,509 proposes a method and apparatus for carrying out a non-linear operation on a digital signal, in which a digital input signal having a sampling frequency f is interpolated by a factor N, where N is a positive integer, whereby a first digital signal having a sampling frequency Nf is generated. A non-linear operation is carried out on the first digital signal having the sampling frequency Nf, and a second digital signal having the sampling frequency Nf is provided. The second digital signal is decimated by a factor N and thereby provides a digital output signal having the sampling frequency f. In brief, by adding more values, a less jagged sloping boundary is obtained. However, nothing points at a solution for an undesired harmonics problem. These and other aspects of the invention will now be described in greater detail by way of example for a preferred embodiment with reference to the accompanying drawings. In the drawings: Fig. 1 is a waveform diagram illustrating the problem to be solved; Fig. 2 is a block diagram illustrating a median filter with upsampling and downsampling according to the present invention; Fig. 3 is a schematic block diagram of upsampling (a) and downsampling (b) filters for use in the present invention; Fig. 4 is a block diagram illustrating the basis of a second embodiment of the invention; Fig. 5 is a schematic block diagram of a second embodiment of a filter with upsampling according to the present invention; and Fig. 6 is a frequency response correction filter. The cause of the problem to be solved by the present invention was discussed above with reference to Fig. 1. Direct implementation of the proposed solution, namely a local upsampling by, for example, a factor of 2 would require a second clock having twice the frequency of the standard clock. Also, the median filter would have to operate at twice the normal frequency, which may be a very difficult requirement to implement. Thus, according to the invention, a standard median filter is replaced by upsampling units 12, 14 and 16, one for each input 1, 2, 3, two median filters 18 and 20, and downsampling stage 22. Median filter 18 processes the odd samples, while median filter 20 processes the even samples. Median filters 18 and 20 thus each operate at the standard or conventional frequency. The outputs of the two median filters are combined in the downsampling stage 22 which furnishes an output at the conventional sampling frequency. Identical upsampling filters 12, 14 and 16 are shown in greater detail in Fig. 3a. Input terminal 30 is connected to a first delay 32 which is connected to a second delay 34 at a common point 36. The incoming samples, multiplied by a factor of 1/4 in a multiplier 38, are combined with the previous sample, namely the sample at terminal 36, multiplied by a factor of 3/4 in a multiplier 40, by addition in an adder 42 which furnishes odd output samples. The even samples are similarly obtained by addition of the sample at common point 36 multiplied by a factor of 3/4 to the twice delayed sample at the output of delay 34 multiplied by 1/4 in multiplier 44, the addition taking place in an adder 46 at whose output the even samples appear. Thus for every input at terminal 30 an odd and even output are created, i.e. the frequency is doubled. Referring again to Fig. 2, the odd outputs of stages 12, 14 and 16 are applied to respective inputs of the odd median filter 18, while the even outputs of upsampling stages 12, 14 and 16 are connected to respective inputs of even median filter 20. The combined output of the filters 18 and 20 is thus an output at twice the conventional frequency. The output signals of filters 18 and 20 are, as mentioned above, downsampled in downsampling stage 22. A preferred downsampling stage as illustrated in Fig. 3b is a stage 48 in which the odd and even values are averaged so that the signal at the output of stage 48 is a video signal at the conventional sampling frequency. The upsampling stages described above are simplified for clarity and may not, per se, result in a sufficient suppression of artefacts. A more effective approach is to design the upsampling filters which furnish the "odd" and "even" sample series in such a way that, at the frequency of most of concern (here 1/3 the sampling frequency) the third harmonics at the output of the filters have the same amplitude and a phase relationship of 180°. When the signals are then combined, artefacts of the dominant frequency of FS/3 will be suppressed. The required circuitry to accomplish the above is derived as follows. Referring to Fig. 4, the video signal sampled at a frequency fs is applied via a terminal IN to respective stages H 1 and H 2 . The latter are followed respectively, by non-linear filters 18 and 20, which may be median filters. The outputs of the non-linear filters 18 and 20 are summed by an adder 22a, and thereafter applied to an equalizer 22b. The following conditions must be met: 1) the gain in both paths, at the base frequency on which the non-linear filter generates the harmonic to be suppressed, must be equal, 2) the i th harmonic of (fs/i), that is generated in the non-linear filters, in the two signal paths must be applied to the adder in opposite phase. For equal amplitudes: H 1 fs/i = H 2 fs/i Condition 2 above can be met if the difference in delay between H, and H 2 is a half sample time at the frequency fs/i. This means that a signal at frequency fs/i is applied to the non-linear filters with a ½ T sample , delay between their respective inputs. The generated harmonics at the outputs of the non-linear filters will therefore also have a ½ T sample delay difference. As the generated harmonics i * (fs/i) = fs, which were to be suppressed have a ½ T sample delay with respect to each other, these two filter-outputs are in opposite phase for fs. For a preferred embodiment: H 1 (z) = 1 (i.e. H 1 has no associated delay); H 2 (z) = K(1 + z -1 ) (H 2 has a delay of Ts/2 at all frequencies). K is a parameter used to obtain: |H2 (fs/i)| = |H 1 (fs/i)| ≡ 1 for the harmonic i to be cancelled. It can be shown that K = 1 if the third harmonic is cancelled. The resultant circuitry is illustrated in Fig. 5. Here the odd samples are the original samples i.e. the inputs 1, 2 and 3 of upsampling stages 12, 14 and 16 in Fig. 2 are directly connected to the inputs of the odd median filter 18 of Fig. 5. The inputs of median filter 20 are derived from a filter with 1,1 coefficients, i.e. the direct and once delayed samples at each input are summed in respective adder stages 46a, 46b and 46c before being applied to the respective inputs of even median filter 20. The outputs of filters 18 and 20 are summed in an output summing stage 22a. Computer simulations show that the third harmonic, as expected, is completely suppressed. However, the overall gain of the arrangement illustrated in Fig. 4 is not equal to 1 and, furthermore, the frequency characteristic is not flat. For correction, the equalizing filter 22b illustrated in Fig. 6 may be connected to the output of summing stage 22a. As illustrated in Fig. 6, it consists of a divider 50 which divides the incoming signal by a factor of 2. The output of divider 50 is applied to a summing stage 52 whose second input is connected to the filter output 54 by means of a second divider 56 in which the output signal is divided by a factor of 2 and phase shifted by 180°. The output of summing circuit 52 is connected by a one-sample interval delay 58 with output 54. This correction filter has the inverse characteristic of (H 1 + H 2 ) and therefore equalizes both gain and phase changes resulting therefrom. The present invention has been illustrated by a particular example in the video signal processing field. It should be noted that the local upsampling followed by processing and subsequent downsampling is applicable to many circuits in which alias is otherwise created by the beat between sampling frequencies and undesired signal components resulting, e.g. from imperfect filtering. Other applications will therefore readily occur to one skilled in the art, as will different embodiments of the upsampling and downsampling stages and frequency correction filters if required. All of the above form part of the present invention and are encompassed in the following Claims.

Claims: Apparatus for non-linearly processing signal samples sampled at a given sampling frequency to create processed output samples, comprising: means (12-16; H1, H2) for preventing at least one undesired harmonic to be created by said non-linearly processing (18, 20) from occurring, said undesired harmonic preventing means (12-16; H1, H2) including upsampling means for upsampling the signal samples to create higher frequency signal samples, wherein the higher frequency is a multiple N of the given sampling frequency where N is a positive integer larger than one; non-linear processing means (18, 20) for processing the higher frequency signal samples, the non-linear processing means (18, 20) including N parallel nonlinear processing circuits; and downsampling means (22) coupled to the non-linear processing means (18, 20) for downsampling the processed output samples to the given sampling frequency. Apparatus as claimed in claim 1, wherein N = 2, and wherein the non-linear processing means comprise a first (18) and second (20) median filter respectively filtering odd and even samples furnished by the upsampling means (12-16; H1, H2), and wherein the output of the first median filter (18) cancels the output of the second median filter (20) at an interfering frequency. Apparatus as claimed in claim 1, wherein the upsampling means comprise first (H1) and second (H2; T, 46) parallel stages having equal gain at a base frequency on which the non-linear processing means (18, 20) generate the harmonic to be suppressed, the parallel stages (H1, H2) having inputs coupled to an input of the apparatus and providing a mutual delay of half a sampling period at said base frequency, and wherein inputs of first (18) and second (20) parallel non-linear circuits are coupled to outputs of said first (H1) and second (H2; T, 46) parallel stages, and outputs of said first (18) and second (20) parallel non-linear circuits are combined (22a) to suppress the undesired harmonic. Apparatus as claimed in claim 3, wherein the outputs of said first (18) and second (20) parallel non-linear circuits are applied to an equalizer (22b) for providing a flat frequency characteristic at an overall gain of one. Method for removing at least one undesired harmonic created by non-linear processing of sequential sets of received signal samples having a given sample frequency, characterized in that each of the signal samples in a set of signal samples is delayed by a predetermined delay time (T) thereby creating a delayed signal sample, each delayed signal sample is added (46) to the corresponding signal sample to create combined signal samples, the sequential sets of received signal samples are processed non-linearly (18) to create a processed output signal having said undesired harmonic, the sets of combined signal samples are non-linearly processed (20) independently of the processing (18) of the sets of received signal samples to produce a second processed output signal having said undesired harmonic of the same amplitude and opposite phase of said undesired harmonic in said first processed output signal, and further characterized in that said first processed output signal and said second processed output signal are summed (22a) to form a final output signal not having the undesired harmonic.

Inventors: DOORNHEIN LAURENS, KETTENIS JEROEN MARIA, DOORNHEIN, LAURENS, KETTENIS, JEROEN MARIA
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H04N5
IPC codes: H04N5