NRZ clock and data recovery system employing phase lock loop

Abstract: An improved NRZ clock and data recovery system lends itself to integration, includes a NRZ phase detector, an NRZ frequency detector and a lock detector, and provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations. NRZ data is applied to one side of an exclusive-OR gate (6) and a twice delayed (2, 4) version of the NRZ data is applied to the other side. The output of the XOR gate (6), a "blivet" signal, is applied to a NRZ phase detector (10) comprising two AND gates (12,14), one of which (12) has as its other input a recovered clock signal output of a VCO (20) and the other of which has as its other input an inverted (16) version of the recovered clock signal. The "up" and "down" outputs of the AND gates (10,12) indicate which direction a frequency control signal (26) should change the VCO (20) frequency. A data holding flip-flop (28) whose input is a once delayed (2) version of the NRZ data is clocked with the recovered clock signal. The NRZ frequency detector (50) monitors the state of the recovered clock signal on opposite edges (52,53) of the blivet to detect too-high (56), too low (55) and good (54) conditions. The results of the detection can be ignored if a lock signal indicates that the phase lock loop is locked. The lock detector (30) consists of a saturating up/down counter (42) that is incremented (38) by one when good blivets (32) occur and is decremented (40) by four when not-good blivets (36) occur.

Description: Background of the Invention This invention relates to digital data transmission, and more particularly to non-return to zero (NRZ) clock and data recovery. NRZ data does not contain a spectral component at the clock frequency. Therefore, some way must be found to ascertain the clock signal frequency and phase. FIG. 1 shows one prior art approach to this problem. In this approach a non-linearity, in the form of a delay line and an exclusive-OR gate, is introduced to produce a frequency component at the NRZ clock frequency. The delay element is typically one half of the expected bit interval or less. A bandpass filter then detects the introduced frequency component at the clock frequency and either produces a clock directly or produces a clock indirectly with the assistance of a phase lock loop. The difficulty with the approach shown in FIG. 1 and described above is that a bandpass filter does not lend itself to integration into an integrated circuit (IC), and the phase accuracy of the recovered clock depends on the tuning of the bandpass filter. Another prior art approach is shown in FIG. 2. This approach does not require a tuned circuit and is therefore more amenable to IC implementation. However, the accuracy of the placement of the clock edge in the center of the bit interval depends primarily on the length of the delay line. In all of the typical IC implementations of a delay line, the amount of delay that results is subject to process and temperature variations. Thus, the clock edge is not well centered within the bit interval and, in the presence of significant jitter, the bit error rate suffers accordingly. US-A-4590602, US-A-3992581 and EP-A-0009939 disclose input processing circuits for producing a pulse at each transition of an input signal, which pulses are input to a phase detector for comparison with a VCO output clock signal. The phase compared signal is filtered to provide a control signal to the VCO so that the VCO provides the recovered clock signal. In US-A-3992581 the recovered clock is applied to a data flip-flop to which also is applied the input signal to provide the data output. US-A-4590602 also shows a frequency detector that compares a reference frequency from a separate oscillator with a sub-divided version of the VCO frequency (recovered clock) to provide an input to a summation circuit to which is also input the output of the phase detector, the sum being input to a loop filter. The frequency detector is inhibited by a lock detector that has the recovered clock and pulsed signal at each transition of the input signal, as inputs. What is desired is an improved NRZ clock and data recovery system that lends itself to integration, that provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations. Summary of the Invention According to this invention there is provided an NRZ clock/data recovery system using a phase locked loop as claimed in claim 1 herein. NRZ data is applied to one side of an exclusive-OR gate and a twice delayed version of the NRZ data is applied to the other side. The output of the XOR gate, a "blivet" signal, is applied to a NRZ phase detector comprising two AND gates, one of which has as its other input a recovered clock signal output of a VCO and the other of which has as its other input an inverted version of the recovered clock signal. The outputs of the two AND gates are an "up" signal and a "down" signal that indicate which direction a frequency control signal should change the VCO frequency. A data holding flip-flop whose input is a once delayed version of the NRZ data is clocked with the recovered clock signal. Preferably, there is provided an NRZ frequency detector that includes two flip-flops for monitoring the state of the recovered clock signal on opposite edges of the blivet signal. Three gates monitor the output of the two flip-flops to detect too-high, too-low and "good" conditions. Additional flip-flops hold the results of this detection, and feedback from these flip-flops is used to inhibit detection of error states that are the opposite of an immediately preceding error state. The flip-flops holding the results of the detection can be forced to ignore their inputs and hold a "good" instead if a lock signal indicates that the phase lock loop is locked. Advantageously there is also provided a lock detector consisting of a saturating up/down counter that is incremented by one when blivets occur and the NRZ frequency detector is signaling a "good" condition and is decremented by a number larger than one when blivets occur and the NRZ frequency detector is signaling "not-good". A lock signal output is produced whenever the count in the counter is above a predetermined threshold, e.g. half full. The subject matter of the present invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. However, both the organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following detailed description and accompanying drawings. Brief Description of the Drawings FIG. 1 is a block diagram of a prior art circuit for NRZ clock recovery; FIG. 2 is a block diagram of another prior art circuit for NRZ clock and data recovery; FIG. 3 is a block diagram of a portion of the MRZ clock and data recovery circuit according to the present invention, with schematic details of the phase detection block; FIG. 4 is a block diagram of the NRZ clock and data recovery system used in the present invention; FIG. 5 is a schematic diagram of the MRZ frequency detector used in the present invention; FIG. 6 is a timing diagram illustrating the operation of the NRZ frequency detector used in the present invention; and FIG. 7 is a block diagram of the lock detector used in the present invention. Detailed Description FIG. 3 is a block diagram of a portion of the NRZ clock and data recovery circuit according to the present invention, with an inset schematic detail of the phase detection circuitry 10. This design lends itself to integration and provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations. The NRZ data input is applied to a unique "blivet" generator 8. A "blivet" is a pulse indicative of a transition, either low-going or high-going, in the NRZ data. Internal to the blivet generator 8, the NRZ data input is applied to one side of exclusive-OR (XOR) gate 6 and also to two matching delay elements 2 and 4 in series, after which the doubly delayed output of those delay elements is applied to the other side of the XOR gate 6. In addition to generating blivets, blivet generator 8 also provides an NRZ output that is delayed by one half of the blivet width. The blivet output of the blivet generator is a pulse whose duration is the sum of the delay imposed by the two matching delay elements 2 and 4. As will be further explained below, the sum of these delays should be less than one half of the bit interval of the expected data, but as long as possible within that constraint. The blivet output of the blivet generator 8, from XOR gate 6, is applied to NRZ phase detector 10, which also receives a clock output from a VCO 20. The NRZ phase detector 10 comprises AND gates 12 and 14 and inverter 16. The NRZ phase detector 10 generates two signals, an "up" signal that goes to the "+" input of loop filter 26, and a "down" signal that goes to the "-" input of the loop filter 26. The "up" and "down" signals are used by the loop filter 26 to produce the control voltage for VCO 20. The loop filter 26, which is suitably a charge pump, receives the "up" and "down" pulses from the NRZ phase detector 10 and integrates their difference into an analog VCO control signal with only low frequency components. As will be further explained below, the effectiveness of this invention relies on the centering of the low-going edge of the VCO 20 recovered clock output within this blivet. If the VCC output low-going edge is already centered within the blivet produced by the XOR gate 6, the duration of the output from AND gate 12 is the same as the duration of the output from AND gate 14, and the inputs to the loop filter 26 cancel, indicating that no frequency adjustment is necessary and the loop filter 26 continues to produce an unchanged VCO control signal. If the downward transition of the VCO 20 clock signal output is late within the blivet, the output of AND gate 12 has a longer duration than the output of AND gate 14, and the "up" input to the loop filter prevails over the "down" input and the VCO control voltage output of the loop filter 26 increases the VCO frequency to cause the next low-going edge to occur sooner within the blivet interval. Conversely, if the downward transition of the VCO 20 clock signal is early within the blivet, the output of AND gate 14 has a longer duration than the output of AND gate 12, and the "down" input to the loop filter 26 prevails over the "up" input and the VCO control voltage output of the lowpass filter 26 decreases the VCO frequency to cause the next low-going edge to arrive later in the blivet interval. It will be therefore be seen that regardless of the position of the clock signal relative to the center of the blivet, the NRZ phase detector 10 and loop filter 26 operate over time to force the downward edge of the clock signal from VCO 20 to the center of the blivet interval. Because the delay elements 2 and 4 are identical, they produce equal delays despite process and temperature variations. Therefore, changes in process or temperature affect the blivet width, which affects the NRZ phase detector's sensitivity, but not its ability to properly detect phase differences. Sensitivity increases with increasing blivet width, because the difference between the widths of the "up" and "down" pulses can be greater. The clock output of the VCO 20 is also applied to the clock input of flip-flop 28. The D input of flip-flop 28 is connected to receive the once delayed NRZ data output of the blivet generator 8, from the output of delay element 2. In the approach utilized in this invention, the ability to position the clock edge that clocks the data into flip-flop 28 in the center of the "eye" of the bit interval depends on the centering of the opposite clock edge within the blivet, as described above. The VCO is balanced to have a near perfect 50% duty cycle. So, with the VCO 20 clock output low-going transitions centered in the blivets from XOR gate 6, the high going transitions are guaranteed to occur while the data present at the junction of the two delay elements 2 and 4 is right in the middle of the bit interval. This is because the falling clock edge occurred half of blivet after the end of the last bit interval, and data at this junction is also delayed by one half blivet at the time of the rising clock edge. The D input of flip-flop 28 is connected to this junction between the delay elements 2 and 4 and is clocked by the rising edge of the VCO 20 output clock signals. Thus, the circuit shown in FIG. 3 reliably recovers NRZ clock and data signals and lends itself to integration into an IC. The circuit shown in FIG. 3 only performs phase detection, not frequency detection. Yet frequency detection permits much more efficient frequency acquisition by a phase lock loop. Consequently, referring now to FIG. 4, a complete system for NRZ clock and data recovery includes all of the circuitry shown in FIG. 3, plus an NRZ frequency detector 50, a lock detector 30 and OR gates 24 and 22 for combining the "up" and "down" outputs of the phase and NRZ frequency detectors before they are presented to the loop filter 26. In the full system shown in FIG. 4, the blivet signal is supplied to the NRZ frequency detector 50 and the lock detector 30, as well as the NRZ phase detector 10. The NRZ frequency detector 50 also receives the clock output of the VCO 20 and a "lock" signal from the lock detector 30. Like the NRZ phase detector 10, the NRZ frequency detector 50 produces "up" and "down" signals to steer the VCO 20 via the loop filter 26. These "up" and "down" signals are combined with the "up" and "down" signals from the NRZ phase detector 10 by up OR gate 24 and down OR gate 22. The NRZ frequency detector 50 also produces "not-good" signals that inform the lock detector 30 when the present blivet is going to cause an "up" or "down" signal. Referring now to FIG. 5, the NRZ frequency detector 50 contains four flip-flops 52, 57, 58 and 59 that are clocked by the rising edge of the blivet signal and one flip-flop 53 that is clocked by the falling edge of the blivet signal, due to the operation of inverter 51. Flip-flops 52 and 53 monitor the clock output of the VCO 20 on opposite edges of the blivet signal. A "good" blivet is a blivet whose rising edge occurs while the VCO 20 clock out is high and whose falling edge occurs while it is low. A good blivet therefore sets flip-flop 52 and resets flip-flop 53. NAND gate 54 monitors the Q output of flip-flop 52 and the /Q output of flip-flop 53, and produces a low output whenever a good blivet has been detected by these two flip-flops. The following table summarizes the information inferred by the NRZ frequency detector 50 circuitry from the relationship between the clock output level and the blivet edges: CLOCK/BLIVET INFERENCES High-going Edge (FF52) Low-going Edge (FF53) Frequency Inference 1 0 good 1 1 Too Low 0 0 Too High 0 1 Unclear (?) NAND gate 55 monitors the states of flip-flops 52 and 53 for the "tool-low" condition, i.e., both flip-flops having a high output. The third input to this NAND gate 55 is from the D-C flip-flop created by NAND gates 62 and 63, which produces a high output from NAND gate 62 and a low output from NAND gate 63 when the frequency is too high. The reason for this third input to NAND gate 55 is to prevent going directly from a "too-high" condition to a "too-low" condition without going through a good state in-between. Thus, when the last state out of the NRZ frequency detector was "Down (too-high)", NAND gate 55 is prevented from producing an active-low output indicating that the next state should be "Up (too-low)" by the low output of NAND gate 63. Similarly, NAND gate 56 monitors the states of flip-flops 52 and 53 for the "too-high" condition, i.e., both flip-flops having a low output. And, in the same way as before, a high output of NAND gate 61 in the other D-C flip-flop, indicating that the last state was not "too-low", is required before an active "too-high" signal can be produced. The D-C flip-flops 64 and 65, comprising NAND gates 60, 61 and 62, 63 hold the last known frequency direction, too-low, too-high or neither, until a /good blivet occurs. An active low/good signal attempts to clear both of the D-C flip-flops, and will do so in the absence of an active low /too-low or /too-high signal. The states of the NAND gates 54, 55 and 56 are clocked into flip-flops 57, 58 and 59, respectively, by the rising edge of the next blivet, if the signal lock is inactive low, indicating that the phase lock loop is not locked. If the signal lock is active high, indicating that a phase lock loop lock has been detected, the signal lock forces the /good flip-flop 57 to its cleared state, producing an inactive high output from that flip-flip, which indicates that the state is "good". The active high lock signal also forces the "too-low" and "too-high" flip-flops to ignore their inputs from NAND gates 55 and 56, respectively, and produce inactive high outputs. Thus, while the loop is locked, the NRZ frequency detector cannot produce any output to disrupt that lock, leaving control entirely up to the NRZ phase detector 10. Note, however, that even while the loop is locked and the up and down outputs of the NRZ frequency detector 50 are disabled, it can still produce /good (blivet) signal outputs from NAND gate 54. Thus, as will be further explained below, if enough /good blivets are detected, the lock detector 30 can respond by decrementing down to below its one half full level and going to an unlocked condition. Referring now to FIG. 6, a series of blivets produces appropriate results in the presence of three different clock frequencies, one correct, one too-high and one too-low. In FIG. 6, good relationships between blivets and clock levels are indicated by "O"s above clock signal, while too low relationships are indicated with an "L" and too-highs with an "H". Unclear results, where the clock is low for the rising blivet edge and high for falling blivet edge, are indicated with a "?". Everything is simple for the "Correct Clock Freq" line, with each blivet producing a "O". The "Clock Low" line is much more interesting, producing the sequence of relationships: "OOLL??HOO?". The unclear, ?, indications are totally unrecognized by the circuitry shown in FIG. 5, so the "H" at blivet 7 is ignored because the last indication was a "L" and so the output of NAND gate 61 is low disabling NAND gate 56 which would otherwise detect this "H". Even though the "H" is not detected, the failure to satisfy NAND gate 54 because the Q output of flip-flop 52 is low causes the output of NAND gate 54 to go high, and this high is clocked into flip-flop 57 by the next blivet (blivet 8). The continuing high output of flip-flop 57 has no effect on the D-C flip-flops comprising NAND gates 60, 61 and 62, 63. The good blivet at blivet 8 is detected by NAND gate 54, whose output goes low in response. The good state of flip-flops 52 and 53 also means that neither of the other NAND gates 55 or 56 are satisfied. The low output of NAND gate 54 is clocked into flip-flop 57 on the rising edge of blivet 9. The same rising clock edge of blivet 9 also clocks the high levels that are present on the output of NAND gates 55 and 56 into flip-flops 58 and 59, respectively. The low output of flip-flop 57 immediately clears the two D-C flip-flops 60,61 and 62,63, so that their outputs on NAND gates 60 and 62 become low, since both of both of their inputs are now high. The cleared states of the D-C flip-flops 60,61 and 62,63 enable the third inputs to NAND gates 55 and 56, allowing them tc detect the next high or low state. If the frequency were now correct, mostly good blivets would be detected from now on and the NRZ frequency detector would behave as it does on the line labeled "Correct Clock Freq". In the absence of jitter, an incorrect frequency will produce indications like those shown in FIG. 6, in which the desired indication always follows a good blivet, and any erroneous indications always follow a desired indication and are locked out by it. In the presence of jitter, however, erroneous indications sometimes follow a good blivet and reach the output. Even in the presence of heavy jitter, though, the desired indications always heavily out-weigh the erroneous ones and the system successfully locks onto the correct frequency. For the NRZ frequency detector 50 to work correctly, the blivet length has to be less than one half of the bit interval. And, since resistors implemented in silicon and metal capacitors both have tolerances of up to +/- 20%, and the delay elements 2 and 4 are based on an RC product of such devices, the worst case delay tolerance could be as bad as +/- 40%. Thus, if the delay lines are designed to produce a combined delay of 35% of the bit interval, the worst case deviation still leaves the resulting total delay under half of the bit interval, thereby permitting the NRZ frequency detector 50 to function properly. Referring now to FIG. 7, the lock detector 30 receives as its inputs the blivet signal and the /good signal. Counter 42 is a saturating up/down counter. A saturating counter is a counter that does not wrap around; when it reaches a full count, it stays there as additional increment signals are received. The saturating up/down counter 42 is incremented by incrementing means 38 whenever a "good" blivet is detected by AND gate 32, and decremented by decrementing means 40 whenever a "bad" blivet is detected by AND gate 36. Inverter 34 changes the /good signal into a good signal for AND gate 32. When the count in the counter reaches a threshold, for instance, more than half full, a "lock" signal is generated. The ratio of the increment step size (typically one) to the decrement step size (typically some multiple of increment size) determines the tolerance of the lock detector 30 to jitter. A 1:4 ratio has been found to provide a suitable jitter tolerance. The size of the saturating up/down counter 42 (in bits) determines the integration time of the lock detector 30, and hence its response time to a locked or unlocked condition. There is a trade-off between the speed with which a lock is identified and the certainty of that identification. In the present application, 12 bits of binary, for a total count of 4096, has been found to be a suitable length for this counter, so that a lock indication appears after a count of 2048. If jitter is minimal, a lock is achieved in about 15 microseconds at 270 Megabits per second. This lock detector 30 implementation is completely digital and therefore does not require an analog integration capacitor and associated IC pin. This is a significant benefit in some applications where a shortage of IC pins is an important design constraint. Thus, it can be seen that the present invention provides an improved NRZ clock and data recovery system that lends itself to integration, that includes a NRZ phase detector, preferably an NRZ frequency detector and a lock detector, preferably and that provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations. While a preferred embodiment of the present invention has been shown and described, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the invention in its broader aspects.

Claims: An NRZ clock/data recovery system using a phase locked loop characterized by: a blivet generator (8) coupled to receive an NRZ input signal in order to produce a once delayed NRZ signal and a blivet signal derived from a twice delayed NRZ signal and the NRZ input signal, the blivet signal providing a pulse for each transition of the NRZ input signal; a controllable oscillator (20) coupled to receive an oscillator control signal in order to produce a recovered clock signal; an NRZ phase detector (10) coupled to receive the recovered clock signal and the blivet signal in order to produce a first up signal and a first down signal; a loop filter (26) coupled to receive as first and second inputs the first up and down signals in order to produce the oscillator control signal; and a data recovery circuit (28) coupled to receive the once delayed NRZ signal in order to produce a recovered data output signal in response to the recovered clock signal. The NRZ clock/data recovery system as recited in claim 1 further including: a frequency detector (50) coupled to receive the blivet signal and the recovered clock signal in order to produce a second up signal and a second down signal; and a combining circuit (22, 24) coupled between the NRZ phase detector and the loop filter to receive the first and second up and down signals in order to produce a combined up signal and a combined down signal as the first and second inputs to the loop filter. The NRZ clock/data recovery system as recited in claim 2 further including a lock detector (30) coupled to receive the blivet signal and a not-good blivet signal from the frequency detector in order to produce a lock signal to inhibit the frequency detector from producing the second up and down signals when the number of pulses of the blivet signal received bears a predetermined relationship to the number of pulses of the not-good blivet signal received. The NRZ clock/data recovery system as recited in claims 1, 2 or 3 wherein the blivet generator includes: a first delay circuit (2) coupled to receive the NRZ input signal in order to produce the once delayed NRZ signal; a second delay circuit (4) coupled to receive the once delayed NRZ signal in order to produce the twice delayed NRZ signal; and an exclusive OR gate (6) coupled to receive the NRZ input signal and the twice delayed NRZ signal in order to produce the blivet signal, the pulses of the blivet signal occurring when the state of the NRZ input signal is different from the state of the twice delayed NRZ signal. The NRZ clock/data recovery system as recited in claim 4 wherein the first and second delay circuits produce substantially equal delays. The NRZ clock/data recovery system as recited in claims 1, 2 or 3 wherein the NRZ phase detector includes: a first gating means (12) coupled to receive the blivet signal and the recovered clock signal in order to produce the first up signal while the state of the recovered clock signal is the same as the state of the blivet signal; an inverter (16) coupled to receive the recovered clock signal in order to produce an inverted recovered clock signal; and second gating means (14) coupled to receive the blivet signal and the inverted recovered clock signal in order to produce the first down signal while the state of the inverted recovered clock signal is the same as the state of the blivet signal. The NRZ clock/data recovery system as recited in claim 2 or 3 wherein the frequency detector includes: means for determining (51, 52, 53) the states of the recovered clock signal at times when edges in the blivet signal occur; and means for ascertaining (55, 56, 64, 65) from the determined states when the frequency of the recovered clock signal is apparently low or apparently high in order to produce the second up signal when the frequency is apparently low and the second down signal when the frequency is apparently high. The NRZ clock/data recovery system as recited in claim 7 wherein the ascertaining means includes: means for ignoring (55, 65) an apparently low frequency when the result of an immediately preceding ascertaining was that the frequency was apparently high; and means for ignoring (56, 64) an apparently high frequency when the result of the immediately preceding ascertaining was that the frequency was apparently low. The NRZ clock/data recovery system as recited in claim 3 wherein the lock detector includes a saturating up/down counter (32 - 44) coupled to increment by a first constant when the states of the blivet signal and an inverted not-good blivet signal are the same and to decrement by a second constant when the states of the blivet signal and the not-good blivet signal are the same in order to produce the lock signal when a predetermined count is reached.

Inventors: HERSHBERGER DAVID L, HERSHBERGER, DAVID L.
Applicants: GRASS VALLEY GROUP, THE GRASS VALLEY GROUP, INC.
Application year: 1992
Main classification: H04L7
IPC codes: H04L7, H04L25, H03M5, H03L7, G11B20