Automatic frequency control circuit

Abstract: In a first embodiment of the present invention, an AFC circuit comprises a frequency divider (24) for dividing a frequency of a local oscillation signal output from a voltage controlled oscillator, and a switch (15) for selecting an output signal of the frequency divider (24) or a pilot signal extracted from converted signals. While the pilot signal is not obtained, the switch selects the output signal of the frequency divider (24), to thereby construct a PLL to stabilize the frequency of the local oscillation signal. In a second embodiment of the present invention, an AFC circuit comprises a frequency divider for selectively dividing a frequency of a pilot signal included in the converted signal. Various frequencies of the pilot signal can be dealt with by altering a division number in the frequency divider.

Description: The present invention relates to an automatic frequency control (AFC) circuit for use in a receiver of radio or satellite communication equipment. More particularly, the present invention is concerned with an AFC circuit providing frequency stability sufficient for use in receivers in a single channel per carrier (SCPC) system. In a SCPC system since a bandwidth occupied by a single channel is very narrow (several dozen kHz) compared with a carrier frequency (more than several hundred MHz), and tends to be narrower every year to raise the utilization factor of frequencies, a high level of stability of a received frequency is strongly recommended to ensure stable communication. However, the stability of a frequency of a signal received from a satellite is limited to a certain level because of unstable influences from a local oscillator mounted on the satellite, the Doppler effect, and the instability of a high-frequency circuit of a receiver. Therefore, an AFC system is employed to ensure stable communication. From EP-A-0 075 332 an AFC circuit is known in a TV or radio reception circuit which has a phase detector supplied with alternative input signals. The reception circuit has a mixture stage coupled to a voltage controlled oscillator (VCO) connected in a phase-locked loop. The intermediate frequency output signal of the mixture stage and the output signal of the voltage controlled oscillator are alternately coupled by a switch to the regulating circuit, either directly or via frequency dividers. The regulating circuit comprises the phase comparator and a local oscillator. In the known circuit, the filter extracts the signal which includes information signals to perform automatic frequency control. In another AFC system, a pilot signal not including modulation components is transmitted in a specific frequency position within the used band and the frequency of a local oscillator is automatically controlled so that the frequency of a received pilot signal is converted into a precise frequency in a frequency converter. The local oscillator consists of a voltage controlled oscillator (VCO). The received radio frequency signal or an intermediate frequency signal is converted into an intermediate frequency signal or a lower intermediate frequency signal by being mixed with an output of the VCO in the frequency converter. The pilot signal is extracted from an output of the frequency converter through a band pass filter having a narrow passband and is compared with a reference frequency output from a reference oscillator in a phase comparator. An output of the phase comparator is applied through a loop filter to the VCO as a control signal, to thereby control the frequency and the phase of the extracted pilot signal so as to be equal to those of the reference signal. Since frequencies of the other received signals within that band fluctuate simultaneously with the received pilot signal, the fluctuations of the other received signals are compensated for in converted signals. Usually, the pilot signal is transmitted only from a master station or a reference station supervising a whole communication network. Therefore, the pilot signal is not obtained when a transmission of the pilot signal is terminated for some reason or other, when the receiver is used in a system where the pilot signal is not transmitted, or when a loop test is carried out within a part of the transmission paths. Conventionally, in order to maintain receiver functions even when the pilot signal is not obtained, a switch is provided between the VCO and the loop filter for selecting the output of the loop filter or a fixed bias voltage. If the pilot signal is obtained, the switch is set so as to select the output of the loop filter, and if the pilot signal is not obtained, the switch is set so as to select the fixed bias voltage. In the above construction, since frequency stability of outputs of the frequency converter is determined by the stability of the VCO while the pilot signal is not obtained, a high level of stability is required in the VCO. However, since the stability of the VCO is determined by an oscillation frequency, a variable range, and the quality factor (Q) of a resonator, etc., it is very difficult to obtain a VCO having a high level of stability as well as an ultra high operating frequency (more than several hundred MHz) and a variable range necessary for searching over the assigned frequency band to catch the pilot signal. For example, frequency stability of 10 -6 is realized by using a crystal oscillator as a reference oscillator when the pilot signal is obtained, whereas the same frequency stability cannot be realized in practice when the pilot signal is not obtained, because frequency stability of the VCO is generally about 10 -4 . In this case, if the output frequency of the VCO is 1,120 MHz to convert 1,190 MHz into 70 MHz, the output frequency of the VCO fluctuates over a range of 112 kHz (1120 MHz * 10 -4 ). Therefore, if the bandwidth of a channel is 45 kHz, a designated channel cannot be received because the width of the fluctuation is larger than the bandwidth. It is an object of the present invention to provide an AFC circuit that enables precise frequency control even when a pilot signal is not obtained. In accordance with the present invention this object is achieved by an automatic frequency control circuit supplied with input signals including information carrying signals and a pilot signal not carrying information, comprising: frequency conversion means for converting the input signals into converted signals having frequencies different than the frequencies of the input signals by mixing a local oscillation signal with the input signals; extraction means for extracting the pilot signal having a specific frequency from the converted signals and outputting it; oscillation means for outputting a reference signal having a reference frequency; phase comparison means having first and second input terminals for comparing a first frequency and a first phase of the reference signal input to the first input terminal with a second frequency and a second phase of a selected signal input to the second input terminal, to output a comparison result; variable oscillation means for outputting, to the frequency conversion means the local oscillation signal having a frequency varying in accordance with the comparison result; frequency division means for dividing the frequency of the local oscillation signal by a division number to output a frequency-divided local oscillation signal; and switch means for selecting one of the pilot signal and the frequency-divided local oscillation signal to output the selected signal to the second input terminal of the phase comparison means. Figure 1 is a diagram showing an example of disposition of signals in a SCPC system; Figure 2 is a block diagram showing a construction of an AFC circuit according to an embodiment of the present invention; Figure 3 is a block diagram showing a construction of an AFC circuit as a modification of the AFC circuit of Fig. 2; Figure 4 is a circuit diagram of a loop filter 22 used in the AFC circuit of Fig. 3; Figure 5 is a block diagram showing a construction of an AFC circuit as another modification of the AFC circuit of Fig. 2; Figure 6 is a flow chart showing a control process in the controller 42 of Fig. 5; Figure 7 is a block diagram showing a construction of an AFC circuit as another modification of AFC circuit of Fig. 2; Figures 8A and 8B are flow charts showing examples of a control process in the controller 52 of Fig. 7. Figure 9 is a block diagram showing a construction of an AFC circuit as another modification of the AFC circuit of Fig. 2; Figure 10 is a flow chart showing a control process in the controller 76 of Fig. 9; Figure 11 is a block diagram showing a construction of an AFC circuit as a modification of the AFC circuit of Fig. 9; Figure 12 is a flow chart showing a control process in the controller 94 of Fig. 11. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows an example of disposition of signals in a received signal of a SCPC system. As shown in Fig. 1, channel slots CH1 to CHn for channel 1 to channel n are assigned at constant channel intervals and a pilot signal from a reference station is transmitted in a frequency position within the band. In an AFC circuit, a frequency of a local oscillator is controlled so that a frequency of the received pilot signal is converted into a frequency equal to a frequency of a reference oscillator. Since frequencies of received signals of the channel 1 to the channel n fluctuate simultaneously with that of the received pilot signal, the fluctuations of the frequencies of the received signals are compensated for in the converted signals. Figure 2 is a block diagram showing a construction of an AFC circuit according to an embodiment of the present invention. A radio frequency signal having a frequency of ƒ RF or an intermediate frequency signal is mixed in a frequency converter 10 with an output signal of a voltage controlled oscillator (VCO) 12, to be thereby converted into an intermediate frequency signal having a frequency of ƒ IF or a lower intermediate frequency signal. The output signals of the frequency converter 10 branch in a branching circuit (not shown) and the pilot signal contained in the branch signal is extracted through a band pass filter 14 having a narrow passband. The extracted pilot signal is input to one input terminal A of a manual switch 15. While the manual switch 15 selects the terminal A, the extracted pilot signal having a frequency of ƒ P is input to one input terminal of a phase comparator 18. A reference signal having a frequency of ƒ r is generated in a reference oscillator 20 and is input to another input terminal of the phase comparator 18. The phase comparator 18 compares frequency and phase of the two input signals and outputs the comparison result through a loop filter 22 to the VCO 12 as a control voltage. An output signal having a frequency of ƒ L is fed from the VCO 12 to the frequency converter 10. The signal ƒ L is also fed to a frequency divider 24. The frequency-divided signal is fed to another input terminal B of the manual switch 15. While the pilot signal is obtained, an AFC loop similar to the conventional AFC circuit is constructed by setting the manual switch 15 so as to select the terminal A (AFC-ON). When the pilot signal is not obtained, the manual switch 15 is set so as to select the terminal B (AFC-OFF). Then, as a phase lock loop (PLL) is constructed, a stable frequency ƒ L based on the reference frequency ƒ r is obtained. The frequencies ƒ IF and ƒ r are designed so that ƒ L is an integral multiple of ƒ r . The division number N of the frequency divider 24 is given as N = ƒ L /ƒ r For example, if the input frequency ƒ RF of the frequency converter 10 is 1,190 MHz, the output frequency ƒ IF is 70 MHz, the output frequency ƒ L of the VCO 12 is 1,120 MHz, and the pilot signal exists at the center of the frequency band, then the pilot frequency ƒ P becomes 70 MHz. While the manual switch 15 selects the terminal A, the local frequency ƒ L is controlled by the error signal from the phase comparator 18 so that ƒ P becomes equal to ƒ r . If the reference frequency ƒ r is 70 MHz, the output frequency ƒ IF is kept to 70 MHz by varying the local frequency ƒ L nearly at 1,120 MHz even when the input frequency ƒ RF fluctuates. When frequency stability of the reference oscillator 20 is 1 × 10 -7 , the same stability is obtained in ƒ IF . While the manual switch 15 selects the terminal B, an output signal of the frequency divider 24 having a frequency of ƒ P = ƒ L /N, i.e., 70 MHz where N = 16, is fed to one input terminal of the phase comparator 18, and the VCO 12 is controlled so that ƒ P becomes equal to ƒ r . Since the output signal of the VCO 12 is in phase-synchronism with the output signal of the reference oscillator 20, frequency stability of the VCO 12 becomes equal to that of the reference oscillator 20, i.e., 1 × 10 -7 , or 112 Hz for ƒ L = 1,120 MHz. Figure 3 is a block diagram showing a construction of an AFC circuit as a modification of the AFC circuit of Fig. 2. In the AFC circuit of Fig. 3, a controller 26 is provided for switching parameters of the loop filter 22 simultaneously with switching of a switch 16 provided instead of the manual switch 15. If a response characteristic required in PLL during AFC-OFF is not equal to a response characteristic in AFC loop during AFC-ON, the simultaneous switching of the parameters of the loop filter 22 improves the response characteristic under optimum parameters. Figure 4 is a circuit diagram of the loop filter 22 used in the AFC circuit of Fig. 3. The loop filter 22 consists of an amplifier 28, a capacitor 30, and resisters 32 to 36. The loop parameter of the loop filter 22 is determined by parameters of the capacitance 30, resistor 32 and resister 34 or 36. By switching a switch 38 in synchronism with the AFC ON/OFF, the response characteristic of the loop is altered. Thus, the optimum response characteristic is always obtained by altering the parameters of the loop filter 22 according to a distinction of the control loop in AFC ON/OFF. Figure 5 is a block diagram showing a construction of an AFC circuit as another modification of the AFC circuit of Fig. 2. A detector 40 detects the presence or absence of the pilot signal and a controller 42 controls the switch 16 according to an output signal of the detector 40. In the circuit of Fig. 5, when the detector 40 detects the interruption of the pilot signal, the controller 42 automatically changes the AFC loop to the PLL by controlling the switch 16, to thus obtain a stable output frequency of the VCO 12. Since the interruption of the pilot signal is also detected in the reference station and a system for transmitting the pilot signal is automatically swapped to a spare system, the pilot signal is again transmitted after a short interruption. Then, the detector 40 detects the pilot signal and the controller 42 automatically changes the PLL to the AFC loop. Figure 6 is a flow chart showing the control process in the controller 42. In step 44, if the pilot signal is absent, the switch 16 is set so as to select the terminal B in step 46 to construct the PLL. If the pilot signal is present in step 44, the switch 16 is set so as to select the terminal to construct the AFC loop in step 48. Figure 7 is a block diagram showing a construction of an AFC circuit as another modification of the AFC circuit of Fig. 2. The AFC circuit of Fig. 7 comprises an alarm generator 50 for detecting an abnormal output of the phase comparator 18 and for outputting an alarm signal, and a controller 52 for controlling the switch 16 according to the alarm signal. When the pilot signal is interrupted, the phase comparator 18 is latched to one side and outputs a maximum or minimum value. The alarm generator 50 detects this abnormal output and then outputs the alarm signal. Figure 8A is a flow chart showing a first example of a control process in the controller 52. When the alarm is not output from the alarm generator 50 in step 54, the switch 16 is set so as to select the terminal A to construct the AFC loop in step 56. If the alarm is output in step 54, the switch 16 is set so as to select the terminal B to construct the PLL in step 58, and the control process stops until the process restarts. Figure 8B is a flow chart showing a second example of a control process in the controller 52. When the alarm is not output from the alarm generator 50 in step 60, the switch 16 is set so as to select the terminal A in step 61 and a parameter K is reset to zero in step 62. If the alarm is output in step 60, the switch 16 is set so as to select the terminal B to construct the PLL in step 63. If the parameter K does not reach K 0 (for example, K 0 = 3) in step 64, the parameter K is increased in step 65, a wait operation for a time τ 1 is carried out in step 66, the switch 16 is set so as to select the terminal A in step 68, and the process returns to the step 60. If the parameter K reaches K 0 in step 64, the control process stops until the process restarts. The wait time τ 1 is set as longer than the interruption time of the pilot signal necessary for switching the current to spare. Figure 9 is a block diagram showing a construction of an AFC circuit as another modification of the AFC circuit of Fig. 2. The AFC circuit of Fig. 9 comprises a detector 40 that is the same as that of Fig. 5. In addition, the AFC circuit comprises a frequency divider 70 for dividing the reference frequency from the reference oscillator 20 by an integer M, a frequency divider 72 for dividing the frequency of the pilot signal by an integer P, a variable frequency divider 74 for dividing the frequency of the output signal of the VCO 12 by a variable division number N and a controller 76 for controlling the switch 16 and for giving the division number N to the variable frequency divider 74 in response to the output signal of the detector 40. Although the pilot signal is again transmitted after an AFC-OFF connection is performed in response to the detection of the interruption of the pilot signal, the pilot signal may not be caught by merely performing AFC-ON connection if a frequency of the pilot signal is altered or is drifted during the interruption. In the AFC circuit of Fig. 9, in order to catch the altered or drifted pilot frequency, the division number of the variable frequency divider 74 is scanned over an assigned range in the AFC-OFF connection until the pilot signal is detected. After the pilot signal is detected, AFC-ON is performed. In the AFC-off (PLL) connection where the switch 16 selects the terminal B, if a frequency of the one input of the phase comparator 18 is represented by ƒ r , the output frequency ƒ L of the VCO 12 after establishment of synchronism is represented as ƒ L = N × ƒ r where ƒ r is 1/M of the frequency of the reference oscillator 20. Thus, by varying the division number N of the variable frequency divider 74, ƒ L can be varied stepwise by ƒ r . For example, in the aforementioned case where ƒ L = 1,120 MHz, N is 1,120,000 if ƒ r = 1 kHz, and ƒ L becomes 1,120.001 MHz if the N increases by 1. Therefore, the pilot signal can be searched over an assigned range where the pilot signal is expected to exist, by varying the ƒ L and the variation of the ƒ L can be performed by varying the N by the controller 76. The 1/P divider 72 is provided for equalizing the frequency of the extracted pilot signal to the ƒ r . Since the equalization of the pilot signal to the ƒ r can also be performed by bypassing the frequency divider 70 simultaneously with AFC-ON (not shown in figure) instead of using the 1/P divider 72; use of the 1/P divider 72 is not essential. Figure 10 is a flow chart showing a control process in the controller 76 of Fig. 9. In step 80, if the pilot signal is detected, the switch 16 is set so as to select the terminal A in step 82. If the pilot signal is not detected in step 80, the switch 16 is set so as to select the terminal B in step 84, and the division number N is scanned within a range from N max to N min in steps 88 to 92 until the pilot signal is detected in step 86. If the pilot signal is detected, the control process returns to step 80. In the aforementioned process, when the pilot signal is interrupted, PLL loop is automatically constructed, and the division number N is scanned to catch the pilot signal to reconstruct the AFC loop. Figure 11 is a block diagram showing a construction of an AFC circuit as a modification of the AFC circuit of Fig. 9. The AFC circuit of Fig. 11 further comprises an alarm generator 50 that is the same as that of Fig. 7. A control process in a controller 94 is shown in a flow chart of Figure 12. In Fig. 12, when the alarm is not output from the alarm generator 50 in step 100, the switch 16 is set so as to select the terminal A in step 102. If the alarm is output in step 100, it is examined whether the pilot signal is detected in detector 40 in step 104. If the pilot signal is detected, the switch 16 is set so as to select the terminal B to construct the PLL in step 106 and the control process stops until the process restarts. If the pilot signal is not detected in step 104, the switch 16 is set so as to select the terminal B and the pilot signal is searched in steps 110 to 116 similar to steps 86 to 92 of Fig. 10.

Claims: An automatic frequency control circuit supplied with input signals including information carrying signals and a pilot signal not carrying information, comprising: frequency conversion means (10) for converting the input signals into converted signals having frequencies different than the frequencies of the input signals by mixing a local oscillation signal with the input signals; extraction means (14) for extracting the pilot signal having a specific frequency from the converted signals and outputting it; oscillation means (20) for outputting a reference signal having a reference frequency; phase comparison means (18) having first and second input terminals for comparing a first frequency and a first phase of the reference signal input to the first input terminal with a second frequency and a second phase of a selected signal input to the second input terminal, to output a comparison result; variable oscillation means (12) for outputting, to the frequency conversion means the local oscillation signal having a frequency varying in accordance with the comparison result; frequency division means (24) for dividing the frequency of the local oscillation signal by a division number to output a frequency-divided local oscillation signal; and switch means (15; 16) for selecting one of the pilot signal and the frequency-divided local oscillation signal to output the selected signal to the second input terminal of the phase comparison means. An automatic frequency control circuit as claimed in claim 1, further comprising: filter means (22) for eliminating high frequency components from the comparison result output from the comparison means, to output a comparison result not including the high frequency components to the variable oscillation means; and control means (26) for controlling a response characteristic of the filter means based on a selection in the switch means. An automatic frequency control circuit as claimed in claim 1 or 2, further comprising: detection means (40) for detecting a presence of the pilot signal output from the extraction means; and control means (42) for controlling the switch means so as to select the frequency-divided local oscillation signal when the detection means does not detect the presence of the pilot signal. An automatic frequency control circuit as claimed in claim 1 or 2, further comprising: alarm generation means (50) for generating an alarm signal based on whether the comparison result has an abnormal value; and control means (52) for controlling the switch means so as to select the frequency-divided local oscillation signal when the alarm generation means generates the alarm signal. An automatic frequency control circuit as claimed in claim 4, wherein the control means controls the switch means so as to select the pilot signal after a predetermined time passes after the switch means selects the frequency-divided local oscillation signal. An automatic frequency control circuit as claimed in claim 3, wherein the frequency division means includes a variable frequency divider having a variable division number, and wherein the control means includes a controller scanning the variable division number of the variable frequency divider after controlling the switch means so as to select the frequency-divided local oscillation signal until the detection means detects the presence of the pilot signal. An automatic frequency control circuit as claimed in claim 6, further comprising an alarm generation means for generating an alarm signal based on whether the comparison result has an abnormal value, wherein the control means controls the switch means so as to select the frequency-divided local oscillation signal when the alarm generation means generates the alarm signal and when the detection means does not detect the presence of the pilot signal.

Inventors: ENDO YOICHI, ITAYA EIJI, KUMAGAI YOSHIAKI, ENDO, YOICHI, ITAYA, EIJI, KUMAGAI, YOSHIAKI, Endo, Yoichi, c/o FUJITSU LIMITED, Itaya, Eiji, c/o FUJITSU LIMITED, Kumagai, Yoshiaki, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H03J7
IPC codes: H03J7