Programmable read only memory

Abstract: A non-volatile memory cell including a pn diode whereby the diode in its normal state represents one logic state and the other logic state is created by fusing the diode for creating a short circuit, and means for sensing the logic state of the diode, comprising means for developing a sense voltage across the diode, a first comparator means for comparing the sense voltage with a first reference voltage greater than the normal junction voltage, a second comparator means for comparing the sense voltage with a second reference voltage less than the normal junction voltage but greater than the fused junction voltage and means responsive to the outputs of the first and second comparator means to provide an output signal which has a first value if the sense voltage is between the first and second reference voltages and a second value if the sense voltage is not between the first and second reference voltages.

Description: Field of the Invention This invention relates to a non-volatile (programmable) read only memory for use in automotive applications. Background Art A variety of programmable read only memories are known. Some contain a fusible link which is blown by a high current pulse or irradiation by ultra violet light. Other types contain floating gates wherein a charge is placed on the gate by applying a high voltage, say about 25 volts. Another method is to apply a high reverse voltage to a Zener diode, much higher than its normal breakdown voltage in order to cause the diode to go open circuit. A problem with all the above types of programmable memory is that they are not suitable for automotive applications wherein in situ programming of the elements is required using only the 12 volt battery power source; furthermore fusible link type memories are not always reliable. It has been proposed to provide a pn diode junction with a metallic layer nearby whereby the diode in its normal state represents one logic state and the other logic state is created by subjecting the diode to a low voltage current pulse in a forward bias direction which is sufficient to fuse the junction by causing migration of metal ions or atoms into the diode junction region. This is described further in the publication IEEE Journal of Solid State circuits, vol. 21, no. 5, October 1986, pages 861-868, by Fukushima et al, titled "A 15-ns 8-kbit Junction-Shorting Registered PROM". A problem with such an arrangement is that said current pulse may destroy the electrical continuity of said metallic layer, resulting in an open circuit. In addition, further metal migration during the lifetime of an otherwise correctly programmed diode junction may destroy electrical continuity. Summary of the Invention It is an object of the present invention to overcome the above problems. The present invention provides a non-volatile memory cell including a pn diode whereby the diode in its normal state represents one logic state and the other logic state is created by fusing the diode for creating a short circuit, and means for sensing the logic state of the diode, characterised in that the means for sensing comprises means for developing a sense voltage across the diode, a first comparator means for comparing the sense voltage with a first reference voltage greater than the normal junction voltage of the pn diode, a second comparator means for comparing the sense voltage with a second reference voltage less than the normal junction voltage but greater than the fused junction voltage of the pn diode and means responsive to the outputs of the first and second comparator means to provide an output signal which has a first value if the sense voltage is between the first and second reference voltages and a second value if the sense voltage is not between the first and second reference voltages. Thus in accordance with the invention the comparator means provides an EXCLUSIVE OR function such that when the comparator outputs values which are different the output signal has a first value (denoting the diode junction is fused and is short circuit, or electrical continuity has been destroyed and it is open circuit) whereas if the comparator values are the same, the output signal has a second value (denoting the diode junction is in a normal condition) Hence in accordance with the invention, it is possible to determine the logic state of the memory cell, whether the cell is in a first state representing a normal condition of the diode junction or in a second state representing an open or short circuit condition of the diode junction. Brief Description of the Drawings A preferred embodiment of the invention will now be described with reference to the accompanying drawings wherein:- Figure 1 is a circuit diagram of a memory cell in accordance with the invention. Description of the Preferred Embodiment Referring to Figure 1 there is shown a memory cell of a programmable read only memory comprising as its central element a base emitter junction 2 of a bipolar transistor Q3. This base emitter junction is of a construction to permit fusing of the junction when a low voltage current pulse is applied thereto such as to change the normal diode junction voltage of 0.7 volts to a low value of 0.1 volts. These two different states represent different logic states of the memory cell. For programming the junction 2, a Darlington pair of transistors Q1, Q2 is coupled between a supply voltage V cc and the base of junction 2. A program logic signal is applied to the base of transistor Q1 in order to effect programming. In order to determine the state of the diode junction, a sense circuit 4 is provided comprising a voltage V m applied via a resistor R1 to diode 2 in order to develop a sense voltage thereacross. This sense voltage is applied to the inverting input of a first operational amplifier or comparator C1 and to the non-inverting input of a second operational amplifier or comparator C2. A reference voltage of 1.0 volts is applied to the non-inverting input of comparator C1 and a reference of 0.2 volts is applied to the inverting input of comparator C2. The outputs of comparators C1 and C2 are connected in common to the input of an inverting I2L gate 6. The input of gate 6 is also coupled by a load resistor R2 to voltage V m . Gate 6 is powered by a supply voltage R 1 . Thus in operation, diode 2 may have a normal voltage of 0.7 volts, or if programming has been effected a short circuit voltage of 0.1 volts or, if electrical continuity has been broken, an open circuit voltage which will be equal to V m . In order to sense the logical state of diode 2, if the diode is in its normal state providing a sense voltage of 0.7 volts then both the comparators will provide a positive output. That is to say the output transistors of comparators C1 and C2 will be off giving positive outputs and permitting current injection by a resistance R2 to the input of gate 6, which gate inverts to give a zero volt output. If diode 2 has been fused by appropriate programming, resulting in a low junction voltage of 0.1 volts or thereabouts, this voltage applied to the inputs of comparators C1, C2 result in comparator C1 remaining high at its output whereas comparator C2 goes low in the sense that its output transistor is turned on resulting in a drain of current from resistor R2 so that no current is injected into gate 6 and the output of gate 6 remains high. If during the programming of junction 2, the junction goes open circuit, then a voltage V m is applied to the inputs of comparators C1, C2, resulting in the output of C1 going low whereas the output of C2 is high. Thus the output transistor of C1 is turned on which drains the current from resistor R2 and prevents current injection into gate 6. Thus the output of gate 6 remains high.

Claims: A non-volatile memory cell including a pn diode (2) whereby the diode in its normal state represents one logic state and the other logic state is created by fusing the diode for creating a short circuit, and means for sensing the logic state of the diode, characterized in that the means for sensing comprises means (R1) for developing a sense voltage across the diode, a first comparator means (C1) for comparing the sense voltage with a first reference voltage greater than the normal junction voltage of the pn diode, a second comparator means (C2) for comparing the sense voltage with a second reference voltage less than the normal junction voltage but greater than the fused junction voltage of the pn diode and means (6,R2) responsive to the outputs of the first and second comparator means to provide an output signal which has a first value if the sense voltage is between the first and second reference voltages and a second value if the sense voltage is not between the first and second reference voltages. A cell as claimed in claim 1, wherein the diode (2) is provided by the emitter of the bipolar transistor (Q3). A cell as claimed in claim 1 or 2, wherein said means for developing a sense voltage comprises a first resistance (R1) coupled between a memory power supply (Vm) and the diode (2), the first and second comparator means being coupled to a node between the diode and the first resistance. A cell as claimed in any preceding claim, wherein the first comparator means (C1) comprises a first operational amplifier having a non-inverting input (+) coupled to the first reference voltage (1V) and an inverting input (-) connected to the sense voltage means (R1). A cell as claimed in any preceding claim, wherein the second comparator means (C2) comprises a second operational amplifier being a non-inverting input (+) connected to the sense voltage means (R1) and an inverting input (-) connected to the second reference voltage (0.2V). A cell as claimed in any preceding claim, wherein the output of the first and second comparator means are connected in common to the input of an output gate means (6). A cell as claimed in claim 6, wherein the output gate means (6) comprises an inverting I 2 L gate. A cell as claimed in claim 6 or 7 wherein a load resistance (R2) is connected between the outputs of the comparator means (C1,C2) and a memory power supply (Vm). A cell as claimed in any preceding claim, including means for programming the diode comprising a Darlington pair of transistors (Q1, Q2) coupled to the diode.

Inventors: BURRI MICHEL, BURRI, MICHEL
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1992
Main classification: G11C17
IPC codes: G11C17, H01L27, G01R31, H01L21