Semiconductor read only memory

Abstract: A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a semiconductor read only memory, and more particularly to a semiconductor read only memory in which MOSFETs constituting memory cells are connected in parallel. 2. Description of the Prior Art: Figure 5 shows an equivalent circuit of a semiconductor read only memory (hereinafter, sometimes referred to simply as "a ROM") which is conventionally and widely used. This ROM is a lateral ROM constructed in such a manner that memory cells 3 of MOSFETs are connected in parallel with respect to a plurality of bit lines 2 which cross word lines 1 . It is known that each of the bit lines 2 is made of metal or made by diffusion (the former is referred to as a metal bit line, and the latter is referred to as a diffusion bit line). In order to dispose memory cells more densely, a hierarchical system (hereinafter, referred to as a hierarchical bit line system) has been proposed (Japanese Patent Application No. 63-75300), as shown in Figure 6 . In the system, main bit lines Mb l , Mb l+1 , ···, etc. and sub-bit lines bm 2l , bm 2l+1 , ···, etc. are hierarchically provided. In the hierarchical bit line system, each of the memory cells such as Mm 2l.2 is connected between two adjacent sub-bit lines, and the memory cells are alternately assigned into two groups of odd-numbered banks such as Bm 2l-1 and even-numbered banks such as Bm 2l . For the selection of these banks, bank selecting MOSFETs QO m.2l , QE m.2l , ···, etc. are provided on both ends of the sub-bit lines, respectively. Bank select lines BO m and BE m are connected to these bank selecting MOSFETs. The main bit lines Mb l , Mb l+1 , ···, etc. are connected to sense amplifiers such as SA l , or connected to GND via MOSFETs such as Q l+1 . In the ROM with the hierarchical bit line system, the wired pitch of the main bit lines can be made double as compared with the conventional lateral ROM shown in Figure 5 . The ROM with the hierarchical bit line system can advantageously reduce the parasitic capacitance on bit lines, and especially when the diffusion bit lines are used, the wiring resistance on bit lines can be greatly reduced. However, when the diffusion bit lines are used in the hierarchical bit line system shown in Figure 6 , there arises a problem in that the diffusion resistance greatly varies depending on the position of a memory cell in a bank, which is described below, so that the value of discharge current for the read of information greatly varies depending on the position of the memory cell. There is another problem in that since the value of the diffusion resistance is large and the value of the discharge current is small, such a ROM is not suitable for high-speed reading. For example, the case where information is read out from a memory cell Mm 2l-1.1 by setting the bank select line BO m High, the other bank select line BE m Low, and the word line WL 1 High is considered. In this case, the control signal VG for the transistor Q l (not shown) connected to the main bit line Mb l is made Low. The control signal VG for the transistor Q l-1 connected to the adjacent main bit line Mb l-1 is made High, so that the main bit line Mb l-1 is connected to the GND. The circuit in the above-mentioned state is shown in Figure 7 . The discharge current i flows through the main bit line Mb l , the bank selecting MOSFET QO m.2l-1 , the sub-bit line b m.2l-1 , the memory cell Mm 2l-1.1 , the sub-bit line b m.2l-2 , and the main bit line Mb l-1 , in this order. The total value of diffusion resistance of the sub-bit lines b m.2l-1 and b m.2l-2 in this path is 2r, if the resistance value between respective two cells is indicated by r. Now, the case where information is read out from a memory cell Mm 2l-1.n is considered. The circuit in this case is shown in Figure 8 . The total value of diffusion resistance of the sub-bit lines b m.2l-1 and b m.2l-2 in the path is 2nr. In this case, the diffusion resistance of sub-bit lines becomes largest. As described above, in the ROM shown in Figure 6 , the value of diffusion resistance greatly varies depending on the position of a memory cell from which information is read out. SUMMARY OF THE INVENTION The semiconductor read only memory of this invention, which overcomes the above-discussed and numerous other disadvantages and deficiencies of the prior art, comprises: a plurality of first bit lines disposed in parallel; a plurality of groups of memory cells, in each group, cells being connected in parallel between two adjacent ones of said first bit lines; second bit lines disposed in parallel to said first bit lines, the proportion of said second bit lines to said first bit lines being 1 to 2; a group of first bank selecting switches each of which is connected between one end of an odd-numbered one of said first bit lines and one end of an odd-numbered one of said second bit lines; and a group of second bank selecting switches each of which is connected between one end of an even-numbered one of said first bit lines which is adjacent to a said odd-numbered one of said first bit lines and one end of an even-numbered one of said second bit lines. In a preferred embodiment, said groups of first and second bank selecting switches are constructed using a plurality of pairs of two adjacent selecting switches, said adjacent two selecting switches being connected to the same one of said second bit lines. In a preferred embodiment, said memory cells and said selecting switches are MOSFETs. In a preferred embodiment, said first bit lines are made by diffusion layers, and said second bit lines are metal lines. Thus, the invention described herein makes possible the objective of providing a ROM capable of reading out at a high speed while provided with memory cells densely disposed. BRIEF DESCRIPTION OF THE DRAWINGS This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1 is a circuit diagram showing a portion of a ROM in one embodiment of the invention. Figure 2 shows a layout of the embodiment having diffusion bit lines. Figure 3 is a circuit diagram schematically showing the current flow when information is read out from a memory cell in the embodiment. Figure 4 is a circuit diagram schematically showing the current flow when information is read out from another memory cell which is positioned differently in the embodiment. Figure 5 is a circuit diagram showing a prior art ROM. Figure 6 is a circuit diagram showing a prior art ROM with a hierarchical bit line system. Figure 7 is a circuit diagram schematically showing the current flow when information is read out from a memory cell in the prior art ROM shown in Figure 6 . Figure 8 is a circuit diagram schematically showing the current flow when information is read out from another memory cell which is positioned differently in the prior art ROM shown in Figure 6 . DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows a portion of a ROM in one embodiment of the invention. Figure 2 shows a pattern on the surface of a semiconductor substrate in this embodiment. The ROM of this embodiment basically adopts a hierarchical bit line system. The bit lines are constituted by sub-bit lines SB 1 , SB 2 , ···, etc., and main bit lines MB 1 , MB 2 , ···, etc. Each of the main bit lines (e.g., MB 1 ) is formed between an odd-numbered sub-bit line and the succeeding even-numbered sub-bit line (e.g., between SB 1 and SB 2 ). A plurality of memory cells M ij of MOSFETs are connected in parallel between respective two sub-bit lines. The gates of the memory cells M ij in each column are connected to word lines WL j . The main bit lines MB 1 , MB 2 , ···, etc. are connected to sense amplifiers such as SA 1 , or to GND via transistors such as Q 2 . To the ends of the odd-numbered sub-bit lines SB 2m-1 (m is a integer, 1 or larger) on the side of the memory cells M i1 (i.e., on the upper side in Figure 1 ), bank selecting MOSFETs BSO 1 , BSO 2 , ···, etc. are respectively connected. Two adjacent MOSFETs (e.g., BSO 1 and BSO 2 ) are also connected to an odd-numbered main bit line (e.g., MB 1 ) which is provided therebetween. The gates of the bank selecting MOSFETs BSO 1 , BSO 2 , ···, etc. which are connected to these odd-numbered sub-bit lines are alternately connected to two bank select lines BO 1 and BO 2 . To the ends of the even-numbered sub-bit lines SB 2m (m is a integer, 1 or larger) on the side of the memory cells M in (i.e., on the lower side in Figure 1 ), bank selecting MOSFETs BSE 1 , BSE 2 , ···, etc. are respectively connected. Two adjacent MOSFETs (e.g., BSE 1 and BSE 2 ) are also connected to an even-numbered main bit line (e.g., MB 2 ) which is provided therebetween. The gates of the bank selecting MOSFETs BSE 1 , BSE 2 , ···, etc. which are connected to these even-numbered sub-bit lines are alternately connected to two bank select lines BE 1 and BE 2 . In the ROM of the above-mentioned configuration, the case where information is read out from a memory cell M 41 is considered. In this case, the bank select lines BO 1 and BE 2 are set to High, the other bank select lines BO 2 and BE 1 are set to Low, and the word line WL 1 is set to High. The control signal VG for the transistor Q 2 connected to the main bit line MB 2 is set to High, so that the main bit line MB 2 is grounded. The circuit in this state is shown in Figure 3 . The discharge current i flows through the main bit line MB 3 , the bank selecting MOSFET BSO 3 , the sub-bit line SB 5 , the memory cell M 41 , the sub-bit line SB 4 , and the main bit line MB 2 , in this order. The total value of diffusion resistance on the sub-bit lines SB 5 and SB 4 in the path is r + (n - 1)r = nr, if the value of resistance between respective two cells is indicated by r. Now, the case where information is read out from the memory cell M 4n is considered. The circuit in this case is shown in Figure 4 . The total value of diffusion resistance on the sub-bit lines SB 5 and SB 4 in the path is(n - 1)r + r = nr. As described above, irrespective of the position of the memory cell from which information is to be read out, the diffusion resistance on sub-bit lines is always constant, so that the value of the discharge current is constant even when the position of the memory cell differs. Moreover, since the value of the diffusion resistance is half as compared with the maximum value of the diffusion resistance in the prior art, the value of the discharge current is larger. In the above embodiment, though a mask ROM has been described as an example, the invention is applicable to any type of semiconductor read only memory such as an EPROM or an E 2 PROM in which a plurality of memory cells are disposed in a matrix array. As described above, according to the invention, irrespective of the position of the memory cell from which information is to be read out, the resistance against the read-out current is constant. Therefore, especially when diffusion bit lines are used, in the prior art, since the resistance varies from position to position of memory cells from which information is to be read out, the value of read-out current must be set on the basis of the minimum resistance. On the contrary, according to the invention, a larger read-out current can be used. As a result, the read operation is performed at a higher speed, and a wide operation margin can be ensured, thereby guaranteeing a stable read operation. It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art within the scope of the claims. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein.

Claims: A semiconductor read only memory comprising: a plurality of first bit lines (SB 1 , SB 2 ...) disposed in parallel; a plurality of groups (M j.1 ... M j.n ) of memory cells, in each group, memory cells being connected in parallel between two adjacent ones of said first bit lines; second bit lines (MB 1 , MB 2 ...) disposed in parallel to said first bit lines, the proportion of said second bit lines to said first bit lines being 1 to 2; a group of first bank selecting switches (BSO 1 , BSO 2 ...) each of which is connected between one end of an odd-numbered one (SB 1 , SB 3 ...) of said first bit lines and one end of an odd-numbered one (MB 1 , MB 3 ...) of said second bit lines; and a group of second bank selecting switches (BSE 1 , BSE 2 ...) each of which is connected between one end of an even-numbered one of said first bit lines which is adjacent to a said odd-numbered one of said first bit lines and one end of an even-numbered one of said second bit lines. A semiconductor read only memory according to claim 1, wherein said groups of first and second bank selecting switches are constructed using a plurality of pairs of two adjacent selecting switches (BSO 1 , BSO 2 ), said adjacent two selecting switches being connected to the same one of said second bit lines (MB 1 ). A semiconductor read only memory according to claim 1, wherein said memory cells and said selecting switches are MOSFETs. A semiconductor read only memory according to claim 1, wherein said first bit lines (SB 1 , SB 2 ...) are made by diffusion layers, and said second bit lines are metal lines.

Inventors: HOTTA YASUHIRO, HOTTA, YASUHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: G11C17
IPC codes: G11C17