Liquid crystal device and driving method therefor

Abstract: A liquid crystal device of active matrix type including a layer of a liquid crystal material and a plurality of unit cells each provided with an active element, comprises: a circuit for maintaining signal lines, for supplying signals for determining the optical state of the liquid crystal material, at a reference potential during a period, other than a period in which the signals are supplied to the unit cells.

Description: The present invention relates to a method of driving an active matrix type liquid crystal device which may be adapted for use in a flat panel display or in an image information processing apparatus such as a projection television or a video recorder. It also concerns a flat panel display or image information processing apparatus adapted to perform the method aforesaid. Related Background Art Liquid crystal devices, particularly so-called active matrix liquid crystal display devices employing active elements as the pixel switches, have been widely utilised, principally employing twisted nematic (TN) liquid crystal, and commercialised in the fields of flat panel displays and projection televisions. The above-mentioned active matrix element, represented by a thin film transistor (TFT), a thin film diode and an MIM (metal-insulator-metal) element is used for assisting the optical switching response of liquid crystal by maintaining a voltage application state for a period longer than the actual line selecting period for the TN liquid crystal of a relatively slow response, and realising a practical memory state for a frame period, by the above-mentioned voltage application state, in liquid crystal lacking the memory property (self-holding property) such as the TN liquid crystal mentioned above. Also the configuration utilizing such active matrix elements is in principle free from crosstalk among the lines or the pixels, thus providing satisfactory display characteristics. In recent years there has been developed ferroelectric liquid crystal (FLC) with a response speed which is several orders higher than that of the TN liquid crystal, and the developments of a display panel, a light valve etc. utilizing such FLC have been announced. There is conceived possibility of obtaining a further improved display device by driving the FLC with the above-mentioned active matrix elements, and the combination of FLC and the above-mentioned TFT is already disclosed for example in the U.S. Patent No. 4,840,462 and in the Proceedings of the SID, vol. 30, 1989 "Ferroelectric Liquid-Crystal Video Display". Fig. 1 is a circuit diagram of such conventional active matrix liquid crystal device. The driving unit of said device is composed of pixels parts each consisting of a liquid crystal cell 701, containing liquid crystal sealed between a common electrode (with a potential V COM ) and an individual pixel electrode, and pixel TFT's 702; an image signal line parts (hereinafter called signal lines 703); a line buffer 704; a shift pulse switch 708; a horizontal shift register 705; gate signal lines (hereinafter called gate lines) 711; and a vertical shift register 706, and the recording signals are transferred from an input terminal 707 to the successive pixels or successive lines in successive timings. Fig. 2 is a timing chart showing the driving pulses for said conventional active matrix liquid crystal device, in a line-sequential drive. The image signal S VI to be recorded on the liquid crystal is stored, by an amount corresponding to a line, in the buffer 704, through the shift pulse switch 708 which is controlled by the output signal, of a frequency synchronized with said image signal, from the horizontal shift register 705. After the storage of the image signal of all the pixels of an n-th line is stored in the line buffer 704, the pixel image signals V PEN are recorded in the liquid crystal cells 701 of said line, through an output switch 710, turned on by a signal ø T , of the line buffer 704 and pixel switches 702 turned on by signals S2 from the vertical shift register 706. The signal transfer to the liquid crystal cells is conducted collectively for a line, generally during a blanking period in a horizontal scanning period. According to the above-explained timings, the pixel image signals V PEN , V PEN+1 ,... are recorded in the successive lines. The signal voltage thus transferred causes the movement of liquid crystal molecules constituting each cell, thereby causing a change in the transmittance of the liquid crystal cell, depending on the directions of polarizing plates so positioned as to constitute a cross polarizer, as shown in Fig. 3. The signal voltage V SIG shown on the abscissa in Fig. 3 is known to have different meanings according to the liquid crystal to be employed. For example, in case of TN liquid crystal, this value is defined as the effective voltage V rms . Fig. 4A provides qualitative explanation on this value. The polarity of the signal voltage is alternated in every frame, in order to avoid the prolonged application of a DC signal to the liquid crystal, but the liquid crystal itself responds to the AC voltage component, represented by hatched areas. Consequently, the effective voltage V rms is represented by the following equation (1): wherein t F is the time of two frames and V LC (t) is the signal voltage transferred to the liquid crystal. On the other hand, the above-mentioned FLC is generally driven with a DC voltage. In case of bistable FLC (for example chiral smectic liquid crystal, preferably of a chiral smectic phase C (SmC*) or phase H (SmH*), or of SmI*, SmF* or SmG*), there is employed a driving wave form as shown in Fig. 4B. More specifically, the signal voltage V LC (t) at first resets the liquid crystal to one of the bistable states by V R , and then applies a writing voltage signal V W . The signal voltage V SIG contributing to the transmittance shown in Fig. 3 is again represented by hatched areas. Different from the case of TN liquid crystal, the DC component of the writing voltage constitutes directly the signal voltage V SIG . However, in such conventional configuration, the signal voltage accumulated in the liquid crystal cell, through the signal transfer in the aforementioned timings, is known to fluctuate principally for the following two reasons. The first reason lies in the swing of the liquid crystal voltage, resulting from a voltage variation in the gate line 711 for driving each pixel switch. The swing ΔV LC1 in the liquid crystal voltage can be represented by the following equation (2): ΔV LC1 = C GD C GD + C LC · ΔV G wherein C LC is the capacitance of the liquid crystal cell, C GD is the gate-drain capacitance of the pixel TFT 702, and Δ VG is the voltage variation of the gate line 711 (amplitude of gate voltage required for on-off operation of the pixel TFT). The second reason lies in the swing of the liquid crystal voltage, caused by a voltage variation in the signal line 703 for transferring the image signal V LC (t) to the liquid crystal cells. Said swing ΔV LC2 in the liquid crystal voltage can be represented by the following equation (3): ΔV LC2 = C DS C DS + C LC · ΔV S wherein C LC is the capacitance of the liquid crystal cell, C DS is the parasite capacitance between each pixel electrode and the signal line, and ΔV S is the voltage variation in the signal line 703 (namely the image signal voltage for each line or each pixel). Fig. 5 shows the first-mentioned swing ΔV LC1 of the liquid crystal voltage resulting from the voltage variation in the gate line 711, while Figs. 6 and 7 show the second-mentioned swing ΔV LC2 of the liquid crystal voltage resulting from the voltage variation in the signal line. As will be apparent from Fig. 5, the voltage swing ΔV LC1 caused by the first reason always varies the voltage applied to the liquid crystal cell to the negative side. Consequently, said voltage change ΔV LC1 generates a state equivalent to the continuous application of a DC voltage component, and said DC voltage component leads to the coagulation of liquid crystal molecules particularly when the TN liquid crystal is employed. Also in the foregoing equation (2), if the capacitance C GD fluctuates for example by the instability in the process, the voltage swing ΔV LC1 itself also fluctuates. In case of display with gradation by a liquid crystal display device, the gradation characteristics are lost if said fluctuation exceeds the voltage range required for the display of one level (ca. 47 mV for a level for displaying 64 levels within an amplitude of 3 V). Certain proposals have been made for coping with said voltage variation ΔV CL1 , particularly for removing the DC voltage component. A widely employed method consists, in case of using the TN liquid crystal, of providing an auxiliary capacitance parallel to the capacitance of the liquid crystal, thereby increasing the apparent cell capacitance to increase the denominator in the equation (2), thus reducing the swing. Another proposal consists of providing each pixel with plural TFT's and specially designing the arrangement thereof, thereby rendering the swing less conspicuous. Also for reducing the fluctuation in the swing, there has been tried to suppress the fluctuation in the parasite capacitance among the elements, by varying the structure of the pixel TFT from the conventional inverse staggered TFT of amorphous silicon to a planar TFT employing polysilicon, and introducing the ion implantation, utilized in the IC process, into the formation of source and drain of the TFT. On the other hand, based on the voltage variation ΔV CL2 of the second reason, when a signal voltage is supplied to a pixel and a charge is accumulated in the liquid crystal cell, the signal charge of said pixel varies according to the equation (3) if a signal is transferred to another pixel through the same signal line. In the above-explained circuit configuration, the signal line 703 for signal transfer has a certain parasite capacitance C S which in practice is several hundred times to several thousand times larger than the liquid crystal capacitance of the pixel. In the transfer of a signal voltage from the buffer to the liquid crystal cell in such system, the signal voltage accumulated in said parasite capacitance is scarcely attenuated, and the voltage of the signal line can be considered to be always fixed at the signal voltage then transferred. When a new signal voltage is subsequently supplied for transfer to another pixel, the voltage of the signal line varies for the same reason. The drawbacks induced by such voltage variation will be considered more detailedly in the following. For the purpose of simplicity, it is assumed that, in the entire image frame, a certain horizontal line only displays black (absolute signal level being minimum) while other lines display white (absolute signal level being maximum). In such situation, the signal level of the black-displaying line swings according to the equation (3), at the signal transfers to other lines, and such situation is illustrated in Figs. 6 and 7. Fig. 6 shows the drawback inducted by the voltage variation ΔV LC2 of the second reason, in case of FLC, and Fig. 7 shows the drawback in case of TN liquid crystal. Fig. 7 shows a case in which an n-th line in the input image signal V IN displays black while other lines display white. As will be apparent from Fig. 7, the image signal V LCn of the n-th line is subjected to a variation of the signal level by ΔV CL2 according to the foregoing equation (3), whereby the effective voltage V rms represented by the equation (1) varies, thus becoming unable to maintain the black level. More specifically, the equation (1) is changed to the following equation (4), whereby the effective voltage V rms varies: Fig. 6 shows that, in case of FLC, the voltage V LCn written in a pixel in the n-th line varies by the subsequent write-in of the pixel image signals by gate signals S2 n+1 , S2 n+2 , S2 n+3 ,... of another line. Consequently the display level of said line gradually varies to another level by the voltage variation ΔV LC2 according to the equation (3), thus becoming unable to maintain the original display level. This phenomenon can be numerically analyzed in the following manner. As an example, there are employed a signal line 703 of Al (aluminum) with a width of 3 µm and a thickness of 0.5 µm; a pixel electrode of a size of 30 x 30 µm or 150 x 150 µm; a liquid crystal cell gap of 6 µm; a dielectric constant of liquid crystal of 5.0; an interlayer insulation film between the signal line and the gate line with a dielectric constant of 3.9 and a thickness of 0.5 µm; a distance between the signal line and the pixel electrode of 3 µm; and a driving voltage of ±5.0 V at maximum for the liquid crystal. In such system, by calculating the parasite capacitance V DS and the liquid crystal cell capacitance C LC and substituting these values into the equation (3), there is obtained a variation in the pixel voltage as represented by the following equation (5), for a pixel size of 150 x 150 µm: ΔV LC2 = C DS x V S C DS + C LC = 1.37E-14 x 10 1.37E-14 + 1.66E-13 = 0.76[V] In case of effective voltage drive as in the TN liquid crystal, the effective voltage V rms varies according to the foregoing equation (4), and, in the case of DC voltage drive as in the FLC, said voltage variation is directly reflected in the variation of the signal voltage for the liquid crystal. Such voltage variation is more complex in case the signal level varies linearly as in the ordinary television image signal. In any case, the signal level of a pixel varies at the signal transfer to another pixel, if the level of said signal is different from that of the first-mentioned pixel. As said variation occurs in a direction to approach the signal level of said another pixel, the image appears to blot between the pixels or between the lines, and the image boundary becomes less clear. Such blotting appears as vertically streaking smears on the image, thus significantly deteriorating the image quality. Also for a pixel size of 30 x 30 pm, there is obtained the result shown by the equation (6) in the above-mentioned black-and-white display. It will thus be understood that the voltage variation ΔV LC2 of the second reason becomes unnegligibly large, as the pixel size becomes smaller and the resolving power of the display device becomes higher: ΔV LC2 = C DS x V S C DS + C LC = 2.75E-15 x 5 2.75E-15 + 6.64E-15 = 1.47[V] This is because the decrease in the parasite capacitance C DS between the signal line and each pixel electrode at the reduction of pixel size is less than that in the liquid crystal capacitance C LC , so that the influence of C DS becomes more conspicuous by the reduction in the liquid crystal capacitance C LC . In order to cancel the voltage variation ΔV LC2 of the second reason, there is conceived to reduce C DS to zero, but this is absolutely impossible as long as the above-explained circuit configuration is adopted, regardless how finely it is made. Nextly conceivable is the reduction of the voltage variation in the signal line, and, for this purpose, there is required to reduce the proportion of the parasite capacitance of the signal line with respect to the entire capacitance. However, the parasite capacitance of the signal line, though being reducible to a certain extent by the reduction of the width of the line, will still be far larger (still several hundred times to several thousand times) than the capacitances C DS , C LC ) at the liquid crystal side. Also the capacitance C DS cannot be made larger, as it is mostly determined by the structure and size of the pixel part. Consequently, there is nextly conceived as the increase of the liquid crystal capacitance C LC . For this purpose it is conceivable to form, as in the current TN liquid crystal cell configuration, to form a large auxiliary capacitance, parallel to the liquid crystal capacitance C LC . However, in order to cancel the influence of the capacitance C S of several hundred times to several thousand times, it is required to attach an auxiliary capacitance of a similar or larger magnitude, and the addition of such large auxiliary capacitance increases the load of signal transfer to the pixel parts. Such capacitance cannot be increased excessively since the increase in the number of pixels reduces the time allotted to each line. In summary, the drawbacks associated with the voltage variation ΔV LC2 of the second reason will become more conspicuous in the display devices requiring high definition and high-speed drive, such as the display for the high definition television which is expected to become rapidly popular in the future. On the other hand, the status of the display device employing liquid crystal with memory property is as follows. In such case, the optical axis of liquid crystal and that of the polarizing plates are so aligned that one of two optical bistable states provides white display while the other provides black display. A voltage providing the white display is called an optical information recording signal, while a voltage providing the black display is called a reset signal. In case of driving the FLC with bistable states, each pixel has to be given, prior to the access to the recording signal, a black (reset) signal in order to reset the record at the preceding access. In practice, however, the parasite capacitance C S is several hundred times to several thousand times larger than the liquid crystal capacitance in the pixel part, and is about equal to or even larger than the capacitance in the buffer. Thus the signal voltage (optical information recording signal or reset signal) entered from the input terminal 707 is transferred while charging and discharging the capacitance of the buffer and the parasite capacitance of the line, whereby the signal transferring ability of the device is deteriorated, also under influence of the resistance in the lines. Besides, these phenomena become more conspicuous as the display becomes larger in size and higher in definition. Furthermore, the conventional driving method has been associated with the following drawbacks. In the driving method shown in Fig. 7, the voltage of the pixel electrode, though variable depending on the signal voltage, is always positive with respect to the potential of the common electrode, and such situation is equivalent to the continuous application of a DC voltage component to the liquid crystal cell. Such DC component leads to the coagulation of the liquid crystal molecules, particularly in case of the TN liquid crystal. Certain proposals have been made for eliminating said DC voltage component. Already employed widely is the frame inversion driving method shown in Fig. 4A. In this driving method, the polarity of the signal voltage with respect to the common electrode potential V COM is inverted every frame in such a manner that an N-th signal voltage is applied positively with respect to the potential of the common electrode while an (N+1)-th signal voltage is applied negatively, whereby the DC voltage component applied to the liquid crystal cell is cancelled and the coagulation of the liquid crystal molecules is prevented. There have also been proposed driving methods with inversion in every horizontal scanning period or in every pixel, for attaining similar effects. However, such methods are still associated with the following drawbacks. With a signal voltage V N applied to the pixel electrode at the N-th time and a signal voltage -V N+1 applied at the (N+1)-th time, a bias (V N + V N+1 ) is applied between the source and the drain of the pixel TFT 102 at the signal application of the (N+1)-th time. Thus, in the above-explained inversion driving method with a maximum amplitude V MAX of the signal voltage, there is applied a bias of 2V MAX at maximum between the source and the drain of the pixel TFT 102, which is therefore required to have an on-state source-drain voltage resistance exceeding said maximum bias. Such requirement can be alleviated by a reduction in the maximum amplitude of the signal voltage, but such method is undesirable because it tends to sacrifice the display of gradation as will be understood from Fig. 3, whereas the display devices require an improved definition in the future, as in those for the high definition television which is expected to become rapidly popular. Another method for alleviating said voltage resistance requirement lies in the use of a MOS transistor of a high voltage resistance structure, such as the LDD (lightly doped drain) structure, as the pixel switch 102. However, the MOS transistor of currently proposed structure for high voltage resistance is associated with a drawback of a loss in gm because of an increased serial resistance to the source and the drain, as a trade-off for the improvement in the voltage resistance. As explained above, high-speed drive will be increasingly required for the liquid crystal devices, as in those for high-definition television, and a larger gm will be required for this purpose in the pixel switching TFT. Besides, the MOS transistor of the above-mentioned high voltage resistance structure is inevitably associated with a high manufacturing cost, because of the complex manufacturing process. Such drawbacks are not limited to the case of TN liquid crystal, but also are present in case of driving FLC by active matrix elements, utilising a signal as shown in Fig. 4B. SUMMARY OF THE INVENTION The aforesaid problems have now been addressed, particularly that of eliminating smearing streaks, and it is intended to provide a method that is compatible with high definition and high speed drive. The method of driving to be described hereinafter is applied to an active matrix type liquid crystal device as described in the preamble of claim 1 appended. The particular feature of this method is that in each frame a reset voltage is applied across the unit cells of a respective row, immediately prior to application of respective signal voltages thereacross, each for a time interval at least long enough for charging the parasitic capacitances of the respective signal line and the respective unit cell of the respective row, while the respective active element is closed, and repeatedly row by row, the reset voltage having a value that is between the maximum positive value of the signal voltages and the inverted value thereof. It is acknowledged that it is known to reset the voltages of the unit cells of an active matrix type liquid crystal device prior to setting display states. EP-A-0284134 describes a method of driving a ferroelectric liquid crystal display device in which the unit cells are reset to an extreme transmission state, completely transmissive or non-transmissive, before being set to a voltage corresponding to that of an intermediate grey scale condition. Each unit cell is thus reset at a maximum signal voltage which is applied for a time interval that is long enough for bringing the cell to its extreme state. As a result, each grey scale condition is exclusively determined by signal voltage. It is also acknowledged that US-A-5105288 discloses a method of driving in which a reset voltage is applied to the signal lines in order to maintain the optical state of the liquid crystal in signal lines non-transmissible. The reset voltage is necessarily equal to, or higher than, the signal voltages and does not, as in the present invention, have a value that is between the maximum positive value and the inverted value of the signal voltages. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a conventional active matrix liquid crystal display device; Fig. 2 is a timing chart showing the driving method for the device shown in Fig. 1; Fig. 3 is a chart showing the relationship between the transmittance and the signal voltage in a liquid crystal display device; Figs. 4A and 4B are timing charts showing an example of the conventional driving signal; Figs. 5 and 6 are timing charts for explaining the variation in the voltage applied to the pixels in conventional liquid crystal display devices; Fig. 7 is a timing chart showing another example of the conventional driving signal; Fig. 8 is a circuit diagram of a liquid crystal display device constituting embodiments 1 to 3 of the present invention; Fig. 9 is a timing chart for explaining the driving method for the liquid crystal display device of the embodiment 1; Fig. 10 is a timing chart for explaining the driving method for the liquid crystal display device of the embodiment 2; Fig. 11 is a timing chart for explaining the driving method for the liquid crystal display device of the embodiment 3; Fig. 12 is a circuit diagram of a liquid crystal display device constituting embodiments 4 and 5 of the present invention; Fig. 13 is a timing chart for explaining the driving method for the liquid crystal display device of the embodiment 4; Fig. 14 is a timing chart for explaining the driving method for the liquid crystal display device of the embodiment 5; Fig. 15 is a circuit diagram of a liquid crystal display device constituting an embodiment 6 of the present invention; Fig. 16 is a timing chart for explaining the driving method for the liquid crystal display device of the embodiment 6; Fig. 17 is a schematic view of a liquid crystal device of the present invention; and Fig. 18 schematically shows a liquid crystal element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The liquid crystal material employed in the present invention may have a stable state, or at least two stable states. The former is represented by nematic liquid crystals, such as twisted nematic liquid crystal or super twisted nematic liquid crystal. The latter is represented by ferroelectric liquid crystals, preferable chiral smectic liquid crystals. Specific examples of such liquid crystal includes those of chiral smectic phase C (SmC*), SmH*, SmI*, SmF* and SmG*. Also the means for supplying the resetting voltage, for maintaining the unit cells or the signal lines at a resetting voltage can be a bus line (power supply line) for supplying said voltage from an external power source, or a resetting voltage source provided in an integrated semiconductor circuit for generating the resetting voltage by dropping a voltage supplied from an external power source and a line connected thereto. [Embodiment 1] Fig. 8 shows a driving circuit for the active matrix liquid crystal device constituting an embodiment 1 of the present invention, wherein shown are a liquid crystal cell 101 represented by a capacitance associated therewith; a pixel TFT 102 for applying a signal voltage to said liquid crystal cell 101; a recording signal line 103; a transfer gate 104; a buffer capacitance 105; a switching TFT 106 for accumulating an external signal pulse in a corresponding buffer capacitance; a horizontal shift register 107 for pulse driving the switching TFT's 106; a vertical shift register 108 for driving the pixel TFT's 102; a gate signal line 110 for driving the pixel TFT's 102 by the output signals of the vertical shift register 108; a resetting line 109 connected to an unrepresented resetting voltage source; and a switching TFT 110 for selectively connecting the recording signal lines 103 with the resetting line 109. In the following there will be explained, with reference to Fig. 9, the functions of the active matrix liquid crystal device employing the above-explained driving circuit and a TN liquid crystal, in line-sequential drive with signal inversion in every frame. When image signals of a line are entered in succession from the input terminal 112, they are respectively transferred to the buffer capacitances 105 through the switching TFT's 106 which are turned on by the horizontal shift register 107 driven by the pulses synchronized with the frequency of said image signals. Within so-called blanking period t B which is after the transfer of the last bit of the line to the buffer capacitance 105 (t 1 in Fig. 9) but before the entry of the image signals of a next line to the input terminal 112 and during which the switching TFT's 116 are turned off, the switching TFT's 110 and the pixel TFT's 102 are simultaneously turned on (t 2 ) while the transfer gates 104 are turned off, thereby resetting the pixel electrodes from the signal voltages to the pixel resetting voltage V RES . Said resetting voltage V RES is usually selected between the maximum value V MAX of the signal voltage and the inverted value -V MAX thereof, commonly at the middle thereof. Said pixel resetting operation is executed in a part of the blanking period. The resetting period, in which the switching TFT's 110 are turned on (t R = t 3 - t 2 ), should be at least enough for charging the parasite capacitance C S of the signal line 103 and the pixel capacitance 101 of the pixel to be reset. In the remaining part of the blanking period, after the switching TFT's 110 are turned off, the transfer gates 104 are turned on (t 4 ) thereby transferring the signals from the buffer capacitances to the respective pixels, and the pixel TFT's 102 and the transfer gates 104 are turned off before the end of the blanking period (t 5 ). As a result, each pixel electrode is reset once during the change from the signal voltage of the present to the inverted signal voltage in the next frame, so that the on-state source-drain bias applied to the pixel TFT 102 does not exceed V MAX . The above-explained timings are shown in Fig. 9, wherein shown are the image signals S VI of the N-th and (N+1)-th lines; gate input signals ø RES , ø V1 - ø Vn respectively of the switching TFT's 110 and the pixel TFT's 102; the input signal ø T of the transfer gates 104; and the signal voltages of the pixels of the N-th line (solid line) and the (N+1)-th line (broken line). As will be apparent from the charts, the pixel electrode is maintained at the resetting voltage V RES in the course of change from the signal voltage to the next inverted signal voltage, whereby the on-state source-drain bias applied to the pixel TFT is alleviated. In the following there is considered the variation in the signal voltage under the above-explained situation. The period t R , in which the pixel voltage is maintained at the set level, is in the order of microseconds less than the blanking period, and the liquid crystal molecules do not respond to such voltage variation within such short period. In this state, with the resetting potential V RES , the effective voltage V rms actually applied to the liquid crystal can be represented as follows, based on the foregoing equation (1): Consequently the curve representing the relationship between the transmittance (T) and the effective voltage (V rms ) is displaced by the contribution of the resetting voltage V RES , but the image is not influenced if t R is sufficiently negligible with respect to a frame period. For example, in the high definition television image signal, a frame period is about 33 msec, and a blanking period therein is about 3 µsec. In said blanking period, the period required for pixel resetting is about 1 µsec. Consequently the pixel electrodes are maintained at the resetting potential V RES for 2/33000 of a frame period, but is maintained at the signal voltage V LC for 32998/33000 of the frame period, so that the influence to the image is extremely small. Also as explained above, the curve representing the relationship between the transmittance T and the effective voltage V rms is displaced by the contribution of V RES , but the effective voltage V rms is uniquely determined by a given value of V LC , as long as the resetting voltage V RES and the resetting time t R are constant. Consequently the characteristics of the display device may be determined, based on thus displaced curve. It is also possible to cancel said displacement by the regulation of the original signal voltage V LC . Since the bias voltage applied to the pixel TFT's is reduced as explained above, the vertically streaking smear, resulting from the swing of the signal voltage of each pixel, under the influence of signals in other pixels connected to a same signal line, is eliminated and the image quality is therefore improved. [Embodiment 2] Fig. 10 is a timing chart of an embodiment 2, utilizing also the circuit shown in Fig. 8. In this embodiment 2, after the switching TFT's 106 are turned off (t 1 ) upon completion of the image signals to the buffer capacitance 105, the switching TFT's 110 and the pixel TFT's 102 are simultaneously turned on (t 2 ) while the transfer gates 104 are turned off, thereby resetting the pixel electrodes from the signal voltages to the pixel resetting voltage. Then the switching TFT's 110 are turned off (t 3 ) while the pixel TFT's 102 are turned on, and the transfer gates 104 are turned on (t 4 ) to transfer the signals from the buffer capacitances 105 to the respective pixels 101. The above-explained operations are same as those in the embodiment 1. However, when the pixel TFT's 102 are turned off (t 5 ) after the signal transfer to the pixels 101, the transfer gates 104 are not turned off simultaneously but maintained in on-state, and the switching TFT's 110 are again turned on (t 5 ), thereby resetting the buffer capacitances 105 also to the reset voltage V RES . In the foregoing embodiment 1, signals inverted every frame are supplied from the input terminal 112 to the buffer capacitances 105 through the switching TFT's 106, and, in such signal supply, an on-state source-drain bias voltage of 2V MAX at maximum is applied to said switching TFT's in a similar manner as in the pixel TFT's 102 in the conventional configuration. However, with the timings shown in Fig. 10, the potential of the buffer capacitances 105 is reset in the course of change from the signal voltages to the next inverted signal voltages, so that the on-state source-drain voltage resistance can be reduced not only in the pixel TFT's 102 but also in the switching TFT's 110. The on-state of the switching TFT's 110 required for the resetting of the buffer capacitances 105 should be at least enough for charging the parasite capacitances of the signal lines 103 and the buffer capacitances 105. The switching TFT's 110 and the transfer gates 104 are turned off before the end of the blanking period. As a result the on-state source-drain bias applied to the pixel TFT's 106 is also alleviated. In Fig. 10 there are shown the image signals S VI of the N-th and (N+1)-th lines; the gate input signals ø RES , ø Vl - ø Vn respectively of the switching TFT's 106 and the pixel TFT's 102; the transfer gate input signal ø T ; and the signal voltages of the pixels in the N-th line (solid line) and in the (N+1)-th line (broken line). As will be apparent from these charts, the pixel electrode is maintained once at the resetting voltage in the course of change from the signal voltage to the next inverted signal voltage, whereby the on-state source-drain bias is alleviated not only the pixel TFT's 102 but also in the switching TFT's 110. [Embodiment 3] Fig. 11 is a timing chart of an embodiment 3 also utilizing the circuit shown in Fig. 8. In this embodiment, in the blanking period t B after the switching TFT's 106 are turned off (t 1 ) upon completion of transfer of the image signals of a line to the buffer capacitances 105, the pixel TFT's 102 are turned on (t 2 ) while the transfer gates are maintained turned off. The switching TFT's 110 are already turned on from the horizontal scanning period, thereby resetting the pixel electrodes from the signal voltages to the resetting voltage V RES . Said resetting voltage V RES is selected between the maximum value V MAX of the signal voltage and the inverted voltage -V MAX thereof, normally at the middle thereof. Said pixel resetting operation is executed in a part of the blanking period. The on-state period of the switching TFT's 110 should be at least enough for charging the parasite capacitances C S of the signal lines 103 and the pixel capacitances 101 to be reset. In the remaining part of the blanking period after the switching TFT's 110 are turned off (t 3 ), the transfer gates 104 are turned on while the pixel TFT's 102 are maintained turned on (t 4 ), thereby transferring the signals from the buffer capacitances 105 to the respective pixels 101. After said signal transfer, the pixel TFT's 102 are turned off (t 5 ) while the transfer gates 104 are maintained in the on-state, and the switching TFT's 110 are again turned on (t 6 ) thereby resetting the buffer capacitances 105 also to the resetting potential. Then the transfer gates 104 are turned off (t 7 ) before the end of the blanking period. The switching TFT's 110 are still maintained in the on-state during a horizontal scanning period, in order to maintain the signal lines 103 at a constant voltage. In Fig. 11, there are shown the image signals S VI of the N-th and (N+1)-th lines; the gate input signals ø RES , ø Vl - ø Vn respectively of the switching TFT's 110 and the pixel TFT's 102; the input signal ø T of the transfer gates; and the signal voltages of the pixels of the N-th line (solid line) and the (N+1)-th line (broken line). As will be apparent from these charts, the pixel electrodes are maintained once at the resetting voltage in the course of change from the signal voltages to the next inverted signal voltages, so that the on-state source-drain bias is alleviated not only in the pixel TFT's 102 but also in the switching TFT's 106. Thus the present embodiment not only reduces the requirements for the voltage resistance of TFT's but also suppresses the aforementioned variation in the signal voltage. More specifically, the signal voltage in each pixel is no longer influenced by those in other pixels connected to the same signal line, whereby the vertically streaking smear can be eliminated and the image quality is therefore improved. [Embodiment 4] Fig. 12 is a circuit diagram of a driving circuit for the active matrix liquid crystal device constituting an embodiment 4 of the present invention. The circuit shown in Fig. 12 is obtained by adding, to the circuit shown in Fig. 8, a second resetting circuit for resetting the buffer capacitances 105. Said second resetting circuit is similar to the aforementioned resetting circuit for resetting the pixel potential, and is composed of a resetting line 512 connected to a buffer capacitance resetting power source, and switching TFT's 513 for connecting said resetting line 512 selectively with the recording signal lines 103. In the following there will be explained, with reference to Fig. 13, the functions of an active matrix liquid crystal device employing TN liquid crystal, in a line-sequential drive with inversion of polarity in every frame. When the image signals of a line are entered in succession from the input terminal 112, said signals are transferred to the buffer capacitances 105 by the switching TFT's 106 turned on by the horizontal shift register 107 which is driven by the pulses synchronized with the frequency of said signals. In the so-called blanking period t B which is after the transfer of the signal of the last bit of said line into the buffer capacitance (t 1 in Fig. 13) but prior to the entry of the image signals of a next line into the input terminal 112, the pixel TFT's 102 are turned on (t 2 ). The switching TFT's 110 are already in the on-state from the preceding horizontal scanning period, whereby the pixel electrodes are reset from the signal voltages to the pixel resetting voltage V RES . Said resetting voltage is selected between the maximum value V MAX of the signal voltage and the inverted value -V MAX thereof, generally at the middle thereof. Said pixel resetting operation is executed in a part of the blanking period. The on-period of the switching TFT 110 should be at least enough for charging the parasite capacitance C S of the signal line 103 and the pixel capacitance 101 of the pixel to be reset. In the remaining part of the blanking period after the switching TFT's 110 are turned off (t 3 ), the transfer gates 104 are turned on (t 4 ) to transfer the signals from the buffer capacitances 105 to the respective pixels. After said signal transfer, the pixel TFT's 102 and the transfer gates 104 are turned off (t 5 , t 7 ). Subsequently the switching TFT's 513 are turned on (t 8 ), thereby resetting the buffer capacitances 105 also. Then, after the TFT's 513 are turned off (t 9 ), the switching TFT's 110 are turned on (t 10 ). In this embodiment, since the resetting of the pixel 101 and the signal line 103 is executed by the switching TFT 110 while the resetting of the accumulating capacitance 105 is executed by the separate TFT 513, so that the loads on these TFT's can be alleviated and the resetting operation can be achieved with a higher speed. Fig. 13 shows the timings of functions of the present embodiment. In Fig. 13 there are shown the image signals S VI of the N-th and (N+1)-th lines; the gate input signals ø RES , ø Vl - ø Vn respectively of the switching TFT 110 and the pixel TFT 102; the input signal ø T of the transfer gate 104; the pixel signals voltages V PE of the N-th line (solid line) and the (N+1)-th line (broken line); and the gate input signal ø CTR of the switching TFT 513. As will be apparent from these charts, the pixel electrode is once maintained at the resetting voltage in the course of change from the signal voltage to the next inverted signal voltage, whereby the on-state source-drain bias is alleviated not only in the pixel TFT 102 but also in the switching TFT 106. [Embodiment 5] Fig. 14 shows the function timings constituting an embodiment 5 utilizing the circuit shown in Fig. 12. Said embodiment 5 on the circuit shown in Fig. 12 corresponds to the functions shown in Fig. 10 on the circuit shown in Fig. 8, but the resetting operation of the buffer capacitances 105 is effected by switching TFT's 513 instead of the switching TFT 110 in case of Fig. 10. In the embodiment shown in Figs. 12 and 14, when the image signals of a line are entered in succession from the input terminal 112, said signals are transferred to the buffer capacitances 105 by the switching TFT's 106 turned on by the horizontal shift register 107 which is drive by pulses synchronized with the frequency of said image signals. In the so-called blanking period t B which is after the transfer of the signal of the last bit of said line into the buffer capacitance (t 1 ) but before the entry of the image signals of a next line into the input terminal 112, the switching TFT's 110 and the pixel TFT's 102 are simultaneously turned on while the transfer gates 104 are maintained in the off-state (t 2 ), whereby the pixel electrodes are reset from the signal voltages to the pixel resetting voltage V RES . Then the switching TFT's 110 are turned off (t 3 ) while the pixel TFT's 102 are maintained in the on-state, and the transfer gates 104 are turned on (t 4 ), thereby transferring the signals from the buffer capacitances 105 to the respective pixels 101. After said signal transfer to the pixels 101, the pixel TFT's 102 are turned off (t 5 ), and the switching TFT's 513 are turned on (t 8 ). Thus the buffer capacitances 105 and the parasite capacitances 113 are reset to the potential of the buffer capacitances, which is equal to the potential of the resetting line 512. Subsequently the transfer gates 104 and the switching TFT's 513 are turned off (t 7 , t 9 ) within the remaining part of the blanking period t B . In the present embodiment, as in the embodiment 4, the loads on the TFT's for resetting the pixel capacitance 101 and the buffer capacitance 105 can be alleviated, so that the resetting operation can be achieved with a higher speed. Also the on-state source-drain bias can be reduced in the pixel TFT's 102 and in the switching TFT's 106. [Embodiment 6] In the foregoing embodiments 1 to 5, the active matrix is driven by a line-sequential driving method for every horizontal line, but similar effects can also be attained in a pixel-sequential drive. Fig. 15 shows a driving circuit for the sequential-drive active matrix liquid crystal device of the present embodiment, wherein shown are a capacitance 101 of a liquid crystal cell; a pixel TFT 102 for applying a signal voltage to said liquid crystal cell 101; a signal line 103; a switching TFT 104 for accumulating an external signal pulse in a corresponding liquid crystal cell capacitance; a first horizontal shift register 107 for pulse driving the switching TFT's 104; a vertical shift register 108 for driving the pixel TFT's; a resetting line 109 connected to a pixel resetting source; a switching TFT 110 for selectively connecting the resetting line 109 with the recording signal line 103; and a second horizontal shift register 810 for driving the switching TFT's 110. In the following there will be explained, with reference to Fig. 16, the functions of the circuit shown in Fig. 15. At first the pixel TFT's 102 of a line selected by the vertical shift register 108 are turned on (t 11 in Fig. 16). Then the second shift register 810 in succession turns on the switching TFT's 110 (t 12 ), thereby resetting the pixels 101 to the resetting potential V RES . After said resetting the TFT's 110 are turned off (t 13 ), and the image signals of a line are entered in succession from the input terminal 112 and are transferred, in succession, to all the pixels of a horizontal line through the switching TFT's 104, which are turned on by the first horizontal shift register 107 driven by pulses synchronized with the frequency of said image signals (t 14 - t 15 ). Fig. 16 shows the function timings of the present embodiment. In Fig. 16 there are shown the image signals S VI of the N-th and (N+1)-th lines; the gate input signals ø Vl - ø Vn , ø HRl - ø HRm , ø HTl - ø HTm respectively of the pixel TFT's 102, switching TFT's 110 and transfer gates 104; and the pixel signal voltages V PE of the N-th line (solid line) and the (N+1)-th line (broken line). As will be apparent from these charts, the pixel electrode is once maintained at the resetting voltage in the course of change from the signal voltage to the next inverted signal voltage, whereby the on-state source-drain bias applied to the pixel TFT's 102 is alleviated. The embodiments 1 to 6 explained above can provide an active matrix liquid crystal display device capable of achieving a high definition and a high-speed drive without a large burden on the display device structure, and an active matrix liquid crystal display employing such device. Thus, there can be formed a flat display for direct observation or a projection display, of a high definition. Naturally it is also possible to construct a colour television or a projection colour television, by providing the pixels with different colour filters, or by employing a plurality of the liquid crystal device adopting the driving method of the present invention and illuminating said devices with different coloured lights. Fig. 17 is a block diagram of an information signal processing system including the liquid crystal device of the present invention, wherein provided are a liquid crystal device 1 for displaying an image; a drive control circuit 2 for controlling the drive of said liquid crystal device and releasing the aforementioned resetting signal ø RES , resetting reference voltage V RES , transfer signal ø T , image signal S VI , and clock signal ø CLK for driving the shift registers; an image input circuit 3 for reading image information from an original ORL bearing said image information by means of a photoelectric converting device 7; an information recording circuit 4 for recording the information on a recording medium RCM by means of a recording head 8, which can be an ink jet recording head or a thermal head in case said medium RCM is paper or a plastic sheet, or can be a magnetic head or an optical head in case said medium RCM is a magnetic tape, an optical disk or a magnetic disk; a communication circuit 5 for effecting communication with the outside through a channel NT; and a control circuit 6 for controlling the above-mentioned circuits, and provided with a known central processing unit CPU. Fig. 18 illustrates a liquid crystal device, wherein included are a main frame 10; semiconductor integrated circuits 11 including the vertical shift register 108; semiconductor integrated circuits 12 including the horizontal shift register, buffer circuits and resetting circuits; and a liquid crystal display unit 13 containing a layer of a liquid crystal material between a pair of substrates, one of which bears matrix lines 103, 111, active elements 15, and individual pixel electrodes 14. As explained in the foregoing, the present invention can provide a liquid crystal device capable of effecting high-speed drive and suppressing the smear in inexpensive manner.

Claims: A method of driving an active matrix type liquid crystal device which includes a plurality of unit cells (101) arranged in rows, each unit cell (101) having a respective pixel electrode (14) and a common electrode each side of a common layer of liquid crystal material, a plurality of active elements (102) each connected to the respective pixel electrode (14) of each unit cell (101), respective gate lines (111) connected to the active elements (102) of each respective row, and a plurality of signal lines (103) each connected to a respective active element (102) in each row; wherein in each frame a reset voltage (V RES ) is applied across the unit cells (101) of a respective row, immediately prior to application of respective signal voltages (V PE ) thereacross, each for a time interval (t R ) at least long enough for charging the parasitic capacitances of the respective signal line (103) and the respective unit cell (101) of the respective row, while the respective active element (102) is closed, and repeatedly row by row, the reset voltage (V RES ) having a value that is between the maximum positive value (+V MAX ) of the signal voltages (V PE ) and the inverted value (-V MAX ) thereof. A method according to claim 1 wherein said reset voltage (V RES ) has a value at the middle of the range of said signal voltage (V PE ) from said inverted value (-V MAX ) to said maximum positive value (+V MAX ). A method according to either preceding claim wherein said liquid crystal material is nematic, each unit cell (101) is a twisted nematic cell, said application of respective signal voltages (V PE ) is performed line sequentially, and said signal voltages (V PE ) are inverted for alternate frames. A method according to either preceding claim 1 or 2 wherein said liquid crystal material is nematic, each unit cell (101) is a twisted nematic cell, said application of respective signal voltages (V PE ) is performed pixel sequentially, and said signal voltages (V PE ) are inverted for alternate frames. A method according to claim 3, wherein each signal line (103) is connected to a respective buffer capacitance (105) via a respective transfer gate (104) and said respective buffer capacitances (105) are reset before inversion of the signal voltage (V PE ). A method according to claim 5 wherein said respective buffer capacitances (105) are reset to said reset voltage (V RES ). A method according to any preceding claim wherein said respective signal lines (103) are maintained at said reset voltage (V RES ) at all times other than during the charging of respective signal lines (103) and respective connected unit cells (101) to respective signal voltage (V PE ). A method according to any preceding claim applied to an active matrix type liquid crystal device in which the active elements (102) are thin film transistors. A flat panel display or image information processing apparatus comprising: an active matrix type liquid crystal device (1) which includes a plurality of unit cells (101) arranged in rows, each unit cell (101) having a respective pixel electrode (14) and a common electrode each side of a common layer of liquid crystal material, a plurality of active elements (102) each connected to the respective pixel electrode (14) of each unit cell (101), respective gate lines (111) connected to the active elements (102) of each respective row, and a plurality of signal lines (103) each connected to a respective active element (102) in each row; a driving circuit (2) for supplying a reset voltage (V RES ), signal voltages (S VI ), and timing signals ( RES ,  T ,  CLK ) for controlling the timing of application of said reset voltage (V RES ) and signal voltages (S VI ) to said signal lines (103) and to each unit cell (101); respective transfer means (110 & 104-107; 110, 810 & 104, 107) responsive to respective ones ( RES ,  CLK &  T ;  CLK ) of said timing signals ( RES ,  T ,  CLK ) for transferring said reset voltage (V RES ) and said signal voltages (S VI ) at predetermined timings (t 2 , t 4 ) to said signal lines (103); and active element controlling means (108) responsive to a respective one ( CLK ) of said timing signals ( RES ,  T ,  CLK ) to control the timing of operation of said active elements (102) via said respective gate lines (111); whereby in each frame the reset voltage (V RES ) shall be applied across the unit cells (101) of a respective row, immediately prior to application of respective signal voltages (V PE ) thereacross, each for a time interval (t R ) at least long enough for charging the parasitic capacitances of the respective signal line (103) and the respective unit cell (101) of the respective row, while the respective active element (102) is closed, and repeatedly row by row, the reset voltage (V RES ) having a value that is between the maximum positive value (+V MAX ) of the signal voltages (V PE ) and the inverted value (-V MAX ) thereof.

Inventors: KOHCHI TETSUNOBU, KONDO SHIGEKI, SUGAWA SHIGETOSHI, KOHCHI,TETSUNOBU, KONDO, SHIGEKI, SUGAWA, SHIGETOSHI, Kohchi,Tetsunobu , c/o Canon Kabushiki Kaisha, KONDO, SHIGEKI, C/O CANON KABUSHIKI KAISHA, SUGAWA, SHIGETOSHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: G09G3
IPC codes: G09G3