CVD diamond or diamond-like carbon for chemical-mechanical polish etch stop

Abstract: Metallized semiconductor chips, such as are intended for VLSI, are coated with a first layer of SiO2 followed by a second layer of CVD diamond or DLC as an etch stop. The resulting structure is reproducibly and controllably planarized using a chem-mech slurry and an appropriate polishing pad, enabling subsequent layers to be built up similarly.

Description: The present invention relates to the manufacture of high performance Very Large Scale Integrated (VLSI) semiconductor chips in general and, more particularly, to a method for planarizing topographical features and films on a substrate according to a chemical-mechanical (chem-mech) polishing technique combined with a diamond or diamond-like etch stop material. The above method is used in the fabrication of planarized multilevel metallized semiconductor structures. A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of metal wiring called traces. In VLSI chips, these metal patterns are multilayered and separated by layers of an insulating material. Interlevel contacts between metal wiring patterns are made by through-holes (aka via holes), which are etched through the layers of insulating material. Typical chip designs consist of one or two wiring levels, with three wiring levels being the current state of the art. Circuit cost and performance continue to place demand on the fabrication processes, so that adding supplementary wiring levels can be competitive even though additional processing steps are required. However, the technique using via holes, although widely used today, has multiple limitations and drawbacks in that, as the number of metallization layers increases, wiring and level-to-level alignment become increasingly difficult. In the art of making VLSI semiconductor devices, a silicon wafer is metallized with circuitry traces and pads, typically of aluminum-copper alloy, sputter coated overall with SiO2, resulting in an irregular topography. It is necessary to achieve a smooth topography without damaging the circuitry traces and pads or insulation in order to align devices precisely level-to-level. Etch stops and polishing slurries are known in the art US-A-No. 4 671 851 issued June 9, 1987 to Beyer et al and assigned to the assignee of the present invention, for example, describes the removal of undesired SiO2 protuberances called "bird's heads" using a combination of chem-mech polishing and Si3N4 blanket deposited at 700 degrees C by Low Pressure Chemical Vapor Deposition (LPCVD). Among other descriptive material included therein, the patent is useful for its description of the importance of the selection of polishing pads and the dependency of polishing success on the polishing solution chemistry which is set forth in column 6, lines 16-27. US-A-No. 4 944 836 issued July 31, 1990 to Beyer et al and assigned to the assignee of the present invention describes a new chem-mech polishing slurry to be used with Si3N4 etch stop layer, the water-based alumina slurry formerly used having been found lacing with respect to the etch rate ratio of AlCu to SiO2. EP-A-461498 describes an integrated circuit device as fabricated upon a semiconductor wafer by first forming a stop layer (e.g. CVD nitride or CVD carbon) upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer (e.g. CVD SiO2) is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer. Patent Abstract of Japan, Vol. 10, N° 370 (JP-A-61166041) describes a process wherein N-type epitaxial layer and a thermally oxidized film are sequentially formed on a P-type silicon substrate and a diamond thin film, e.g., is formed as a thin film for polish stopping. Then, the thin film for polish stopping, the thermally oxidized film and the N-type epitaxial layer are sequentially etched and an isolation groove reaching to the P-type silicon substrate is formed. Next a CVD oxide film 100-500nm thick is formed on all the surface of the substrate, a polycrystalline silicon film is formed and the isolation groove is filled. Finally, the polycrystalline silicon film and the CVD oxide film are removed by polishing using less hard abrasives than the thin film for polish stopping and the surface of the thin film for polish stopping is exposed. The CVD oxide film remains at the side wall and the bottom surface of the isolation groove. Not all semiconductor structures are compatible with processing at a high temperature level such as 700 degrees C. For example, in multilevel interconnection levels on wafers with actual circuits, it is necessary to maintain all processing steps at or below about 400 degrees C in order to prevent diffusion of metal into the underlying devices. Silicon nitride deposited at a temperature compatible with the processing of interconnects, i.e. at about 325 degrees C, has proven to be insufficiently hard to function effectively as an etch stop in such "Back End Of the Line (BEOL)" processes. Aluminum oxide, Al2O3, which is harder than SiO2, has proven to polish at a faster rate than SiO2, presumably due to chemical reactions with the polish, making it an ineffective etch stop material. Radio frequency (RF) and direct current (DC) sputtering, and hot filament CVD, electron-assisted CVD, thermal CVD and plasma-enhanced CVD (PECVD) of diamond and amorphous hydrogenated diamond-like carbon (DLC) films has been reported. An article by Sawabe et al in Thin Solid Films Vol. 137, pp. 89-99, reports chemical vapor deposition of a carbon film with interplanar spacings in good agreement with reported values for cubic diamond as measured by reflection high energy electron diffraction (RHEED). The authors also report that the film's hardness, thermal conductivity, and electrical resistivity are almost the same as natural diamond. In Japanese Journal of Applied Physics Vol. 25, part 2, no. 6, pp. 519-521, Hirose et al report a film whose measurements of RHEED, Raman spectra, Vicker's hardness, and specific gravity indicate a diamond film. However, no known art reports that use of a diamond or diamond-like carbon film as a chemical-mechanical polishing etch stop, and no known art reports CVD of such a film at temperatures and having properties compatible with BEOL processing. Hard carbon films are known, but not as an etch stop. Also, compatibility with BEOL processing of such diamond or diamond-like carbon layers is not known in the art. The chemical-mechanical polish works by chemically dissolving and mechanically abrading the SiO2 layer coating over the metallized wafer. The polish is comprised of an alkali silica slurry. It is important that any etch stop polish slower in the alkaline slurry than the SiO2 or than quartz, a crystalline form of SiO2, or any other material that may be coated over the metallized wafer. Diamond, graphite and amorphous carbon are insoluble in water, acid and alkali and are harder than SiO2 and quartz, DLC layers having a hardness of about 3000 to about 9000 Kg/mm2. The etch stop determines the end point of the polishing process. Diamond and DLC, because of their greater hardness in relation to that of SiO2, make end-point detection in the polishing process controllable. The greater hardness of diamond or DLC in relation to that of SiO2, combined with the chemical inertness of the diamond or DLC means that the etch rate ratio of SiO2:diamond or DLC can equal from about 19:1 up to about 311:1. This ratio range is particularly attractive for feature step heights in BEOL processes. DLC adheres well on most surfaces, such as on Si, SiO2, and carbide forming metals. Planarization permits improved control of subsequent lithographic steps to prepare for subsequent levels of metallized circuit traces and pads, and to prevent circuit traces from cracking, which can occur when metal traces are disposed over stepped surface features. It is therefore an object of the invention to provide a semiconductor device having surface planarity. It is another object of the invention to provide a VLSI device having interlevel planarity. It is another object of the invention to provide a planar surface on a semiconductor device by chem-mech etching/polishing using techniques and materials that result in predictable rates of SiO2 removal from run to run. It is another object of the invention to planarize all high spots on the surface of the device without sacrificing uniformity of insulator thickness. It is another object of the invention to provide an etch stop material under conditions which are compatible with BEOL processing. It is another object of the invention to provide an etch stop material which is harder than SiO2 and is relatively more resistant to the chem-mech slurry chemistry. It is another object of the invention to be able to clean thoroughly the planarized device after the step of etching, including nondestructively removing vestiges of the etch stop material once it has served its purpose. These and other objects are achieved according to the present invention in which planarity of a semiconductor device is produced by a method which includes: providing a substrate on which are disposed topographical features including metallic traces and pads and which is coated overall by a first layer of insulating material with an irregular surface; depositing on the layer of insulating material a second layer comprising conformal diamond or diamond-like carbon (DLC) as an etch stop layer; chem-mech polishing for a preselected time in a slurry and with a soft polishing pad having a shore hardness of less than 70 such that the first layer polishes at a rate greater than that of the second layer and such that the remaining thickness of insulation at termination of polishing is known and is substantially planar (less then 50 nm roughness); and, finally removing any diamond or carbon-containing debris. In an embodiment of the present invention, a semiconductor substrate having disposed thereon conductor traces and pads comprised of aluminum-based alloy, such as Al-Cu, is sputter coated with about 1 micrometer of a doped or non-doped glass such as SiO2 such that the entire substrate surface including traces, pads and any other surface features are coated with a layer of the glass. A layer comprising CVD diamond or DLC is deposited overall at a nondestructive temperature and the device is chem-mech polished for a time sufficient to achieve planarity. According to methods known in the art, but at low temperatures, the diamond or CVD film is deposited by the thermal, electrical or catalytic fragmentation of a carbon-containing material such as a hydrocarbon precursor, for example methane, ethane, ethylene, acetylene, alcohol and mixtures thereof. Residual carbon is removed, such as by reactive ion etching (RIE). The planarized device is ready to enter further processing whereby additional such devices are constructed to form a multilevel metal-semiconductor structure. FIG. 1 is a flow chart of the process of the invention. In order to facilitate understanding of the present invention, reference is made to the following detailed description taken in conjunction with the above described drawing. EXPERIMENTAL Wafers with a 3.0 micrometers film of bias sputtered quartz (BSQ), over the metal lines as shown in FIG. 1-1 were coated with a conformal diamond-like carbon (DLC) deposited from a hydrocarbon precursor by CVD at about 75 to about 200 degrees C as shown in FIG. 1-2. The depositions were split between 75 nm and 100 nm thick films to determine the optimum DLC thickness required for planar polishing. The topography on the metal pads where the film thickness was measured before polishing was 1.2 microns. The wafers were polished using a standard oxide planarization process: 8:1 water/colloidal silica slurry, 93.10 3 Pa (15 psi) pressure, 40 RPM for both quill and table speed. Two different polishing pads were evaluated, the IC-60, a hard pad, and the IC-40, a softer pad, Shore C hardness 70 and 55, respectively, from Rodel Inc. Newark, Delaware. The endpoint was determined by measuring the SiO2 thickness after polishing. Polishing pressure ranged from about 0.15 to about 0.7 kg/cm2, with-the preferred conditions being in the lower range. The advantage to using the DLC occurs when using the softer pad. Polishing with the softer pad results in less degradation of the SiO2 thickness uniformity across the wafer. It is surmised that this is true because the soft pad is more conformal, so that there is uniform removal of BSQ from both the high and low topography areas on the wafers. The DLC in these areas protects the BSQ from polishing until the surface is planar. No difference in the thickness uniformity or planarity was observed between polished wafers with and without the DLC film when processed using the harder pad. Actual BSQ removal over the raised (topographical) features was inhibited until the DLC film was removed. The effect of the DLC is very evident with the use of the softer IC-40 pad. The wafers without the protection of the DLC film show removal of material from the pad and the field regions almost immediately after polishing starts. The result of this effect is that topography remains around large features. The softness of the pad prevents planarization over these areas. The wafers protected with the DLC film demonstrate the removal of the BSQ over the pads while protecting the field regions. The 100 nm DLC film inhibits the removal of material from the raised features much longer than the 75 nm film. The thinner film is adequate to allow the pads to polish down to the field, and yields a more planar surface than the wafers without the DLC. The gradual planarization is shown in FIG. 1-3, 1-4, and 1-5. Oxygen ashing was used to remove the DLC layer using a power density of about 200 to about 500mW/cm2 at a pressure of about 30 to about 13.3 Pa. A removal rate of 100nm/min has been achieved at 100mTorr pressure. In that oxygen ashing of DLC carbon results in the formation of CO2 as a sole product, it is cleanly removed from the wafer, enabling further sequential use of the method without adding unknown materials to the final product. In the end, the resultant structure remains,unaltered apart from improved planarity.

Claims: A method of planarizing a semiconductor device, comprising: providing a planar substrate on which are disposed topographical features including metallic traces and pads; coating the substrate and topographical features overall with a first layer of insulating material with an irregular surface; coating the first layer with a second layer; chemical-mechanical polishing with a polishing pad in a slurry such that the material over the topographical features is removed at a faster rate than the material over the planar substrate; and stopping the process when substantial overall planarity is achieved characterized in that : said second layer comprises conformal diamond or diamond-like carbon material; said second layer is deposited within a temperature range of about room temperature to about 300°C; and, said polishing pad comprises a pad having a Shore hardness of less than 70. The method recited in claim 1, further including the step of removing any residual carbon. The method recited in claim 1 or 2, wherein the traces and pads are comprised of aluminum-copper alloy. The method recited in any above claim, wherein the first layer material comprises amorphous or SiO2 or quartz. The method recited in claim 4, wherein the SiO2 is deposited by sputtering. The method recited in any above claim, wherein the diamond or DLC is deposited by CVD, sputtering or from a hydrocarbon precusor. The method recited in claim 6, wherein the diamond or DLC is deposited to a thickness of about 75 nm to about 100 nm. The method recited in any above claim wherein the slurry comprises an aqueous colloidal silica slurry. The method recited in claim 2, wherein the residual carbon is removed by RIE or oxygen ashing.

Inventors: JASO MARK ANTHONY, JONES PAUL BRADLEY, MEYERSON BERNARD STEELE, PATEL VISHNUBHAI VITTHALBHAI, JASO, MARK ANTHONY, JONES, PAUL BRADLEY, MEYERSON, BERNARD STEELE, PATEL, VISHNUBHAI VITTHALBHAI
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1992
Main classification: H01L21
IPC codes: H01L21