Current mirror circuit

Abstract: A current mirror circuit comprises, first (2) and second (6) transistors of a first conductivity type whose emitters are connected to a power source (V) and whose bases are commonly connected; a third transistor (3) of the first conductivity type whose collector is connected to a reference potential and whose emitter is connected to the bases of the first and second transistors and whose base is connected to a collector of the first transistor; a fourth transistor (8) of the first conductivity type whose emitter is connected to a collector of the second transistor; and control means (4,7,9) for controlling a base of the fourth transistor by an output current which changes in accordance with a current flowing in the collector of the first transistor.

Description: BACKGROUND OF THE INVENTION Field of the Invention The invention relates to a current mirror circuit among electronic circuits which are used in various electronic apparatuses. Related Background Art A conventional current mirror circuit is constructed as shown in Figs. 1 and 2. The current mirror circuit of Fig. 1 has a circuit construction such that a constant current source 4 is connected to the collector side of a PNP transistor 2 in which the portion between the base and collector is short-circuited and a connecting point of the collector and base terminals is connected to a base terminal of another PNP transistor 6. Reference numeral 1 denotes a power source line. A collector current I out of the transistor 6 is generally expressed as follows by using a collector current I in of the transistor 2 I out = I in 1 + 2 h FE or is expressed as follows in consideration of an Early effect I out = (1 + V CB V A ) I in , h FE = ∞ where, h FE : current amplification factor V CB : voltage between collector and base V A : early voltage. As will be obviously understood from the equation (1), however, I out depends on the magnitude of h FE . For instance, when h FE = 30, I out = 0.9375I in and an error of 6 % or more occurs. From the equation (2), even when h FE = ∞, for instance, if V A = 15 V and V CB = 2 V, I out = 0.88I in , so that there is a problem such that an error of 10 % or more really occurs. Fig. 2 is a diagram showing a current mirror circuit to reduce the dependency on h FE in the above two problems. An emitter of a transistor 3 whose collector is connected to a reference potential V Ref is connected to a base of the PNP transistor 2. A collector of the transistor 2 is connected to a base of the transistor 3. The other construction is similar to that of Fig. 1. In case of the circuit of Fig. 2, the collector current I out of the transistor 6 is generally given by I out = I in 1+ 2 h FE (1+h FE ) For instance, in a manner similar to the circuit of Fig. 1, when h FE = 30, I out = 0.998I in and a mirror coefficient has a value which is almost near 100 %. However, the dependency on the voltage between collector and base due to the Early effect still remains and there is a problem such that a large error occurs in a manner similar to the circuit shown in Fig. 1. Document US-A-4 503 381 discloses a current mirror circuit comprising: first and second transistors of a first conductivity type whose emitters are connected to a power source and whose bases are commonly connected; a third transistor of said first conductivity type whose collector is connected to a reference potential and whose emitter is connected to the bases of said first and second transistors and whose base is connected to the collector of said first transistor; and a fourth transistor of said first conductivity type whose emitter is connected to the collector of said second transistor. Furthermore, US-A-4 412 186 discloses a current mirror circuit comprising two stages. The first stage comprises three PNP type transistors Q 11 , Q 12 , and Q 13 , the emitters of the first and second transistors Q 12 and Q 11 being connected to a first power supply terminal and their bases being commonly connected and connected to the emitter of the third transistor Q 13 . The collector of this third transistor Q 13 is connected to a second power supply terminal and its base is connected to the collector of the first transistor Q 12 . The emitter of fourth and fifth transistors Q 14 and Q 15 belonging to the second stage which also comprises three PNP transistors are connected to the collectors of the second and first transistors Q 11 and Q 12 of the first stage, respectively. Furthermore, an output current of the current mirror circuit changes in accordance with a collector current of the transistor Q 12 . In addition, EP-A-0 067 447 discloses a current mirror circuit comprising first and second current mirror transistors of a first conductivity type. Their emitters are both connected to a power supply, their bases are connected together, and their collectors are connected to an input terminal and an output terminal, respectively. A third first conductivity type transistor has its emitter connected to the bases of the first and second transistors and its collector connected to a reference potential point. It is an object of the present invention to provide a current mirror circuit which can simultaneously reduce the error due to the base current and the error due to the Early effect. According to the invention this object is accomplished by a current mirror circuit comprising: first and second transistors of a first conductivity type whose emitters are connected to a power source and whose bases are commonly connected; a third transistor of said first conductivity type whose collector is connected to a reference potential and whose emitter is connected to the bases of said first and second transistors and whose base is connected to the collector of said first transistor; and a fourth transistor of said first conductivity type whose emitter is connected to the collector of said second transistor; characterized by control means comprising a fifth transistor of a second conductivity type and a constant current source for controlling the base of said fourth transistor by an output current which changes in accordance with a current flowing in the collector of said first transistor; the base of said fifth transistor being connected to the collector of said first transistor, its collector being connected to said power source, and its emitter being connected to the base of said fourth transistor; and said constant current source being provided between the emitter of said fifth transistor and said reference potential. The present invention will be described hereinbelow by way of example and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a conventional current mirror circuit; Fig. 2 is a circuit diagram of another conventional current mirror circuit; Fig. 3 is a circuit diagram of the first embodiment of the invention; Fig. 4 is a diagram showing the result of simulation of the circuit of the invention; Fig. 5 is a diagram showing the result of simulation of the conventional circuit; and Fig. 6 is a circuit diagram of the second embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the invention will be described in detail hereinbelow with reference to the drawings. The invention, however, is not limited to the following embodiments but can be also applied to any other modifications which can accomplish the objects of the invention. (Embodiment 1) Fig. 3 shows a semiconductor integrated circuit according to the first embodiment of the invention. Reference numeral 1 denotes a power source line connected to a power source V. Reference numeral 2 denotes a bipolar transistor of a first conductivity type (PNP type) whose collector is connected to a constant current source 4 for causing the input current I in and whose emitter is connected to the power source line 1. The base of the bipolar transistor 2 is connected to a base of a transistor 6 which constructs a current mirror circuit together with the transistor 2. An emitter of the transistor 6 is connected to the power source line 1. Further, the bases of the transistors 2 and 6 are connected to the emitter of the transistor 3 of the first conductivity type whose collector is connected to the reference potential V Ref and which is used to compensate a base current. The collector of the transistor 2 is connected not only to the constant current source 4, but also to the base of the transistor 3 and a base of a transistor 7 of the second conductivity type (NPN type) whose collector is connected to the power source line 1. An emitter of the transistor 7 is connected to a base of a transistor 8 of the first conductivity type which gives the output current and the other terminal of a constant current source 9 whose one end is connected to the reference potential V Ref . An emitter of the transistor 8 is connected to a collector of the transistor 6. A collector current of the transistor 2 assumes I C2 , a base current assumes I B2 , an emitter current assumes I E2 , a voltage between base and emitter assumes V BE2 , and a voltage between collector and base assumes V CB2 . Similarly, for a transistor N, they are set to I CN , I BN , I EN , V BEN , and V CBN , respectively. On the other hand, a current amplification factor of the transistor of the first conductivity type assumes h FE1 , a current amplification factor of the transistor of the second conductivity type assumes h FE2 , and an Early voltage of the transistor of the first conductivity type assumes V A1 . The following equations are satisfied for the circuit of Fig. 3. I in = I C2 + I B3 - I B7 I B3 = I B2 +I B6 h FE1 ≃ 2I B2 h FE1 = 2I C2 h FE1 2 I B7 = I B -(I B7 +I B8 ) h FE2 = I B - I out h FE1 1+h FE2 The equation (4) shows that by setting I B3 = I B7 , the input currents I in and I C2 can be equalized and the error due to the base current can be cancelled. The following equation (7) is obtained from the equations (5) and (6). 2I C2 h FE1 2 = I B - I out h FE1 1+h FE2 The invention intends to equalize the input current I in and the output current I out . From the equation (4), by setting I B3 = I B7 , I in = I C2 . Therefore, from the equation (7), the following equation (8) is derived. I B = 2+3h FE1 h FE1 2 ·I in By setting the current I B flowing in the constant current source 9 for bias to the value of the equation (8), the error of the base current can be cancelled. The reduction of the Early effect will now be described. The collector potentials V C2 and V C6 of the transistors 2 and 6 serving as a current mirror circuit can be respectively expressed as follows. Assuming that the potential of the power source line 1 is set to V CC , V C2 = V CC - V BE2 - V BE3 V C6 = V CC - V BE2 - V BE3 - V BE7 + V BE8 The following equations are generally satisfied. I S2 = (1 + V CB2 V A1 ) I S2 e x p qV BE2 kT I S6 = (1 + V CB6 V A1 ) I S6 e x p qV BE6 kT where, I S2 , I S6 : saturation currents in the opposite direction of the transistors 2 and 6, and q, k, T: constants. Since the portion between the emitter and base of each of the transistors 2 and 6 is short-circuited, V BE2 = V BE6 can be obtained in the equations (11) and (12). Generally, the opposite direction saturation currents of the transistors of the same size are almost equal in the integrated circuit and I S2 = I S6 can be set. Therefore, in order to set I S2 = I S6 , it is sufficient that the following equation (13) is satisfied from the equations (11) and (12). V CB2 = V CB6 However, since the bases are commonly connected, the meaning of the equation (13) is substantially the same as the following equation (14). V C2 = V C6 By setting V BE7 = V BE8 from the equations (9), (10), and (14), the collector potentials of the transistors 2 and 6 can be equalized and the Early effect can be reduced. From the equation (15), the following equation (16) is derived. kT q ln I C7 I S7 = kT q ln I out I S8 In the equation (16), the transistor current I C7 can be expressed by the following equation (18) I C7 = (I B - I out h FE1 ) / (1 + 1 h FE2 ) from the following equation (17). I C7 = I E7 - I B7 = (I B - I B8 ) - I B7 = I B - I out h FE1 - I C7 h FE2 From the equations (16) and (18), the following equation (19) is obtained. I B - I out h FE1 1 + 1 h FE2 I S7 = I out I S8 From the equation (19), by setting the Early effect can be eliminated. Fig. 4 shows the result of simulation according to the current mirror circuit of the invention. An axis of abscissa indicates the collector potential of the transistor 8 and an axis of ordinate indicates the output current. When the input current I in = 10 µA, the output current lies within a range from 10.00235 µA to 10.0025 µA so long as the collector potential lies within a range from 0 to 3V. An error of up to 0.025 % occurs. Fig. 5 shows the result of simulation of the conventional circuit of Fig. 2. Under the same condition as that mentioned above, the output current lies within a range from 11.89 µA to 10.38 µA and an error of up to 18.9 % occurs. The current mirror circuit of a high precision can be obtained by the invention. (Embodiment 2) Fig. 6 shows a circuit of embodiment 2 according to the invention. The conventional current mirror circuits are cascade connected. In this case, there are two advantages such that the constant bias current I B is unnecessary and the transistor of the second conductivity type is unnecessary. In a manner similar to the embodiment of Fig. 3, the collector potentials of the transistors 2 and 6 constructing the current mirror circuit can be equalized and the Early effect can be reduced. According to the invention as mentioned above, it is possible to obtain the current mirror circuit of a high precision which can remarkably reduce the error due to the base current and the error due to the Early effect.

Claims: A current mirror circuit comprising: first (2) and second (6) transistors of a first conductivity type whose emitters are connected to a power source (V) and whose bases are commonly connected; a third transistor (3) of said first conductivity type whose collector is connected to a reference potential (V ref ) and whose emitter is connected to the bases of said first and second transistors (2, 6) and whose base is connected to the collector of said first transistor (2); and a fourth transistor (8) of said first conductivity type whose emitter is connected to the collector of said second transistor (6); characterized by control means (4, 7, 9) comprising a fifth transistor (7) of a second conductivity type and a constant current source (9) for controlling the base of said fourth transistor (8) by an output current which changes in accordance with a current flowing in the collector of said first transistor (2); the base of said fifth transistor (7) being connected to the collector of said first transistor (2), its collector being connected to said power source (V), and its emitter being connected to the base of said fourth transistor (8); and said constant current source (9) being provided between the emitter of said fifth transistor (7) and said reference potential (V ref ). A current mirror circuit according to claim 1, characterized in that said control means (4, 10, 11) comprise sixth and seventh transistors (10, 11) of said first conductivity type, the emitter of said sixth transistor (10) being connected to the collector of said first transistor (2) and its collector being connected to the base of said seventh transistor (11), the collector of said seventh transistor (11) being connected to said reference potential (V ref ) and its emitter being connected to both the base of said sixth transistor (10) and the base of said fourth transistor (8).

Inventors: NAKAMURA HIROYUKI, NAKAMURA, HIROYUKI, Nakamura, Hiroyuki, c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: G05F3
IPC codes: H03F3, G05F3