Image signal coding and decoding apparatus

Abstract: Image signal coding and decoding apparatus is adapted to reduce the redundancy between move vectors in divided blocks of an image to realize enhanced data compression. The coding apparatus comprises a local decoder (9) for locally decoding quantized data; a move detector (11) for calculating the move vectors of individual subblocks defined by dividing each of macroblocks (MB) for move compensation of a dynamic image; a controller (12) for selecting an optimal process for the move vectors to minimize the redundancy; a move compensator for forming a predictive image; and a difference calculator (2) for calculating the difference between the predictive image and the original image signal corresponding thereto. The image signal decoding apparatus comprises an inverse multiplexer for separating the coded data into variable-length coded data and vector coded data; and a controller (30) for selecting an optimal move vector process on the basis of the vector coded data.

Description: The present invention relates to image signal coding and decoding apparatus for use in compression and expansion of data relating to dynamic images. In a previously proposed dynamic image compressing/ expanding apparatus, a dynamic image composed of, e.g., 720 pixels (horizontal) x 480 lines (vertical) as shown in Fig. 8 is divided into macroblocks (MB) each composed of 16 pixels x 16 lines. Each macroblock is further divided into four subblocks each composed of 8 pixels x 8 lines as shown in Fig. 9, and a move vector is generated in each of such subblocks. When there occurs merely little change in the movement of an image, the move vectors in the individual subblocks constituting the macroblock are substantially equal to one another as shown in Fig. 10(a). In such a case, the move vector in one of the four subblocks constituting the macroblock is applied to the other subblock and is encoded. More specifically, one move vector is encoded with regard to one macroblock MB which consists of four subblocks. [Coding per macroblock: MB unit mode] When there exists a relatively large change in the movement of the image, the move vectors in the individual subblocks become different from one another (as shown in Fig. 10(b)). Then the minimum, for example, of the move vectors in the individual subblocks constituting the macroblock is selected as a representative vector. Then there are encoded the representative vector and the differences between the representative vector and the move vectors in the subblocks other than the one having the representative vector. In this case, one move vector is encoded with regard to one subblock. [Coding per subblock: Representative value mode] In such coding per subblock where the difference between the representative vector of the macroblock and the move vector of each subblock is calculated, the redundancy can be reduced in comparison with the case of encoding the entire data (move vectors) of the individual subblocks constituting the macroblock, hence compressing the quantity of the data. However, in a zooming operation for example as shown in Fig. 11, there exists correlation between the mutually adjacent macroblocks to consequently raise a problem that some redundancy is still left in the data for calculation of the difference. The present invention has been accomplished in view of the circumstances mentioned. Embodiments of the invention provide image signal coding and decoding apparatus, and more particularly a move vector coder and decoder. for use in compression and expansion of move vector data representing moves of dynamic images. Embodiments of the invention provide improved apparatus which is capable of further reducing the redundancy of data to realise enhanced compression of the data. US-A-4,796,087 discloses image signal coding apparatus corresponding to the precharacterising portion of claim 1. Here, the coding apparatus starts with large blocks of image data. If no movement is detected for a block, a fixed block signal is transmitted with the image data. If movement is detected, the large block is broken down into smaller blocks for detection of move vectors for the smaller blocks. EP-A-0 397 402 discloses image signal coding apparatus in which the input signal is decimated to eliminate certain frames. The eliminated frames are reconstructed by interpolation after motion vector detection and the interpolated frame error is transmitted with the coded image data. According to one aspect of the present invention, there is provided an image signal coding apparatus for executing orthogonal transformation of an image signal composed of blocks of image data, then quantizing the transformed data, and subsequently coding the data thus quantized, said apparatus comprising: an inverse quantizer for inversely quantizing said quantized data; inverse transform means for inverse orthogonal transformation of the inversely quantized data; a move detector for calculating the move vectors of respective subblocks, formed by further dividing each of said blocks of image data, for movement compensation of a dynamic image; a move compensator for forming a predictive image by executing movement compensation in conformity with the output of said inverse transform means and the move vectors from said move detector; and a difference calculator for calculating the difference between the predictive image formed by said move compensator and the original image signal corresponding to the predictive image; characterised by: a controller for processing the move vectors for said blocks to generate processed move vectors for output with the coded image data, the controller selecting one of the first, second and third processes for generating said processed move vectors; said first process comprising selecting a first representative vector, determined in a predetermined manner from the move vectors for the subblocks in a said block, as the processed move vector for that block; said second process comprising calculating the differences between a second representative vector, determined in a predetermined manner from the move vectors for the subblocks in a said block, and respective move vectors for the subblocks, said second representative vector and said differences forming the processed move vectors for that block; and said third process comprising calculating the differences between a third representative vector, determined in a predetermined manner from the move vectors for the subblocks in a said block, and respective predictive vectors for the subblocks, said predictive vectors being generated from vectors derived for the current block and adjacent blocks, and said third representative vector and said differences forming the processed move vectors for said block; wherein the controller selects said first process for a block when the move vectors for the subblocks in that block are approximately equal, and otherwise selects either the second or third process so as to minimise the redundancy in the processed move vectors output with said coded image data. The controller may comprise a move vector memory means for storing the move vectors of the subblocks; a representative move vector memory means for storing the first representative move vector of each block (ie macroblock); a move vector predictive means for generating the predictive move vectors for the subblocks of the current macroblock on the basis of the first representative move vectors of the current macroblock and adjacent macroblocks stored in the memory means; a difference calculator means for calculating the difference between the predictive move vector of each subblock obtained from the predictive means or the second representative move vector and the actual move vector of the subblock. According to another aspect of the present invention, there is provided an image signal decoding apparatus for decoding the data output by the above-described coding apparatus, the decoding apparatus comprising an inverse multiplexer for separating the data into coded image data and processed move vector data; and a decoding controller for selecting, on the basis of said processed move vector data, one of three processing operations for said move vector data to generate therefrom the original move vectors for the subblocks of a said block; a decoder for decoding said coded image data to obtain decoded difference image data; an inverse quantizer for inversely quantizing said decoded difference image data; and inverse orthogonal transform means for inverse orthogonal transformation of the inversely quantized difference image data; and a decoded image generator for producing a predictive image through execution of movement compensation on the basis of the move vectors generated by said decoding controller, and generating a decoded image on the basis of said predictive image and the inversely transformed difference image data. Due to the constitution described above, it becomes possible to reduce the redundancy between the move vectors of the subblocks stored in the memory and the move vector of the current macroblock to consequently achieve a higher efficiency in coding an image signal with another advantage that realises complete expansion of the coded data compressed at the enhanced efficiency based on the reduction of the redundancy. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Fig. 1 shows the constitution of an exemplary dynamic image data coding apparatus where a move vector coder embodying the invention is applied; Fig. 2 shows subblocks having move vectors to be used as representative vectors of macroblocks when predictive vectors of the subblocks are calculated by a predictive circuit 14 in the apparatus of Fig. 1; Fig. 3 illustrates how predictive vectors of the subblocks in the current macroblock MB(N) are calculated by the predictive circuit 14 in the apparatus of Fig. 1; Fig. 4 is a flow chart for explaining an algorithm to determine an optimal coding mode by a controller 12 employed in the apparatus of Fig. 1; Fig. 5 shows a format of the data outputted from a VLC circuit 5 in the apparatus of Fig. 1; Fig. 6 shows the constitution of an exemplary move vector decoder for decoding the data encoded by the apparatus of Fig. 1; Fig. 7 is a flow chart for explaining an algorithm to control switches 24 and 25 by a switch controller 30 employed in Fig. 6; Fig. 8 illustrates how a dynamic image is divided into macroblocks each composed of 16 pixels x 16 lines; Fig. 9 shows a macroblock which consists of four subblocks each composed of 8 pixels x 8 lines; Figs. 10(a) and 10(b) show move vectors in subblocks constituting a macroblock; and Fig. 11 shows move vectors in subblocks in a zooming operation. Fig. 1 shows the constitution of an exemplary dynamic image data coding apparatus where a move vector coder embodying the invention is applied. In this embodiment, a frame memory 1 stores, block by block as shown in Fig. 2, a digital signal obtained through analog-to-digital conversion of, by an A-D converter (not shown), an image signal outputted from a video camera (not shown) or the like. A calculator 2 calculates the difference between the data read out from the frame memory 1 and the data outputted from a local decoder 9, and a DCT circuit 3 executes a discrete cosine transformation of the input data. A quantizer 4 quantizes the data outputted from the DCT circuit 3, and a VLC circuit 5 converts the quantized output data of the quantizer 4 into a variable length code and multiplexes the same with the data outputted from a controller 12. An inverse quantizer 6 inversely quantizes the data outputted from the quantizer 4, and an inverse DCT circuit 7 executes an inverse discrete cosine transformation of the data outputted from the inverse quantizer 6. A move detector 11 detects the movement of an image of each block stored in the frame memory 1 and supplies the detected move vector to the controller 12. A predictive circuit 14 incorporated in the controller 12 comprises, similarly to a predictive circuit 31 shown in Fig. 6, a representative value register 14a, a vector memory 14b and calculators 14c, 14d. The representative value register 14a temporarily stores, out of the entire vectors stored in the memory 13, a representative vector which is in the lower right subblock (denoted by a symbol *) in each macroblock which consists of four subblocks as shown in Fig. 2. The vector memory 14b stores the representative vector read out from the register 14a, and the calculator 14c adds the representative vector of the current macroblock, which is stored in the representative value register 14a, to the representative vector of the preceding macroblock (anterior to the current macroblock) stored already in the vector memory 14b. Subsequently the calculator 14d multiplies the output value (vector) of the calculator 14c by 1/2. Namely, the predictive circuit 14 calculates the average (predictive value) of the representative vector of the current macroblock stored in the representative value register 14a and the representative vector of the preceding macroblock stored already in the vector memory 14b. The controller 12 calculates the difference between the predictive vector obtained from the predictive circuit 14 and the vector inputted to the controller 12. Further the controller 12 designates a step size and so forth in each of the quantizer 4 and the inverse quantizer 6 in accordance with the input vector. An address generator 10 addresses the move vector supplied thereto from the move detector 11 via the controller 12 and delivers the addressed move vector to a local decoder 9, Then, with reference to the address given to the move vector by the address generator 10, the local decoder 9 performs a move compensation corresponding to the move vector relative to the data stored in an incorporated memory (not shown), and supplies the move-compensated data to the calculators 2 and 8. The calculator 8 adds the output data of the local decoder 9 to the output data of the inverse DCT circuit 7 and then supplies the added data to the memory incorporated in the local decoder 9. Thus, the predictive image data is stored in the memory of the local decoder 9. Now an explanation will be given below with regard to the operation. The image data divided into macroblocks and further into subblocks as shown in Fig. 3 are stored in the frame memory 1 block by block. The data of each subblock thus stored in the frame memory 1 is read out therefrom, and then the difference between such data and the predictive image data outputted from the local decoder 9 is calculated by the calculator 2. Subsequently the difference data is inputted to the DCT circuit 3 where a discrete cosine transformation is executed. The data outputted from the DCT circuit 3 is supplied to the quantizer 4, and then the quantized data therefrom is supplied to the VLC circuit 5. The output data of the quantizer 4 is inversely quantized by the inverse quantizer 6 and then is supplied to the inverse DCT circuit 7 where an inverse cosine transformation is executed. The data thus transformed (difference data) is added by the calculator 8 to the predictive image data outputted from the local decoder 9, whereby the former image data is regained. Such image data is supplied to and stored in the memory incorporated in the local decoder 9, so as to be used for predictive image data which is supplied next from the frame memory 1 to the calculator 2. Meanwhile the movement of the image (move vector) stored in the frame memory 1 is detected block by block in the move detector 11, and such move vector is supplied via the controller 12 to the address generator 10 where an address is given. Then the addressed move vector is outputted to the local decoder 9. Subsequently with reference to the address given to the move vector, the local decoder 9 performs a move compensation corresponding to the move vector relative to the data stored in the incorporated memory of the local decoder 9, whereby the predictive image data is produced. The output data of the local decoder 9 is subtracted by the calculator 2 from the output data of the frame memory 1. A P picture is produced on the basis of the decoded I picture (intracoded image) or the decoded P picture (preceding predictive coded image) positioned temporally anterior as the predictive image (reference image for calculation of the difference). Further a B picture (bidirectional predictive coded image) is produced on the basis of the decoded I picture or P picture positioned temporally posterior or three kinds of interpolated images obtained from both the I and P pictures. The I picture is produced in case merely the data from the frame memory 1 is supplied to the DCT circuit 3, without utilizing the data obtained from the local decoder 9. The move-compensated data inputted from the local decoder 9 is added by the calculator 8 to the data supplied from the inverse DCT circuit 7, whereby an image of the decoded I picture, P picture or B picture is produced and then is supplied to and stored in the memory incorporated in the local decoder 9. Meanwhile, the move vector outputted from the move detector 11 is temporarily stored in the memory 13 of the controller 12. And when the vector stored in the memory 13 is decided in the controller 12 to be the representative vector of the macroblock (i.e., the move vector in the lower right one of the four subblocks constituting the macroblock), such vector is stored in the representative value register 14a. Upon completion of calculating the below-mentioned predictive value (average) in the predictive circuit 14, the representative vectors of the individual macroblocks stored in the representative value register 14a are sequentially stored in the vector memory 14b. In the predictive circuit 14, the process of calculating the predictive value is executed in the following procedure. First, as shown in Fig. 3, there are stored in the memory 13 the vectors of the four mutually adjacent macroblocks MB such as MB(N-46) at the upper left of the current macroblock MB(N), MB(N-45) above the current macroblock MB(N), subsequently MB(N-1) at the left of the current macroblock MB(N), and then MB(N) in this order. Thereafter the representative vector VN of the macroblock MB(N) stored last is read out and stored in the representative value register 14a. Subsequently in the predictive circuit 14, there are calculated the respective averages of such representative vector VN and the other representative vectors VN-46, VN-45 and VN-1 of the macroblocks MB(N-46), MB(N-45) and MB(N-1) stored previously in the vector memory 14b. In the controller 12, the average of the representative vector VN of MB(N) and the representative vector VN-46 of MB(N-46) is determined to be the predictive value (predictive vector) of the subblock existing between the two subblocks relative to such representative vectors, and the difference between the predictive value thus obtained and the actual vector of the subblock is calculated and outputted. More specifically, the difference between the vector Va and the average of the representative vector VN of MB(N) and the representative vector VN-46 of MB(N-46) is outputted as a move vector of the subblock having the vector Va (i.e., the subblock existing between the lower right subblock of the macroblock MB(N-46) and the lower right subblock of the current macroblock MB(N). Similarly, the difference between the vector Vb and the average of the representative vector VN of MB(N) and the representative vector VN-45 of MB(N-45) is outputted as a move vector of the subblock having the vector Vb (i.e., the subblock existing between the lower right subblock of the macroblock MB(N-45) and the lower right subblock of the current macroblock MB(N). And further the difference between the vector Vc and the average of the representative vector VN of MB(N) and the average vector VN-1 of MB(N-1) is outputted as a move vector of the subblock having the vector Vc (i.e., the subblock existing between the lower right subblock of the macroblock MB(N-1) and the lower right subblock of the current macroblock MB(N)). In the manner mentioned, there are calculated the difference vectors equivalent to the differences between the averages (predictive vectors) and the three move vectors Va, Vb, Vc other than the representative vectors VN of the current macroblock MB(N), and then the representative vector VN of MB(N) is stored in the vector memory 14b. In the VLC circuit 5, the three difference vectors calculated with respect to the individual macroblocks and the representative vectors of such macroblocks are multiplexed with the corresponding picture data (I, P or B picture) as the move compensating vectors for the I, P or B picture quantized by the quantizer 6. Due to the process mentioned, the data stored in the memory of the local decoder 9 corresponds to the image formed by decoding the data outputted from the VLC circuit 5, so that it is rendered possible to obtain the data of the P picture or the B picture sequentially by utilizing the data stored in the memory of the local decoder 9. Hereinafter the procedure of processing the move vectors in the controller 12 will be described with reference to the flow chart of Fig. 4. First at step S41, the move vectors of four subblocks constituting the macroblock (current MB) to be encoded now are compared with one another. If the result of such comparison at step S41 signifies that the vectors of the four subblocks constituting the current MB are approximately equal to one another (i.e., any difference between the individual vectors is smaller than the predetermined reference value), the operation proceeds to step S42 where the vector of one of the four subblocks constituting the current MB (in the example of Fig. 3, the lower right one of the macroblock) is selected as the move vector of the macroblock. The move vector thus selected is multiplexed in the VLC circuit 5 to serve as a move compensating vector for the current MB. [MB unit mode] If the result of the comparison at step S41 signifies that the vectors of the four subblocks constituting the current MB are mutually different (i.e., any difference between the individual vectors is greater than the predetermined reference value), the operation proceeds to step S43 for calculating the differences between the minimum of the vectors of the four subblocks constituting the current MB and the other vectors. Also the difference vectors are calculated from the predictive vectors of the current MB calculated by the predictive circuit 14. Subsequently at step S44, the three difference vectors equivalent to the differences between the minimum vector of the four subblocks constituting the current MB and the other vectors are compared with the three difference vectors calculated from the predictive vectors of the current MB. And if the result of such comparison at step S44 signifies that the data quantity of the three difference vectors calculated from the predictive vectors of the current MB is smaller, the operation proceeds to step S45 where, in the VLC circuit 5, the three difference vectors and the move vector (representative vector) of the lower right one of the four subblocks constituting the current MB are multiplexed to serve as move compensating vectors for the individual subblocks. [Predictive value mode] When the result of the comparison at step S44 signifies that the three difference vectors equivalent to the differences between the minimum of the vectors of the four subblocks constituting the current MB and the other vectors are smaller, the operation proceeds to step S46 where, in the VLC circuit 5, the minimum vector of the current MB and the three difference vectors thereof are multiplexed to serve as move compensating vectors for the individual subblocks. [Representative value mode] As described above, the redundancy between the individual subblocks of the macroblock may be so low as to enable coding by the MB unit mode. In case some redundancy is left between the macroblocks in execution of coding by the representative value mode, the predictive value mode is selectively employed to reduce the redundancy between the macroblocks, hence attaining high compression of the data. Fig. 5 shows the format of the data multiplexed in the VLC circuit 5. An MB header comprises addresses and so forth of the macroblocks MB, and a move compensation mode flag (denoted by a variable A) becomes "0" for example when the move compensation is performed per macroblock MB, or becomes "1" for example when such compensation is performed per subblock. In case the move compensation is performed per subblock (with the move compensation mode flag "1") by the predictive value mode, a subblock vector transfer mode flag (denoted by a variable B) becomes "1" for example. Meanwhile, in case the move compensation is performed per subblock (with the move compensation mode flag "1") by the representative value mode, the subblock vector transfer mode flag becomes "0" for example. And in succession to the subblock vector transfer mode flag, there are additionally affixed the move vector corresponding to the move compensation mode flag and the subblock vector transfer mode flag, and also coefficients of the data processed through the discrete cosine transformation and outputted from the DCT circuit 3 via the quantizer 4. Fig. 6 shows the constitution of an exemplary vector decoding apparatus used to decode the data encoded in the aforementioned data format. In this embodiment, an inverse VLC circuit 21 processes the input data by inverse variable length coding, and an inverse quantizer 22 executes inverse quantization of the data outputted from the inverse VLC circuit 21. An inverse DCT circuit 23 executes inverse discrete cosine transformation of the data outputted from the inverse quantizer 22 and delivers the transformed data to a calculator 26. Subsequently the calculator 26 adds the output data of the inverse quantizer 22 to the output data of a move compensator 28 and delivers the added data to a frame memory 29, which then stores the data outputted from the calculator 26. A switch controller 30 controls a first switch 24 (SW1) and a second switch 25 (SW2) in conformity with the move compensation mode flag or the subblock vector transfer mode flag outputted from the inverse VLC circuit 21. The first switch 24 is controlled by the switch controller 30 to select a zero (no signal), or the difference vector outputted by the representative value mode from the inverse VLC circuit 21, or the difference vector outputted by the predictive value mode from the circuit 21, and delivers the selected data to the calculator 27. Meanwhile the second switch 25 selects the MB-representing move vector encoded by the MB unit mode and stored in a representative value register 31a which constitutes a predictive circuit 31 in combination with a vector memory 31b and calculators 31c, 31d, or the minimum of the move vectors of the MB-constituting subblocks corresponding to the representative vectors obtained by the representative value mode, or the predictive vector outputted from the calculator 31d of the predictive circuit 31. The data thus selected is delivered to the calculator 27. The calculator 27 adds the data (vectors) outputted from the two switches 24 and 25. Subsequently a move compensator 28 executes, in accordance with the output vector of the calculator 27, a move compensation for the data stored in a frame memory 29, and then delivers the move-compensated data to a calculator 26. Now the operation of such decoding apparatus will be described below with reference to the flow chart of Fig. 7. First a decision is made at step S51 with regard to the move compensation mode flag outputted from the inverse VLC circuit 21 and supplied to the switch controller 30. If the result of the decision signifies that the move compensation mode (MC) flag is equal to "0", i.e., the data to be decoded is the one encoded by the MB unit mode, the operation proceeds to step S52 where the switches 24 and 25 are set to the upper positions thereof. In this case, the MB-representing move vector outputted from the inverse VLC circuit 21 is stored in the representative value register 31a. Since the switch 24 is set to its upper position, a zero indicative of no signal is delivered therefrom. Meanwhile from the switch 25 set also to its upper position, there is delivered the MB move vector stored in the representative value register 31a. Accordingly, the zero and the MB move vector stored in the representative value register are added to each other by the calculator 27. Namely, the MB move vector stored in the representative value register is outputted without any change from the calculator 27 to the move compensator 28. If the result of the decision at step S51 signifies that the move compensation mode (MC) flag is equal to "1", the operation proceeds to step S53 for making another decision with regard to the subblock vector transfer mode flag outputted from the inverse VLC circuit 21. When the result of such decision signifies that the subblock vector transfer mode flag is equal to "0", i.e., the data to be decoded is the one encoded by the representative value mode, the operation proceeds to step S54 where the first switch 24 is set to the lower position while the second switch 25 is set to the upper position. In this case, the minimum vector of the macroblock outputted from the inverse VLC circuit 21 is stored in the representative value register 31a. Since the first switch 24 is set to the lower position, the difference vectors of the individual subblocks of the macroblock based on the representative value mode are outputted therefrom. Meanwhile from the second switch 25 set to the upper position, there is outputted the minimum vector of the macroblock stored in the representative value register 31a. Accordingly the difference vectors equivalent to the differences between the minimum vector of the macroblock and the other vectors thereof are added to the minimum vector of the macroblock by the calculator 27. Namely, the move vectors of the individual subblocks of the macroblock are decoded in the calculator 27 and are outputted therefrom to the move compensator 28. In case the result of the decision at step S53 signifies that the subblock vector transfer mode flag is equal to "1", i.e., the data to be decoded is the one encoded by the predictive value mode, the operation proceeds to step S55 where the switches 24 and 25 are both set to the lower positions thereof. In this case, the vectors of the lower right subblocks of the macroblocks outputted from the inverse VLC circuit 21 are stored in the representative value register 31a. Since the first switch 24 is set to its lower position, the difference vectors of the individual subblocks of the macroblock based on the predictive value mode are outputted therefrom. Meanwhile from the second switch 25 set to its lower position, there are outputted the predictive vectors calculated by the predictive circuit 31. (This operation is the same as that in the aforementioned case of the predictive circuit 14 in the coding apparatus of Fig. 1.) Therefore the difference vectors equivalent to the differences between the predictive vector and the move vectors other than the representative vector of the macroblock are added to the predictive vector by the calculator 27. Namely, the move vectors of the individual subblocks of the macroblock are decoded by the calculator 27 and then are outputted therefrom to the move compensator 28. Meanwhile the data outputted from the inverse VLC circuit 21 is inversely quantized in the inverse quantizer 22 and then is supplied to the inverse DCT circuit 23, where the data is processed through an inverse discrete cosine transformation. When the data thus transformed is the I-picture data, it is supplied without any change via the calculator 26 to the frame memory 29 and is stored therein. In case the data outputted from the inverse DCT circuit 24 is the P-picture data based on the predictive image of I or P picture, the I- or P-picture data is read out from the frame memory 29 and then is supplied to the move compensator 28 where a move compensation is executed correspondingly to the move vector outputted from the calculator 27. Subsequently the move-compensated data is supplied to the calculator 26 where the output data of the inverse DCT circuit 23 is added to the output data of the move compensator 28 to thereby generate P-picture data, which is then stored also in the frame memory 29. When the B-picture data is outputted from the inverse DCT circuit 23, the I-picture or P-picture data is read out from the frame memory 29 and then is supplied to the move compensator 28 where a move compensation is executed correspondingly to the move vector outputted from the calculator 27. Subsequently the move-compensated data is supplied to the calculator 26 where the output data of the inverse DCT circuit 23 is added to the output data of the move compensator 28 to thereby generate the decoded B-picture data, which is then stored also in the frame memory 29. The data thus stored in the frame memory 29 are supplied to a D-A converter (not shown) where digital-to-analog conversion of the data is executed, and the converted data are further supplied to a cathode-ray tube (not shown) or the like so as to be displayed. In the manner described above, the highly compressed data can be decoded in conformity with the redundancy thereof. In the embodiment mentioned, the move vector in the lower right subblock of each macroblock is selectively adopted as a representative vector in the predictive value mode. Such adoption is based on the fact that the scanning in a video camera and a cathode-ray tube is generally performed rightward from the left and downward from the top. More specifically, before completion of the scanning on the representative vector VN of the current macroblock MB(N) as shown in Fig. 3, it is necessary, for calculating the predictive values of the vectors Va, Vb, Vc in the other subblocks of the current macroblock MB(N), to complete the scanning on the representative vectors VN-46, VN-45 and VN-1 of the other preceding macroblocks MB(N-46), MB(N-45) and MB (N-1). Therefore, it is preferred that the subblock having the move vector to be selected as the representative vector by the predictive value mode is the last one of the individual subblocks of the macroblock with respect to the scanning order in the video camera and the cathode-ray tube. In the image signal coding apparatus described above, it is possible to reduce the redundancy between the move vectors of the stored subblocks and the move vector of the current macroblock to consequently achieve an enhanced coding efficiency in compressing the move vectors. In the image signal decoding apparatus described above it is possible to expand the move vectors compressed at a high efficiency with reduction of the redundancy.

Claims: An image signal coding apparatus for executing orthogonal transformation of an image signal composed of blocks (MB) of image data, then quantizing the transformed data, and subsequently coding the data thus quantized, said apparatus comprising: an inverse quantizer (6) for inversely quantizing said quantized data; inverse transform means (7) for inverse orthogonal transformation of the inversely quantized data; a move detector (11) for calculating the move vectors of respective subblocks (SB), formed by further dividing each of said blocks (MB) of image data, for movement compensation of a dynamic image; a move compensator (9) for forming a predictive image by executing movement compensation in conformity with the output of said inverse transform means (7) and the move vectors from said move detector (11); and a difference calculator (2) for calculating the difference between the predictive image formed by said move compensator (11) and the original image signal corresponding to the predictive image; characterised by: a controller (12) for processing the move vectors for said blocks (MB) to generate processed move vectors for output with the coded image data, the controller (12) selecting one of the first, second and third processes for generating said processed move vectors; said first process comprising selecting a first representative vector, determined in a predetermined manner from the move vectors for the subblocks (SB) in a said block (MB), as the processed move vector for that block (MB); said second process comprising calculating the differences between a second representative vector, determined in a predetermined manner from the move vectors for the subblocks (SB) in a said block (MB), and respective move vectors for the subblocks (SB), said second representative vector and said differences forming the processed move vectors for that block (MB); and said third process comprising calculating the differences between a third representative vector, determined in a predetermined manner from the move vectors for the subblocks (SB) in a said block (MB), and respective predictive vectors for the subblocks (SB), said predictive vectors being generated from vectors derived for the current block (MB) and adjacent blocks (MB), and said third representative vector and said differences forming the processed move vectors for said block (MB); wherein the controller selects said first process for a block (MB) when the move vectors for the subblocks (SB) in that block are approximately equal, and otherwise selects either the second or third process so as to minimise the redundancy in the processed move vectors output with said coded image data. Apparatus according to claim 1, wherein said first and third representative vectors are the same. Apparatus according to claim 2, wherein said first and third representative vectors are the move vector for the subblock (SB) which is scanned last in the temporal scanning sequence for the block (MB) of image data. Apparatus according to any preceding claim, wherein said second representative vector is the minimum of the move vectors for the subblocks (SB) in the block (MB) of image data. Apparatus according to any preceding claim, wherein said controller includes: move vector memory means (13) for storing the move vectors of said subblocks (SB); representative move vector memory means (14b) for storing the first representative vector of each block (MB); move vector predictive means (14) for generating the predictive move vectors for the subblocks (SB) of the current block (MB) from the first representative move vector of the current block (MB) and the first representative move vectors of adjacent blocks (MB) stored in said memory means (14b); and difference calculator means for calculating the difference between the predictive move vector of each subblock (SB) obtained from said predictive means (14) or said second representative move vector and the actual move vector of said subblock (SB). Apparatus according to any preceding claim, including means (5) for multiplexing said quantized data and the processed move vector data output by said controller (12). Apparatus according to any preceding claim, wherein said predictive vector for a subblock (SB) has the average value of the third representative vectors of said current block (MB) and a temporally preceding adjacent block (MB). An image signal decoding apparatus for decoding the data output by coding apparatus as claimed in any preceding claim, the decoding apparatus comprising: an inverse multiplexer (21) for separating the data into coded image data and processed move vector data; and a decoding controller (30, 31, 24, 25, 27) for selecting, on the basis of said processed move vector data, one of three processing operations for said move vector data to generate therefrom the original move vectors for the subblocks (SB) of a said block (MB); a decoder (21) for decoding said coded image data to obtain decoded difference image data; an inverse quantizer (22) for inversely quantizing said decoded difference image data; and inverse orthogonal transform means (23) for inverse orthogonal transformation of the inversely quantized difference image data; and a decoded image generator (28, 26) for producing a predictive image through execution of movement compensation on the basis of the move vectors generated by said decoding controller, and generating a decoded image on the basis of said predictive image and the inversely transformed difference image data. Apparatus as claimed in claim 8, wherein said coded image data is variable-length coded data and said decoder (21) comprises inverse variable-length coding means.

Inventors: FUJINAMI YASUSHI, FUJINAMI, YASUSHI, Fujinami, Yasushi, c/o Patents Division Sony Corp.
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H04N7
IPC codes: H04N7, G06T9