Chrominance signal processing circuit

Abstract: When an input signal is of PAL type, a switch (20) is shifted to a position a such that the PAL chrominance signal is supplied directly to a converting circuit (30). The converting circuit (30) sequentially performs the addition and subtraction for a signal from a BP amplifier (22) and for an output of a delay circuit (29) to form B-Y and R-Y signal components which are in turn supplied respectively to R-Y and B-Y demodulators (31 and 32). On the other hand, if an input signal is of SECAM type, the switch (20) is shifted to the side b such that the signal demodulated by a demodulating circuit (14) will include a burst component having of invariable phase overlaid thereon at a modulating circuit (19) while a amplitude-modulated carrier signal is supplied to the BP amplifier (22). The converting circuit (30) sequentially switches signals from the BP amplifier (22) for each horizontal line, the switched signal being then supplied to the B-Y and R-Y demodulators (31 and 32). In such a manner, the inputted signals can be demodulated into B-Y and R-Y signals whether they are PAL or SECAM type.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a chrominance signal processing circuit capable of demodulating both PAL and SECAM type chrominance signals and particularly to such a circuit having a reduced number of components. A chrominance signal processing circuit according to the preamble part of the claim 1 is known from JP-A-62 269 592. This circuit is capable of demodulating both the SECAM and PAL types of chrominance signals. Description of the Related Art: There is known a chrominance signal processing circuit adapted to convert a SECAM type chrominance signal into a PAL type chrominance signal which is in turn demodulated by a PAL type demodulator. Such a chrominance signal processing circuit does not require circuitry for processing the SECAM type chrominance signal, resulting in a reduction in the number of components. In areas where both types of chrominance signals can be received, thus, television receiver sets having such chrominance signal processing circuits are currently used. One of such chrominance signal processing circuits is described, for example, in Japanese Patent Laid-Open No. Sho JP-A-53-6534. Referring now to Fig. 1, there is shown a transcoder included in such a chrominance signal processing circuit, which can convert a SECAM type chrominance signal into a PAL type chrominance signal and is contained in an integrated circuit shown enclosed by a broken line. The SECAM type system frequency-modulates color difference signals (R-Y) and (B-Y) sequentially for each horizontal line and overlays the frequency-modulated signals on luminance signals while the PAL type system amplitude-modulates color difference signals (R-Y) and (B-Y) while inverting the phase of the (R-Y) signal for each horizontal line, the amplitude-modulated signals being then overlaid on luminance signals. Referring again to Fig. 1, the transcoder comprises a filter 2 which functions to pass only a chrominance signal therethrough when a SECAM type composite video signal 101 is applied to the input terminal 1 of the transcoder; a SECAM demodulator 3 for demodulating a frequency-modulated chrominance signal; a clamping circuit 4 for clamping the demodulated chrominance signal; a PAL modulator 5 for amplitude-modulating the clamped chrominance signal into a PAL signal; and an oscillator 6 having a frequency which has been set to the subcarrier frequency of the PAL signal (4.43 MHz). The converted PAL signal is fed respectively to a delay circuit 7 and level regulating circuit 8 which are located outside the integrated circuit of the transcoder. The delay circuit 7 is adapted to delay the PAL signal by one horizontal synchronizing signal period. After processed, the PAL signal is again fed to a matrix circuit 9 in the integrated circuit. The integrated circuit further includes a control circuit 10 which is responsive to the output signal of the SECAM demodulator 3 to judge whether the signal 101 being received is an R-Y or a B-Y signal. Thus, the control cir cuit 10 applies control signals 102 inverted for each one horizontal synchronizing signal period to the matrix circuit 9. The matrix circuit 9 performs the addition or subtraction for two inputted chrominance signals and responds to said control signals to output the result of addition or subtraction for each horizontal synchronizing signal period. The operation of the matrix circuit 9 will be described with reference to Figs. 2A - 2C. Fig. 2A shows an output signal 103 from the level regulating circuit 8, including amplitude-modulated R-Y and B-Y signal components each of which is fed to the matrix circuit 9 for each horizontal synchronizing signal period. Fig. 2B shows an output signal 104 from the delay circuit 7, which is obtained by delaying the respective one of the signal components shown in Fig. 2A by one horizontal synchronizing signal period. Fig. 2C shows an output signal from the matrix circuit 9, which is provided by adding the signal of Fig. 2A to the signal of Fig. 2B in a first horizontal synchronizing signal period and subtracting the signal of Fig. 2B from the signal of Fig. 2A in the next horizontal synchronizing signal period. Such addition and subtraction operations are subsequently repeated in the matrix circuit 9 to form PAL type chrominance signals in which the phase of the R-Y signal components is inverted for each horizontal line, as shown in Fig. 2C. If the signal of Fig. 2C is applied to the PAL type demodulating circuit, one can provide a PAL type television receiver set which can receive SECAM signals. However, the prior art transcoder must have a complicated PAL modulator 5 for converting SECAM signals into PAL signals. Such a PAL modulator 5 requires the insertion of a burst signal having its phase of 135 degrees (assuming that the phase of the B-Y signal is equal to zero) and another burst signal having its phase of 225 degrees alternately into the chrominance signals for each horizontal synchronizing signal period. It has been thus proposed that a signal having an invariable phase, such as an NTSC type burst signal, is used. If such a signal is inserted into a chrominance signal, the modulated signal could not be demodulated by the PAL demodulating circuit in the subsequent stage. Furthermore, the prior art could not sometimes reproduce colors inherent in SECAM signals when the R-Y and B-Y signals were combined together. To overcome the disadvantages of the prior art circuits the present invention is characterized by the features of claim 1. In accordance with the present invention, a burst signal having its invariable phase (180 degrees) is inserted into the demodulated SECAM signal and at the same time the B-Y and R-Y signals are respectively modulated by carriers having phases of 0 and 90 degrees. The SECAM signals thus modulated are alternately outputted from the signal converting circuit for each horizontal synchronizing signal period after they have been compared with a signal from one horizontal synchronizing signal period before. In these outputted color difference signals, the R-Y and B-Y signal components are completely separated from each other. Thus, the signals can be demodulated by the PAL demodulator. The chrominance signal processing circuit of the present invention is also characterized by the fact that it comprises an oscillator adapted to oscillate in synchronism with the burst signal from the switch; an ID circuit for discriminating the phase of the burst signal from the switch; and an inverting circuit for sequentially inverting signals outputted from the oscillator in response to the output signal of the ID circuit. Further, if the discriminating circuit judges that the inputted chrominance signal is of PAL type, a signal having its invariable phase is supplied from the oscillator to the B-Y demodulating circuit and the inverting circuit is actuated so as to supply a signal having its phase inverted for each horizontal synchronizing signal period to the R-Y demodulating circuit while if the discriminating circuit judges that the inputted chrominance signal is of SECAM type, the signal having its invariable phase is supplied to the B-Y and R-Y demodulating circuits. The chrominance signal processing circuit of the present invention is further characterized by the fact that the carriers used in the modulating means to modulate the chrominance signal are at a phase of 0 degrees for the B-Y signal components and 90 degrees for the R-Y signal components and that the phase of the burst signal inserted in the modulating means is equal to 180 degrees. Thus, the insertion of the burst signal can be facilitated and the demodulating signal generating circuit used in the subsequent stage can be simplified in construction. The oscillator is characterized by the fact that it output signals have substantially the same phase for both of the burst signals which are contained in the inputted chrominance signal and inserted in the modulating means. In such an arrangement, there is not required any complicated demodulating circuit even if the burst signal inserted in the modulating means has a invariable phase. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a chrominance signal processing circuit constructed in accordance with the prior art. Figs. 2A, 2B and 2C are vector diagrams for illustrating the arrangement of Fig. 1. Fig. 3 is a block diagram of a chrominance signal processing circuit constructed in accordance with the present invention. Fig. 4 is a detailed circuit diagram of the signal converting circuit shown in Fig. 3. Figs. 5A - 5D are vector diagrams for illustrating the arrangement of Fig. 3. Fig. 6 is a detailed circuit diagram of the modulating circuit shown in Fig. 3. Figs. 7A - 7E are vector diagrams for illustrating the arrangement of Fig. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 3, there is shown one embodiment of a chrominance signal processing circuit constructed in accordance with the present invention. The chrominance signal processing circuit comprises an input terminal 11 for receiving a composite video signal 201 consisting of either a PAL or a SECAM modulated signal; a bell filter 12 for extracting a chrominance signal 202 from the SECAM signal from the input terminal 11; a band pass filter 13 for extracting a chrominance signal 203 from the PAL signal from the input terminal 11; a SECAM demodulator 14 for frequency-modulating the SECAM signal; a clamping circuit 15; a burst gate pulse generator for overlaying a burst pulse on the clamped SECAM signal; a CW generator 17 for generating carriers of 4.43 MHz; a ninety-degree phase shifter 18; a modulating circuit 19 for amplitude-modulating the B-Y and R-Y signal components in the demodulated SECAM signal containing the burst pulse overlaid thereon by the use of carriers having their phases of 0 and 90 degrees, respectively and also for overlaying burst signals having a phase of 180 degrees on the B-Y and R-Y signal components during the burst pulse period; a switch 20 for selectively outputting the PAL signal 203 from the band pass filter 13 or a signal 204 obtained by demodulating and amplitude-modulating the SECAM signal from the modulating circuit 19 in response to a judgment signal from a PAL/SECAM discriminator 21; a band pass amplifier 22 for separating a burst signal 301 from a chrominance signal 301; an ACC killer circuit 23 for performing automatic color control (ACC) based on the burst signal 302 and the control of color killer for stopping the operation of the band pass amplifier 22 on receiving mono-chrominance television signals; an automatic phase control (APC) circuit 24 for locking and driving an oscillator 25 for the burst signal 302; an ID circuit 26 for identifying whether the phase of the burst signal 302 in the PAL type chrominance signal is now 135 or 225 degrees, in response to the burst signal 302; a flip flop (FF) 27; an inverting circuit 28 for converting the output of the oscillator 25 into 0 or 180 degrees in response to the output of the flip flop 27; a delay circuit 29 for delaying the chrominance signal 301 by one horizontal synchronizing signal period; a signal converting circuit 30 for receiving the first output chrominance signal 301 from the band pass amplifier 22 and the second output chrominance signal 303 from the delay circuit 29 and for matrix calculating the signals 301 and 303 in the PAL mode and selectively outputting the signal 301 or 303 for each horizontal synchronizing signal period in the SECAM mode, in response to the judgment signal from the PAL/SECAM discriminator 21; a B-Y demodulator 31 for demodulating the B-Y signal components; and an R-Y demodulator 32 for demodulating the R-Y signal components. The ninety-degree phase shifter 33 is adapted to shift the phase of the 4.43 MHz signal from the oscillator 25 by 90 degrees and it then supplies the phase shifted signal to the B-Y demodulator. In Fig. 3, if the conventional PAL signals are being received by the system, the switch 20 is positioned at the side a opposite to the illustrated side. The PAL signal 201 is applied to the band pass amplifier 22 through the band pass filter 13 after the PAL signal has been converted into a chrominance signal 203. The band pass amplifier 22 separates a burst signal from the PAL signal in response to a burst gate pulse BGP from the BGP generating circuit 16 and applies the chrominance signal 301 having no burst signal directly to the signal converting circuit 30. At the same time, the band pass amplifier 22 causes the signal 303 delayed by one horizontal synchronizing signal period in the delay circuit 29 to pass to the signal converting circuit 30. The signal converting circuit 30 is responsive to the output of the PAL/SECAM discriminator 21 (which in this case is a PAL signal) to function as a matrix circuit. The signal converting circuit 30 will now be described with respect to Fig. 4. In Fig. 4, the switches 33, 34, 35 and 36 are shifted to the PAL side, opposite to the illustrated side, in response to the judgment result of the PAL/SECAM discriminator 21 indicating that conventional PAL signals are being received. Thus, the signals 301 and 303 are summed at an adder 37 while they are subjected to subtraction at a subtractor 38. The signal 310 resulting from the addition (301+303) is fed to the B-Y demodulator through the switch 35 while the signal 311 resulting from the subtraction (301-303) is applied to the R-Y demodulator 32 through the switch 36. Such a situation will be further described with reference to Figs. 5A - 5D. Fig. 5A shows a signal 301; Fig. 5B a signal 303; Fig. 5C an addition signal 310 (301+303) and Fig. 5D a subtraction signal 311 (301-303). Signals 310 having an invariable phase (0 degrees) are continuously applied to the B-Y demodulator 31 while the R-Y demodulator 32 receives signals 311 the phase of which is inverted into 90 or 270 degrees for each horizontal synchronizing signal period. The B-Y demodulator 31 also receives carriers having an invariable phase (0 degrees) from the oscillator 25 while the R-Y demodulator 32 also receives the outputs of the inverting circuit 28 which is inverted in response to the outputs of the flip flop 27. Thus, the R-Y demodulator 32 can detect the signal components -(R-Y) and (R-Y) shown in Fig. 5D as having the same phase. In such a manner, the first and second output terminals 39 and 40 can obtain PAL type B-Y and R-Y signal components. The inverting circuit 28 is initiated by the judgment signal (PAL) from the PAL/SECAM discriminator 21 and terminated by the other judgment signal (SECAM). When the circuit of Fig. 3 receives a frequency-modulated SECAM chrominance signal 202, it is applied to the SECAM demodulator 14 through the input terminal 11 wherein the signal is demodulated before it is clamped by the clamping circuit 15. The clamped SECAM chrominance signal is added with a signal BGP, which is at a lower level during the burst signal period, at the burst pulse generator 16, with the overlaid signal being then provided to the modulating circuit 19. Fig. 6 shows one specific arrangement of the modulating circuit 19 which comprises an adder circuit 41 for receiving and adding the chrominance signal (R-Y or B-Y signal component) from the clamping circuit 15 to the BP signal from the burst pulse generator 16, the sum of these signals being then applied to the modulating circuit 19. During the burst period, the switch 42 is positioned on the side a so that carriers of 0 degrees will be selected from the CW generator 17. On the other hand, a transistor 43 is turned off and a transistor 44 is turned on, in response to the "low level" BP signal. As a result, a differential amplifier 45 is turned on while the operation of a differential amplifier 46 is turned off. Therefore, the zero-degree carriers will be converted to have a phase equal to 180 degrees and will be provided to the output terminal 47. When the circuit enters the B-Y signal cycle, the switch 42 is again shifted to the side a. The collectors of the transistors 43 and 44 will have B-Y signals which are opposite to each other in phase. Thus, the carriers inputted into the differential amplifiers 45 and 46 are amplitude-modulated by the B-Y signals, the amplitude-modulated signals appearing at the output terminals 47. When the circuit enters the R-Y signal cycle, the switch 42 is shifted to the side b so that carriers of 90 degrees will be amplitude-modulated by R-Y signals. Consequently, the output terminals can readily obtain a chrominance signal including burst signal components, as shown in Fig. 7A. The signal of Fig. 7A is applied to the band pass amplifier 22 through the switch 20 of Fig. 3 wherein the burst signal components are separated from the chrominance signal components. The signal converting circuit 30 receives the chrominance signal 301 of Fig. 7B as well as the chrominance signal 303 of Fig. 7C which has been delayed by the delay circuit 29. As shown in Fig. 4, all the switches 33, 34, 35 and 36 of the signal converting circuit 30 are shifted to the opposite directions. Switches 48 and 49 are also shifted in response to a pulse signal H of one horizontal synchronizing signal period from a terminal 50. Thus, the signals of Figs. 7B and 7C will be extracted alternately for each horizontal synchronizing signal period. As a result, a signal of Fig. 7D occurs at the output end of the switch 48 while a signal of Fig. 7E occurs at the output end of the switch 49. All the signal components of Fig. 7D can be demodulated by the B-Y demodulator 31 since they have been modulated by the zero-degree carriers. All the signal components of Fig. 7E can be demodulated by the R-Y demodulator 32 using the outputs of the inverting circuit 28 which are fixed to one of the selected phases since the signal components have been modulated by the ninety-degree carriers. This is because the phase of the carriers applied to the inverting circuit 28 are inherently offset from that of the B-Y demodulator 31 by 90 degrees. Since each demodulator receives the corresponding color difference signal (e. g. the B-Y demodulator 31 receives only B-Y signals), these two types of color difference signals will not be combined with each other. Therefore, colors can be reproduced in accordance with the characteristics inherent in the SECAM system. In such a manner, the color difference signals demodulated by the SECAM system can occur at the first and second output terminals 39 and 40. It is to be noted herein that the BP amplifier 22 is adapted to separate burst signal components from the inputted chrominance signals and also to amplify these chrominance signals to a desired level. Therefore, the BP amplifier 22 can be constituted of a gain controllable amplifier and a switch. By shifting the switch in response to the BGP signal indicative of the BGP period from the BP generator 16, thus, the burst signal components can be supplied to the ACC killer circuit 23, APC circuit 24 and ID circuit 26. The ID circuit detects the phase of a burst signal component and judges whether it is of 135 or 225 degrees. The judgment result is stored by the flip flop 27. The APC circuit 24 together with the oscillator 25 are adapted to form a phase locked loop (PLL). The phase locked loop functions to provide a signal having the same frequency as that of the inputted burst signals to the APC circuit 24. If an input signal is a SECAM signal, a burst signal component inputted into the APC circuit 24 has its phase equal to 180 degrees. If the input signal is a PAL type, the phase of the burst signal component is repeatedly changed from 135 degrees to 225 degrees or vice versa for each horizontal synchronizing signal period. In this embodiment, the gain of the APC circuit 23 is selected to be any suitable level such that the phase of the input signal will be synchronized with the input signal having its phase equal to 180 degrees in any event. The output signal of the oscillator 25 will be at a phase of 90 degrees. Thus, a signal having its phase to equal to 0 degrees is supplied to the B-Y demodulator 31 through a minus ninety-degree phase shifter 33. A signal of 90 or 270 degrees is supplied to the R-Y demodulator 32 through the inverting circuit 28.

Claims: A chrominance signal processing circuit capable of demodulating both the SECAM and PAL types of chrominance signals, comprising: (A) a SECAM demodulating circuit (14) for demodulating a SECAM type chrominance signal; (B) a modulating circuit (19) for inserting a burst signal having an invariable phase into the SECAM demodulated signal from said SECAM demodulating circuit (14) and for amplitude-modulating two carriers supplied for each horizontal synchronizing signal period by using said SECAM demodulated signal, said carriers having their phases different from each other by 90 degrees; (C) a switch (20) for selectively outputting the amplitude-modulated signal from said modulating circuit (19) and an inputted PAL Type chrominance signal; (D) a delay circuit (29) for delaying the output signal from said switch (20) by one horizontal synchronizing signal period; (E) a discriminating circuit (21) for judging whether the inputted chrominance signal is of PAL or SECAM type; characterized by (F) a signal converting circuit (30) including a matrix section for receiving a first signal (301) from said switch (20) and a second signal (303) from said delay circuit (29) and a switch section for sequentially selecting one of said first and second signals for each horizontal synchronizing signal period to output B-Y and R-Y signal components individually to respective B-Y and R-Y demodulators (31, 32) in accordance with the judgement result of said discriminating circuit such that, in the case of a SECAM signal the two signals being input to the signal converting circuit are output unchanged, the B-Y and R-Y demodulators sequentially receiving said first and second signals during successive horizontal synchronizing periods, the B-Y demodulator (31) receiving said first signal (301) when the R-Y demodulator (32) receives said second signal (303) and vice versa, and in the case of a PAL signal the first and second signals (301, 303) are summed (37) and subtracted (38), the summed signal (310) being fed to said B-Y demodulator (31) and the subtracted signal (311) being fed to said R-Y demodulator (32). A chrominance signal processing circuit as defined in claim 1, further comprising an oscillator (25) adapted to oscillate in synchronism with the burst signal from said switch (20); an ID circuit (26) for discriminating the phase of the burst signal from said switch (20); and an inverting circuit (28) for sequentially inverting signals outputted from said oscillator (25) in response to the output signal of said ID circuit (26) and supplying, if said discriminating circuit (21) judges that the inputted chrominance signal is of PAL type, a signal having an invariable phase from said oscillator to said B-Y demodulating circuit (31) and said inverting circuit (28) is actuated so as to supply a signal having its phase inverted for each horizontal synchronizing signal period to said R-Y demodulating circuit (32) and if said discriminating circuit judges that the inputted chrominance signal is of SECAM type, the signal having an invariable phase is supplied to said B-Y and R-Y demodulating circuits (31, 32). A chrominance signal processing circuit as defined in claim 1 wherein the carriers used in said modulating means (19) to modulate the chrominance signal are of a phase of 0 degrees for said B-Y signal components and of 90 degrees for said R-Y signal components and wherein the phase of the burst signal inserted in said modulating means (19) is equal to 180 degrees. A chrominance signal processing circuit as defined in claim 1 wherein said oscillator (25) is adapted to output signals having substantially the same phase for both of the burst signals which are contained in the inputted chrominance signal and inserted in said modulating means (19).

Inventors: UEKI KEIJIRO, UEKI, KEIJIRO
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1992
Main classification: H04N9
IPC codes: H04N9, H04N11