BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS

Abstract: A bipolar transistor having an emitter (25), a base (31), and a collector (30) includes an intrinsic base (33) region having narrow side areas (p-) and a wider central area (37). The side areas are located adjacent to the extrinsic base region (31), while the central area (37) is disposed underneath the emitter (25). The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region (31) and the central area (37) are relatively high compared to the doping concentration of the narrow side areas (p-) of the intrinsic base (33). The combination of the narrow side areas (p-) and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Description: BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS HELP OF THE INVENTION The present invention relates to the field of bipolar junction transistor device structures. BACKGROUND OF THE INVENTION Modem high speed bipolar junction transistors (BJTs) are generally constrained by the competing concerns of high beta (i.e., forward current gain) and high base punch-through resistance. Punch-through refers to the effect wherein the neutral base width is reduced to zero at a sufficiently high collector-base voltage, V c _>- With the neutral base reduced to zero, the collector-base depletion region is in direct contact with the emitter-base depletion region. At this point, the collector is effectively short-circuited to the emitter, and a large current flows. The effects of beta and punch-through voltage are both coupled directly through the base charge, Qb- The total charge in the base region of a bipolar transistor is given by the product of the doping concentration, NA, and the base width, Wb. Lowering Qb raises beta but also lowers punch-through voltage at the same tim For the opposite condition, raising Qb lowers the beta that resulting in a higher punch through voltage. The trade-off between high beta and high punch-through resistance has been a fundamental feature of silicon bipolar junction transistors for many years. In the past, researchers have attempted to decouple the competing effects of beta and punch-through voltage by altering the band gap characteristics of the emitte the base, or both. Lowering the band gap at the base, for instance, by the use of silicon germanium (SiGe) alloys has produced favorable beta values with acceptable punch-through voltages. Alternatively, experiments in utilizing silicon carbide (SiC) alloys to raise the band gap of the emitter region have also produced favorable results. Considerable work is being done today in the technical community to further increase the performance of these "band gap engineered" structures. While efforts to engineer the band gap of the emitters and base regions have produced impressive results, these results have not come without certain costs. One of the primary drawbacks of using alloy semiconductors such as silicon germanium or silicon carbide is that forming such alloys generally require the use of exotic processing equipment. Typically, heterojunction epitaxial layers are grown using a technique known as molecular beam epitaxy (MBE). In this method the substrate is held in a high vacuum while molecular or atomic beams of the constituent atoms impinge upon its surface. The main problem with MBE machines, however, is that they are characterized by extremely slow growth rates (approximately 1 micron/hr.) and are very expensive and very difficult to operate in a manufacturing environment. Moreover, techniques such as MBE for forming heterojunction alloys are generally not compatible with modern processing requirements and structures, (e.g., BiCMOS processes), in light of these limitations, advanced epitaxfal growth techniques like MBE have been limited to research facilities or to specific applications (e.g., microwave amplification devices) where the level of integration is severely limited and the manufacturing volumes are likewise small. Thus, the goal of simultaneously achieving high beta and high punch- through voltage in a bipolar transistor manufactured using conventional silicon processing equipment and techniques has not yet been accomplished. As will be seen, the present invention provides a solution to the problem of achieving high beta and simultaneously high punch-through voltage in a homojunction bipolar device. Furthermore, according to the present invention, the novel device structure is easily fabricated using standard silicon processing equipment and lithographic techniques. Moreover, the invention is well-suited to a large volume, high production semiconductor manufacturing environment. SUMMARY OF THE INVENTION A homojunction bipolar transistor comprising emitter, base and collector regions is described. In one embodiment, the base region includes an extrinsic region disposed laterally about the emitter, and an intrinsic region which vertically separates the emitter from the collector. The intrinsic region further includes a side area adjacent to the extrinsic region, and a central area disposed generally beneath the emitter, importantly, the lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the side area of the intrinsic base. In accordance with the present invention, the side areas are purposefully made narrow such that the lateral doping profile across the base constrains the depletion region formed within the side areas. Reducing the extension of the collector depletion region into the base has the salutary effect of raising the punch-through voltage of the transistor without adversely affecting beta. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and wherein: Figure 1 illustrates a depletion layer width as a function of doping for a simpl one-dimensional theory. Figure 2A illustrates the expected result according to a one-dimensional theory conjoining a heavily doped sample with a lightly doped semiconductor sample Figure 2B illustrates the actual result achieved and predicted by a two- dimensional theory conjoining a lightly doped and more heavily doped semiconducto materials. Figure 3A illustrates a thin, lightly doped PN junction sandwiched between two heavily doped PN junctions for simply one-dimensional theory. Figure 3B illustrates the result predicted for the structure Figure 3A under a two-dimensional theory. Figure 3C shows the depletion region for a tree layer semiconductor structur having high-low-high lateral doping profile in the p-type material. Note that the depletion layers are illustrated for two-dimensional theory in Figure 3C. Figure 4A illustrates a cross sectional elevation view of a conventional bipola junction transistor structure. Figure 4B illustrates the lateral doping profile of the transistor Figure 4A as taken through pipelines A-A'. Figure 4C illustrates the collector and emitter depletion region generated within the prior art bipolar transistor of Figure 4A. Figure 5A illustrates a cross sectional elevation view of the present invention. Figure 5B is a plot of the lateral doping concentration in the base region of th structure of Figure 5A as taken through cut lines B-B'. Figure 5C illustrates the collector and emitter depletion regions for the presen invention. Figures 6A-6D are cross sectional elevation views illustrating one method of fabricating the device structure of Figure 5A. DETAILED DESCRIPTION In the following description, a novel bipolar junction transistor device structure is disclosed wherein numerous specific details are set forth, such as specific doping levels, processing steps, dimensions, etc., in order to provide a thorough understanding of the present invention. It will obvious, however, to one skilled in the art that these specific details may not be used to practice the present invention. In other instances, well known structures and processing techniques have not been shown in detail in order to avoid unnecessarily obscuring the present invention. In order to better understand the mechanism of the present invention, a brief discussion of basic semiconductor physics is helpful. Referring to Figure 1, the effect of doping concentration on the width of a depletion region, Wd, formed on either side of a PN junction is shown. Figure 1 illustrates a heavily-doped junction having p+ an n+ regions, a medium-doped junction, and a lightly-doped junction having p- and n- materials. As is clearly seen, the width Wd increases with decreasing doping. Figure 2A illustrates the effect of joining a heavily-doped sample to a lightly- doped sample according to simple, one-dimensional semiconductor theory. One- dimensional transistor theory has been used in the past to predict the general behavior of standard bipolar transistors. Note that the one-dimensional physical theory predicts a discontinuity in the depletion layer width at the junction between the two differently doped material. A more accurate, two-dimensional theory is needed t accurately predict the shape of the depletion layer width in the narrow interface regio between the two differently doped samples. In Figure 2B, the actual junction betwee the lightly-doped and heavily-doped materials is shown by a finite transition region 11 A slightly more complex case is illustrated in Figures 3A-3C. Here, a thin, lightly-doped PN junction is shown sandwiched between two wider, more heavily- doped PN junctions. The heavily-doped samples are shown by regions 13 and 15, while the thin, lightly-doped sample is shown as region 14. As before, the one- dimensional theory is incapable of accounting for the change in depletion layer width which occurs at the transition regions between the lightly-doped and more heavily-doped samples. The two-dimensional result, however, of Figure 3B illustrates an important new effect. Note that in Figure 3B the depletion layer width in the lightly-doped sample 14 does not extend as far into the p- and n- regions as predicted by the one-dimensional theory. It is determined that if the thickness of region 14 is small enough (e.g., on the order of about 0.1 microns wide) the depletion region in this narrow sample will be constrained from extending to the full one-dimensional width. The amount that the depletion region is reduced is illustrated as ΔWd in Figure 3B. The phenomena whereby the depletion width is constrained in a thin, narrow, lightly-doped sample surrounded by wider, more heavily-doped samples, is a key concept of the present invention. Note that this effect is not limited to the particular structure shown in Figure 3B. The same effect can be achieved utilizing a thin, sample wherein only one side of the PN junction is lightly-doped. This situation is shown in Figure 3C. in Figure 3C, one side of the PN junction in region 14 is heavily doped (e.g., n+), while the other side is lightly-doped (e.g., p-). In other words, the acceptor side of the junction has a lateral profile which changes abruptly in central region 14. In the structure of Figure 3C, the depletion region on the donor (n-type) side of the junction is minimally affected since the doping concentration is largely uniform across regions 13, 14 and 15. On the other hand, depletion region on acceptor (p- type) side varies across region 14. The significance of all of this is that by constructing a similar p+/p-/p+ lateral doping profile in the base of a bipolar junction transistor, it is possible to reduce punch-through in a thin, lightly-doped base region, while simultaneously maintaining high beta. That is, the crux of the present invention invoives tailoring the lateral doping profile across the base region to accomplish the previously unattainable goal of high beta and high punch-through voltage in a, high- performance, homojunction bipolar transistor. With reference now to Figure 4A, a cross-sectional elevation view of a prior ar bipolar transistor is shown. The transistor of Figure 4A includes a collector region 20 formed in a semiconductor substrate. The collector region is typically doped heavily N-type. Directly above the n+ collector region is a base region comprising extrinsic base regions 21 and intrinsic base region 23. The extrinsic regions are heavily-dop with p-type dopant to lower the base resistance of the device. In contrast, the intrinsi base region 23 (located directly beneath n+ emitter 25) is lightly-doped to provide high forward current gain. The fundamental operating principles of the bipolar transistor of Figure 4A are well understood and therefore will not be discussed in detail in this application. Figure 4B is a plot of the doping concentration N A across the lateral dimension of the transistor of Figure 4A through the base region. Line 26 represents the lateral doping profile as taken through cut lines A-A 1 . Note that the different doping concentration of the intrinsic versus the extrinsic base regions is reflected in the relatively lower doping concentration level within intrinsic base region 23. Figure 4C illustrates the bipolar junction transistor of Figure 4A including dash lines 28 and 29 which represent the extent of the emitter and collector depletion regions, respectively, into base regions 21 and 23. Note that the extension of these depletion regions into the base region 23 leaves only a narrow undepleted intrinsic base area 30. Although a narrow base is desirable for purposes of providing high beta and high speed, any increase in the collector-base voltage will cause depletion region 29 to further extend into base region 23 until it eventually meets depletion region 28. Thus, the penalty for having the high beta BJT shown in Figure 4A-4C, is that the punch-through voltage is unfavorably low. On the other hand, widening the undepleted base area 30 or increasing its doping raises punch-through voltage but only at the expense of lower beta and slower speed. The device structure of the present invention is illustrated in Figures 5A-5C. The most notable difference between the present invention and the prior art structure is the presence of a heavily-doped central intrinsic base region 37. Central base region 37 is separated from the extrinsic base 31 by a relatively lightly-doped intrinsic base region 33. Intrinsic base region 33 and central base region 37 are both disposed generally beneath emitter 25. At the same time, extrinsic base region 31, intrinsic base region 33 and central base region 37 are all disposed above collector region 30. In the currently preferred embodiment, emitter region 25 is on the order of 0.2 to 0.3 microns wide, and is formed to a depth of about 0.05 microns. The nominal base width is about 0.1 microns. Extrinsic p+ base regions 31 are again included to reduce base resistance. Regions 31 are typically formed by diffusion of dopants into the silicon substrate. In the current embodiment, p+ extrinsic base regions 31 are ion implanted to a concentration of approximately 3.0 x 10 15 atoms/cm 2 . The intrinsic base region 33 is also typically formed by ion implantation through a masking layer. Preferably, base region 33 is implanted to a concentration of approximately 5.0 x 10 13 atoms/cm 2 . A primary characteristic of the present invention is that the lateral doping profile across the base region is highly altered as compared to the standard BJT. Preferably, the dose (and hence the total charge Qb) in the intrinsic base is reduced to about five times less than normal. A second base implant step is then performed through a masking layer positioned over the center of intrinsic base region 33 to produce the localized, heavily-doped p+ region 37. Note that the implant for region 37 is normally performed prior to formation of emitter 35. In the currently preferred embodiment, the masking layer used to form emitter 35 is also be for implantation of region 37. Localized p+ region 37 is preferably doped to about twice the standard intrinsi base charge level. After implantation of region 37, the device may optionally be subjected to an annealing cycle prior to implantation or diffusion of emitter 35. It is appreciated that there are numerous ways of fabricating the structure Figure 5A, the present invention may be realized employing a wide range of fabrication and processing techniques. Therefore, the present invention is not limited to the particula embodiments described. The essential feature illustrated in Figure 5A is that including of central region 37 to radically alter the lateral doping profile of the base region. Specifically, inclusio of region 37 creates very narrow spaces of lightly-doped intrinsic base regions while are surrounded by more heavily-doped extrinsic and central base regions. This basi structural improvement improves the punch-through voltage characteristics without adversely affecting beta. Figure 5B shows lateral doping profile for the transistor structure of Figure 5A. Note that the doping concentration is significantly lower in the narrow spaces (p-) 39 which separate extrinsic base regions (p+) 31 from central base region (p+) 37. In central region 37, the doping concentration is indicated by line 38 and is shown to be much higher than that of intrinsic base regions 33. Although in the currently preferre embodiment, the doping concentration in region 37 is slightly less than that associated with extrinsic base regions 31, they may be doped to the same order of magnitude. Because of the close spacing of the two P+ regions in the lateral base dimension, the situation shown in Figures 5A-C is akin to that represented in Figure 3C. That is, because of the narrow spacing, the collector-base depletion region does not extend as far into the p- intrinsic base region 33 as it normally would given the relative doping concentrations. In other words, the depletion region is constrained by the high/low/high lateral doping profile of the base. Therefore is not allowed to reach full extension. This depletion condition is illustrated in Figure 5C where the collector- base depletion region is shown by dash line 41, and the emitter-base depletion region is illustrated by dash line 40. Note that because the collector-base depletion region is constrained by the sandwiched doping profile, the undepfeted base area 42 is significantly wider than in conventional homojunction bipolar structures. The structure of Figures 5A-5C basically utilizes the more heavily-doped central base region to effectively "pull" the collector depletion region back-analogous to the drawing of Figure 3C. The invented transistor structure is now dominated by the narrow lightly- doped base regions near the edges of the emitter, i.e., spaces 39. Due to the effect of the nearby p+ regions on either side of spaces 39, the punch-through current is greatly reduced. Due to the lighter doping in the small emitter-base spaces 39, the barrier height of the pn junction is reduced in this area relative to regions 37 and 31. The forward beta is then dominated by these small, lightly-doped regions and is significantly increased. It should be understood that constraining the depletion region in the manner described above is unrelated to the classical emitter edge effect caused by a voltage drop induced by the flow of base current laterally to the high resistance pinched base. Rather, the dramatic reductions in punch-through current and simultaneous increase in beta are confirmed to be the result of limiting the extension of the collector-base depletion region by means of a heavily-doped/slightly-doped/heavily-doped laterally based profile under the emitter. In the currently preferred embodiment, this spacing is extremely small - on the order of about 0.05 microns wide. Additionally, because of the overall increase in gain, the maximum operating frequency (e.g., Ft ) is also significantly improved. By way of example, a modern, state-of-the-art silicon homojunction bipolar transistor commonly has a maximum beta of about 100 for punch-through currents of approximately 1 nanoampere for a 3 volts collector voltage. A typical Ft for this device is on the order of 40 GHz. In contrast, a device fabricated in accordance with the present invention exhibits a beta of approximately 500 ; a punch-through current of about 1 picoampere at 3 volts, and an Ft of nearly 55 GHz. Moreover, base resistance and base-collector capacitance is about the same as in previous structures. Because of the smaller potential barrier in lightly-doped regions where the majority of emitter current is injected under forward bias, the turn-on voltage, i.e., Vbe. of the invented bipolar transistor is also slightly decreased. Another significant advantage of the present invention is that the bipolar transistor of Figure 5A-5C is able to perform equally well with 5 volts on the collector. At 5 volts, across the collector emitter, the Ft of the device rises to about 60 GHz with punch-through current of only 1 nanoampere. The frequency characteristics of the transistor can be further improved by the addition of a narrow spike in the buried laye directly under the emitter. This provides a means of reducing collector transit time without significantly increasing the base-collector capacitance. Besides improving the performance of existing bipolar transistors, the present invention promises to significantly extend the scaleabiiity of future BJTs. Using this technique, for example, a transistor can be scaled much more aggressively without having to reduce power supply voltage accordingly. Thus, the present invention facilitates compatibility with standard supply voltages while maintaining system cost as low as possible. Although the present invention embodies the concept of controlling depletion regions to specifically improve the performance of a high speed bipolar transistor, thi technique may also be applied more generally to other applications. In other words, the formation of narrow, lightly-doped spaces surrounded by more heavily-doped areas which reduced the extent of the associated depletion region in the lightly-dope area will no doubt prove useful in other semiconductor device structures. For example, the same concept may be used to improve the performance of pnp devices in a structure similar to that described, but with the conductivity types reversed. In either case, however, it is worth noting that the spacings should to be on the order of 0.10 microns (or smaller) wide to provide effective reduction in the extent of the depletion width. in addition, the specific technique of forming a base doping profile that is tailored in the manner described above, represents only one of many processing methods which may be used. Other embodiments might form lightly-doped narrow spaces surrounded by a more heavily-doped areas by means of small holes or slots disposed in a continuous sheet of more heavily-doped material. Such alternatives are considered to be well within the spirit and scope of the present invention. Figures 6A-6D illustrate one alternative method of fabricating the structure of the present invention. For example, Figure 6A illustrates a collector region 30 formed using conventional processing techniques. A heavily-doped p+ region 46 is formed directly above collector region 30. Region 46 is typically formed by diffusion or ion implantation. A masking layer 48 is then patterned to form an opening over the heavily-doped p-type region 46. (An example of a refractory masking layer which may used for layer 48 is silicon dioxide). Following the pattering of masking layer 48, a compensating dopant is then introduced into the substrate to form a lightly-doped p- region 51. This is indicated in Figure 6B by arrows 50. Of course, the compensating dopant may be introduced either by diffusion or by ion implantation. The dopant is then diffused laterally to form a compensated region 51 that is slightly larger than the opening of masking layer 48. Alternatively, the compensating dopant may be ion implanted at an angle, or lateral implant scattering may be relied upon to produce the slightly larger lateral dimension of region 51. Without removing refractory masking layer 48, an additional dopant is then implanted or diffused into the silicon substrate. This is shown in Figure 6C by arrows 51. Typically, the dopant used to form region 46 would be the same as used to form region 52. That is, the doping concentrations in regions 52 and 46 are nearly the same. It is important, however, that the lateral diffusion or extent of region 52 be less than that associated with region 51. This ensures that narrow, lightly-doped regions 51 will be formed around the periphery of region 52. It is appreciated that region 52 forms the highly-doped central intrinsic base region for the BJT. Following the completion of the base region, masking layer 48 is removed and emitter 55 is formed using conventional photolithographic techniques. Practitioners i the art will appreciate that the above method has certain advantages over the earlier described process in that it relies upon very controllable diffusion or implant processes to form the small required spaces 51. Although the present invention has been described in conjunction with certain embodiments, it is appreciated that the invention may be implemented in a variety of other ways. For instance, a pnp transistor having similar improved characteristics could be realized in accordance with the present invention by reversing the p-type and n-type regions. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to b considered limiting. References to the details of these embodiments is not intended t limit the scope of the claims which themselves recite only those features regarded as essential to the invention.

Claims: CLAIMS I claim: 1. A bipolar transistor comprising: an emitter of a first conductivity type; a collector of said first conductivity type; a base of a second conductivity type having an extrinsic region disposed laterally about said emitter and an intrinsic region which vertically separates said emitter from said collector; said intrinsic region having a side area adjacent to said extrinsic region and a central area disposed generally beneath said emitter, the lateral doping profile of said base being such that the doping concentrations in said extrinsic region and said central area are relatively high compared to the doping concentration of said side area of said intrinsic base, 2. The transistor of claim 1 wherein said first conductivity type is n-type and said second conductivity type is p-type. 3. The transistor of claim 1 wherein said first conductivity type is p-type and said second conductivity type is n-type. 4. The transistor of either claim 2 or 3 wherein said side area is sufficiently narrow to constrain the depletion region formed therein so as to raise the punch-through voltage of said transistor. 5. The transistor of claim 4 wherein said side areas are approximately 0.05 microns wide. 6. The transistor of claim 5 wherein said doping concentrations in said extrinsic region and said central area are on the order of 1 x 10 18 atoms/cm 3 . 7. The transistor of claim 6 wherein the doping concentration of said said 16 3 area of said intrinsic base is on the order of 1 x 10 atoms/cm . 8. A bipolar junction transistor (BJT) formed in a semiconductor substrate comprising: a collector region of a first conductivity type; a emitter region of said first conductivity type; an extrinsic base region of a second conductivity type heavily-doped to a first concentration level, said extrinsic base region being generally disposed laterally about said emitter region; an intrinsic base region of said second conductivity type generally disposed beneath said emitter region and above said collector region, said intrinsic base regi having a second doping concentration level in the side areas adjacent to said extrinsic base region and a third doping concentration level in the central area direct beneath said emitter region, said second doping level being substantially lower than said first doping level with said third doping level being higher than said second doping level. 9. The BJT of claim 8 wherein said first conductivity type is n-type and sai second conductivity type is p-type. 10. The BJT of claim 8 wherein said first conductivity type is p-type and sai second conductivity type is n-type. 11. The BJT of either claim 9 or 10 wherein said side areas of said intrinsic base region are sufficiently narrow to constrain the depletion region within said side areas such that punch-through current is reduced. 12. The BJT of claim 8 wherein said side areas are approximately 0.05 microns wide. 13. The BJT of claim 12 wherein said first and third doping concentration levels are on the order of 1 x 10 atoms/cm . 14. The BJT of claim 10 wherein said second doping concentration level is 18 3 on the order of 1 x 10 atoms/cm . 15. A bipolar junction transistor (BJT) comprising: an emitter of a first conductivity type; a base of a second conductivity type forming a pn junction with said emitter; a collector of said first conductivity type forming a pn junction with said base; said base including a doping means for constraining the extension of the base- collector depletion region into said base thereby increasing the punch-through voltage of said transistor. 16. The BJT of claim 15 wherein said first conductivity type is n-type and said second conductivity type is p-type. 17. The BJT of claim 15 wherein said first conductivity type is p-type and said second conductivity type is n-type. 18. The BJT of either claim 16 or 17 wherein said doping means comprises a lightly-doped space confined between a pair of more heavily-doped areas. 19. The BJT of claim 18 wherein said space is in the order of about 0.05 microns wide. 20. The BJT of claim 19 wherein said space is generally disposed about the periphery of said emitter. 21. A method of fabricating a bipolar junction transistor in a silicon substrate comprising the steps of: forming a collector region in said substrate; forming extrinsic and intrinsic base regions, said extrinsic region being more heavily doped than said intrinsic region; introducing a dopant into said intrinsic region to form a heavily doped central area separated from said extrinsic region by a more lightly doped side area; forming an emitter region disposed generally above said central area of said intrinsic base region and being surrounded laterally by said extrinsic base region. 22. The method of claim 21 wherein said side area is approximately 0.05 microns wide. 23. The method of claim 21 wherein said introducing step comprises the steps of: forming an opening in a masking layer over said intrinsic region; and implanting a p-type dopant into said intrinsic region. 24. The method of claim 23 wherein said step of forming said emitter region comprises the step of implanting an n-type dopant through said opening. 25. The method of claim 24 wherein said step of forming said emitter region comprises the step of diffusing an n-type dopant through said opening. 26. A method of fabricating a bipolar junction transistor exhibiting improved beta and punch-through characteristics comprising the steps of: providing a substrate; forming a collector region in said substrate; heavily doping a base region disposed above said collector region utilizing a first dopant; patterning a masking layer to provide an opening over said base region; introducing a compensating dopant into said base region through said opening; introducing a second dopant into said base region, the lateral diffusion of said second dopant being less than the lateral diffusion of said compensating dopant so as to form relatively lightly-doped areas surrounded by more heavily-doped areas within said base region; forming an emitter region over said base region, said emitter region extending laterally at least as far as said lightly-doped areas. 27. The method of claim 26 wherein said first and second dopants are a p- type, and wherein said compensating dopant is n-type. 28. The method of claim 27 wherein said patterning step comprises the steps of: depositing a refractory masking layer over said substrate; and patterning said masking layer to form said opening. 29. The method of claim 28 wherein said refractory masking layer comprises silicon dioxide. 30. The method of claim 29 wherein said second dopant is introduced into said base region through said opening. 31. The method of claim 30 wherein said compensating dopant is introduced into said base region by ion implantation. 32. The method of claim 31 wherein said emitter region is formed by a diffusion through another masking layer.

Inventors: MATTHEWS JAMES A, MATTHEWS, JAMES, A.
Applicants: MICROUNITY SYSTEMS ENG, MICROUNITY SYSTEMS ENGINEERING, INC.
Application year: 1992
Main classification: H01L23
IPC codes: H01L21, H01L29