Picture quality improving apparatus for compensating contour of images

Abstract: The present invention relates to an improved image improvement apparatus which can be applied to video apparatus and to various other types of image processing apparatus. This invention has as an object the emphasis of the edge directly adding a waveform step difference to a middle position of a waveform change portion of an envelope of color signals in the form where they have been amplitude modulated, and therefore provides an apparatus which prevents unnatural contour compensation, improves color saturation phenomenon without giving an unnatural sensation to the viewer, facilitates the use of digital circuits and for which adjustment of the edge effect is possible. The control signals (Sc) are obtained by control signal generating circuit (6) and subtracter (3-5) which use the input signal (S1), output signal (S2) of a delay circuit (1), and output signal (S3) of a delay circuit (2). The output signals (S11, S33) of a composite circuit (7) are supplied to a signal selection circuit (8) along with said signals S2. The signal selector circuit 8 selects and outputs one of the three supplied signals (S11, S33 and S2) in accordance with a control signal (SC), and obtains an output signal (So) for which the edge has been emphasized. The input signal (S1), and each of the output signals (S2, S3, S4 and S5) of the delay circuit (1-4) are supplied to a signal selection circuit (13). The control signal generating circuit (12) and the subtracter (5-11) use the signals (S1 through S5) to obtain the control signal (Sc). The signal selection circuit (13) selects and outputs one of the supplied five signals (S1 through S5) in accordance with the control signal (Sc) and obtains an output signal (So) for which the edge has been emphasized.

Description: The present invention relates to picture quality improving apparatus applicable to various video devices and apparatus such as television (TV) image receiving apparatus, video tape recorders (VTR) and the like, and various image processing apparatus handling image data and the like. More particularly, the present invention relates to picture quality improving apparatus applicable to digital circuits and capable of improving a distinction and a resolution of represented images by means of an improvement of a color blur phenomenon. The improvement is performed by stressing an envelope edge of chrominance signal whose amplitude is modulated in the manner that a person watching a picture feels an intact picture without a sense of incongruity. There has been conventionally performed contour compensation used for improving a picture quality in which a contour compensation component is obtained by a quadratic differential calculation to add the proper quantity of the component to an original signal. In contour compensation by the above method, a quadratic differential waveform as a contour compensation component has peak which is considerably outside a midpoint of a change portion (edge portion) of a waveform of the original signal. Accordingly, when the quadratic differential waveform is added to the original signal, it is possible to generate a preshoot and an overshoot so as not to obtain a picture improving effect at a desired degree. Furthermore, it is possible to perform artificial contour compensation in that an edging of other colors such as white and black occurs at edges of the reproduced picture. GB-A-2213022 discloses a similar picture quality improving apparatus to the present invention, which considers the absolute values of the differential signals for choosing between the 3 outputted alternative delayed signals. SUMMARY OF THE INVENTION An object of the present invention is to provide a picture improving apparatus applicable to a digital circuits and capable of improving a distinction and a resolution of represented images by means of an improvement of a color blur phenomenon, and the improvement is performed by stressing an envelope edge chrominance signals of which an amplitude is modulated in the manner that a person watching a picture feels an intact picture without a sense of incongruity. In order to achieve the above object, image improvement apparatus according to the present invention includes: when input signals which are amplitude modulated by a modulating wave are first signals; a delay circuit which outputs second signals which are said first signals which have been time delayed by an integral multiple of a cycle of said modulation wave, and third signals which are said second signals which have been time delayed by said positive integral multiple; a first subtractor which subtracts said second signals from said first signals and outputs fourth signals; a second substractor which subtracts said second signals from said first signals and outputs fourth signals, a third subtractor which substracts said fifth signals from said fourth signals and outputs sixth signals, a control signal generating circuit which is supplied with said fourth, fifth and sixth signals and outputs a seventh signal which is a control signal for which the value changes in accordance with combinations of said fourth, fifth and sixth signals, a composite circuit supplied with said first, second and third signals and which combines said first signals and said second signals and outputsan eighth signal and combines said second and third signal and outputs a ninth signal, and a signal selection circuit supplied with said eighth, second, ninth and seventh signals, and which selects and outputs one of said eighth, second and ninth signals in accordance with said seventh signal which is a control signals, said control signal generating circuit is arranged to output a control signal instructing said signal selection circuit to select and output (a) said ninth signal when values of said fourth and fifth signals are both larger than a first positive constant, and a value of said sixth signal is simultaneously larger than a second positive constant, or when values of said fourth and fifth signals are both smaller than a first negative constant, and a value of said sixth signal is simultaneously smaller than a second negative constant, and (b) said eighth signal when values of said fourth and fifth signals are both larger than a first positive constant, and a value of said sixth signals is simultaneously smaller than a second negative constant, or when values of said fourth and fifth signals are both smaller than a first negative constant, and a value of said sixth signal is larger than a second positive constant, and (c) said second signal when a combination of the three signals of said fourth, fifth and sixth signals is other than a combination of (a) and (b). The present invention is also characterised by the features of independent claims 3,5 and 6. As described above, the picture quality improving apparatus of this invention has several effects as follows: (i) because the delay time of the delay circuit is set as a positive and integral number times of the cycle of the modulated wave, or as odd number times of 1/2 cycle of the modulated wave, and the edge stressing is performed by properly adding the waveform step to the midpoint of a slant portion of the envelope of the input signal which is modulated in amplitude (namely, the signal before modulated in amplitude), thereby obtaining an output signal in which frequency components are added without the frequency band of the input signal, it is possible to reduce color blur in the reproduced picture images and to stress the contour of the images; (ii) the edge stressing is not performed over the amplitude of the original signal such as in conventional contour compensation, namely preshoot or overshoot, and is performed in the amplitude of the original signal. Accordingly, even though the apparatus and devices having this picture quality improving apparatus is formed by digital devices, there are no problem such as overflow, thereby performing good picture improvement by these apparatus and devices; (iii) because degrees of edge stressing to the input signal depend on a frequency including the input signal and have an intimate correlation, the picture quality improving apparatus can improve a distinction and resolution and does not give a person watching the reproduced picture a sense of incongruity; (iv) even though the composite ratio is regulated between the delay time of the delay circuit and the composite circuit, it is possible to regulate an edge stressing quantity, thereby a person watching the picture can set the picture quantity to the desired quantity, namely optimum edge stressing quantity coincident to his liking with watching a signal waveform and reproduced picture; (v) since the each component in the picture quality improving apparatus is realized by a simple circuitry of general articles on the market such as integrated circuits (IC), it is possible to easily manufacture the entire apparatus in lower cost. Furthermore, since the picture quality improving apparatus has a wide usage, the apparatus is useful in various industries; and (vi) when the constants α and β are set for eliminating noise components in the control signal generating circuit, the picture quality improving apparatus can obtain more perfect control signal Sc which is not influenced by the noise components, thereby performing more precise edge stressing. Furthermore, the picture quality improving apparatus of the present invention as one aspect, has effects as follows: (vii) an edge stressing is performed by adding a proper waveform step to a midpoint of a slant portion of the waveform of the input signal. As a result, it is possible to obtain the output signal added frequency components outside the frequency band of the input signal. Furthermore, since the pseudo-contour such as a preshoot and overshoot is not added to the output signal, it is possible to perform a precise contour compensation without a sense of incongruity; (viii) this apparatus performs edge stressing within an amplitude of the original signal and does not perform the edge stressing over the amplitude of the original signal, such as preshoot and overshoot in the conventional contour compensation. Accordingly, when this apparatus is disposed in the digital apparatus and devices, the problem of overflow does not occur, and the apparatus and devices can perform extreme picture quality improvement; (ix) since the degree of edge stressing to the input signal depend on the frequency including in the input signal and have a perfect correlation with the input signal, the picture quality improving apparatus does not give a sense of incongruity to a person watching the reproduced picture, and it is possible to improve a distinction and resolution; (x) if the number of the delay circuits is regulated, it is possible to control the edge stressing quantity, so that a person watching the picture can set the optimum edge stressing quantity coincident to his liking, namely his desired picture quality; and (xi) each component of the picture quality improving apparatus is realized by a simple circuitry of general articles on the market such as integrated circuits (IC), it is possible to easily manufacture the entire apparatus in lower cost. Furthermore, since the picture quality improving apparatus has a wide usage, the apparatus is useful in various industries. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is a block diagram showing a schematic configuration of a picture quality improving apparatus according to a first embodiment of the present invention; FIGS. 2(a) to 2(p) are characteristic diagrams for respectively explaining operation of the picture quality improving apparatus shown in FIG. 1; FIG. 3 is a circuit diagram showing a control signal generating circuit in the apparatus shown in FIG. 1; FIGS. 4(a) to 4(e) are circuit diagrams respectively showing a specific example of a composite circuit in the apparatus shown in FIG. 1; FIGS. 5A and 5B are circuit diagram each showing a specific example of a signal selection circuit of the apparatus shown in FIG. 1; FIG. 6 is a block diagram showing a schematic configuration of a picture quality improving apparatus according to a second embodiment of the present invention; FIG. 7 is a characteristic diagram showing a waveform of a chrominance signal of the apparatus shown in FIG. 6; FIG. 8 is a block diagram showing a schematic configuration of a picture quality improving apparatus according to a third embodiment of the present invention; FIGS. 9(a) to 9(r) are characteristic diagrams respectively showing signal timings of each portion of the apparatus shown in FIG. 8; FIG. 10 is a circuit diagram showing a specific example of a control signal generating circuit in the apparatus shown in FIG. 8; FIGS. 11A and 11B are circuit diagrams each showing a specific example of a signal selection circuit of the apparatus shown in FIG. 8; FIG. 12 is a block diagram showing a schematic configuration of a picture quality improving apparatus according to a fourth embodiment of the present invention; and FIGS. 13(a) to 13(z) are characteristic diagrams respectively showing signal timings of each portion of the apparatus shown in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The followings are the description of the preferred embodiments of this invention. At first, there is described a picture quality improving apparatus according to a first embodiment of this invention with reference to FIG. 1. In FIG. 1, numerals 1 and 2 denote delay circuits having the same delay time, respectively, 3 to 5 subtracters, 6 a control signal generating circuit, 7 a composite circuit, and a a signal selection circuit. For the sake of convenience in a description, there is omitted a signal delay which is caused by own processing time of each circuit of itself and a delay circuit or the like which is used only for compensating the signal delay. Furthermore, an input signal dealt in this picture quality improving apparatus is supposed as the signal that is a signal modulated in amplitude such as a chrominance signal in television signals and the like. It is supposed that there is supplied an input signal S1 as a chrominance signal of the television signals shown in FIG. 2(a) through a line L1. The signal S1 has a waveform resulting from suppressed-carrier amplitude modulation of a chrominance subcarrier wave (a frequency fsc of the chrominance subcarrier wave is about 3.58 MHz in NTSC system), a phase in a section A is , and a phase in a section B is  + π. In a boundary of the sections A and B , an amplitude is small because there is duplication of both the sections A and B . The input (chrominance) signal S1 has an I signal which is limited in 1.5 MHz band and a Q signal which is limited in 0.5 mHz band in a base band system before modulated. The input signal S1 is supplied to the delay circuit 1 having a delay time T which is obtained by an equation (1) as follows: T = l/fsc where fsc is about 3.58 MHz. A value of the delay time T corresponds to one cycle or period of the chrominance subcarrier wave. T = m/fsc where m is 1, 2, 3 ... an integral value. Even though the delay time T can extend to the value obtained by an equation (2) in the first embodiment, the delay time T obtained by the equation (1) is first described. The delay circuit 1 outputs a signal S2 which delays in time T and is shown in FIG. 2(b). The delay circuit 2 of the next step has the same function as the delay circuit 1, and outputs a signal S3 which further delays time T from the signal S2 and is shown in FIG. 2(c). The subtracter 3 subtracts the signal S2 of the delay circuit 1 from the input signal S1 to generate and output a signal S4 obtained by an equation (3) as follows: S4 = S1 - S2 The subtracter 4 has the same function as the subtracter 3 and subtracts the signal S3 of the delay circuit 2 from the signal S2 of the delay circuit 1 to generate and output a signal S5 obtained by an equation (4) as follows: S5 = S2 - S3 The subtracter 5 also has the same function as the subtracter 3 and subtracts the signal S5 of the subtracter 4 from the signal S4 of the subtracter 3 to generate and output a signal S6 obtained by an equation (5) as follows: S6 = S4 - S5 The signals S4, S5 and S6 have waveforms which are respectively shown in FIGS. 2(d), 2(e) and 2(f). The characteristics of these waveforms are to obtain a significant value in the waveform change portion in the envelope of the chrominance signal. The frequency characteristics of the subtracters 3 to 5 are differential features G1 of the sine wave amplitude obtained by an equation (6) are as follows: G1 = -j2sin (πf/fsc) Assuming the signal S2 as a time reference, the signal S4 is advanced by the time T/2, the signal S5 is retarded by the time T/2, and the signal S6 has no time difference. The signal S6 is explained by S1, S2 and S3 after the equations (3) and (4) are substituted for the equation (5). The frequency characteristics G2 of the signal S6 are obtained by an equation (7) as follows: G2 = 2 (cos(2πf/fsc) - 1) Accordingly, the delay circuit 1 and 2 and the subtracters 3 to 5 function as a comb filter of the same phase. Anyway, since a subtracting operation between the signals is performed by using the time difference which is equal to the period T of the chrominance subcarrier wave, the same time difference T, the operation is to obtain a difference between the signals having the same polarity. This corresponds to obtain the change of the envelope of the chrominance signal. The signal S4, S5 and S6 of the subtracters 3, 4 and 5 are supplied to the control signal generating circuit 6 of the next step. The circuit 6 generates a control signal Sc corresponding to the combinations of values of the signals S4, S5 and S6. The control signal Sc is a logic signal comprised of signals Sc1, Sc2 and Sc3 which are shown in an equation (8) as follows: As described above, the conditions are as follows: (i) when the signals S4, S5, and S6 are all positive or negative polarity as the same each other, the signal Sc3 is "0" (Low); (ii) when both the signals S4 and S5 are the same polarity of positive or negative each other, and the signal S6 has the polarity different from the signal S4 and S5, the signal Sc1 is "0" (Low); and (iii) when the combinations of the signals S4, S5 and S6 are different from the above conditions, the signal Sc2 is "0" (Low). FIG. 3 shows an example of circuit for realizing the control signal generating circuit 6. In FIG. 3, converters 61, 62 and 63 respectively convert the signals S4, S5 and S6 (which are digital signals having 8 bits that is a complement of 2) into "1" when the signals are positive and "-1" when negative, so as to output it as a 2 bit signal of representing a complement of 2. Tables 1(a), 1(b) and 1(c) show conversion tables of the respective converters 61, 62 and 63, and the signals S4, S5 and S6 are obtained by an equation (9) as follows: The converter 61, 62 and 63 are formed from a table look up system such by a TTL-IC (transistor-transistor-logic integration circuit) or a ROM (read only memory) and a PLA (programmable logic array). Output signals of three converters 61, 62 and 63 are respectively passed through AND circuits 64 to 68, OR circuits 71 and 72, and NAND circuits 73, 74 and 75 to be the control signals Sc1, Sc2 and Sc3 which are obtained by an equation (10): In FIG. 3, the signals Sc1, Sc2 and Sc3 are denoted as simple name, and in the equation (10) these signals are represented by logical equation of the low active (negative logic), namely adding bars, in order to clarify usage object. Since the signals S4, S5 and S6 are the output signals of the subtracters 3, 4 and 5, it is generally possible to include noise components of the high frequency wave. In order to improve performance of the control signal generating circuit 6 to the noise component, reference values for distributing the signals S4, S5 and 96 in the converters 61, 62 and 63 are not used as "0" as shown in Tables 1(a), 1(b) and 1(c), but are set as small positive constants α and β which distribute the signals S4, S5 and S6. The constants α and β are those of values corresponding to amplitudes of the noise component. Tables 2(a), 2(b) and 2(c) show conversion tables of the converters 61, 62 and 63 to which noise measures are taken, and a table 3 shows logic values and conditions of each signals: (LSB) S41 S40 S4 > α 0 1 |S4| ≤ α 0 0 S4 < -α 1 1 (LSB) S51 S50 S5 > α 0 1 |S5| ≤ α 0 0 S5 < -α 1 1 (LSB) S61 S60 S6 > α 0 1 |S6| ≤ α 0 0 S6 < -α 1 1 CONTROL SIGNAL LOGIC VALUE CONDITIONS Sc3 0 (Low) S4>α, S5>α, S6>β, or S4>-α, S5>-α, S6>-β 1 (High) Except the above condition Sc2 0 (Low) Both Sc1 & Sc3 are 1 (High) 1 (High) At least any one of Sc1 & Sc3 is 0 (Low) Sc1 0 (Low) S4>α, S5>α, S6>-β, or S4>-α, S5>-α, S6>β 1 (High) Except the above condition where α and β in Table 3 are small positive constants for removing a noise component. The constants α and β are values smaller than the signals S4, S5 and S6 and set for removing noise components. By this, there is eliminated noise components in which amplitude values in the signals S4 and S5 are less than α, and an amplitude value in the signal S6 is less than β. Accordingly, more precise control signal Sc can be obtained without an influence of noise components. It is no problem that the signal component is lost with the noise component if the lost component is limited under several % of the original signal. Here, the description returns FIG. 1 and the signals S1, S2 and S3 are supplied to the composite circuit 7 of the next step. In this section, the signals S1 and S3 are respectively converted into new signals S11 and S33 through a composite ratio k as the above equation (11). FIG. 4(a) shows a specific circuit for realizing the equation (11). In FIG. 4(a), blocks 3-1 and 3-2 denote amplifiers of a table look-up system which are comprised of a ROM, and a block 3-3 denotes an adder. The adder 3-3 composes the signal S11 (or S33) by adding the signal S2 supplied to the amplifier 3-2 and the signal S1 (or S3) supplied to the amplifier 3-1. The signals S11 and S33 outputted from the composite circuit 7, the signal from the delay circuit 1 and the control signal Sc (Sc1, Sc2 and Sc3) are supplied to the signal selection circuit 8 as the next step. The circuit 8 selects any one of the signals S11, S2 and S33 corresponding to the control signal Sc so as to output a signal So which is obtained by an equation (12) as follows: Namely, the signal selection circuit 8 selects and outputs the signal S11 when the control signal Sc1 is "0" (Low), the signal S2 when the control signal Sc2 is "0" (Low), and the signal S33 when the control signal Sc3 is "0" (Low). Fig. 5A shows a circuit example for realizing the signal selection circuit 8. In FIG. 5A, numerals 81 to 83 denote switch circuits which are respectively supplied the signals S11, S2 and S33. When any one of the control signals Sc1, Sc2 and Sc3 is "0" (Low), any one of the switch circuits 81 to 83 to which the control signal of "0" is supplied, is turned on so an to output as the signal So any one of signals S11, S2 and S33 through a shared output terminal. The switch circuits 81, 82 and 83 have the same configuration as each other. FIG. 5B shows the specific circuit example of the switch circuit 81 as the representative of the switch circuits 81 to 83. Here, the signals S11 and So are 8 bit and a complement of 2. In FIG. 5B, blocks 811 to 818 denote buffer circuits each having a control terminal and circuits 811 to 818 have a shared control terminal to which the control signal Sc1 is supplied. When the control signal Sc1 is "0" (Low), the input signal S11 that is signals S110 (LSB) to S117 (MSB) is outputted as it is, namely as the output signal So that is signals S00 (LSB) to S07 (MSB). When the control signal Sc1 is "1" (High), an output is a try-state or a high impedance condition. The output signal So which is obtained by the above steps and also is an output of the picture quality improving apparatus, is shown as the waveform of FIG. 2 (j). Where this waveform chart is drawn in the manner that a value of the composite ratio k of the composite circuit 7 is "0". When the output signal So is compared with the input signal S1, the signal So is understood that a waveform step is added to a substantial midpoint of the waveform change (edge) portion of the envelope of the input waveform of the signal S1, the waveform change of the envelope is shaped sharp, and the edge is properly stressed. If the output signal So is reproduced, there can be obtained the reproduced picture in which the contour is compensated and the color blur improved. Furthermore, in this picture quality improving apparatus, edge stressing is performed within an amplitude of the original and is not over the amplitude of the original signal such as the preshoot and the overshoot which occur in the conventional contour compensation, as understood from the output waveform so shown in FIG. 2(j). Accordingly, in the case that the apparatus and devices including this picture quality improving apparatus are comprised of digital circuits, the problem of overflow does not occur and the apparatus and devices perform an extreme improvement for a picture quantity. As described above, since the signal So outputted from the line L2 is stressed by the edge, there is the signal to which a spectrum over the original band of the signal S1 is newly added. The new addition of the spectrum gives a person watching the reproduce picture image an impression that the resolution of the original signal is improved and this additional spectrum functions to improve the picture distinction. When the value of the composite ratio k in the composite circuit 7 increases from the minimum value "0" to the maximum value "1", an edge stressed amount decreases. Accordingly, the picture quality improving apparatus can set the edge stressed amount coincident to a liking of a person watching the picture image by means of the regulation of the value of the composite ratio k. FIG. 2(k) shows a diagram of the rising waveform of the signal S2 (the chrominance signal) in which the time axis is extended. When the delay circuits 1 and 2 of the first embodiment (see FIG. 1) having the delay time of the value obtained by the equation (1) perform the edge stressing for the signal S2, the output signal So shown in FIG. 2(m) is obtained. On the contrary, when the circuit 1 and 2 having the value which is obtained by the equation (2), namely, m is 2, perform the edge stressing, there can be obtained the signal So shown in FIG. 2(o). Clearly, the signal So in FIG. 2(o) has the edge sharper than the signal So in FIG. 2(m) at the rising portion of the envelope of the waveform. If the delay time of the delay circuits 1 and 2 is set to integral number times of the cycle of the chrominance subcarrier wave (the modulation wave), the change portion of the envelope of the chrominance can be sharpened. Next, FIG. 6 shows a picture quality improving apparatus according to a second embodiment. Numerals 11 and 12 denote delay circuits having the same delay time, 13 to 15 denote adders, 16 denotes a control signal generating circuit, 17 denotes a composite circuit, and 18 denotes a signal selection circuit. In the second embodiment, an entire configuration is substantially the same as the first embodiment without using a delay time in the delay circuits 11 and 12 which is obtained by an equation (13) below different from the delay time in the circuit 1 and 2 which is obtained by the equation (1). T = 1/(2fsc) Here, a half cycle of the chrominance subcarrier wave is the basic delay time. An expansion equation corresponding to the equation is the following equation (14) by which the delay time can be set odd number times of the half cycle of the chrominance subcarrier wave. T = n/(2fsc) where n = 1, 3, 5, ... odd numbers. The difference between the first and second embodiments resides in that the adders 13 to 15 are used in the place of the subtracters 3 to 5 in order to obtain the change of the envelope component by using the values the signals S1 to S3 which have the distance of the half cycle of the chrominance signal. The adders 13 to 15 perform the operation shown in equations (15), (16) and (17), thereby obtaining the signals S4, 55 and 56. S4 = S1 + S2 S5 = S2 + S3 S6 = S4 + S5 The signal S6 has the polarity opposite to the signal S6 which is obtained by the equation (6). Accordingly, the converters 61, 62 and 63 use the conversion table for making the signal 2 bit of a Tables 4(a), 4(b) and 4(c) in the place of the Tables 1(a), 1(b) and 1(c). S41 S40 S4 > 0 0 1 S4 = 0 0 0 S4 < 0 1 1 S51 S50 S5 > 0 0 1 S5 = 0 0 0 S5 < 0 1 1 S61 S60 S6 > 0 1 1 S6 = 0 0 0 S6 < 0 0 1 The control signal generating circuit 16 has the same function as the circuit 6 shown in FIG. 1. In the place of the equation (11), the composite circuit 17 performs an operation by using an equation (18) so as to obtain the signals S11 and 533. where k is a composite ratio in condition 0 ≤ k ≤ 1. A specific example of the composite circuit 7 is shown in FIG. 4(b). The amplifier 3-4 multiplies the signal S1 (S3) by "k-1" times, and the amplifier 3-5 multiplies the signal S2 by "k" times. The outputs of these two amplifiers are used as composing signals at an adder 36. The signal selection circuit 18 has the same configuration as the first embodiment shown in FIG. 1. FIG. 2(k) is a diagram of the waveform showing the rising portion of the chrominance signal in which a time axis of the signal S2 is extended. The delay circuits 11 and 12 of the second embodiment having a delay time represented by an equation (13) perform the edge stressing to the signal S2, thereby obtaining the output signal So shown in FIG. 2(ℓ). Next, the delay circuits 11 and 12 set "n" to 3 in the equation (14), thereby obtaining the output signal So as shown in FIG. 2(n). Furthermore, if "n" is set to 5, the output signal So is obtained as shown in FIG. 2(p). AS clarified from the figures, the rising portion of the waveform in FIG. 2(n) is sharper than that in FIG. 2(ℓ), and that of FIG. 2(p) sharper than FIG. 2(n). Accordingly, if the delay time of the delay circuits 11 and 12 are set to odd number times of the half cycle of the chrominance carrier signal (the modulation wave), it is possible to sharpen the change portion of the envelope of the chrominance signal. The odd number value n in the equation (14) and the integral number value m in the equation (2) as parameters should be determined corresponding to a band width of the signal before modulated the amplitude of the input signal S1 (namely the envelope of the input signal S1), that is the spectrum component included in the signal S1. In the case that the chrominance signal of the television signal is an object for edge stressing, n is limited to 5 and m is to 2. Here, FIG. 7 shows a waveform diagram of several cycles of the signal S1 (the chrominance signal) which is inputted after modulating an amplitude. The first embodiment shown in FIG. 1 has a value P0 as an object of the edge stressing is displaced by a value Pn (n = -4, -2, 2, and 4) which is distant from the integral number times of the cycle (1/fsc) of the chrominance subcarrier wave (the modulation wave) or displaced by a composite value of the values P0 and Pn. On the other hand, the second embodiment shown in FIG. 6 has a value P0 as an object of the edge stressing, displaced by a value having the polarity opposite to Pn (n = -5, -3, -1, 1, 3, and 5) which is distant from the odd number times of the half cycle {1/(2fsc)} of the chrominance subcarrier wave (the modulation wave) or displaced by a composite value of the values P0 and Pn having the opposite polarity. By this, there is a sharpened change portion of the envelope of the chrominance signal S1 supplied after modulating an amplitude, that is the waveform change portion of the original chrominance signal before modulating an amplitude. The equation (11) in the composite circuit 7 of the first embodiment shown in FIG. 1 can be displaced by an equation (19). Namely, the composite circuit 7 can be constructed by using signals outputted from the subtracters 3 and 4 in the place of the signal S2, that is "S1 - S2" (- S4) and "S2 - S3" (= S5). FIG. 4(c) shows a configuration of the composite circuit 7 in which the signal "S2 - S3 (- S5)" is multiplied by k in the amplifier 3-7 and the subtracter 3-8 subtracts the signal S1 from the multiplied result, and FIG. 4(d) shows a configuration of the composite circuit 7 in which the signal "S2 - S3" is multiplied by k in the amplifier 3-9 and the adder 3-10 adds the multiplied result with the signal S3. The equation (18) in the composite circuit 7 shown in FIG. 6 representing the second embodiment, can be transformed to an equation (20) written above, and the circuit 7 calculates by using the outputs of the adders 13 and 14 in the place of the signal S2, that is, "S1 + S2 (- S4)" and "S2 + S3 (= S5)". FIG. 4 (e) shows a configuration of the composite circuit 7 in which the signal "S1 + S2" (or "S2 + S3") in multiplied by k in the amplifier 3-11 and the subtracter 3-12 subtracts the signal S1 (or S3) from the multiplied result. Here, the sharpness of the change portion of the envelope (degrees of the edge stressing) of the output signal So depends on the frequency characteristics within the change portion of the envelope in the original signal S1 before stressing the edge (namely, the waveform of the chrominance signal before modulating the amplitude). If the leading and trailing edge portions of the envelope of the original signal S1 have sharper slants, edge stressing is performed to a stronger degree, but to a weaker degree for gentler slants. As described above, since the degrees of the edge stressing depend on the frequency of the input signal and have the complete correlation with the input signal without delay times of the delay circuit 11 and 12 and the composite ratio k of the composite circuit 7, this picture quality improving apparatus does not give a person watching the reproduced picture a sense of incongruity and he feels intact pictures, thereby improving a distinction and a resolution. Furthermore, as each component of the shown embodiments is comprised itself of the simple circuitry such as general articles, for example, IC and the like on the markets, it is possible to manufacture the entire apparatus and devices at low cost. Even though the above embodiments use the chrominance signals of the television signals as the input signal, the picture quality improving apparatus of the present invention can process other signals in which the amplitude is modulated. For digitalized image data, a software processing by the computer can realize the contour compensation and edge stressing which are equivalent to the present invention, and this invention can be applied to an image data processing by the software. Furthermore, this invention has effects to improve the waveform deterioration in the general digital transmission and communication system. Next, there is described a third embodiment shown in FIG. 8. Numerals 21 to 24 denote delay circuits having the same delay time, 25 to 31 denote subtracters, 32 denotes a control signal generating circuit, and 33 denotes signal selection circuit. For the sake of convenience in a description, there is omitted a signal delay which is caused by own processing time of each circuit of itself and a delay circuit or the like which is used only for compensating the signal delay. Furthermore, an input signal dealt in this picture quality improving apparatus assumes the signal that is a signal modulated in amplitude such as chrominance signals in television signals and the like. It is supposed that there is an input signal S1 as a chrominance signal of the television signals shown in FIG. 9(a) through a line L1. This signal is an example of a luminance signal in the NTSC system having a band of 4 MHz. The input signal S1 is supplied to the delay circuit 21 having a delay time T which is obtained by an equation (21) as follows: T = 1/(8fsc) = 34.9 ns where Fsc is about 3.58 MHz. A value of the delay time T corresponds to 1/8 cycle of the chrominance subcarrier wave (its frequency is Fsc). Furthermore, the value of T is 1/2 of the ordinary sampling period {1/(4fsc)} which is used in the quantization of the television signal. FIG. 9(b) shows the output signal S2 which is delayed time T by the delay circuit 21. The delay circuit 22 of the next step has the same function as FIG. 9(c) and further delayed time T from the supplied signal S2. The delay circuit 23 of the next step has the same function as the circuit 21 and outputs the signal S4 which is shown in FIG. 9(d) and further delayed time T from the supplied signal S3. The delay circuit 24 of the next step has the same function as the circuit 21 and outputs the signal S5 which is shown in FIG. 9(e) and further delayed time T from the supplied signal S4. These signals S1-S5 form a first signal group. The subtracter 25 subtracts the output signal S2 of the delay circuit 21 from the input signal S1 and outputs a signal D1 which is obtained by an equation (22). There is a time difference T between the signals S1 and S2 which are adjacent in time axis in the first signal group. D1 = S1 - S2 The subtracter 26 has the same function as subtracter 25 and subtracts the output signal S3 of the delay circuit 22 from the output signal S2 of the delay circuit 21 to output a signal D2 which is obtained by an equation (23). D2 = S2 - S3 The subtracter 27 has the same function as subtracter 25 and subtracts the output signal S4 of the delay circuit 23 from the output signal S3 of the delay circuit 22 to output a signal D3 which is obtained by an equation (24). D3 = S3 - S4 The subtracter 28 has the same function as subtracter 25 and subtracts the output signal S5 of the delay circuit 24 from the output signal S4 of the delay circuit 23 to output a signal D4 which is obtained by an equation (25). D4 = S4 - S5 These signals D1, D2, D3 and D4 respectively represent a first difference signal and form a first difference signal group. And the subtracter 25-28 form a first subtracter group. The subtracter 29 has the same function as subtracter 25 and subtracts the output signal D2 of the subtracter 26 from the output signal D1 of the subtracter 25 to output a signal D5 which is obtained by an equation (26). D5 = D1 - D2 The subtracter 30 has the same function as subtracter 25 and subtracts the output signal D3 of the subtracter 27 from the output signal D2 of the subtracter 26 to output a signal D6 which is obtained by an equation (27). D6 = D2 - D3 The subtracter 31 has the same function as subtracter 25 and subtracts the output signal D4 of the subtracter 28 from the output signal D3 of the subtracter 27 to output a signal D7 which is obtained by an equation (28). D7 = D3 - D4 These signals D5, D6, and D7 respectively represent a second difference signal and form a second difference signal group. And the subtracters 29-31 form a second subtracter group. FIGS. 9(f) to 9(ℓ) show waveforms of signals D1, D2, D3, D4, D5, D6 and D7. A frequency characteristic gl of a first differential operation of the first subtracter group (the subtracters 25-28) except phase items is represented a differential characteristic of the sine waveform, which is obtained by an equation (29). A frequency characteristic g2 of a second differential operation of the second subtracter group (the subtracters 29-31) except phase items is represented a differential characteristic of the sine waveform in a high-pass filter, which is obtained by an equation (30). The first difference signal corresponds to a simple differential signal, and the second difference signal corresponds to a quadric differential signal. The characteristics of these waveforms of the difference signals are to obtain a significant value at the change portion in the waveform of the input signal. g1 = -j2sin {πf/(8fsc)} g2 = -2[1 - cos {πf/(4fsc)}] The output signals D1 to D7 of the subtracters 25 to 31 are supplied to the control signal generating circuit 32 of the next step. The circuit 32 generates the control signal Sc corresponding to the input signals D1 to D7. The control signal Sc is a logic signal of a low active (negative logic) comprising five signals Sc1, Sc2, Sc3, Sc4 and Sc5 which are shown in FIGS. 9(q), 9(p), 9(o), 9(n) and 9(m) and obtained by an equation (31) as follows: As described above, the conditions are as follows: (i) when a first condition is satisfied in that values of - the signals D2, D3, D4, D6 and D7 are all positive or negative polarity as the same each other, the signal Sc5 is "0" (Low); (ii) when values of the signals D2, D3 and D6 are all positive or negative polarity as the same each other and the first condition is not satisfied, the signal Sc4 is "0" (Low); (iii) when a second condition is satisfied in that values of the signals D1, D2 and D3 are all positive or negative polarity as the same each other, values of the signals D5 and D6 are all positive or negative polarity as the same each other, and the values of the signals D5 and D6 has the polarity different from the signals D1, D2 and D3, the signal Sc1 is "0" (Low); (iv) when values of the signals D2 and D3 are all positive or negative polarity as the same each other, the value of the signal D6 has the polarity different from the signals D2 and D3, and the second condition is not satisfied, the signal Sc2 is "0" (Low); and (v) when the combinations of values of the signals D1 to D7 is not the above conditions, the signal Sc3 is "0" (Low). FIG. 10 shows a circuit example for realizing the control signal generating circuit 32. In FIG. 10, converters 2-1 to 2-7 output 2-bit signals after converting the signals D1-D7 into "10" when they are positive, "00" when they are zero, and "01" when they are negative. A Table 5 shows a conversion table of each converter, and signals D1 to D7 formed in 2-bit are represented in an equation (32) as follows: Dn1 Dn0 Dn > 0 1 0 Dn = 0 0 0 Dn < 0 0 1 where n = 1-7. Dn = 2 0 Dn1 + 2 -1 Dn0 where n = 1-7. The converter 2-1 to 2-7 are comprised of the table look-up system such as TTL-IC and ROM and a PLA (programmable logic array). Outputs of the seven converters pass through AND circuits 2-8 to 2-23, NOR circuits 2-24 to 2-27, and a NAND circuit 2-28 so as to output the control signals Sc1, Sc2, Sc3, Sc4 and SC5 obtained by an equation as follows: Even though the signals Sc1 to Sc5 are represented as a simple name in FIG. 10, in the above equation, the signals are represented by logical equation of the low active (negative logic), namely, adding bars in order to clarify usage object of these signals. Since the signals D1 to D7 are the output signals of the subtracters having the function of the high-pass filter, it is generally possible to include noise components of the high frequency wave. In order to improve performance of the control signal generating circuit 32 to the noise component, reference values in the converters 2-1 to 2-7 are set as a small positive value β (a value corresponding to a level of high frequency noise components) not to "0". The converters 2-1 to 2-7 respectively output 2-bit signals of the signals D1 to D7 which have value "10" when the reference value is over β, "00" when the value on or between -β and β, and "01" when the value is under -β. Setting the reference value causes the control signal generating circuit 32 to improve performance to noises. The reference values β may be set different values each converter. Here, description returns to FIG. 8 and the signals S1, S2, S3, S4 and S5 and the control signal Sc (signals Sc1, Sc2, Sc3, Sc4 and Sc5) are supplied to the signal selection circuit 33 of the next step. The signal selection circuit 33 outputs any one of the signals S1 to S5 corresponding to the control signal Sc to output a signal So obtained by an equation (34) as follows: So = Sn (when Scn = 0 where n = 1, ... 5). Namely, the signal selection circuit 33 selects and outputs signal S1 when the control signal Sc1 is "0" (Low), the signal S2 when the control signal Sc2 is "0" (Low), the signal S3 when the control signal Sc3 is "0" (Low), the signal S4 when the control signal Sc4 is "0" (Low), and the signal S5 when the control signal Sc5 is "0" (Low). FIG. 11A shows a circuit example for realizing the signal selection circuit 33. Numerals 3-101 to 3-105 denote switch circuits to which the signals S1 to S5 and the control signals Sc1 to Sc5 are respectively supplied. When any one of the control signals Sc1 to Sc5 is "0" (Low), the switch circuit to which the control signal is supplied, is turned on so as to output any one of the signals S1 to S5 through the shared output terminal. The switch circuit 3-101 to 3-105 have the same configuration as each other. FIG. 11B shows the specific circuit example of the switch circuit 3-101 as the representative of the switch circuits 3-101 to 3-105. The signals S1 and So have a bit which represents the complement of "2". In FIG. 11B, blocks 3-10 to 3-17 denote buffer circuits each having a control terminal and have the shared control terminal which receives the control signal Sc1. When the control signal Sc1 is "0" (Low), the input signal S1 that is signals S10 (LSB) to S17 (MSB) is outputted as it is, namely, as the output So {that is So0 (LSB) to So7 (MSB)}. When the control signal Sc1 is "1" (High), an output is a try-state or a high impedance condition. The output signal So which is obtained by the above steps and also is an output of the picture quality improving apparatus, is shown as the waveform of FIG. 9 (r). When the output signal So is compared with the input signal S1 shown in FIG. 9(a), the signal So is understood that a waveform step is added to a substantial midpoint of the waveform change (edge) portion of the envelope of the input waveform of the signal S1, the waveform change of the envelope is shaped sharp, and the edge is properly stressed. If the output signal So is reproduced, there can be obtained the reproduced picture in which the contour is compensated and the color blur improved. Furthermore, in the picture quality improving apparatus, edge stressing is performed within an amplitude of the original signal and is not over the amplitude of the original signal such as the preshoot and the overshoot which occur in the conventional contour compensation, an understood from the output waveform So shown in FIG. 9(r). Accordingly, in the case that the apparatus and devices including this picture quality improving apparatus are comprised of digital circuit, the problem of overflow does not occur and the apparatus and devices perform an extreme improvement for a picture quality. As described above, since the edge stressing prevents the reproduced picture image having preshoot and overshoot, there is obtained the reproduced picture about which a watching person feels intact without a sense of incongruity. Accordingly, the picture signal So outputted from the line L2 is stressed by the edge, there is the signal to which a spectrum over the original band of the signal S1 is newly added. The new addition of the spectrum gives a person watching the reproduced picture image an impression that the resolution of the original signal is improved and this additional spectrum functions the improvement of a picture distinction. Here, the sharpness of the Change portion of the envelope (degrees of the edge stressing) of the output signal So depends on the frequency characteristics within the change portion of the envelope in the original signal S1 before stressing edge. If the leading and trailing edge portions of the envelope of the original signal S1 have sharper slants, edge stressing is performed to a stronger degree, but to a weaker degree for gentler slants. As described above, since the degree of edge stressing depends on the frequency of the input signal and has a complete correlation with the input signal, this picture quality improving apparatus does not give a person watching the reproduced picture a sense of incongruity and he feels intact pictures, thereby improving a distinction and a resolution of the picture image. Furthermore, as each component of the shown embodiments is comprised itself of the simple circuitry such as general articles, for example, IC and the like on the markets, it is possible to manufacture the entire a ratus and devices at low cost. Next, FIG. 12 shows a picture quality improving apparatus according to a fourth embodiment. Numerals 41 to 46 denote delay circuits having the same delay time, 47 to 57 denote subtracters, 58 denotes a control signal generating circuit, and 59 denotes a signal selection circuit. In the fourth embodiment, an entire configuration is substantially the same as the third embodiment shown in FIG. 8. The difference between the third and fourth embodiments resides in that the numbers of the delay circuits. Even though the number of the delay circuits 41 to 46 is even numbers, the delay circuits 45 and 46 are added to the configuration of the third embodiment in the fourth embodiment. The first subtracter group also has the subtracters 47 to 52 two more than the third embodiment, which are even numbers. Also, the second subtracter group has the subtracters 53 to 57 two more than the third embodiment, which are odd numbers. In the fourth embodiment, when the input signal S1 is a signal which is shown in FIG. 13(a), and the delay times of the delay circuits 41-46 are given by the equation (21), FIGS. 13(b) to 13(g) show waveforms of the signals S2 to S7 which are delayed step by step time T. The subtracters 47 to 52 respectively performs the first difference operation by using the signals S1 to S7 of the delay circuits 41 to 46 which respectively have the time difference T, thereby outputting the signals D1 to D6 obtained by an equation (35) as follows: FIGS. 13(h) to 13(m) show the waveforms of the signals D1 to D6. The subtracters 53 to 57 respectively performs the second difference operation, thereby outputting the signals D7 to D11 obtained by an equation (36) as follows: FIGS. 13(n) to 13(r) show the waveforms of the signals D7 to D11. The first difference signals D1, D2, D3, D4, D5 and D6 and the second difference signals D7, D8, D9, D10 and D11 are supplied to the control signal generating circuit 58 of the next step. The circuit 58 generates the control signal Sc (that is, Sc1, Sc2, Sc3, Sc4, Sc5, Sc6 and Sc7) corresponding to the combinations of the value of each signal. The condition of each signal is represented by an equation (37) as follows: FIGS. 13(s) to 13(y) show the waveforms of the control signals Sc7 to Sc1. As described in the third embodiment shown in FIG. 8, in order to improve the performance for suppressing noises of the control signal generating circuit 58, the converters in the circuit 58 may have the reference value β for removing noises, thereby distributing the signals D1 to D11. The signals S1 to S7 and the control signal Sc (that is, Sc1 to Sc7) are supplied to the signal selection circuit 59 which selects signal Sn (n = 1-7) corresponding to the condition that any one of the seven control signals Scn (n = 1-7) becomes low "0", thereby outputting the signal So shown in FIG. 13(z). A sharpness of the waveform edge of the signal So obtained in the fourth embodiment, is sharper than that of the third embodiment shown in FIG. 9(r). By this, it can be understood that the increase of the number of the delay circuits can increase an amount of edge stressing. Accordingly, increasing and decreasing the numbers of the delay circuits can make the picture quality improving apparatus regulate the amount of edge stressing. The fourth embodiment has also and of course the same effect as the third embodiment except above. It is easy to generalize the method for increasing and decreasing the numbers of the above delay circuits. Namely, the picture quality improving apparatus comprises delay circuits of an even number (2M, where M is an integral number more than two) which are connected in series and gives in turn an input signal a predetermined delay time; a first signal group of an odd number (2M plus 1) including the input signal and an even number (2M) of output signals of the delay circuit; a first subtracter group which is formed by connecting an even number (2M) of subtracters for each obtaining a first differential signal by calculating a difference between two signals in time adjacent in the first signal group; a first differential signal group including the even number (2M) of the first differential signals which are obtained by the first subtracter group; a second subtracter group which is formed by connecting an odd number (2M - 1) of subtracters for each obtaining a second differential signal by calculating a difference between two signals in time adjacent in the first differential signal group; a second differential signal group including the even number (2M - 1) of the second differential signals which are obtained by the second subtracter group; a control signal generating circuit for obtaining a control signal which changes its value corresponding to combinations of the first and second differential signals in the first and second differential signal groups; a signal selection circuit which is supplied the first signal group and control signal for selecting and outputting anyone signal amongst the first signal group corresponding to the control signal in the manner of obtaining an output signal which is generated by adding a waveform step to a midpoint portion of a waveform change of the input signal. Accordingly, the apparatus obtains an output signal stressed by an edge of an input signal. Even though the above embodiments use the luminance signals of the television signals as the input signal, the picture quality improving apparatus of the present invention can process other signals in which the amplitude is modulated. For digitalized image data, a software processing by the computer can realize the contour compensation and edge stressing which are equivalent to the present invention, and this invention can be applied to an image data processing by the software. Furthermore, this invention has effects to improve the waveform deterioration in the general digital transmission and communication system.

Claims: An image improvement apparatus including: when input signals which are amplitude modulated by a modulating wave are first signals (S1); a delay circuit (1,2) which outputs second signals (S2) which are said first signals (S1) which have been time delayed by an integral multiple of a cycle of said modulation wave, and third signals (S3) which are said second signals (S2) which have been time delayed by said positive integral multiple; a first subtractor (3) which subtracts said second signals (S2) from said first signals (S1) and outputs fourth signals (S4); a second subtractor (4) which subtracts said third signals (S3) from said second signals (S2) and outputs fifth signals (S5), a third subtractor (5) which substracts said fifth signals (S5) from said fourth signals (S4) and outputs sixth signals (S6), a control signal generating circuit (6) which is supplied with said fourth, fifth and sixth signals (S4,S5,S6) and outputs a seventh signal (Sc) which is a control signal for which the value changes in accordance with combinations of said fourth, fifth and sixth signals (S4,S5,S6), a composite circuit (7) supplied with said first, second and third signals (S1,S2,S3) and which combines said first signals and said second signals (S1,S2) and outputs an eighth signal (S11) and combines said second (S2) and third signal (53) and outputs a ninth signal (S33), and a signal selection circuit (8) supplied with said eighth, second, ninth and seventh signals, (S11, S2,S33,Sc) and which selects and outputs one of said eighth, second and ninth signals (S11, S2, S33) in accordance with said seventh signal (Sc) which is a control signal, said control signal generating circuit (6) is arranged to output said control signal (Sc) instructing said signal selection circuit (8) to select and output a) said ninth signal (S33) when values of said fourth and fifth signals (S4,S5) are both larger than a first positive constant, and a value of said sixth signal (S6) is simultaneously larger than a second positive constant, or when values of said fourth and fifth signals (S4,S5) are both smaller than a first negative constant, and a value of said sixth signal (S6) is simultaneously smaller than a second negative constant, and b) said eighth signal (S11) when values of said fourth and fifth signals (S4,S5) are both larger than said first positive constant, and said value of said sixth signal (S6) is simultaneously smaller than said second negative constant, or when values of said fourth and fifth signals (S4,S5) are both smaller than said first negative constant, and a value of said sixth signal (S6) is larger than said second positive constant, and c) said second signal (S2) when a combination of the three signals of said fourth, fifth and sixth signals (S4,S5,S6) is other than a combination of a) and b). An image improvement apparatus in accordance with claim 1, wherein said first and second positive constants and said first and second negative constants are all substantially zero. An image improvement apparatus including: when input signals which are amplitude modulated by a modulating wave are first signals (S1), a delay circuit (1) which outputs second signals (S2) which are said first signals (S1) which have been time delayed by an odd integral number of half cycles of said modulation wave, and third signals (S3) which are said second signals (S2) which have been time delayed by said odd integral multiple of half cycles, a first adder (13) which adds said second signals(S2) to said first signals (S1) and outputs fourth signals (S4), a second adder (14) which adds said third signals (S3) to said second signals (S2) and outputs fifth signals (S5), a third adder (15) which adds said fifth signals (S5) to said signals (S4) and outputs sixth signals (S6), a control signal generating circuit (16) which is supplied with said fourth, fifth and sixth signals (S4,S5,S6), and outputs a seventh signal (Sc) which is a control signal for which the value changes in accordance with combinations of said fourth, fifth and sixth signals (S4,S5,S6), a composite circuit (17) supplied with said first, second and third signal (S1,S2,S3) and which combines said first signals (S1) and said second signals (S2) and outputs an eighth signal (S11) and combines said second and third signal (S2,S3) and outputs a ninth signal (S33), and a signal selection circuit supplied with said eighth, second, ninth and seventh signals (S11,S2,S33,Sc) and which selects and outputs one of said eighth, second and ninth signals (S11,S2,S33) in accordance with said seventh signal (Sc) which is a control signal, and wherein said control signal generating circuit (6) is arranged to output said control signal (Sc) instructing said signal selection circuit (8) to select and output a) said eighth signal (S11) when values of said fourth and fifth signals (S4,S5) are both larger than a first positive constant, and a value of said sixth signal (S6) is simultaneously larger than a second positive constant, or when values of said fourth and fifth signals (S4,S5) are both smaller than a first negative constant, and a value of said sixth signal (S6) is simultaneously smaller than a second negative constant, and b) said ninth signal (S33) when values of said fourth and fifth signals (S4,S5) are both larger than said first positive constant, and said value of said sixth signals (S6) is simultaneously smaller than a second negative constant, or when values of said fourth and fifth signals (S4,S5) are both smaller than said first negative constant, and a value of said sixth signal (S6) is larger than said a second positive constant, and c) said second signal (S2) when a combination of the three signals of said fourth, fifth and sixth signals (S4,S5,S6) is other than a combination of a) and b). An image improvement apparatus in accordance with claim 3, wherein said first and second positive constants and said first and second negative constants are all substantially zero. An image improvement apparatus including: four delay circuits (21-24) which are connected in series, which apply a required time delay to first signals (S1) which are input signals and output second signals (S2), which apply a required time delay to said second signals (S2) and output third signals (S3), which apply a required time delay to said third signals (S3) and output fourth signals (S4), and which apply a required time delay to said fourth signals (S4) and output fifth signals (S5); a first subtracter (25) which subtracts said second signals (S2) from said first signals (S1) and outputs sixth signals (D1): a second subtracter (26) which subtracts said third signals (S3) from said second signals (S2) and outputs seventh signals (D2); a third subtracter (27) which subtracts said third signals (S3) from said fourth signals (S4) and outputs eight signals (D3); a fourth subtracter (28) which subtracts said fourth signals (S4) from said fifth signals (S5) and outputs ninth signals (D4) ; a fifth subtracter (29) which subtracts said seventh signals (D2) from said sixth signals (D1) and outputs tenth signals (D5); a sixth subtracter (30) which subtracts said eighth signals (D3) from said seventh signals (D2) and outputs eleventh signals (D6); a seventh subtracter (31) which subtracts said ninth signals (D4) from said eighth signals (D3) and outputs twelfth signals (D7); a control signal generating circuit (32) which is supplied with said sixth, seventh, eighth, ninth, tenth, eleventh and twelfth signals (D1-D7), and outputs a thirteenth signal (Sc) which is a control signal for which the value changes in accordance with combinations of said sixth, seventh, eighth, ninth, tenth, eleventh and twelfth signals (D1-D7); and a signal selection circuit (33) which is supplied with said first, second, third, fourth, fifth and thirteenth signals (S1-S5,Sc), and which selects and outputs one of said first, second, third, fourth and fifth signals (S1-S5) in accordance with said thirteenth signal (Sc) which is the control signal: wherein said control signal generating circuit (32) outputs; a) a control signal for said signal selection circuit (33) to select and output said fifth signal (S5) when values of five signals of said seventh, eighth, ninth, eleventh and twelfth signal (D2,D3,D4,D6,D7) satisfy a first conditions of their values simultaneously being the same polarity for either positive or negative; b) a control signal for said signal selection circuit (33) to select and output said fourth signal (S4) when values of three signals of said seventh, eighth and eleventh signals (D2,D3,D6) all have the same polarity when they are positive or negative at the same time, and when said first condition is not established; and c) a control signal for said signal selection circuit (33) to select and output said first signal (S1) when values of the three signals of said sixth, seventh and eighth signals (D1,D2,D3) all have the same polarity when they are positive or negative at the same time, and when the values of said tenth and eleventh signals (D5,D6) both have the same polarity when they are positive or negative at the same time, and when there is the establishment of a second condition for the values of a polarity of said tenth and eleventh signals (D5,D6) to be a value different from the polarity of a value of said sixth, seventh and eighth signals (D1,D2,D3); d) a control signal for said signal selection circuit (33) to select and output second signal (S2) when values of said seventh and eighth signals (D2,D3) both have the same polarity when they are positive or negative at the same time, and when the value of the polarity of said eleventh signal (D6) is a value which is different from that of the polarity of said seventh and eighth signals (D2,D3), and when said second condition is not established; and e) a control signal for said signal selection circuit (33) to select and output said third signal (S3) when combinations of values of the seven signals of said sixth, seventh, eighth, ninth, tenth, eleventh and twelfth signals (D1-D7) are other than the combinations described above: An image improvement apparatus including-. six delay circuits (41-46) which are connected in series, which apply a required time delay to first signals (S1) which are input signals and output second signals (S2), which apply a required time delay to said second signals (S2) and output third signals (S3), which apply a required time delay to said third signals (S3) and output fourth signals (S4), which apply a required time delay to said fourth signals (S4) and output fifth signals (S5), which apply a required time delay to said fifth signal (S5) and output sixth signals (S6), and which apply a required time delay to said sixth signals (S6) and output seventh signals (S7); a first subtracter (47) which subtracts said second signals (S2) from said first signals (S1) and outputs eighth signals (D1): a second subtracter (48) which subtracts said third signals (S3) from said second signals (S2) and outputs ninth signals (D2); a third subtracter (49) which subtracts said fourth signals (S4) from said third signals (S3) and outputs tenth signals (D3); a fourth subtracter (50) which subtracts said fifth signals (S5) from said fourth signals (S4) and outputs eleventh signals (D4); a fifth subtracter (51) which subtracts said sixth signals (S6) from said fifth signals (SS) and outputs twelfth signals (D5); a sixth subtracter (52) which subtracts said seventh signals (S7) from said sixth signals (S6) and outputs thirteenth signals (D6); a seventh subtracter (53) which subtracts said ninth signals (D2) from said eighth signals (D1) and outputs fourteenth signals (D7); an eighth subtracter (54) which subtracts said tenth signals (D3) from said ninth signals (D2) and outputs fifteenth signals (D8); a ninth subtracter (55) which subtracts said eleventh signals (D4) from said tenth signals (D3) and outputs sixteenth signals (D9); a tenth subtracter (56) which subtracts said twelfth signals (D5) from said eleventh signals (D4) and outputs seventeenth signals (D10); an eleventh subtracter (57) which subtracts said thirteenth signals (D6) from said twelfth signals (D5) and outputs eighteenth signals (D11): a control signal generating circuit (58) which is supplied with said eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth signals (D1-D11), and outputs a nineteenth signal (Sc) which is a control signal for which the value changes in accordance with combinations of said eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth signals (D1-D11); and a signal selection circuit (59) which is supplied with said first, second, third, fourth, fifth, sixth, seventh and nineteenth signals (S1-S7,Sc), and which selects and outputs one of said first, second, third, fourth, fifth, sixth and seventh signals (S1-S7) in accordance with said nineteenth signal (Sc) which is the control signal: wherein said control signal generating circuit (58) outputs; a) a control signal for said signal selection circuit (59) to select and output said first signal (S1) in the case where first conditions are satisfied, in which the first conditions are established when values of four signals of said eighth, ninth, tenth and eleventh signal (D1-D4) have a positive polarity and when values of three signals of said fourteenth, fifteenth and sixteenth signals (D7-D9) have a negative polarity, or when values of four signals of said eighth, ninth, tenth and eleventh signal (D1-D4) have a negative polarity and when values of three signals of said fourteenth, fifteenth and sixteenth signals (D7-D9) have a positive polarity; b) a control signal for said signal selection circuit (59) to select and output said second signal (S2) in the case where second conditions are satisfied, in which the second conditions are established when values of three signals of said ninth, tenth and eleventh signals (D2-D4) all have the same positive polarity and when values of two signals of said fifteenth and sixteenth signals (D8,D9) both have the same negative polarity, or when values of three signals of said ninth, tenth and eleventh signals (D2-D4) all have the same negative polarity and when values of two signals of said fifteenth and sixteenth signals (D8,D9) both have the same positive polarity, and when said first conditions are not established; c) a control signal for said signal selection circuit (59) to select and output said third signal (S3) in the case where third conditions are satisfied, in which the third conditions are established when values of two signals of said tenth and eleventh signals (D3,D4) both have the same positive polarity and when a value of said sixteenth signal (D9) has a negative polarity, or when values of two signals of said tenth and eleventh signals (D3,D4) both have the same negative polarity and when a value of said sixteenth signal (D9) has a positive polarity, and when said first and second conditions are not established; d) a control signal for said signal selection circuit (58) to select and output said seventh signal (S7) in the case where fourth conditions are satisfied, in which said fourth conditions are established when values of seven signals of said tenth, eleventh, twelfth, thirteenth, sixteenth, seventeenth and eighteenth signals (D3-D6,D9-D11) all have the same polarity when they are positive or negative at the same time; e) a control signal for said signal selection circuit (59) to select and output said sixth signal (S6) in the case where fifth conditions are satisfied, in which the fifth conditions are established when values of five signals of said tenth, eleventh, twelfth, sixteenth and seventeenth signals (D3-D5,D9,D10) all have the same polarity when they are positive or negative at the same time, and when said fourth conditions are not established; f) a control signal for said signal selection circuit (59) to select and output said fifth signal (S5) in the case where sixth conditions are satisfied,, in which the sixth conditions are established when values of three signals of said tenth, eleventh and sixteenth signals (D3,D4,D9) all have the same positive or negative polarity and when said fourth and fifth conditions are not established; and g) a control signal for said signal selection circuit (59) to select and output said fourth signal (S4) in the case where said first, second, third, fourth, fifth and sixth conditions are not established;

Inventors: ITO SHIGEHIRO, ITO, SHIGEHIRO
Applicants: VICTOR COMPANY OF JAPAN, VICTOR COMPANY OF JAPAN, LTD.
Application year: 1992
Main classification: H04N9
IPC codes: H04N9