Hemt type semiconductor device

Abstract: A HEMT type semiconductor device comprising: a semiconductor substrate (1, 31); a buffer semiconductor layer (2, 32) formed on the substrate; a first semiconductor well layer (3, 33) formed on the buffer layer and serving as a first conductivity type channel layer; a second semiconductor well layer (4, 34) formed on the first well layer and serving as a second conductivity type opposite the first conductivity, channel layer; and a potential barrier layer (5, 35) formed on the second well layer and forming a potential barrier for carriers. The substrate (1, 31) is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a HEMT (High Electron Mobility Transistor) type semiconductor device. 2. Description of the Related Art A conventional HEMT type semiconductor device comprises a semiconductor substrate, a buffer layer formed on the substrate, a semiconductor well layer (i.e., a channel layer or a carrier-flowing layer) formed on the buffer layer, a potential barrier layer forming an electric potential barrier against the carriers and formed on the well layer, and a gate electrode forming a Schottky contact and formed on the barrier layer. In the semiconductor well layer electrons (so-called two dimensional electron gas) are generated and flow at a high electron mobility, or holes (so-called two dimensional hole gas) are generated and flow at a high hole mobility. The substrate and formed layers are made of suitable compound semiconductor materials and form hetero-junctions at the interfaces between them. For example, the substrate and the well layer (channel layer) are of GaAs, InGaAs or InP, and the barrier layer is of AlGaAs or AlInAs. Referring to Fig. 1, a conventional complementary HEMT type semiconductor device (C-HEMT) comprises, for example, a semiconductor substrate 51 of a semi-insulating GaAs substrate, a buffer layer 52 of undoped GaAs layer, a semiconductor well layer 53 of undoped In 0.25 Ga 0.75 As layer, and a potential barrier layer 55 of Al 0.5 Ga 0.5 As, the layers being formed by a continuous epitaxial growth process. To separate a p-channel HEMT and an n-channel HEMT from each other, an isolation region 61 is formed by ion-implanting B (boron) or O (oxygen) ions to the substrate 51 from the top surface. On the barrier layer 55 first and second gate electrodes 62 and 63 are formed as Schottky barrier contacts and are surrounded by side-wall insulating films 64 and 65 of, e.g., SiO 2 , respectively. P-type (electrode) regions 56 and 57 are formed by selectively ion-implanting p-type impurities (e.g., Be) to the buffer layer 52 from the top surface by using the first gate electrode 62 and a suitable resist pattern layer (not shown) as a mask, and n-type (electrode) regions 58 and 59 are formed by selective ion-implanting n-type impurities (e.g, Si) in the layers 52, 53 and 55 by using the second gate electrode 63 and another suitable resist pattern layer as another mask. On the doped regions 56 and 57 p-type electrodes (not shown) are formed, on the doped regions 58 and 59 n-type electrode (not shown) are formed, and then these electrodes are electrically connected with suitable interconnections (wiring layers, not shown) to form an electric circuit. In such a C-HEMT, a p-channel (i.e., two dimensional hole gas) is generated in a p-channel region 53p of a portion of the semiconductor well layer 53 between the p-type regions 56 and 57 and an n-channel (i.e., two dimensional electron gas) is generated in an n-channel region 53n of another portion of the semiconductor well layer 53 between the n-type regions 58 and 59. A C-HEMT having the above-mentioned structure corresponds to a complementary III-V heterostructure FET (C-HFET) disclosed in an article by A.I. Akinwande et al. IEDM90, IEEE, 1990, pp.983-986. The article discloses that a p-channel HFET (i.e., p-channel HEMT) has a threshold voltage of about -0.35 V (see Table 2) and an n-channel HFET (i.e., n-channel HEMT) has a threshold voltage of about 0.7 V (see Table 1). The sum (1.05 V) of the threshold voltages of the p-channel HEMT and n-channel HEMT corresponds to a bandgap of the semiconductor well layer 53. A drain current variation of each of the p-channel HEMT and n-channel HEMT, depending on the gate voltage, is obtained, as shown with a broken line in Fig. 2. The conventional C-HEMT shown in Fig. 1 has, however, relatively high threshold voltages, and when absolute values of gate voltages applied on the gate electrodes are increased, gate leakage currents between the gate and source are generated and increased, as shown in Fig. 2. In such a case, when a logic amplitude is increased to maintain a high speed operation, the gate leakage current is also increased. Where the gate leakage current is suppressed, a gate voltage cannot be increased with the result that the high speed operation is not sufficiently attained. For example, at a power supply voltage of 1.5 V, a no-load gate delay is about 230 ps and power dissipation is about 64 µW/gate, and at a power voltage of 1.0 V, a no-load gate delay is about 700 ps and power dissipation is about 7 µW/gate (cf. the above-cited article, page 985, right column). It is possible to adjust the threshold voltage of the n-HEMT to about zero volt by adding a threshold voltage controlling layer formed between the potential barrier layer and the gate electrode of the n-HEMT. In this case, it is necessary to make the controlling layer relatively thick, and thus a distance between the gate electrode and the semiconductor well layer becomes large, which deteriorates the controllability of the n-HEMT. Another C-HEMT similar to that of Fig. 1 has been reported by R.R. Daniels et al. "Complementary Heterostructure Insulated Gate FET Circuits for HighSpeed, Low Power VLSI", IEDM86, IEEE, 1986, pp.448-451. To lower the threshold voltages of the p-channel HEMT and n-channel HEMT, it is possible to form these HEMTs on the same semiconductor substrate such that a semiconductor laminated structure of the former HEMT is different from that of the latter HEMT. For example, Japanese Unexamined Patent Publication (Kokai) No 57-208174 proposed a complementary FET utilizing a two dimensional electron gas and two dimensional hole gas; the FET of which comprises a p-channel HEMT having an undoped Ge layer, an undoped GaAs layer and a p-GaAs layer successively epitaxially grown on an undoped GaAlAs layer formed on a semi-insulating GaAs substrate; and an n-channel HEMT having an undoped GaAs layer, an undoped GaAlAs layer and an n-GaAlAs layer successively epitaxially grown on the undoped GaAlAs layer on the substrate, as shown in Fig. 9 thereof. Finally, document EP-A-0 067 721 discloses a heterojunction semiconductor device based on a first semiconductor layer made of Ge with no impurity and a second layer made of a group III-V compound semiconductor having impurities, the two layers being separated by an interface. A HEMT device disclosed in DE-A-3 731 000 is comprised of two transistors configured in a CMOS configuration and fabricated on Si-Ge layers. The biasing conditions are such that two-dimensional electron and hole gases are created in the respective n and p channels in the Si-Ge layers. The device has a buffer region formed as three separate layers on the substrate and on which well layers are superposed. The uppermost layer of the device also serves as a barrier. In another complementary semiconductor device disclosed in EP-A-0 323 896, there is formed a CMOS configuration in which a p-channel layer is comprised of a continuously graded Si/Ge ratio. The purpose of this structure is essentially to overcome strain problems arising from lattice mismatching. Finally, EP-A-0 256 363 discloses an AlGaAs/GaAs complementary IC structure based on heterostructure insulated gate FETs, in which the n-channel transistor utilises an In x Ga 1-x semiconductor gate to reduce the threshold voltage of the n-channel FET and thus obtain low power circuit operation. SUMMARY OF THE INVENTION An object of the present invention is to provide a new structure HEMT type semiconductor device having a p-channel layer for a two dimensional hole gas and an n-channel layer for a two dimensional electron gas, the former layer being different from the latter layer. Another object of the present invention is to provide a new structure C-HEMT comprising a p-channel HEMT and an n-channel HEMT having low threshold voltages. A further object of the present invention is to provide a HEMT type semiconductor device operating a p-channel HEMT or an n-channel HEMT in a device structure having a gate electrode and two electrodes arranged on both sides of the gate electrode. The above mentioned and other object of the present invention are attained by providing a HEMT type semiconductor device according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more apparent from the description of the preferred embodiments set forth below the reference to the accompanying drawings, in which; Fig. 1 is a schematic sectional view of a conventional C-HEMT; Fig. 2 is a diagram showing drain currents and a gate leakage currents depending on a gate voltage; Fig. 3 is a schematic sectional view of a C-HEMT according to the first embodiment of the present invention; Fig. 4A is an energy band diagram of a semiconductor multilayer structure of a C-HEMT using a GaAs substrate; Fig. 4B is an energy band diagram of a p-channel HEMT of the C-HEMT using a GaAs substrate; Fig. 4C is an energy band diagram of an n-channel HEMT of the C-HEMT using a GaAs substrate; Fig. 5 is an energy band diagram of another semiconductor multilayer structure of a C-HEMT using a GaAs substrate; Fig. 6A is an energy band diagram of a semiconductor multilayer structure of a C-HEMT using an InP substrate; Fig. 6B is an energy band diagram of another semiconductor multilayer structure of a C-HEMT using an InP substrate; Fig. 7 is a graph showing switching properties of various semiconductor devices; Fig. 8A is a schematic sectional view of a HEMT type semiconductor device according to another embodiment, not forming part of the claimed invention; Fig. 8B is a schematic plane view of the device of Fig. 8A; and Figs. 9A and 9B are diagrams showing a drain current depending on a gate voltage, and an input signal and a corresponding output signal from the device of Fig. 8, respectively. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 3, a complementary HEMT type semiconductor device (C-HEMT) comprises a semiconductor multilayer structure epitaxially formed on a semi-insulating substrate 1; the multilayer structure is composed of a buffer layer 2 for improving crystallinity, a first semiconductor well layer 3 for a p-channel, a second semiconductor well layer 4 for an n-channel, and a potential barrier layer 5 for a potential barrier against carriers. These layers 2, 3, 4 and 5 are successively formed (deposited) on the substrate 1 by a continuous epitaxial growth method. On the layer 5, a threshold voltage controlling semiconductor layer 10 is epitaxially formed by the continuous epitaxial growth method and then is selectively removed by a suitable etching method. The semiconductor multilayer structure is separated with an isolation region 11 into a p-channel HEMT area (at a left side) and an n-channel HEMT area (at a right side). In the p-channel HEMT area, a Schottky gate electrode 12 is formed on the potential barrier layer 5 and is surrounded with an insulating layer 14 on its side, and a p-type source region 6 and a p-type drain region 7 are formed in the multilayer structure to extend to the buffer layer 2 from the barrier layer 5. In the n-channel HEMT area, a Schottky gate electrode 13 is formed on the threshold voltage controlling semiconductor layer 10 and they are surrounded with an insulating layer 15 on their side, and an n-type source region 9 and an n-type drain region 8 are formed in the multilayer structure to extend to the buffer layer 2 from the barrier layer 5. A source ohmic electrode 17 and a drain ohmic electrode 18 are formed on the p-type regions 6 and 7, respectively, and a source ohmic electrode 19 and an drain ohmic electrode 20, respectively. Furthermore, suitable interconnections (conductor lines) are formed to connect the drain electrodes 18 and 20 and to make a suitable circuit. Thus, the C-HEMT is complicated. As above-mentioned, the second well layer 4 can be made of a semiconductor material different from that of the first well layer 3 for the p-channel; suitable semiconductor materials are selected for the first and second well layers to lower both the threshold voltages of the p-channel HEMT and n-channel HEMT. Furthermore, where the potential barrier layer 5 is doped with impurities to retain ionized charges (i.e., impurities) after an outflow of free carriers, the ionized charge contributes an adjustment of potentials of the semiconductor well layers. When the layer 5 is doped with n-type impurities, positive ionized charges remain to shift the threshold voltage of both the p-channel and n-channel HEMTs toward negative. For the n-channel HEMT it is preferable to dope the threshold controlling layer 10 with n-type impurities with the result that positive ionized charges remain to shift the threshold voltage of the n-channel HEMT toward negative. It is possible to reverse the piling order of the semiconductor well layer for the p-channel layer and the semiconductor well layer for the n-channel layer, namely,the former layer for the p-channel layer is formed on the latter layer for the n-channel layer. However, where the n-channel semiconductor well layer lies under the p-channel well layer, a distance between the Schottky gate electrode 13 and the layer 3 becomes larger, which reduces the controllability of the n-HEMT. Furthermore, it is preferable that the distance between the p-channel semiconductor well layer and its gate electrode is almost equal to that between the n-channel semiconductor well layer and its gate electrode, since such a condition is suitable for operation uniformity of these HEMTs. Therefore, it is preferable to form the n-channel semiconductor well layer on the p-channel semiconductor well layer. Example 1 A C-HEMT according to the first embodiment of the present invention comprises a semi-insulating GaAs substrate 1, the semiconductor multilayer structure shown in Fig. 4A, and an n-type GaAs threshold voltage controlling layer 10, as shown in Fig. 3. The buffer layer 2 is made of undoped GaAs having a bandgap of about 1.42 eV; the p-channel semiconductor well layer 3 is made of undoped Ge having a bandgap of about 0.66 eV; the n-channel semiconductor well layer 4 is made of undoped In 0.25 Ga 0.75 As having a bandgap of about 1.1 eV, and the potential barrier layer 5 is made of n-type In 0.5 Ga 0.5 As having a bandgap of about 2.0 eV. In this case, conduction band bottoms and valence band top of the semiconductor layers 2 to 5 make a band diagram shown in Fig. 4A, and thus the potential difference between the valence band top of the p-channel layer 3 and the conduction band bottom of the n-channel layer 4 is about 0.39 eV. This value is much smaller than "about 1.0 eV" of the conventional C-HEMT shown in Figs. 1 and 2 and comprises a single semiconductor well layer for both the p-channel and n-channel HEMTs. Furthermore, both threshold voltages of the p-HEMT and n-HEMT can be lowered to nearly zero in the following manner. The GaAs buffer layer 2 having a thickness of, e.g., about 600 nm, is epitaxially formed on the semi-insulating GaAs substrate 1; the undoped Ge layer 3 having a thickness of, e.g., about 20 nm, is epitaxially formed on the buffer layer 2, and then the undoped In 0.25 Ga 0.75 As layer 4 has a thickness of about 10 nm. The n-type Al 0.5 Ga 0.5 As layer 5 having a thickness of, e.g., 18 nm and doped with n-type impurities (Si) of about 1.4 × 10 18 cm -3 , is epitaxially formed on the layer 4. In the p-channel HEMT, the Schottky gate electrode 12 is directly formed on the potential barrier layer 5, and thus a band diagram shown in Fig. 4B is obtained. The doped impurities (Si) in the layer 5 are ionized to generate positive stationary charges, which rises the valence band top of the p-channel semiconductor well layer 3 to a level almost equal to the Fermi level. Accordingly, the threshold voltage of the p-channel layer 3 becomes almost zero. A two dimensional hole gas (2DHG; hole carriers) is generated in a portion 3H of the p-channel layer 3 between the p-type regions 6 and 7. In the n-channel HEMT, the n-type GaAs layer 10 having a thickness of, e.g., 8 nm and doped with n-type impurities (Si) of about 1.4 × 10 -18 cm -3 , is epitaxially formed on the potential barrier layer 5. The Schottky gate electrode 13 is directly formed on the controlling layer 10, and thus a band diagram shown in Fig. 4 is obtained. The doped impurities (Si) in the layer 10 are also ionized to generate positive stationary charges, which lower the conduction band bottom of the n-channel semiconductor well layer 4 to a level almost equal to the Fermi level. Accordingly, the threshold voltage of the n-channel layer 4 becomes almost zero. A two dimensional electron gas (2DEG; electron carriers) is generated in a portion 4E of the n-channel layer 4 between the n-type regions 8 and 9. Therefore, the C-HEMT consisting of the p-channel HEMT and n-channel HEMT having zero threshold voltages and drain current curves, indicated with solid lines in Fig. 2, can be obtained. Where a semiconductor layer having a different composition from that of a semiconductor substrate is epitaxially grown on the semiconductor substrate, it is necessary to consider a lattice matching. When a lattice constant of the epitaxial layer is different from that of the substrate, a thickness of the epitaxial layer is limited so as to prevent misfit dislocations from generating. In such a case, the epitaxial layer has a strain therein. The C-HEMT shown in Figs. 3 and 4A to 4C is produced as follows, for example. The semi-insulating GaAs substrate (wafer) is set in a metal organic chemical vapor deposition (MOCVD) apparatus to successively and epitaxially grow the undoped GaAs buffer layer 2 (about 600 nm thick), the p-channel undopted Ge layer 3 (about 20 nm thick), the n-channel undoped In 0.25 Ga 0.75 As layer (about 10 nm thick), the n-type Al 0.5 Ga 0.5 As layer 5 (about 18 nm thick), and the n-type GaAs layer 10 (8 nm thick), on the substrate. Each of the n-type layers 5 and 10 is doped with Si ions of about 1.4 × 10 -18 cm -3 . Then B ions are selectively ion-implanted to reach the substrate 1 at an accelerated energy of about 140 keV and a dose of about 4 x 10 -13 cm -2 , so that the isolating region 11 is formed to separate the semiconductor multilayer structure to the p-channel HEMT area and the n-channel HEMT. By using a photomask and a suitable etching process, the n-type GaAs layer 10 is selectively dry-etched to leave a portion thereof as the threshold voltage controlling layer on the layer 5 at the n-channel HEMT area. Next, a WSi layer is deposited over the layers 5 and 10 by a sputtering process and is selectively etched by using a conventional photolithography to form the Schottky gate electrodes 12 and 13 having a gate length of about of 1 µm. A SiO 2 layer is deposited over the whole surface by a CVD process and is anisotropically etched to leave insulating layers 14 and 15 on sidewalls of the gate electrode 12 and of the gate electrode 13 and layer 10, respectively. Then, Be ions are selectively ion-implanted at an accelerated energy of about 40 keV and a dose of about 1.4 × 10 -13 cm -2 by using the gate electrode 12 and a suitable resist pattern as a mask, and Si ions are selectively ion-implanted at an accelerated energy of about 40 keV and a dose of about 1.4 × 10 -13 cm -2 by using the gate electrode 13 and another suitable resist pattern as a mask. Thereafter, a rapid thermal annealing is carried out to form the p-type regions 6 and 7 and the n-type regions 8 and 9, which extend to the buffer layer 2, as shown in Fig. 3. Then, an AuGe/Ni/Au layer is deposited and patterned by a vacuum evaporation method and a lift-off process to form the electrodes 19 and 20 on the n-type regions 9 and 8, and an AuZn/Au layer is deposited and patterned by a vacuum evaporation method and a lift-off process to form the electrodes 17 and 18 on the p-type 6 and 7, respectively. An annealing treatment is carried out at about 400°C, for 5 minutes, under a nitrogen atmosphere to complete the ohmic electrodes 17, 18, 19 and 20. Finally, suitable interconnections (conductive lines) of, e.g., aluminum or its alloy, are formed to make a complementary circuit (C-HEMT) including the p-channel HEMT and n-channel HEMT interconnected to each other. Example 2 On the semi-insulating GaAs substrate 1, another semiconductor multilayer structure shown in Fig. 5 is formed in the same manner as that in Example 1, except for the use of GaAs 0.75 Sb 0.25 for the p-channel layer 3 instead of the Ge layer. In this case, the multilayer structure comprises a buffer layer 2 which is made of undoped GaAs having a bandgap of about 1.42 eV and is 600 nm thick, a p-channel semiconductor well layer 3 which is made of undoped GaAs 0.75 Sb 0.25 having a bandgap of about 1.15 eV and is 20 nm thick, an n-channel semiconductor well layer 4 which is made of undoped In 0.25 Ga 0.75 As having a bandgap of about 1.1 eV and is 10 nm thick, and a potential barrier layer 5 which is made of p-type Al 0.5 Ga 0.5 As having a bandgap of about 2.0 eV and is 12 nm thick; layers 2 to 5 are successively and epitaxially formed on the substrate 1. The p-type layer 5 is doped with Be ions of 1.4 × 10 18 cm -3 to lower the threshold voltage of the p-channel HEMT to nearly zero. Furthermore, the threshold voltage controlling layer 10 is made of n-type GaAs and has a thickness of 44 nm, for the n-channel HEMT. The n-type layer 10 is doped with Si ions of about 1.4 × 10 18 cm -3 to lower the threshold voltage of the n-channel HEMT to nearly zero. Example 3 A C-HEMT having a structure shown in Fig. 3 is produced by using an InP substrate 1 instead of the GaAs substrate and by epitaxially growing a semiconductor multilayer structure shown in Fig. 6A or 6B on the substrate 1. The multilayer structure (Fig. 6A) comprises a buffer layer 2 which is made of undoped InP having a bandgap of about 1.35 eV and is 600 nm thick, a p-channel semiconductor well layer 3 which is made of undoped GaAs 0.5 Sb 0.5 having a bandgap of about 0.9 eV and is 15 nm thick, an n-channel semiconductor well layer 4 which is made of undoped In 0.5 Ga 0.5 As having a bandgap of 0.8 eV and is 15 nm thick, and a potential barrier layer 5 which is made of n-type In 0.5 Al 0.5 As having a bandgap of about 1.6 eV and is 17 nm thick. The n-type layer 5 is doped with Si ions of about 1.4 × 10 18 cm -3 to lower the threshold voltage of the p-channel HEMT to nearly zero. Furthermore, the threshold voltage controlling layer 10 made of n-type InP and being 14 nm thick is epitaxially formed on the layer 5 for the n-channel HEMT. The n-type layer 10 is doped with Si ions of about 1.4 × 10 18 cm -3 to lower the threshold voltage of the n-channel HEMT to nearly zero. As shown in Fig. 6B, the other multilayer structure comprises a buffer layer 2 which is made of undoped InP and is 600 nm thick, a p-channel semiconductor well layer 3 which is made of undoped GaAs 0.25 Sb 0.75 having a bandgap of about 0.7 eV and is 10 nm thick, an n-channel semiconductor well layer 4 which is made of undoped In 0.75 Ga 0.25 As having a bandgap of 0.6 eV is 10 nm thick, and a potential barrier layer 5 which is made of n-type In 0.5 Al 0.5 As and is 20 nm thick. The n-type layer 5 is doped with Si ions of about 1.4 × 10 18 cm -3 to lower the threshold voltage of the p-channel HEMT to nearly zero. Furthermore, the threshold voltage controlling layer 10 made of n-type InP and being 2 nm thick is epitaxially formed on the layer 5 for the n-channel HEMT. The n-type layer 10 is doped with Si ions of about 1.4 x 10 18 cm -3 to lower the threshold voltage of the n-channel HEMT to nearly zero. As is evident from Figs. 4A, 5, 6A and 6B, from the viewpoint of the hole energy, the top of the valence band of the p-channel semiconductor well layer 3 is lower than the tops of the buffer layer 2 and n-channel semiconductor well layer 4 and potential barrier layer 5, while from the viewpoint of electron energy, the bottom of the conduction band of the n-channel semiconductor well layer 4 is lower than the bottoms of the buffer layer 2, p-channel semiconductor well layer 3 and potential barrier layer 5. Therefore, carriers (holes or electrons) are injected into the semiconductor well layers 3 and 4 to confine the holes in the layer 3 and the electrons in the layer 4, respectively. Moreover, these semiconductor multilayer structure can lower the threshold voltages of both the p-channel and n-channel HEMTs of a conventional C-HEMT. The formation of the threshold voltage controlling layer and the modulation doping for the potential layer and the controlling layer can adjust the threshold voltages to almost zero. Figure 7 shows switching properties of various semiconductor devices. In Fig. 7, the abscissa indicates a power and the ordinate indicates a delay time. For example, when a conventional C-HEMT having a gate length of about 1 µm is operated at a supply voltage of 1 V or 1.5 V, it has a performance indicated with a point C1 or C2, respectively. These performances are equivalent to those of C-MOS. The C-HEMT according to the present invention having a gate length of about 1.0 or 0.25 µm will operate at a supply voltage of 1 V, and it would have a performance indicated with a point P1 or P2, respectively. Thus, it is possible to obtain a C-HEMT having improved characteristics. According to a second embodiment of the present invention, the above-mentioned semiconductor multilayer structure is utilized to provide a HEMT type semiconductor device serving as a mutilfunction element, as shown in Figs. 8A, 8B, 9A and 9B, not forming part of the claimed invention. As shown in Fig. 8A, the HEMT type semiconductor device comprises a semiconductor substrate 31 of, e.g., semi-insulating GaAs, a buffer layer 32 of, e.g, undoped Ge, a p-channel semiconductor well layer 33 of, e.g., undoped In 0.25 Ga 0.75 As, and a potential barrier layer 35 of, e.g., n-type Al 0.5 Ga 0.5 As; layer 32 to 35 being successively and epitaxially grown on the substrate 31 by an MOCVD method. Such a multilayer structure is similar to that shown in Fig. 4A of the Example 1. the n-type Al 0.5 Ga 0.5 As layer 35 is doped with Si ions of about 1.4 × 10 18 cm -3 and has a thickness of about 22 nm. It is possible to use the semiconductor multilayer structure shown in Figs. 5, 6A and 6B, and to reverse the p-channel layer and the n-channel layer. A Schottky gate electrode 36 of, e.g., WSi, is selectively formed on the potential barrier layer. Then, Be ions are selectively ion-implanted at an accelerated energy of about 40 keV and a dose of about 1.4 × 10 13 cm -2 by using a suitable resist pattern as a mask, and Si ions are selectively ion-implanted at an accelerated energy of about 40 keV and a dose of about 1.4 × 10 13 cm -2 by using another suitable resist pattern as a mask to form p-type regions 37a to 37f and n-type regions 38a to 38f, as shown in Figs. 8A and 8B. Each of the doped regions extends to the buffer layer 32. The p-type regions 37a, 37b and 37c and the n-type regions 38a, 38b and 38c are alternately arranged to make a line on one side of the gate electrode 36, while the p-type regions 37d, 37e and 37f and the n-type regions 38d, 38e and 38f are alternately arranged to make a line on the other side of the gate electrode 36. Thereafter, a rapid thermal annealing is carried out. Then, a metal (e.g., Au) layer is deposited and patterned by a vaccum evaporation method and a lift-off process to form ohmic electrodes 39 and 40 on the doped regions in the shape of two stripes. When the obtained HEMT type semiconductor device is controlled with a gate voltage applied on the Schottky gate electrode, the device operates as shown in Figs. 9A and 9B. Namely, at a negative gate voltage the two dimensional hole gas is generated in a portion of the p-channel semiconductor well layer 33 and the p-channel HEMT operates, while at a positive gate voltage, the two dimensional electron gas is generated in a portion of the n-channel semiconductor well layer 34 and the n-channel HEMT operates as shown in Fig. 9A. In this case, Fig. 9A is obtained under conditions of about a 10 µm gate width and about a 1 µm gate length, and the threshold voltages of the p-channel and n-channel HEMTs are not reduced to zero. Therefore, an input of the gate voltage varies at an oscillation between a negative voltage and a positive voltage, with the result that an output of the drain current from the device varies, as shown in Fig. 9B. When the input (gate) voltage varies from positive to negative, the output current is obtained as a full-wave rectification state, whereby a double frequency generator can be constituted of only the obtained device (element) provided with one gate electrode and two ohmic electrodes.

Claims: A complementary HEMT type semiconductor device comprising: a semiconductor substrate (1); a buffer semiconductor layer (2) formed on said substrate; a first semiconductor well layer (3) formed on said buffer layer and serving as a first conductivity type channel layer; a second semiconductor well layer (4) formed on said first well layer and serving as a second conductivity type opposite said first conductivity, channel layer; and a potential barrier layer (5) formed on said second well layer and forming a potential barrier for carriers; an isolation region (11) extending from said potential barrier layer to said semiconductor substrate for a p-channel HEMT area and an n-type channel HEMT area; p-type regions (6, 7) extending from said potential barrier layer to said buffer layer within the p-channel HEMT area; a gate electrode (12) formed on said potential barrier layer and located between said p-type regions; n-type regions (8, 9) extending from said potential barrier layer to said buffer layer within the n-channel HEMT area; characterised in that it further comprises; a threshold voltage controlling semiconductor layer (10) selectively formed on said potential barrier layer between said n-type regions. and a gate electrode (13) on said threshold voltage controlling layer. A semiconductor device according to claim 1, wherein said buffer layer (2) serving as a potential barrier for carriers flowing through said first conductivity type channel layer and other carriers flowing through said second conductivity type channel layer. A semiconductor device according to claim 1 or 2, wherein said substrate (1) is GaAs, one of said first well layer (3) and second well layer (4) is one of Ge and GaAsSb, the other is InGaAs, said potential barrier layer (5) is one of AlGaAs and AlInGaP, and said threshold voltage controlling layer (10) is GaAs. A semiconductor device according to claim 1 or 2, wherein said substrate (1) is InP, one of said first well layer (3) and second well layer (4) is of GaAsSb, the other is of InGaAs, said potential barrier layer (5) is one of AlInAs, AlGaAs and AlGaAsSb, and said threshold voltage controlling layer (10) is InP. A HEMT type semiconductor device according to claim 1 or 2, wherein said first well layer is used for generating a two dimensional hole gas of a p-channel, and said second well layer is used for generating a two dimensional electron gas of an n-channel. A HEMT type semiconductor device according to claim 1 or 2, wherein said first well layer is used for generating a two dimensional electron gas of an n-channel, and said second well layer is used for generating a two dimensional hole gas of a p-channel. A semiconductor device according to any of claims 1 to 6, said potential barrier layer (5) being doped with n-type impurities. A semiconductor device according to any of claims 1 to 7, said threshold controlling layer (10) being doped with n-type impurities.

Inventors: TAKIKAWA MASAHIKO, TAKIKAWA, MASAHIKO, Takikawa, Masahiko, c/o FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L27