MOS composite static induction thyristor

Abstract: In a MOS controlled power device, or MOS composite a static induction thyristor, an static induction thyristor (SI thyristor) unit, a MOS transistor connected in cascode relation to the SI thyristor unit and a voltage regulation element, such as a Zener diode, are merged onto the single monolithic chip. The SI thyristor unit has a cathode region of first conductivity type having high impurity concentration, an anode and a gate regions of second conductivity type having high impurity concentration, and a channel region of first conductivity type having low impurity concentration. The MOS transistor has a drain region which is the same region as the cathode region, a well or a base of second conductivity type formed adjacent to the channel region of the SI thyristor unit, and a source region of first conductivity type having high impurity concentration. The source region is formed within the well or above the base. The voltage regulation element comprises a first semiconductor region of second conductivity type, and a second semiconductor region of first conductivity type, both having high impurity concentration.

Description: BACKGROUND OF THE INVENTION The present invention relates to a novel structure of a static induction thyristor (hereinafter referred to as an "SI thyristor") and, more particularly, to a MOS composite static induction thyristor in which a MOS transistor, a diode and an SI thyristor are integrated onto a single monolithic chip. In recent years, various MOS controlled power devices or MOS gated power devices such as MGT, MCT, EST, DMT have been proposed. However, these MOS composite devices have, as a main thyristor unit, a conventional device such as GTO. Since ON-voltage of these MOS composite devices is finally determined by a characteristic of the main thyristor unit, above MOS composite device combined with the conventional thyristor such as GTO has disadvantages that the ON-voltage and conduction loss are high. Further, these conventional MOS composite device has a disadvantage that it is difficult to bring the device to high frequency use. In view of the above, a MOS composite SI thyristor, or MOS controlled SI thyristor (MCSITH) in which high efficiency, high-speed operation are expected and which comprises, as a main thyristor unit, an SI thyristor unit, whose ON-voltage and, accordingly, conduction loss are small and high frequency operation and high speed switching are possible, has already been proposed by the Applicant of the present invention in Japanese Patent Laid-Open No. 3-292770. The MCSITH is one having a structure in which a MOS transistor is integrated at a location between a gate and a cathode of a normally-off SI thyristor, as shown in Fig. 20 and Fig. 21 (a cross-sectional view taken along a line A - A in Fig. 20) of the attached drawings. Fig. 20 is a top plan view, while Fig. 21 is a cross-sectional view taken along a line A - A in Fig. 20. As shown in Figs. 20 and 21, an SI thyristor is formed in which an n + region 23 is a cathode, a p + region 21 is an anode, a p + region 31 under a floating condition is a gate, and an n - region 22 is a channel. A p + region 31 simultaneously serves as a source of a pMOS transistor in which a p + region 32 is a drain, and a polycrystalline silicon layer 25 is a gate electrode. Turning-on of the MCSITH is realized by the fact that positive potential is applied to a capacity formed by the polycrystalline silicon layer 25 and an oxide film 26 that is an insulating film above the p + gate region 31, to reduce the height of a potential barrier formed in the n - channel region 22 by means of capacitive coupling (static induction effects). Turning-off is realized by the fact that the pMOS transistor is conducted to short-circuit the p + gate region 31 and the n + cathode region 23 to each other, to withdraw a hole through the p + gate region 31. However, this MCSITH has the following disadvantages. That is, if impurity concentration of the n - channel region 22 is brought approximately to 10 13 cm -3 in order that the main thyristor unit has a normally-off characteristic, it is required that the spacing between the adjacent p + gate regions 31 and 31 is equal to or less than approximately 6 µm. Assuming that diffusion width of the n + cathode stripped region 23 is 2 µm, then it is required that an interval between the n + cathode region 23 and the p + gate region 31 is narrowed to 2 µm. Accordingly, a fine processing technique is required in order to merge a MOS transistor in a portion between the n + cathode region 23 and the p + gate region 31. For this reason, manufacturing is difficult, and a yield is low. SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOS composite SI thyristor, having a novel structure, which has an essentially low ON-voltage, therefore, a small conduction loss, which is easy to get a high frequency and a high speed operation, in which manufacturing is easy. It is another object of the invention to provide a MOS composite SI thyristor having a novel structure, in which a gate loss can be reduced, and a gate drive circuit can be simplifed. According to the invention there is provided a single monolithic semiconductor chip wherein a static induction thyristor unit, a MOS transistor and a voltage regulation element are merged, thereby forming a MOS composite static induction thyristor, said static induction thyristor unit having at least a cathode region of first conductivity type having high impurity concentration, an anode region and a pair of gate regions of second conductivity type having high impurity concentration, said gate regions being positioned to opposite sides of said cathode region and laterally spaced therefrom, and a channel region of first conductivity type having low impurity concentration; said MOS transistor having at least a drain region that is the same region as said cathode region, a well region or a base region of second conductivity type formed adjacent to said channel region of said static induction thyristor unit, a source region of first conductivity type having high impurity concentration formed within said well region or above said base region, respectively, a gate insulating film formed on a surface of said well region or base region between said source region and drain region, and a MOS gate electrode formed on said gate insulating film; said voltage regulation element having a first semiconductor region of second conductivity type having high impurity concentration, and a second semiconductor region of first conductivity type having high impurity concentration; wherein said MOS composite static induction thyristor has at least a structure in which said first semiconductor region and said source region are connected to each other through a first wiring layer of high electrical conductivity, and said second semiconductor region and said gate regions are connected to each other through a second wiring layer of high electrical conductivity; whereby a main current flowing between said anode and cathode regions is controlled by a control voltage applied to said MOS gate electrode. According to the invention there is further provided a single monolithic semiconductor chip wherein a static induction thyristor unit, a MOS transistor and a voltage regulation element are merged, thereby forming a MOS composite static induction thyristor, said static induction thyristor unit having at least a cathode region of first conductivity type having high impurity concentration, an anode region, and a pair of first gate regions of second conductivity type having high impurity concentration, a pair of second gate regions of first conductivity type having high impurity concentration, said first gate regions, and said second gate regions, being positioned to opposite sides of said cathode region and laterally spaced therefrom, and a channel region of first conductivity type having low impurity concentration, thereby forming a double-gate static induction thyristor unit; said MOS transistor having at least a drain region that is the same region as said anode region, a well region of first conductivity type formed adjacent to said channel region of said static induction thyristor unit, a source region of second conductivity type having high impurity concentration formed within said well region, a gate insulating film formed on a surface of said well region between said source region and drain region, and a MOS gate electrode formed on said gate insulating film; said voltage regulation element having a first semiconductor region of first conductivity type having high impurity concentration, and a second semiconductor region of second conductivity type having high impurity concentration; wherein said MOS composite static induction thyristor has at least a structure in which said first semiconductor region and said source region are connected to each other through a first wiring layer of high electrical conductivity, and said second semiconductor region and said second gate regions are connected to each other through a second wiring layer of high electrical conductivity, whereby a main current flowing between said anode and cathode regions is controlled by a control voltage applied to at least one of said MOS gate electrode or said first gate regions. With the above arrangement of the invention, since the MOS transistor is integrated on the single monolithic chip by cascode connection, inductance of the wiring can be reduced and, as a result, extremely high speed switching is made possible. Further, since the SI thyristor unit having a characteristic of a normally-on type or approximately the middle of normally-on and normally-off type can be employed as the main thyristor unit, it is possible to take a gate interval wide. Since it is easy to merge the MOS transistor at the wide space in the gate interval, manufacturing is easy, and device yield is high. Moreover, since the SI thyristor unit can be driven without the use of both positive and negative power sources for the trigger pulse and the quench pulse respectively, the gate drive circuit can be simplified. Furthermore, since the MOS gate terminal of composite devices and the gate regions of the main thyristor unit are electrically separated from each other by the MOS transistor, a gate loss of SI thyristor unit is extremely reduced. Needless to say, since the SI thyristor unit is the main thyristor unit, the above arrangement is essentially low in ON-voltage and, accordingly, conduction loss is small and is easy in being brought to high frequency operation. Though the SI thyristor unit having a characteristic of a normally-on type or approximately in the middle of normally-on and normally-off type is employed, the normally-off characteristic as a whole is obtained, and a large power handling capability and a low ON-resistance characteristic of the normally-on SI thyristor are still maintained. The MOS composite SI thyristor according to the present invention is very convenient in application to various circuits represented by an inverter. In connection with the above, it is possible to use the normally-off SI thyristor unit, if the latter is superior in trigger sensitivity. However, the deep normally-off type with very narrow gate interval, which is strong in off-characteristic is inadequate, since the turning-off time is lengthened or SI thyristor cannot be turned off. As described above, the MOS composite SI thyristor according to the present invention has practical advantages such that manufacturing is easy, a switching speed is high, a gate loss can be reduced, and a gate drive circuit can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a first embodiment of a MOS composite SI thyristor according to the present invention, which shows a cascode connection of a SI thyristor and a MOS transistor; Fig. 2 is a top plan view showing a specific or exemplified structure into which the first embodiment is integrated; Fig. 3 is a cross-sectional view taken along a line B - B in Fig. 2; Fig. 4 is a cross-sectional view of a second embodiment of the present invention; Fig. 5 is a cross-sectional view of a third embodiment of the present invention; Fig. 6 is a cross-sectional view of a fourth embodiment of the present invention; Fig. 7 is a top plan view of a fifth embodiment of the present invention; Fig. 8 is a top plan view of a sixth embodiment of the present invention; Fig. 9 is a cross-sectional view taken along a line C - C in Fig. 8; Fig. 10 is a cross-sectional view taken along a line D - D in Fig. 8; Fig. 11 is a partially cut-away perspective view of a seventh embodiment according to the present invention; Fig. 12 is a partially cut-away perspective view of an eighth embodiment according to the present invention; Fig. 13 is a partially cut-away perspective view of a ninth embodiment according to the present invention; Fig. 14 is a circuit diagram of a tenth embodiment according to the present invention; Fig. 15 is a cross-sectional view showing a specific structure into which the tenth embodiment is integrated; Fig. 16 is a circuit diagram of an eleventh embodiment according to the present invention; Fig. 17 is a cross-sectional view showing a specific structure into which the eleventh embodiment is integrated; Fig. 18 is a cross-sectional view taken along a line E - E in Fig. 17; Fig. 19 is a cross-sectional view of a twelfth embodiment according to the present invention; Fig. 20 is a top plan view of a conventional example; and Fig. 21 is a cross-sectional view taken along a line A - A in Fig. 20. DESCRIPTION OF THE EMBODIMENTS Various embodiments of the invention will hereunder be described in detail with reference to the accompanying drawings. Fig. 1 is a circuit diagram of a first embodiment of a MOS composite SI thyristor according to the present invention. Such a circuit is disclosed in JP-A-2 026 276. Fig. 2 is a top plan view showing a specific structure into which the MOS transistor, SI thyristor unit and diode are integrated, while Fig. 3 is a cross-sectional view taken along a line B - B in Fig. 2. As shown in Fig. 1, the MOS composite SI thyristor is arranged as follows. That is, an SI thyristor unit 1 has a cathode 23 to which a drain of a MOS transistor (n-channel MOS transistor) is connected in series, or in cascode relation. The SI thyristor unit 1 has a gate 31 to which a source 52 of a MOS transistor 2 is connected through a voltage regulation element such as a Zener diode 3. The SI thyristor unit 1, the MOS transistor and the Zener diode 3 are merged onto a single monolithic chip. As shown in Figs. 2 and 3, a cathode region of the SI thyristor unit 1 and a drain region of the n-channel MOS transistor 2 are merged into the same n + region 23. A p + region 21, the p + region 31 and an n - region 22 are the anode, the gate and the channel region of the SI thyristor unit 1, respectively. Each of the n + regions 52 is a source region of the MOS transistor 2 and is formed within a corresponding p-well 51. Further, a polycrystalline silicon layer 251 is a gate electrode of the MOS transistor 2 whose gate oxide film is a thin portion of each of oxide films 26. Further, a p-n junction Zener diode 3 consisting of P + region 62 and n + region 61 is used as a voltage regulation element. In this embodiment, however, the Zener diode 3 is formed within each of the p + gate regions 31. The n + region 61 of the Zener diode and the p + gate region 31 are short-circuited to each other through a silicide film 71 made of a refractory metal such as WSi 2 , TiSi 2 . The silicide film 71 also reduces a resistance of the p + gate region 31. The reference numeral 211 denotes an anode electrode, while 231 denotes a cathode electrode. The present embodiment is constructed as described above. Accordingly, when positive potential is applied to the p + anode region 21, voltage (V nMOS ) between the drain and the source of the MOS transistor 2 rises. The following difference between the above voltage (V nMOS ) and the Zener voltage (V ZD ): V GK = V nMOS - V ZD is applied to a location between the gate region 31 and the cathode region 23 of the SI thyristor as a reverse bias. Even if the SI thyristor unit 1 has a normally-on characteristic, the SI thyristor indicates a normally-off characteristic as a whole. When positive voltage equal to or more than a threshold value is applied to the gate electrode 251 of the MOS transistor 2, the MOS transistor 2 is shifted from the off-state to the on-state, and a value of V nMOS is reduced during the process of the shifting. Simultaneously therewith, V GK (= V nMOS - V ZD ) is also reduced and, accordingly, voltage capable of being blocked by the SI thyristor is reduced. From the time V nMOS is reduced to a minimum value, V GK becomes negative. Since the location between the gate area 31 and the cathode area 23 of the SI thyristor unit 1 is forward-biased, the SI thyristor unit 1 is turned on. Next, when an off-bias is applied to the gate 251 of the MOS transistor 2, the MOS transistor 2 is first turned off. Then, V nMOS rises, and terminal voltage between the gate area 31 and the cathode area 23 is reversely biased. Simultaneously, the main current flowing from the anode area 21, via the cathode area 23 and the source area 52 of the MOSFET, to the cathode electrode 231 changes to flow through the gate area 31 of the SI thyristor unit 1 and the Zener diode 3, so that the SI thyristor unit 1 is turned off. Operation principle of the present embodiment has been described above. Since, however, the present embodiment is arranged such that the MOS transistor 2 is merged onto a single monolithic chip by cascode connection, inductance of the wiring can be reduced and, as a result, extremely high speed switching is possible. Further, since the SI thyristor unit 1 having a characteristic of the normally-on or approximately the middle between the normally-on and the normally-off type serves as the main thyristor unit, it is possible to widen the gate spacing of the SI thyristor. Since it is easy to form the MOS transistor 2 at the wide portion of the gate interval, manufacturing is easy, and device yield is high. Moreover, since the SI thyristor unit 1 can be driven without using both positive and negative power sources for a trigger and a quench pulse respectively, a gate drive circuitry can be simplified. Further, since the gate terminal 251 of this MOS composite devices and the gate region 31 of a main thyristor unit are electrically separated from each other by the MOS transistor 2, a gate loss is reduced extremely. In connection with the above, as shown in Figs. 2 and 3, the n + cathode region 23 is not required to be located at a center between the paired p + gate regions 31, but may be shifted to the left. Enough space is allowed for dimensions defined by photolithography by this cathode shifted arrangement. That is, since a wide space is afforded between the n + cathode region 23 and the p + gate region 31, on the right of the n + cathode region 23, no critical mask alignment are required and, as a result, manufacturing is further facilitated. On the other hand, even if the n + cathode region 23 is shifted to the right between the paired gate regions 31, there can be provided similar advantages. In fact, as shown in Figs. 2 and 3, if the impurity concentration of the n - channel region 22 is 2 x 10 13 cm -3 , the spacing between the adjacent p + gate regions 31 and 31 is 10 µm, a diffusion width of each of the n + cathode region 23 and each of n + source region 52 are 2 µm, respectively, the gate length of the polycrystalline silicon should be 2 µm. Well known manufacturing method of a standard MOS transistor is used to easily manufacture this embodiment. In this embodiment, it is desirable to employ a MOS-SIT whose gate length is equal to or less than 1 µm, as a nMOS transistor, since the ON-resistance is further reduced. Fig. 4 is a cross-sectional view of a second embodiment of the invention, in which each of n + cathode regions 23 is arranged at a center of n - channel regions, that is, at a center between adjacent p + gate regions 31 and 31, and nMOS transistors (hereinafter referred to as "nMOS") are arranged at both sides of the n + cathode region 23. Since two nMOSs per one channel of the main thyristor are connected, an effective gate width becomes twice, and the ON-resistance of the nMOS becomes 1/2, as compared with the first embodiment. Moreover, a U-shaped groove is formed between an n + source region 52 and the p + gate region 31, and is plugged by an oxide film 26. Accordingly, it is possible to raise the break down voltage between the cathode and the gate. Further, since a polycrystalline silicon gate electrode 251 is formed as a common electrode for the two nMOSs, a wiring width of the polycrystalline silicon gate electrode 251 can increase approximately thrice as compared with the first embodiment. As a result, the gate resistance of the nMOS is reduced. Thus, this embodiment is adequate for high-speed operation. Fig. 5 is a cross-sectional view of a third embodiment of the invention, which is arranged such that an n-buffer layer 42 is formed adjacent to p + anode regions 21. In this case, the impurity concentration of the n-buffer layer 42 is 1 x 10 15 ∼ 1 x 10 17 cm -3 , and that of an n - channel area (or i-area) 22 is of 1 x 10 11 ∼ 1 x 10 12 cm -3 which is extremely low, and electric field strength between the gate and the anode is uniform. Hence, it can be formed such that a depletion layer from gate areas 31 does not reach the anode areas 21. Accordingly, both a maximum forward blocking voltage and a switching speed can increase. Further, forward voltage drop (ON voltage) can also be reduced. If the maximum forward blocking voltage may be the same as with no n - buffer layer 42, it is sufficient that the thickness of the n - region 22 is half. Thus, the ON voltage is naturally reduced, and the switching speed is raised. The above-described n-buffer structure can be apply to a fourth embodiment (Fig. 6), a seventh embodiment (Fig. 11), an eighth embodiment (Fig. 12), an eleventh embodiment (Fig. 18), and a twelfth embodiment (Fig. 19). It is of course that, other than the above embodiments, the n-buffer structure is applicable also to other embodiments except for a tenth embodiment (Fig. 15). The embodiment illustrated in Fig. 5 is an SI anode short structure in which each of p + anode areas 21 is one of the sections formed by dividing a p + anode region, and an n + short region 24 is formed between the sections. In this case, by potential of the p + anode region 21 and potential of the n + short region 24, electrons can be swept to the n + short region 24. Accordingly, a tail current at turning-off is reduced and high-speed switching is possible. In this connection, a pitch of the divided p + anode region 21 is selected to a value equal to or less than twice the diffusion length of the electrons. The above-described SI anode short structure is applicable to a fourth embodiment (Fig. 6), a seventh embodiment (Fig. 11), an eighth embodiment (Fig. 12), an eleventh embodiment (Fig. 18), a twelfth embodiment (Fig. 19), and other embodiments except for a tenth embodiment (Fig. 15). In the second embodiment, a polycrystalline silicon gate electrode 251 is also formed above the n + cathode region 23 (refer to Fig. 4). In the present embodiment, however, as shown in Fig. 5, the polycrystalline silicon gate electrode 251 is divided into two sections which are formed only above the nMOS channel. Accordingly, there can be produced an advantage that the n + drain 23 and source regions 52 are simultaneously implanted with the gate electrode 251 by a self-alignment process using the gate electrode 251 as a ion-implantation mask, similarly to a standard MOS manufacturing process. Fig. 6 is a cross-sectional view showing a fourth embodiment of the invention, a so-called VMOS structure, in which a gate oxide film 26 is formed on a side wall of a V-shaped groove (V-groove), and the polycrystalline silicon gate electrode 251 is formed within the V-groove. This embodiment has the following advantages. That is, a thickness and an impurity concentration of a p-base layer 53 can be selected, independently of spacing between gates of a main thyristor unit. Accordingly, design of an nMOS is facilitated, and design of a MOS composite SI thyristor is also facilitated as a whole. Particularly, since the present embodiment has a structure suitable for short-channeled nMOS structure, high speed operation at low ON-resistance is possible. The structure should not be limited to the V-groove, but, it is needless to say, also to a U-groove (UMOS). Fig. 7 is a top plan view of a fifth embodiment of the invention, which is arranged such that an nMOS is formed in a longitudinal direction of a planar pattern (stripe) of an n + cathode region 23. This embodiment has an advantage that a gate length of the nMOS can be selected independently of spacing between p + gate regions of the main thyristor unit, but, has a disadvantage that it is impossible to increase a gate width of nMOS. Although a Zener diode having a p + region 62 and an n + region 61 is formed between adjacent p + gate regions 31 in Fig. 7, the area of Zener diode may intrude into the p + gate region. The n + region 61 and the p + gate regions 31 are connected to each other by metal wiring 72. The aforesaid first to fifth embodiments are arranged such that the main thyristor unit is a surface-gate SI thyristor unit. In the next sixth embodiment, however, the main thyristor unit is a buried gate SI thyristor. Fig. 8 is a top plan view of the sixth embodiment, and Fig. 9 is a cross-sectional view taken along a line C - C in Fig. 8, while Fig. 10 is a cross-sectional view taken along a line D - D in Fig. 8. An nMOS consisted of each of n + source regions 52 formed within a corresponding p-well 51, an n + drain region 23 serving also as an n + cathode region of an SI thyristor unit, and a gate electrode 251 can use almost all the surface on the cathode side. Accordingly, an area occupying rate of nMOS is high, a degree of freedom of nMOS design is large, and an ON-resistance of the nMOS can be reduced. Further, since a manufacturing process of the nMOS may entirely be the same as that of standard MOSs, manufacturing is extremely easy. A plurality of p + gate regions 31 and n + regions 61 forming a Zener diode are connected to each other by a metal wiring layer 72 at a bottom of a U-groove 80. Figs. 11 through 13 are partially cut-away perspective views of seventh to ninth embodiments of the invention, respectively, each of which is arranged such that a main thyristor unit is a recessed-gate SI thyristor. In the seventh embodiment (Fig. 11), a pair of p + gate regions 31 are formed in the entire bottom of a U-groove. In the eighth embodiment (Fig. 12) and the ninth embodiment (Fig. 13), however, the p + gate regions 31 are formed respectively only on side walls of the U-grooves, and thick oxide films 26 are formed respectively at bottoms of gate electrodes 78 and 79. By this structure, capacitance between the gate and the anode is extremely low, and high-speed operation is possible. In the seventh and eighth embodiments, an nMOS is a UMOS in which a gate oxide film is formed on a side wall of a second U-groove 82 at a center of a convexed channel 22. The nMOS comprises n + source regions 52, p-base 53, n + drain regions 23 serving also as cathode regions of an SI thyristor unit, and a gate electrode 251. However, the nMOS may be a VMOS as the fourth embodiment (Fig. 6). Similarly to the fourth embodiment, design parameters of the nMOS in the seventh and eighth embodiments can be selected independently of main thyristor dimensions, and the degree of freedom of design is large. Accordingly, it is easy to reduce a channel length and an ON-resistance of the nMOS, and high-speed operation is easily obtained. A Zener diode is formed by a p + region 62 and an n + region 61. In the seventh and eighth embodiments, however, the n + region 62 and the gate electrodes 78 of the SI thyristor unit are connected to each other at location within the U-groove by a polycrystalline silicon wiring layer 72 extending up to the side walls of the U-groove. In the ninth embodiment, since the gate electrode 79 fills up the U-groove by selective CVD of W (tungsten), the n + region 61 and the gate electrode 79 are wired on the same plane, and there is no fear of wire breaking. By a structure of the ninth embodiment in which the U-groove is filled up by the gate electrode, a gate resistance of the SI thyristor unit is extremely low, and super high frequency operation is possible. The ninth embodiment has a double-gate SI thyristor unit in which p + region 31 is a first gate of recessed structure, and the n + region 99 is a second gate of a buried gate structure. There is no turn-off tail current, and high-speed operation is possible with a low ON-resistance. Fig. 14 is a circuit diagram of a tenth embodiment, while Fig.15 is a cross-sectional view of a specific structure into which the tenth embodiment is integrated. The tenth embodiment is arranged such that a Zener diode 3 is connected to a location between a second gate 99 and an anode electrode 211 of a double gate SI thyristor unit 11; a p + anode region 21 serves as a p + drain region and a p + region 89 is a source area so that a MOSFET 12 is formed within an n-well 88. The source region 89 and the anode electrode 211 are connected to each other. Although, in Fig. 15, the first gate is a surface gate structure, while a second gate is a buried gate structure, both the first and second gates may be a buried type, and the first gate may be a recessed gate. The first and second gates may be a combination other than those mentioned above. The combination should be selected in accordance with objects. An n + region 85 and a p + region 86 cooperate with each other to form the Zener diode 3. The second gate region 99 and the p + region 86 are connected to each other by wiring 98 consisting of polycrystalline silicon. Of course, the Zener diode 3 and an nMOS 2 may be connected between the first gate region 31 and the n + cathode region 23, as illustrated in Fig. 1. Fig. 16 is a circuit diagram of an eleventh embodiment of the invention, and Fig. 17 is a cross-sectional view of a specific structure into which the eleventh embodiment is integrated, while Fig. 18 is a cross-sectional view taken along a line E - E in Fig. 17. The eleventh embodiment is arranged such that a depletion mode (normally-ON type) p-channel MOS transistor (hereinafter referred to as "pMOS") 14 is connected in parallel to a Zener diode 3 which is connected between a p + gate region 31 and a cathode electrode 231, and a gate electrode of the pMOS 14 is connected to a gate electrode of the nMOS. Both the pMOS 14 and the nMOS 2 are planar structure. The pMOS composed of a p + source region 63 and p + drain region 31 is formed within a n-well 59. Similarly to the aforesaid third embodiment, a n + region 23 serves both as a cathode region of the SI thyristor unit 1 and as the drain region of the nMOS. The nMOS 2 is formed within a p-well 51, and an n + region 52 is a source region of the nMOS 2. In this embodiment, when positive voltage is applied to a gate electrode 251, the nMOS 2 is turned on. If voltage V nMOS between the drain and the cathode becomes smaller than breakdown voltage V ZD of the Zener diode 3, a forward bias is applied between the gate region 31 and the cathode region 23 of the SI thyristor unit 1. Accordingly, the SI thyristor is turned on. At this time, the pMOS 14 is under off state. Next, when the voltage of the gate electrode 251 is brought to zero or to off-bias voltage for the nMOS 2, the nMOS 2 is turned off, and the pMOS 14 is turned on, so that main current flowing through the channel of the SI thyristor unit 1 is withdrawn from the p + gate area 31 of the SI thyristor unit 1 through the pMOS 14 and flows to the cathode electrode 231. Accordingly, the SI thyristor unit 1 is turned off. At this turning off, turning-off current flows also to the Zener diode 3, and a reverse-bias is applied between the gate and the cathode of the SI thyristor unit 1 by the following difference between the breakdown voltage (V ZD ) of the Zener diode and the voltage (V nMOS ) between the drain and the source of the nMOS: V GK = V nMOS - V ZD Accordingly, the ON-voltage of the pMOS is selected to a value substantially equal to or slightly smaller than V ZD . This embodiment is effective in a case where the main thyristor unit has a characteristic intermediate between normally-off and normally-on. Fig. 19 is a cross-sectional view of a twelfth embodiment of the invention. The twelfth embodiment has a circuit arrangement similar to that of the eleventh embodiment, but is different in that the twelfth has a so-called UMOS, or vertical structure in which a polycrystalline silicon gate 251 is formed in a U-groove. It is easy by the present embodiment to decrease a channel length of the MOS transistor so that high-speed operation is possible with low ON-resistance. As shown in Fig. 19, an n + source region 52 of the nMOS 2 is formed above a p-base 53, and an p + source region 63 of the pMOS 14 is formed above the n-base 58. In the above-described eleventh and twelfth embodiments, the structure in which the pMOS 14 and the nMOS 2 is reversed and they are connected to the SI thyristor unit 1 are also effective.

Claims: A single monolithic semiconductor chip wherein a static induction thyristor unit, a MOS transistor and a voltage regulation element are merged, thereby forming a MOS composite static induction thyristor, said static induction thyristor unit (1) having at least a cathode region (23) of first conductivity type having high impurity concentration, an anode region (21) and a pair of gate regions (31) of second conductivity type having high impurity concentration, said gate regions (31) being positioned to opposite sides of said cathode region (23) and laterally spaced therefrom, and a channel region (22) of first conductivity type having low impurity concentration; said MOS transistor (2) having at least a drain region (23) that is the same region as said cathode region (23), a well region (51) or a base region (53) of second conductivity type formed adjacent to said channel region (22) of said static induction thyristor unit (1), a source region (52) of first conductivity type having high impurity concentration formed within said well region (51) or above said base region (53), respectively, a gate insulating film formed on a surface of said well region (51) or base region (53) between said source region (52) and drain region (23), and a MOS gate electrode (251) formed on said gate insulating film; said voltage regulation element (3) having a first semiconductor region (62) of second conductivity type having high impurity concentration, and a second semiconductor region (61) of first conductivity type having high impurity concentration; wherein said MOS composite static induction thyristor has at least a structure in which said first semiconductor region (62) and said source region (52) are connected to each other through a first wiring layer (231) of high electrical conductivity, and said second semiconductor region (61) and said gate regions (31) are connected to each other through a second wiring layer (71,72) of high electrical conductivity; whereby a main current flowing between said anode and cathode regions (21,23) is controlled by a control voltage applied to said MOS gate electrode (251). A MOS composite static induction thyristor according to claim 1, wherein said MOS transistor (2) is provided with a well region (51), said cathode region (23) has an elongated shape defining a longitudinal direction and said MOS transistor (2) extends in said longitudinal direction. A MOS composite static induction thyristor according to claim 1 or claim 2, wherein said gate regions (31) are buried within said channel region (22). A MOS composite static induction thyristor according to claim 1, wherein said MOS transistor (2) is provided with a base region (53) and said thyristor unit (1) has at least a pair of grooves, said gate regions (31) being formed on bottom or on side walls of said grooves, and said cathode region (23) being formed substantially at a center of an upper portion of said channel region (22) which is sandwiched in between said grooves. A MOS composite static induction thyristor according to claim 4, wherein said thyristor unit (1) has gate electrodes (78,79) contacting said gate regions (31) and located within said grooves. A MOS composite static induction thyristor according to claim 1, comprising a further MOS transistor of the same type as said MOS transistor merged onto said single monolithic chip, said first semiconductor region (62) and both source regions (52) of said both MOS transistors being connected to each other through said first wiring layer (231) of high electrical conductivity and said voltage control being applied to the gate electrodes (251) of both MOS transistors. A MOS composite static induction thyristor according to any one of the claims 1 to 6, wherein said cathode region (23) is shifted toward one gate region of said pair of gate regions (31). A MOS composite static induction thyristor according to any one of the claims 1 to 7, wherein said cathode region is arranged at a center between the gate regions of said pair of gate regions (31), and said MOS transistor (2) is arranged on opposite sides of said cathode region (23). A MOS composite static induction thyristor according to claim 8, including a groove formed between said source (52) and cathode (23) regions and an oxide film (26) deposited within said groove. A MOS composite static induction thyristor according to any one of the claims 1 to 9, including a buffer layer (42) of first conductivity type at a location adjacent to said anode region (21). A MOS composite static induction thyristor according to any one of the claims 1 to 10, wherein said anode region (21) is divided into a plurality of portions, and a short region (24) of first conductivity type having high impurity concentration is formed between said portions of said anode region (21). A MOS composite static induction thyristor according to claim 11, wherein said portions of said anode region (21) are arranged periodically, and the pitch of the periodic arrangement of said portions of said anode region (21) is at most two times the diffusion length of the charge-carrier inducing the first conductivity type. A single monolithic semiconductor chip wherein a static induction thyristor unit, a MOS transistor and a voltage regulation element are merged, thereby forming a MOS composite static induction thyristor, said static induction thyristor unit (11) having at least a cathode region (23) of first conductivity type having high impurity concentration, an anode region (21), and a pair of first gate regions (31) of second conductivity type having high impurity concentration, a pair of second gate regions (99) of first conductivity type having high impurity concentration, said first gate regions (31), and said second gate regions (99), being positioned to opposite sides of said cathode region (23) and laterally spaced therefrom, and a channel region (22) of first conductivity type having low impurity concentration, thereby forming a double-gate static induction thyristor unit (11); said MOS transistor (12) having at least a drain region (21) that is the same region as said anode region (21), a well region (88) of first conductivity type formed adjacent to said channel region (22) of said static induction thyristor unit (11), a source region (89) of second conductivity type having high impurity concentration formed within said well region (88), a gate insulating film formed on a surface of said well region (88) between said source region (89) and drain region (21), and a MOS gate electrode (881) formed on said gate insulating film; said voltage regulation element (3) having a first semiconductor region (85) of first conductivity type having high impurity concentration, and a second semiconductor region (86) of second conductivity type having high impurity concentration; wherein said MOS composite static induction thyristor has at least a structure in which said first semiconductor region (85) and said source region (89) are connected to each other through a first wiring layer (211) of high electrical conductivity, and said second semiconductor region (86) and said second gate regions (99) are connected to each other through a second wiring layer (98) of high electrical conductivity, whereby a main current flowing between said anode and cathode regions (21,23) is controlled by a control voltage applied to at least one of said MOS gate electrode (881) or said first gate regions (31).

Inventors: NISHIZAWA JUN-ICHI, SUZUKI SOHBE, NISHIZAWA, JUN-ICHI, SUZUKI, SOHBE
Applicants: ZAIDAN HOJIN HANDOTAI KENKYU, ZAIDAN HOJIN HANDOTAI KENKYU SHINKOKAI
Application year: 1992
Main classification: H01L29
IPC codes: H01L29