Nonvolatile semiconductor memory

Abstract: A nonvolatile semiconductor memory device includes a matrix (1) of nonvolatile erasable memory cells (M11), each memory cell comprising a memory cell transistor. Erase verification circuitry (623, 624) operates, following an erase operation on a plurality of the said memory cells of the matrix, to carry out an erase verify operation to verify that each cell of the said plurality has been erased sufficiently. In this cicruitry, threshold voltage measuring means (623, 626) produce, for a set (605) of those memory cells, a measurement signal representative of a threshold voltage of the said memory cell transistor of that cell of the set having the highest erasure rate. Reference signal generating means (628) produce a reference signal (Vref) representative of a predetermined highest-erasure-rate threshold voltage, being the post-erasure threshold voltage required of that cell of the matrix having the highest erasure rate. Comparison means (625) compare the or each said measurement signal with the reference signal and judge, based on the comparison(s), whether the threshold voltage of any one of the memory cells of the plurality has reached the predetermined highest-erasure-rate threshold voltage.

Description: This invention relates to a nonvolatile semiconductor memory, particularly to an EPROM and an EEPROM including a nonvolatile memory circuit and, more particularly to a circuit construction of a nonvolatile semiconductor memory of the batch erasure type (hereinafter referred to as a flash memory). The invention further relates particularly to a circuit construction concerning an improvement in the speed of an erase verify operation in a nonvolatile semiconductor memory. Fig. 2 of the accompanying drawings shows diagrammatically a structure of a cell used in a flash memory. In this figure, indicated at V G is a gate terminal, at V D a drain terminal, at V S a source terminal, at 27 a control gate CG connected to the gate terminal V G , and at 25 a floating gate FG which is controlled by the potential of the control gate CG. Further, indicated at 22 is a semiconductor substrate, e.g. a semiconductor substrate having P-type conductivity. On the semiconductor substrate 22 are mounted well portions 23, 24 made of semiconductor having N-type conductivity. The well portion 23 forms a drain while the well portion 24 forms a source. Indicated at 26, 28 are insulating films. When data is read from the cell, 0V is applied to the source terminal V S , a read voltage (normal supply. voltage V CC ) of 5V is applied to the gate terminal V G , and a voltage of about 1V is applied to the drain terminal V D . Then, it is discriminated whether the read data is "1" or "0" depending upon whether a current flows through the cell. On the other hand, when data is written in the cell, 0V is applied to the source terminal V S , a write/erase voltage V PP of about 12V is applied to the gate terminal V G , and a write drain voltage V W (lower than V PP ) is applied to the drain terminal V D . Thereby, electrons are injected into the floating gate FG from a drain region (writing operation). Further, when the data is erased, the drain terminal V D is brought into an open state, and 0V and the write/erase voltage V PP are applied to the gate terminal V G and the source terminal V S respectively. Thereby, the electrons are taken from the floating gate FG to a source region (erasing operation). When the data is written, it is required to check whether the data is written sufficiently in the memory cell (write verification). Likewise, when the data is erased, it is required to check whether the data is erased sufficiently from the memory cell (erase verification). The write verification and erase verification are carried out so as to confirm whether the degree of writing and the degree of erasing have a sufficient margin for the read voltage, i.e. a variation range of the normal supply voltage V CC (5V ± 0.5V). Generally, these verifications are carried out to confirm that an operation margin of about 0.5V to 1.0V is available for a voltage range of V CC . In this case, the verify voltage including the operation margin is 6V to 6.5V in the write verification, and 3.5V to 4V in the erase verification. It is expected that the write verification and the erase verification can be accomplished easily if the verify voltage including the operation margin to be secured is applied to word lines (for example, word lines WL 1 to WL m of the flash memory shown in Fig. 1), so that the sensitivity of the S/A circuit is the same regardless of whether the voltage V CC or the verify voltage is applied as the supply voltage of the S/A circuit. Fig. 3 of the accompanying drawings shows a construction of a general S/A circuit used in the nonvolatile semiconductor memory such as an EPROM. In this figure, indicated at V CC is a line of a supply voltage 5V, and at V SS a line of a supply voltage 0V. Between the power supply lines V CC and V SS are connected a p-channel transistor 11 and an n-channel transistor 12 in series. A gate of the transistor 11 is connected to power supply line V SS , while a gate of the transistor 12 is connected to a data line (i.e. a bit line). Between the power supply line V CC and the data line is connected an n-channel transistor 13 whose gate is connected to drains of the respective transistors 11, 12. Likewise, between the power supply line V CC and the data line are connected a p-channel transistor 14 and an n-channel transistor 15 in series. A gate of the transistor 14 is connected to the power supply line V SS , while a gate of the transistor 15 is connected to the drains of the respective transistors 11, 12. An output (data output) of the S/A circuit is taken from drains of the respective transistors 14, 15. In this construction, when the data read from the memory cell is "1", i.e. when the level of the data line is "H", the transistor 12 is turned on and thereby a drain potential thereof is reduced to "L" level. Accordingly, the transistor 15 is cut off. Thus, the voltage of "H" level is output from the power supply line V CC through the transistor 14 (data output). In other words, the data having the same level as the read data is sensed. Conversely, when the data read from the memory cell is "0", the transistor 12 is cut off and the voltage of "H" level is fed from the power supply line V CC through the transistor 11 to the gate of the transistor 15 to turn the transistor 15 on. Thereupon, the level of a data output line is reduced to "L" (the data of "L" level is the same as the read data). In this way, the transistor 15 is provided with a function of transmitting the level of the bit line to the data output line (bit line level adjustment), and the transistor 14 is provided with a function of discriminating the data of the memory cell according to the state (on/off) of the transistor 15. In recent years, a high speed operation has been aimed at. However, there is a limit in carrying out the data writing, data reading, and erasing operations at a high speed in the conventional nonvolatile semiconductor memory in terms of its circuit construction and software, thus realization of higher operations are earnestly demanded. Further, in the nonvolatile semiconductor memory of the prior art, since there is variation in an erasing characteristic of the memory cell transistors, it takes time to erase the information written in the memory reliably, which creates a risk of erasing even necessary information. In view of these problems, it is desirable to provide a nonvolatile semiconductor memory capable of shortening an erase verifying time and a time required to erase information, and/or of carrying out an erasing operation such that there is no memory cell transistor having necessary information erased therefrom. The invention is specified by claims 1, 15 und 18. According to an embodiment of the present invention, there is provided a nonvolatile semiconductor memory comprising a cell matrix circuit (1) having erasable nonvolatile memory cell transistors (M ij ) arranged at intersections of a plurality of word lines (WL 1 to WL m ) and a plurality of bit lines (BL 11 to BL 1k , ..., BL n1 to BL nk ); a row decoding circuit (3); a column decoding circuit (5); and sense amplifying circuits (7 1 to 7 n ) connected to the respective bit lines (BL 11 to BL 1k , ..., BL n1 to BL nk ) of the cell matrix circuit (1). Memory cell transistors included in the cell matrix circuit in the aforementioned nonvolatile semiconductor memories are connected in parallel with one another while being in on-states, and the cell matrix circuit has voltage discriminating means connected thereto, the voltage discriminating means including voltage detecting means for detecting a generated voltage in response to a current flowing through all the memory cell transistors, reference voltage generating means, and comparing means for comparing an output voltage from the voltage detecting means and a reference voltage output from the reference voltage generating means. In a first preferred embodiment a predetermined voltage is applied to a source line to which the cell transistors are commonly connected at the sources thereof, the same or different positive voltage are applied to all or a part of the plurality of word lines forming the control gates of the plurality of cell transistors; and the plurality of cell transistors are connected at the drains thereof commonly to the data bus to which the voltage judgement circuit is also connected. For an erase verify operation, the voltage judgement circuit applies the same or different positive voltages higher than the predetermined voltages to all or a part of the plurality of word lines that form the control gates of the plurality of cell transistors connected at the sources thereof to a common source line and this source line, and when a data bus (provided correspondingly to the plurality of bit lines to which the plurality of cell transistors are connected at the drains thereof) is connected to all or a part of the plurality of bit lines, the judgement circuit compares the voltage on the data bus with a predetermined reference voltage to judge whether or not the voltage at all or a part of the drains of the plurality of cell transistors has reached a value derived by subtracting from the positive voltage applied to the word lines a lower limit threshold permitted for the plurality of cell transistors. More particularly, in the first embodiment, the same or different positive voltages higher than predetermined voltages are applied to, for example, the plurality of word lines and the source line, for erasure verification, and when the data bus is connected to the plurality of bit lines, the drain voltage of the plurality of cell transistors will be a value derived by "subtraction of a threshold value of the cell transistor for which the erase rate is highest (lowest threshold value of all the cell transistors) from the positive voltage applied to the word lines". In the first embodiment, the voltage judgement circuit judges whether or not the drain voltage of the plurality of cell transistors has reached a value derived by "subtraction of a permitted lower limit threshold value from the positive voltage applied to the word lines". When "the threshold value of the cell transistor for which the erase rate is highest equals the permitted lower threshold value", the drain voltage of the plurality of cell transistors will be a value derived by a "subtraction of the permitted lower limit threshold value from the positive voltage applied to the word lines". In other words, when the drain voltage of the plurality of cell transistors has reached a value derived by "substraction of the permitted lower limit threshold from the positive voltage applied to the word lines", it can be decided that the threshold of the cell transistor for which the erase rate is highest has reached the permitted lower limit threshold. Also in this case, it can be decided that the threshold of the cell transistor for which the erase rate is lowest has reached the permitted upper limit threshold. Namely, in this first embodiment, the same or different positive voltage are applied to the plurality of word lines and the source line, respectively, and the data bus is connected to all of the bit lines. The voltage judgement circuit judges whether or not the drain voltage of the plurality of cell transistors has reached the value derived by "subtraction of the permitted lower limit threshold value from the positive voltage applied to the word lines", thereby permitting erasure verification for the plurality of cell transistors at one time. According to the first embodiment described above, erase verification can be made simultaneously for a plurality of memory cell transistors, and consequently all the memory cell transistors need not be read out one by one. Therefore, the erase verification time can be shortened. According to the first embodiment, erase verification can be made by detecting the case where the threshold value of the memory cell transistor having the highest erase rate reaches the allowed lower limit threshold value. Therefore, the erasing operation can be carried out without causing any memory cell transistors to be over-erased. Incidentally, if erase verification is then performed by the prior art method after the threshold value of the memory cell transistor having the highest erase rate has reached the allowed lower limit threshold value, it is possible to confirm the existence of any memory cell transistors exhibiting a greater threshold value than the threshold value after erasure permitted for the memory cell transistor having the lowest erase rate, and thus to detect defects in the devices. In such a case, erase verification by the prior art method needs to be carried out only once for each memory cell transistor. Therefore, the overall erase verify time can be made shorter than in the prior art method. Furthermore, this first embodiment includes the voltage judgement circuit for judging whether or not the drain voltage of all, or a part, of a plurality of memory cell transistors has reached the difference obtained by subtracting the allowed lower limit threshold value from the positive voltage applied to the word lines, by comparing the voltage of the data bus with a predetermined reference voltage. Therefore, erase verification can be executed for those memory cell transistors which share a common bit line, or for each memory cell transistor in turn. In this case, the same or different voltages above predetermined voltage values are applied to a part of a plurality of word lines and to the source lines, and the data bus is connected to a part of a plurality of bit lines at the time of erase verify. In a second embodiment, for erasure verification the voltage judgement circuit applies the same or different positive voltages higher than the predetermined voltages to all or a part of the plurality of word lines that form the control gates of the plurality of cell transistors connected at the sources thereof to a common source line and to a data bus provided correspondingly to the plurality of bit lines to which the plurality of cell transistors are connected at the drains thereof, and when the data bus is connected to all or a part of the plurality of bit lines, the judgement circuit compares the voltage on the source line with a predetermined reference voltage to judge whether or not the voltage at all or a part of the sources of the plurality of cell transistors has reached a value derived by subtracting from the positive voltage applied to the word lines the lower limit threshold permitted for the plurality of cell transistors. In the second embodiment, when the same or different positive voltages above predetermined voltage values are applied to all of a plurality of word lines and to the data bus, and a plurality of bit lines are connected together at the time of erase verify, for example, the source voltage of a plurality of memory cell transistors becomes equal to [positive voltage applied to the word lines] - [the threshold value of the memory cell transistor having the highest erase rate]. In this second embodiment, the voltage judgement circuit judges whether or not the source voltage of a plurality of memory cell transistors reaches a predetermined reference potential difference equal to [the positive voltage applied to the word lines] - [the allowed lower limit threshold value]. When [the threshold value of the memory cell transistor having the lowest erase time] is equal to [the allowed lower limit threshold value], the source voltage of a plurality of memory cell transistor reaches the difference, that is, [the positive voltage applied to the word lines] - [the allowed lower limit threshold value]. In other words, when the source voltage of a plurality of memory cell transistors reaches the reference potential difference, i.e. [the positive voltage applied to the word lines] - [the allowed lower limit threshold value], the threshold value of the memory cell transistor having the highest erase rate can be judged as reaching the allowed lower limit threshold value. In this case, the threshold value of the memory cell transistor having the lowest erase rate can be judged as reaching the allowed upper limit threshold value. In other words, the second embodiment can simultaneously execute erase verify for a plurality of memory cell transistors by applying the same or different positive voltages above predetermined voltages to all of a plurality of word lines and to the data bus at the time of erase verify, connecting the data bus to all of a plurality of bit lines, and judging by the voltage judgement circuit whether or not the source voltage of a plurality of memory cell transistors reaches the difference obtained by subtracting the allowed lower limit threshold value from the positive voltage applied to the word lines. As described above, the second embodiment can simultaneously execute erase verification for a plurality of memory cell transistors in the same way as the first embodiment. Since all the memory cell transistors need not be read out one by one, the erase verify time can be shortened. The second embodiment can execute erase verification by detecting the point of time when the threshold value of the memory cell transistor having the highest erase rate reaches the allowed lower limit threshold value. Therefore, the second embodiment can carry out the erasing operation without causing any memory cell transistors to be over-erased. When erase verification is then carried out by the prior art method after the threshold value of the memory cell transistor having the highest erase rate has reached the allowed limit threshold value, the existence of any memory cell transistors which exhibit a greater threshold value than the threshold value after erasure allowed for the memory cell transistor having the lowest erase rate can be confirmed, and any defects in the devices can be discovered. In such a case, too, erase verification according to the prior art method may be carried out only once. Therefore, the erase verify time can be made shorter than in the prior art method. The second embodiment includes the voltage judgement circuit for judging whether or not the source voltage of all, or a part, of a plurality of memory cell transistors has reached the voltage value obtained by subtracting the allowed lower limit threshold value from the positive voltage applied to the word lines. For this reason, erase verification can be carried out for those memory cell transistors which share a common bit line, or for each memory cell transistor. In this case, the same or different positive voltages exceeding the predetermined voltage values are applied to a part of a plurality of word lines and to the data bus at the time of erase verify, and the data bus is connected to a part of a plurality of bit lines. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a diagram showing the overall construction of a flash memory to which an embodiment of the present invention can be applied; Fig. 2 is a diagram showing a cell structure for explaining an operation of the flash memory; Fig. 3 is a circuit diagram showing a construction of a S/A circuit as an example of the prior art; Fig. 4 is a diagram showing the principle of another sense amplifier suitable for use in an embodiment of the present invention; Fig. 5 is a chart showing a relationship between an erasing time and a threshold value of a memory cell transistor; Fig. 6 is a flow chart showing a procedure of erasure carried out in a conventional flash type memory; Fig. 7 is a circuit diagram showing parts of a first embodiment of the present invention; Fig. 8 is a chart showing a relationship between the erasing time and the threshold value of a memory cell transistor in an embodiment of the present invention; Fig. 9 is a flow chart showing a procedure of erasure carried out in the first embodiment of the present invention; Fig. 10 is a circuit diagram showing parts of a second embodiment of the present invention; Fig. 11 is a flow chart showing a procedure of erasure carried out in the second embodiment of the present invention; Fig. 1 is a block diagram showing parts of an overall construction of a flash type memory to which an embodiment of the present invention can be applied. In this figure, indicated at 1 is a cell array formed by arranging erasable nonvolatile memory cells M ij at intersections of a plurality of word lines WL 1 to WL n and a plurality of bit lines BL 11 to BL 1k , ..., BL n1 to BL nk . In this embodiment, the cell array is divided into n blocks, in each of which (k × m) memory cells are arranged. Indicated at 2 is a row address buffer for buffering a row address RAD of an address signal fed externally thereto, at 3 a row decoder for decoding the row address and selecting any one of the word lines WL 1 to WL n , at 4 a column address buffer for buffering a column address CAD of the address signal, and at 5 a column decoder for decoding the column address and selecting any one of column lines CL 1 to CL k corresponding to the bit lines BLi l to BLi k for each of the aforementioned blocks. Indicated at 6 is a column gate circuit including transfer gate transistors Q 1 to Q k corresponding to the bit lines BL il to BL ik for each of the aforementioned blocks. The respective transistors Q 1 to Q k are turned on when the corresponding column lines CL 1 to CL k are selected, to thereby connect the selected bit line BL ij to a data line D i . Indicated at 7 1 to 7 n are respectively writing circuits and S/A circuits for applying amplification to a write data and sense amplification to a read data between corresponding internal data lines D 1 to D n and external input/output data lines I/O 1 to I/O n . Indicated at 8 is a verify source voltage generating circuit for generating a verify voltage V VER in accordance with a control signal C fed externally thereto. The generated verify source voltage V VER is supplied to the selected word lines WL 1 to WL n through the row decoder 3 as described later, and to the S/A circuit corresponding to the selected word line. Indicated at 9 is a source voltage supply circuit for supplying a source voltage in common to the respective sources of the nonvolatile memory cells M ij . It may sometimes be necessary to erase predetermined information once written into the memory cell transistor; however, a method thereby providing easy and positive erasure of such information has not been proposed heretofore. More particularly, for erasing the memory cell transistor in the flash-type memory etc., erase verify operations are to be done to verify whether the information has been positively erased. However, it is difficult to determine when the erasing operation has been completed and no appropriate method has been proposed heretofore. The memory cell transistors forming together a cell array in a flash-type memory vary in characteristics from one to another even in the case of similar manufacturing process. Thus, when memory cell transistor are erased under the same conditions, certain transistors may be sufficiently erased while others may be not be sufficiently erased. If all the memory cell transistors are erased based on the erasure extent of a low-erase-speed memory cell transistor, the memory cell transistors for which the erase rate is higher will be over-erased and cannot be used again. Also, if all the memory cell transistors are erased in a way appropriate for a high-erase-speed memory cell transistor many of them will not be sufficiently erased and further write operations cannot be made to these transistors. Therefore, heretofore elaborate erasure methods have been used. Specifically, in one such method used in a flash-type memory, erasure and verification (verification of whether the erasure has been completed) are repeatedly effected during an erasure so that no memory cell transistors (called cell transistors from now on) will remain under-erased. No cell transistors should be over-erased. However, this conventional erasing operation is effected using an address for an individual cell transistor, which causes the erasure time to be extremely long, and it is necessary that this erasure time be shortened. Accordingly, it is desirable to overcome such drawbacks of the conventional technique and to provide a flash-type memory in which the erase/verify can be done in a short time, thereby shortening the erase time, without over-erasure of any cell transistors. One example of a flash-type memory is shown in Fig. 1, and one example of the configuration of a sense amplifier for use in such a memory is shown in Fig. 4. For erase verify in a flash-type memory having such a configuration, the word lines WL0 to WL2, for example, are applied with the same voltage as the post-erase threshold required for the cell transistors that are erased at the lowest speed, that is, the upper limit threshold permitted for the cell transistors M11 00 to M11 jj , taking into consideration the variance in characteristics of the cell transistors. This voltage is a voltage based on the fact that it must be possible to judge whether or not a current flows to the cell transistors M11 00 to M11 jj , when each one of the cell transistors is read respectively; in this case, the applied voltage may be the power-supply voltage Vcc. More particularly, a previously-considered flash-type memory, when the erase verify operation is being carried out, if no current flows to the cell transistors M11 00 to M11 jj when they are read individually for erasure verification, namely, if the voltage at the node 332 in Fig. 4 is equal to a reference voltage Vref, the erasure is determined to be insufficient (under-erase). If the voltage is smaller than Vref, it is determined that the erasure is completed. Fig. 5 shows the relation between the erase time and the threshold of the cell transistors M11 00 to M11 jj . The solid line 620 is for the cell transistor for which the erase rate is lowest, and the solid line 621 is for the cell that can be erased at the highest speed. In a previously-considered flash-type memory, the erasure is done by taking as a reference potential the post-erase threshold for the cell transistor having the lowest-speed erasure characteristic, that is, to a permitted upper limit threshold shown in Figure 5, so that the erasure is deemed to be completed when the threshold of the cell transistor for which the erase rate is lowest reaches the upper limit threshold. The erasure is done following the procedure shown in Fig. 6. More particularly, a write for all the cell transistors M11 00 to M11 jj is done first (step A1), and then an erasing operation is started (step A2). After waiting a predetermined time (erasing operation continues - step A3) the erasing operation is stopped (step A4). Thereafter, the cell transistors M11 00 to M11 jj are read individually, and the voltage at the node 332 of the sense amplifier 329 is compared with the reference voltage Vref for the erase verify operation (step A5). Then it is determined whether or not he voltage at the node 332 is smaller than Vref for all the cell transistors M11 00 to M11 jj , namely, whether or not all the cell transistors M11 00 to M11 jj have successfully been erased (step A6). If all the cell transistors M11 00 to M11 jj have not yet been erased (judgement of NO at step A6), the operation returns to step A2. When all of them have been erased (YES at step A6), the erasing operation is terminated. In such conventional flash-type memory, the cell transistors M11 00 to M11 jj are read one by one and only one of them is subject to the erasure verification at a time. In other words, for each sense amplifier, only one cell transistor can be subject to the erase verify operation at a time, which causes the total erase verify operation time to be long and further leads to a long erasure time. Also because of the configuration of the conventional flash-type memory, completion of the erasure of all the cell transistors M11 00 to M11 jj is judged by checking that the threshold of the cell transistor for which the erase rate is lowest reaches the permitted upper limit threshold. Thus, it is impossible to avoid the situation where the cell transistor for which the erase rate is high is over-erased. It also means that over-erased cell transistors will be mixed in with correctly-erased cell transistors after the erasure procedure is finished. Fig. 7 is a circuit diagram showing portions of a first embodiment of the present invention. In the drawing, symbol SL represents a source line to which the sources of the memory cell transistors M11 00 to M11 22 are connected. In this embodiment, there is disposed a voltage supply circuit 623 for supplying a power supply voltage VCC to the source line SL at the time of erase verify. There is disposed a voltage judgement circuit 624 which judges whether or not he voltage of a data bus 613 is greater than the difference obtained by subtracting from VCC an allowed lower limit threshold value (see Figure 8) of the memory cell transistors M11 00 to M11 22 . The rest of the circuit construction is the same as that of the flash memory shown in Fig. 1. In the voltage judgement circuit 624, reference numeral 625 denotes an operational amplifier which constitutes a comparator, reference numerals 626 and 627 denote depletion type n-MOS transistors each constituting a load, and reference numeral 628 denotes a reference voltage generation circuit for generating a reference voltage Vref. The reference voltage Vref is set to be the difference obtained by subtracting from VCC the allowed lower limit threshold value of the memory cell transistors M11 00 to M11 22 . Reference numeral 629 denotes an enhancement type n-MOS transistor having the same size as that of n-MOS transistors 612 0 to 612 2 of a column gate circuit 607. A voltage of VCC + V th-n (an n-MOS transistor threshold voltage) is applied to the gate of the n-MOS transistor 629 at the time of erase verify. Reference numeral 630 denotes a judgement output terminal from which the judgement is output. In this first embodiment, erase verification is carried out with the reference voltage set in accordance with the post-erasure threshold value required of the memory cell transistor having the highest erase rate, that is, the allowed lower limit threshold value. It is first confirmed whether or not the threshold value of the memory cell transistor having the highest erase rate has reached the reference voltage, and then erase verify is carried out by the prior art method. More definitely, the erasing operation is carried out in the sequence shown in Fig. 9. In other words, in this embodiment of the present invention, the memory cell transistor having the highest erase rate among the memory cell transistors is focused on, and the threshold value V th at which the memory cell transistor having the highest erase rate should be judged to be erased is used to set the reference potential. As shown in Figure 8 the cell transistors will inevitably have threshold values which vary within a range of values having the threshold value V th as its lower limit but it is assumed that when the highest-erase-rate cell transistor is judged as being erased (i.e. its threshold value has fallen to the allowed lower limit value) all the memory cell transistors in the memory cell array can be judged as being erased (i.e. all of them are assumed to have threshold values lower than an allowed upper limit value of the range). To begin with, a write to all the memory cell transistors M11 00 to M11 22 is carried out (step B1). Next, after the erasing operation is started, a wait state (the erasing operation holding state) is maintained for a predetermined time (steps B2 and B3). Incidentally, the erasing operation may be carried out by setting the source line to SL to VCC, the word lines WL 0 - WL 2 to a negative potential, and the bit lines BL 0 - BL 2 to OPEN (i.e. turning OFF the n-MOS transistors 612 0 - 612 2 ), or by setting the source line SL to a high voltage, e.g. 12V, the word lines WL 0 to WL 2 to 0 V, and the bit lines BL 0 - BL 2 to OPEN. Next, erase verification is carried out (step B4). This operation is carried out by setting the word lines WL 0 - WL 2 to VCC, the source line SL to VCC, turning ON the n-MOS transistors 612 0 - 612 2 and 629 (gate voltage = VCC + V th-n ), and comparing the voltage value of the data bus 613 with the voltage value of the reference voltage V ref . In this case, the voltage of the data bus 613 coincides with the drain voltage of the memory cell transistors M11 00 to M11 22 , and the voltage of the data bus 613 is the difference obtained by subtracting from the voltage (VCC) applied to the word lines the threshold value of the memory cell transistor having the highest erase rate among n-MOS transistors M11 00 -M11 22 (the threshold value of the memory cell transistor which has the minimum threshold value within the above-mentioned range). In the next step B5, it is judged whether or not the judgement output obtained at the judgement output terminal 630 is "H". When the judgement output is not "H" (NO at step B5) (that is, when the voltage of the data bus 613 < the reference voltage Vref) the threshold value of the memory cell transistor having the highest erase rate among the memory cell transistors M11 00 - M11 22 is higher than the allowed lower limit threshold value Vth. In this case, because of variations in the cell-transistor characteristics there is the possibility that there exists a memory cell transistor which exhibits a greater threshold value than the post-erasure threshold value (allowed upper limit threshold value) required of the memory cell transistor having the highest erase time (slowest erase rate). Therefore, the flow returns to the step B2, and erase is carried out once again. In contrast, when the judgement output obtained at the judgement output terminal 630 is "H" (YES at step B5) (that is, when the voltage of the data bus 613 ≥ the reference voltage Vref) the threshold value of the memory cell transistor having the highest erase rate among the memory cell transistors M11 00 - M11 22 has reached the allowed lower limit threshold value. In this case, the threshold value of the memory cell transistor having the lowest erase rate can be assumed to have reached the allowed upper limit threshold value, but it is not possible to exclude the possibility that, due to defects, there exists one or more memory cell transistors having a greater threshold value than the allowed upper limit threshold value. In the first embodiment, therefore, even in the case of YES at the step B5, the output of the sense amplifier 608 is judged (step B6) by carrying out erase verification according to the prior art method. In other words, the memory cell transistors M11 00 to M11 22 are read one by one, and it is judged in step B7 whether or not any memory cell transistor renders the output of the sense amplifier 608 "H" (that is, whether or not there exists a memory cell transistor which exhibits a greater threshold value than the allowed upper limit threshold value). When no memory cell transistor exists which renders the output of the sense amplifier 608 "H" (NO at step B7), the erasing operation is completed on the presumptions that the device is not a defective device and that erasure has been completed for all the memory cell transistors M11 00 to M11 22 . In contrast, when there does exist a memory cell transistor which renders the output of the sense amplifier 608 "H" (YES at step B7), the device is treated as a defective device (step B8). As described above, the first embodiment sets the reference potential in accordance with the post-erasure threshold value required of the memory cell transistor having the highest erase rate (that is, the allowed lower limit threshold value) and confirms that the threshold value of the memory cell transistor having the highest erase rate has reached the allowed lower limit threshold value using the reference potential, and then confirms the absence of any memory cell transistor rendering the output of the sense amplifier 608 "H". The first embodiment can thus complete the erasing operation. Here, whether or not the threshold value of the memory cell transistor having the highest erase time reaches the allowed lower limit threshold value can be confirmed by setting the word lines WL 0 - WL 2 to VCC, the source line SL to VCC and the gates of the n-MOS transistors 612 0 - 612 2 and 629 to VCC + V th-n . In this case, it is not necessary to read the memory cell transistors M11 00 - M11 22 one by one. Incidentally, when a voltage above VCC + V th-n is applied to the gates of the n-MOS transistors 612 0 - 612 2 and 629, the voltage drop of these n-MOS transistors 612 0 to 612 2 and 629 can be neglected. The judgement of the existence or absence of the memory cell transistor rendering the output of the output for the sense amplifier 608 "H" can be accomplished by carrying out the erase verify of the prior art method only once. This first embodiment can execute erase verify by detecting the case where the memory cell transistor having the highest erase rate reaches the allowed lower limit threshold value. Accordingly, over-erased memory cell transistors are not caused. Accordingly, the first embodiment can shorten the erase verify time as well as the time necessary for erase, and can execute erase without generating over-erased memory cell transistors. In this first embodiment, erase verification may also be executed for those memory cell transistors which share a common bit line (i.e. one erase verification per bit line), or for each memory cell transistor (i.e. one erase verification per cell transistor). When erase verification is carried out for those memory cell transistors which share a bit line in common, for example when erase verification is simultaneously executed for the memory cell transistors M11 oo , M11 10 and M11 20 connected to the bit line BL o , for example, this operation can be carried out by setting the word lines WL o - WL 2 to VCC, the source line SL to VCC, turning ON the n-MOS transistors 612 0 and 629 (gate voltage = VCC + V th-n ), and turning OFF the n-MOS transistors 612 1 and 612 2 (gate voltage = ground potential VSS). Erase verification can be executed for an individual memory cell transistor such as the memory cell transistor M11 oo by setting the word line WL o to VCC, the word lines WL 1 and WL 2 to VSS, and the source line SL to VCC, turning ON the n-MOS transistors 612 o and 629 (gate voltage = VCC + V th-n ) and turning OFF the n-MOS transistors 612 1 and 612 2 (gate voltage = VSS). In this first embodiment, VCC + V ch-n is applied to the gates of the n-MOS transistors 612 o - 612 2 and 629 when these transistors are turned ON, but VCC may also be applied. Fig. 10 is a circuit diagram showing portions of a second embodiment of the present invention. In this second embodiment, there is disposed a voltage supply circuit 631 for supplying the power supply voltage VCC to the data bus 613 at the time of erase verify. Reference numeral 632 denotes the VCC power supply line, and reference numeral 633 denotes an n-MOS transistor. At the time of erase verify, VCC + V th-n is applied to the gate of this n-MOS transistor 633 to turn ON this transistor, and VSS is applied to the gate at other times to turn the transistor OFF. There is also disposed a voltage judgement circuit 634 which judges whether or not the voltage of the source line SL is greater than the difference obtained by subtracting the allowed lower limit threshold value of the memory cell transistors M11 oo - M11 22 from VCC at the time of erase verify. The rest of the construction is the same as that of the prior art flash memory shown in Fig. 1. In this voltage judgement circuit 634, reference numeral 635 denotes a reference voltage generation circuit for generating a reference voltage Vref, and this reference voltage Vref is set to the difference obtained by subtracting from VCC the allowed lower limit threshold value of the memory cell transistors M11 00 - M11 22 . Reference numerals 636 and 637 denote enhancement type n-MOS transistors having the same size and constituting a gating circuit, reference numerals 638 and 639 denote depletion type n-MOS transistors having the same size and constituting respective load circuits, reference numeral 640 denotes an operational amplifier, and reference numeral 641 denotes a judgement output terminal which outputs a judgement result. The n-MOS transistors 636 and 637 are turned ON at the time of erase verify as VCC + V th-n is applied to their gates, and are turned OFF at other times as VSS is applied to their gates. In this second embodiment the erasing operation is carried out in the same way as in the first embodiment. In other words, the post-erasure threshold value required of the memory cell transistor having the highest erase rate, that is, the allowed lower limit threshold value, is used to set the reference voltage Vref, and it is confirmed using the reference voltage Vref whether or not the threshold value of the memory cell transistor having the highest erase rate has reached the allowed lower limit threshold value. Then, erase verification is executed by the prior art method. More definitely, this operation is carried out in the sequence shown in Fig. 11. First of all, write to all the memory cell transistors M11 00 - M11 22 is carried out (step C1). Next, after the erasing operation is started, a wait state (the erasing operation holding state) is held for a predetermined waiting time (steps C2 and C3). Here, the erasing operation is carried out by setting the source line SL to VCC, the word lines WL 0 - WL 2 to a negative potential and the bit lines BL 0 - BL 2 to OPEN (i.e. turning OFF the n-MOS transistors 612 0 - 612 2 ), or by setting the source line SL to a high voltage, e.g. 12V, the word lines WL 0 - WL 2 to 0 V, and the bit lines BL 0 - BL 2 to OPEN. Next, erase verify is executed (step C4). This operation is carried out by turning ON the n-MOS transistors 612 0 - 612 2 , 633, 636 and 637 (the gate voltage = VCC + V th-n ), setting the bit lines BL 0 - BL 2 to VCC and the word lines WL 0 - WL 2 to VCC, and comparing the voltage value of the source line SL with the reference voltage Vref. At this time, the source voltage of the memory cell transistors M11 00 - M11 22 , that is, the voltage of the source line SL, becomes equal to the potential difference between VCC and the threshold voltage of the memory cell transistor having the highest erase rate (the threshold value of the memory cell transistor having the minimum threshold value). Here, it is judged whether or not the judgement output obtained at the judgement output terminal 641 is "H" (step C5). When the judgement output is not "H" (NO at step C5), that is, when the voltage of the source line SL < the reference voltage Vref, the threshold voltage of the memory cell transistor having the highest erase rate is higher than the allowed lower limit threshold value. In this case, because of cell-transistor characteristic variations there is a possibility that there is a memory cell transistor exhibiting a greater post-erasure threshold value than the allowed upper limit threshold value (i.e. the threshold value required of the memory cell transistor having the highest erase time (the slowest erasure rate)). Therefore, the flow returns to the step C2, and the erasing operation is carried out once again. In contrast, when the judgement output obtained at the judgement output terminal 641 is "H" (YES at the step C5), that is, when the voltage of the source line SL ≥ the reference voltage Vref, the threshold value of the memory cell transistor having the highest erase rate among the memory cell transistor M11 00 - M11 22 has reached the allowed lower limit threshold value. In this case, the threshold value of the memory cell transistor having the lowest erasure rate can be assumed to have reached the allowed upper limit threshold value. However, it is not possible to exclude the possibility that there exists one or more defective memory cells which have a greater threshold value than the allowed upper limit threshold value. In this second embodiment, therefore, it is judged (even in the case of YES at the step C5) whether or not there exists a memory cell transistor which renders the output of the sense amplifier 608 "H", that is, which exhibits a greater threshold value than the allowed upper limit threshold value. This is done by effecting the erase verify by the prior art method or, in other words, by bringing the memory cell transistors M11 00 - M11 22 into the read state one by one and by judging the output of the sense amplifier 608 (steps C6 and C7). If none of memory cell transistors renders the output of the sense amplifier 608 "H" (NO at the step C7), the device is not a defective device, and the erasing operation is completed on the presumption that all of the memory cell transistors M11 00 - M11 22 have been erased. In contrast, when any memory cell transistor renders the output of the sense amplifier 608 "H" (YES at the step C7), the device is treated as a defective device (step C8). As described above, the second embodiment uses the post-erasure threshold value required of the memory cell transistor having the highest erase rate, that is, the allowed lower limit threshold value, to set the reference potential, confirms using the reference potential whether or not the threshold value of the memory cell transistor having the highest erase rate reaches the allowed lower limit threshold value, confirms also whether or not there exists a memory cell transistor which renders the output of the sense amplifier 608 "H", and can thus complete the erasing operation. In this case, it can be confirmed whether or not the threshold value of the memory cell transistor having the highest erase rate has reached the reference potential by setting the word lines WL 0 - WL 2 to VCC and the bit lines BL 0 - BL 2 to VCC and turning ON the transistors 612 0 - 612 2 , 633, 636 and 637 (gate voltage = VCC + V th-n ). The memory cell transistors M11 00 - M11 22 need not be brought into the read state one by one. Judgement of whether or not any memory cell transistor renders the output of the sense amplifier 608 "H" is carried out by executing erase verification by the prior art method only once for all the memory cell transistors M11 00 - M11 22 . Since this second embodiment can execute erase verification by detecting the case where the memory cell transistor having the highest erase rate has reached the allowed lower limit threshold value, over-erasure of memory cell transistors is not caused. Accordingly, this second embodiment can shorten the erase verify time and the time necessary for the erasing operation. Moreover, it can execute the erasing operation without causing the over-erased memory cell transistors. In this second embodiment, erase verification may also be executed for each set in turn of memory cell transistors which share a common bit line, or for each memory cell transistor in turn. When erase verification is executed for a set of memory cell transistors which have a bit line in common, the memory cell transistors M11 00 , M11 10 and M11 20 connected to the bit line BL 0 , for example, can be subjected simultaneously to erase verification by setting the word lines WL 0 - WL 2 to VCC, turn ON the n-MOS transistors 612 0 , 633, 636 and 637 (gate voltage = VCC + V th-n ) and turning off the n-MOS transistors 612 1 to 612 2 (gate voltage = VSS). When erase verification is executed individually for each memory cell transistor such as the memory cell transistor M11 00 , for example, it can be carried out by setting the word lines WL 0 to VCC and the word lines WL 1 and WL 2 to VSS, turning ON the n-MOS transistors 612 0 , 633, 636 and 637 (gate voltage = VCC + V th-n ) and turning OFF the n-MOS transistors 612 1 and 612 2 (gate voltage = VSS). Incidentally, in this second embodiment, VCC + V th-n is applied to the gates of the n-MOS transistors 612 0 - 612 2 , 636 and 637 when these transistors are turned ON, but VCC may also be applied. As described above, an embodiment of the present invention can simultaneously execute erase verification for a plurality of memory cell transistors, and since all the memory cell transistors need not be read out one by one, this embodiment can shorten the erase verify time and the time necessary for the erasing operation. Since this embodiment executes erase verification by detecting the point of time when the threshold value of the memory cell transistor having the highest erase rate has reached the allowed lower limit threshold value, the erasing operation can be carried out without causing any over-erased memory cell transistors. As described above, in one embodiment of the present invention a flash-type memory has a cell matrix circuit 1 in which erasable nonvolatile memory cells Mij are disposed at the intersections of a plurality of word lines WL1 to WLm. The memory further includes a plurality of bit lines BL11 to BL1k, ..., BLn1 to BLnk, a row decoder circuit 3, a column decoder circuit 5 and sense amplifier circuits connected to the bit groups BL11 to BL1k, ..., BLn1 to BLnk of the cell matrix circuit 1. All the cell transistors forming together the cell matrix circuit are connected parallel to each other with the transistors remaining conductive. The cell matrix circuit has connected thereto a voltage judgement means composed of a means of detecting a voltage developed in response to a current flowing through all of the cell transistors, a reference voltage generating means, and a means of comparing the voltage output from the voltage detecting means with a reference voltage delivered from the reference voltage generating means.

Claims: A nonvolatile semiconductor memory device including: a matrix (1) of nonvolatile erasable memory cells (M11) formed at intersections of word lines (WL) and bit lines (BL), each said memory cell comprising a memory cell transistor; a row decoder (3); a column decoder (5); sense amplifiers (7) corresponding to the bit lines; and erase verification means (623, 624; 633, 634) operable, following an erase operation on a plurality of the said memory cells of the matrix, to carry out an erase verify operation to verify that each cell of the said plurality has been erased sufficiently; characterised in that the said erase verification means comprise: threshold voltage measuring means (623, 626; 631, 636, 638) connected with the memory cells of the said plurality and operable to produce, for an individual one of those memory cells or for a set (605; 606) of those memory cells, a measurement signal that, in the case of an individual memory cell, is representative of a threshold voltage of the said memory cell transistor of the individual memory cell or that, in the case of a set, is representative of a threshold voltage of the said memory cell transistor of that cell of the set having the highest erasure rate; reference signal generating means (628; 635) for producing a reference signal (Vref) representative of a predetermined highest-erasure-rate threshold voltage, being the post-erasure threshold voltage required of that cell of the matrix having the highest erasure rate; and comparison means (625; 640) for comparing the or each said measurement signal with the said reference signal and for judging, based on the comparison(s), whether the threshold voltage of any one of the memory cells of the said plurality has reached the said predetermined highest-erasure-rate threshold voltage. A device as claimed in claim 1, wherein the said predetermined highest-erasure-rate threshold voltage is chosen such that, when the threshold voltage of the said cell of the matrix having the highest erasure rate has reached the said predetermined highest-erasure-rate threshold voltage, a non-defective cell of the matrix having the lowest erasure rate will have been erased sufficiently. A device as claimed in claim 1 or 2, wherein, to produce the said measurement signal for such a set (605; 606), the said threshold voltage measuring means are operable to make the respective memory cell transistors of the cells of the set conductive so that a current path is formed in each transistor between respective first and second current-path terminals thereof, and are also operable to connect the respective memory cell transistors of the cells of the set in parallel with one another such that the respective first current-path terminals thereof are connected together to a first connection line (SL) and the respective second current-path terminals thereof are connected together to a second connection line (613), the said measurement signal being derived from one (613; SL) of the said first and second connection lines. A device as claimed in claim 3, wherein the cells of the said set are arranged along the same bit line or along the same group of bit lines (BL0 to BL2). A device as claimed in claim 3 or 4, wherein the cells of the said set are arranged along the same word line or along the same group of word lines (WL0 to WL2). A device as claimed in claim 1 or 2, wherein, to produce the said measurement signal for an individual memory cell, the said threshold voltage measuring means are operable to make the memory cell transistor of the cell conductive so that a current path is formed in that transistor between respective first and second current-path terminals thereof, and are also operable to connect the first and second current-path terminals thereof respectively to first and second connection line (SL, 613) of the device, the said measurement signal being derived from one (613; SL) of the said first and second connection lines. A device as claimed in any one of claims 3 to 6, wherein a predetermined voltage (VCC) is applied to a control electrode of the memory cell transistor of the said individual memory cell, or of the said memory cell transistor of each cell of the said set, as the case may be. A device as claimed in claim 7, wherein the said measurement signal represents a difference between the said predetermined voltage (VCC) and the threshold voltage of the said individual memory cell or highest-erasure-rate memory cell of the set. A device as claimed in claim 7 or 8, wherein the said reference signal represents a difference between the said predetermined voltage (VCC) and the said predetermined highest-erasure-rate threshold voltage. A device as claimed in any one of claims 7 to 9, wherein the said predetermined voltage is a normal supply voltage (VCC) of the device. A device as claimed in any one of claims 3 to 10, wherein the said first current-path terminal of the or each memory cell transistor is a source terminal and the said second current-path terminal of the or each memory cell transistor is a drain terminal thereof. A device as claimed in claim 11, wherein the said first connection line (SL) is a source line connected in common to respective source terminals of the memory cell transistors of all of the memory cells of the said plurality, and the said second connection line (613) is a data bus of the device serving to connect one or more bit lines (BL) to one of the said sense amplifiers (608). A device as claimed in any preceding claim, further including erase means operable, in the event that it is determined that none of the said memory cells of the said plurality has reached the said predetermined highest-erasure-rate threshold voltage, to cause a further such erase operation to be performed on the memory cells of the said plurality. A device as claimed in any preceding claim, further comprising: defect detection means operable, following such a judgement by the said comparison means (625; 640) that the threshold voltage of one of the said memory cells of the said plurality has reached the said predetermined highest-erasure-rate threshold voltage, to carry out a further verification operation in which it is determined individually, for each memory cell of the said plurality, whether the threshold voltage has reached a predetermined lowest-erasure-rate threshold voltage, being the threshold voltage required of that cell of the matrix having the lowest erasure rate, and, if not, the cell concerned is determined as being defective. An erase verification method, for use in a nonvolatile semiconductor memory that includes: a matrix (1) of nonvolatile erasable memory cells (M11) formed at intersections of word lines (WL) and bit lines (BL), each said memory cell comprising a memory cell transistor; a row decoder (3); a column decoder (5); and sense amplifiers (608) corresponding to the bit lines; which method comprises the steps of: following an erase operation on a plurality of the said memory cells of the matrix, producing, for an individual one of those memory cells or for a set (605; 606) of those memory cells, a measurement signal that, in the case of an individual memory cell, is representative of a threshold voltage of the said memory cell transistor of the individual memory cell or that, in the case of a set, is representative of a threshold voltage of the said memory cell transistor of that cell of the set having the highest erasure rate; producing a reference signal representative of a predetermined highest-erasure-rate threshold voltage, being the post-erasure threshold voltage required of that cell of the matrix having the highest erasure rate; and comparing the or each said measurement signal with the said reference signal and judging, based on the comparison(s), whether the threshold voltage of any one of the memory cells of the said plurality has reached the predetermined highest-erasure-rate threshold voltage. A method as claimed in claim 15, wherein, in the event that it is determined that none of the said memory cells of the said plurality has reached the said predetermined highest-erasure-rate threshold voltage, a further such erase operation is caused to be performed on the memory cells of the said plurality. A method as claimed in claim 15 or 16, wherein, following such a judgement that the threshold voltage of one of the said memory cells of the said plurality has reached the said predetermined highest-erasure-rate threshold voltage, a further verification operation is carried out in which it is determined individually, for each memory cell of the said plurality, whether the threshold voltage has reached a predetermined lowest-erasure-rate threshold voltage, being the threshold voltage required of that cell of the matrix having the lowest erasure rate, and, if not, the cell concerned is determined as being defective. A nonvolatile semiconductor memory having a matrix (1) of nonvolatile erasable memory cells (Mij) formed at intersections of word lines (WL1 to WLm) and bit lines (BL11 to BL1k, ..., BLn1 to BLnk), a row decoder (3), a column decoder (5), sense amplifiers (7) connected to the bit lines (BL11 to BL1k, ..., BLn1 to BLnk) respectively, and voltage determination means connected to the matrix, characterized in that said voltage determination means comprises: voltage detection means (3, 8, 9, 612, 613) for making all memory cell transistors of the matrix conductive and connecting them in parallel with one another to detect a voltage produced by a current flowing through the memory cell transistors; reference voltage generation means (628); and comparison means (625) for comparing an output voltage (613) of the voltage detection means with a reference voltage provided by the reference voltage generation means (628). The nonvolatile semiconductor memory according to claim 18, wherein: a predetermined voltage is applied to a source line connecting all the sources of the memory cell transistors together, the same or different positive voltages are applied to the source line and all or part of word lines that form control gates of the memory cell transistors, the drains of the cell transistors are connected to a data bus, and the voltage determination means is connected to the data bus. The nonvolatile semiconductor memory according to claim 18, wherein: the sources of the memory cell transistors are connected to a single source line, the drains of the cell transistors are commonly connected to a data bus, the same or different positive voltages are applied to the data bus and all or some of word lines that form the control gates of the memory cell transistors, and the voltage determination means is connected to the source line.

Inventors: AKAOGI TAKAO, KASA YASUSHI, AKAOGI,TAKAO, KASA, YASUSHI, Akaogi,Takao, c/o Fujitsu Ltd., Kasa, Yasushi, c/o Fujitsu Ltd.
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11C29
IPC codes: G11C29, G11C16