Pixel Interpolation Circuit and its Applications

Abstract: In an image processing system, an outline correction of image data and a smoothing for noise removal are performed. Generally, the outline correction is performed by emphasizing a high frequency component, and the smoothing is performed by removing the high frequency component. Within one image data, by properly switching the emphasizing and the removal of the high frequency component, while the outline correction is carried out, the noise removal can be performed. An absolute value of a high frequency component Fa extracted from the image data Pi by a first differential filter (2) is compared with a discrimination threshold value K, and depending on the comparison result, either Fa or -Fa as the correction data Fo is selected by a selctor (6) and is added to the image data Pi. As a result, when Fo = Fa, the high frequency component is emphasized, and when Fo = -Fa, smoothing is performed. A pixel interpolation and a multi picture formation are also disclosed.

Description: The present invention relates to an image processing system, and more particularly to a pixel interpolation circuit for interpolating missing or omitted pixels, and its application in devices for signal processing of video images. Fig. 43 shows a conventional pixel interpolation circuit, for example, as disclosed in Japanese Patent Laid-Open No.Hei 2-131689. in Fig. 43 the pixel interpolation circuit Is comprised of an interpolation data formation circuit 200, a pair of low pass filters (hereinafter referred to as "LPFs") 201a and 201b, a selector circuit 228, a correlative discrimination circuit 229 and a one line delay circuit 230 for delaying the input image data. The interpolation data formation circuit 200 includes registers 207, 208, 209 and 210, adders 211, 212 and 213 and 1/2 (half) multipliers 214, 215 and 216. The LPF 201a includes registers 202a, 203a and 205a and adders 204a and 206a, and the LPF 201b includes registers 202b, 203b and 205b and adders 204b and 206b. The correlative discrimination circuit 229 includes registers 217, 218, 219 and 220, subtracters 221, 222 and 223, absolute value circuits 224, 225 and 226, and a minimum value discrimination circuit 227. Next, the operation of the above-described pixel interpolation circuit will now be described. The input image data Pi are input to the one line delay circuit 230 and are delayed one line therein. The input image data Pi are also input to the interpolation data formation circuit 200 and the LPF 201a, and the one line delayed image data output from the one line delay circuit 230 are input to the interpolation data formation circuit 200 and the LPF 201b. In the interpolation data formation circuit 200, by using the registers 207, 208, 209 and 210, the adders 211, 212 and 213 and the half multipliers 214, 215 and 216, for the interpolation pixel, addition averaging values in the upward, downward and inclined directions are calculated as interpolation data. On the other hand, in the LPF 201a and the LPF 201b, by using the registers 202a, 203a, 205a, 202b, 203b and 205b and the adders 204a, 206a, 204b and 206b, horizontal low frequency components (hereinafter referred to as "horizontal low components") of the respective input image data are picked up and output to the correlative discrimination circuit 229. In the correlative discrimination circuit 229, by using the registers 217, 218, 219 and 220, the subtracters 221, 222 and 223, and the absolute value circuits 224, 225 and 226, differential absolute values in the upward, downward and inclined directions centering around the interpolation pixel are calculated. The calculated differential absolute values are Input to the minimum value discrimination circuit 227, and the minimum value discrimination is performed therein. At this time, the direction of the minimum value is the most correlated direction, and thus the selector circuit 228 selects the interpolation data of the most correlated direction from the three outputs of the multipliers 214, 215 and 216 of the interpolation data formation circuit 200 and outputs the selected interpolation data as the output image data Po. In the conventional pixel interpolation circuit, as described above, relating to an image whose signal frequency band is offset to the low side (hereinafter referred to as "low band image"), a correlative difference among the upward, downward and inclined directions is small, and hence an interpolation result with sufficient effects can not be obtained. Fig. 44 shows a pixel interpolation device of color signals for use in a conventional video printer. In Fig. 44 the pixel interpolation device comprises a Y/C separation circuit 482 for separating a video signal input from an input terminal 481 into a luminance signal Y and a color signals C, an A/D (analog-digital) converter 483 for converting the separated analog color signal C into digital image data, a thinning switch 484 for thinning the conversion data every pixel, and an image memory 433 for storing the thinned conversion data to be output from an output terminal 485. Next, the operation of the above-described pixel interpolation device will now be described. In Fig. 44 the analog color signals C separated in the Y/C separation circuit 482 are sampled by a sampling frequency 2 f sc (subcarrier frequency) in the A/D converter 483 to obtain sampled digital signals 512a. Fig. 45 shows a pixel arrangement of the signals 512a, wherein H represents a one pixel interval and V represents one line interval. Then, the signals 512a are thinned every pixel in the thinning switch 484 to obtain signals 512b. Since the thinned signals 512b are resampled signals every sampling clock f sc, the image information is reduced to the half, and thus the capacity of the image memory 433 for storing the signals 512b can be reduced to the half compared with a case for storing the signals 512a. Fig. 46 shows a pixel arrangement of the signals 512b, wherein X indicates an omitted or missed pixel by the sampling. The image memory 433 stores one frame of the signals 512b at a predetermined timing and outputs from the first line at a predetermined timing. At this time, no particular interpolation calculation for the omitted pixels is not carried out, and the just preceding data as the omitted pixel data can be simply used at it is. In the conventional pixel interpolation device, as described above, no particular interpolation processing for the omitted pixels is performed and thus the image quality is largely deteriorated. Further, the border lines or outlines of the edges in the inclined direction are jagged. According to the present invention, there is provided a pixel interpolation circuit for calculating an interpolation pixel value of a pixel to be interpolated from digital two-dimensional image date input thereto, the circuit comprising: extraction means for extracting, from the input image data, reference pixel data of reference pixels around the pixel to be interpolated; threshold calculation means for calculating a threshold value from the values of said reference pixels; coding means for binary coding said reference pixel data based on said threshold value to represent the direction of change in pixel values of the reference pixels; discrimination means for discriminating an interpolation direction based on the binary coded reference pixel data according to a prestored interpolation table relating possible sets of binary coded reference pixel data to particular interpolation directions; selection means for selecting, from said reference pixels, a plurality of pixels in said interpolation direction; and data calculation means for calculating the interpolation pixel value of the pixel to be interpolated from the pixel values of the selected plurality of pixels. In the pixel interpolation circuit according to the present invention, the reference pixels required for the interpolation are extracted from the input binary image data, and by the combinations of the extracted reference pixels, the interpolation pixels are output. In the pixel interpolation of the present invention, the reference pixels can be directly used as the addresses of the interpolation table. Thus, the good interpolation result can be obtained by the simple structure. As a result of binary coding there reference pixels the omitted pixel to detect the local change direction of the image, and by the detection result, the interpolation directions are properly switched. Hence, the image drop is reduced, and particularly the border lines in the included directions can be smoothed. Preferably said reference pixels are the respective pixels from the horizontal lines above and below the pixel to be interpolated on the same vertical column of the image as said pixel to be interpolated, and the next but one pixels on either side of said respective pixels. Hence, a good interpolation result can be obtained even in the low band image, and the good interpolation result can be obtained at the frequency to be readily recognized. Desirably, said extraction means comprises means for extracting, from the input image data, pixel data of a plurality of pixels around the pixel to be interpolated and means for selecting said reference pixel data therefrom. Thus, the reference pixels can be selected by the characteristic of the input image data. Hence, the good interpolation results can be obtained in both the low band image and the high band image. Also, in the pixel interpolation circuit according to the present invention, the interpolation table may be switched by discriminating that the interpolation part of the input binary image data is the dummy gradation part or the character part. In the pixel interpolation of the present invention, the interpolation table for the dummy gradation part and the interpolation table for the character part are mutually switched (passive). Hence, the good interpolation results can be obtained in both the dummy gradation part and the character part. The pixel interpolation circuit according to the present invention may be used in an image transmission device. In this case, the uncorrected error pixel data within the error of the received image data detected by the error correction code can be corrected in the pixel interpolation circuits. In such image transmission, the uncorrected data by the error correction code within the detected data errors can be replaced with the interpolation data. Hence, the image with no data omission can be transmitted. The pixel interpolation circuit according to the present invention may be used in a pixel correction device. In this case, the output image signals of the CCD image sensor are quantized, and the obtained image data are input to the pixel interpolation circuit to calculate the interpolation data. By comparing the interpolation data with the output data of the CCD, the trouble of the CCD is detected, and the omitted data can be replaced with the interpolation data. In such pixel correction of the present invention, the omitted pixels by the trouble of the CCD image sensor can be interpolated. Hence, the error pixels caused in the image sensor are corrected to obtain the good output image, and the yield improvement of the CCD sensor can be expected. Further, the pixel interpolation according to the present invention may be used in a dropout correction device according to the present invention. In this case, the image signals reproduced in the VTR are quantized with the predetermined sampling frequency, and the image data are input to the pixel interpolation circuits described above to calculate the interpolation data. When the dropout is detected in the reproduction of the VTR, the omitted pixels by the dropout are replaced with the interpolation pixels obtained by the pixel interpolation circuit to correct the dropout. In such dropout correction of the present invention, at the dropout occurrence time, the dropout data can be replaced with the interpolation data. Thus, the influence of the dropout given to the image can be reduced to the minimum. Further, the pixel interpolation according to the present invention may be used in a signal processing device which includes means for converting the two-dimensional matrix sampled data group to the offset sampled data group, the memory means for storing the offset sampled data group, and the pixel interpolation device for restoring the matrix sampled data group by calculating the interpolation value of the omitted pixels read out of the memory means so as to reduce the memory capacity to the half. As the pixel interpolation device, any of the above-described interpolation devices can be used. The present invention will now be described by way of non-limitative example in connection with three groups of preferred embodiments with reference to the accompanying drawings, wherein like reference characters designated like or corresponding parts throughout the views and thus the repeated description thereof can be omitted for brevity. In the drawings: Fig. 1 is a block diagram of an embodiment 1-1 of a pixel interpolation circuit according to the present invention; Fig. 2 is a block diagram of one embodiment of a delay circuit; Fig. 3 is a block diagram of one embodiment of a threshold calculation circuit; Fig. 4 is a block diagram of one embodiment of a binary coding circuit; Fig. 5 is a block diagram of one embodiment of an interpolation direction discrimination circuit; Fig. 6 is a block diagram of one embodiment of a selecting circuit used in a pixel interpolation circuit; Fig. 7 is a schematic view showing a part of quantized two-dimensional image data shown in a pixel interpolation circuit; Fig. 8 is a schematic view showing a interpolation table used in a pixel interpolation circuit; Fig. 9 is a block diagram of another embodiment of a threshold calculation circuit; Fig. 10 is a block diagram of another embodiment of an interpolation direction discrimination circuit; Fig. 11 is a block diagram of an embodiment 1-2 pixel interpolation circuit according to the present invention; Fig. 12 is a block diagram of one embodiment of a delay circuit shown in Fig. 11; Fig. 13 is a block diagram of an embodiment 1-3 pixel interpolation circuit according to the present invention; Fig. 14 is a block diagram of one embodiment of a delay circuit shown in Fig. 13; Fig. 15 is a schematic view showing a part of quantized two-dimensional image data shown in Figs. 13 and 14; Fig. 16 is a schematic view showing another interpolation table; Fig. 17 is a block diagram of an embodiment 1-4 pixel interpolation circuit; Fig. 18 is a block diagram of an embodiment 1-5 image transmission device; Fig. 19 is a schematic view showing a part of quantized two-dimensional image data shown Fig. 18; Fig. 20 is a schematic view showing a part of quantized two-dimensional image data including error pixels shown Fig. 18; Fig. 21 is a block diagram of an embodiment 1-6 pixel correction device according to the present invention; Fig. 22 is a block diagram of an embodiment 1-7 of a dropout correction device according to the present invention; Fig. 23 is a schematic view showing a part of quantized two-dimensional image data including error pixels shown Fig. 22; Fig. 24 is a block diagram of an embodiment 2-1 of a pixel interpolation device according to the present invention; Fig. 25 is a schematic view showing a pixel arrangement used in the device shown in Fig. 24; Fig. 26 is schematic view showing a binary coding pattern used in the device shown in Fig. 24; Fig. 27 is a schematic diagram showing a pattern table for setting directions of interpolation reference pixels for a binary coding pattern used in the device shown in Fig. 24; Figs. 28 and 29 are schematic views showing binary coding patterns used in the device shown in Fig. 24; Fig. 30 is a block diagram of a threshold value calculation circuit of an embodiment 2-2 of a pixel interpolation device according to the present invention; Fig. 31 is a block diagram of an embodiment 2-3 of a pixel interpolation device according to the present invention, applied to a signal processing device having an image memory such as a video printer or the like; Fig. 32 is a schematic view of a pixel arrangement for explaining a block extraction in the device shown in Fig. 31; Fig. 33 is a block diagram of embodiment 2-4 of a digital coding transfer device of image signals, including a pixel interpolation device according to the present invention; Fig. 34 is a block diagram of embodiment 2-5 of a pixel data correction device including a pixel interpolation device according to the present invention; Fig. 35 is a block diagram of an embodiment 3-1 of a pixel interpolation device according to the present invention; Fig. 36 is a schematic view of a binary coding pattern for explaining a binary coding process in the device shown in Fig. 35; Figs. 37a, 37b and 37c are schematic diagrams showing correlativity of data of pixel blocks used in the device shown in Fig. 35; Figs. 38 and 39 are schematic views binary coding patterns used in the device shown in Fig. 35; Fig. 40 is a block diagram of an embodiment 3-2 of a pixel interpolation device according to the present invention; Fig. 41 is a block diagram of an embodiment 3-3 of a pixel interpolation device according to the present invention; Fig. 42 is a block diagram of an embodiment 3-4 of a pixel interpolation device according to the present invention; Fig. 43 is a block diagram of a conventional pixel interpolation circuit; Fig. 44 is a block diagram of a conventional pixel interpolation device; Fig. 45 is a schematic view of a pixel arrangement of signals shown in Fig. 44; and Fig. 46 is a schematic view of a pixel arrangement of thinned signals shown in Fig. 44. The first group of the preferred embodiments of the present invention will now be described. In Fig. 1, there is shown the embodiment 1-1 of a pixel interpolation circuit according to the present invention. As shown in Fig. 1, the pixel interpolation circuit is comprised of a delay circuit 301 for delaying the input image data Pi a predetermined time, a correlative discriminator 302 for discriminating correlativity of the images, and an interpolation calculator 306. The correlative discriminator 302 includes a threshold value calculation circuit 303, a binary coding circuit 304 and an interpolation direction discrimination circuit 305. An interpolation calculator 306 includes a selector circuit 307, an adder 308 and a multiplier 309. In Fig. 1 there are shown reference pixel data a, c, e, f, h and j which are picked up by the delay circuit 301 and are required for the interpolation, a threshold value TH, binary codes ℓ, m, n, x, y and z of the picked pixels, interpolation direction selection data IS, data PU and PD selected for the interpolation by the selector circuit 307, and an interpolation result Po output by the multiplier 309. Fig. 2 shows one embodiment of the delay circuit 301 used in a pixel interpolation circuit according to the present invention, including registers 310a to 310j composed of delay elements of one pixel, and a one line delay circuit 311. Fig. 3 shows one embodiment of the threshold calculation circuit 303 used in a pixel interpolation circuit according to the present invention, including a maximum value detecting circuit 312, a minimum value detecting circuit 313, an adder 314 and a half (1/2) multiplier 315. Fig. 4 illustrates one embodiment of the binary coding circuit 304 used in a pixel interpolation circuit according to the present invention, including a plurality of comparators 316a to 316f connected in parallel. Fig. 5 shows one embodiment of the interpolation direction discrimination circuit 305 used in a pixel interpolation circuit according to the present invention, including an interpolation table 317. Fig. 6 shows one embodiment of the selector circuit 307 used in a pixel interpolation circuit according to the present invention, including two selectors 318a and 318b. Next, the operation of the pixel interpolation circuit described above will now be described. The two-dimensional image data quantized by a predetermined sampling frequency are input to the delay circuit 301. As shown in Fig. 2, the image data Pi are delayed the predetermined time by the registers 310a to 310j and the one line delay circuit 311, and the reference pixel data a, c, e, f, h and j are extracted. Fig. 7 shows a relationship between a pointed pixel Po and reference pixels, wherein o represents a sample pixel and x represents an interpolation pixel. The reference pixel data a, c, e, f, h and j extracted by the delay circuit 301 are input to the threshold value calculation circuit 303, the binary coding circuit 304 and the selector circuit 307. As shown in Fig. 3, in the threshold value calculation circuit 303, the maximum value of the reference pixel data a, c, e, f, h and j is detected by the maximum value detecting circuit 312 and the minimum value of the reference pixel data a, c, e, f, h and j is detected by the minimum value detecting circuit 313. The detected maximum and minimum values are added by the adder 314, and the addition result is multiplied by 1/2 in the half multiplier 315 to obtain the threshold value TH. The threshold value TH is input to the binary coding circuit 304. In the binary coding circuit 304, as shown in Fig. 4 the threshold value TH is compared with the reference pixel data a, c, e, f, h and j in respective comparators 316a to 316f. When a, c, e, f, h or j ≧ TH, each of the comparators 316a to 316f outputs "1", and when a, c, e, f, h or j < TH, each of the comparators 316a to 316f outputs "0". The comparators 316a to 316f output the comparison results, that is, the binary codes ℓ, m, n, x, y and z as the addresses of the interpolation table 317 in the interpolation direction discrimination circuit 305, as shown in Fig. 5 and the interpolation direction selection data IS are output to the selector circuit 307 from the interpolation table 317. In the selector circuit 307, as shown in Fig. 6 by the interpolation direction selection data IS, the selectors 318a and 318b select any of a vertical interpolation, a right slant interpolation and a left slant interpolation. in the vertical interpolation, the selectors 318a and 318b selects the reference pixels c and h input to the terminals B and outputs the selected reference pixels c and h as the data PD and PU. Then, the adder 308 adds the reference pixels c and h, and the addition result is multiplied by 1/2 in the multiplier 309 to output the interpolation result Po. In the right slant interpolation, the selectors 318a and 318b selects the reference pixels e and f input to the terminals C, and in the left slant interpolation, the selectors 318a and 318b selects the reference pixels a and j input to the terminals A. Then, the operation is performed in the same manner as described above to output the interpolation result Po. Fig. 8 illustrates one embodiment of the interpolation table showing the relationship between the interpolation directions and the binary codes ℓ, m, n, x, y and z at this time, wherein a white circle o represents "0" of the binary code and a black circle o represents "1" of the binary code. in the interpolation table shown in Fig. 8 combinations of x, y and z are shown in the top from the left such as u0, u1, u2, u3, u4, u5, u6 and u7, and combinations of ℓ, m and n are shown in the left hand side from the top such as d0, d1, d2, d3, d4, d5, d6 and d7. For instance, as shown in Fig. 8 when xyz is u0 and ℓmn is dO, the vertical interpolation is selected, and when selecting a combination of u7 - d6 or ul - d7, the right slant interpolation or the left slant interpolation is selected. Fig. 9 shows another embodiment of the threshold calculation circuit 303 used in a pixel interpolation circuit according to the present invention, including adders 319a to 319e and a 1/6 multiplier 320. The operation of this threshold value calculation circuit 303 will now be described. As shown in Fig. 9 the reference pixel data a, c, e, f, h and j extracted by the delay circuit 301 are successively added by the adders 319a to 319e, and the addition result is multiplied by 1/6 in the multiplier 320 to output the threshold value TH as follows. TH = (a + c + e + f + h + j)/6 The other part of the operation is the same as the above-described embodiment and thus can be omitted for brevity. Fig. 10 shows another embodiment of the interpolation direction discrimination circuit 305 used in a pixel interpolation circuit according to the present invention, including two decoders 321 and 322 and a selection signal generating circuit 323. The operation of this interpolation direction discrimination circuit 305 will now be described. As shown in Fig. 10 the binary codes ℓmn and xyz output from the binary coding circuit 304 are input to the decoders 321 and 322, respectively, and are decoded therein to output respective decoded results to the selection signal generating circuit 323. Depending on the combinations of the decoded results, the selection signal generating circuit 323 generates the interpolation direction selection data IS on the basis of the interpolation table shown in Fig. 8 and outputs the interpolation direction selection data IS to the selector circuit 307. The other part of the operation is the same as the embodiment described above and thus can be omitted for brevity. In Fig. 11 there is shown the embodiment 1-2 of an pixel interpolation circuit according to the present invention, having the same construction as the embodiment 1-1 shown in Fig. 1 except that a selector circuit 324 is further provided. A selection signal Si is input to the selector circuit 324. Fig. 12 shows one embodiment of the delay circuit 301 of the embodiment 1-2 shown in Fig. 12 including a plurality of registers 310a to 310j to output respective extracted pixel data a, b, c, d, e, f, g, h, i and j and the one line delay circuit 311. Next, the operation of the pixel interpolation circuit described above will now be described. The two-dimensional image data quantized by predetermined sampling frequency are input to the delay circuit 301. As shown in Fig. 12 the image data Pi are delayed the predetermined time by the registers 310a to 310j and the one line delay circuit 311 to extract the pixel data a, b, c, d, e, f, g, h, i and j. As described above, Fig. 7 shows the relationship between the pointed pixel Po and the extracted pixels, wherein o represents the sample pixel and x represents then interpolation pixel. The pixel data a, b, c, d, e, f, g, h, i and j extracted by the delay circuit 301 are input to the selector circuit 324. In the selector circuit 324, when the band of the input image data Pi is low, the pixel data a, c, e, f, h and j are selected in the same manner as the embodiment 1-1 and are output as reference pixel data s1, s2, s3, s4, s5 and s6 to the threshold value calculation circuit 303, the binary coding circuit 304 and the selector circuit 307. When the band of the input image data Pi is high, the selector circuit 324 selects the pixel data b, c, d, g, h and i and outputs these pixel data as the reference pixel data s1, s2, s3, s4, s5 and s6. The other part of the operation is the same as the embodiment 2-1 described above and thus can be omitted for brevity. As regard the examples of the low band case and the high band case, a television broadcasting image (low) and scanner color separation images (high) can be given. Further, in the television broadcasting image, a person close-up image (low) and a landscape image (high) can be given. In Fig. 13 there is shown the embodiment 2-3 of a pixel interpolation circuit according to the present invention, including a delay circuit 325 for delaying input binary image data Bi a predetermined time, and an interpolation discrimination circuit 326 to output interpolated pixel data Bo. Fig. 14 shows one embodiment of the delay circuit 325 shown in Fig. 13 including a plurality of registers 327a to 327f to output extracted reference pixel data a, b, c, d, e and f and a one line delay circuit 328. Fig. 30 shows a relationship between the interpolated pixel data Bo and the reference pixel data a, b, c, d, e and f shown in Figs. 13 and 14. Next, the operation of the pixel interpolation circuit described above will now be described. The input binary image data Bi are input to the delay circuit 325 and are delayed the predetermined time by the registers 327a to 327f and the one line delay circuit 328 to extract the reference pixel data a, b, c, d, e and f, as shown in Fig. 14. The extracted reference pixel data a, b, c, d, e and f are input to the interpolation discrimination circuit 326. Fig. 16 shows another interpolation table used in a pixel interpolation circuit according to the present invention, which is comprised of combinations of the reference pixel data abc and def in a similar manner to the interpolation table shown In Fig. 8. In the interpolation discrimination circuit 326, by using the reference pixel data a, b, c, d, e and f as the addresses, the interpolated pixel data Bo are output on the basis of the interpolation table shown in Fig. 16. In this case, the interpolation discrimination circuit 326 can be constructed in the same manner as shown in Fig. 10. In Fig. 17, there is shown the embodiment 2-4 of a pixel interpolation circuit according to the present invention, including a delay circuit 325, a first interpolation discrimination circuit 326a, a second interpolation discrimination circuit 326b, a dummy gradation discrimination circuit 329 and a selector circuit 330. Next, the operation of the pixel interpolation circuit described above will now be described. Input binary image data Bi are input to the delay circuit 325 and the dummy gradation discrimination circuit 329. The delay circuit 325 delays the binary image data Bi the predetermined time to extract reference pixel data a, b, c, d, e and f for interpolation pixel data Bo. The extracted reference pixel data are input to the first interpolation discrimination circuit 326a for a character part and the second interpolation discrimination circuit 326b for a dummy gradation part. The first and second interpolation discrimination circuits 326a and 326b output the interpolation results according to the input reference pixel data. On the other hand, the dummy gradation discrimination circuit 329 discriminates which the binary image data Bi are the dummy gradation part or the character part and control the selector circuit 330 on the basis of the discrimination result. The selector circuit 330 selects the output of the first interpolation discrimination circuit 326a when the binary image data Bi are the dummy gradation part or the output of the second interpolation discrimination circuit 326b when the binary image data Bi are the character part. The selector circuit 330 outputs the selected output as the interpolated pixel data Bo. The other part of the operation is the same as the embodiment 1-3 described above and thus can be omitted for brevity. In Fig. 18, there is shown the embodiment 1-5 of an image transmission device including the pixel interpolation circuit described above according to the present invention. As shown in Fig. 18, the image transmission device comprises a coder 331 for coding sending image data IMGi, a modulator 332 for modulating the coded data, a transmission line 333 for transmitting the modulated data, a demodulator 334 for demodulating the transmitted data, a decoder 335 for decoding the demodulated data, a pixel interpolation circuit 336 described above in the embodiment 1-1 or 1-2, and a selector circuit 337 for selecting either the interpolated data Po of the pixel interpolation circuit 336 or the output of the decoder 335 to output received image data IMGo. Next, the operation of the image transmission device described above will now be described. The sending image data IMGi are coded in the coder 331 and are then modulated in the modulator 332. The coded and modulated data are sent to the demodulator 334 via the transmission line 333, and the demodulator 334 demodulates the input data to output the demodulated data to the decoder 335. In the decoder 335, the input data are decoded and a detection and a correction of error in the data are performed at the same time to obtain decoded image data Pi. The image data Pi are input to the pixel interpolation circuit 336 to output the interpolation result Po in the same manner as described above. The image data Pi and the interpolated result Po are input to the selector circuit 337, and the selector circuit 337 is controlled by a control signal output from the decoder 335 so that the uncorrected error data in the detected and received data may be replaced by the interpolated data Po. As a result, the output signals of the selector circuit 337 become the received image data IMGo. Figs.19 and 20 show the part of the received image data IMGo. In Figs. 19 and 20, o represents the sample pixel and x represents the uncorrected error pixel. Fig. 19 shows a state of the image data with no error pixel data impossible to be corrected, and in Fig. 20, there are shown the error pixels impossible to be corrected in the line n and the columns m-1, m and m+1. By replacing the error pixel data in Fig. 20 with the interpolated data Po, the received image data IMGo can be obtained. In Fig. 21, there is shown the embodiment 1-6 of a pixel correction device according to the present invention. As shown in Fig. 21, the pixel correction device comprises a lens 340 of a camera, a CCD image sensor 341, an image signal processor 342 for performing a noise removal, a synchronous signal addition and the like of the output of the CCD image sensor 341, a sensor driving circuit 343 for the CCD image sensor 341, a synchronism generating circuit 344, an A/D converter 345 for quantizing the image signals, a pixel interpolation circuit 336 described above in the 1-1 or embodiment 1-2 a subtracter 346, an absolute value circuit 347, a comparator 348, a selector circuit 349, a D/A converter 350 and a monitor 351. Next, the operation of the pixel correction device described above will now be described. An image focused on the lens 340 is photoelectrically converted by the CCD image sensor 341 and is output in a predetermined order by the sensor driving circuit 343. The output of the CCD image sensor 341 is successively processed by the image signal processor 342 and the A/D converter 345 to obtain the quantized image data Pi. The image data Pi are input to the pixel interpolation circuit 336 to output the Interpolation result Po in the same manner as described above. The image data Pi and the interpolated data Po are input to the subtracter 346, and the subtraction result is input to the absolute value circuit 347. The absolute value circuit 347 outputs the obtained differential absolute value to the comparator 348, and a threshold value S is also input to the comparator 348 from the outside. The comparator 348 compares the differential absolute value with the threshold value S. When the differential absolute value is larger than the threshold value S, it is discriminated to be error of the pixel of the CCD image sensor 341, and the data Pi of the error pixel are replaced with the interpolated data Po by the selector circuit 349. As described above, Figs. 19 and 20 shou the part of the received image data IMGo. In Figs. 19 and 20,o represents the sample pixel and x represents the error pixel of the error pixel data of the CCD image sensor 341. Fig. 19 shows the state of the image data with no error pixel data, and in Fig. 20, there are shown the error pixels of the error pixel data in the line n and the columns m-1, m and m+1. By replacing the error pixel data in Fig. 20 with the interpolated image data Po, the corrected image data can be obtained. The corrected image data are converted to the analog signals in the D/A converter 350 and the analog signals are sent to the monitor 351 to display a corrected image. In Fig. 22 there is shown the embodiment 1-7 of a dropout correction device according to the present invention. As shown in Fig. 22 the dropout correction device is comprised of a video tape 360, a head 361, a reproducing amplifier 362, a color signal processing circuit 363 to output a color signal C, an FM demodulator 364, a dropout detector 365, an image signal processing circuit 366, an A/D converter 367, an pixel interpolation circuit 336 described above in the embodiment 1-1 or 1-2 a selector circuit 368 and a D/A converter 369 to output a luminance signal Y. Next, the operation of the dropout correction device described above will now be described. An FM modulated video signal recorded on the video tape 360 is picked up by the head 361 and is amplified by the reproducing amplifier 362. The amplified signal is separately processed in a color signal process system and a luminance signal process system. That is, in the color signal process, the amplified signal is fed to the color signal processing circuit 363 and the color signal processing circuit 363 processes the signal to output the color signal C. On the other hand, in the luminance signal process, the amplified signal is input to the FM demodulator 364 and the dropout detector 365. The FM demodulator 364 demodulates the amplified signal and outputs the demodulated signal to the image signal processing circuit 366, and the image signal processing circuit 366 carries out a signal processing such as a band restriction, an de-emphasis and so forth of the input signal and outputs the processed signal to the A/D converter 367. The A/D converter 367 converts the analog signal to the digital signal to obtain the quantized image data Pi. The image data Pi are processed in the pixel interpolation circuit 336 to output the interpolated data Po in the same manner as described above. The image data Pi and the interpolated data Po are input to the selector circuit 368, and by a control signal output from the dropout detector 365, the selector circuit 368 replaces data on a line the dropout occurs with the interpolation data Po and outputs the corrected image data to the D/A converter 369. Figs. 19 and 23 show the part of the reproduced image data Pi. In Figs. 19 and 23, o represents the sample pixel and x represents the error pixel of the error pixel data by the dropout. Fig. 19 shows the state of the image data that no dropout occurs, and Fig. 23 shows the state that the dropout is caused in the line n. The selector circuit 368 replaces the pixel data on the line n with the interpolated image data Po to output the corrected image data to the D/A converter 369. The D/A converter 369 converts the dropout-corrected image data to the analog signal and outputs the luminance signal Y without no dropout. As described above, according to the present invention, the interpolation reference pixels are selected every other pixel to properly perform the interpolation, and hence the good interpolation results against the low frequency image data can be obtained. Further, according to the present invention, for the binary image, the interpolation is suitably performed by using the interpolation table, and thus the good interpolation results can be obtained for the binary image as well. Further, according to the present invention, the error pixels occurring in the image data are corrected by the proper pixel interpolation, and hence the good correction results can be obtained at the outline parts as well. Next, the second group of the preferred embodiments of the present invention will be described. In Fig. 24, there is shown the embodiment 2-1 of a pixel interpolation device according to the present invention. As shown in Fig. 24, the pixel interpolation device is comprised of a block extracting circuit 411 for extracting a block around an omitted pixel of partly omitted digital video signals input from an input terminal 401, a threshold value calculation circuit 402 for calculating a threshold value from extracted block data, a binary coding circuit 416 for coding the block data to form binary codes on the basis of the threshold value calculated by the threshold value calculation circuit 402, a pattern table 417 for setting all combination patterns of previously prepared binary code data and interpolation directions thereof, a pattern table reference circuit 418 for determining the interpolation direction by referring the pattern table 417 and the binary code data, an interpolation reference pixel selecting circuit 419 for selecting necessary pixel data for calculating an interpolation pixel value depending on the output of the pattern table reference circuit 418, and an interpolation pixel value calculation circuit 403 for calculating the interpolation pixel value from the data selected by the interpolation reference pixel selecting circuit 419. The threshold value calculation circuit 402 includes a maximum value calculation circuit 412 for calculating the maximum value from the extracted block data, a minimum value calculation circuit 413 for calculating the minimum value of the extracted block data, an adder 414 for adding the outputs of the maximum value calculation circuit 412 and the minimum value calculation circuit 413, and a 1/2 factor circuit 415 for multiplying 1/2 to the output of the adder 414. The interpolation pixel value calculation circuit 403 includes an adder 420 for adding the output data (e, f, g and h) of the interpolation reference pixel selecting circuit 419, and a 1/4 factor circuit 421 for multiplying 1/4 to the output of the adder 420 to output a result to an output terminal 404. Next, the operation of the pixel interpolation device described above will now be described. in this embodiment, for example, a case for interpolating an omitted pixel P shown in Fig. 25 will be described. First, the block extracting circuit 411 extracts 4 peripheral pixels a, b, c and d adjacent to the four sides of the omitted or interpolation pixel P. Now, assuming that the luminance of the 4 pixels are a = 70, b = 80, c = 90 and d = 200, the maximum value of the 4 pixels is 200, and the minimum value of the 4 pixels is 70. Hence, the threshold value TH is calculated as follows. TH = (maximum value + minimum value)/2 = 135 On the basis of this threshold value TH, the binary code data a', b', c' and d' are obtained under the following conditions by the binary coding circuit 416 as follows. X' = "0" (X ≦ TH) = "1" (X > TH) (X: any of a, b, c and d) By this calculation, a', b', c' and d' are obtained as shown in Fig. 26, that is, a' = "0", b' = "0", c' = "0" and d' = "1". On the other hand, in the pattern table 417, as shown in Fig. 27, all combination patterns to be obtained by the binary coding and the directions of the interpolation reference pixels corresponding to the combination patterns are stored. The directions of the interpolation reference pixels are determined by considering the directions of the edges of the image by the binary code patterns. In the pattern table reference circuit 418, the binary code data a', b', c' and d' and the pattern table 417 are referred to determine the direction or directions of the interpolation reference pixels. For example, the pattern shown in Fig. 26 is coincident with a pattern N shown in Fig. 27. Hence, the interpolation reference pixel direction is the horizontal direction, and the interpolation pixel value p is calculated as follows. p = (b + c + b + c)/4 That is, as shown in Fig. 27, regarding the pattern N, the interpolation reference pixels are b and c, and their average value becomes the above-described interpolation pixel value p. Also, in case of a pattern shown in Fig. 28, it is coincided with a pattern D shown in Fig. 27. Thus, the interpolation reference pixel direction is the vertical direction, and the interpolation pixel value p is obtained as follows. p = (a + d + a + d)/4 Further, in case of a pattern shown in Fig. 29 it is coincident with a pattern C in Fig. 27. Accordingly, the interpolation reference pixel directions are the horizontal and vertical directions, and the interpolation pixel value p is calculated as follows. p = (a + b + c + d)/4 That is, in the interpolation reference pixel selecting circuit 419, depending on the output signal of the pattern table reference circuit 418, the output data of e, f, g and h are output as follows. That is, when the output of the pattern table reference circuit 418 is the horizontal direction, b, b, c and c are output, and when the vertical direction is output from the pattern table reference circuit 418, a, a, d and d are output. Also, when the horizontal and vertical directions are output from the pattern table reference circuit 418, a, b, c and d are output. These output data are calculated in the interpolation pixel value calculation circuit 403 as follows. p = (e + f + g + h)/4 In Fig. 30, there is shown another embodiment of the threshold value calculation circuit of the embodiment 2-2 of a pixel interpolation device according to the present invention. In this embodiment, that is, the other part of the structure is the same as the embodiment 2-1 shown in Fig. 24. The threshold value calculation circuit 402 includes an adder 422 for adding the 4 pixels a, b, c and d, and a 1/4 factor circuit 423 for multiplying 1/4 to the output of the adder 422. Hence, the threshold value TH is obtained from the 4 pixels a, b, c and d extracted by the block extracting circuit 411 in the threshold value calculation circuit 402 as follows. TH = (a + b + c + d)/4 In this embodiment, the circuit structure of the threshold value calculation circuit 402 can be simplified, and almost the same operation can be expected. In Fig. 31 there is shown the embodiment 2-3 of a signal processing device with an image memory such as a video printer or the like according to the present invention, to which the embodiment 2-1 of the pixel interpolation device is applied. As shown in Fig. 31,, in addition to the parts shown in Fig. 24, he signal processing device further comprises a sampling switch 432 for thinning the digital video data input from an input terminal 431 every pixel, an image memory 433 for storing the output of the sampling switch 432, an input terminal 434 for inputting a still image/motion image switching signal, two one-line memories 435 and 436, an adder 437 for adding the output of the one-line memory 436 and the output of the pixel interpolation device, a 1/2 factor circuit 438 for multiplying 1/2 to the output of the adder 437, and a selector 439 connected to an output terminal 440. Next, the operation of the signal processing device described above will now be described. Input signals 503a obtained by sampling certain video signals are input to the input terminal 431. In this case, the video signals constitute one field of image by 1/60 see and two fields of image by 1/30 see, and two fields constitute one frame or one picture. The input signals 503 are thinned by the sampling switch 432 to obtain thinned signals 503b. Fig. 32 shows a part of a pixel arrangement of the thinned signals 503b in frame unit, and, as shown in Fig. 32, by the sampling switch 432, the phase is inverted every other line within the field and the data are thinned every other pixel. In Fig. 32, H represents one pixel interval in the horizontal direction (hereinafter referred to as "one pixel interval") and V represents one line interval in the frame. One frame of the signals 503b are once stored in the image memory 433, and then the missed or omitted pixels shown in Fig. 32 are interpolated. Now, for example, the interpolation of the pixels P 0 and P 1 shown in Fig. 32 will be described. First, in response to the still image/motion image switching signal input to the input terminal 434, peripheral 4 pixels a, b, c and d are extracted in the block extracting circuit 411. In Fig. 32, at the interpolation of the pixel P o , in case of the still image, with respect to a, b, c and d, a1, b0, c0 and d0 are extracted and in case of the motion image, a0, b0, c0 and d0 are extracted. Also, at the interpolation of the pixel P 1 , in case of the still image, a1, b1, c1 and d0 are extracted and in case of the motion image, a1, b1, c1 and dl are extracted. That is, at the interpolation of the still image, the pixels nearest the omitted pixel to be interpolated within the frame are extracted and, in turn, at the interpolation of the motion image, since there is a time difference between the first and second fields and one picture is formed by one field, the pixels nearest the omitted pixel within the same field are extracted. Next, by using the extracted 4 pixels, the interpolation pixel value 503c is calculated in the pixel interpolation device according to the process of the embodiment 2-1 described above. In case of the motion image, as described above, one picture is formed by using only the first or second field. In this case, the one-line memories 435 and 436, the adder 437 and the 1/2 factor circuit 438 shown in Fig. 31 are provided for forming the omitted line of the data, and the interpolation pixel data 503c and the data 503d of two lines earlier than the data 503 (the data of one preceding line within the field) are added in the adder 437, and the addition result is multiplied by 1/2 in the 1/2 factor circuit 438 to obtain an average value 503e. The average value 503e and one line delayed data 503f of the interpolation pixel data 503 are input to the selector 439, and in the selector 439, one of the data 503e and 503f is selected in response to the still image/motion image switching signal input to the input terminal 434. That is, at the still image interpolation, the data 503f are selected, and at the motion image interpolation, the data 503e and 503f are alternately switched every line. By such an operation, the edges in the inclined directions of the image can be smoothed, and the image quality can be improved. In Fig. 33, there is shown the embodiment 2-4 of a digital image data transmission device including the pixel interpolation device described above, according to the present invention. As shown in Fig. 33, the digital image data transmission device comprises a coder 452 for coding video signal input from an input terminal 451, a modulator 453 for modulating the output of the coder 452, a transmission line 454 for transmitting the data modulated by modulator 453, a demodulator 455 for demodulating the transmitted data, a decoder 456 for decoding the data demodulated by the demodulator 455, a pixel interpolation device 500 described above in the embodiment 2-1 or 2-2 and a selector 457 for selecting either the output 504a of the pixel interpolation device 500 or the output 504b of the decoder 456 on the basis of error detection data output from the decoder 456 to output the selected one to an output terminal 458. Next, the operation of the digital image data transmission device described above will now be described. The video signals input from the input terminal 451 are coded in the coder 452 and the coded data are then modulated in the modulator 453. The modulated data are transmitted to the demodulator 455 via the transmission line 454, and the transmitted data are demodulated in the demodulator 455, and the demodulated data are then decoded in the decoder 456 while errors are detected at the same time. The obtained image data are Pi are input to the pixel interpolation device 500. In the pixel interpolation device 500, the interpolation data 504a of each pixel are calculated and are input to the selector 457. The coded data 504b are also input to the selector 457 from the decoder 456. In the selector 457, the error pixel data of the coded data 504b output from the decoder 456 are replaced with the interpolation data 504a output from the pixel interpolation device 500 on the basis of the error detection data output from the decoder 456 to output the corrected image data from the output terminal 458. In this embodiment, the uncorrected data caused by the image data transmission are interpolated by using the correct image data to improve the quality of the received image. In Fig. 34, there is shown the embodiment 2-5 of a pixel data correction device including the interpolation device described above, for correcting error pixel data caused by a pixel omission of a CCD sensor in a CCD camera according to the present invention. As shown in Fig. 34, the pixel data correction device comprises a lens 460 of a camera, a CCD image sensor 461 for photoelectrically converting an image picked up by the lens 460 to obtain image signals, a synchronism generating circuit 462 for generating a synchronous signal for forming the image signals, a sensor driving circuit 463 for generating a clock for driving the CCD image sensor 461 by the synchronous signal generated by the synchronism generating circuit 462, an image signal processing circuit 464 for performing a noise removal, a synchronous signal addition and the like of the output of the CCD image sensor 461, an A/D converter 465 for performing an A/D conversion of the output of the image signal processing circuit 464, a pixel interpolation device 500 described above in the embodiment 2-1 or 2-2 a subtracter 466 for subtracting the output 505b of the pixel interpolation device 500 from the output 505a of the A/D converter 465, an absolute value circuit 467 for calculating an absolute value of the output of the subtracter 466, a comparator 468 for comparing the output 505c of the absolute value circuit 467 with threshold data 505d input from a threshold input terminal 469, a selector 470 for selecting either the output 505a of the A/D converter 465 or the output 505b of the pixel interpolation device 500 on the basis of the output of the comparator 468, a D/A converter 471 for carrying out a D/A conversion of the output of the selector 470 and a monitor 472 for displaying the output of the D/A converter 471. Next, the operation of the pixel data correction device described above will now be described. In Fig. 34, an image focused on the lens 460 is photoelectrically converted by the two-dimensional CCD image sensor 461 and is successively output in a predetermined order in synchronism with the clock signal output from the sensor driving circuit 463. The output of the CCD image sensor 461 is successively processed in the image signal processor 464 and the A/D converter 465 to obtain the image data 505a. The image data 505a are input to the pixel interpolation circuit 500 to output the interpolated data 505b in the same manner as described above. The image data 505a and the interpolated data 505b are input to the subtracter 466, and the subtraction result is input to the absolute value circuit 467. The absolute value circuit 467 outputs the obtained differential absolute value to the comparator 468, and the threshold value 505d is also input to the comparator 468 from the outside. The comparator 468 compares the differential absolute value 505c with the threshold value 505d in order to discriminate whether or not the image data 505a are error. As a result, When it is discriminated to be error of the pixel of the CCD image sensor 461, the data 505a of the error pixel are replaced with the interpolated data 505b by the selector circuit 470. That is, when 505c > 505d, it is discriminated to be error and thus the data 505a are replaced with the data 505b in the selector 470. On the other hand, when 505c ≦ 505d, it is discriminated to be correct and the data 505a are not replaced and are output as it is. The corrected image data are output from the selector 470 to the D/A converter 471 and are converted to the analog signals in the D/A converter 471 and the obtained analog signals are sent to the monitor 472 to display a corrected image. in this embodiment, the correction of the helpless pixel omission within the CCD image sensor 461 can be possible, and the yield in the product fabrication can be improved. As described above, in the pixel interpolation device according to the present invention, by binary-coding the pixel data of the peripheral pixel block around the omitted pixel, the direction of the local change in the image is assumed, and depending on this result, the interpolation data are formed. Hence, the deterioration of the image quality is small, particularly, the smoothed border lines in the inclined directions can be obtained in the image. Further, by adding the pixel interpolation device to the CCD sensor, the yield of the CCD sensor can be improved. Next, the third group of the preferred embodiments of the present invention will be described. In Fig. 35, there is shown the embodiment 3-1 of a pixel interpolation device according to the present invention. As shown in Fig. 35, the pixel interpolation device comprises a block extracting circuit 911 for extracting a block surrounding an omitted pixel of partly omitted digital video signals input from an input terminal 901 to output block data a, b, c and d of extracted 4 pixels, a maximum value output circuit 912 for outputting the maximum value of the data a and b, a maximum value output circuit 913 for outputting the maximum value of the data c and d, a minimum value output circuit 914 for outputting the minimum value of the data a and b, a minimum value output circuit 915 for outputting the minimum value of the data c and d, a threshold value calculation circuit 902 for calculating a threshold value from the output data of the maximum value output circuits 912 and 913 and the minimum value output circuits 914 and 915, a binary coding circuit 920 for coding the block data to form binary codes on the basis of the threshold value output from the threshold value calculation circuit 902, a pattern table 922 for setting all combination patterns of previously prepared binary code data and interpolation directions thereof, a pattern table reference circuit 921 for determining the interpolation directions by referring the pattern table 922 and the binary code data, a minimum value output circuit 923 for calculating the minimum value MD1 of the output data of the maximum value output circuits 912 and 913, a maximum value output circuit 924 for calculating the maximum value MD2 of the output data of the minimum value output circuits 914 and 915, an interpolation reference data selecting circuit 925 for selecting necessary pixel data for calculating an interpolation pixel value depending on the output of the pattern table reference circuit 921, and an interpolation pixel value calculation circuit 903 for calculating the interpolation pixel value from the data selected by the interpolation reference data selecting circuit 925. The threshold value calculation circuit 902 includes a maximum value calculation circuit 916 for calculating the maximum value of the output data of the maximum value output circuits 912 and 913, that is the maximum value MX of the block data extracted by the block extracting circuit 911, a minimum value calculation circuit 917 for calculating the minimum value of the output data of the minimum value output circuits 914 and 915, that is, the minimum value MN of the block data extracted by the block extracting circuit 911, an adder 918 for adding the outputs of the maximum value calculation circuit 916 and the minimum value calculation circuit 917, and a 1/2 factor circuit 919 for multiplying 1/2 to the output of the adder 918. The interpolation pixel value calculation circuit 903 includes an adder 926 for adding the output data k and l of the interpolation reference data selecting circuit 925, and a 1/2 factor circuit 927 for multiplying 1/2 to the output of the adder 926 to output a result to an output terminal 904. Next, the operation of the pixel interpolation device described above will now be described. In this embodiment, for example, a case for interpolating an omitted pixel P shown in Fig. 25 will be described. First, the block extracting circuit 911 extracts peripheral 4 pixels a, b, c and d adjacent to the four sides of the omitted or interpolation pixel P. In the maximum value output circuits 912 and 913 and the minimum value output circuits 914 and 915, from the data of a, b, c and d, the maximum and minimum values such as MAX (a, b), MAX (c, d), MIN (a, b) and MIN (c, d) are calculated, and then in the maximum value calculation circuit 916 and the minimum value calculation circuit 917 of the threshold value calculation circuit 902, from the calculation data, the maximum value MX = MAX {MAX (a, b), MAX (c, d)} and the minimum value MN = MIN {MIN (a, b), MIN (c, d)} are calculated. Now, assuming that the luminance of the 4 pixels are a = 70, b = 80, c = 90 and d = 200, the maximum value MX is 200, and the minimum value MN is 70. Hence, the threshold value TH is calculated as follows. TH = (MX + MN)/2 = 135 On the basis of this threshold value TH, the data a, b, c and d are converted to binary code data e, f, g and h under the following conditions in the binary coding circuit 920 as follows. X' = "0" (X ≦ TH) = "1" (X > TH) {(X, X'): any of (a, e), (b, f), (c, g) and (d, h)} By this calculation, e, f, g and h are obtained as shown in Fig. 36, that is, e = 0, f = 0, g = 0 and h = 1. On the other hand, in the pattern table 922, as shown in Fig. 27, all combination patterns to be obtained by the binary coding and the directions of the interpolation reference pixels corresponding to the combination patterns are stored. The directions (central arrows in the horizontal and/or vertical directions in each pattern) of the interpolation reference pixels are determined by considering the directions of the edges of the image by the binary code patterns. Then, adequacy of the directions of the interpolation reference pixels will now be described in connection with Figs. 52a, 37b and 37c. Every pixel block of some images, the differential absolute value in the horizontal direction (the absolute value of the difference between the data of the pixels b and c in Fig. 25) and the differential absolute value in the vertical direction (the absolute value of the difference between the data of the pixels a and d in Fig. 25) are calculated and the obtained values are graphically drawn in the directions of the interpolation reference pixels to obtain Figs. 37a, 37b and 37c. That is, Fig. 37a is a graph of a pixel block in which the correlative direction of the interpolation reference pixels is the horizontal direction, and it is readily understood that in all data, the differential absolute value in the horizontal direction is smaller than the differential absolute value in the vertical direction, and all data is correlated with the same horizontal direction as the interpolation reference pixels. Fig. 37b is a graph of a pixel block in which the correlative direction of the interpolation reference pixels is the vertical direction, and it is readily understood that in all data, the differential absolute value in the vertical direction is smaller than the differential absolute value in the horizontal direction, and all data is correlated with the same vertical direction as the interpolation reference pixels. Fig. 37c is a graph of a pixel block in which the correlative direction of the interpolation reference pixels is not specific, and it is readily understood that the data are present near positions of y = x where the differential absolute value in the horizontal direction is equal to the differential absolute value in the vertical direction, and all data is not correlated with the horizontal nor vertical direction. As described above, the directions of the interpolation reference pixels, determined in the pattern table, are coincident with the correlative directions of the data of the pixel blocks, and the adequacy can be proved. In the pattern table reference circuit 921, the pattern table 922 and the binary code data e, f, g and hare referred to determine the direction or directions of the interpolation reference pixels. For example, the pattern shown in Fig. 36 is coincident with a pattern N shown in Fig. 27. Hence, the interpolation reference pixel direction is the horizontal direction, and the interpolation pixel value p is calculated as follows. p = (b + c)/2 Also, in case of a pattern shown in Fig. 38, it is coincided with a pattern D shown in Fig. 27. Thus, the interpolation reference pixel direction is the vertical direction, and the interpolation pixel value p is obtained as follows. p = (a + d)/2 Further, in case of a pattern shown in Fig. 39, in which the interpolation reference pixel direction is not specified, that is, a pattern C in Fig. 27 (there are arrows in both the horizontal and vertical directions in the center of the pattern). In this case, the interpolation pixel value p is calculated as follows. p = (MD1 + MD2)/2 Now, MD1 and MD2 are the data which are selected from the block data a, b, c and d and satisfy the respective conditions such as MX ≧ MD1 and MD2 ≧ MN. Also, in this case, MD1 and MD2 are obtained from the output data of the maximum value output circuits 912 and 913 and the minimum value output circuits 914 and 915 in the minimum value output circuit 923 and the maximum value output circuit 924, respectively. Hence, in the interpolation reference data selecting circuit 925, as the data of k and 1, the data b and c are output when the output of the pattern table reference circuit 921 is the horizontal direction, and the data a and d are output when the vertical direction is output from the pattern table reference circuit 921. Also, when the direction can not be specified in the pattern table reference circuit 921, both MD1 and MD2 are output. Thus the output data of k and l are calculated in the interpolation pixel value calculation circuit 903 as follows. (k + 1)/2 In Fig. 40, there is shown the embodiment 3-2 of a pixel interpolation device according to the present invention. having the same construction as the embodiment 3-1 shown in Fig. 35, except that the threshold value calculation circuit 902 includes an adder 928 for adding the block data a, b, c and d and a 1/4 factor circuit 929 for multiplying 1/4 to the addition result of the adder 928 to obtain the threshold value TH = (a + b + c + d)/4. In this embodiment, the circuit structure of the threshold value calculation circuit 902 can be simplified, and almost the same operation can be expected. In Fig. 41, there is shown an essential part of the embodiment 3-3 of a pixel interpolation device according to the present invention. As to the other part not shown in Fig. 41, the corresponding parts shown in Fig. 35 or Fig. 40 can be used if necessary. In the embodiments 3-1 and 3-2 shown in Figs. 35 and 40, as described above, the interpolation pixel value is obtained according to the pattern table shown in Fig. 27. The patterns shown in Fig. 27 can be classified into four groups. The first group includes patterns having one white circle and three black circles, as typically shown in Fig. 36. The second group includes patterns having three white circles and one black circle, as shown in Fig. 39. The third group includes patterns having two white circles and two black circles, as shown in Fig. 39. The fourth group includes a pattern having four black circles. The 4 pixel data constituting each pattern have four values such as the maximum value MX, the minimum value MN and two intermediate values MD1 and MD2, as described above. As shown in Fig. 27, relating to the first group of the patterns, an average value of two data of two pixel within three pixels excluding the white circle pixel having the maximum value MX, that is, two data of the three data MD1, MD2 and MN, is the interpolation pixel value. As to the second group of the pattern, on the contrary, an average value of two data of two pixel within three pixels excluding the black circle pixel having the minimum value MN, that is, two data of the three data MX, MD1 and MD2, is the interpolation pixel value. As regards the third and fourth groups of the patterns, the average value of MD1 and MD2 is the interpolation pixel value. That is, as described above, the probability for obtaining the interpolation pixel value of the patterns by using MD1 and MD2 except MX nor MN is quite high. Hence, in this embodiment, in order to reduce the circuit scale of the pixel interpolation device, the average value of MD1 and MD2 is used as the interpolation pixel value irrespective of the aforementioned patterns. As shown in Fig. 41, the pixel interpolation device is comprised of the block extracting circuit 911 for extracting the pixel block data a, b, c and d from the input image data input from the input terminal 901, the maximum value output circuits 912 and 913, the minimum value output circuits 914 and 915, the minimum value output circuit 923 to output MD1, the maximum value output circuit 924 to output MD2, the adder 926 for adding MD1 and MD2, and the 1/2 factor circuit 927 for multiplying 1/2 to the addition result MD1+MD2 of the adder 926 to output the average value (MD1 + MD2)/2 to the output terminal 904. The structures and functions of the above-described parts are the same as those of the embodiment 3-1 or 3-2 described above and thus the detailed description thereof can be omitted for brevity. In Fig. 42, there is shown the embodiment 3-4 of a pixel interpolation device according to the present invention. In this embodiment, the construction of the pixel interpolation device is further simplified compared with the embodiment 3-3 shown in Fig. 41. As shown in Fig. 42, the pixel interpolation device comprises the block extracting circuit 911 coupled with the input terminal 901, the maximum value output circuits 912 and 913 and the minimum value output circuit 923 to output MD1 from the output terminal 904. In this embodiment, MD1 is output as the interpolation pixel value. In this embodiment, as shown in Fig. 42, although the maximum value output circuits 912 and 913 and the minimum value output circuit 923 are used for outputting MD1, on the contrary, in place of these parts, by using the minimum value output circuits 914 and 915 and the maximum value output circuit 924, MD2 can be used as the interpolation pixel value. In this embodiment, by not using the average value of MD1 and MD2 as the interpolation pixel value but using either MD1 or MD2, the circuit scale can be further reduced, and the processing speed can be raised. Hence, this pixel interpolation device can be also used for a receiving processing in a so-called high vision TV receiver or the like. As described above, in the pixel interpolation device according to the present invention, by binary-coding the peripheral pixel block around the omitted pixel, the local change direction of the image is assumed, and depending on this result, the interpolation data are formed. The drop of the image quality is small, in particular, the image having the smoothed inclined border lines can be obtained. Further, in the pixel interpolation device according to the present invention, regardless of the changing direction of the image, the interpolation pixel value is obtained by using the data of the peripheral pixel block around the omitted pixel except the maximum and minimum values. Hence, nevertheless a little image quality drop, almost the same effects as the aforementioned pixel interpolation device can be obtained, and the pixel interpolation device with a small circuit scale and high processing speed can be obtained.

Claims: A pixel interpolation circuit for calculating an interpolation pixel value of a pixel to be interpolated from digital two-dimensional image date input thereto, the circuit comprising: extraction means (301,411,911) for extracting, from the input image data, reference pixel data of reference pixels around the pixel to be interpolated; threshold calculation means (303,402,902) for calculating a threshold value from the values of said reference pixels; coding means (304,416,920) for binary coding said reference pixel data based on said threshold value to represent the direction of change in pixel values of the reference pixels; discrimination means (305,418,921) for discriminating an interpolation direction based on the binary coded reference pixel data according to a prestored interpolation table relating possible sets of binary coded reference pixel data to particular interpolation directions; selection means (307,419,925) for selecting, from said reference pixels, a plurality of pixels in said interpolation direction; and data calculation means (308,418,903) for calculating the interpolation pixel value of the pixel to be interpolated from the pixel values of the selected plurality of pixels. A pixel interpolation circuit according to claim 1, wherein said reference pixels are the respective pixels from the horizontal lines above and below the pixel to be interpolated on the same vertical column of the image as said pixel to be interpolated, and the next but one pixels on either side of said respective pixels. A pixel interpolation circuit according to claim 1, wherein said extraction means comprises means (301) for extracting, from the input image data, pixel data of a plurality of pixels around the pixel to be interpolated and means (324) for selecting said reference pixel data therefrom. A pixel interpolation circuit according to claim 3, wherein said means (324) for selecting selects, as said reference pixels, from the horizontal lines above and below said pixel to be interpolated, either: the pixels on the same vertical column of the image as the pixel to be interpolated, and the next but one pixels on either side when the band of the input image data is low; or the pixels on the same vertical column of the image as said pixel to be interpolated, and the adjacent pixels on either side, when the band of the input image is high. A pixel interpolation circuit according to any one of the preceding claims, wherein the reference pixels are a plurality of pixels proximately located to the pixel to be interpolated. A pixel interpolation circuit according to claim 5, wherein the reference pixels include alternate pixels from the same horizontal line of the input image data. A pixel interpolation circuit according to claim 5 or 6, wherein the reference pixels are six pixels proximate to the input pixel. A pixel interpolation circuit according to any one of claims 5 to 7, wherein the interpolation direction is one of a vertical direction, a right slanted direction and a left slanted direction. A pixel interpolation circuit according to claim 5, wherein the reference pixels are the four pixels adjacent to the pixel to be interpolated, respectively above, below and either side of the pixel to be interpolated. A pixel interpolation circuit according to any one of the preceding claims, wherein the extraction means includes a delay circuit (301,411,911) for delaying the input image data to extract the pixel data required for interpolation. A pixel interpolation circuit according to any one of the preceding claims, wherein the binary coded reference pixel data are used as addresses by the discrimination means to access the interpolation direction from the prestored interpolation table. A pixel interpolation circuit according to any one of the preceding claims, wherein the selection means (307,419,925) is arranged to select two of the reference pixels and the data calculation means (308,418,903) is arranged to calculate the interpolation pixel value therefrom. A pixel interpolation circuit according to claim 12, wherein the data calculation means is arranged to calculate the interpolation pixel data by averaging the two reference pixels. A pixel interpolation circuit according to claim 13, when appendant to claim 10, wherein the selection means (925) is arranged to select one of (i) the two reference pixels above and below the pixel to be interpolated, (ii) the two pixels on either side of the pixel to be interpolated, or (iii) the two reference pixels which have neither the maximum nor minimum data value out of the four reference pixels. A pixel interpolation circuit according to any one of the preceding claims, wherein said threshold calculation means is arranged to calculate the threshold value by averaging a maximum pixel value and a minimum pixel value of reference pixels. A receiver of a transmission device which is operative to transmit quantized image data having an error correction code, the receiver including means for replacing uncorrected error data of received data with interpolation data obtained by a pixel interpolation circuit according to any one of the preceding claims. A pixel correction device for correcting error pixels of a CCD image sensor, the device comprising: means for quantizing image signals picked up by the CCD image sensor to obtain image data; and a pixel interpolation circuit according to any one of the preceding claims. A dropout correction device for correcting a dropout on reproducing by a video tape recorder, the device comprising: means for detecting the dropout; means for quantizing image signals reproduced by the video tape recorder to obtain image data; and a pixel interpolation circuit according to any one of preceding claims; and means for replacing dropout pixels with the interpolation data. A signal processing device comprising: means for converting a matrix sampled data group of two-dimensional image data to an offset sampled data group; memory means for storing the offset sampled data group; and a pixel interpolation device according to any one of the preceding claims for calculating interpolation values of the omitted pixels of the data read out of the memory means and interpolating the omitted pixel by the calculated interpolation value to restore the matrix sampled data group.

Inventors: BAMBA NORIKO, CHIBA KAZUHIRO, INAMURA MAMORU, NAGAYAMA TAKESHI, SOMEYA JUN, SUNADA NOBORU, WATABU KAZUYOSHI, YAMAMOTO YOSHIE, BAMBA, NORIKO, CHIBA, KAZUHIRO, INAMURA, MAMORU, NAGAYAMA, TAKESHI, SOMEYA, JUN, SUNADA, NOBORU, WATABU, KAZUYOSHI, YAMAMOTO, YOSHIE, Bamba, Noriko, c/o Mitsubishi Denki K. K., Chiba, Kazuhiro, c/o Mitsubishi Denki K. K., Inamura, Mamoru, c/o Mitsubishi Denki K. K., Nagayama, Takeshi, c/o Mitsubishi Denki K. K., Someya, Jun, c/o Mitsubishi Denki K. K., Sunada, Noboru, c/o Mitsubishi Denki Eng. K. K., Watabu, Kazuyoshi, c/o Mitsubishi Denki K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N5
IPC codes: G06T5, H04N5, H04N1, H04N9, G06T3