Control of saturation of integrated bipolar transistors

Abstract: Saturation of a bipolar power transistor is controlled by sensing the current which is eventually injected into the substrate of the integrated circuit by the saturating transistor and using this signal for exerting a limiting action on the current which is driven to the base of the power transistor by a dedicated driving circuit. Differently from the prior art antisaturation systems, it is no longer necessary to precisely monitor the operating voltages across the terminals of the bipolar power transistor. A suitable sensing resistance may be integrated conveniently at a distance from the often complex integrated structure of the bipolar transistor. The system of the invention offers numerous advantages and ensures intervention of the antisaturation circuit only when the power transistor has positively reached a state of saturation, but well before any unwanted consequence.

Description: The present invention relates to a technique for controlling saturation of integrated bipolar transistors, according to which the current injected into the substrate by a saturating transistor is used an information for exerting a limiting control of saturation. The saturation of an integrated bipolar transistor causes an injection of current into a substrate of the integrated circuit, that is commonly connected to ground. This effect of saturation, beside representing an undue power consumption, may also have other consequences, all highly undesirable. Of course the problem becomes severe in the case of power transistors, which are commonly driven through a base terminal by a driving circuit. The driving circuit may comprise an operational amplifier, to the inputs of which a control signal is fed. A representative application of this type of circuit is that of a so-called series voltage regulator. Fig. 1 depicts a functional diagram of this common circuit wherein, in the particular instance, the power transistor is a PNP transistor. The operational amplifier OP drives the base of the power transistor T1 in function of a control signal fed to its inputs, which in this specific instance represents a voltage difference between the regulated output voltage V L and a reference voltage V R . When the V L voltage is lower than V R , the OP amplifier increases the output current I B that, fed to the base of T1, forces the transistor to increase its collector current IL, thus determining a desired increase of the output voltage V L . Viceversa, when V L is greater than V R , a reduction of the base current I B and therefore of the collector current I L and of the output voltage V L is obtained. Of course there are physical limitations to the variation ranges within which such parameters may vary. In particular, by progressively reducing the input voltage I IN , a condition is reached eventually whereby the difference of potential (VCE) between the emitter and the collector of the power transistor T1, by dropping to few hundreds mV, brings the transistor to operate in a saturation region of its characteristic. Under these conditions of operation, the voltage regulator of Fig. 1, i.e. the bipolar transistor T1, ceases to provide a correct performance. In a regulator circuit as the one shown in Fig. 1, it becomes impossible to maintain an output voltage V L equal to the desired voltage V R , because to an increase of the base current I B of the power transistor T1 no longer corresponds an increase of collector current. The operational amplifier OP, in an attempt of maintaining V L equal to V R increases its output current up to the maximum level of its intrinsic regulating capabilities. This last effect has in turn other negative influences when the power transistor T1 is an integrated transistor. In this case, the transistor has a "fourth terminal", commonly referred to as the substrate terminal (schematically indicated with "S" in Fig. 1) which, for obvious reasons, should be kept at the lowest potential present in the integrated circuit (typically to ground potential). The negative effects caused by the saturation of an integrated power transistor T1 are essentially connected with the generation of a current I S through the substrate terminal, which is related to the base current I B by a gain factor. Therefore this current I S , which is injected in the substrate of the integrated circuit, is generally rather high, by considering that already the base current I B tends to be high under saturation conditions. A saturating transistor may even invert the sign of its own collector's current if any component connected thereto can sustain it. As a consequence the current I L may flow into the collector of the power transistor T1. The presence of an inductive load (L) is a typical situation wherein such a reversed collector's current may occur. In other circumstances, large capacitances are often connected in parallel to the load of a voltage regulator for obvious reasons. One reason may be the need of sustaining a certain current through the load also during brief power supply interruptions to the regulator circuit. Therefore, under the above noted conditions of saturation, these "storage" capacitors may deliver a current (-IL) to the collector of a saturating power transistor, thus unduly losing stored electrical charge and reducing the time of "self-sustainment" of the current through the load in case of a power supply interruption. The substrate current I S should be summed to the base current I B of the power transistor T1 for determining the sum of the emitter and collector currents, according to the relation: I S + I B = I IN - IL. As a consequence, a large value of the sum: I S + I B , determines a large "input" current I IN , as well as a high discharge current (-IL) of a load capacitance. Both these currents are highly undesirable because they may overload the current path, cause undue power dissipation and eventually a shortening of the maximum time of interruption of the power supply that the powered circuits may tolerate before losing their functional ability. Several devices are known for controlling saturation of an integrated bipolar transistor with the aim of relieving or preventing the above-noted consequences. The document JP-A-60153204, discloses in an anti-saturation circuit for an output bipolar transistor. The circuit makes the leaked current to flow through an auxiliary collector of the output transistor through a sensing resistor to the ground node of the integrated circuit. When the voltage on the sensing resistor overcomes the forward drop voltage of a diode, the leaked current flows through the diode and into a feedback transistor thus reducing the drive level of the output transistor to prevent saturation. The document G-A-2,179,218 describes an anti-saturation circuit for an integrated PNP transistor wherein the characteristic of intervention may be predefined according to a certain law. The circuit employs a control loop wherein a certain current, function of the input current is summed to the leakage current of the PNP transistor and eventually causes a comparator to switch causing the intervention of a circuit that decreases the drive current drawn from the base of the PNP transistor. An antisaturation circuit that is commonly used according to a known technique is schematically depicted in Fig. 2. The transistor T2, which is in an OFF condition during normal operation of the circuit, switches-ON when the voltage between the collector and the base of the power transistor T1 becomes equal to the voltage, which, when present between the emitter and the base of T2, is sufficiently high to switch-ON the latter. The current flowing through T2 is then used for reducing or switch-OFF the output current of the operational amplifier OP which drives the base of T2. In this manner the problems caused by an uncontrolled increase of such a driving current when the power transistor T1 enters saturation are contained. Basically, the principle on which the operation of these known antisaturation circuits rests is that a transistor may be defined to be working in saturation conditions when its collector/base junction is directly biased. The base/emitter junction of the antisaturation transistor T2 is connected in parallel to the collector/base junction of the power transistor and therefore the transistor T2 begins to conduct when such a collector/base junction of the saturating power transistors becomes directly biased. This well known solution, though producing a satisfactory control of saturation is not exempt of drawbacks. In view of the fact that the power transistor T1 generally carries relatively high currents, there may be voltage drops along the connection between its collector terminal and the output terminal (OUT). In order to avoid that such voltage drops may falsify the voltage "read" by the emitter of T2, this transistor must be physically located very close to the collector terminal of T1 (to minimize the length of the connection). This is not always easy to reallize in the case of an integrated power transistor because such a device has already a relatively complex system of connections. The structure of the base terminal of T1 may present similar problems of layout, even though of lesser entity, because the current I B is at least an order of magnitude lower than I L . In general, according to the prior art, a control of saturation is implemented by acting upon the cause of such a current, i.e. a directly biasing voltage (VBC) across the collector/base junction. However, it is also necessary to ensure that the current I S does not rise above a certain maximum value. For this reason, under critical working conditions and/or in presence of critical intrinsic physical parameters of a particular fabrication process, it is necessary to adjust the intervention threshold of T 2 with a certain safety margin and in many occasions the power transistor T1 may be in a condition which is not yet of true saturation when the antisaturation circuit intervenes. A not yet saturated T1 imposes a lower limit to the difference of potential (VCEmin), between emetter and collector thereof, which is higher than what would be ideally necessary for eliminating the negative effects of saturation of the power transistor, as noted above. An higher VCEmin voltage (as required by safety margin considerations) may have a remarkable importance, as in the case of a voltage regulator, because in turn it imposes a lower limit to the input voltage I IN during operation. In fact, it may be observed from Fig. 2, that VINmin = VCEmin + V R . In order to ensure the lowest VINmin as possible, it would be desirable that the equality: VCEmin = VCEsat be always verified, wherein VCEsat is the VCE of the power transistor T1 under mild (initial) saturation conditions, which would not yet cause the above-noted consequences. On the other hand, fast transients may occur while the V IN voltage is within a normal working range for which the antisaturation transistor T2 should not intervene. Such transients propagate to the base of the power transistor T1 because its VBE is approximately constant. From this point, through the parasitic capacitance that exists between the collector and the base of the antisaturation transistor T2, the transients reach the collector of T2, which is connected to a high sensitivity input node of the driving operational amplifier OP. As said above, such an input signal modulates the output current, i.e. I B , which in turn acts upon IL and eventually on V L . In conclusion, the presence of the antisaturation transistor T2, with its parasitic capacitances, worsens the overall performance of the circuit in presence of fast transients on the supply lines. In many applications this aspect becomes very important because of the consequences that may ensue therefrom. Object of the present invention is to provide a system for controlling the saturation of an integrated bipolar power transistor, which may be easily integrated independently of the layout of the power transistor and wherein the control on saturation is readily adjustable in order to intervene when a certain tolerable level of saturation is surpassed. It is a further object of the present invention to provide an improved voltage regulator circuit, having a low voltage drop and utilizing a bipolar power transistor as a series regulating element, driven by an operational amplifier, and provided with an improved circuit arrangement for controlling saturation of the power transistor used as series regulator. Basically, the antisaturation system of the present invention, differently from the known systems, does not monitor the occurrence of a direct biasing of the collector/base junction of the power transistor as an indication of a saturation condition of the transistor. Conversely, the system of the invention monitors a substrate current which is actually caused by the operation of the transistor in a saturation region of its characteristic. This is implemented by connecting a sensing resistance, generally of a small value, in the connection path between the substrate terminal of the power transistor and a ground node of the integrated circuit. The current which is eventually injected into the substrate by the power transistor when operating in a saturation condition, determines a certain voltage drop across the sensing resistance and this voltage is used as a signal confirming a certain saturation state. This voltage is compared with a reference voltage, for example by the use of an operational amplifier capable of generating an output current that is fed to an input of the driving circuit of the power transistor in order to exert a desired control on the saturation. According to the system of the invention, it is no longer necessary to "disturb" the geometry of an integrated power transistor because it is no longer necessary to detect, as done in the known circuits, an "internal" operating voltage of the integrated transistor. An information in the form of a substrate current is not altered by the length (resistance) of the connection path between the substrate of the transistor and a sensing resistance, which advantageously may be physically realized far away from the integrated structure of the power transistor. In practice, a corrective (limiting) action on saturation is effected by modifying the driving base current of the saturating power transistor, similarly to what is done in an antisaturation system of the prior art. By contrast, instead of monitoring the parameters or the parameter which causes saturation of the power transistor (i.e. its VBC), an effect of saturation, that is the current which is injected into the substrate, is monitored instead. In this way it is possible to limit very precisely the degree of saturation, by adjusting the triggering threshold of a comparator. The power transistor is permitted to reach a certain predetermined tolerable level of saturation, irrespectively of the working conditions and/or of the spread of electrical parameters typical of the particular large-scale fabrication process. In this manner, a very useful condition: VCEmin = VCEsat, wherein VCEsat can be extremely small, may be ensured because the operating conditions of the power transistor are corrected only when stricly necessary to avoid undesirable consequences. In the case of a typical application such as that of a series voltage regulator, transients which may occur in the input line V IN are not propagated to the inputs of the comparator which controls saturation, nor to the output node and therefore the antisaturation circuit of the invention does not modify in any way the behaviour of the voltage regulator in presence of transients. Fig. 1 is a functional diagram of a low-drop voltage regulator utilizing as regulating element a PNP power transistor, as described above. Fig. 2 is a basic circuit diagram of a low-drop series regulator according to Fig. 1, provided with a known antisaturation circuit, as described above. Fig. 3 is a basic diagram of a circuit for controlling saturation, made in accordance with the present invention; Fig. 4 is a more detailed embodiment of the circuit of Fig. 3. With reference to the basic diagram of Fig. 3, the circuit for controlling the saturation of the power transistor T1 is composed of a sensing resistance Rs, a differential amplifier OP1 and a source of a reference voltage V s . The current I S , which is injected into the substrate by the transistor T1 when it operates in a saturation region of its characteristic, determines a certain voltage drop across the sensing resistance R s , which is compared by the operational amplifier OP1 (comparator) with the reference voltage V S . When the voltage drop across Rs is greater than Vs, the amplifier OP1 generates an output current that is fed to an input of the operational amplifier OP. As a consequence, the OP that drives the power transistor T1 reduces the driving current I B and therefore the substrate current I S , which is injected into the substrate by the saturating transistor, is reduced. This current reduction process stops when the substrate current I S drops below a threshold value (Vs/Rs). An embodiment of an antisaturation circuit of the invention is depicted in Fig. 4. The emitter of the transistor T6 coincides with the inverting input (-) of the differential amplifier OP1. The emitter of the transistor T5 coincides with a negative pole of a reference voltage, while the non-inverting (+) input of the OP1 amplifier is functionally incorporated in the integrated structure of the pair of input transistors T5 and T6. The collector of the transistor T3 coincides with the output node of the amplifier OP1, which in the example shown is not connected to a dedicated control input of the driving amplifier OP but to an inverting input (-) thereof. In practice, the output signal that is produced by the amplifier OP1 does not exert a direct control on the output current I B of the driving amplifier OP, but has a substantially equivalent effect by modifying the reference voltage V R which is actually applied to the inverting input (-) of the driving amplifier OP. The resistance R3 serves exclusively for powering the amplifier OP1 by deriving a current from the output node of the voltage regulator. The operation of the antisaturation circuit composed of the amplifier OP1 and the voltage reference Vs of Fig. 4 is as follows. The current passing through the resistance R3 is injected into the emitter of the PNP transistor T4. This transistor splits the current in two portions (between its collectors C1 and C2). A first portion of this current enters the collector region of the transistor T5 and a second portion enters the collector region of the transistor T6. The transistors T5 and T6 have a common base and the emitter area of T6 is n times the emitter area of the transistor T5. In this way a voltage difference between the two emitters, given by: Vt*ln(n*Ic6/Ic5)where Vt = K*T/q, where K = Boltzmann's constant, T = absolute temperature, q = charge of the electron, Ic6 = current through T6, Ic5 = current through T5, is produced. If the two collectors C1 and C2 of the transistor T4 are made so as to divide the current into equal parts (Ic5 = Ic6), such a voltage difference becomes equal to Vt*ln(n). By assuming for example n = 3 and a temperature of 27°C, such a voltage difference will be about 30mV. This voltage represents substantially the reference voltage Vs of Fig. 3. In fact, if the voltage across Rs becomes greater than the above-determined threshold voltage, the current Ic5 becomes greater than Ic6 which by contrast is always equal to the current through the collector C1 of the transistor T4. The difference current between these two currents flows through R2 and the transistor T3 and through the resistance R1, which is connected in series with the voltage reference V R of the driving amplifier of the power transistor T1. This current by flowing through R1 determines a lowering of the reference voltage as seen by the voltage regulator, which consequently reduces the output voltage V R and therefore brings the power transistor T1 out of saturation. The resistance R2 has the purpose of placing an upper limit to the current flowing through the transistor T3. In fact, when the transistor T5 is at peak conduction and its collector's voltage reaches the voltage present on its emitter, the voltage drop across R2 becomes: Vbe T6 + Vbe T4 - Vbe T3 ≈ Vbe. As a consequence, the above-noted upper limit of the current flowing through the transistor T3 becomes: Vbe/R2.

Claims: A method for controlling saturation of a bipolar transistor integrated in a semi-conducting substrate of an integrated (T 1 ) circuit for limiting the current (I S ) that is injected into the substrate(s) by the saturating transistor (T 1 ), by controlling a driving current (I B ) fed to a base (B) of the integrated transistor (T 1 ) in function of a signal representative of the state of saturation of the transistor, which comprises sensing across a sensing resistance (R S ) through which said substrate current (I S ) flows a first signal representative of a saturation condition of said integrated transistor; comparing said first signal with a reference voltage (V S ); generating (OP1) a second amplified signal, replica of said first signal when said first signal becomes greater than a threshold established by said reference voltage (V S ); feeding said second amplified signal to a control terminal of a driving circuit (OP) for modifying said driving current (I B ). An antisaturation circuit for an integrated bipolar transistor (T 1 ) comprising a sensing resistance (R S ) functionnally connected between a substrate region(s) of said integrated transistor and a ground node of the integrated circuit; a comparator (OP1) having a first input functionally connected to said sensing resistance (R S ), a second input functionally connected to a reference voltage (V S ) and an output connected to a control terminal of a driving circuit (OP) of said integrated transistor (T 1 ); said comparator (OP1) producing an amplified signal in function of a signal present across said sensing resistance (R S ), through which a substrate current (I S ) generated by said integrated transistor (T 1 ) when operating in a saturation region of its characteristic, when the signal present across said sensing resistance (I S *R S ) becomes greater than said reference voltage (V S ). A voltage regulator circuit utilizing as a series regulator an integrated bipolar transistor (T 1 ) having an emitter (E) functionally connected to an input node (IN) and a collector (C) functionally connected to an output node (OUT) of the voltage regulator circuit, a base (B) connected to an output of an operational amplifier (OP) having a non-inverting input connected to said output node (OUT) of the circuit and an inverting input connected to a first reference voltage (V R ) and a substrate region (B) coupled to ground potential, characterized by comprising a sensing resistance (R S ) functionally connected between said substrate region(s) and a ground node of the integrated circuit; a comparator (OP1) having a first input connected to said sensing resistance (R S ), a second input connected to a second reference voltage (V S ) and an output connected to a control node of said operational amplifier (OP); said comparator (OP1) generating an amplified signal in function of a signal present across said sensing resistance (R S ) when it becomes greater than a threshold value established by said second reference voltage (V S ) and said amplified signal being applied to said control node of said operational amplifier (OP) for reducing a driving current (I B ) fed to the base (B) of said integrated transistor (T 1 ) for limiting saturation thereof.

Inventors: MORELLI MARCO, POLETTO VANNI, MORELLI, MARCO, POLETTO, VANNI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: G05F1
IPC codes: H01L29, G05F1, H01L21, H03K17