Video memory interface to control processor access to video memory

Abstract: A full screen of video data is stored in a video memory. A small block of video data to be imminently displayed on a raster scan display device is copied, two double-words (32 bits) at a time, from the video memory to a 6 by 32-bit first in, first out buffer (FIFO). A fill detection circuit determines when the fill level of the FIFO is at or above certain predetermined levels; specifically, 3, 5 and 6 double-words. The current operating mode is stored in a programmable mode register wherein each mode corresponds to a unique screen resolution. For example, one mode corresponds to a 1024 by 768 pixel resolution having 256 colors per pixel, while another mode corresponds to a 320 by 200 pixel resolution having 4 colors per pixel. A minimum fill level is selected by a level selection circuit depending on the current operating mode. Since the FIFO is emptied quickly in a high resolution mode, a higher minimum fill level is selected for high resolution modes than for low resolution modes. Processor access circuitry permits a central processor to write new video data to the video memory. The processor access circuitry, however, is disabled whenever the current fill level is below the minimum fill level set by the level selection circuit. Thus, central processor access to the video memory is only permitted when there is a minimum level of data in the FIFO, and that minimum level of data is selected according to the current operating mode.

Description: This invention pertains to computer video graphics systems and, more particularly, to a video graphics system in which processor access to a video memory is dependent upon the current fill level of a FIFO refresh buffer. To display video data on a raster scan display device, such as a cathode ray tube (CRT) display, a typical video system includes a dedicated video memory for storing a full screen of video data. The video data to be displayed is transferred from the computer's central processor to the video memory. A CRT controller (CRTC) generates the appropriate horizontal and vertical sync pulses and associated timing signals and, at the appropriate time, a bit, byte or block of video data is read from the video memory, processed, and displayed on the screen. Unless dual ported video memory (VRAM) is used, the central processor can not access the video memory at the same time that the bit, byte or block of data is read from the video memory to "refresh" the screen. Consequently, a video memory read operation for purposes of screen refresh usually has priority over a central processor write operation to the video memory. If this were not the case, display data would momentarily disappear from the screen during periods of processor video memory access. Therefore, processor access to the video memory is usually limited to periods of horizontal and vertical blanking. As the resolution of video systems increases, both in terms of pixels per screen and colors per pixel, the total number of bits or bytes per screen increases dramatically, along with the time required for the processor to re-write one screen of data into the video memory. Consequently, if processor access to the video memory is limited only to periods of horizontal and vertical blanking, eventually a point is reached at which the processor can not re-write the video memory fast enough to keep up with images that are constantly changing. One way to help overcome this problem is to buffer the refresh output of the video memory with, for example, a first in, first out buffer (FIFO). with a buffer at the refresh output of the video memory, a block of video data can be rapidly copies from the video memory to the buffer. Data stored in the buffer is then used to refresh the screen, however, until the buffer is emptied to a predetermined level, the processor can write new video data into the video memory, even during non-blanking periods. Examples of FIFO buffering systems are disclosed in US Patent 4,845,661 and EP-A-0 391 584. There are a number of video or "graphics" standards available today. For example, a low resolution standard or "mode" may display only 320 by 200 pixels, with each pixel being one of four colors. In a high resolution mode, 1024 by 768 pixels may be displayed with each pixel being one of 256 colors. In accordance with the present invention, there is now provided a video memory interface capable of operating in any one of at least first and second resolution modes, the interface comprising: a first in, first out buffer ("FIFO") having an input coupled to a video memory port; fill level detection means, coupled to said FIFO, for detecting at least two fill levels of said FIFO; processor access means, coupled between a processor access port and said video memory port, for coupling address and video data at said processor access port to said video memory port; and means for disabling said processor access means when the current fill level of said FIFO is below a minimum fill level; characterised in that the interface comprises: a programmable mode register for storing a code indicative of a selected one of the first and second resolution modes; and fill level selection means, coupled between the fill level detection means and the mode register, for selecting a first minimum fill level when the mode register is programmed to indicate the first resolution mode, and for selecting a second minimum fill level when the mode register is programmed to indicate the second resolution mode. Brief Description of the Drawings Fig 1 is a block diagram of a computer including the video graphics system of the present invention. Fig. 2 is a block diagram of the video memory interface unit. Fig. 3 is a schematic diagram of the fill level selection circuitry. Fig. 4 is a state diagram illustrating the operation and construction of the memory cycle arbiter. A block diagram of a computer 100 including the video system 101 of the present invention is illustrated in Fig. 1. Referring to this figure, a central processor unit (CPU) 102 is coupled to a memory bus 103 and an input/output (I/O) bus 104. Although memory bus 103 and I/O bus 104 are illustrated as separate buses, they could be joined as one single bus. A semiconductor memory 105 is coupled to the memory bus 103 and a plurality of I/O devices 106-109 are coupled to the I/O bus 104; specifically, a keyboard 106, a pointing device such as a mouse or trackball 107, a hard disk drive 108, and a floppy disk drive 109. A power supply 110 supplies power to the computer. The video system 101 is coupled to the I/O bus 104 and includes a cathode ray tube controller (CRTC) 111 of conventional design. CRTC 111 generates the horizontal and vertical sync pulses and other timing signals necessary to display video information on a raster scan display screen, such as a cathode ray tube (CRT). A memory interface 112 is described in more detail with reference to Fig. 2. A video memory 113 is coupled to the memory interface unit 112. Video memory 112 includes a plurality of dynamic random access memories (DRAMS) of conventional design. The output of the memory interface unit 112 is coupled to a serializer 114 and digital-to-analog converter (DAC) 115, both of conventional design. The serializer 114 converts the parallel output of the memory interface unit 112 into serial form, and the DAC 115 converts the serialized digital video information into analog voltages that represent the red, green and blue colors. A conventional raster scan display device 116, such as a CRT display, is used to display the video information. A detailed diagram of the video interface unit 112 is illustrated in Fig. 2. Referring to this figure, a conventional 6 by 32 bit first in, first out buffer (FIFO) temporarily stores up to 6 "double words" of video data, which are transferred to the serializer, one double word at a time. The convention used throughout this specification is that a byte = 8 bits, a word = 2 bytes, and a double word (DWord) = 2 words. Consequently, a double word = 4 bytes or 32 bits. The video data is copied from the video memory 113 to the FIFO 201, one double word at a time. A conventional Fill Level Detect Circuit 202 is coupled to the FIFO 201. The FIFO Fill Status output of Fill Level Detect Circuit 202 has three individual outputs to indicate when the minimum fill level of FIFO 201 is 3 DWords, 5 DWords and 6 Dwords. The operating mode of the Video system 101 is loaded into Mode Register 203 from the computer's data bus. The Mode Register 203 is accessed at a unique address on the bus, as decoded by Address Decode Circuit 204. The Video System is capable of operating in a plurality of screen resolution modes, from a high resolution mode of 1024 by 768 pixels with 256 colors per pixel, to a low resolution mode of 320 by 200 pixels with only 4 colors per pixel. The Mode Register 203 includes 5 programmable bits. A first bit indicates the alpha-numeric mode, a second bit indicates that there are 8 bits per pixel, and the third, fourth and fifth bits are used to set the clock frequency and are referred to as Clock Select Bits 0, 1 and 2 (CS0, CS1 and CS2). In particular, the clock frequency is set according to the following table: CS2 CS1 CS0 Frequency 0 0 0 25 MHz 0 0 1 28 MHz 0 1 0 <= 28 MHz 0 1 1 45 MHz 1 0 0 42 MHz A Fill Level Select Circuit 205 selects the minimum FIFO fill level that is required to permit the CPU 102 to access the Video Memory 113. This selection of the minimum fill level is based on the current operating mode of the Video System, as programmed in the Mode Register 203. In general, a high minimum fill level (e.g., 6 DWords) is required for high resolution modes, while only a low minimum fill level (e.g., 3 DWords) is necessary for low resolution modes. When the actual fill level of the FIFO is at or above the minimum fill level, as selected by the Fill Level Select Circuit 205, the Fill Level OK output of the Select Circuit goes active. The Fill Level Circuit 205 is described in more detail with reference to Fig. 3. The following table lists the minimum fill levels as a function of operating mode: Mode Type Bits/Pixel Pixel Rate Minimum Fill Level Alpha-Num N/A <= 28 MHz 3 DWords Alpha-Num N/A > 28 MHz 5 DWords Graphics <= 4 <= 28 MHz 3 DWords Graphics 8 <= 28 MHz 5 DWords Graphics <= 4 > 28 MHz 5 DWords Graphics 8 > 28 MHz 6 DWords A Memory Cycle Arbiter 206 controls access to the Video Memory 113 by shifting control of the Video Memory between the CRTC 111 and the CPU 102 at the appropriate time. The Memory Cycle Arbiter implements the state machine of Fig. 4 and it is of conventional arbiter design. Control of the address lines to the Video Memory 113 is provided by a conventional multiplexer, MUX 207, which is controlled by the CRTC/CPU-NOT output from the Memory Cycle Arbiter 206. When this line is active, the CRTC 111 addresses the Video Memory 113 via the CRTC port "C" and the Video Memory Port "V." When the CRTC/CPU-NOT output is not active, the CPU 102 addresses the Video Memory through the Central Processor Port "P". Thus, the Memory Cycle Arbiter 206 provides a means for enabling and disabling CPU access to the Video Memory 113 depending on the actual level of the FIFO relative to the minimum fill level selected by the Fill Level Select Circuit 205. In addition, when the CRTC/CPU-NOT line is inactive, the Memory Cycle Arbiter generates, in a conventional fashion, the CPU Write Enable and CPU Read Strobe signals necessary to write CPU data to Buffer 208 and read data from Latch 209, respectively. Thus, the MUX 207, the Buffer 208 and the Latch 209 provide a processor access means for coupling address and video data at the Processor Port "P" to the Video Memory Port "V." The Memory Cycle Arbiter also generates, in a conventional fashion, an Execute Memory Cycle (EMC) command, which signals the Memory Cycle Generator to generate another cycle of Video Memory Control signals, such as the Row Address Select, Column Address Select, and Write Enable signals necessary to access the Video Memory 113. Memory Cycle Generator 210 is of conventional design and it responds with an Acknowledge (ACK) signal back to the Memory Cycle Arbiter 206 when it has completed the requested memory cycle. A schematic diagram of the Fill Level Select Circuit 205 is illustrated in Fig. 3. Referring to this figure, the Fill Level Select Circuit includes AND gates 301-304, OR gates 305-306, NAND gate 307 and NOR gate 308. The Fill Level Select Circuit selects a minimum fill level for processor video memory access based on the current state of the five bits in the Mode Register 203. The output of OR gate 305 is the Fill Level OK signal that indicates that the current FIFO fill level, as sensed by the Fill Level Detect Circuit 202, is at or above the minimum level selected by the Fill Level Select Circuit 205. Fig. 4 is a state diagram of the Memory Cycle Arbiter 206. Referring to this figure in conjunction with Fig. 2, the Arbiter has three states and moves between states in response to changes in the FIFO and the current need for the CPU to access the video memory. The first state is an idle state in which the Arbiter waits until the FIFO is not completely full, or the CPU needs to access the video memory. In the second state, the CRTC has access to the Video Memory 113 and transfers video data to the FIFO until the FIFO is full, or the CPU needs access to the Video Memory and the Fill Level is OK. In state 3, the CPU has access to the Video Memory.

Claims: A video memory interface (112) capable of operating in any one of at least first and second resolution modes, the interface comprising: a first in, first out buffer, "FIFO", (201) having an input coupled to a video memory port; fill level detection means (202), coupled to said FIFO, (201), for detecting at least two fill levels of said FIFO; processor access means (207), coupled between a processor access port and said video memory port, for coupling address and video data at said processor access port to said video memory port; and means for disabling said processor access means (207) when the current fill level of said FIFO is below a minimum fill level; a programmable mode register (203) for storing a code indicative of a selected one of the first and second resolution modes; and fill level selection means (205), coupled between the fill level detection means (202) and the mode register (203), for selecting a first minimum fill level when the mode register (203) is programmed to indicate the first resolution mode, and for selecting a second minimum fill level when the mode register (203) is programmed to indicate the second resolution mode. The video memory interface (112) of claim 1, further comprising an arbiter (206) having first, second and third states, wherein no access to said video port is provided in said first state, video information is loaded from said video port to said FIFO (201) in said second state, and video information is transferred from said processor port to said video port in said third state. A computer, comprising: a video memory interface (112) as claimed in claim 1 or claim 2; at least one processor unit (102) coupled to the video memory interface; memory (105) coupled to said processor unit via a memory bus; a plurality of input/output, "I/O", devices (106-109) coupled to said processor unit via an I/O bus; and a power supply for supplying power to said computer.

Inventors: THOMPSON STEPHEN PATRICK, THOMPSON, STEPHEN PATRICK
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1992
Main classification: G09G1
IPC codes: G06F3, G09G1, G06F5, G09G5