Digital transmission test system

Abstract: Disclosed is a digital transmission test signal generating circuit for generating a digital test signal applied to a digital signal transmission system having encoding means (4), a transmission path (5), decoding means (7) and a display (9) supplied with the output of the decoding means (7). The digital transmission test signal generating circuit comprises generating means and timing means. The generating means generates repeatedly specific data with a predetermined bit pattern. The timing means controls the generating means in such a manner that the data will occur in the duration corresponding to a predetermined area of the display (9). The specific data generated constitute the worst-case state for the target transmission system to operate in. This provides easy, visual checks on the system to see on a monitor if it functions normally given the worst-case signals to work with. No specialized measuring instruments are required for the checks.

Description: BACKGROUND OF THE INVENTION: Field of the Invention: The present invention relates to a digital transmission test system suitable for checking digital signal transmission systems. Description of the Prior Art: In EP 0 138 613 A2 is described a method and apparatus for monitoring suitability of a transmission path for transmission of digital data by transmitting a test signal over the transmission path. The test signal is composed of a succession of video signal lines each including a horizontal sync pulse and a pattern of digital 1's and 0's at a predetermined frequency and occurring on each line at the same data position relative to the horizontal sync pulse. The patterns comprise a reference pattern of alternating 1's and 0's and test pattern of 1's and 0's at random or in a sequence known to be disruptive to the transmission path. The test signal is received and is displayed on a waveform monitor with the reference pattern and the test pattern interleaved with the complement of the reference pattern and complement of the test pattern, so that the four patterns are superimposed and enclose a generally eye-shaped area. Furthermore DE 36 01 605 A discloses a digital transmission test signal generating circuit, wherein a quasi-statistic bit pattern is used as a digital test signal to be transmitted during the lines 25 to 312 and 338 to 625 of first and second fields and displayed at the decoder output in the form of quasi-statistic colour pattern on a TV monitor screen. The SMPTE (Society of Motion Picture and Television Engineers, Inc.) of the United States is expected to adopt a scrambled NRZI (no-return-to-zero inverted code) method as its standard method for interfacing digital video/audio data primarily on an intra-office basis. This method involves having a transmitting side scramble 10-bit input data by performing a modulo-2 division thereon using a polynomial: G(x) = (x + s1) (x 9 + x 4 + 1) and having a receiving side descramble the data by performing a module-2 multiplication thereon using the same polynomial. One disadvantage of this method is that its automatic gain control (AGC) circuit for automatic compensation of cable-induced deterioration can malfunction due to the presence of DC components generated upon input of a specific combination of video/audio data. For example, suppose that 10-bit hexadecimal data "300" and "198" are supplied alternately, as shown in Fig. 5 (A). In this case, DC components are generated in the scrambled data. This is the worst state for the AGC circuit to operate in, as depicted in Fig. 5 (B). Another disadvantage of the above method is that a specific combination of input data may suppress for an extended period of time the signal transition (i.e., from "1" to "0" or from "0" to "1") that would normally occur at substantially constant intervals. For example, suppose that 10-bit hexadecimal data "110" and "200" are supplied alternately, as shown in Fig. 6 (A). In that case, signal transition only occurs every 20 clock pulses in the scrambled data. This is the worst state for the phase-locked loop (PLL) circuit to operate in for clock reproduction, as illustrated in Fig. 6 (B). Statistically, the worst-case states described above almost never occur during ordinary signal transmissions. But there is no absolute guarantee that they will be completely eliminated. In addition to the above cases discussed by the SMPTE, there also exist worst-state signals for the digital signal transmission system to operate with if the scrambling method remains the same regardless of the contents of the signals transmitted. Since the incidence of such worst-case signals is not appreciably high, it has been conventionally difficult to check digital signal transmission systems (i.e., newly manufactured or readjusted equipment) for their performance with worst-case signals while such systems are allowed to operate under ordinary operating conditions. SUMMARY OF THE INVENTION: It is therefore an object of the present invention to provide a digital transmission test system that generates test signals by which to check digital signal transmission systems easily for performance. According to the invention a digital video transmission test system is provided including encoding means for encoding digital data, a transmission path for transmitting the encoded data, decoding means for recovering digital data from the transmitted data, a display for displaying the recovered data and a test signal generating circuit for generating and supplying a digital test signal to the encoding means, characterized in that said display is a monitor TV set and the test system further includes processing means for processing the transmitted data by means of controlling at least one signal parameter of the transmitted data and timing means for controlling said generating circuit in such a manner that said data will occur in the duration corresponding to a first predetermined area of said display, and in that the digital test signal is formed by a repeated first bit pattern which is with the respect to the controlled signal parameter the worst case of possible bit pattern forming digital data to be transmitted. If the transmission system functions normally, the data having passed therethrough cause an image with particular brightness and color to be displayed in particular areas of the screen. If the transmission system fails to function normally, the data acquire an error during passage therethrough and produce changes in the image displayed in those particular areas of the screen. This makes it possible to check the target transmission system for performance with the worst-case data in an easy, visual manner without recourse to special measuring instruments. Further objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a block diagram of a digital transmission test system embodying the invention; Fig. 2 is a view showing what a monitor screen illustratively displays when an AGC part and a PLL circuit of a target system function normally; Fig. 3 is a view depicting what the monitor screen illustratively displays when the AGC part and the PLL circuit of the target system fail to function normally; Fig. 4 is a view indicating what the monitor screen illustratively displays when the PLL circuit fails to function normally; Fig. 5 (Figs. 5A and 5B) is a set of views depicting typical worst-case data for AGC operation during data transmission under the scrambled NRZI method; and Fig. 6 (Figs. 6A and 6B) is a set of views showing typical worst-case data for clock signal reproduction under the scrambled NRZI method. DESCRIPTION OF THE PREFERRED EMBODIMENT: A preferred embodiment of the invention will now be described with reference to Fig. 1. The embodiment constitutes a circuit arrangement for checking a transmission system that transmits digital video data under the scrambled NRZI method. In Fig. 1, digital video data DTV fed to a terminal 1 are forwarded to the "a" side fixed terminal of a changeover switch 2. The "b" side fixed terminal of the changeover switch 2 is supplied with a test signal DTE from a test signal generating circuit 3. The test signal DTE comprises two combinations of alternately repeated 10-bit hexadecimal data. One data combination is made of "300" and "198" continuing alternately for display on the upper part of the screen, and the other combination is constituted by "110" and "200" continuing alternately for display on the lower part of the screen. The output data from the changeover switch 2 are fed to a scrambler 4. The scrambler 4 scrambles the data by performing a modulo-2 division thereon using the polynomial: G(x) = (x + 1)(x 9 + x 4 + 1) After being scrambled by the scrambler 4, the data are forwarded over a transmission path 5 to a circuit 6 comprising an AGC part and a equalizer part. The AGC part controls gain in such a way that keeps the level of the transmitted data constant. The equalizer part corrects the high and low frequency characteristics that were deteriorated during transmission, whereby the inter-symbol interference involved is suppressed. The output data from the circuit 6 are supplied to both a descrambler 7 and a PLL circuit 8. The PLL circuit 8 reproduces the clock signal that is sent to the descrambler 7. The descrambler 7 descrambles the received data by performing a module-2 multiplication thereon using the above polynomial. The descrambling takes place in synchronism with the clock signal CLK. After being descrambled by the descrambler 7, the data are supplied to a monitor TV set 9. In operation, the changeover switch 2 is first placed in the "a" position. This causes the scrambler 4 to scramble the digital video data DTV. The scrambled data are sent over the transmission path 5 and through the circuit 6 to the descrambler 7. In turn, the descrambler 7 outputs the descrambled digital video data DTV to the monitor TV set 9. The screen of the monitor TV set 9 displays the image produced by the received digital video data DTV. When the changeover switch 2 is placed in the "b" position, the scrambler 4 scrambles the test signal DTE. As described, the test signal DTE corresponding to the upper part of the screen is the combination of hexadecimal 10-bit data "300" and "198" continuing alternately. Thus the scrambled data develop a DC component (see Fig. 5 (B)), which constitutes the worst state for the AGC part of the circuit 6 to operate in. This is because the DC component can cause the AGC part to deviate from its normal judging operation. On the other hand, the test signal DTE corresponding to the lower part of the screen is the above-mentioned combination of hexadecimal 10-bit data "110" and "200" continuing alternately. Thus the scrambled data cause one signal transition to occur only every 20 clock pulses (see Fig. 6 (B)). This is the worst state for the PLL circuit 8 to reproduce clock pulses in. The output data from the scrambler 4 are sent over the transmission path 5 and through the circuit 6 to the descrambler 7. If the AGC part of the circuit 6 functions normally, the data output by the descrambler with respect to the upper area of the screen are hexadecimal 10-bit data "300" and "198" alternated continuously. This causes an image IMa with predetermined brightness and color to be displayed in the upper area of the screen on the monitor TV set 9 (see Fig. 2). If the PLL circuit 8 functions normally, the data output by the descrambler 7 with respect to the lower area of the screen are hexadecimal 10-bit data "110" and "200" alternated continuously. This causes the lower area of the screen of the monitor TV set 9 to display an image IMb with levels of brightness and color different from those of the image IMa (see Fig. 2). If, on the other hand, the AGC part of the circuit 6 fails to function normally, the data output by the descrambler 7 with respect to the upper area of the screen develop an error that keeps the hexadecimal 10-bit data "300" and "198" from continuing alternately. This causes an image IMa' having drop-out noise NS to be displayed in the upper area of the screen of the monitor TV set 9 (see Fig. 3). If the PLL circuit 8 fails to function normally, the resulting bit slip generates an error in the data output by the descrambler 7 with respect to the lower area of the screen. That error prevents the hexadecimal 10-bit data "110" and "200" from continuing alternately. As a result, the lower area of the screen of the monitor TV set 9 displays an image IMb' having drop-out noise NS (see Fig. 4). As described, the test signal DTE generated by the test signal generating circuit 3 with respect to the upper area of the screen constitutes the hexadecimal 10-bit data "300" and "198" alternated continuously. When scrambled, these data make up the worst-state signal for the AGC part of the circuit 6 to operate with. The test signal DTE generated by the test signal generating circuit 3 with respect to the lower area of the screen constitutes the hexadecimal 10-bit data "110" and "200" alternated continuously. After being scrambled, these data form the worststate signal with which the PLL circuit 8 reproduces clock pulses. When the AGC part of the circuit 6 fails to function normally in the worst state entered by placing the changeover switch 2 in the "b" position, the image IMa' having drop-out noise NS is displayed in the upper area of the screen of the monitor TV set 9 (Fig. 3). When the PLL circuit 8 fails to function normally in the worst state prepared therefor, the image IMb' having drop-out noise NS appears in the lower area of the screen of the monitor TV set 9 (Fig. 4). Thus the above embodiment permits easy, visual checks on the AGC part of the circuit 6 and on the PLL circuit 8 to see if they function normally in their respective worst states. No specialized measuring instruments are needed for the checks. With these circuits found to operate normally, the scrambled NRZI method for extensive spectrum generation may be used for binary data transmission. This makes it possible to manufacture necessary hardware with relative ease and at reduced costs. Although the above embodiment is constructed to check transmission systems that transmit data under the scrambled NRZI method, other embodiments of the invention may be devised to generate similar signals with which to check other transmission systems that transmit data under other methods. In such cases, the test signal is the worststate signal for each circuit of a given transmission system to operate with. The worst-case signal is generated repeatedly with respect to specific areas of the screen. The above embodiment has divided the screen into two areas in which the AGC part of the circuit 6 and the PLL circuit 8 are checked for their operation. Alternatively, the screen may be used as a single area or may be divided into three or more areas for checks on as many test items. As many test signals DTE as the number of the areas allocated on the screen may be generated to check the multiple items concurrently and efficiently. As described and according to the invention, specific data are generated to constitute the worst-case state for the target transmission system to operate in. This provides easy, visual checks on the system to see on a monitor if it functions normally given the worst-case signals to work with. No specialized measuring instruments are required for the checks. Where a number of data repeat operations are involved, as in PCM transmissions, the economic benefits made available with the invention applied to the whole measuring setup in question are considerable. While a preferred embodiment of the invention has been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the scope of the following claims.

Claims: A digital video transmission test system including encoding means (4) for encoding digital data, a transmission path (5) for transmitting the encoded data, decoding means (7) for recovering digital data from the transmitted data, a display (9) for displaying the recovered data and a test signal generating circuit (3) for generating and supplying a digital test signal to the encoding means, characterized in that said display (9) is a monitor TV set and the test system further includes processing means (6, 8) for processing the transmitted data by means of controlling at least one signal parameter of the transmitted data and timing means for controlling said generating circuit (3) in such a manner that said data will occur in the duration corresponding to a first predetermined area of said display (9), and in that the digital test signal is formed by a repeated first bit pattern which is with the respect to the controlled signal parameter the worst case of possible bit patterns forming digital data to be transmitted. A digital video transmission test system according to claim 1, wherein said processing means (6, 8) includes gain control means (6) and/or a phase locked loop (8), said gain control means (6) controlling the level of the signal supplied to said decoding means, said phase locked loop (8) reproducing a clock signal, said digital test signal including first and/or second repeated bit patterns, said first repeated bit patterns being the worst case for said gain control means and occuring in the duration corresponding to an upper half area of said display and/or said second repeated bit patterns being the worst case for said phase locked loop (8) and occuring in the duration corresponding to a lower half area of said display (9). A digital video transmission test system according to claim 1, wherein said encoding means includes scrambling means (4) for scrambling input data and said decoding means includes descrambling means (7) for descrambling received data. A digital video transmission test system according to claim 2 characterized in that the repeated first pattern causes a first predetemined image to appear at a first predetermined area on the display if a first predetermined component within the digital video signal transmission system operates normally in processing the first predetermined repeated bit pattern and another, different second predetermined image to appear on the display if the first predetermined component operates abnormally in processing the first predetermined repeated bit pattern.

Inventors: EGUCHI TAKEO, EGUCHI, TAKEO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H04N17
IPC codes: H04N17, H04L25, H04L9