Data processing method and apparatus

Abstract: A plurality of physical registers greater (105) in number than can be addressed by instructions are provided. The physical registers are divided into a plurality of partial groups or windows. Each of the physical registers is specified by a physical register number determined by a combination of the number of the window and a register number contained in the window. The window number is indicated by a current floating point window pointer stored in a current floating point window pointer register (110, 113). In executing a vector calculation program having repetitive loops of an instruction sequence, the window is changed for each loop by changing the value of the current floating point window pointer. Vector data to be calculated at the i-th loop is read from a main memory (30) at the loop before the i-th loop. The calculated result of the vector data at the i-th loop is stored in the main memory at the loop after the i-th loop, thereby eliminating performance degradation to be caused by a slow data read time and improving the operation speed.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a data processing method and apparatus and more particularly to a technique whereby the data processor can access a greater number of registers than can be addressed by instructions. Specifically this invention relates to vector processing method and apparatus which practically prevents performance degradation caused by data transfer from the main memory during a so-called vector processing that processes a great deal of data continuously for which a cache is not so effective. DESCRIPTION OF THE RELATED ART A conventional technique that permits the data processor to access the greater number of registers than can be addressed by instructions is cited in the Japanese Patent Laid-Open JP-A- 166649/1982. According to this method, a group of hardware registers greater in number than the general registers that can be addressed by programs are provided. When there are two or more load instructions for the same general register from different main memory addresses, the load instructions are retained in these hardware registers. When the number of general registers addressable by the program is 16, 16 hardware registers are provided for each general register. In other words, 256 hardware registers are prepared in total. A general register 0 , for instance, is assigned hardware registers 0 to 15 . When 16 load instructions specifying different main memory addresses are executed for the general register 0 , the data of the 16 load instructions are held in the hardware register 0 to hardware register 15 . A memory architecture is provided to register the main memory addresses of the load instructions that were executed in the past and the hardware register numbers in which the loaded data were stored. When the main memory address of a load instruction issued by the program matches the main memory address registered in the memory, the program reads data from the corresponding hardware register, instead of from the main memory. This method reduces the number of times that the main memory is accessed and prevents performance degradation due to reference register conflicts between instructions. One of the conventional techniques that allow the data processor to access a greater number of registers than can be addressed by instructions is described in a book "Computer Architecture: A Quantitative Approach", at pp. 450 - 454, by J.L. Hennessy and D.A. Patterson, published by Morgan Kaufmann Publishers, Inc. (1990). According to this method, a larger number of registers called "physical registers" than can be addressed by programs are provided and divided into a plurality of parts called windows. That is, each window consists of a plurality of physical registers. For example, let us assume that the program numbers the registers as 1 to n and that there are n*m physical registers, numbered from 1 to n*m . If m windows are provided, numbered from 1 to m, a window 1 may be assigned physical registers 1 to n and a window 2 physical registers n+1 to 2n . It is general practice to provide physical registers common for all windows or those common for adjacent windows. For simplicity, however, the above example is described. Each window has registers used by one program. In other words, referencing registers that can be addressed by a program actually means referencing physical registers belonging to a certain window. In the preceding example, if a certain program is assigned a window 2 and the program specifies a register k , the physical register to be referenced is n+k . This window is used in the following manner. Suppose that a certain program is assigned a window j . When that program calls other program, the called program is assigned a window j+1 . If a certain program is allocated with a window j and the control returns from that program to the original program, the latter program to which the control has returned is assigned a window j-1 . Using the registers in this way offers the following advantages. In a system that has only the number of registers that can be addressed by programs, data stored in the registers must be stored in the main memory each time a call for a program occurs, in order to save information present at time of the call. Further, each time the control returns to the calling program, the data saved in the main memory must be written into the register again to resume the execution of the program. In the system having the above-mentioned window architecture, programs assigned different windows reference different physical registers, so that it is not necessary to save data from register to the main memory and rewrite the data again from the main memory to the register, making the process faster. However, in a system with the above window structure, a control is needed whereby when a program call is made by a program with the maximum window number, a window overflow interrupt occurs and when a program return is initiated from a program with the minimum window number, a window underflow interrupt is produced. Scientific and engineering computations are mostly the vector calculation shown below. C(i) = A(i) + B(i), i = 1, ..., N where A, B, C are vectors with the element number N . Among important calculations in scientific and engineering computations is a list vector calculation, which is expressed in the following equations and mainly used for a sparse matrix calculation. A(i) = B(Li(i)), i = 1, N A(Li(i)) = B(i), i = 1, N A(Li(i)) = A(Li(i))@B(i), i = 1, N where Li is called a list vector. Equation (2) is a source index type calculation, and A and Li are vectors with an element number N , equation (3) is a target index type calculation, and B and Li are vectors with an element number N , and equation (4) is a particle pusher type calculation, and B and Li are vectors with an element number N . In equation (3), @ represents calculation such as addition, subtraction, multiplication and division. As can be seen from equation (2), the source index type calculation stores into an i-th element of the vector A an element of the vector B whose element number is an i-th element of the list vector. The equation (3) indicates that the target index type calculation stores an i-th element of the vector B into an element of the vector A whose element number is an i-th element of the list vector. The equation (4) indicates that the particle pusher calculation performs operation on an element of the vector A whose element number is an i-th element of the list vector and on an i-th element of the vector B and stores the calculation result into the element of the vector A whose element number is the i-th element of the list vector. That is, the equations (2), (3) and (4) are calculations that take an element number of a vector as an element of another vector (list vector). The equation (4) is used in a sparse matrix, particularly in the field of particle pusher and therefore is referred to as a particle pusher type calculation. When the equation (1) is executed by a general computer, the program will be as shown in Fig. 7. When the equation (2) is executed by a general computer, the program will be as shown in Fig. 8. In the following explanation, the data widths of the general register and the floating point register are taken to be 8 bytes. The function of each instruction in Figs. 7 and 8 are described below. GLDM a (GRm), GRn (Function) 8 bytes of data are read from the main memory address specified by the value of the general register m and stores the data in the general register n . And then the value of the general register m is added with a . FLDM a (GRm), FRn (Function) 8-byte data is read from the main memory address specified by the value of the general register m and stored in the floating point register n . And then, the value of the general register m is added with a . FADD FRj, FRm, FRn (Function) The value of the floating point register m and the value of the floating point register n are added up and then the result is stored in the floating point register j . FADD FRm, FRn (Function) The value of the floating point register m and the value of the floating point register n are added up and then the result is stored in the floating point register m . FSTM a (GRm), FRn (Function) The value (8 bytes) of the floating point register n is stored in the main memory address specified by the value of the general register m . And then the value of the general register m is added with a . BCNT GRm, t (Function) The value of the general register m is decremented by 1 . If the result is not zero, the program branches to an address t . If the decremented result is zero, no branching is made. Prior to execution of the program of Fig. 7, the vector A is assumed to be stored in a contiguous region in the main memory starting from address ad1 . That is, the main memory address of A(1) is ad1 and that of A(2) is ad1+8 . Likewise, the vector B is assumed to be stored in a contiguous region of the main memory starting from address ad2 . The vector C is assumed to be stored in a contiguous region of the main memory starting from address ad3 . It is also assumed that the general register 1 is preset with ad1 , the general register 2 with ad2 , the general register 3 with ad3 , and the general register 4 with N . As is seen from Fig. 7, the No. 1 and No. 2 FLDM instructions load A(i) and B(i) into the floating point registers 12 , 13 , add up the values of the two registers, stores the result in the floating point register 20 , and then stores the content of the register into C(i) . That is, executing once the loop of five instructions produces a result for one element. By repeating this loop N times, the results for all elements can be obtained. What matters here is the execution time of one loop. No. 1 and No. 2 FLDM instructions load the data from the main memory into the floating point registers 12, 13 . When data exists in cache, the FLDM instruction is completed in a small number of cycles. But when data is not in he cache, it must be read out from the main memory, which is much slower than the cache, taking a significantly longer time than when the data exists in the cache. Next, No. 3 FADD instruction uses the values of the floating point registers 12, 13 . Since the values of the floating point registers 12, 13 can only be determined after the two preceding FLDM instructions have been executed, i.e., after the data have been read out, the FADD instruction cannot be executed until then. Further, No. 4 FSTM instruction uses the value of the floating point register 20 . The value of the floating point register 20 , however, cannot be determined before the preceding FADD instruction is completed, so that the FSTM instruction cannot be executed until then. That is, two performance degrading factors ― (1) data reading time and (2) conflict between registers ― prolong the execution time of the loop. Particularly the factor (1) constitutes a serious problem for a computation handling a great deal of data because a large amount of data cannot often be accommodated in the cache, resulting in a significant reduction in performance. Prior to execution of the program of Fig. 8, the vector L is assumed to be stored in a contiguous region in the main memory starting from address ad1 . That is, the main memory address of L(1) is ad1 and that of L(2) is ad1+8 . Likewise, the vector A is assumed to be stored in a contiguous region of the main memory starting from address ad2 . The vector B is assumed to be stored in a contiguous region of the main memory starting from address ad3 . It is also assumed that the general register 1 is preset with ad1 , the general register 2 with ad2 , and the general register 4 with N . The vector L is a variation of the list vector Li as shown below. L(i) = 8*(Li(i) - 1) + ad3 That is, L(i) contains the address of B(Li(i))) . When expressing the equation (2) by using Li(i) , the program becomes complex because it contains the operations that multiply (Li(i)-1) by 8 and add ad3 to the result. For simplicity, therefore, L(i) is introduced. From Fig. 8, it is seen that No. 1 GLDM instruction loads L(i) into the general register 20 , No. 2 FLDM instruction loads B(Li(i)) from the main memory address specified by the general register into the floating point register 20 , and No. 3 FSTM instruction stores the value of the floating point register into A(i) . By executing the loop made up of four instructions once, it is possible to determine the result of one element. Executing this loop N times calculates the results for all elements. When matters here is the execution time of one loop as in Fig. 7. No. 1 GLDM instruction loads data from the main memory into the general register 20 . No. 2 FLDM instruction uses the general register 20 , so that it cannot initiate execution before the loading is completed. Further, since No. 2 FLDM instruction loads data from the main memory into the floating point register 20 and No. 3 FSTM instruction uses the floating point register 20 , the instruction execution cannot be started before the data loading is completed. Similar to the case of Fig. 7, two performance degrading factors ― (1) data reading time and (2) register conflict ― extend the execution time of the loop. Likewise when the equations (3) and (4) are executed by a general computer, the programs will be as shown in Figs. 9 and 10. The same performance degrading factors extend the execution time of the loop. The description of the programs are omitted. It is conceivable to use a loop unrolling method as a means for solving the problem of the two performance degrading factors - (1) data reading time and (2) register conflict - caused by the vector processing programs shown in Figs. 7 to 10. With this loop unrolling method, a plurality of elements (=n) are processed in one loop. When compared with the conventional method whereby one element is processed in one loop, this loop unrolling method has 1/n the number of loops required by the conventional method. The principle of the loop unrolling method is described in the above-cited book "Computer Architecture: A Quantitative Approach", at pp.314 to 318 by J.L. Hennessy and D.A. Patterson. The present inventors applied the loop unrolling method to the above-described programs. Application of the loop unrolling method to these programs results in the programs shown in Figs. 11 and 12. In both the programs, four elements are processed in one loop. Prior to the execution of the program of Fig. 11, it is assumed that the general register 4 is preset with N/4 . The other preset data is the same as when executing the program shown in Fig. 7. As seen from Fig. 11, executing once the loop consisting of 17 instructions determines the results of four elements and repeating this loop N/4 times produces the calculated result for all elements. As shown in Fig. 11, for the i-th element, the load operation is performed by No. 1 and No. 2 FLDM instructions, the add operation is done by No. 9 FADD instruction, and the store operation is done by No. 13 FSTM instruction. Similarly, for the (i+1)-th element, the load operation is done by No. 3 and No. 4 FLDM instructions, the add operation is done by No. 10 FADD instruction, and he store operation is done by No. 14 FSTM instruction. Likewise, for the (i+2)-th element, the load operation is performed by No. 5 and No. 6 FLDM instructions, the add operation is performed by No. 11 FADD instruction, and the store operation is performed by No. 15 FSTM instruction. For the (i+3)-th element, the load operation is done by No. 7 and No. 8 FLDM instructions, the add operation is done by No. 12 FADD instruction, and the store operation is done by No. 16 FSTM instruction. Therefore, unlike the instructions in Fig. 7, the series of operations ― load, add and store ― on a certain element is separated from other instructions on the instruction sequence, thereby reducing the effects of performance degradation caused by the (1) data reading time and (2) register conflict. For example, No. 1 and No. 2 FLDM instructions load A(i) and B(i) and the result of the load operation is used seven instructions later, so that as long as the data read time is within seven cycles, the No. 9 FADD instruction that uses the result of the load operation is not made to wait. Further, since the result of addition A(i)+B(i) performed by No. 9 FADD instruction is used four instructions later, No. 13 FSTM instruction is not made to wait if the addition time is less than four cycles. Next the program shown in Fig. 12 will be described. Prior to the execution of the program of Fig. 12, it is assumed that the general register 4 is preset with N/4 . The other preset data is the same as when executing the program shown in Fig. 8. As seen from Fig. 12, executing once the loop consisting of 13 instructions determines the results of four elements and repeating this loop N/4 times produces the calculated result for all elements. As is seen from Fig. 12, for the i-th element, the load operation of L is performed by No. 1 GLDM instruction, the load operation of B(Li) is done by No. 5 FLDM instruction, and the store operation of B(Li) into A is done by No. 9 FSTM instruction. Similarly, for the (i+1)-th element, the load operation of L is performed by No. 2 GLDM instruction, the load operation of B(Li) is carried out by No. 6 FLDM instruction, and the store operation of B(Li) into A is done by No. 10 FSTM instruction. Likewise, for the (i+2)-th element, L is loaded by No. 3 GLDM instruction, B(Li) is loaded by No. 7 FLDM instruction, and B(Li) is stored into A by No. 11 FSTM instruction. For the (i+3)-th element, loading of l is done by No. 4 GLDM instruction, loading of B(Li) is done by No. 8 FLDM instruction, and storing of B(Li) into A is performed by No. 12 FSTM instruction. Therefore, unlike the instructions in Fig. 8, the series of operations ― loading of L element, loading of B(Li) element and storing of B(Li) element into A ― on a certain element number is separated from other instructions on the instruction sequence, thereby reducing the effects of the two performance degradation factors ― (1) data reading time and (2) register conflict. For example, No. 1 GLDM instruction loads L(i) and the result of the load operation is used four instructions later, so that as long as the data read time is within four cycles, the No. 5 FLDM instruction that uses the result of the load operation is not made to wait. Further, since the result of load operation B(Li(i)) performed by No. 5 FLDM instruction is used four instructions later, No. 9 FSTM instruction that uses the result of the load operation is not made to wait if the data read time is less than four cycles. Although the detailed description of application of the loop unrolling method to the programs shown in Figs. 9 and 10 will not be given, the result of the study by the present inventors shows the same effects as described above. According to the study by the present inventors, it has been found that while the loop unrolling method improves the performance, it also has a disadvantage of requiring many registers. The program shown in Fig. 7 requires three floating point registers, whereas the program shown in Fig. 11 requires twelve floating point registers. The program shown in Fig. 8 requires one floating point register and one general register, whereas the program shown in Fig. 12 requires four floating point registers and four general registers. Likewise, the program shown in Fig. 9 requires one floating point register and one general register for vector data storage, whereas the program by the loop unrolling method requires four floating point registers and four general registers. Likewise, the program shown in Fig. 10 requires two floating point registers and one general register for vector data storage, whereas the program by the loop unrolling method requires eight floating point registers and four general registers. If the time it takes to read data or perform calculation increases, a greater number of elements must be processed in one loop, requiring a greater number of registers. Generally, the registers are formed of active elements (i. e., not memory elements) and thus can have many read/write ports (data access ports) permitting a much faster operation than the memory device which can only perform one data read/write operation in one operating cycle. Hence, it is essential to have registers with sufficient capacity to increase the operation speed. Despite this fact, only a small number of registers have conventionally been employed because the cost per bit is high and there is the following limitation on the field length of the register number in the instruction format. The cost problem is being alleviated by the advancement of LSI, whereas the latter problem is still not solved. The number of registers that can be addressed by the program is limited by architecture. For example, if the instruction word has five bits for the register specification field, the number of addressable registers is 32 (5th power of 2). Increasing the number of bits of the register specification field increases the number of registers that can be addressed by the program. But it changes the instruction format, requiring modification of the existing program, which is unrealistic. It is therefore necessary to provide a method that allows the data processor to access a greater number of registers than can be addressed by instructions, without changing the architecture of the data processor. With the first method described the Japanese Patent Laid-Open JP-A- 166649/1982, when a new load instruction is issued for the main memory address for which a load instruction was executed in the past, the operation becomes faster. However, since the vector calculation like the equation (1), (2), (3), and (4) mostly makes the load request for one main memory address only once as with the programs of Figs. 7 to 10, the operation speed is not increased by the conventional technique. In the second register/window prior art, the registers that one program can use are those physical registers belonging to one window and its number is equal to the number of program-addressable registers. This means that the calculation performed by one program cannot be made faster. That is, the window architecture mentioned earlier can increase the processing speed only when a program call and return occurs. Where the processing is complete with one program as in the vector calculation of equation (1), (2), (3) and (4), a speed increase cannot be obtained. Another computer system according to the prior art is quoted in JP-A-62242349. The prior art computer system is equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc., may be lessened to attain a raised speed of program run processing. An address part for designating the main memory is provided in the same instruction. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing method and data processor capable of accessing registers greater in number than registers accessible by instructions, without changing the architecture of the data processor. It is another object of the present invention to provide a vector processing method and vector processor capable of performing a vector calculation of a large number of data without performance degradation due to time required for data transfer to and from a main memory. It is a further object of the present invention to provide a vector processing method and vector processor capable of performing a list vector calculation for scientific and engineering computations. In order to achieve the above objects of the present invention, a plurality of physical registers greater in number than can be addressed by program instructions are provided. The physical registers are divided into a plurality of partial groups (hereinafter referred to as windows). Each of the physical registers is specified by a physical register number determined by a combination of the number of the window and a register number (hereinafter referred to as a logical register number) in an instruction. The logical register number is converted into the physical register number by using the window number. In executing a calculation program having repetitive loops of an instruction sequence, the window is changed for each loop. An element to be calculated at the i-th loop is loaded at the loop before the i-th loop (hereinafter referred to as a preloop), and the result of the calculation at the i-th loop is stored at the loop after the i-th loop (hereinafter referred to as a postloop). The data processor may comprise a plurality of physical registers greater in number than can be addressed by program instructions, the physical registers being divided into a plurality of windows and each of the physical registers being specified by a physical register number determined by a combination of a window number and a logical register number, a current window pointer register for storing a window pointer indicating the window number, and conversion means for converting the logical register number representing the register number in a program instruction into the physical register number by using the current window pointer. Preferably, the data processor further comprises current window pointer valid indicating means for indicating that the current window pointer stored in the current window pointer register is valid. The data processor may comprise a plurality of physical floating point registers greater in number than floating point registers addressable by program instructions, the physical floating point registers being divided into a plurality of windows and each of the physical floating point registers being specified by a physical floating point register number determined by a combination of the window number and a floating point register number (hereinafter called a logical floating point register number) in an instruction, a current floating point window pointer register for storing a current floating point window pointer indicating the window number, a current floating point window pointer valid register for storing a value representing that the current floating point window pointer is valid, and a conversion circuit for converting the logical floating point register number into the physical floating point register number in a program instruction by using the current floating point window pointer. For the processing operation by the data processor, there are provided: a current floating point window pointer change instruction for changing the current floating point window pointer; a floating point register preload instruction for converting the logical floating point register number into the physical floating point register number by using a current floating point window pointer having a different value from the current floating point window pointer stored in the current floating point window pointer register, the different value being determined from said current floating point window pointer stored in the current floating window pointer register, and storing data in the physical floating point register specified by the converted physical floating point register number; and a floating point register poststore instruction for converting the logical floating point register number into the physical floating point register number by using a floating point window pointer having a different value from the floating point window pointer stored in the floating point window pointer register, the different value being determined from the floating point window pointer stored in the floating point window pointer register, and storing data in a main memory from the physical floating point register specified by the converted physical floating point register number. The data processor may comprises : a plurality of physical floating point registers greater in number than floating point registers addressable by program instructions, the floating point registers being divided into a plurality of windows and each of the physical floating point registers being specified by a physical floating point register number determined by a combination of the window and the logical floating point register number; a current floating point window pointer register for storing a current floating point window pointer to be used for converting the logical floating point register number indicating the floating point register number in a program instruction; a first conversion circuit for converting the logical floating point register number into the physical floating point register number by using the current floating point window pointer; a plurality of physical general registers greater in number than floating point registers addressable by instructions and greater in number than general registers addressable by instructions; a current general window pointer register for storing a current general floating point register to be used for converting one of the logical floating point register number and a general register number in a program instruction; a second conversion circuit for converting one of the logical floating point register number and logical general register number into the physical general register number by using the current general floating point window pointer; and a current general window pointer valid register for storing a value representing that the current general window pointer is valid. For the processing operation by the data processor, there are provided at least: a current floating point window pointer change instruction for changing the current floating point window pointer; a current general window pointer change instruction for changing the current floating point window pointer; a floating point register preload instruction for reading data from a main memory at a main memory address stored in the physical general register specified by converting the logical general register number into the physical general register number by using the current general window pointer, converting the logical floating point register number into the physical floating point register number by using a current floating point window pointer having a different value from the current floating point window pointer stored in the current floating point window pointer register, the different value being determined from the current floating point window pointer stored in the current floating window pointer register, and storing the data in the physical floating point register specified by the converted physical floating point register number; and a floating point register poststore instruction for reading data from the physical floating point register specified by the physical floating point register number converted from the logical floating point register number by using a floating point window pointer having a different value from the floating point window pointer stored in the floating point window pointer register, the different value being determined from the floating point window pointer stored in the floating point window pointer register, and for storing the data into the main memory at a main memory address stored in the physical general register specified by converting the logical general register number in the physical general register number by using the current general window pointer. There are further provided: A data processor, wherein said data processor is a vector data processor and further comprising window pointer validity indicating means for indicating that said window pointer stored in said window pointer storing means is valid; a data processor comprising a plurality of physical general-purpose registers greater in number than floating point registers addressable by instructions and greater in number than general-purpose registers addressable by instructions; a second window pointer storing means for storing a second window pointer to be used for converting said logical register number or a general-purpose register number as a logical general-purpose register number in an instruction; a second conversion means for converting said logical register number or a logical general-purpose register number into said physical general-purpose register number by using said second window pointer; and said window pointer valid register for storing a value representing that said window pointer is valid and said second window pointer is valid; a data processor, wherein said instructions include: a second window pointer change instruction for changing said second window pointer; a floating point register preload instruction for reading vector data from said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number into said physical general-purpose register number by using said second window pointer, converting said logical register number into said physical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means, and storing said vector data in said physical register specified by said converted physical register number; and a floating point register poststore instruction for reading vector data from said physical register specified by said physical register number converted from said logical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means and for storing said vector data into said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number in said physical general-purpose register number by using said second window pointer; a data processor, wherein said instructions further include: a floating point register list load instruction for reading vector data from said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number by using a second window pointer having a different value from said second window pointer stored in said second window pointer storing means, said different value being determined from said second window pointer stored in said second window pointer storing means, and storing said vector data in said physical register specified by converting said logical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means; a general register list load instruction for reading vector data from said main memory means at a main memory address determined from information stored in said physical general-purpose register specified by converting a first said logical general-purpose register number by using said second window pointer, and storing said vector data in said physical general-purpose register specified by converting a second said logical general-purpose register number by using a second window pointer having a different value from said second window pointer stored in said second window pointer storing means, said different value being determined from said second window pointer stored in said second window pointer storing means; and a floating point register list store instruction for reading vector data from said physical register specified by converting said logical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means, and storing said vector data in said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number by using a second window pointer having a different value from said second window pointer stored in said second window pointer storing means, said different value being determined from said second window pointer stored in said window pointer storing means; a vector processor, wherein said window pointer storing means is identical with said second window pointer storing means; a data processor, further comprising window pointer validity indicating means for indicating that said window pointer stored in said window pointer storing means is valid. The "register number in the instruction" mentioned in the above description of the floating point register list load instruction means a logical floating point register number or a logical general register number. In the embodiments later described represents the logical floating point register number. In the above description of the general register list load instruction, the operation that "determines a main memory address from information contained in a physical general register" takes the information contained in-the physical general register as the main memory address in the embodiments. In the above description of the floating point register list store instruction, the "register number in the instruction" means a logical floating point register number or a logical general register number. In the embodiments later described it represents the logical floating point register number. All the instructions that reference the floating point registers ― except for the floating point register preload instruction, the floating point register poststore instruction, the floating point register list load instruction, the general register list load instruction, and the floating point register list store instruction ― convert the logical floating point register number into the physical floating point register number by using the current floating point window pointer if the value of the current window pointer valid register is 1 so that referencing the floating point register references the corresponding physical floating point register number. If the value of the current window pointer valid register is 0, the logical floating point register number is equal to the physical floating point register number. All the instructions that reference the general registers ― except for the floating point register preload instruction, the floating point register post-store instruction, the floating point register list load instruction, the general register list load instruction, and the floating point register list store instruction ― convert the logical general register number into the physical general register number by using the current general window pointer if the value of the current window pointer valid register is 1 so that referencing the general register references the corresponding physical general register number. If the value of the current window pointer valid register is 0, the logical general register number is equal to the physical general register number. The floating point register preload instruction, the floating point register poststore instruction, the floating point register list load instruction, the general register list load instruction, and the floating point register list store instruction perform conversion from the logical floating point register number into the physical floating point register number, from the logical floating point register number into the physical general register number, and from the logical general register number into the physical general register number, aforementioned instruction specification, when the value of the current window pointer valid register is 1, and then reference the physical floating point register or physical general register specified by the register number obtained as a result of conversion. When the value of the current window pointer valid register is 0, the logical floating point register number in the instruction specification regarding the conversion from the logical floating point register number into the physical floating is equal to the physical floating point register number to be referenced; as to the conversion from the logical floating point register number into the physical general register number, the logical floating point register number is equal to the physical general register number to be referenced; and in the conversion from the logical general register number into the physical general register number, the logical general register number is equal to the physical general register number to be referenced. The above-described main memory data means the data stored in the main memory, including data stored in the cache. Such main memory data includes vector data. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an explanatory diagram showing an embodiment for converting a logical floating point register number into a physical floating point register number according to the invention; Fig. 2 is an explanatory diagram showing an embodiment for converting a logical floating point register number or a logical general register number into a physical general register number according to the invention; Fig. 3 is a block diagram showing an embodiment of a data processor executing instructions shown in Figs. 4A to 4D; Figs. 4A to 4D show examples of the formats of a current floating point window pointer change instruction, a floating point register preload instruction, an extended floating point register preload instruction, and a floating point register poststore instruction, respectively; Fig. 5 is a block diagram showing an embodiment of a data processor executing instructions shown in Figs. 6A to 6H; Figs. 6A to 6H show examples of the formats of a current floating point window pointer change instruction, a current general window pointer change instruction, a floating point register preload instruction, an extended floating point register preload instruction, a floating point register poststore instruction, a floating point register list load instruction, a general register list load instruction, and a floating point register list store instruction, respectively; Fig. 7 shows an example of a program for vector calculation, part of scientific and engineering computation, performed in general purpose computers; Fig. 8 shows an example of a program for source index type list vector calculation, part of scientific and engineering computation, performed in general purpose computers; Fig. 9 shows an example of a program for target index type list vector calculation, part of scientific and engineering computation, performed in general purpose computers; Fig. 10 shows an example of a program for particle pusher type list vector calculation, part of scientific and engineering computation, performed in general purpose computers; Fig. 11 shows a program of Fig. 7 rewritten by the loop unrolling method; Fig. 12 shows a program of Fig. 8 rewritten by the loop unrolling method; Fig. 13 shows an example of a program for vector calculation according to an embodiment of the present invention; Figs. 14A and 14B show an example of a program for source index type list vector calculation according to an embodiment of the present invention; Figs. 15A and 15B show an example of a program for target index type list vector calculation according to an embodiment of the present invention; and Figs. 16A and 16B show an example of a program for particle pusher type list vector calculation according to an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. An embodiment of the conversion from a logical floating point register number into a physical floating point register number will be described with reference to Fig. 1. In this embodiment, a window of this embodiment defines the range of a physical floating point register number which a logical floating point register number designates. In this embodiment shown in Fig. 1, there are 32 logical floating point registers, whose register numbers are specified as 0 to 31. 88 physical floating point registers are assigned register numbers from 0 to 87. Four windows are provided, w0 to w3, which are specified by the current floating point window pointer 0 to 3 . Let w stand for the current floating point window pointer and r for the logical floating point register number. The physical floating point register number is determined from w and r and represented as < w , r >. w is increased or reduced by instructions, modulo 4. When, for example, w = 3, the value w+1 is 0. In the embodiment shown in Fig. 1, the following conversion is done from the logical floating point register number to the physical floating point register number. 1. When 0 ≤ r ≤ 7: <w, r> = r irrespective of w 2. When 8 ≤ r ≤ 31: <0, r> = r <1, r> = r + 20 <2, r> = r + 40 <3, r> = r + 60 (8 ≤ r ≤ 27) r - 20 (28 ≤ r ≤ 31) Another embodiment of the conversion from a logical register number into a physical register number will be described with reference to Fig. 2. In this embodiment, a window of this embodiment defines the range of a physical general register number which a logical floating point register number or a logical general register number designates. In this embodiment shown in Fig. 2, there are 32 logical floating point registers, whose register numbers are specified as 0 to 31 . 88 physical general registers are assigned register numbers from 0 to 87 . Four windows are provided, w0 to w3 , which are specified by the current general window pointer 0 to 3 . Let wG stand for the current general window pointer and r for the logical general, or floating point, register number. The physical general register number is determined from wG and r and represented as < wG, r >. wG is increased or reduced by instructions, modulo 4. When, for example, wG = 3, the value wG+1 is 0. In the embodiment shown in Fig. 2, the following conversion is done from the logical floating point register number or logical general register number into the physical general register number. 1. When 0 ≤ r ≤ 7: <wG, r> = r irrespective of wG 2. When 8 ≤ r ≤ 31: <0, r> = r <1, r> = r + 20 <2, r> = r + 40 <3, r> = r + 60 (8 ≤ r ≤ 27) r - 20 (28 ≤ r ≤ 31) The above conversion method expressed by equations (6) to (15) has the following two features. 1. 0th to 7th physical general registers and physical floating point registers are used commonly for all windows. These registers as a global register hold data common for all the calculation loops that use respective windows. 2. As to the physical floating point registers (Fig. 1), the logical floating point register numbers 28 to 31 in each window represent the physical floating point registers that are identical with the logical floating point register number 8 to 11 in a window whose window pointer is one larger. As to the physical general register (Fig. 2), when a logical general register number is converted into a physical general register number, the logical general register numbers 28 to 31 in each window represent the physical general registers that are identical with the logical general register numbers 8 to 11 in a window whose window pointer is one larger. When a logical floating point register number is converted into a physical general register number, the logical floating point register numbers 28 to 31 in each window represent the physical general registers that are identical with the logical floating point register numbers 8 to 11 in a window whose window pointer is one larger. These registers are used as overlap registers for data transfer between calculation loops that use adjacent windows. The instruction mnemonics and functions of the newly added instructions mentioned above are defined as follows. An extended floating point register preload instruction shown below, though not mentioned in the foregoing, is newly added as an instruction which has an extended function of the floating point register preload instruction. 1. Current floating point window pointer change instructions: (Instruction mnemonic) CFRWPS GRm (Function) Sets the value of general register m into the current floating point window pointer. 2. Current general window pointer change instruction: (Instruction mnemonic) CGRWPS GRm (Function) Sets the value of general register m into the current general window pointer. 3. Floating point register preload instruction: (Instruction mnemonic) FLDPRM a (GRm), FRn (Function) Reads 8-byte data from the main memory address specified by the value of the general register m and stores it in the floating point register n . At this time, the conversion from a logical floating point register number into a physical floating point register number is done by taking (current floating point window pointer + 1) as a new current floating point window pointer. A logical general register number is converted into a physical general register number by using a current general window pointer. Then, the value of the general register m is added with a . At this time, conversion from the logical general register number into the physical general register number is done by using the current general window pointer. 4. Extended floating point register preload instruction: (Instruction mnemonic) FLDPRE a (GRm), FRn (Function) Reads 8-byte data from the main memory address specified by the value of the general register m and stores it in the floating point register n . The conversion from a logical floating point register number into a physical floating point register number is done by taking (current floating point window pointer + 2) as a new current floating point window pointer. A logical general register number is converted into a physical general register number by using a current general window pointer. Then, the value of the general register m is added with a . At this time, conversion from the logical general register number into the physical general register number is done by using the current general window pointer. 5. Floating point register poststore instruction: (Instruction mnemonic) FSTPOM a (GRm), FRn (Function) Stores the value (8 bytes) of the floating point register n in the main memory address specified by the value of the general register m . At this time, the conversion from the logical floating point register number into the physical floating point register number is done by taking (current floating point window pointer - 1) as a new current floating point window pointer. A logical general register number is converted into a physical general register number by using a current general window pointer. Then, the value of the general register m is added with a . At this time, conversion from the logical general register number into the physical general register number is done by using the current general window pointer. 6. Floating point register list load instruction: (Instruction mnemonic) FLDLI, FRn (Function) Reads 8-byte data from the main memory address specified by the value of the general register n and stores it in the floating point register n . At this time, for a logical floating point register number n , conversion from the logical floating point register number into the physical floating point register number is performed by taking (current floating point window pointer + 1) as a new current floating point window pointer. For a logical floating point register number n , conversion from the logical floating point register number into the physical general register number by taking (current general window pointer + 1) as a new current general window pointer. 7. General register list load instruction: (Instruction mnemonic) GLDLIM a (GRm), GRn (Function) Reads 8-byte data from the main memory address specified by the value of the general register m and stores it in the general register n . At this time, for a logical general register number n , conversion from the logical general register number into the physical general register number is performed by taking (current general window pointer + 2) as a new current general window pointer. For a general register m , conversion from the logical general register number into the physical general register number is performed by using the current general window pointer. Then, the value of the general register m is added with a . At this time, conversion from the logical general register number into the physical general register number is done by using the current general register window pointer. 8. Floating point register list store instruction: (Instruction mnemonic) FSTLI, FRn (Function) Stores the value (8 bytes) of the floating point register n into the main memory address specified by the value of the general register n . At this time, for a logical floating point register number n , conversion from the logical floating point register number into the physical floating point register number is performed by taking (current floating point window pointer - 1) as a new current floating point window pointer. For a logical floating point register number n , conversion from the logical floating point register number into the physical general register number by taking (current general window pointer - 1) as a new current general window pointer. In general floating point isntructions (those using the flaoting point registers, except for instructions 3 to 8), the current floating point window pointer is used in converting the logical floating point register number into the physical floating point register number. With general instructions (those using the general registers, except for instructions 3 to 8), the current general window pointer is used in converting the logical general register number into the physical general register number. In all the instructions described above, the physical floating point register or physical general register are referenced by using the physical floating point register number or physical general register number, generated from the current floating point window pointer or current general window pointer, and the logical floating point register number or logical general register number in an instruction. However, an instruction for directly specifying the physical floating point register number or physical general register number, i.e., an instruction having a wider register number field than other instructions, may also be used. Using the above new mnemonics and functions of instructions in the equation (1) results in a program shown in Fig. 13. This program will be described with reference to Fig. 3. Before executing the program of Fig.13, it is assumed that the general register 4 is preset with N-2 , general register 5 with 1 , general register 6 with 0 , and the current floating point register window pointer with 0 . The other settings are the same as those shown in the program of Fig. 7. Fig. 13 includes an ADD instruction, which is not described in the above. The function of this instruction is described below. ADD GRj, GRm (Function) Adds the value of the general register j and the value of the general register m and stores the result in the general register j . Fig. 13 will be explained below. No. 1 FLDM instruction performs conversion from the logical floating point register number to the physical floating point register number by the current floating point register window pointer and stores A(1) in the physical floating point register <0, 12>. Likewise, No. 2 FLDM instruction stores B(1) in the physical floating point register <0, 13>. No. 3 FLDPRM instruction performs conversion from the logical floating point register number to the physical floating point register number by using the value of (current floating point register window pointer + 1) and stores A(2) in the physical floating point register <1, 12>. In the same way, No. 4 FLDPRM instruction stores B(2) in the physical floating point register <1, 13>. No. 5 FADD instruction performs conversion from the logical floating point register number to the physical floating point register number by using the current floating point register window pointer, and adds up the values of the physical floating point registers <0, 12> and <0, 13>, storing the result in the physical floating point register <0, 20>. Since the No. 1 and No. 2 FLDM instructions store A(1) and B(1) in the physical floating point registers <0, 12> and <0, 13>, respectively, A(1)+B(1) is saved in the physical floating point register <0, 20>. No. 5 ADD instruction and No. 6 CFRWPS instruction increment the current floating point register window pointer by +1 to 1. No. 8 FLDPRM instruction to No. 14 BCNT instruction form a loop and repetitively executed N-2 times. Let w stand for the value of the current floating point register window pointer in the loop. Let us consider the loop executed the ( i -1)th time. It is seen from the values of the general registers 1 and 2 that the data added up by No. 10 FADD instruction are A(i) and B(i) and that what is loaded by the No. 8 and No. 9 FLDPRM instructions into the physical floating point registers < w +1,12> and < w +1,13> is A(i+1) and B(i+1) . As is seen from the value of the general register 3 , No. 11 FSTPOM instruction stores the value of the physical floating point register < w -1,20> in the main memory address C(i-1) . No. 12 ADD instruction and No. 13 CRFWPS instruction increments the current floating point register window pointer w by +1 and the program returns to the start of the loop. That is, in one loop, data A(i+1) , B(i+1) to be added up in the next loop are stored in the physical floating point registers < w +1,12> and < w +1,13>. A(i) and B(i) stored in the physical floating point registers < w ,12> and < w ,13> in the preceding loop are added up and the result stored in the physical floating point register < w ,20>. A(i-1)+B(i-1) stored in the physical floating point register < w -1,20> in the preceding loop is stored in the main memory address C(i-1) . No. 15 through No. 19 instructions after leaving the loop call for processing on the unprocessed elements. No. 15 FADD instruction executes A(N)+B(N), and No. 16 and No. 19 FSTPOM instructions store A(N-1)+B(N-1), A(N)+B(N) in the main memory, respectively. As is seen from the processing in the loop, No. 8 and No. 9 FLDPRM instructions specify the logical floating point registers 12 , 13 and the succeeding No. 10 FADD instruction, though it uses the same logical floating point registers 12 , 13 , accesses different physical floating point registers. No. 10 FADD instruction stores the addition result in the logical floating point register 20 and the next FSTPOM instruction, though it uses the same logical floating point register 20 , accesses different physical floating point registers. Hence, the phenomena that occurred with the program of Fig. 7 ― such as holding the execution of succeeding instructions until the data is read out or the preceding calculation is completed ― do not happen. In other words, the data reading and calculation need only be completed before the next loop is initiated, allowing the program to be executed at high speed. Further, only three logical floating point registers are specified by the program as opposed to many floating point registers required by the program of Fig. 11. When compared with the programs of Figs. 7 and 11, the program of Fig. 13 has a greater overhead because it has an additional processing of updating the current floating point register window pointer that is not included in the programs of Figs. 7 and 11. For example, while the program loop of Fig. 7 is formed of five instructions, the program loop of Fig. 13 consists of seven instructions. It is noted, however, that the overhead caused by the holding of execution of the succeeding instructions until the data is read out or the calculation is completed, as found in the program of Fig. 7, is much larger. The loop unrolling method of the program in Fig. 11 cannot be realized when the registers that can be specified by the program are all used up. In the vector calculation as in scientific and engineering computation which mainly repeats executing the loop of instruction strings, this invention changes the current floating point register window pointer for each loop, i.e., changes the window to be used. The i-th element is processed by loading the i-th element of the operand vector by the floating point register preload instruction in the (i-1)th loop; by performing calculation in the i-th loop; and by storing the result of calculation into the i-th element of the result storage vector by the floating point register poststore instruction performed in the (i+1)th loop. This processing increases the distance on the instruction string between load, calculate and store instructions on one data, eliminating performance degradation due to prolonged data read time and calculation execution time and hence increasing the operation speed. The effect of increasing the operation speed will be described quantitatively. Assume that the time required for reading data during a load operation is four cycles and the time required for an addition is four cycles. As described above, in the program of Fig. 7, No.3 FADD instruction cannot be executed until the data read by No. 1 and No. 2 FLDM instructions have been stored in FR12 and FR13 . No. 4 FSTM instruction cannot be executed until the addition result by No. 3 FADD instruction has been stored in FR20 . Namely, one loop requires 11 cycles = 5 + 3 + 3 = (the number of instructions) + (read data wait cycle number - 1) + (addition cycle number - 1). The "-1" in the second and third terms results from that one cycle in the read data wait cycle number and the addition cycle number is included in the first term. The processing speed is therefore one element/11 cycle = 0.09 element. As described previously, in the program shown in Fig. 11, the time required for the data read and addition during a load operation does not appear so that one loop requires cycles corresponding to the number of instructions. In this case, one loop requires 17 cycles and processes 4 elements. Therefore, the processing speed is 4 elements/17 cycles = 0.24 element/cycle. According to the present invention, as shown in Fig. 13, the time required for the data read and addition during a load operation does not appear so that one loop requires cycles corresponding to the number of instructions. In this case, one loop requires 7 cycles and processes one element. Therefore, the processing speed is one element/7 cycles = 0.14 element/cycle. From the comparison of Figs. 7, 11, and 13, it can be seen that the processing speed becomes faster in the order of Fig. 11, 13, and 7. The program shown in Fig. 11 uses a number of registers to be designated by instructions, posing a fatal problem that usable application programs are limited. Namely, the number of floating point registers to be designated by instructions in the program shown in Fig. 7 is three, the number of floating point registers to be designated by instructions in the program shown in Fig. 11 is twelve, and the number of floating point registers to be designated by instructions in the program shown in Fig. 13 is three. The programs shown in Figs. 7 and 13 can be executed by a data processor having 3 bits of a floating point register specification field, but the program shown in Fig. 11 cannot be executed. The data processing method provides therefore a method of increasing the operation speed by not using the time required for the data read and calculation, without changing the architecture of the data processor. Next, an embodiment of a data processor of the present invention for executing the above-described data processing method will be described with reference to the accompanying drawings. Fig. 3 shows the data processor of the embodiment. The data processor includes: an instruction processing unit 10 for issuing and executing instructions; a main memory 30 for storing instructions and data executed by the instruction processing unit; and a memory control unit 20 for controlling data transfer between the instruction processing unit and the main memory. The instruction processing unit 10 includes: an instruction register 101 for holding the instruction to be executed; an instruction controller 102 for reading the contents of the instruction register 101 and controlling the execution of instructions; a general register group 103 for holding data necessary for general calculation and address calculation; a general calculator 104 for executing general calculation specified by the instruction; a physical floating point register group 105 for holding data necessary for floating point calculation; a floating point calculator 106 for executing floating point calculation specified by the instruction; an address adder 107 for calculating the main memory address containing data to be accessed; a cache 108 for holding main memory data read out by the memory control unit 20 ; a main memory access controller 109 for performing control such as reading main memory data from the memory control unit 20 according to the result of search in the cache 108 ; a current floating point window pointer register 110 for storing a current floating point register window pointer; a current floating point window pointer valid register 111 for indicating that the current floating point register window pointer is valid; and a conversion logic 112 for converting the logical floating point register number specified by the instruction into a physical floating point register number according to equations (6) to (10). The data processor, as shown in Figs. 4A - 4D, is added with four new instructions. These are shown in Fig. 4A as a current floating point window pointer change instruction, in Fig. 4B as a floating point register preload instruction, in Fig. 4C as an extended floating point register preload instruction, and in Fig. 4D as a floating point register poststore instruction. Of the above instructions, the instruction mnemonics and functions of the instructions have been described already. In Figure 4A, the instruction code represents the current floating point window pointer change instruction. The general register number specifies the general register that contains a value of the current floating point register window pointer to be set. The floating point register preload instruction is one to store the main memory data into a floating point register belonging to the window of (current floating point register window pointer + 1). In Figure 4B, the instruction code represents the floating point register preload instruction. The floating point register number represents a logical floating point register number ( r ) where the main memory data is stored. The corresponding physical floating point register number is < w+1,r > where w is a current floating point register window pointer. The value of the general register is the main memory address from which data is to be read out. After data is read out, the value to be added to the general register is an increment value. The extended floating point register preload instruction is one to store the main memory data into a floating point register belonging to a window of (current floating point register window pointer + 2). In Figure 4C, the instruction code represents the extended floating point register preload instruction. The floating point register number represents a logical floating point register number ( r ) where the main memory data is stored. The corresponding physical floating point register number is < w+2,r > where w is a current floating point register window pointer. The value of the general register is the main memory address from which data is to be read out. After data is read out, the value to be added to the general register is an increment value. The function of the extended floating point register preload instruction is simply an extension of the floating point register preload instruction and is self-evident from the above description. The extended floating point register preload instruction is used in the following case. In the embodiment shown in Fig. 13, the data read time is within eight cycles. The data read at No. 9 FLDPRM instruction during the (i-1)-th loop is stored in the physical floating point register < w +1, 13> which is read by No. 10 FADD instruction during the i-th loop, within eight cycles after the execution of No. 9 instruction. Therefore, the execution of No. 10 instruction is not required to wait, and the instructions in the loop from No. 8 to No. 14 instruction can be executed one instruction per one cycle. For example, assume that the data read time becomes long and exceeds eight cycles because of a slow memory element. In such a case, the data read by No. 9 FLDPRM instruction during the (i-1)-th loop is stored in the physical floating point register < w +1, 13> which is read by No. 10 FADD instruction during the i-th loop, after more than nine cycles after the execution of No. 9 instruction. Therefore, the execution of No. 10 instruction is required to wait. Namely, the instructions within the loop from No. 8 to No. 14 instruction cannot be executed one instruction per one cycle pitch. In such a case, as an alternative of the floating point register preload instruction, the extended floating point register preload instruction is used. The program is changed such that the time when the data read by the extended floating point register preload is stored in the floating point register, is delayed by two loops. Namely, although in the program shown in Fig. 13 the data read during the (i-1)-th loop is stored in the floating point register during the i-th loop, it becomes possible by using the extended floating point register preload instruction to store the data read during the (i-1)-th loop in the floating point register during the (i+1)-th loop. By changing the program correspondingly, the instruction within the loop can be executed one instruction per one cycle pitch, even in the case of a longer data read time. In Figure 4D, the instruction code represents the floating point register poststore instruction. The floating point register number represents a logical floating point register number ( r ) from which the data is read. The corresponding physical floating point register number is < w-1,r > where w is a current floating point register window pointer. The value of the general register is the main memory address in which data is to be stored. After data is read out, the value to be added to the general register is an increment value. The operation of these instructions is explained by referring to Figure 3. First, let us explain about the current floating point register window pointer change instruction. When an instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a current floating point register window pointer change instruction, the general register specified by the instruction is read from the general register group 103 and the value of that register is set in the current floating point window pointer register 110 . Next, the floating point register preload instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a floating point register preload instruction, the address adder 107 takes in the content of the general register specified by the instruction and puts it out as a main memory address from which to read data. The main memory access controller 109 searches through the cache 108 according to the main memory address. If there is desired data in the cache, the controller 109 transfers it from the cache and, when the data is not found, transfers data from the main memory 30 through the memory control unit 20 . The transferred data is stored in the floating point register 105 . The physical floating point register number in which the data is stored is determined by the conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ), and the physical floating point register number is < w+1,r > where w is the value of the current floating point window pointer register 110 . After the data transfer has started, the general calculator 104 adds an increment value to the value of the general register. If the data is not present in the cache 108 , it is conceivable that the data transferred from the main memory 30 is written in the floating point register 105 and in the cache 108 . However, the write operation into the cache 108 requires two or more cycles in general. Therefore, there is a fear that the execution of the next instruction is stopped, being unable to ensure the processing speed of one instruction per one cycle. In view of this, in this embodiment, if the data is not present in the cache, the data transferred from the main memory 30 is not written in the cache 108 but is written only in the floating point register 105 . Next, we will explain about the extended floating point register preload instruction. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be an extended floating point register preload instruction, the address adder 107 takes in the content of the general register specified by the instruction and puts it out as a main memory address from which to read data. The main memory access controller 109 searches through the cache 108 according to the main memory address. If there is desired data in the cache, the controller 109 transfers it from the cache and, when the data is not found, transfers data from the main memory 30 through the memory control unit 20 . The transferred data is stored in the floating point register 105 . The physical floating point register number in which the data is stored is determined by the conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ), and the physical floating point register number is < w +2 ,r > where w is the value of the current floating point window pointer register 110 . After the data transfer has started, the general calculator 104 adds an increment value to the value of the general register. Next, the floating point register poststore instruction will be described. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a floating point register poststore instruction, the address adder 107 takes in the content of the general register specified by the instruction and puts it out as a main memory address in which to store data. The data is read from the floating point register 105 . The physical floating point register number from which the data is read out is determined by the conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ), and the physical floating point register number is < w-1,r > where w is the value of the current floating point window pointer register 110 . The main memory access controller 109 searches through the cache 108 according to the main memory address. If the cache has a copy of data which is stored in the main memory address, the controller 109 replaces that data with the read data. When the data is not found in the cache, nothing is done about the cache. The main memory access controller 109 stores the read data into the main memory address via the memory control unit 20 . After the data transfer has started, the general calculator 104 adds an increment value to the value of the general register. If a copy of the data stored in the main memory 30 is not present in the cache 108 , it is conceivable that the data read from the floating point register 105 is stored in the main memory 30 at the corresponding address, and also in the cache 108 . However, the write operation into the cache 108 requires two or more cycles in general. Therefore, there is a fear that the execution of the next instruction is stopped, being unable to ensure the processing speed of one instruction per one cycle. In view of this, in this embodiment, if a copy of the data stored in the main memory 30 is not present in the cache, the data read from the floating point register 105 is stored in the main memory 30 at the corresponding address, but is not written in the cache 108 . In general floating point instructions (calculate, load and store), the logical floating point register number r indicated in the instruction is converted by the conversion logic 112 into a physical floating point register number, which is given by < w,r > where w is the value of the current floating point window pointer register 110 . Then, a reference is made to the floating point register represented by the physical floating point register number. When the value of the current floating point window pointer valid register 111 is "1", the current floating point register window pointer is valid. That is, the conversion circuit 112 converts the logical register number into the physical register number. When the register 111 has a value "0", the logical register number-physical register number conversion is not performed, making the logical floating point register number specified by the instruction a physical floating point register number. Thus, the physical floating point register specified by this derived physical floating point register number is referenced. The current floating point window pointer valid register 111 may be assigned an idle bit of an existing register that stores control information of the data processing system and the validity bit may be set by using an existing instruction for storing a value in the register. In the description of the above embodiment, one current floating point register window pointer register 111 is used. However, two such current floating point register window pointer registers may be used, one (referred to as register A ) being used only by the floating point register preload instruction and the other (referred to as register B ) being used by other instructions except the floating point register preload instruction, and the current floating point window pointer change instruction change both the two current floating point register window pointer registers at the same time. Such arrangement is effective for a longer memory read time as in the following. For the floating point register preload instruction, the processing pitch of one instruction per one cycle can be ensured under the condition that the memory read time allows the data read by the i-th loop instruction to be stored in the floating point register before the calculation instruction starts at the (i+1)-th loop, as described previously. For the extended floating point register preload instruction, the processing pitch of one instruction per one cycle can be ensured under the condition that the memory read time allows the data read by the i-th loop instruction to be stored in the floating point register before the calculation instruction starts at the (i+2)-th loop, as described previously. If the memory read time is longer than the time required for the data read by the i-th loop instruction to be stored in the floating point register before the calculation instruction starts at the (i+2)-th loop, it is not possible to ensure the processing pitch of one instruction per one cycle. It is possible to use an instruction extended further from the above-described extended floating point register preload instruction, but an increase of the number of instructions is not desirable. In this connection if the window pointer to be used by the floating point register preload instruction is different from other window pointers to be used by other instructions, it is possible to deal with a change in the memory read time without using the extended floating point register preload instruction. For example, if the memory read time is within such a time period allowing the data read during the i-th loop to be stored in the floating point register before the calculation instruction starts at the (i+1)-th loop, it is possible to ensure the processing pitch of one instruction per one cycle by issuing the floating point register preload instruction and loading the data in the register of the window ( w +1) while setting the register B to a value w and the register A to the value w during the i-th loop. If the memory read time is not shorter than such a time period allowing the data read during the i-th loop can be stored in the floating point register before the calculation instruction starts at the (i+2)-th loop but it is within such a time period allowing the data read during the i-th loop can be stored in the floating point register before the calculation instruction starts at the (i+3)-th loop, then it is possible to ensure the processing pitch of one instruction per one cycle by issuing the floating point register preload instruction and loading the data in the register of the window ( w +3) while setting the register B to a value ( w ) and the register A to a value w +2) during the i-th loop. At the end of a loop, the current floating point window pointer change instruction adds 1 to the two current floating point register window pointer registers at the same time, allowing the concurrent processing at the next loop. Described above is the way the instructions-the current floating point window pointer change instruction, the floating point preload instruction, the extended floating point register preload instruction, the floating point register poststore instruction, and general floating point instructions under the control of the floating point window pointer-work. With the above embodiment, the program shown in Fig. 13 can be implemented increasing the speed of the vector calculation. This has been described previously. According to the method of this invention, the current floating point window pointer is changed to convert a floating point register number in an instruction into a different physical floating point register number, making it possible to access a greater number of physical registers than can be addressed by instructions, without changing the architecture of the data processor. This method realizes a program as shown in Fig. 13, preventing performance degradation which would otherwise be caused by the holding of instruction execution due to prolonged data reading or register conflicts. This in turn ensures a faster execution of programs. As can be seen from the program of Fig. 13, vector calculation as in scientific and engineering computation which mainly repeats executing the loop of instruction strings performs processing as follows by allocating different windows to different loops. The i-th element is processed by loading the i-th element of the operand vector by the floating point preload instruction in the (i-1)th loop; by performing calculation in the i-th loop; and by storing the result of calculation into the i-th element of the result storage vector by the floating point poststore instruction performed in the (i+1)th loop. This processing increases the distance on the instruction string between load, calculate and store instructions on one data, eliminating performance degradation due to prolonged data read time and calculation execution time and increasing the operation speed. Next, an embodiment of a data processor of the present invention for executing the above-described data processing method will be described with reference to the accompanying drawings. Next, an embodiment of a data processing method and data processor applying the present invention to a list vector calculation will be described with reference to the accompanying drawings. A program shown in Figs. 14A and 14B is obtained when applying the present invention to the equation (2) of the source index type calculation. Before executing the program of Figs. 14A and 14B, the vectors L , A , and B are assumed to be stored in contiguous regions of the main memory starting from addresses ad1 , ad2 , and ad3 . It is also assumed that the general register 1 is preset with ad1 , the general register 2 with ad2 , the general register 4 with N-3 , the general register 5 with 1 , the general register 6 with 0 , the current floating point window pointer with 0 , the current general window pointer with 0 , and the current window pointer valid register with 1 . The vector L is a variation of the list vector Li as shown in equation (5). Figs. 14A and 14B include the SUB instruction that is not described in the above. This function will be explained below. SUB GRj, GRm (Function) Subtracts the value of the general register m from the value of the general register j and store the result into the general register j . Figs. 14A and 14B will be explained below. No. 1 GLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer. Hence, L(1) , i.e., "address of B(Li(1)) " is stored in the physical general register <0,20>. No. 2 FLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer and converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer. Hence, data B(Li(1)) in the main memory address specified by L(1) contained in the physical general register <0,20> is stored into the physical floating point register <0,20>. No. 3 ADD instruction specifies the logical general register 6 . Since, from equation (10), this register is a physical general register 6 (global register), the value of the physical general register 6 is set to 1. No. 4 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, i.e., sets the window pointer to 1. Similarly, No. 5 CGRWPS instruction puts the value of the physical general register 6 into the current general window pointer, i.e., set the window pointer to 1. No. 6 GLDM instruction performs conversion from the logical general register number into a physical general register number by using the current general window pointer. This causes L(2) , i.e., the "address of B(Li(2)) " to be stored in the physical floating point register <1,20>. No. 7 FLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer and also the logical floating point register number into the physical floating point register number by using the current floating point window pointer. As a result, the data B(Li(2)) in the main memory address specified by L(2) contained in the physical general register <1,20> is stored into the physical floating point register <1,20>. No. 8 ADD instruction sets 2 into the physical general register 6 . No. 9 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, i.e., sets 2 into the window pointer. Likewise, No. 10 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer, i.e., sets 2 into the window pointer. No. 11 GLDM instruction perform conversion from the logical general register number into the physical general register number by using the current general window pointer. This causes L(3) , i.e., the "address of B(Li(3)) " to be stored into the physical floating point register <2,20>. No. 12 SUB instruction sets 1 into the physical general register 6 . No. 13 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, i.e., sets 1 into the window pointer. Likewise, No. 14 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer, i.e., sets 1 into the window pointer. No. 15 GLDLIM instruction to No. 21 BCNT instruction form a loop, which is repetitively executed N-3 times. Let w stand for the value of the current floating point window pointer and WG for the value of the current general window pointer. Let us look at the loop that is executed the i-th time (i starts from 2). As is seen from the value of the physical general register 1 , what is loaded into the physical general register < WG +2,20> by No. 15 GLDLIM instruction is L(i+2) , i.e., "the address of B(Li(i+2)) ." It is seen from the value of the physical general register < WG +1,20> that what is loaded into the physical floating point register < w +1,20> by No. 16 FLDLI instruction is B(Li(i+1)) . As is seen from the value of the general register 2 , No. 17 FSTPOM instruction stores the value of the physical floating point register <w-1,20> into the main memory address of A(i-1) . No. 18 ADD instruction, No. 19 CFRWPS instruction and No. 20 CGRWPS instruction increment the current floating point window pointer by +1 and also the current general window pointer WG by +1 before the program returns to the start of the loop. In one loop, the current floating point window pointer is assumed to have a value w and the current general window pointer a value WG . The address of data B(Li(i+2)) , which will be stored into the physical floating point register < w +2,20> in the next loop, i.e., L(i+2) , is stored into the physical general register < WG +2,20>. From the address of data B(Li(i+1)) , i.e., L(i+1) , which was stored in the physical general register < WG +1,20> in the previous loop, the data B(Li(i+1)) is read out and stored into the physical floating point register < w +1,20>. Data B(Li(i-1)) , which was stored in the physical floating point register < w -1,20> two loops before, is stored into the main memory address of A(i-1) . No. 22 through No. 28 instructions after leaving the loop call for processing on the unprocessed elements. No. 23 STPOM instruction stores B(Li(N-2)) into the main memory address of A(N-2) . No. 27 FSTPOM instruction stores B(Li(N-1)) into the main memory address of A(N-1) . No. 28 FSTM instruction stores B(Li(N)) into the main memory address of A(N) . As is seen from the processing within the loop, No. 15 GLDLIM instruction specifies the logic general register 20 and writes data into it and No. 16 FLDLI instruction specifies the logical general register 20 and reads data from it. It is noted, however, that the physical general registers 20 actually accessed by these instructions are different, that is, < wG +2,20> and < wG +1,20>. No. 16 FLDLI instruction specifies the logical floating point register number 20 and writes data into the floating point register and No. 17 FSTPOM instruction specifies the logical floating point register number 20 and reads data from the floating point register. It should be noted that the physical floating point registers actually accessed are different, i.e., < w +1,20> and < w -1,20>. Therefore, the phenomena that occurred with the program of Fig. 8 ― such as halting the execution of succeeding instructions until the data is read out ― do not happen. In other words, the data reading need only be completed before the next loop is initiated, allowing the program to be executed at high speed. Further, only one each of logical floating point register and logical general register are specified by the program for vector data storage, whereas many floating point registers and general registers are required by the program of Fig. 12. When compared with the program of Fig. 8, the program of Figs. 14A and 14B has a greater overhead because it has additional processing of updating the current floating point window pointer and current general window pointer that is not included in the program of Fig. 8. For example, while the program loop of Fig. 8 is formed of four instructions, the program loop of Figs. 14A and 14B consists of seven instructions. It is noted, however, that the overhead caused by the holding of execution of the succeeding instructions until the data is read out, as found in the program of Fig. 8, is much larger. The loop unrolling method of the program in Fig. 12 cannot be realized when the registers that can be specified by the program are all used up. Although it has overhead due to the updating of the current floating point window pointer and the current general window pointer, this method is therefore considered to be superior. The equation (3) of the target index type calculation is realized by the program of Figs. 15A and 15B when the above newly added functions are used. Prior to execution of the program of Figs. 15A and 15B, the vector L is assumed to be stored in a contiguous region in the main memory starting from address ad1 . That is, the main memory address of L(1) is ad1 and that of L(2) is ad1+8 . Likewise, the vector B is assumed to be stored in a contiguous region of the main memory starting from address ad2 . The vector A is assumed to be stored in a contiguous region of the main memory starting from address ad3 . It is also assumed that the general register 1 is preset with ad1 , the general register 2 with ad2 , the general register 4 with N-3 , the general register 5 with 1 , the general register 6 with 0 , the current floating point window pointer with 0 , the current general window pointer with 0 , and the current window pointer valid register with 1 . The vector L is a variation of the list vector Li as shown in equation (5). Now, Figs. 15A and 15B will be explained. No. 1 GLDM instruction performs conversion from the logical general register number into the physical general register number by using the current general window pointer and thus stores L(1) , i.e., the address of A(Li(1)) into the physical general register <0,20>. No. 2 FLDM instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer and thus stores B(1) into the physical floating point register <0,20>. No. 3 ADD instruction sets 1 to the physical general register 6 (the general register 6 is a global register and thus is not subjected to the logical general register number-physical general register number conversion). No. 4 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, that is, sets 1 to the window pointer. Likewise, No. 5 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer to put 1 into the window pointer. No. 6 GLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer and thus stores L(2) , i.e., the address of A(Li(2)) , into the physical general register <1,20>. No. 7 FLDM instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer and thus stores B(2) into the physical floating point register <1,20>. No. 8 ADD instruction sets 2 into the physical general register 6 (the general register 6 is a global register and therefore is not subjected to the conversion from the logical general register number to the physical general register number). No. 9 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, that is, sets 2 to the window pointer. Likewise, No. 10 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer to put 2 into the window pointer. No. 11 GLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer and thus stores L(3) , i.e., the address of A(Li(3)) , into the physical general register <2,20>. No. 12 SUB instruction sets 1 into the physical general register 6 . No. 13 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer to put 1 in the window pointer. Similarly, No. 14 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer to put 1 in the window pointer. No. 15 GLDLIM instruction to No. 21 BCNT instruction form a loop, which is repetitively executed N-3 times. Let w stand for the value of the current floating point window pointer and WG for the value of the current general window pointer. let us look at the loop that is executed the i-th time (i starts from 2 ). As is seen from the value of the general register 1 , what is loaded into the physical general register < WG +2,20> by No. 15 GLDLIM instruction is L(i+2) , i.e., "the address of A(Li(i+2)) ." It is seen from the value of the general register 2 that what is loaded into the physical floating point register < w +1,20> by No. 16 FLDPRM instruction is B(i+1) . No. 17 FSTLI instruction stores the value of the physical floating point register < w +1,20>, i.e., B(i-1) into the main memory address of A(Li(i-1)) . No. 18 ADD instruction, No. 19 CFRWPS instruction and No. 20 CGRWPS instruction increment the current floating point window pointer by +1 and also the current general window pointer WG by +1 before the program returns to the start of the loop. In one loop, the current floating point window pointer is assumed to have a value w and the current general window pointer a value WG . The address of data A(Li(i+2)) , i.e., address L(i+2) , in which B(i+2) will be stored three loops later, is stored into the physical general register < WG +2,20>. B(i+1) , which is to be stored in the main memory two loops later, is stored in the physical floating point register < w +1,20>. B(i-1) , which was stored in the physical floating point register <B-1,20> two loops before, is stored into the address of A(Li(i-1)) , i.e., L(i-1) , which was stored in the physical general register < WG -1,20> three loops before. No. 22 through No. 28 instructions after leaving the loop call for processing on the unprocessed elements. No. 23 FSTLI instruction stores B(N-2) into the main memory address of A(Li(N-2)) . No. 27 FSTLI instruction stores B(N-1) into the main memory address of A(Li(N-1)) . No. 28 FSTM instruction stores B(N) into the main memory address of A(Li(N)) . As can be seen from the processing in the loop, while No. 15 GLDLIM instruction specifies the logical general register number 20 and writes data into the general register and No. 17 FSTLI instruction specifies the logical floating point register number 20 and reads data from the general register, the physical general registers actually accessed are different, i.e., < WG +2,20> and < WG -1,20>. No. 16 FLDPRM instruction specifies the logical floating point register number 20 and writes data into the floating point register and the immediately following No. 17 FSTLI instruction specifies the logical floating point register number 20 and reads data from the floating point register. It is noted that the actual physical floating point registers accessed are different, < w +1,20> and < w -1,20>. Therefore, the phenomena that occurred with the program of Fig. 9 ― such as halting the execution of succeeding instructions until the data is read out ― do not happen. In other words, the data reading need only be completed before the next loop is initiated, allowing the program to be executed at high speed. When compared with the program of Fig. 9, the program of Figs. 15A and 15B has a greater overhead because it has additional processing of updating the current floating point window pointer and current general window pointer that is not included in the program of Fig. 9. For example, while the program loop of Fig. 9 is formed of four instructions, the program loop of Figs. 15A and 15B consists of seven instructions. It is noted, however, that the overhead caused by the holding of execution of the succeeding instructions until the data is read out, as found in the program of Fig. 9, is much larger. Although it has overhead due to the updating of the current floating point window pointer and the current general window pointer, this method is therefore considered to be superior. Using the above-mentioned new functions, the equation (4) for particle pusher type calculation is implemented by the program shown in Figs. 16A and 16B. Prior to execution of the program of Figs. 16A and 16B, the vector L is assumed to be stored in a contiguous region in the main memory starting from address ad1 . That is, the main memory address of L(1) is ad1 and that of L(2) is ad1+8 . Likewise, the vector A is assumed to be stored in a contiguous region of the main memory starting from address ad3 . The vector B is assumed to be stored in a contiguous region of the main memory starting from address ad2 . It is also assumed that the general register 1 is preset with ad1 , the general register 2 with ad2 , the general register 4 with N-3 , the general register 5 with 1 , the general register 6 with 0 , the current floating point window pointer with 0 , the current general window pointer with 0 , and the current window pointer valid register with 1 . The vector L is a variation of the list vector Li as shown in equation (4). Now, Figs. 16A and 16B will be explained. No. 1 GLDM instruction performs conversion from the logical general register number into the physical general register number by using the current general window pointer and thus stores L(1) into the physical general register <0,20>. No. 2 FLDM instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer and also the logical general register number into the physical general register number by using the current general window pointer. The No. 2 instruction hence stores the main memory data at an address specified by L(1) , i.e., A(Li(1)) , into the physical floating point register <0,20>. No. 3 FLDM instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer and thus stores B(1) into the physical floating point register <0,20>. No. 4 FADD instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer, adds up the value of the physical floating point register <0,20> and the value of the physical floating point register <0,21>, and stores the result A(Li(1))+B(1) into the physical floating point register <0,20>. No. 5 ADD instruction sets 1 into the physical general register 6 (the general register 6 is a global register from equation (10)). No. 6 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, that is, sets 1 to the window pointer. Likewise, No. 7 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer to put 1 into the window pointer. No. 8 GLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer and thus stores L(2) , i.e., the address of A(Li(2)) , into the physical general register <1,20>. No. 9 FLDM instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer and also the logical general register number into the physical general register number by using the current general window pointer, and thus stores the main memory data at an address specified by L(2) , i.e., A(Li(2)) , into the physical floating point register <1,20>. No. 10 FLDM instruction converts the logical floating point register number into the physical floating point register number by using the current floating point window pointer and thus stores the B(2) into the physical floating point register <1,21>. No. 11 ADD instruction sets 2 into the physical general register 6 . No. 12 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer, that is, sets 2 to the window pointer. Likewise, No. 13 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer to put 2 into the window pointer. No. 14 GLDM instruction converts the logical general register number into the physical general register number by using the current general window pointer and thus stores L(3) , i.e., the address of A(Li(3)) , into the physical general register <2,20>. No. 15 SUB instruction sets 1 into the physical general register 6 . No. 16 CFRWPS instruction sets the value of the physical general register 6 into the current floating point window pointer to put 1 in the window pointer. Similarly, No. 17 CGRWPS instruction sets the value of the physical general register 6 into the current general window pointer to put 1 in the window pointer. No. 18 GLDLIM instruction to No. 26 BCNT instruction form a loop, which is repetitively executed N-3 times. Let w stand for the value of the current floating point window pointer and WG for the value of the current general window pointer. Let us look at the loop that is executed the i-th time (i starts from 2). As is seen from the value of the general register 1 , what is loaded into the physical general register < WG +2,20> by No. 18 GLDLIM instruction is L(i+2) , i.e., "the address of A(Li(i+2)) ." It is seen from the physical general register < WG +1,20> that what is loaded into the physical floating point register < w +1,20> by No. 19 FLDLI instruction is A(Li(i+1)) . It is also seen from the value of the general register 2 that what is loaded into the physical floating point register < w +1,21> by No. 20 FLDPRM instruction is B(i+1) . No. 21, FADD instruction adds up the value of the physical floating point register < w ,20>, i.e., (Li(i)) , and the value of the physical floating point register < w ,21>, i.e., B(i) and stores the result into the physical floating point register < w ,20>. No. 21 FSTLI instruction stores the value of the physical floating point register < w -1,20>, i.e., A(Li(i-1))+B(i-1) , into the main memory address specified by the general register < WG -1,20>, i.e., L(i-1) or the address of A(Li(i-1)) . No. 23 ADD instruction, No. 24 CFRWPS instruction and No. 25 CGRWPS instruction increment the current floating point window pointer by +1 and also the current general window pointer WG by +1 before the program returns to the start of the loop. In one loop, the current floating point window pointer is assumed to have a value w and the current general window pointer a value WG . No. 18 GLDLIM instruction reads from the main memory the address of data A(Li(i+2)) ― which is to be stored into the physical floating point register < w +2,20> in the next loop ― that is, address L(i+2) or the address of A(Li(i+2)) , and then stores the address into the physical general register < WG +2,20>. No. 19 FLDLI instruction reads A(Li(i+1)) from L(i+1) or the address of A(Li(i+1)) , which was stored in the physical general register < WG +1,20> one loop before, and stores the data into the physical floating point register < w +1,20>. No. 20 FLDPRM instruction stores into the physical floating point register < w +1,21> data B(i+1) that is to be used in the addition calculation in the next loop. No. 21 FADD instruction adds up A(Li(i)) and B(i) , which were loaded into the physical floating point registers < w ,20> and < w ,21> in the previous loop, and stores the result into the physical floating point register < w ,20>. No. 22 FSTLI instruction stores A(Li)(i-1))+B(i-1) ― which was stored in the physical floating point register < w -1,20> one loop before ― into the main memory address or L(i-1) (i.e., the address of A(Li(i-1)) ) that was loaded into the physical general register < WG -1,20> three loops before. No. 28 through No. 36 instructions after leaving the loop call for processing on the unprocessed elements. No. 30 FSTLI instruction stores A(Li(N-2))+B(N-2) into the main memory address of A(Li(N-2)). No. 35 FSTLI instruction stores A(Li(N-1))+B(N-1) into the main memory address of A(Li(N-1)) . No. 36 FSTM instruction stores A(Li(N))+B(N)) into the main memory address of A(Li(N)) . As can be seen from the processing in the loop, while No. 18 GLDLIM instruction specifies the logical general register number 20 and writes data into the general register and No. 19 FLDLI instruction specifies the logical general register number 20 and reads data from the general register, the physical general registers actually accessed are different, i.e., < WG +2,20> and < WG +1,20>. No. 19 FLDLI instruction specifies the logical floating point register number 20 and writes data into the floating point register and No. 21 FADD instruction specifies the logical floating point register number 20 and reads data from the floating point register. It is noted that the actual physical floating point registers accessed are different, < w +1,20> and < w ,20>. Further, No. 20 FLDPRM instruction specifies the logical floating point register number 21 and writes data into the floating point register and No. 20 FADD instruction specifies the logical floating point register number 21 and reads data from the floating point register. The actual physical floating point registers accessed, however, are different, i.e., < w +1,21> and < w ,21>. No. 21 FADD instruction specifies the logical floating point register number 20 and writes data into the floating point register and No. 22 FSTLI instruction specifies the logical floating point register number 20 and reads data from the floating point register. The actual physical floating point registers accessed, however, are different, i.e., < w ,20> and < w -1,20>. Therefore, the phenomena that occurred with the program of Fig. 10 ― such as halting the execution of succeeding instructions until the data is read out ― do not happen. In other words, the data reading need only be completed before the next loop is initiated, allowing the program to be executed at high speed. When compared with the program of Fig. 10, the program of Figs. 16A and 16B has a greater overhead because it has additional processing of updating the current floating point window pointer and current general window pointer that is not included in the program of Fig. 10. For example, while the program loop of Fig. 10 is formed of six instructions, the program loop of Figs. 16A and 16B consists of nine instructions. It is noted, however, that the overhead caused by the holding of execution of the succeeding instructions until the data is read out, as found in the program of Fig. 10, is much larger. Although it has overhead due to the updating of the current floating point window pointer and the current general window pointer, this method is therefore considered to be superior. In the list vector calculation ― a part of the vector calculation in scientific and engineering computation ― which mainly repeats executing the loop of instruction sequence, this invention changes the current floating point window pointer and the current general window pointer for each loop, i.e., changes the window to be used. In the source index type calculation, the i-th element is processed by the following steps: loading an i-th element of the list vector into a general register by the general register list load instruction in (i-2)-th loop; loading an element of the source vector (a vector to be read out) specified by the i-th element of the list vector into a floating point register ― which uses data in the general register as its main memory address ― by means of the floating point register list load instruction in the (i-1)-th loop; and storing data of the floating point register into an i-th element of the target vector (a vector to be written into) by means of a floating point register poststore instruction in the (i+1)-th loop. This series of operations increases the distances on the instruction string between the list vector loading, source vector loading and target vector storing operations on one element number, thereby eliminating performance degradation due to prolonged data read time and hence increasing the operation speed. In the target index type calculation, the i-th element is processed by the following steps: loading an i-th element of the list vector into a general register by the general register list load instruction in (i-2)-th loop; loading an i-th element of the source vector (a vector to be read out) into a floating point register by a floating point register preload instruction in (i-1)-th loop; and storing into an element of the target vector specified by the i-th element of the list vector the data in the floating point register ― which uses data in the general register as its main memory address ― by means of the floating point register list store instruction in (i+1)-th loop. This series of operations increases the distances on the instruction string between the list vector loading, source vector loading and target vector storing operations on one element number, thereby eliminating performance degradation due to prolonged data read time and hence increasing the operation speed. In the particle pusher type calculation, the i-th element is processed by the following steps: loading an i-th element of the list vector into a general register by the general register list load instruction in (i-2)-th loop; loading into a first floating point register an element of a first vector (i.e., vector A of equation (4)) specified by the i-th element of the list vector by means of the floating point register list load instruction in (i-1)-th loop; loading an i-th element of a second vector (i.e., vector B of equation (4)) into a second floating point register by means of the floating point register preload instruction; adding up the values of the two floating point registers (i.e., adding the element of the fist vector specified by the i-th element of the list vector and the i-th element of the second vector) by means of the floating point addition instruction in i-th loop; and storing the result of addition into the element of the first vector specified by the i-th element of the list vector, the element using the value of the general register as its main memory address. This series of operations increases the distances on the instruction string between various operations on one element number, i.e., between the list vector loading, first vector loading, second vector loading (first and second vector loading are performed in one loop because they are not related with each other), addition of the first and second vectors' elements and storing of the addition result into the first vector, thereby eliminating performance degradation due to prolonged data read time and calculation execution time and hence increasing the operation speed. Next, an embodiment of a data processor suitable for executing a list vector calculation will be described with reference to the accompanying drawings. Fig. 5 shows the data processor of this embodiment. In Fig. 5, like elements to those shown in Fig. 3 are represented by using identical reference numerals. The main circuitry of the instruction processing unit 10 includes: a current floating point window pointer register 110 for storing a current floating point window pointer; a current general window pointer register 113 for storing a current general window pointer; a current window pointer valid register 111 for indicating that the current floating point window pointer and the current general window pointer are valid; a signal 115 representing the logic floating point register number specified by the instruction; a first conversion circuit 112 for converting the signal 115 into a physical floating point register number according to equations (6) to (10); a signal 116 representing the logical general register number specified by the instruction; and a second conversion circuit 114 for converting the signal 115 or 116 into a physical general register number according to equations (11) to (15). The signal 115 and signal 116 can carry a plurality of register numbers to permit execution of the instructions that specify a plurality of general register numbers or floating point register numbers. The data processor, as shown in Figs. 6A to 6H, is added with eight new instructions. These are shown in Fig. 6A as a current floating point window pointer change instruction, in Fig. 6B as a current general window pointer change instruction, in Fig. 6C as a floating point register preload instruction, in Fig. 6D as an extended floating point register preload instruction, in Fig. 6E as a floating point register poststore instruction, in Fig. 6F as a floating point register list load instruction, in Fig. 6G as a general register list load instruction, and in Fig. 6H as a floating point register list store instruction. The mnemonics and functions of these instructions have been described already. The current floating point window pointer change instruction is one to specify a current floating point window pointer. In Figure 6A, the instruction code indicates that the instruction is a current floating point window pointer change instruction. The general register number specifies a general register that contains the current floating point window pointer value to be set. The current general window pointer change instruction is one to specify a current general window pointer. In Figure 6B, the instruction code indicates that the instruction is a current general window pointer change instruction. The general register number specifies a general register that contains the current general window pointer value to be set. The floating point register preload instruction is one to read data from the main memory address specified by the general register belonging to the current window and store the main memory data into a floating point register belonging to a window of (current floating point window pointer + 1). In Figure 6C, the instruction code represents the floating point register preload instruction. The floating point register number represents a logical floating point register number ( r ). The corresponding physical floating point register in which the data is stored has a number < w +1, r > where w is a current floating point window pointer. The general register number represents a logical general register number ( rG ). The value of a physical general register < wG,rG >, where wG stands for the current general window pointer, represents a main memory address from which the data is to be read out. After the data is read out, the physical general register < wG,rG > is added with an increment value. The extended floating point register preload instruction is one to read data from the main memory specified by the general register belonging to the current window and store the main memory data into a floating point register belonging to a window of (current floating point window pointer + 2). In Figure 6D, the instruction code indicates that the instruction is an extended floating point register preload instruction. The floating point register number represents a logical floating point register number ( r ). The corresponding physical floating point register in which the data is to be stored has a number < w +2 ,r > where w is a current floating point window pointer. The general register number represents a logical general register number ( rG ). The value of a physical general register < wG,rG >, where wG stands for the current general window pointer, represents a main memory address from which the data is to be read out. After the data is read out, the physical general register < wG,rG > is added with an increment value. The floating point register poststore instruction is one to read data from a floating point register belonging to a window of (current floating point window pointer - 1) and store data into the main memory address specified by the general register belonging to the current window. In Figure 6E, the instruction code indicates that the instruction is a floating point register poststore instruction. The floating point register number represents a logic floating point register number ( r ). The corresponding physical floating point register from which the data is to be read out has a number < w +2 ,r > where w is a current floating point window pointer. The general register number represents a logical general register number ( rG ). The value of a physical general register < wG,rG >, where wG stands for the current general window pointer, represents a main memory address into which the data is to be stored. After the data is read out, the physical general register < wG,rG > is added with an increment value. The floating point list load instruction reads data from a main memory address specified by the general register belonging to a window of (current general window pointer + 1) and stores data into a floating point register belonging to a window of (current floating point window pointer + 1). In Figure 6F, the instruction code indicates that the instruction is a floating point register list load instruction. The floating point register number represents a logical floating point register number ( r ). The corresponding physical floating point register in which the data is to be stored has a number < w +1 ,r > where w is a current floating point window pointer. The general register number represents a logical general register number ( rG ). The value of a physical general register < wG +1 ,rG >, where wG stands for the current general window pointer, represents a main memory address from which the data is to be read out. The general register list load instruction stores data from a main memory address specified by a general register belonging to the current window into a general register belonging to a window of (current general window pointer + 2). In Figure 4G, the instruction code indicates that the instruction is a general register list load instruction. The general register number 1 represents a logical general register number ( rG1 ). The value of the physical general register < wG,rG1 >, where wG stands for the current general window pointer, indicates a main memory address from which the data is to be read out. The general register number 2 represents a logical general register number ( rG2 ). The number of a physical general register in which data is to be stored in < wG +2 ,rG2 >. After the data is read out, the physical general register < wG,rG1 > is added with an increment value. The floating point register list store instruction reads data from a floating point register belonging to a window of (current floating point window pointer - 1) and stores data into a main memory address specified by a general register belonging to a window of (current general window pointer - 1). In Figure 4H, the instruction code indicates that the instruction is a floating point register list store instruction. The floating point register number is a logical floating point register number ( r ). The physical floating point register from which the data is to be read out is numbered as < w -1 ,r > where w stands for the current floating point window pointer. The value of the physical general register < wG -1 ,r >, where wG stands for the current general window pointer, represents a main memory address in which the data is to be stored. The operation of these instructions is explained below by referring to Figure 5. First, let us explain about the current floating point window pointer change instruction. When an instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a current floating point window pointer change instruction, the general register specified by the instruction is read and the value of that register is set in the current floating point window pointer register 110 . Next, the current general window pointer change instruction will be described. When an instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a current general window pointer change instruction, the general register specified by the instruction is read and the value of that register is set in the current general window pointer register 113 . Next, the floating point register preload instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a floating point register preload instruction, the logical general register number ( rG ) specified by the instruction is transferred via the signal 116 to the second conversion circuit 114 where it is converted into a physical general register < wG,rG > where wG stands for the value of the current general window pointer register 113 . The address adder 107 takes in the content of the physical general register and puts it out as a main memory address from which to read data. The main memory access controller 109 searches through the cache 108 according to the main memory address. If there is desired data in the cache, the controller 109 transfers it from the cache and, when the data is not found, transfers data from the main memory 30 through the memory control unit 20 . The transferred data is stored in the floating point register 105 . The physical floating point register number in which the data is stored is determined by the first conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ) and is transferred via the signal 115 to the first conversion circuit 112 . The physical floating point register number is determined as < w +1 ,r > where w is the value of the current floating point window pointer register 110 . After the data transfer has started, the general calculator 104 adds an increment value to the value of the physical general register < wG,rG >. Next, the extended floating point register preload instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be an extended floating point register preload instruction, the logical general register number ( rG ) specified by the instruction is transferred via the signal 116 to the second conversion circuit 114 where it is converted into a physical general register < wG,rG > where wG stands for the value of the current general window pointer register 113 . The address adder 107 takes in the content of the physical general register and puts it out as a main memory address from which to read data. The main memory access controller 109 searches through the cache 108 according to the main memory address. If there is desired data in the cache, the controller 109 transfers it from the cache and, when the data is not found, transfers data from the main memory 30 through the memory control unit 20 . The transferred data is stored in the floating point register 105 . The physical floating point register number in which the data is stored is determined by the first conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ) and is transferred via the signal 115 to the first conversion circuit 112 . The physical floating point register number is determined as < w +2 ,r > where w is the value of the current floating point window pointer register 110 . After the data transfer has started, the general calculator 104 adds an increment value to the value of the physical general register < wG,rG >. Next, the floating point register poststore instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a floating point register poststore instruction, the logical general register number ( rG ) specified by the instruction is transferred via the signal 116 to the second conversion circuit 114 where it is converted into a physical general register < wG,rG > where wG stands for the value of the current general window pointer register 113 . The address adder 107 takes in the content of the physical general register and puts it out as a main memory address into which to store data. Data is read out from the floating point register 105 , and the physical floating point register number from which the data is to be read out is determined by the first conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ) and is transferred via the signal 115 to the first conversion circuit 112 . The physical floating point register number is determined as < w -1 ,r > where w is the value of the current floating point window pointer register 110 . The main memory access controller 109 searches through the cache 108 according to the main memory address. If the cache has a copy of data which is stored in the main memory address, the controller 109 replaces that data with the read data. When the data is not found in the cache, nothing is done about the cache. The main memory access controller 109 stores the read data into the main memory address via the memory control unit 20 . After the data transfer has started, the general calculator 104 adds an increment value to the value of the physical general register < wG,rG >. Next, the floating point register list load instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a floating point register list load instruction, the logical floating point register number ( r ) specified by the instruction is transferred via the signal 115 to the second conversion circuit 114 where it is converted into a physical general register < wG +1 ,r > where wG stands for the value of the current general window pointer register 113 . The address adder 107 takes in the content of the physical general register and puts it out as a main memory address from which to read data. The main memory access controller 109 searches through the cache 108 according to the main memory address. If there is desired data in the cache, the controller 109 transfers it from the cache and, when the data is not found, transfers data from the main memory 30 through the memory control unit 20 . The transferred data is stored in the floating point register 105 . The physical floating point register number in which the data is stored is determined by the first conversion circuit 112 as follows. The floating point register number specified by the instruction represents a logical floating point register number ( r ) and is transferred via the signal 115 to the first conversion circuit 112 . The physical floating point register number is determined as < w +1 ,r > where w is the value of the current floating point window pointer register 110 . Next, the general register list load instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a general register list load instruction, the logical general register number 1 ( rG1 ) or the first general register number specified by the instruction is transferred via the signal 116 to the second conversion circuit 114 where it is converted into a physical general register < wG,rG1 > where wG stands for the value of the current general window pointer register 113 . The address adder 107 takes in the content of the physical general register and puts it out as a main memory address from which to read data. The main memory access controller 109 searches through the cache 108 according to the main memory address. If there is desired data in the cache, the controller 109 transfers it from the cache and, when the data is not found, transfers data from the main memory 30 through the memory control unit 20 . The transferred data is stored in the general register 103 . The physical general register number in which the data is stored is determined by the second conversion circuit 114 as follows. The logical general register number 2 ( rG2 ) or the second general register number specified by the instruction is transferred via the signal 116 to the second conversion circuit 114 , where it is converted into a physical general register < wG +2 ,rG2 >. After the data transfer has started, the general calculator 104 adds an increment value to the value of the physical general register < wG,rG1 >. Next, the floating point register list store instruction is explained. When the instruction is taken into the instruction register 101 , the instruction is decoded by the instruction controller 102 . When the instruction is identified to be a floating point register list store instruction, data is read out from the floating point register 105 . The register number of the physical floating point register from which the data is read out is determined by the first conversion circuit 112 as follows. The floating point register number specified by the instruction is a logical floating point register number ( r ) and is transferred via the signal 115 to the first conversion circuit 112 where it is converted into a physical floating point register number < w -1 ,r > where w stands for the value of the current floating point window pointer register 110 . The logical floating point register number r is transferred via the signal 115 to the second conversion circuit 114 where it is converted into a physical general register number < wG -1 ,r >. The address adder 107 takes in the content of the physical general register and puts it out as a main memory address into which to store data from the physical floating point register. The main memory access controller 109 searches through the cache 108 according to the main memory address. If the cache has a copy of data which is stored in the main memory address, the controller 109 replaces that data with the read data. When the data is not found in the cache, nothing is done about the cache. The main memory access controller 109 stores the read data into the main memory address via the memory control unit 20 . In general floating point instructions (those using floating point registers, except for the floating point register preload instruction, extended floating point register preload instruction, floating point register poststore instruction, floating point register list load instruction, general register list load instruction and floating point register list store instruction), when the value of the current window pointer valid register 111 is "1," the logical floating point register number r specified by the instruction is converted by the first conversion logic 112 into a physical floating point register number, which is given by < w,r > where w is the value of the current floating point window pointer register 110 . Then, a reference is made to the physical floating point register represented by this derived physical floating point register number. When the current window pointer valid register 111 has a value "0," the logical floating point register number r specified by the instruction does not undergo conversion processing by the first conversion logic 112 . As a result a reference is made to the physical floating point register specified by the physical floating point register number r . In general instructions (those using general registers, except for the floating point register preload instruction, extended floating point register preload instruction, floating point register poststore instruction, floating point register list load instruction, general register list load instruction and floating point register list store instruction), when the value of the current window pointer valid register 111 is "1," the logical general register number rG specified in the instruction is converted by the second conversion logic 114 into a physical general register number, which is given by < wG,rG > where wG is the value of the current general window pointer register 113 . Then, a reference is made to the physical general register represented by this derived physical general register number. When the current window pointer valid register 111 has a value "0," the logical general register number rG specified by the instruction does not undergo conversion processing by the second conversion logic 114 . As a result a reference is made to the physical general register specified by the physical general register number rG . In the floating point register preload instruction, extended floating point register preload instruction, floating point register poststore instruction, floating point register list load instruction, general register list load instruction and floating point register list store instruction, when the value of the current window pointer valid register 111 is "1", the following conversions are performed as in the aforementioned instructions: conversion from the logical floating point register number into the physical floating point register number, conversion from the logical floating point register number into the physical general register number, and conversion from the logical general register number into the physical general register number. A reference is made to the physical floating point register or physical general register specified by the converted number. When the current window pointer valid register 111 has a value "0", the logical floating point register number is equal to the physical floating point register number in the conversion from the logical floating point register number into the physical floating point register number; the logical floating point register number is equal to the physical general register number in the conversion from the logical floating point register number into the physical general register number; and the logical general register number is equal to the physical general register number in the conversion from the logical general register number into the physical general register number. The current window pointer valid register 111 may be assigned an idle bit of an existing register that stores control information of the data processing system and the validity bit may be set by using an existing instruction for storing a value in the register. Described above is the way the following instructions work ― the current floating point window pointer change instruction, the current general window pointer change instruction, the floating point register preload instruction, the extended floating point register preload instruction, the floating point register post-store instruction, the floating point register list load instruction, the general register list load instruction, the floating point register list store instruction, and common floating point instructions and general instructions under the control of the current floating point window pointer and the current general window pointer. With the above embodiment, the programs shown in Figs. 14A, 14B, 15A, 15B, 16A, and 16B can be implemented increasing the speed of the list vector calculation. According to the method of this invention, the current floating point window pointer is changed to convert a floating point register number in an instruction into a different physical floating point register number, and the current general window pointer is changed to convert a floating point register number or general register number in the instruction into a different physical general register number, making it possible to access a greater number of physical registers than can be addressed by instructions, without changing the architecture of the data processor. This method realizes programs such as shown in Figs. 14A, 14B, 15A, 15B, 16A, and 16B preventing performance degradation which would otherwise be caused by the holding of instruction execution due to prolonged data reading or register conflicts. This in turn ensures a faster execution of programs. As can be seen from the programs of Figs. 14A, 14B, 15A, 15B, 16A, and 16B, in the list vector calculation ― a part of the vector calculation in scientific and engineering computation ― which mainly repeats executing the loop of instruction sequence, this invention changes the window to be used. In the source index type calculation, the i-th element is processed by the following steps: loading an i-th element of the list vector into a general register by the general register list load instruction in (i-2)-th loop; loading an element of the source vector (a vector to be read out) specified by the i-th element of the list vector into a floating point register ― which uses data in the general register as its main memory address ― by means of the floating point register list load instruction in the (i-1)-th loop; and storing data of the floating point register into an i-th element of the target vector (a vector to be written into) by means of a floating point register poststore instruction in the (i+1)-th loop. This series of operations increases the distances on the instruction string between the list vector loading, source vector loading and target vector storing operations on one element number, thereby eliminating performance degradation due to prolonged data read time and hence increasing the operation speed. In the target index type calculation, the i-th element is processed by the following steps: loading an i-th element of the list vector into a general register by the general register list load instruction in (i-2)-th loop; loading an i-th element of the source vector (a vector to be read out) into a floating point register by a floating point register preload instruction in (i-1)-th loop; and storing into an element of the target vector specified by the i-th element of the list vector the data in the floating point register ― which uses data in the general register as its main memory address ― by means of the floating point register list store instruction in (i+1)-th loop. This series of operations increases the distances on the instruction string between the list vector loading, source vector loading and target vector storing operations on one element number, thereby eliminating performance degradation due to prolonged data read time and hence increasing the operation speed. In the particle pusher type calculation, the i-th element is processed by the following steps: loading an i-th element of the list vector into a general register by the general register list load instruction in (i-2)-th loop; loading into a first floating point register an element of a first vector (i.e., vector A of equation (3)) specified by the i-th element of the list vector by means of the floating point register list load instruction in (i-1)-th loop; loading an i-th element of a second vector (i.e., vector B of equation (3)) into a second floating point register by means of the floating point register preload instruction; adding up the values of the two floating point registers (i.e., adding the element of the first vector specified by the i-th element of the list vector and the i-th element of the second vector) by means of the floating point addition instruction in i-th loop; and storing the result of addition into the element of the first vector specified by the i-th element of the list vector, the element using the value of the general register as its main memory address. This series of operations increases the distances on the instruction string between various operations on one element number, i.e., between the list vector loading, first vector loading, second vector loading (first and second vector loading are performed in one loop because they are not related with each other), addition of the first and second vectors' elements and storing of the addition result into the first vector, thereby eliminating performance degradation due to prolonged data read time and calculation execution time and hence increasing the operation speed. With this invention described in detail above, the current floating point window pointer is changed to convert a floating point register number in an instruction into a different physical floating point register number, and the current general window pointer is changed to convert a floating point register number or general register number in the instruction into a different physical general register number, making it possible to access a greater number of physical registers than can be addressed by instructions, without changing the architecture of the data processor. This method prevents performance degradation which would otherwise be caused by the holding of instruction execution due to prolonged data reading or register conflicts. This in turn ensures a faster execution of programs. Particularly in a vector calculation in scientific and engineering computation which mainly repeats executing the loop of instruction sequence, a different window is allocated to each loop, and the i-th element is processed by loading an i-th element of the operand vector specified by the floating point preload instruction during the (i-1)-th loop, executing the calculation in the i-th loop, and storing the result storage vector by the floating point poststore instruction performed in the (i+1)-th loop. This processing increases the distance on the instruction sequence between load, calculation, and store instructions on one data, eliminating performance degradation due to prolonged data read time and calculation execution time and increasing the operation speed. Furthermore, in list vector calculations in scientific and engineering computation which mainly repeats executing the loop of instruction sequence, such as a source index type calculation, target index type calculation, and particle pusher type calculation, a different window is allocated to each loop so that performance degradation due to prolonged data read time can be eliminated and the operation can be speeded up.

Claims: A data processor having main memory means (30) for storing instructions and data, and instruction processing means (10) for processing instructions by using main memory data stored in said main memory means, said data processor comprising: a plurality of physical registers (105) greater in number than can be addressed by instructions, said plurality of physical registers being divided into a plurality of partial groups, hereinafter called windows, and each of said plurality of physical registers being specified by a physical register number determined by a combination of the number of said window and a register number, hereinafter called a logical register number, in an instruction; at least one window pointer storing means (110, 113) for storing a window pointer indicating said window number; conversion means (112) for converting said logical register number into said physical register number by using said window pointer; a window pointer change instruction for changing said window pointer stored in said window pointer storing means; a register preload instruction for converting said logical register number into said physical register number and storing data from said main memory means in said physical register specified by said converted physical register number; and a register poststore instruction for converting said logical register number into said physical register number and storing data into said main memory means from said physical register specified by said converted physical register number, wherein converting said logical register number into said physical register number is achieved by using a window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means. A data processor according to claim 1, wherein two said window pointer storing means are provided (110, 113), one of two said window pointer storing means being used only by said register preload instruction and the other of two said window pointer storing means being used only by instructions other than said register preload instruction, the contents of two said window pointer storing means being changed at the same time by said window pointer change instruction. A data processor according to claim 1, wherein said different value to be used by said register preload instruction is a value obtained by adding a predetermined integer number to the value stored in said window pointer storing means. A data processor according to claim 1, further comprising a cache (108) for temporarily storing part of the contents of said main memory means (30), wherein in reading said main memory data by said register preload instruction, the contents of said cache are not changed if said main memory data has not been stored in said cache, and in storing data in said main memory means by said register poststore instruction, the contents of said cache are not changed if said main memory data at a corresponding address has not been stored in said cache. A data processor according to claim 1, wherein in converting said logical register number into said physical register number, at least one overlap register number is provided between a set of said physical register numbers convertible from said logical register number by one of said window pointers and a set of said physical register numbers convertible from said logical register number by another of said window pointers having a value different by 1 from the value of said one of said window pointers, at least one of said logical register numbers is converted into the same physical register number called a global register number irrespective of the value of said window pointer, and each of said physical register numbers except said overlap register number and said global register number is derived by using a corresponding one of said window pointers. A data processor according to claim 1, wherein said logical and physical registers addressed by said instruction are floating point registers for storing floating point number. A data processor according to claim 6, wherein said data processor is a vector data processor and further comprises a window pointer valid register (111) for indicating that said window pointer stored in said window pointer storing means is valid. A data processor according to claim 7, comprising: a plurality of physical general-purpose registers (103) greater in number than floating point registers addressable by instructions and greater in number than general-purpose registers addressable by instructions; a second window pointer storing means (113) for storing a second window pointer to be used for converting said logical register number or a general-purpose register number as a logical general-purpose register number in an instruction; a second conversion means (114) for converting said logical register number or a logical general-purpose register number into said physical general-purpose register number by using said second window pointer; and said window pointer valid register (111) for storing a value representing that said window pointer is valid and said second window pointer is valid. A data processor according to claim 8, wherein said instructions include: a second window pointer change instruction for changing said second window pointer; a floating point register preload instruction for reading vector data from said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number into said physical general-purpose register number by using said second window pointer, converting said logical register number into said physical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means (110), said different value being determined from said window pointer stored in said window pointer storing means, and storing said vector data in said physical register specified by said converted physical register number; and a floating point register poststore instruction for reading vector data from said physical register specified by said physical register number converted from said logical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means and for storing said vector data into said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number in said physical general-purpose register number by using said second window pointer. A data processor according to claim 9, wherein said instructions further include: a floating point register list load instruction for reading vector data from said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number by using a second window pointer having a different value from said second window pointer stored in said second window pointer storing means, said different value being determined from said second window pointer stored in said second window pointer storing means, and storing said vector data in said physical register specified by converting said logical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means; a general register list load instruction for reading vector data from said main memory means at a main memory address determined from information stored in said physical general-purpose register specified by converting a first said logical general-purpose register number by using said second window pointer, and storing said vector data in said physical general-purpose register specified by converting a second said logical general-purpose register number by using a second window pointer having a different value from said second window pointer stored in said second window pointer storing means, said different value being determined from said second window pointer stored in said second window pointer storing means; and a floating point register list store instruction for reading vector data from said physical register specified by converting said logical register number by using said window pointer having a different value from said window pointer stored in said window pointer storing means, said different value being determined from said window pointer stored in said window pointer storing means, and storing said vector data in said main memory means at a main memory address stored in said physical general-purpose register specified by converting said logical general-purpose register number by using a second window pointer having a different value from said second window pointer stored in said second window pointer storing means, said different value being determined from said second window pointer stored in said window pointer storing means. A vector processor according to claim 9, wherein said window pointer storing means is identical with said second window pointer storing means. A data processor according to claim 1, further comprising window pointer validity indicating means (111) for indicating that said window pointer stored in said window pointer storing means is valid.

Inventors: IMORI HIROMITSU, NAKAMURA HIROSHI, NAKAZAWA KISABURO, WADA HIDEO, IMORI, HIROMITSU, NAKAMURA, HIROSHI, NAKAZAWA, KISABURO, WADA, HIDEO
Applicants: HITACHI LTD, IMORI HIROMITSU, NAKAMURA HIROSHI, NAKAZAWA KISABURO, HITACHI, LTD., IMORI, HIROMITSU, NAKAMURA, HIROSHI, NAKAZAWA, KISABURO
Application year: 1992
Main classification: G06F9
IPC codes: G06F9, G06F17