Dynamic random access memory device with multiple word line selector used in burn-in test

Abstract: A dynamic random access memory device is subjected to a burn-in test operation prior to delivery from a factory, and is equipped with an auxiliary word line driving unit (5) so that all of the word lines (W1 to Wm) are simultaneously driven by the auxiliary word line driving unit in the burn-in test operation, thereby shrinking time period for the burn-in test operation.

Description: FIELD OF THE INVENTION This invention relates to a dynamic random access memory device and, more particularly, to a multiple word line selector incorporated in the dynamic random access memory device for a burn-in test on the memory cells. DESCRIPTION OF THE RELATED ART Upon completion of fabrication process for a dynamic random access memory device, the dynamic random access memory device is subjected to various test operations, and one of the test operations is known as "burn-in test". In the burn-in test, the dynamic random access memory device is placed in high temperature ambience, and the word lines are driven to active level after writing data bits in the memory cells. However, the prior art dynamic random access memory can simultaneously drive a single or a few word lines selected from all the word lines, and the burn-in test tends to be prolonged due to the sequential drive for the word lines. If 1024 word lines of the prior art dynamic random access memory device are sequentially driven to the active level from a word line to another word line, the prior art dynamic random access memory device needs to repeat the word line drive 1024 times, and long time period is consumed for the burn-in test. The dynamic random access memory device is continuously increasing the memory capacity, and, accordingly, the word lines incorporated therein are increased together with the memory cells. This means that the time period tends to be prolonged, and the cost for the diagnosis is increased together with the memory capacity. A memory device as set out in the preamble of claim 1 and in which all word lines can be driven simultaneously is known from EP-A-0 405 576. SUMMARY OF THE INVENTION It is an important object of the present invention to provide a dynamic random access memory device which can shrink time period for the diagnostic operation. To accomplish the object, the present invention proposes to simultaneously drive all of the word lines with one of the signal pins, as set out in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the dynamic random access memory device according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram showing the circuit arrangement of a dynamic random access memory device according to the present invention; Fig. 2 is a circuit diagram showing the circuit arrangement of another dynamic random access memory device according to the present invention; and Fig. 3 is a diagram showing the waveforms of clock signals applied to the dynamic random access memory device shown in Fig. 2. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring first to Fig. 1 of the drawings, a dynamic random access memory device embodying the present invention is fabricated on a single semiconductor chip 1, and comprises a memory cell array 2 implemented by a plurality of memory cells M11, M1n, M21, M2n, Mm1 and Mmn arranged in rows and columns. Though not shown in the drawings, each of the memory cells M11 to Mmn is implemented by a series combination of an n-channel enhancement type switching transistor and a storage capacitor. Word lines W1, W2, W3 and Wm are respectively coupled with the memory cells M11 to Mmn in the rows of the memory cell array 2, and bit line pairs BL1 to BLn are respectively coupled with the memory cells in the columns of the memory cell array 2 for propagating data bits to associated sense amplifier circuits SA1 to SAn. A row address decoder and driver unit 3 is associated with the word lines W1 to Wm, and drives one of the word lines W1 to Wm indicated by row address bits. Though not shown in Fig. 1, a column selector is coupled between the sense amplifier circuits SA1 to SAn and a data pin, and a column address decoder unit 4 allows one of the bit line pairs BL1 to BLn indicated by column address bits to couple through the column selector with the data pin. The dynamic random access memory device shown in Fig. 1 further comprises an auxiliary word line driver unit 5 coupled with the word lines W1 to Wm, and the auxiliary word line driver unit 5 is provided on the opposite side to the row address decoder and driver unit 3. The auxiliary word line driver 5 is implemented by a plurality of p-channel enhancement type switching transistors Q1, Q2, Q3 and Qm, and the drain nodes of the p-channel enhancement type switching transistors Q1 to Qm are respectively coupled with the word lines W1 to Wm. The source nodes of the p-channel enhancement type switching transistors Q1 to Qm are commonly coupled with a predetermined pin 6, and the predetermined pin 6 is coupled through a step-down circuit 7 with the gate electrodes of the p-channel enhancement type switching transistors Q1 to Qm. The step-down circuit 7 is implemented by a series combination of p-channel enhancement type load transistors Q11, Q12 and Q13, and decreases a voltage level at the predetermined pin 6. When the dynamic random access memory device is installed in an electronic system, data bits are written into or read out from the memory cells M11 to Mmn indicated by the row and column address bits, and the row address decoder and driver unit 3 lifts one of the word lines W1 to Wm to an active level. Memory cells coupled with the activated word line are coupled with the bit line pairs BL1 to BLn, and data bits are transferred therebetween. However, the dynamic random access memory device is subjected to various test operations prior to delivery from the manufacturing factory. The burn-in test operation is carried out for the dynamic random access memory device for screening a defective product with breakable memory cells, and the burn-in test traces the following sequence. First, data bit of logic "0" is written into all of the memory cells M11 to Mmn, and a plurality of clock pulses are supplied to the predetermined pin 6. Each clock pulse is distributed from the predetermined pin 6 to the source nodes of the p-channel enhancement type switching transistors Q1 to Qm, and the step-down circuit 7 supplies the gate electrodes a voltage level lower than the source nodes by the threshold level of the switching transistors Q1 to Qm. Then, the p-channel enhancement type switching transistors Q1 to Qm simultaneously turn on in the presence of every clock pulse, and the clock pulses are transferred to all of the word lines W1 to Wm. With the clock pulses, the gate oxide films of the n-channel enhancement type switching transistors are stressed. Next, data bit of logic "1" level is written into all of the memory cells M11 to Mmn, and a plurality of clock pulses are applied to a pin. The data write-in and the application of stress are repeated predetermined times, and the manufacturer diagnoses the memory cells M11 to Mmn. Thus, the clock pulses are simultaneously applied to all of the word lines W1 to Wm in the burn-in test operation, and the burn-in test operation is completed within short time period rather than the prior art dynamic random access memory device. Second Embodiment Turning to Fig. 2 of the drawings, another dynamic random access memory device embodying the present invention is fabricated on a single semiconductor chip 21. The dynamic random access memory device shown in Fig. 2 is similar in circuit arrangement to the first embodiment except for some additional circuits, and components are labeled with the same references as the corresponding components of the dynamic random access memory device shown in Fig. 1 without description. In this instance, an external row address strobe signal RAS is applied to the first predetermined pin 6 in the standard mode of operation having a write-in phase and a read-out phase, and a first clock signal CLK1 is supplied to the first predetermined pin 6 in the diagnostic mode of operation. For this reason, the first predetermined pin 6 is coupled in parallel with the auxiliary word line driving unit 5 and an internal row address strobe generator 22. The dynamic random access memory device implementing the second embodiment further comprises a switching circuit 23 which is implemented by a plurality of pairs of n-channel enhancement type switching transistors Q21, Q22, Q23, Q24, Q25 and Q26. The pairs of n-channel enhancement type switching transistors Q21 to Q26 are respectively coupled with the bit line pairs BL1, BL2 and BLn and a ground voltage line serving as a source of logic "0" level. The gate electrodes of the n-channel enhancement type switching transistors Q21, Q23 and Q25 are coupled with a second predetermined pin 24, and the other n-channel enhancement type switching transistors Q22, Q24 and Q26 are coupled at the gate electrodes thereof with a third predetermined pin 25. Second and third clock signals CLK2 and CLK3 are respectively supplied to the second and third predetermined pins 24 and 25 in synchronism with the first clock signal CLK1 as shown in Fig, 3. The circuit behavior in the standard mode of operation is similar to that of the first embodiment, and no further description is incorporated hereinbelow for avoiding repetition. Assuming now that the dynamic random access memory device shown in Fig. 2 enters the burn-in test operation in the diagnostic mode. The burn-in test starts without write-in of a data bit into all of the memory cells M11, M12, M1n, M21, M22, M2n, M31, M32, M3n, Mm1, Mm2 and Mmn, and the first clock signal CLK1 is supplied to the first predetermined pin 6. The first clock signal CLK1 allows the auxiliary word line driving unit 5 to lift all of the word lines W1 to Wm to the active level at time t1, and the second clock signal CLK2 rises together with the first clock signal CLK1 so that the n-channel enhancement type switching transistors Q21, Q23 and Q25 discharges the associated bit lines, thereby supplying logic "0" to these bit lines. The first and second clock signals CLK1 and CLK2 are recovered to the low voltage level at time t2, and the first and third clock signals CLK1 and CLK3 are lifted to the high voltage level at time t3. The n-channel enhancement type switching transistors Q22, Q24 and Q26 turn on so as to discharge the associated bit lines, and the first and third clock signals CLK1 and CLK3 are recovered at time t4. Thus, the switching circuit 23 alternately supplies logic "1" level to half of the bit lines, and stress is applied to all of the memory cells M11 to Mmn without any write-in operation. As will be understood from the foregoing description, the auxiliary word line driving unit of the dynamic random access memory device according to the present invention simultaneously drives all of the word lines W1 to Wm, and the burn-in test operation is completed within short time period. This results in reduction of production cost of the dynamic random access memory device. Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention.

Claims: A dynamic random access memory device fabricated on a single semiconductor chip (1; 21) and having a standard mode and a diagnostic mode of operation, comprising: a) a plurality of memory cells (M11 to Mmn); b) a plurality of bit lines (BL1 to BLn) respectively coupled with the columns of said plurality of memory cells for propagating data bits; c) a plurality of word lines (W1 to Wm) respectively coupled with the rows of said plurality of memory cells, and selectively driven to an active level for allowing said data bits to be transferred between said plurality of bit lines and one of said memory cells in said standard mode of operation; and d) an auxiliary word line driving unit (5) comprising a first predetermined pin (6) applied with a first external clock signal (CLK1) characterized in that said auxiliary word line driving unit (5) further comprises d-1) a plurality of p-channel enhancement type switching transistors (Q1/Q2/Qm) coupled between said plurality of word lines and said first predetermined pin (6), and d-2) a plurality of p-channel enhancement type transistors (Q11 to Q13) coupled in series between said first predetermined pin (6) and gate electrodes of said plurality of p-channel enhancement type switching transistors (Q1-to Qm) and having respective gate electrode coupled to source nodes thereof so as to allow said plurality of switching transistors (Q1 to Qm) to concurrently turn on in the presence of said first external clock signal (CLK1), and wherein e) said plurality of memory cells CM11 to Mmn) are arranged in rows and columns and f) said plurality of bit lines CBL1 to BLn) comprise a plurality of bit line pairs. A dynamic random access memory device as set forth in claim 1, in which a voltage control circuit (7) is provided in association with said auxiliary word line driving unit (5) for producing a gate voltage from said first external clock signal, said gate voltage being supplied to gate electrodes of said plurality of switching transistors (Q1, Q2, Qm) so as to allow said plurality of switching transistors to concurrently turn on. A dynamic random access memory device as set forth in claim 1, in which said dynamic random access memory device further comprises e) a switching circuit (23) coupled between said plurality of bit line pairs and a source of first logic level, and responsive to second and third external clock signals (CLK2/CLK3) alternately lifted to an active level in synchronism with said first external clock signal (CLK1) for alternately supplying said first logic level to component bit lines of said plurality of bit line pairs. A dynamic random access memory device as set forth in claim 3, in which said switching circuit (23) comprises e-1) a plurality of first switching transistors (Q21/Q23/Q25) each coupled between said source of first logic level and one of the component bit lines of each bit line pair, and responsive to said one of said second and third external clock signals, and e-2) a plurality of second switching transistors (Q22/Q24/Q26) each coupled between said source of first logic level and the other of the component bit lines of said each bit line pair, and responsive to the other of said second and third external clock clock signals.

Inventors: FUJITA MITSUOKI, FUJITA, MITSUOKI, Fujita, Mitsuoki, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G11C29
IPC codes: H01L21, H01L27, G11C29, G01R31, G11C11