Timing recovering apparatus

Abstract: A timing recovering apparatus comprises an equalizer for equalizing a digital data signal subjected to interleaved NRZI such that the digital data signal has partial response (1, 0, -1), two comparators for comparing the equalized data signal with two different reference levels, two phase comparing portions for detecting phase difference between the outputs of the comparators and a reproduced clock signal separately, an adder for summing the outputs of the phase comparators, and a VCO for generating the reproduce clock signal in accordance with the output of the adder. This timing recovering apparatus performs phase comparing with two different phase comparators and PLL control is performed sum of the output of the two different phase comparators, so that the clock signal is not affected by data pattern of the data signal. An automatic slice apparatus comprises the equalizer for equalizing a digital data signal subjected to interleaved NRZI, and two comparators supplied with reference levels, and the timing recovering apparatus, detects amplitude of the output of the equalizer in response to the reproduced clock signal to compensate the reference levels.

Description: This invention relates to a timing recovering apparatus for recovering timing of received data signal, and particularly relates to a timing recovering apparatus used in a digital magnetic reproducing apparatus for reproducing a video signal or a sound signal. A timing recovering apparatus for recovering timing of received data signal used in a digital magnetic reproducing apparatus for reproducing a video signal or a sound signal after a/d conversion is known. Such timing recovering apparatus is used for recovering timing of interleaved NRZI (I-NRZI) coded digital data signal. In the timing recovering apparatus, the reproduced or transmitted interleaved NRZI coded digital data signal is supplied to an equalizer circuit for frequency-compensating to produce a data signal having partial response waveform, hereinafter referred to as PR (1, 0,-1). The equalized data signal shows three-valued eye pattern, that is, it shows three levels (1, 0, and -1), that is, it is represented by three-valued notation. The equalized data signal is compared with two different reference levels by comparators. A logic circuit detects change in logic level of outputs of the comparators and a clock generation circuit produces a reproduced clock signal with timing of the receive data signal recovered. An automatic slice apparatus for detecting the data signal by comparing the data signal with reference levels controlled in accordance with a magnitude of the output of the equalizer is known. It is used in a digital magnetic recording apparatus and a digital magnetic reproducing apparatus. Such automatic slice apparatus detects the received digital data signal by comparing such that the reference level is controlled to the center level of the eye pattern of the received data signal to effect accurate comparison. Such comparison reduces fluctuation in amplitude of received digital data signal. Such fluctuation may be developed at a magnetic head for reading a recorded data signal. Such automatic slice apparatus can used together with the timing recovering circuit mentioned above. In this case, the automatic slice circuit generates two different reference levels to comparing the equalized data signal having partial response waveform. Fig. 6 is a block diagram of a prior art timing recovering apparatus having a prior art automatic slice circuit. Figs. 7A to 7F show waveforms for explaining a prior art timing recovering apparatus. A digital data signal reproduced from a magnetic recording medium 31 by a magnetic head 32 is applied to an equalizing circuit 33 for frequency-compensating the received data signal to produce a data signal having partial response (PR) waveform. The equalized data signal shows three-valued eye pattern. The equalized data signal is compared by comparing circuits 34 and 35. Comparing circuits 34 and 35 have different reference levels C1 and C2 shown in Fig. 7A to discriminate the equalized data signal into three level ranges with their binary outputs. The comparing circuit 35 having the reference level C2 outputs an inverted output such that a level of -1 is output as 1. The binary outputs from the comparator 34 and 35 are input to an Exclusive OR circuit 36 for effecting Exclusive OR operation. A clock signal generation circuit 37 for detecting bit phase, comprising: a tank circuit 38, multiplier 39, low-pass filter (LPF) 40, and a voltage controlled oscillator (VCO) 41. In response to edge portions of the binary output of the Exclusive OR 36, the tank circuit 38 generates a clock signal whose frequency corresponds to the reproduced clock signal of the timing recovering circuit. The output signal of the tank circuit 38 is applied to a phase locked loop (PLL) circuit including the multiplier 39, low-pass filter 40 and the voltage controlled oscillator 41. Therefore, the phase locked loop circuit outputs the clock signal with timing recovered from the received digital data signal. In this prior art timing recovering circuit, a phase of the output of the tank circuit 38 may change in accordance with pattern of data. Fig. 7A shows eye pattern of the output of the equalizer 36, the eye pattern being to be discriminated into three values. In Fig. 7A, the output of the equalizer 36 is normally discriminated at timings A0, B0, C0, and D0 with the same possibility substantially, so that the the tank circuit 38 generates a sine signal as shown in Fig. 7B with phases of respective waves of the sine signal (ω o t) averaged. However, when the data signal indicative of a specific data pattern, that is, a waveform W1 represented by (1, 0, -1, 0, 1) of three-valued notation, is input repeatedly to the prior art timing recovering circuit, the output of the Exclusive OR circuit 36 outputs a signal shown in Fig. 7E because the output of the comparing circuit 34 shows a waveform shown in Fig. 7C and the output of the comparing circuit 35 shows a waveform shown in Fig. 7D. Accordingly, the tank circuit 38 would output a signal represented by waveform W5 in response to falling edges of the output of the Exclusive OR circuit 36. On the other hand, the tank circuit 38 would output a signal represented by waveform W6 in response to rising edges of the output of the Exclusive OR circuit 36. In fact, due to averaging, the tank circuit 38 outputs a signal represented by a waveform W4, that is, a signal of sin (ω o t+ π /2). This signal represented by the waveform W4 is different in phase by π /2 from the waveform shown in Fig. 7B, so that bit slip occurs. That is, bias of data pattern causes phase shift of the reproduced clock signal, so that there is a problem that bit synchronizing cannot be obtained accurately by this prior art timing recovering circuit. In Fig. 6, an automatic slice circuit 42 controls a reference level for the comparing circuits 34 and 35 in accordance with a detected amplitude of the output of the equalizer 33. The output of the equalizer 33 is applied to a squaring circuit 43 for detecting an absolute amplitude of the output of the equalizer 33 which is sent to a low-pass filter 44 for removing high frequency component to produce the reference level. The reference level is sent to a reference signal generation circuit 28 for generating the reference levels C1 and C2 for the comparing circuits 34 and 35. Comparing circuits 34 and 35 discriminate the received data signal into three-valued notation from the reference level. This automatic slice circuit 42 causes the comparing circuits 34 and 35 to discriminating the received data signal into three-valued notation with variation in amplitude of the output of the equalizer 33 caused by the magnetic head 32. However, because the pass band of the received data signal is limited to obtain partial response (1, 0, -1) in this system, bias of data pattern causes variation in amplitude at the output of the equalizer 33. For example, a data pattern represented by a waveform W2 indicated by three-value notation (1, 1, -1, -1) shown in Fig. 7A shows such variation. Therefore, there is a problem that the reference level for comparing is inaccurate due to bias of data pattern of the received data signal in this prior art automatic slice circuit 42. Moreover, there is a further problem that such prior art automatic slice circuit 42 is adversely affected by external noises because such prior art automatic slice circuit has an open-loop structure, or feedforward structure. Furthermore, document EP-A-0 365 257 discloses a phase correcting clock circuit for accurately recovering binary data. To be precise, in this prior art arrangement an analog signal which has been read from a magnetic track and which is equalized and gain controlled is applied to threshold detecting means. Then the signals output by the threshold detecting means are fed to edge detectors, respectively, outputting a pulse whenever the fed signal undergoes an edge transition. Next, the pulse signals are supplied to phase detectors, respectively, detecting a phase error. This phase error is supplied to current source charge pump means providing output currents which are a function of the magnitude of the phase error signals output by the phase detectors, respectively. The phase error current signal output by the current source charge pump means is applied to loop filter means averaging or integrating the phase error information over a significant time period. The present invention has been developed in order to remove the above-described drawbacks inherent to the conventional timing recovering apparatus. According to the present invention this object is accomplished by a timing recovering apparatus as defined in claim 1. The object and features of the present invention will become more readily apparent from the following detailed description taken in conjunction with the accompanying drawings in which: Fig. 1 is a block diagram of an explanatory example of this invention of timing recovering circuit; Figs. 2A to 2F shows waveforms at respect points of the timing recovering circuit shown in Fig. 1; Fig. 3 is a block diagram of an embodiment of this invention ; Fig. 4 is a block diagram of an example of an automatic slice circuit; Figs. 5A to 5F show waveforms of outputs at respective points shown in Fig. 4; Fig. 6 is a block diagram of a prior art timing recovering apparatus having a prior art automatic slice circuit; and Figs. 7A to 7F show waveforms for explaining a prior art timing recovering apparatus; The same or corresponding elements or parts are designated as like references throughout the drawings. Hereinbelow will be described an explanatory example of this invention. Fig. 1 is a block diagram of an explanatory example of this invention of timing recovering circuit. Figs. 2A to 2F shows waveforms at respect points of the timing recovering circuit shown in Fig. 1. A video signal and a sound signal is recorded on the magnetic recording medium 1 after a/d conversion and I-NRZI (interleaved nonreturn to zero inversion). A data signal reproduced from the magnetic recording medium 1 by a magnetic head 2 is applied to an equalizing circuit 3 comprising an AGC circuit 4 and equalizer 5. The reproduced data signal is input to the AGC circuit 4 for amplifying the reproduced data signal with automatic gain controlled. An output of the AGC circuit 4 is supplied to equalizer 5 for frequency-compensating the received data signal to produce a data signal having partial response waveform, PR (1, 0, -1). The equalized data signal shows three-valued eye pattern as shown in Fig. 2A. The equalized data signal is compared by comparator 6 and 7. Comparators 6 and 7 are supplied with different reference levels C1 and C2 respectively as shown in Fig. 2A to discriminate the equalized data signal into three level ranges with their two binary outputs. The comparator 7 supplied with the reference level C2 outputs an inverted output such that a level of -1 is output as 1. The binary output of the comparator 6 is input to a clock shaping circuits 9 of a clock signal generation circuit 8a. The binary output of the comparator 7 is input to a clock shaping circuit 10. The clock shaping circuit 9 comprises an Exclusive-OR circuit 12 responsive to the binary output of the comparator 6 and a delay circuit 11 for delaying the binary output by a half of a period T of clock signal, i.e., (T/2), to supply the delayed binary signal to the another input of the Exclusive OR circuit 12. The clock shaping circuit 10 has the same structure as the clock shaping circuit 9. That is, the clock shaping circuit 10 comprises an Exclusive-OR circuit 14 responsive to the binary output of the comparator 7 and delay circuit 13 for delaying the binary output by a half of a period T of clock signal, i.e., (T/2), to supply the delayed binary signal to the another input of the Exclusive OR circuit 13. The Exclusive OR circuit 12 effects Exclusive-OR operation between the binary output of the comparator 6 and the delayed binary output form the delayed circuit 11 in order to shaping of the binary output to enable phase comparing by the PLL (phase locked loop) circuit of the next stage. Similarly, the Exclusive OR circuit 14 effects Exclusive-OR operation between the binary output of the comparator 7 and the delayed binary output form the delay circuit 13. An output of the clock shaping circuit 9 is applied to a phase comparator 15 for comparing the output of the clock shaping circuit 9 with an output of voltage controlled oscillator (VCO) 19, that is, the reproduced clock signal. An output of the clock shaping circuit 10 is applied to a phase comparator 16 for comparing the output of the clock shaping circuit 10 with the reproduced clock signal. An output of the phase comparator 15 is added to an output of the phase comparator 16 by an adder 17. An output of the adder is sent to the voltage controlled oscillator 19 through a low-pass filter 18 with high frequency component removed. That is, the phase comparators 15 and 16, the adder 17, the low-pass filter 18, and the voltage controlled oscillator 19 form a phase locked loop responsive to binary outputs from the comparators 6 and 7 for generating a clock signal whose timing recovered. Hereinbelow will described operation of the timing recovering circuit of this explanatory example with reference to Figs. 2A to 2F. Fig. 2A shows waveforms of the output of the equalizing circuit 3 in the form of eye pattern to be discriminated into three-valued notation, where "1" and "-1" denote amplitudes-at synchronized clock timings and references C1 and C2 denote the reference levels of the comparators 6 and 7 respectively. Figs. 2B to 2F show waveforms of outputs at respective points in the clock signal generation circuit 8 when the received data signal including data pattern shown by a waveform W3 represented by three-valued notation (1, 1, -1, 0). Therefore, the binary output of the comparator 6 shows an waveform shown in Fig. 2C and the binary output of the comparator 7 shows an waveform shown in Fig. 2D wherein the comparator 7 supplied with the reference level C2 outputs an inverted output such that a level of -1 is output as 1. The binary outputs of the comparators 6 and 7 are shaped by the clock shaping circuits 9 and 10 respectively. Therefore, the output of the clock shaping circuit 9 shows a waveform shown in Fig. 2E and the output of the clock shaping circuit 10 shows a waveform shown in Fig. 2F. There is a relation between the clock signal output from the voltage controlled oscillator 19 and the binary outputs of the comparators 6 and 7 is such that one edge of the binary signals of the comparators 6 and 7 corresponds to one period of the clock signal shown in Fig. 2B. Therefore, PLL control can be obtained from the output of the VCO 19. The phase comparators 15 and 16 comprise Exclusive OR circuits. The adder 17 adds the output of the phase comparator 15 to the output of the phase comparator 16 through analog processing. The added phase signal from the adder 17 is filtered by the low-pass filter 18. The VCO 19 oscillates in accordance with the output of the low-pass filter 18 and outputs the clock signal with timing of the received data signal recovered. Because the equalizing circuit 3 effects frequency compensation to obtain partial response (1, 0, -1), both cross points A0 and D0 or both cross points B0 and C0 in the three-valued eye pattern always exist in any data pattern of the received data signal and phase difference between these cross points. Moreover, the clock signal is the same and if either cross point of a pair of cross points A0 and D0 of B0 and C0 shows lead, the other cross point of the pair shows lag of the same amount. Therefore, this phase relation is averaged by the adder 17 summing the outputs of the phase comparators 15 and 16. More specifically, comparing the waveforms in Fig. 2B with Figs. 2E and 2F, phase difference between rising edges in Fig. 2B and rising edges in Fig. 2E agrees with that between rising edges in Fig. 2B and rising edges in Fig. 2F but polarities of these phase differences have an inverted relation. Therefore, the averaging of these phase differences provides accurate phase control to the phase locked loop, so that the VCO 19 generates the lock signal accurately. Moreover, when the reproduced data signal from the magnetic head 2 varies in magnitude, cross points A0 and D0 or cross points B0 and C0 deviate because the reference levels C1 and C2 are constant in this timing recovering circuit. However, relations between the cross points A0 and D0 or B0 and C0 are constant, so that the averaging of phase differences detected by the phase comparators 15 and 16 removes the variation of magnitude of the reproduced data signal. Fig. 3 is a block diagram of an embodiment of the invention. In the clock shaping circuits 9 and 10 of the embodiment, the binary output form the comparator 6 and 7 are shaped by the Exclusive OR circuit 12 and 14. However, in this modified embodiment, shaping is effected by analog multipliers 61 and 62 of clock shaping circuits 9' and 10'in a clock signal generation circuit 8b. The output of the analog multiplier 61 is add to the output of the analog multiplier 62 linearly by the adder 17. Feedback of a PLL circuit 64 is executed by an analog multiplier 63 for multiplying the output of the adder 17 with the output of the VCO 19 to form phase locked loop. This structure also provides the same function as that of the explanatory example. Hereinbelow will be described an automatic slice apparatus with reference to drawings. Fig. 4 is a block diagram of the example of an automatic slice circuit where the same elements are designated as the same references as Fig. 1. A video signal and a sound signal is recorded on the magnetic recording medium 1 after a/d conversion and I-NRZI. A data signal reproduced from the magnetic recording medium 1 by a magnetic head 2 is an equalizing circuit 3 comprising an AGC circuit 34 and equalizer 5. The reproduced data signal is inputted to the AGC circuit 34 for amplifying the reproduced data signal with automatic gain controlled. An output of the AGC circuit 34 is supplied to equalizer 5 for frequency-compensating the received data signal to produce a data signal having partial response waveform, PR (1, 0, -1). The equalized data signal shows three-valued eye pattern. The equalized data signal is compared by comparators 26 and 27. The comparators 26 and 27 discriminate the equalized data signal into three level ranges with their two binary outputs. The comparator 7 outputs an inverted output such that a level of -1 is output as 1. The binary outputs of the comparing circuits 6 and 7 are input to a clock signal generation circuit 8 which correspond to or the same as the clock signal generation circuit 8a or 8b described in the explanatory example. The clock signal generation circuit 8 outputs a clock signal with timing of the received data signal recovered. Data sampling circuit 20 samples the binary signal from the comparator 26 in response to the clock signal from the clock signal generation circuit 8. Data sampling circuit 21 samples the binary signal from the comparator 7 in response to the clock signal from the clock signal generation circuit 8. Figs. 5A to 5F show waveforms of outputs at respective points of this embodiment when the received data signal including data pattern shown by a waveform W3 represented by three-valued notation (1, 1, -1, 0). Therefore, the binary output of the comparator 26 shows an waveform shown in Fig. 5C when the comparator 26 compares the output of the equalizing circuit 3 with the reference level C3. The binary output of the comparator 27 shows.an waveform shown in Fig. 5D when the comparing circuit 27 is supplied with the reference level C4. The comparator 27 outputs an inverted output such that a level of -1 is output as 1. The data sampling circuits 20 and 21 sample the binary outputs of the comparators 26 and 27 at rising edges of the clock signal shown in Fig. 5B, so that they output signals showing waveforms shown in Figs. 2E and 2F respectively. Outputs of the data sampling circuits 20 and 21 are sent to a subtractor 22 for subtracting the output of the data sampling circuit 20 from the output of the data sampling circuit 21 as shown in Fig. 5G. A waveform of Fig. 2G is indicative of both bit synchronizing timing and polarity of three-valued data signal shown in Fig. 2A. An output of the subtractor 22 is sent to a multiplier 23. The multiplier 23 multiplies the output of the subtractor 22 by the output of the equalizing circuit 3. Therefore, the multiplier 23 detects level of the reproduced data signal at the bit synchronizing timing. This means that the level of the reproduced data signal is constant irrespective of data pattern of the reproduce data signal because the output of the equalizing circuit having partial response (1, 0, -1) except that the level of the reproduced data signal varies. In other words, the multiplier 23 can detect variation in amplitude of the reproduced data signal accurately. A low-pass filter 24 extracts amplitude variation components from the output of the multiplier 23. An output of the low-pass filter 24 is sent to the AGC circuit 34 to compensate the amplitude of the received data signal by feedback control. Therefore, the variation of the reproduced data signal is largely compensated and remaining variation is detected by the low-pass filters 24 and 25. Therefore, the low-pass filter 25 detects the remaining variation. The detected variation is fed to a reference signal generation circuit 29 for generating the reference level C3 and C4 in accordance with the detected variation, that is, the output to the low-pass filter 25. The reference levels C3 and C4 controlled by the detected variation are sent to the comparators 26 and 27 respectively. The comparator 26 compares the output of the equalizing circuit 3 with the reference level C3. The comparator 27 compares the output of the equalizing circuit 3 with the reference level C4. This compensation of the variation of the data signal is feedfoward control. Therefore, the this control can respond the variation quickly, so that the remaining variation in the amplitude of the data signal can be compensated considerably. Moreover, a large part of variation in amplitude of the data signal is compensated by the AGC 34, so that it is not necessary to assign a large dynamic range to the reference levels C3 and C4 of the comparators 26 and 27 and thus, this cause the comparators 26 and 27 to withstand external noises. Moreover, the clock generation circuit 8 can generate the clock signal indicative of bit synchronizing without affection of the variation of amplitude of the data signal. Therefore, the clock generation circuit 8 and the automatic slice circuit can be treated as independent loop. Further, in Fig. 4, the low-pass filter 24 and 25 are provided separately. However, only one low-pass filter can provide the detection of variation in amplitude of the data signal. A timing recovering apparatus comprises an equalizer for equalizing a digital data signal subjected to interleaved NRZI such that the digital data signal has partial response (1, 0, -1), two comparators for comparing the equalized data signal with two different reference levels, two phase comparing portions for detecting phase difference between the outputs of the comparators and a reproduced clock signal separately, an adder for summing the outputs of the phase comparators, and a VCO for generating the reproduce clock signal in accordance with the output of the adder. This timing recovering apparatus performs phase comparing with two different phase comparators and PLL control is performed sum of the output of the two different phase comparators, so that the clock signal is not affected by data pattern of the data signal. An automatic slice apparatus comprises the equalizer for equalizing a digital data signal subjected to interleaved NRZI, and two comparators supplied with reference levels, and the timing recovering apparatus, detects amplitude of the output of the equalizer in response to the reproduced clock signal to compensate the reference levels.

Claims: A timing recovering apparatus comprising: equalizing means (5) for equalizing a digital data signal such that said digital data signal has partial response (1, 0, -1); first and second comparing means (6, 7) for comparing an output of said equalizing means (5) with first and second reference levels, respectively, said first and second reference levels being different from each other; low pass filter means (18); and oscillation means (19) for generating a reproduced clock signal with frequency thereof controlled in accordance with an output of said low-pass filter means (18), characterized by first and second clock signal shaping means (9', 10') for shaping outputs of said first and second comparing means (6, 7), respectively; adding means (17) for linearly adding an output of said first clock signal shaping means (9') to an output of said second clock signal shaping means (10'); and phase comparing means (63) comprising an analog multiplier for detecting phase difference between said reproduced clock signal and an output of said adding means (17), wherein an output of said phase comparing means (63) is filtered by said low-pass filter means (18). A timing recovering apparatus as claimed in claim 1, characterized in that said first clock signal shaping means (9') comprises delay means (11) for delaying said output of said first comparing means (6) by half of a period of a clock signal of said data signal to be reproduced and an analog multiplier (61) for multiplying said output of said first comparing means (6) and an output of said delay means (11). A timing recovering apparatus as claimed in claim 1, characterized in that said second clock signal shaping means (10') comprises delay means (13) for delaying said output of said second comparing means (7) by half of a period of a clock signal of said data signal to be reproduced and an analog multiplier (62) for multiplying said output of said second comparing means (7) and an output of said delay means (13). A timing recovering apparatus as claimed in claim 1, characterized in that said first clock signal shaping means (9') comprises delay means (11) for delaying said output of said first comparing means (6) by half of a period of a clock signal of said data signal to be reproduced and Exclusive-OR operation means (12) for Exclusive-OR operating between said output of said first comparing means (6) and an output of said delay means (11). A timing recovering apparatus as claimed in claim 1, characterized in that said second clock signal shaping means (10') comprises delay means (13) for delaying said output of said second comparing means (7) by half of a period of a clock signal of said data signal to be reproduced and Exclusive-OR operation means (14) for Exclusive-OR operating between said output of said second comparing means (7) and an output of said delay means (13).

Inventors: HASHIMOTO KIYOKAZU, HAYASHI KOICHI, HIGASHIDA YOSHIO, SHIMOTASHIRO MASAFUMI, HASHIMOTO, KIYOKAZU, HAYASHI, KOICHI, HIGASHIDA, YOSHIO, SHIMOTASHIRO, MASAFUMI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: H04L7
IPC codes: G11B20