Memory card apparatus

Abstract: This invention is associated with a memory card apparatus using EEPROMs (17, 18, 19) as semiconductor memories. Externally input data are temporarily recorded in a buffer memory (13) and are subsequently written in the EEPROMs (17, 18, 19). Verify processing is automatically performed between the buffer memory (13) and the EEPROMs (17, 18, 19). Similarly, data read out from the EEPROMs (17, 18, 19) are temporarily recorded in the buffer memory (13) and are subsequently output to an external unit. Even with the EEPROMs (17, 18, 19), it seems that this memory card can be used in the same manner as a memory card using an SRAM, when viewed from the outside of the card.

Description: The present invention relates to a memory card apparatus using an EEPROM (electrically erasable and programmable read-only memory) as a semiconductor memory and, more particularly, to a memory card apparatus suitably used for an electronic still camera or the like which is designed to convert a photographed optical image of an object to be photographed into digital image data and record the data in a semiconductor memory. As is generally known, an electronic still camera apparatus has been developed. This apparatus is designed to convert a photographed optical image of an object to be photographed into an electrical image signal, convert the image signal into digital image data, and record the data in a semiconductor memory. In an electronic still camera of this type, a memory card having a semiconductor memory incorporated in a case is designed to be detachably mounted in a camera main body so that the memory card can be handled in the same manner as a film for a general camera. The standardization of memory cards for electronic still cameral apparatuses is now in progress. As a built-in semiconductor memory, a large-capacity memory is required in order to record digital image data corresponding to a plurality of frames. As such a memory, an SRAM (static random access memory), a mask ROM, or an EEPROM capable of electrically recording and erasing data, or the like has been considered. A memory card using an SRAM has already been on the market. A memory card using an SRAM is advantageous in that it can conform to the data arrangement of any kind of format, and has a high data write/read speed. However, a backup battery must be housed in the memory card to retain written data. Consequently, the storage capacity is reduced according to the space for housing the battery. In addition, since the SRAM is high in cost, the use of it is economically disadvantageous. In order to eliminate the drawbacks of the SRAM, a great deal of attention has currently been paid to an EEPROM as a semiconductor memory used for a memory card. The EEPROM attracts attention as a recording medium replacing a magnetic disk. The EEPROM has its own advantages in that for example, the EEPROM needs no backup battery for retaining data, and allows a reduction in cost of a chip itself. Owing to such advantages, the development of an EEPROM used for a memory card is progressing rapidly. US - A - 4 803 554 discloses an apparatus for recording electronically high resolution still images. Digitally formatted image data are stored in a buffer memory and further in an EPROM module comprising a plurality of individually addressed groups of EPROM circuits by transferring simultaneously the image data via a plurality of latches. EP - A - 0 372 514 discloses an image memory apparatus in which the data storage and read-out is randomized by using plural address generators for the start address of each data block in the memory. The input/output image processing methods from the memory are controlled by detecting means which trigger a switching unit which switches the start address of each data block. Fig. 1 shows the merits and demerits of a memory card (SRAM card) using an SRAM and a memory card (EEPROM card) using an EEPROM for comparison. First, with regard to "backup battery" and "cost" as comparison items 1 and 2, as described above, the SRAM card requires a backup battery and is high in cost, whereas the EEPROM card requires no backup battery and allows a reduction in cost. Next, with regard to "write speed" and "read speed" as comparison items 3 and 4, consider a random access mode common to the SRAM and the EEPROM, in which a data write/read operation is performed with respect to a byte or bit arbitrarily designated by an address, and a page mode unique to the EEPROM, in which a data write/read operation is performed in units of pages by designating a page consisting of a plurality of consecutive bytes (several hundred bytes). In the random access mode, both the write and read speeds of the SRAM are high, whereas those of the EEPROM are low. In the page mode, since a large number of data corresponding to one page are written/read in/from the EEPROM, its write and read speeds are higher than those in the random access mode. "Erase mode" as comparison item 5 is unique to the EEPROM but is not preset in the SRAM. More specifically, in the EEPROM, data cannot be newly written in an area in which data has already been written without erasing the previously written data first. Therefore, when data is to be written, this erase mode is executed. The erase mode includes a chip erase operation in which all the stored contents of the EEPROM are erased at once, and a block erase operation in which stored contents are erased in units of blocks, each (several kbytes) consisting of a plurality of pages. With regard to "write verify" as comparison item 6, this mode is also unique to the EEPROM but is not present in the SRAM. Generally, in the EEPROM, data cannot be completely written by one write operation. For this reason, every time a write operation is performed with respect to the EEPROM, the written contents must be read out from the EEPROM to check whether the data is correctly written. This operation is performed in the write verify mode. More specifically, data to be written in the EEPROM is recorded in a buffer memory in advance. After the data transferred from the buffer memory is written in the EEPROM, the written contents of the EEPROM are read out to check whether the readout contents coincide with the contents of the buffer memory. If an incoincidence (error) is determined as a result of the write verify operation, the contents of the buffer memory are written in the EEPROM again. As is apparent from the above comparison, the EEPROM has unique merits which the SRAM does not have, e.g., the ability to operate without a backup battery, a low cost, and the ability to perform a data write/read operation in units of pages. However, the EEPROM has some demerits as well. For example, the EEPROM has low data write and read speeds in the random access mode, and requires modes which the SRAM does not require, e.g., the erase mode and the write verify mode. If, therefore, the EEPROM is to be used as a semiconductor memory for a memory card in place of the currently used SRAM, improvements in various aspects need to be made to details so as to allow the EEPROM card to be used in the same manner as the memory card incorporating the SRAM, i.e., to allow the SRAM-card-like use of the EEPROM card, by eliminating its drawbacks, i.e., low data write and read speeds, and the necessity for the erase and write verify modes and the like. The present invention has been made in consideration of the above situation, and has as its object to provide a memory card apparatus which allows the SRAM-card-like use of an EEPROM in data write and read processing. The invention is set out in the claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a view showing the merits and demerits of a SRAM and an EEPROM card for comparison; Fig. 2 is a block diagram showing the arrangement of a memory card apparatus according to an embodiment of the present invention. An embodiment in which the present invention is applied to an electronic still camera apparatus will be described in detail below with reference to the accompanying drawings. Referring to Fig. 2, reference numeral 11 denotes a memory card body, which is connected to an electronic still camera main body CA through a connector 12 arranged at one end portion of the memory card body 11. Digital data DA to be written in the memory card body 11 and address data AD indicating its write location are supplied from the electronic still cameral main body CA side to the connector 12. The digital data DA supplied to the connector 12 are temporarily loaded and recorded in a buffer memory 13. The timings at which the digital data DA are loaded in the buffer memory 13 are controlled by address data output from an address generator 14. The address generator 14 counts clocks CK selected by a selector 15 to generate address data to be supplied to the buffer memory 13. The selector 15 designed to receive bus clocks BCK synchronized with the address data AD, and clocks YCK output from a data processing controller 16. When the digital data DA are to be loaded in the buffer memory 13, the selector 15 selects the bus clocks BCK in accordance with a select signal SEL output from the data processing controller 16, and supplies them, as the clocks CK, to the address generator 14. The address data AD supplied to the connector 12 are supplied to the data processing controller 16, and it is discriminated whether the data are header address data HAD or image address data PAD. That is, the digital data DA output from the electronic still camera main body CA side includes header data HD as pieces of memory management information such as memory card attribute information, various types of information unique to each image data, date information, and remaining frame count information, and image (including speech) data PD corresponding to an object to be photographed. If the data processing controller 16 determines that the input address data AD are the header address data HAD, the controller 16 outputs header write enable data HWE to a header EEPROM 17. The EEPROM 17 is constituted by a plurality (two in Fig. 2) of EEPROM chips 171 and 172. The EEPROM 17 is controlled such that data can be written only in a time interval during which the header write enable data HWE is active (e.g., at H level), but a write operation is inhibited in other time intervals. If the data processing controller 16 determines that the input address data AD are the image address data PAD, the controller 16 outputs image write enable data PWE to an image EEPROM 18. This image EEPROM 18 is also constituted by a plurality of EEPROM chips 181 to 18n. The image EEPROM 18 is controlled such that data can be written only in a time interval during which the image write enable data PWE is active (e.g., at H level), and a write operation is inhibited in other time intervals. In general, EEPROMs are classified into the first type which has a small storage capacity of several 10 kbytes but allows data write and read operations at relatively high speeds in units of bytes designated by addresses, and the second type which has a large storage capacity of several 10 Mbits but cannot perform a write/read operation in units of bytes. The second type, however, has a batch erase function of collectively erasing all storage contents, and a function of collectively performing a data write/read operation in units of pages. Each header data HD of the digital data DA is characterized in that its total data amount is as small as 16 kbytes, and it mainly includes data required to be updated in units of bytes, such as date information and remaining frame count information. Therefore, as the header EEPROM 17 for recording the header data HD, an EEPROM of the first type described above, which has a small storage capacity and can perform a data write/read operation in units of bytes, is used. Each image data PD of the digital data DA is characterized in that it has a very large data amount for one image frame and is sequential as a whole. Therefore, as the image EEPROM 18 for recording the image data PD, an EEPROM of the second type, which has a large storage capacity and has the batch erase function and the function of collectively performing a data write/read operation in units of pages, is used. Assume that the digital data DA written in the buffer memory 13 through the connector 12 are the header data HD. In this case, the data processing controller 16 determines that the header data HD are input, because the input address data AD are the header address data HAD. As a result, the data processing controller 16 outputs the header address data HAD to the header EEPROM 17 and sets the header write enable data HWE in an active state. Subsequently, the data processing controller 16 controls the select signal SEL to switch the selector 15 such that the clocks YCK generated by the controller 16 are supplied to the address generator 14. With this operation, the header data HD are sequentially read out from the buffer memory 13 in accordance with address data generated by the address generator 14 on the basis of the clocks YCK, and the readout data are written in the header EEPROM 17. After all the header data HD are written in the header EEPROM 17, the data processing controller 16 executes a write verify operation as follows. The controller 16 activates header output enable data HOE with respect to the header EEPROM 17, and outputs the header address data HAD to read out the written header data HD. The controller 16 then checks whether the readout header data HD coincide with the header data HD recorded in the buffer memory 13. If the header data HD read out from the header EEPROM 17 do not coincide with the header data HD recorded in the buffer memory 13, the data processing controller 16 transfers the header data HD again from the buffer memory 13 to the header EEPROM 17 to write the data therein. This operation is repeated until the header data HD read out from the header EEPROM 17 completely coincide with the header data HD recorded in the buffer memory 13, thereby completing the process of writing the header data HD. Assume that the digital data DA written in the buffer memory 13 through the connector 12 are the image data PD. In this case, since the input address data AD are the image address data PAD, the data processing controller 16 determines that the image data PD are input. As a result, the controller 16 outputs the image address data PAD to the image EEPROM 18, and activates the image write enable data PWE. The data processing controller 16 then controls the select signal SEL to switch the selector 15 such that the clocks YCK generated by the controller 16 are supplied to the address generator 14. As a result, the image data PD are sequentially read out from the buffer memory 13 in accordance with address data generated by the address generator 14 on the basis of the clocks YCK, and the readout data are written in the image EEPROM 18. After all the image data PD are written in the image EEPROM 18, the data processing controller 16 executes a write verify operation as follows. The controller activates image out enable data POE with respect to the image EEPROM 18, and outputs the image address data PAD to read out the written image data PD. The controller 16 then checks whether the readout image data PD coincide with the image data PD recorded in the buffer memory 13. If the image data PD read out from the image EEPROM 18 do not coincide with the image data PD recorded in the buffer memory 13, the data processing controller 16 transfers the image data PD again from the buffer memory 13 to the image EEPROM 18 to write the data therein. This operation is repeated until the image data PD read out from the image EEPROM 18 completely coincide with the image data PD recorded in the buffer memory 13, thereby completing the process of writing the image data PD. The process of reading out the header data HD and the image data PD from the header EEPROM 17 and the image EEPROM 18, and outputting the readout data outside the memory card body 11 will be described below. Addresses at which data are read out from the electronic still camera main body CA side through the connector 12 are designated first. The designated addresses are supplied to the data processing controller 16, and it is discriminated whether the data are the header address data HAD or the image address data PAD. Subsequently, the data processing controller 16 activates the header out enable data HOE and the image out enable data POE on the basis of the discrimination result, and switches the selector 15 such that the clocks YCK generated by the controller 16 are supplied to the address generator 14, thereby reading out the header data HD and the image data PD from the header EEPROM 17 and the image EEPROM 18, respectively, and writing the readout data in the buffer memory 13. The data processing controller 16 then switches the selector 15 such that the bus clocks BCK supplied from the electronic still camera main body CA side through the connector 12 are supplied to the address generator 14. As a result, data are read out from the buffer memory 13 in accordance with address data generated by the address generator 14 on the basis of the bus clocks BCK. The readout data are supplied to the electronic still camera main body CA through the connector 12, and the header data HD and the image data PD are read out from the memory card body 11. According to the arrangement of the embodiment described above, an EEPROM of the first type, which has a small storage capacity and can perform a data write/read operation in units of bytes at a relatively high speed, is used as the header EEPROM 17 for recording the header data HD characterized in that it has a small data amount and mainly includes data updated in units of bytes, and an EEPROM of the second type, which has a large storage capacity and can perform a batch erase operation and a batch data write/read operation in units of pages, is used as the image EEPROM 18 for recording the image data PD characterized in that it has a very large data amount and is sequential as a whole. Therefore, even with the EEPROMs, data can be arbitrarily updated in units of bytes or pages according to the type of data. In addition, since data transfer between the electronic still camera main body CA and the memory card body 11 is always performed through the buffer memory 13, both the data write speed and the data read speed are increased, and the memory card can be used in the SRAM-card-like manner. Furthermore, since a write verify operation unique to the EEPROM is automatically performed between the buffer memory 13 and the header and image EEPROMs 17 and 18 inside the memory card body 11, data write/read processing can be performed in the SRAM-card-like manner when viewed from the electronic still camera main body CA side.

Claims: A memory card apparatus for receiving and storing data from an external unit, comprising a memory (13) for inputting and outputting said data with respect to said external unit, EEPROMs for performing read and write operations with respect to said memory (13), and control means (16), characterized in that said data include a first data group consisting of at least one group of first data which is read/written in units of bytes, and a second data group consisting of at least one group of second data which is sequentially arranged as a whole, each second group of data being larger than each first group of data; said memory (13) is capable of high-speed read and write operations; said EEPROMs include a first EEPROM (17) and a second EEPROM (18), said first EEPROM (17) has a storage capacity large enough to record said first data group and is capable of performing said read and write operations in units of bytes, and said second EEPROM (18) has a storage capacity large enough to record said second data group and is capable of performing data read/write operation in units of reference areas, each reference area having a plurality of consecutive bytes; and said control means (16) comprises means for characterizing data stored in said memory (13) as one of said first data group and said second data group and for writing said data to a selected one of said first and second EEPROMs (17, 18) based on said characterization, and further includes: write control means for, after data has been transferred from said memory (13) to said selected EEPROM (17, 18) and written therein, reading out said data written in said selected EEPROM (17, 18), comparing said readout data with said data stored in said memory (13), and again transferring said data from said memory (13) to said selected EEPROM (17, 18) when said readout data and said data stored in said memory (13) do not coincide with each other; clock switching means (15) for effecting a first switch and a second switch, said first switch being between an input operation in which data supplied from said external unit is input to said memory (13) and an output operation in which data from said memory (13) is output to said external unit, said first switch being effected based on a first clock which is supplied from said external unit, and said second switch being between a writing operation in which data from said memory (13) is transferred to and written in said selected EEPROM (17, 18) and a reading operation in which data from said selected EEPROM (17, 18) is read into said memory (13), said second switch being effected based on an internally generated second clock; and inhibiting signal generation means for, while data from said memory (13) is being read out from and written into said second EEPROM (18) in units of reference areas, generating and outputting a data input inhibiting signal for inhibiting input of data from said external unit. The memory card apparatus according to claim 1, wherein each of said first and second EEPROMs (17, 18) includes: a data area for recording data in units of reference areas, and a management area for recording management information corresponding to said data recorded in said data area, and wherein said control means (16) records a data update count in a part of said management area when a corresponding reference area is updated with data. The memory card apparatus according to claim 1, wherein each of said first and second EEPROMs (17, 18) includes: a data area for recording data in units of reference areas, and a management area for recording management information corresponding to said data recorded in said data area, and wherein said control means (16) records a data erase count in a part of said management area when data is erased from a part of a corresponding data area. The memory card apparatus according to claim 1, further comprising: error detection means for detecting presence/absence of an error within said reference areas of said second EEPROM (18), error flag write means for recording error flags representing said detected presence/absence of an error from within each of said reference areas, said error flags being recorded in one of said reference areas designated as an error flag area, data write substitute means for writing data written in one of said reference areas flagged with an error into a free area which is designated as a substitute area, address write means for writing a substitute address in said error reference area when data is written in said substitute area, said substitute address corresponding to a location within said substitute area of said data which was written by said data write substitute means, and data read means for determining said error reference area by referring to said error flag area, determining said substitute address by reading out data from said error reference area, and reading out said data from said substitute reference area on the basis of said determined address. The memory card apparatus according to claim 4, wherein: said address write means writes said substitute address in a plurality of bytes in said error reference area, and said data read means reads out data from a plurality of bytes in said error reference area to determine a substitute address by majority.

Inventors: KONISHI KAZUO, MARUYAMA KOJI, MATSUBARA HIROAKI, SATO TOSHIAKI, TERASAKI SETSUO, YOSHIOKA SHIMPEI, KONISHI, KAZUO, MARUYAMA, KOJI, MATSUBARA, HIROAKI, SATO, TOSHIAKI, TERASAKI, SETSUO, YOSHIOKA, SHIMPEI, Konishi, Kazuo, c/o Intellectual Pty Division, Maruyama, Koji, c/o Intellectual Pty Division, Matsubara, Hiroaki, c/o Intellectual Pty Division, Sato, Toshiaki, c/o Intellectual Pty Division, Terasaki, Setsuo, c/o Intellectual Pty Division, Yoshioka, Shimpei, c/o Intellectual Pty Division
Applicants: TOSHIBA AVE KK, TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA, TOSHIBA AVE CO., LTD
Application year: 1992
Main classification: H04N5
IPC codes: G11C16, G11C29, H04N5