Method of fabricating a trench structure in a semiconductor substrate

Abstract: A method of fabricating a trench structure (10) includes providing a substrate (12) having a first layer (16) disposed on a surface thereof and a second layer (18) disposed on the first layer (16). A trench (20) is formed through the first (16) and second (18) layers and into the substrate (12). A dielectric liner (22) is formed on the sidewalls of the trench (20) which is then filled with a trench fill material (24). Portions of the trench liner (22) disposed above the trench fill material (24) are removed and a conformal layer (28) is then formed on the trench structure (10). The conformal layer (28) and a portion of the trench fill material (24) are then oxidized.

Description: Field of the Invention This invention relates, in general, to the semiconductor arts and more particularly to a method of fabricating a trench structure. Background of the Invention Trench structures are widely used in the semiconductor arts. Trenches may be used for a variety of purposes although they are most commonly used for isolation. Trench isolation may be utilized to isolate devices, CMOS portions and the like. Polysilicon buffered LOCOS (PBL) is commonly used to form field oxidation regions in semiconductor structures. Typically, a substrate is provided and an oxide layer is formed thereon. A polysilicon layer is formed on the oxide layer and a nitride layer is formed on the polysilicon layer. An opening is formed through the nitride layer that exposes the polysilicon layer. Once the polysilicon layer is exposed, it and the substrate are thermally oxidized to form field oxidation regions. The PBL thermal oxidation step results in birds beak encroachment as is well known in the art. This encroachment is undesirable and does not allow PBL to be a viable isolation scheme in very small geometry structures. PBL is commonly employed with nitride spacers. Following the formation of the opening, nitride spacers are formed on the sidewalls thereof. This allows the opening to have a width that is less than standard lithography resolution limits will allow. PBL utilized with nitride spacers is referred to frame masked polysilicon buffered LOCOS (FMPBL). Nguyen et al. in their article 'Framed Mask Poly Buffered LOCOS Isolation For Submicron VLSI Technology', ECS Extended Abstracts, vol. 90-1, abstract no. 408, p. 614, 1988, teach a framed mask poly buffered LOCOS (FMPBL) using only conventional LSI processes without additional masks. A poly buffered layer is deposited on a thin pad oxide prior to nitride deposition. This reduces the active area of various stress and plasma etch induced damage prior to field oxidation. The poly layer also acts to reduce lateral oxidant diffusion to provide a blunt field oxide edge profile. Second nitride is deposited to cover the masking nitride and is then etched anisotropically to form the silicon nitride sidewall which frames the masking structure to reduce the field isolation width or to offset field encroachment. Yu et al. in their article entitled 'Planarized Deep-Trench Process For Bipolar Device Isolation' ECS Extended Abstracts, vol. 88-2, abstract no. 234, p. 326, 1988, teach planarized device isolation using deep trench isolation technology combined with LOCOS. Trenches were etched into a silicon substrate and the walls and bottom of the trenches were oxidized to form a trench liner. The trenches are refilled with polysilicon and etched back. A pad oxide is then formed followed by a silicon nitride deposition. The nitride is then etched back from trench leaving a mask to form a field isolation region over the trench. Pan, in his article entitled 'Birds Beak-Free Semi-Rox With Large Radius On Corner Curvature', IBM Technical Disclosure Bulletin, vol. 27, no. 6, 1984, teaches a process of forming an isolation scheme that includes a trench liner and doped polysilicon fill in the trench. The polysilicon fill is chemical-mechanical planarized and then recessed by RIE etching. A wet etch leaves the sidewall recess below the polysilicon trench fill. A second doped polysilicon fill is conducted and a second chemical mechanical planarizaion step is performed. A shallow recess on top of the doped silicon is then performed after which the polysilicon is oxidized thermally. European Patent Application EP-A-0425965 teaches a method of fabricating semiconductor structures that includes forming a thermal oxide, a polysilicon layer and a first dielectric layer on a substrate and using a mask to form at least one opening therein. Dielectric spacers are then formed in the opening and a trench having self aligned reduction width due to the dielectric spacers is etched into the substrate beneath the opening. A dielectric trench liner is then formed prior to filling the trench with polysilicon. A second mask is then used to form isolation element openings in the first dielectric layer in which shallow isolation elements are formed. An article entitled 'Formation of Thermal Isolation Cap Oxide' in IBM Technical Disclosure Bulletin, vol. 33, no. 4, 1990, pages 463-465 describes a process for forming a cap oxide on top of polysilicon trenches to eliminate stresses due to vertical bird's beaking during thermal oxidation process steps. The basic integration of FMBPL and trench technology to form field oxidation regions above isolation trenches would appear to have many desirable features. However, this integration also renders substantial processing problems. Specifically, following the formation of a trench including a liner and polysilicon trench fill, the liner is etched back below the surface of the polysilicon trench fill. This etch back causes a recessed surface or divots in the liner. When nitride spacers are formed, nitride residue remains in the divots. During later processing steps, specifically when an oxide cap is grown over the trench, no oxide grows over the nitride in the divots. Therefore, when polysilicon is subsequently deposited and patterned over the trench, polysilicon stringers are formed in the divots. These polysilicon stringers are detrimental to semiconductor processing, final device performance and yield. Accordingly, it would be highly desirable to have a method of fabricating a trench structure that would allow the desired features of FMPBL and trench technology without having the common problems associated with the integration of these technologies. Summary of the Invention In accordance with the present invention there is provided a method of fabricating a trench structure as recited in claim 1 of the accompanying claims. Brief Description of the Drawings FIGS. 1-4 are highly enlarged cross-sectional views of a portion of a trench structure during processing; and FIG. 5 is a highly enlarged cross-sectional view of a portion of a trench structure. Detailed Description of the Drawings FIGS. 1-4 are highly enlarged cross-sectional views of a portion of a trench structure 10 during processing while FIG. 5 is a highly enlarged cross-sectional view of a portion of trench structure 10. FIGS. 1-5 are not to scale. Trench structures such as structure 10 have many uses in the semiconductor arts. Trench structure 10 as shown herein will preferably be used for isolation applications. Trench structure 10 may be employed as an isolation module for BICMOS integrated circuits having submicron features. Now referring specifically to FIG. 1. Structure 10 includes a substrate 12. As shown herein, substrate 12 comprises monocrystalline silicon although it should be understood that the present invention may be employed with substrates of material other than silicon. An oxide layer 14 is formed on substrate 12. Oxide layer 14 is preferably formed by thermally oxidizing substrate 12. Oxide layer 14 should have a thickness in the range of 10 to 50 nm (100 to 500 angstroms) and preferably on the order of 15 nm (150 angstroms). A polysilicon layer 16 is formed on oxide layer 14. Polysilicon layer 16 is formed by LPCVD as is well known in the art. Preferably, polysilicon layer 16 will have a thickness in the range of 35 to 100 nm (350 to 1000 angstroms). A nitride layer 18 is formed on polysilicon layer 16. Nitride layer 18 is also formed by LPCVD. Preferably, nitride layer 18 will have a thickness in the range of 100 to 250 nm (1000 to 2500 angstroms). A trench 20 is formed through nitride layer 18, polysilicon layer 16 and oxide layer 14 into substrate 12. Trench 20 will preferably extend 3.0 to 6.0 micrometers into substrate 12 although this depth may be varied. Trench 20 may be formed by methods well known in the art. Preferably, a trench photoresist layer (not shown) is formed on nitride layer 18 and a window for trench 20 is patterned therein. Reactive ion etching is employed to remove the portion of nitride layer 18 disposed in the trench window. Well known nitride etching chemistries may be employed. Following the etching of nitride layer 18, the trench photoresist is removed and reactive ion etching is then employed to etch through polysilicon layer 16, oxide layer 14 and substrate 12. Well known chemistries may be employed to etch oxide and silicon. The previously etched opening in nitride layer 18 serves as a window for the etch of polysilicon layer 16, oxide layer 14 and substrate 12. For specific applications, it may be desirable to deposit a hard mask oxide layer on top of nitride layer 18 prior to trench formation. This oxide may be a low temperature deposited oxide or a plasma enhanced TEOS oxide. Preferably, this oxide would have a thickness in the range of 200 to 400 nm (2000 to 4000 angstroms). The trench photoresist layer would then be formed on the hard mask oxide layer. The hard mask oxide layer would be removed following the etching of trench 20. The inside of trench 20 is cleaned following its formation. The trench clean may be performed simultaneously with the removal of the optional hard mask oxide layer if employed. The trench clean may also be used to remove a desired amount of silicon from trench 20 if desired. Once trench 20 has been cleaned, specific applications may desire that a channel stop (not shown) is formed beneath trench 20 in substrate 12. A channel stop may be formed by methods well known in the art. A channel stop will not be necessary for the majority of applications if substrate 12 is highly doped. Following cleaning of trench 20, a trench liner 22 is formed therein. Trench liner 22 comprises oxide as shown herein. Oxide trench liner 22 may be thermally grown, deposited or a combination of thermally grown and deposited oxides. Trench liner 22 will have a thickness in the range of 100 to 250 nm (1000 to 2500 angstroms). Preferably, trench liner 22 is fabricated by forming a conformal oxide layer over the entire structure including in trench 20 and later removing the unwanted portions of the conformal layer. This will be explained presently. Following the formation of trench liner 22, lined trench 20 is filled with polysilicon 24. Polysilicon trench fill 24 is preferably formed by forming a conformal polysilicon layer on the surface of structure 10. The conformal layer will have a thickness in the range of 600 to 800 nm (6000 to 8000 angstroms). This, of course, is dependent upon upon the width of trench 20. For specific applications, it may be desired that polysilicon trench fill 24 contact substrate 12. If so desired, the portion of trench liner 22 disposed in the bottom of trench 20 may be removed prior to the formation of polysilicon trench fill 24. Following the formation of the conformal polysilicon layer, a planarizing layer comprising a resin, spin-on glass or similar well known material (not shown) is formed over the surface of structure 10. The planarization layer and the conformal polysilicon layer are etched to leave polysilicon trench fill 24 recessed in trench 20. It should be understood that the etchant used to etch the planarization layer and the conformal polysilicon layer should be selective so that it does not etch any of the oxide layer from which trench liner 22 is formed. This will most likely require a two step etch wherein the planarizing layer and a portion of the conformal polysilicon layer are initially etched and a second step employing a polysilicon etchant selective to oxide and nitride. Once the unwanted portion of the conformal polysilicon layer from which trench fill 24 is formed has been etched away, the portions of the conformal oxide layer which forms trench liner 22 or any portions of trench liner 22 disposed above trench fill 24 are then etched away as is shown in FIG. 2. Etching trench liner 22 beneath the top surface of trench fill 24 leaves divots 26. Divots 26 are extremely detrimental to future processing steps, final device performance and yield. Now referring specifically to FIG. 3. A conformal polysilicon layer is formed over the entire surface of structure 10 including in divots 26 and above polysilicon trench fill 24. The conformal polysilicon layer has a thickness of between 50 and 200 nm (500 and 2000 angstroms) although a thickness on the order of 80 nm (800 angstroms) is preferred. Following its deposition, the conformal polysilicon layer is thermally oxidized to form oxidized layer 28. The thermal oxidation of layer 28 should be such that a portion of polysilicon trench fill 24 is consumed. Following the thermal oxidation of layer 28, the top surface of polysilicon trench fill 24 should be equal to or below the top surface of substrate 12. It is also desirable that the surface of oxidized layer 28 be formed as planar as possible. The oxidation of layer 28 fills in divots 26. Following the oxidation of layer 28, oxidized layer 28 is planarized and etched back. Preferably, oxidized layer 28 will be etched back to a thickness over nitride layer 18 in the range of 5 to 75 nm (50 to 750 angstroms) with a preferable thickness on the order of 30 nm (300 angstroms). Planarization and etch back of oxidized layer 28 may occur by methods well known in the art including an isotropic wet etch with a buffered HF solution or a resin or spin-on glass layer may be applied to planarize oxidized layer 28 and then etched back so that layer 28 will have the desired thickness. Following the planarization and etch back of oxidized layer 28, a photoresist layer (not shown) is formed and patterned on oxidized layer 28. The photoresist layer is patterned so that a window is disposed above trench 20. The window disposed above trench 20 will have a width that is laterally greater than the width of trench 20 itself. This window will be used to form opening 30 as is shown in FIG. 4. Another window is formed in the photoresist layer and is laterally removed from trench 20. The second opening removed from trench 20 will be employed to create opening 32 as is also shown in FIG. 4 Once the photoresist windows have been formed, openings 30 and 32 are formed. To form openings 30 and 32, portions of oxidized layer 28 and nitride layer 18 are etched away. Preferably, no portions of polysilicon layer 16 are removed in this step. An RIE etch having a substantially 1:1 oxide-nitride selectivity as is well known in the art may be used. It should be understood that the etchant must also be selective so that it will not significantly damage polysilicon layer 16. During the etch of openings 30 and 32, the portions of oxidized layer 28 disposed directly above polysilicon trench fill 24 are etched so that only an oxide cap 34 remains. Following the formation of openings 30 and 32, nitride spacers 36 are formed. Nitride spacers 36 are formed on polysilicon layer 16 and extend upward along the sidewalls of openings of 30 and 32 above the interface of nitride layer 18 and oxidized layer 28. Nitride spacers 36 are fabricated by forming a conformal nitride layer over the surface of structure 10 and anisotropically etching the conformal nitride layer to leave spacers 36. It should be understood that oxidized layer 28 and polysilicon layer 16 serve as an etch stop for the etch of nitride spacers 36. Now referring specifically to FIG. 5. Following the formation of nitride spacers 36, field oxidation region 38 is formed above trench 22 in opening 30 and field oxidation region 40 is formed in opening 32. Field oxidation regions 38 and 40 are formed by thermally oxidizing polysilicon layer 16 and substrate 12 and in the case of region 38, polysilicon trench fill 24. Following the formation of field oxide regions 38 and 40, the remaining portions of oxidized layer 28, nitride layer 18, unoxidized polysilicon layer 16 and nitride spacers 36 are removed from the surface of structure 10 as shown in FIG. 5. Trench structure 10 as depicted in FIG. 5 is an isolation module that may be used for bipolar or BICMOS applications and is now ready to have device processing begin thereon. Although field oxidation regions 38 and 40 and trench 22 are specifically configured in FIG. 5, it should be understood that the present invention may be employed with different configurations including variable numbers of trenches and field oxidation regions. The method of fabricating a trench structure disclosed herein is ideal for use in fabricating integrated circuits wherein the devices have submicron features. The integration of FMPBL which has reduced encroachment of the field oxidation regions with trench technology for isolation is superior. The divots formed during the etch back of trench liner 22 are remedied by the formation of oxidized layer 28 which precludes the later formation of polysilicon stringers. Accordingly, future processing problems are greatly reduced, final device performance is enhanced and yield is increased.

Claims: A method of fabricating a trench structure (10) comprising the steps of: providing a substrate (12) having at least a first layer (16) disposed on a surface thereof and a second layer (18) disposed on said first layer (16); forming a trench (20) through said first (16) and second (18) layers and into said substrate (12); forming a dielectric liner (22) in said trench (20), said liner (22) extending along the trench at least to a point above said surface of said substrate (12); forming trench fill material (24) in said trench (20), said trench fill material (24) extending above said surface of said substrate (12) but below the surface of said second layer (18); removing portions of said trench liner (22) disposed above said trench fill material (24) wherein divots (26) are formed adjacent said trench fill material (24); forming a polysilicon conformal layer (28) on said structure (10) including said trench (20) and said second layer (18); oxidising said conformal layer (28) and a portion of said trench fill material (24); forming an opening (30) in the oxidised conformal (28) and second (18) layers wherein the opening overlies the trench and has a width greater than a width of the trench; and forming a field oxidation region (38) in the opening (30) above the trench (20). The method of claim 1 wherein spacers (36) abutting the second layer (18) are formed in the opening (30). The method of claim 2 wherein said spacers (36) comprise nitride. The method of claim 2 further including the steps of: forming at least one opening (32) in the oxidised conformal (28) and second (18) layers laterally remote from the trench (20); forming spacers (36) abutting said second layer (18) in said at least one opening (32) laterally remote from said trench (20); and forming a field oxidation region (40) in said at least one opening (32) laterally remote from said trench (20). The method of claim 4 wherein an oxide layer (14) is formed on the substrate (12), the first layer (16) comprises polysilicon, the second layer (18) comprises nitride, the dielectric liner (22) comprises oxide and the trench fill material (24) is polysilicon.

Inventors: LIANG HAN-BIN KUO, SEE YEE-CHAUNG, WILSON SYD R, ZIRKLE THOMAS, LIANG, HAN-BIN KUO, SEE, YEE-CHAUNG, WILSON, SYD R., ZIRKLE, THOMAS
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L27, H01L21