Common intermediate format converter with reduced number of multipliers

Abstract: A CIF converter has N multipliers (where N is smaller than five) and N integrators connected respectively to the outputs of the N multipliers. Every five horizontal lines of an input NTSC or PAL television signal is stored in memory. On a pixel-by-pixel basis first and second half segments of a luminance component of the stored lines and I and Q chrominance components of the stored lines are transferred from corresponding pixel positions of the memory to the N multipliers at a speed higher than the speed at which the input signal is stored into the memory, and weighted by tap weight coefficients having unique values corresponding respectively to the five horizontal lines. The weighted five-line pixel data of each of the video signal components are then summed by each integrator and stored back into the memory and sequentially read therefrom at a speed equal to the writing speed.

Description: The present invention relates generally to a video communications system, and more specifically to the conversion of a color television signal in the NTSC (National Television Standard Committee) or PAL (Phase Alternation by Line) system format into a common intermediate format (CIF) standardized by CCITT. A conventional CIF converter comprises a series of five memories for respectively storing successive five horizontal lines of an NTSC or PAL signal to produce a set of pixel data spaced a horizontal line apart from each other. Five multipliers are respectively connected to the outputs of the memories to multiply the pixel data with tap weight coefficients. The multiplied data are summed together to produce a single-line output signal for transmission. It is the current practice to implement the CIF converter using LSI technology (see CCITT Study Group XV Report R.16, pages 1-42 (1986)). Since a multiplier is made up of complex logic elements, it occupies a substantial amount of space in an LSI chip and dissipates a substantial amount of power. It has therefore been desired to reduce the number of multipliers required to implement a CIF converter. GB-A-2 047 042 discloses a system for digital storage and processing of picture signals with a video format converter having an arrangement of line memories and multipliers and converter units comprising memory means, multipliers and integrators. It is therefore an object of the present invention to provide a CIF converter which allows implementation with a smaller chip size and reduced power dissipation by reducing the number of multipliers. This object is solved with the features of the claims. In particular, the number of multipliers is reduced to four by equally dividing a luminance component into first and second half segments and treating them in the same way as chrominance components are treated. According to the following description a common intermediate format converter is provided which comprises N multipliers (where N is smaller than five) and N integrators connected respectively to the outputs of the N multipliers. Every five horizontal lines of an input color television signal of NTSC or PAL system format is stored in memory. On a pixel-by-pixel basis first and second half segments of a luminance component of the stored lines and I and Q chrominance components of the stored lines are read and transferred from corresponding pixel positions of the memory to the N multipliers at a speed higher than the speed at which the input signal is stored into the memory. Supplied to the N multipliers are tap weight coefficients having unique values corresponding respectively to the five horizontal lines so that five-line pixel data of each of the video signal components are weighted by each multiplier and summed by each integrator. The outputs of the N integrators are stored back into the memory and sequentially transferred from the memory at a speed equal to the writing speed. In particular, the CIF converter comprises first, second, third and fourth multipliers. First, second, third and fourth integrators are connected respectively to the outputs of the first, second, third and fourth multipliers. On a pixel-by-pixel basis, first and second half segments of a luminance component and I and Q chrominance components of the stored lines are read and transferred from corresponding pixel positions of the memory to the first, second, third and fourth multipliers respectively at a speed higher than the speed at which the input signal is stored. The tap weight coefficients are supplied to the first, second, third and fourth multipliers. The transferred pixel data are weighted by the multipliers and summed by the integrators, whose outputs are stored back into the memory and sequentially read therefrom at the writing speed. A further reduction of the number of multipliers is achieved by equally dividing one of an I- chrominance component into first and second half segments and time-sharing a first multiplier with the first half segments of the luminance and I-chrominance component and time-sharing a second multiplier with the second half segments of the luminance and I-chrominance components. The CIF converter as described may also comprise first, second and third multipliers. First, second and third integrators are connected respectively to the outputs of the first, second and third multipliers. From corresponding pixel positions of the stored lines a first half segment of the luminance component and a first half segment of the I chrominance component are transferred to the first multiplier, and a second half segment of the luminance component and a second half segment of the I chrominance component are transferred to the second multiplier, with the Q chrominance component being transferred to the third multiplier. The tap weight coefficients are supplied to the first, second and third multipliers in which the transferred pixel data are weighted. The weighted data from each multiplier are integrated by the respective integrator. The outputs of the integrators are stored into the memory and sequentially read therefrom at the writing speed. The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a video communications system incorporating a first embodiment of the CIF conversion unit of the present invention; Fig. 2 is a view showing the internationally standardized common intermediate format for conversion between NTSC and PAL system formats; Fig. 3 is a timing diagram associated with the embodiment of Fig. 1; Fig. 4 is a block diagram of a modification of the embodiment of Fig. 1; Fig. 5 is a timing diagram associated with the modification of Fig. 4; Fig. 6 is a block diagram of a second embodiment of the CIF conversion unit of the invention; Fig. 7 is a timing diagram associated with the embodiment of Fig. 6; Fig. 8 is a block diagram of a modification of the embodiment of Fig. 6; and Fig. 9 is a timing diagram associated with the modification of Fig. 8. Referring now to Fig. 1, there is shown a color television transmission system embodying the present invention. At the transmit end of the system, an analog NTSC or PAL video signal is sampled and converted by an A/D converter 1 to a digital signal and supplied to a color decoder 2 in which it is decoded into luminance (Y), I-channel chrominance (I) and Q-channel chrominance (Q) component signals. The outputs of color decoder 2 are applied to a time-division multiplexer 3 In which they are multiplexed. As shown in Fig. 2, the common Intermediate frame format (CIF) specifies that each of 525 horizontal lines consists of a total of 858 pixels for NTSC system and 864 pixels for PAL system. For each standard color TV system, the CIF standard assigns 352 pixels for Y signal, and 176 pixels for each chrominance signal and 64 pixels for separation between these signals. The time-division multiplexed color TV signal Is applied to a CIF conversion unit 4 which is constructed according to a first embodiment of the present invention. Timing signals to AID converter 1, decoder 2, multiplexer 3 and CIF conversion unit 4 are supplied from a timing circuit 5. The output of the CIF conversion unit 4 is applied to a bandwidth compression circuit 6 implemented with a digital band-pass filter for compressing the bandwidth of the CIF signal so that it conforms to the bandwidth of a communication channel. The output of bandwidth compression circuit 6 is applied to a unipolar-to-bipolar converter 7 in which the signal is converted according to a specified line code for transmission through a communication channel 8 to a receive end of the system. At the receive end, the transmitted CIF signal is converted to a unipolar format by a bipolar-to-unipolar converter 9, fed into a bandwidth expansion circuit 10 to expand the CIF signal to the original bandwidth. The output of the bandwidth expansion circuit 10 is applied to a known CIF inverse conversion unit 11 which processes the input signal in a process inverse to that of the CIF conversion unit of the transmitter. A demultiplexer 12 is connected to the output of CIF inverse conversion unit 11 to decompose the signal into Y, I and Q components. A color encoder 13 receives the outputs of demultiplexer 12 for encoding them into NTSC or PAL system format for D/A conversion by a D/A converter 14. To reduce the number of multipliers for CIF conversion, the present invention divides the luminance component equally into a first half portion Y 1 and a second half portion Y 2 so that they can be treated as a block of 176-pixel data in the same manner as chrominance components I and Q are treated. Each CIF conversion sub-unit has the following transfer function: H(z)=Σa n ·z -n where a n is a tap weight coefficient of a horizontal line n, and z -n represents a delay operator, where z -1 indicates the delay time of one horizontal line and n is in the range between 1 and 5. As illustrated in Fig. 1, the CIF conversion unit 4 comprises a plurality of CIF conversion sub-units 21 1 , 21 2 , 21 3 and 21 4 of identical configuration connected to the output of multiplexer 3 to receive luminance components Y 1 , Y 2 , chrominance components I and Q, respectively. Each CIF conversion sub-unit 21 includes a selector 22 having two input terminals, one of which is coupled to the output of multiplexer 3. The output of selector 22 is connected to a dual-port RAM (random access memory) 23 for storing 1056 words, or pixels of video signal. Namely, the RAM 23 is capable of storing 176 x 5 pixels of input signals that occur on five successive horizontal lines plus 176 pixels of a processed version of the five-line video signal. The output of RAM 23 is coupled to the input of a selector 24 having two output terminals, one being coupled to a multiplier 25 in which it is successively multiplied with a tap weight coefficient a n (where n = 1 ∼ 5) supplied from a controller 28. The other output terminal of selector 24 is the output terminal of the sub-unit and is connected together with corresponding output terminals of the other CIF conversion sub-units to the input of bandwidth compression circuit 6. The output of multiplier 25 is applied to one input of an adder 26 in which it is summed with a signal from an accumulator 27 to which the output of adder 26 is connected. An integrator is formed by the adder 26 and accumulator 27 to produce a weighted and summed output. The output of accumulator 27 is applied to the second input terminal of selector 22. Selectors 22 and 24, RAM 23 and accumulator 27 are controlled in response to signals supplied from controller 28. Controller 28 receives a timing signal from timing circuit 5 to control selectors 22, 24 and RAM 23. The operation of each CIF conversion sub-unit will be described with reference to Fig. 3. The controller 28 of each CIF conversion sub-unit is constantly monitoring the signal from the timing circuit 5 to detect when to establish a passage from the output of multiplexer 3 to RAM 23 and cause the latter to sequentially write an associated one of the 176-pixel data from multiplexer 3 during five successive horizontal lines. The controller 28 of sub-unit 21 1 supplies write address codes to RAM 23 during the Y 1 -period of first to fifth lines so that 880-pixel data of the Y 1 component is stored into an 880-word storage area of the memory during times t 1 and t 2 . Likewise, the Y 2 , I and Q components of every first to fifth lines are stored respectively into the RAM's of sub-units 21 2 , 21 3 and 21 4 during successive 176-pixel intervals t 2 -t 3 , t 4 -t 5 , and t 6 -t 7 . During this five-line data entry mode, selector 22 of each sub-unit is switched to the lower input terminal and at the end of this mode, it is transferred to the upper input terminal and RAM 23 is supplied with read address codes at twice the rate at which the input data is written in. These read address codes specify data that occur on corresponding pixel positions of the first to fifth lines to produce a set of five pixel components spaced 858 (or 864) pixels apart from each other. Five pixel components of each set from RAM 23 are passed through selector 24 to multiplier 25 in which they are multiplied respectively with a tap weight a n according to the CIF conversion algorithm and supplied to adder 26 and then to accumulator 27 to produce a summed output. RAM 23 is supplied with a write address for writing the summed output into a 176-word storage area of the memory at 2/5 times the data entry rate. Thus, RAM 23 Is in a read/write mode when all 880 pixel data are read out of the memory and processed to produce 176 summed outputs. During this read/write mode, selector 22 remains in the upper input terminal and selector 24 is transferred to the upper output terminal to enable the 176 summed outputs to be stored into RAM 23. Therefore, all 880-stored pixel data are processed during an interval between time t 2 and time t 5 ' which occurs somewhere between times t 5 and t 6 . This interval corresponds to a count of 440 pixels which would otherwise be continuously read out of RAM 23 at the pixel data entry rate. At time t 5 ', selector 24 is transferred to the lower output terminal for providing a passage to the bandwidth compression circuit 6. RAM 23 is now switched to a read mode in which it is supplied with read address codes at a rate equal to the data entry rate to read the processed 176-pixel data out of the memory through selector 24 to the output of sub-unit 21 1 . This read mode terminates at time t 6 ' which corresponds to the 792th pixel point from the first pixel point. Identical accumulation processes proceed with other sub-units 21 2 , 21 3 and 21 4 , beginning respectively at times t 2 , t 4 , and t 6 , and CIF converted output data is generated by combining the time-sequentially generated outputs of the CIF conversion sub-units 21 with an interval of 64 pixels being interposed between Y 2 and I signals and between I and Q signals. An alternative form of the CIF conversion unit of Fig. 1 is shown in Fig. 4 in which two single-port random access memories 30 and 34 are employed for each of the CIF conversion sub-units, instead of a single dual-port random access memory and two selectors. Each CIF conversion sub-unit 21A i (where i = 1, 2, 3 and 4) comprises an input RAM 30 i , a multiplier 31 i , an adder 32 i , an accumulator 33 i , an output RAM 34 i and a controller 35 i . The input RAM 30 i has a capacity of 880 words and output RAM 34 i has a capacity of 176 words. As illustrated in Fig. 5, RAM 30 1 stores 880 pixels of the Y 1 component in a write mode which is followed by a read mode in which all 880 pixel data are read out of the memory at twice the data entry rate and processed through multiplier 31 1 , 32 1 and 33 1 in the same manner as described above. During this read mode of RAM 30 i , output RAM 34 1 is driven at 2/5 times the data entry rate to store 176 summed outputs of the Y 1 component from accumulator 33 1 . At the end of the accumulation process, RAM 34 1 is driven at the same rate as the data entry rate in a read mode. Similar accumulation processes and data reading occur in other CIF conversion sub-units 21A 2 through 21A 4 . Fig. 6 is a block diagram of a further embodiment of the present invention in which the number of multipliers is reduced to three. This is achieved by time sharing a first multiplier with the luminance component Y 1 and a first half-section of the chrominance component I and time sharing a second multiplier with the luminance component Y 2 and a second half-section of the chrominance component I, and exclusively using the third multiplier for processing the chrominance component Q. The CIF conversion unit of Fig. 6 comprises two CIF conversion sub-units 21B 1 and 21B 2 of identical configuration and one CIF conversion sub-unit 21B 3 . Each of the sub-units 21B i (where i = 1 and 2) comprises two input RAM's 41 i and 42 i with memory capacities of 880 and 440 words, respectively. The outputs of RAM's 41 and 42 are coupled together to the CIF conversion circuit formed by multiplier 43 i , adder 44 i and accumulator 45 i . Two output RAM's 46 i and 47 i with respective capacities of 173 and 88 words are connected to the output of accumulator 45 i . The third sub-unit 21B 3 differs from the other sub-units by using only one input RAM 40 3 and an output RAM 46 3 . In the first sub-unit 21B 1 , the input RAM's 41 1 and 42 1 are driven by controller 48 1 to store 880-pixel data of the luminance component Y 1 in RAM 41 1 and 440-pixel data of the first half segment I 1 of the chrominance component I in RAM 42 1 . Data stored in each of these input RAM's are retrieved at twice the data entry speed. RAM 46 1 is driven at 2/5 times the data entry speed to store 176 summed outputs of the luminance component Y 1 , while RAM 47 1 is driven at the same speed as RAM 46 1 to store 88 summed outputs of the chrominance component I 1 . In a similar manner, the input RAM's 41 2 and 42 2 of the second sub-unit 21B 2 store 880-pixel data of the luminance component Y 2 and 440-pixel data of the second half segment I 2 of the chrominance component I, respectively, the stored data being retrieved at twice the data entry speed. RAM 46 2 is driven at 2/5 times the data entry speed to store 176 summed outputs of the luminance component Y 2 , while RAM 47 2 is driven at the same speed as RAM 46 2 to store 88 summed outputs of the chrominance component I 2 . The third sub-unit 21B 3 operates in the same manner as the CIF conversion sub-unit 21A 4 of the previous embodiment. As will be seen from Fig. 7, the operation of the circuit of Fig. 6 differs from the embodiment of Fig. 4 in that 88-pixel data of the first half-segment of the chrominance component I 1 is written into input RAM 42 1 while the luminance components Y 1 stored in RAM 41 1 is being read for accumulation process. When all data are read out of RAM 41 1 and the processed data are stored into RAM 46 1 , the latter is driven in a read mode at a speed equal to the data writing speed to deliver the processed 176-pixel luminance component Y 1 to the bandwidth compression circuit 6. At the same time, RAM 42 1 is driven in a read mode at twice the data entry speed for processing the chrominance component I 1 and RAM 47 1 is driven in a write mode at 2/5 times the data entry speed to store 88 pixels of the processed I 1 chrominance component. On the other hand, similar processes proceed in the second sub-unit 21B 2 so that a processed version of the luminance component Y 2 is delivered to the bandwidth compression circuit 6 subsequent to the delivery of the luminance component Y 1 . The 88-pixel data of the processed chrominance component I 1 is read out of RAM 47 1 after an interval of 64 pixels following the end of delivery of the luminance component Y 2 , and the 88-pixel data of the processed chrominance component I 2 is read out of RAM 47 2 immediately following the end of delivery of the chrominance component I 1 . A processed version of the chrominance component Q is obtained in RAM 46 3 after a 64-pixel interval following the delivery of chrominance component I 2 and is sequentially read from RAM 46 3 , completing a CIF line output signal. The embodiment of Fig. 6 can be modified as shown in Fig. 8 by a shared use of a dual-port RAM for the entry of input data and the delivery of output data in a manner similar to the approach taken by the embodiment of Fig. 1. In Fig. 8, selectors 50 i and 51 i are provided in each of the CIF conversion sub-units 21C i (where i = 1 and 2) and a single selector 50 3 is provided in the third sub-unit 21C 3 . Each of these selectors has two input terminals, one being coupled to the output of multiplexer 3 and the other being coupled to the output of accumulator 45 i . Dual-port RAM's 52 i and 53 i are connected respectively to the outputs of selectors 50 i and 51 i , and a dual-port RAM 52 3 is connected to the output of selector 50 3 . Selector 54 i selectively applies one of the output signals from RAM's 52 i and 53 i to multiplier 43 i or bandwidth compression circuit 6. As seen in Fig. 9, following a write mode in which selectors 50 i are in their lower input position, these selectors are switched to the upper input position and RAM's 52 1 , 52 2 and 52 3 are driven in a read/write mode for processing 880-pixel Y 1 , Y 2 and Q component signals through selectors 54 1 and 54 2 . While data in RAM's 52 1 and 52 2 are being processed through their accumulators, the first and second half segments of chrominance components I 1 and I 2 are written into RAM's 53 1 and 53 2 , respectively. Upon completion of the accumulation processes on Y 1 and Y 2 data, selectors 51 1 and 51 2 are switched to the upper input position coupling the outputs of accumulators 45 1 and 45 2 to RAM's 53 1 and 53 2 , respectively, and selectors 54 1 and 54 2 are switched to the lower input position coupling the output of RAM's 53 1 and 53 2 to multipliers 43 1 and 43 2 , respectively, to proceed with the accumulation processes on the chrominance components I 1 and I 2 by driving RAM's 53 1 and 53 2 in a read/write mode. RAM 52 3 is driven in a read/write mode for processing chrominance component Q with selector 54 3 being switched to the upper output position. While the accumulation processes are being performed on signals from RAM's 53 1 and 53 2 , selectors 54 1 and 54 2 establish a path for coupling the outputs of RAM's 52 1 and 52 2 to the output terminal of the CIF converter. After an interval of 64 pixels following the end of delivery of the luminance component Y 2 , selector 54 1 is switched to the lower output position and the 88-pixel data of the processed chrominance component I 1 is read out of RAM 53 1 , and immediately following the end of delivery of the chrominance component I 1 , selector 54 2 is switched to the lower output position and the 88-pixel data of the processed chrominance component I 2 is read out of RAM 53 2 . A processed version of the chrominance component Q is obtained in RAM 52 3 after a 64-pixel interval following the delivery of chrominance component I 2 . When this occurs, selector 54 3 is switched to the lower output position and the contents of RAM 52 3 are read out of RAM 53 3 .

Claims: A common intermediate format CIF converter (4) for converting an input color television signal in an NTSC (National Television Standard Committee) or PAL (Phase Alternation by Line) system format into a CIF format, comprising: memory means (23); N multipliers (25) and N integrators (26,27) connected respectively to outputs of said N multipliers (25); characterized by : control means (28) for storing every group of five horizontal lines of said input color television signal into said memory means (23), for each of said groups transferring on a pixel-by-pixel basis first and second half segments of a luminance component (Y1 and Y2, respectively) of the stored lines and I and Q chrominance components (I and Q, respectively) of the stored lines from corresponding pixel positions of said memory means (23) to said N multipliers (25) at a speed higher than a writing speed at which said input signal is stored into said memory means (23), and supplying tap weight coefficients to said N multipliers (25), said tap weight coefficients having unique values corresponding to said five horizontal lines, said control means (28) further storing outputs of said N integrators (26,27) into said memory means (23) and sequentially transferring the stored outputs from said memory means (23) at said writing speed to an output terminal of said converter; and wherein N is smaller than five. A common intermediate format converter as claimed in claim 1, wherein the value N is four. A common intermediate format converter as claimed in claim 1, wherein said N multipliers comprise first, second and third multipliers (43), and said N integrators (44, 45) comprise first, second and third integrators connected respectively to outputs of said first, second and third multipliers, and wherein said control means (48) transfers from corresponding pixel positions of the stored lines at a reading speed higher than a writing speed at which said signal is stored into said memory means a first half segment of a luminance component and a first half segment of an I chrominance component of the signal to said first multiplier, a second half segment of the luminance component and a second half segment of the I chrominance component to said second multiplier, and a Q chrominance component of the signal to said third multiplier, and supplies said tap weight coefficients to said first, second and third multipliers (Fig. 6). A common intermediate format converter as claimed in claim 1, wherein said memory means (30) comprises first, second, third and fourth memories, said N multipliers (31) comprise first, second, third and fourth multipliers connected respectively to said first, second, third and fourth memories, and said N integrators (32, 33) comprise first, second, third and fourth integrators connected respectively to outputs of said first, second, third and fourth multipliers (31), and wherein said control means (35) stores first and second half segments of a luminance component of every five horizontal lines of said input color television signal into said first and second memories respectively and I and Q chrominance components of said five horizontal lines into said third and fourth memories respectively, transfers on a pixel-by-pixel basis signals in corresponding pixel positions of the five horizontal lines from said first, second, third and fourth memories at a speed higher than a writing speed at which said input signal is stored into each of said memories, and supplies said tap weight coefficients to said first, second, third and fourth multipliers, said control means further storing outputs of said first, second, third and fourth integrators into said first, second, third and fourth memories, respectively, and sequentially transfers the stored outputs from said first, second, third and fourth memories at said writing speed to said output terminal of said converter (Fig. 4). A common intermediate format converter as claimed in claim 4, wherein each half segment of said luminance component and each of the chrominance components has 176 pixels along each of the horizontal lines, wherein each of said first, second, third and fourth memory means comprises a first memory with a storage capacity of 880 words for storing 880 pixels of said color television signal and a second memory with a storage capacity of 176 words for storing 176 pixels of the output of a corresponding one of said integrators. A common intermediate format converter as claimed in claim 1, wherein said memory means comprise first, second, third, fourth and fifth memories (41, 42; 52, 53), said N multipliers (43) comprise first, second and third multipliers (43 1 -43 3 ), and said N integrators comprise first, second and third integrators (44, 45) connected respectively to outputs of said first, second and third multipliers (43), and wherein said control means (48) stores first and second half segments of a luminance component of every five horizontal lines of said input color television signal into said first and third memories respectively, first and second half segments of an I chrominance component of said five lines into said second and fourth memories respectively, and a Q chrominance component of said five horizontal lines into said fifth memory, transfers on a pixel-by-pixel basis signals in corresponding pixel positions of the horizontal lines from said first and second memories in sequence to said first multiplier, from said third and fourth memories in sequence to said second multiplier and from said fifth memory to said third multiplier at a speed higher than a writing speed at which said input signal is stored into each of said memories, and supplies said tap weight coefficients to said first, second and third multipliers, said control means further storing outputs of said first, second and third integrators into said first, second, third, fourth and fifth memories and transferring the stored outputs from said first, second, third, fourth and fifth memories at said writing speed to said output terminal of said converter (Fig. 8). A common intermediate format converter as claimed in claim 6, wherein each half segment of said luminance component and each of the chrominance components has 176 pixels along each of the horizontal lines, wherein each of said first, third and fifth memory means comprises a first memory with a storage capacity of 880 words for storing 880 pixels of said color television signal and a second memory with a storage capacity of 176 words for storing 176 pixels of the output of a corresponding one of said integrators, and wherein each of said second and fourth memory means comprises a first memory with a capacity of 440 words for storing 440 pixels of said color television signal and a second memory with a capacity of 88 words for storing 88 pixels of the output of a corresponding one of said integrators.

Inventors: KANOH TOSHIYUKI, MATSUMURA CHIZURU, SHIRATORI AKIHIRO, KANOH, TOSHIYUKI, MATSUMURA, CHIZURU, SHIRATORI, AKIHIRO, KANOH, TOSHIYUKI, C/O NEC CORPORATION, Matsumura, Chizuru, c/o NEC Engineering, Ltd., Shiratori, Akihiro, c/o NEC Engineering, Ltd.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H04N7
IPC codes: H04N7