Image processing method and apparatus

Abstract: The invention relates to an image processing method and apparatus in which the chromatic portion of a color image signal is outputted upon being substituted by a pattern or a luminance signal. The color of an inputted color image signal is identified by a color identifying circuit (107), and a pattern corresponding to the identified color is outputted by a pattern generating circuit (108). A pattern synthesizing circuit (105) outputs a corresponding pattern for a color portion of the color image signal. When a portion of the color image signal does not possess color, the pattern synthesizing circuit measures the distribution of a luminance signal in the color image signal and outputs an image signal the density of which conforms to the luminance distribution. In order that a base-color portion contained in the inputted color-image signal will not be converted into a pattern, the base color is judged by the luminance distribution and the base-color component is not outputted to the pattern generating circuit.

Description: This invention relates to an image processing method and apparatus. More particularly, the invention relates to an image processing method and apparatus for reading a color original, for example, and expressing differences in color by a black-and-white output in conformity with the particular color. A conventional method of expressing a difference in color by a difference in a pattern is described in, say, the specification of Japanese Patent Publication JP-B-6359303. According to this disclosure, colors in an original document are identified, patterns corresponding to the identified colors are selected from a memory storing a plurality of patterns, and the patterns are outputted in a single color. As a result, chromatic portions contained in the image of the original are reproduced in the form of corresponding patterns and all other portions are outputted in the form of luminance information. In the example of the prior art described above, however, when the luminance distribution of the entire document is sampled in the usual manner also when AE (automatic exposure) is applied, even areas (chromatic portions) of the document at which luminance information is not outputted are sampled. As a consequence, AE cannot be performed accurately. Further, in the case where a document has a background or base color, it is desired that this background-color portion is not converted into a pattern. In the prior art, however, the background-color is replaced by a pattern and printed when it is judged that the background of the document is chromatic. US Patent Specification US-A-4369461 discloses apparatus for forming images in which an original document is read while discriminating a predetermined colour portion so as to replace that portion with a pattern. However, this disclosure does not solve problems associated with the background or base colour of the original. The present invention has been devised in view of the foregoing drawbacks of the prior art and has as a concern to provide an image processing method and apparatus through which AE can be implemented in an accurate manner. In accordance with a first aspect of the present invention there is provided an image processing method as set out in claim 1. In accordance with a second aspect of the present invention there is provided image processing apparatus as set out in claim 5. An embodiment of the present invention provides an image processing method and apparatus through which AE processing can be executed in an accurate manner by sampling the luminance of a document in portions other than those that are chromatic. Another embodiment of the present invention provides an image processing method and apparatus through which the background-color of a document is prevented from being converted into a pattern. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. Fig. 1 is a sectional view illustrating the structure of a copying machine in which an image processing according to the present invention is used; Fig. 2 is a diagram for describing the diffraction grating of a CCD sensor; Fig. 3 is a block diagram illustrating the construction of an image processing circuit according to a first embodiment; Fig. 4 is a flowchart for describing the image processing procedure in an image processing circuit according to this embodiment; Fig. 5 is a block diagram showing the construction of a luminance-signal generator according to this embodiment; Fig. 6 is a block diagram showing the construction of a black correcting circuit of this embodiment; Fig. 7 is a block diagram showing the construction of a white correcting circuit of this embodiment; Fig. 8 is a block diagram showing the construction of an AE data sampling unit of this embodiment; Fig. 9 is a diagram for describing a color plane in a hue conversion; Fig. 10 is a block diagram showing the construction of a color identifying circuit in this embodiment; Fig. 11 is a block diagram showing the construction of a pattern generating circuit in this embodiment; Figs. 12A - 12F are diagrams showing the correspondence between colors and patterns; Fig. 13 is a block diagram showing the construction of a pattern synthesizing circuit in this embodiment; Figs. 14A - 14C are diagrams showing specific examples of a LOG conversion characteristic in this embodiment; Fig. 15 is a is a block diagram illustrating the construction of an image processing circuit according to a second embodiment of the present invention; Fig. 16 is a block diagram showing the construction of an image processing circuit according to another embodiment; Figs. 17A and 17B are block diagrams showing the construction of an AE data sampling unit in Fig. 16; Fig. 18 is a diagram showing an example of the luminance histogram of a character-document image which has a background color; Fig. 19 is a diagram showing an example of the data in a background-color correcting table; Fig. 20 is a block diagram showing the construction of a background signal processor in Fig. 16; Fig. 21 is a block diagram showing the construction of a white correcting circuit according to another embodiment; Fig. 22 is a flowchart for describing a white correction according to another embodiment; and Fig. 23 is a diagram showing an example of correction table data used by a LOG converter. Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Fig. 1 is a sectional view showing a copying machine which employs the image processing apparatus of this embodiment. The copying machine has a lower section which includes a printer 22, and an upper section which includes an image reader 3. The printer 22 includes a photosensitive drum 1 the surface of which has a photosensitive layer for electrophotography. The drum 1 is rotatively driven in the direction of arrow X. Disposed about the photosensitive drum 1 are a primary corona discharge device 4, a cleaning unit 5, a corona discharge device 6 and a developer 7. The image reader 3 reads the image of an original placed upon a glass platen and includes the glass plate 8, a lamp 9 for irradiating the original, scanning mirrors 10, 11, imaging lenses 12, a three-color separating blazed diffraction grating 13 and a CCD 14. A halogen lamp 9 for irradiating the original is adapted so as to perform scanning motion together with the scanning mirrors 10, 11. As a result, the original is scanned in the subordinate scanning direction at a preset fixed speed. Reflected light from the scanned original passes through the lenses 12 and then is converted into electric signals upon being separated into colors by the three-color separating blazed diffraction grating 13 and CCD 14. The signals obtained by thus reading the original are subjected to various image processing. Thereafter, laser light modulated by the image signal is emitted from a laser scanner unit 15, and the laser light is made to irradiate the photosensitive drum 1 by fixed mirrors 16, 17 whereby the image is exposed. Numerals 18, 19 denote copy cassettes in which copy paper is stacked, and numeral 20 denotes a conveyor belt for conveying copy paper, to which an image has been transferred by the corona discharge device 6, to a fixer 21. The CCD 14 has a solid-state image pick-up element array (a line sensor) comprising three lines corresponding to each of the colors R, G, B. The spacing between the line sensors corresponding to the three primary colors R, G, B is decided in conformity with the angle of view. Thus, the surface of the original is line-scanned by a mirror (not shown) disposed between the lenses 12 constituting the imaging optical system, the reflected image is separated into a three-color light flux in the color-image reading operation via the lenses 12 by means of the three-color separating blazed diffraction grating 13, and the resulting images are formed on the line sensors corresponding to the colors of the CCD 14. The general features of the three-color separating one-dimensional blazed diffraction grating 13 will now be described with reference to Fig. 2. The three-color separating one-dimensional blazed diffraction grating 13 is so structured that a step-shaped grating repeats periodically in each color-separating direction. For example, if the pitch P of the period is 60 µm, the grating thickness is d 1 = d 2 = 3100 µm and the refractive index of the medium is 1.5, then the incident light is transmitted and diffracted and separated into three directions, as shown in Fig. 2. Fig. 3 is a block diagram showing the overall construction of the image processor in a digital copying machine according to this embodiment. In Fig. 3, numeral 100 denotes an amplifier circuit for amplifying the output signal from the CCD image sensor 14 to obtain a signal of a prescribed amplitude. An A/D converter 101 converts the amplified image signal into a digital signal, and a black-correcting/white-correcting circuit 102 subjects the digital image signal to a black-level correction and a white-level correction (shading correction), described below. The amplifier circuit 100, A/D converter 101 and black-correcting/white-correcting circuit 102 are contained in an input image processing section 1000. A luminance-signal generating unit 103 generates a luminance signal from the digital image signals (R OUT , G OUT , B OUT ) that have undergone the black correction and white correction. An AE data sampling unit 104 samples luminance information when automatic exposure is carried out. Luminance information stored here is sampled by an CPU 110 to measure the luminance of the original. A pattern synthesizing circuit 105 combines the luminance signal sampled by the AE data sampling unit 104 and a pattern signal 116, which is outputted by a pattern generating circuit 108, indicating the particular color. A LOG converter 106 converts the signal outputted by the pattern synthesizing circuit 105 into a luminance signal and delivers the luminance signal to the printer 22. A color identifying circuit 107 identifies the color of each pixel of the digital color image signal that has undergone the black correction and white correction and delivers an identification signal 117 to the pattern generating circuit 108. The latter receives the identification signal 117 as an input and outputs the pattern signal 116, which is decided in conformity with each color, and a HIT signal 115. Numeral 110 denotes a CPU for controlling the overall apparatus, numeral 111 denotes a ROM storing programs for operating the CPU 110 as well as various data, and numeral 112 denotes a RAM used as a work area when the CPU 110 executes control processing. The copying operation performed by the copying machine having the foregoing construction will now be described. It is assumed here that the copying machine is a monochromatic copying machine in which the image of a color original is read and patterns corresponding to the colors of the original are printed, whereby the colors of the image of the original can be identified even though the printed image is monochromatic. Fig. 4 is a flowchart illustrating the copying operation performed by the copying machine of this embodiment. The image reader 3 reads a color original by causing the original to be scanned by the CCD sensor 14, which comprises the three lines R (red), G (green) and B (blue), and converts the read color image signals into analog electric signals (step S1). The analog image signals are amplified by the amplifier 100, after which they are sampled and held, subjected to a gray-level correction, adjusted in dynamic range and then A/D-converted into R, G, B signals by the A/D converter 101. The image signals thus converted into digital signals are subjected to a shading correction (step S2) by the black-correcting/white-correcting circuit 102 in dependence upon the light-receiving sensitivity of the CCD sensor 14. The digital image signals thus corrected (i.e., signals R OUT , G OUT , B OUT ) enter the luminance-signal generating unit 103, where they are converted into a luminance signal (step S3). As for the method of making the conversion to a luminance signal, the operation (R OUT + G OUT + B OUT ) x 1/3 is performed to produce the luminance signal, as shown in Fig. 5. In Fig. 5, numeral 301 denotes an adder for adding the color signals R OUT , G OUT , B OUT , and numeral 302 denotes a divider for dividing the sum from the adder 301 by 3 to obtain an average value of the three color signals. The luminance information thus produced is sent to the pattern synthesizer 105 via the AE data sampling unit 104. In a case where an ordinary copying operation is performed, the luminance information is converted into a density signal, which corresponds to the output density of the printer 22, by the LOG converter 106 via the AE data sampling unit 104 and pattern synthesizing circuit 105, and an image is outputted by the printer 22. The details of this operation will be described later. Meanwhile, the signals R OUT , G OUT , B OUT corrected by the black-correcting/white-correcting unit 102 are sent to the color identifying circuit 107. The latter judges the color area and type of color of each pixel of the image of the original and sends the pattern generating circuit 108 the identification signal 117, which is the result of the judgment (step S4). The pattern generating circuit 108 is constituted by memories such as a RAM and ROM and, in addition to the pattern signal 116 which conforms to the type of color of the identification signal 117, outputs the HIT signal 115, which is indicative of an area in which a color pattern conversion is performed. The HIT signal 115 is sent to the AE data sampling unit 104 (step S5). As a result, when the AE data sampling unit 104 samples the luminance information, the luminance information in an area other than that in which the HIT signal 115 is outputted, namely the luminance information outside an area in which the color pattern conversion is performed, is sampled. Thus, the arrangement is such that in the case of automatic exposure (AE), sampling is not performed in an area in which the sampling of luminance information is not required, i.e., in an area in which a pattern is outputted but luminance information is not (step S6). The HIT signal 115 and the pattern signal 116 outputted by the pattern generating circuit 108 enter the pattern synthesizing circuit 105, in which the luminance information and pattern signal 116 are combined and the chromatic portion of the original is changed into a pattern (step S7). More specifically, an image signal synthesized in such a manner that the pattern signal 116 is outputted for an image area in which the HIT signal 115 is outputted (namely a color area for which a corresponding pattern exists) and the luminance information is outputted for an area in which the HIT signal 115 is not outputted (namely a color area for which a corresponding pattern does not exist) is converted from luminance to density by the LOG converter 106 and is then sent to the printer 22 (step S8), as described earlier. Each component used in executing the image processing of this embodiment shown in Fig. 3 will now be described in succession. [Black-correcting/white-correcting circuit] Fig. 6 is a diagram showing the construction of a black correcting circuit in the black-correcting/white-correcting circuit 102 of this embodiment. The digital color image signal obtained from the CCD image sensor 14 upon being A/D-converted exhibits a large disparity between pixels when the quantity of light which enters the CCD image sensor 14 is very small. If this signal were to be outputted as in the form of an image, streaks or irregularities would develop in the digital image signals. This makes it necessary to correct for the disparities in the output of the black portion. The correction is made by the circuit of the kind shown in Fig 6. Before the reading of the original, the original scanning unit in the image reader 3 is moved up to a black-color board, which possesses average density, disposed in a non-image area at the leading edge of the glass plate 8. The lamp 9 is then turned on and an image signal indicative of the black level is inputted to the black correcting circuit. With regard to a circuit 77aB relating to a blue signal B IN , the A input of a selector 82a is selected, a gate 80a is closed and a gate 81a is opened in order to store one line of the image data in a black-level RAM 78a. More specifically, the data line is connected in the manner 151a → 152a → 153a. Meanwhile, a signal 623 applied to a selector 83a is produced in order that an output 154a of an address counter 84a, which is initialized by HSYNC and counts VCLK, will enter an address input 155a of the RAM 78a. As a result, one line of the black-level signal is stored in the RAM 78a. (The foregoing mode of operation is referred to a black reference-value reading mode.) Thus, when an image is actually read in, the RAM 78a assumes a data read-out mode and the black reference value of the RAM 78a is read out and inputted to the B input of a subtractor 79a every line and every pixel via a path composed of data lines 153a → 157a. That is, the gate 81a is closed and the gate 80a is open at this time. In addition, a selector 86a delivers an A output. Accordingly, an output 156a from the black correcting circuit is obtained as B IN (i) - DK(i) = B OUT (i) with respect to black-level data DK(i) in case of, say, a blue signal (this mode is referred to as the black correction mode). Similarly, green G IN and red R IN are controlled by 77aG and 77aR, respectively. In order to execute control, control lines 621 - 625 of each selector gate are placed under the control of the CPU 110 (Fig. 3) by a latch 85a assigned as the I/O of the CPU 110. By selecting the B inputs of the selectors 82a, 83a and the B output of the selector 86a, the RAM 78a can be accessed by the CPU 110. Fig. 7 is a block diagram showing the construction of the white correcting circuit in the black-correcting/white correcting circuit 102 according to this embodiment. When the CCD 14 for reading the original is at the reading position (home position) of a uniform white board at the time of a color correction (i.e., prior to a copying operation or reading operation), the exposure lamp 9 is turned on, the A input is selected by a selector 182a, a gate 180a is closed and a gate 181a is opened in order to store pixel data of a uniform white level in, say, a correcting RAM 178a for one line. Thus, the data line is connected in the manner 1151a → 1152a → 1153a. Meanwhile, an A input to a selector 183a is produced in order that an output 1154a of an address counter 184a, which is initialized by HSYNC and counts VCLK, will enter an address input 1155a of the RAM 178a. As a result, one line of the white-level signal (white reference value) is stored in the RAM 178a. If the main scanning direction has the length of an A4 sheet of paper longitudinally, then the capacity of the RAM 178a that will be required is 4752 (= 16 x 297 mm) pixels (W 0 ∼ W 4751 ) at 16 pel/mm, i.e., at least 4752 bytes. Next, in a mode (hereinafter referred to as the ordinary mode) other than the pattern substituting mode, in which a color area of a read image is substituted by a pattern, the image data is eight bits with regard to a read value D i of an i-th pixel corresponding to W i . Therefore, data D 0 following a correction should become D 0 = D i x FFH/W i using the shading correction coefficient P 0 = FFH (where H represents a hexadecimal number). When the pattern substituting mode is in effect, the corrected data D 0 ' with respect to the read value Di of an i-th pixel corresponding to W i should be as follows, where the shading correction coefficient is P 1 : D 0 ' = x 0 ≤ x ≤ FFH = FFH x > FFH x = D i x P/W i x ≥ 0 where P i > FFH With regard to the correction coefficient P 1 , this is obtained by scanning and reading the original image in advance, as described in the explanation of the AE data sampling unit 104, set forth below. Further, with regard to the data sampling operation and a histogram of the sampled data, the background level of the image is "DOH", as will be described later with reference to Figs. 17 ∼ 19, and therefore the above-mentioned correction coefficient P 1 is as follows: P 1 = (FFH/DOH) x FFH = 138H In other words, if the background level is represented by B0 H , we have P 1 = (FFH/B0 H ) x FFH The correction table is as shown at 3 ○ in Fig. 19, and the output level is "FFH" at the input level "BOH". As a result, the background of the image fades. Accordingly, signals 701 ∼ 705 from latch 185a are set by the CPU 110 so as to open gates 180a, 181a and select the B input of selectors 182a, 183a and the B output of selector 186a, and the RAM 178a is made accessible by the CPU 110. Next, the CPU 110 successively performs the operations FFH/W 0 , P 1 /W 0 with respect to the leading pixel W 0 of the data in RAM 178a, performs the operations FFH/W i , P 1 /W i ··· with respect to W i , stores the correction value for the ordinary mode in RAM 178a and stores the correction value for the pattern substituting mode in the RAM 187a. To this end, when the data for the ordinary mode is stored, the B input of selector 183 is selected, gate 181a is opened, gates 189a, 180a, 188a are closed and the correction value is written in RAM 178a. On the other hand, in order to store the data for the pattern substituting mode, it will suffice to close gates 181a, 180a, 188a, open gate 189a and write the correction value in RAM 187a. When the processing for the blue component of the color-component image thus ends, writing is performed in similar fashion in the RAMs corresponding to the circuits 177aG, 177aR of the green and red components, respectively. Next, operation in the case of the ordinary mode (in which pattern substitution is not carried out) will be described. Gate 180a is opened, gates 188a, 181a, 189a are closed and data FFH/Wi is read out of the RAM 178a. As a result, the data enters a multiplier 179a through 1153a → 1157a so that this data is multiplied by the original image data 1151a inputted to the other terminal of the multiplier 179a. The output of the multiplier 179a is the product. On the other hand, when the pattern substituting mode is in effect, the gates 180a, 181a, 189a are closed and the gate 188a is opened, whereby data P 1 /W i is read out of the RAM 187a and inputted to the multiplier 179a through 1158a → 1157a so that this is multiplied by the original image data 1151a inputted from the other terminal. The output of the multiplier 179a is the product. Here it is assumed that the multiplier 179a is so designed that its output will be FFH if the result of calculation exceeds FFH. Control for changing over the gates can be performed by the CPU 110 before reading of the original owing to the fact that it is known whether processing applied to this original will carry out pattern substitution or not. [Description of AE data sampling unit 104] The AE data sampling unit 104 will now be described. Fig. 8 is a block diagram showing the construction of the AE data sampling unit 104 according to this embodiment. Shown in Fig. 8 are a counter 601, selectors 602, 604, a RAM 603, a flip-flop 605, and a buffer 606. The counter 601 generates an address when luminance information is stored in the RAM 603. When the selector signal 601 is "1", the selector 602 selects the address from the counter 601 and outputs the address to the RAM 603 so that the luminance information selected by the selector 604 is stored in the RAM 603. At this time, the luminance signal in which the HIT signal is set to the MSB is selected. Thus, the luminance information is stored in the RAM 603. In other words, the luminance information is sampled. Since the luminance signal and the HIT signal whose delay relationship has been adjusted are stored in the MSB of the data in RAM 603, it can be judged whether this data is luminance information of an area judged to have color. Next, when the CPU 110 reads the data in RAM 603, a select signal 610 is made "0" and the address data from the CPU 110 is inputted to the RAM 603. When the CPU 110 performs the reading operation, the gate of buffer 606 is opened and the data in RAM 603 is read. When the luminance information is outputted to the pattern synthesizing circuit 105, the selection signal 610 is made "1", the luminance signal is outputted by the selector 604 and is delivered to the pattern synthesizing circuit 105 via the flip-flop 605. The clock of the flip-flop 605 is VCK (a video-transfer clock), and the clock of the counter 601 also is VCK. More specifically, the luminance signal stored temporarily in the RAM 603 of the AE data sampling unit 104 is read by the CPU 110. Since the data in which the MSB of the read data is "1" is within an area judged to have color, this data is discarded and AE data is created merely by the luminance signal outside the area judged to have color. The color identifying circuit 107 will now be described. In this embodiment, a hue signal is used in the color identifying method. The reason for this is that accurate judgments can be made even in a case where color is the same but vividness and brightness differ. The general features of the color detecting method in the color identifying circuit 107 will be described first. Fig. 9 is a diagram for describing a color plane in a hue conversion. The inputted items of R, G, B data each consist of eight bits and therefore possess information indicative of a total of 2 24 colors. Consequently, using such a massive amount of information as is would involve extremely high cost in terms of the scale of the circuitry. In this embodiment, the above-mentioned hues are used. Strictly speaking, these hues differ from those expressed ordinarily but shall be referred to as hues here just the same. It is known that color space is expressed by saturation, luminosity and hue, as is known in a Munsell color solid or the like. It is necessary that R, G, B data first be converted into a plane, i.e., two-dimensional data. Since the portions that R, G, B have in common, namely the minimum values min(R,G,B) of R, G, B are achromatic components, min(R,G,B) is subtracted from each of the R, G, B data and the remaining information is used as the chromatic components, whereby the three-dimensional input color space is converted into two-dimensional color space. As shown in Fig. 9, the plane resulting from the conversion is divided into six portions from 0° to 360°, and the hue values are obtained using a LUT (look-up table) or the like in accordance with the order of magnitudes of the inputted R, G, B, namely the information R>G>G, R>B>G, G>B>R, G>R>B, B>G>R, B>R>G, and the maximum values and intermediate values among the inputted R, G, B. The construction of the color identifying circuit 107 will now be described. Fig. 10 is a block diagram showing the construction of the color identifying circuit 107 according to this embodiment. Shown in Fig. 10 are a max-mid-min detecting circuit 401, subtractors 402, 403, a hue detecting circuit 404, color judging circuits 415, 416, window comparators 405, 406, an AND gate 410, and a CPU 407. The color judging circuits 415, 416 are identical in construction. The operation of the color identifying circuit 107 will be described next. The inputted items of R OUT , G OUT , B OUT data enter the max-mid-min detecting circuit 401, which discriminates the magnitudes of these items of data. The detecting circuit 401 compares these items of input data using a comparator and outputs a max (maximum) value, mid (middle) value and min (minimum) value in dependence upon the results of processing. Each output value of the comparator is delivered as a ranking signal 420. Since the achromatic components are subtracted from the max value and mid value, as described above, the min value, which is the smallest, is subtracted from the max value and mid value by the subtractors 402, 403, respectively, and the difference signals that result are applied to the hue detecting circuit 404 along with the ranking signal 420. The hue detecting circuit 404 is a memory element which is randomly accessible, such as a RAM or ROM. In this embodiment, the detecting circuit 404 constructs a look-up table using a ROM. Values corresponding to the angle of the plane of the kind shown in Fig. 9 are stored in the ROM in advance. Hue values are outputted depending upon the inputted ranking signal (max - min) value and the (mid - min) value. The outputted hue value is inputted to the window comparators 405, 406. Values that have been set in the window comparator 405, 406 are such that when a hue value of color data originally desired to be converted into a pattern is inputted by data input means (not shown), the hue data value is set by the CPU 407 as an offset value with respect to this hue value. If the value set in the comparator 405 is a1, the comparator 405 will output "1" when (hue data) < a 1 holds with regard to the hue data inputted from the hue detecting circuit 404. If the value set in the comparator 406 is a 2 (a 1 >a 2 ), the comparator 406 will output "1" when (hue data) > a 2 holds. As a result, the AND gate 410 outputs "1" when a 1 > (hue data) > a 2 holds, and this serves as the output of the color judging circuit 415. By virtue of an operation similar to that performed by the color judging circuit 415, a color different from that judged by the color judging circuit 416 is judged by the color judging circuit 416. In this embodiment, the arrangement is such that two types of colors are judged. However, the invention does not limit the types of colors to two; three or more can be judged. [Pattern generating circuit] The pattern generating circuit 108 will now be described. Fig. 11 is a block diagram showing the construction of the pattern generating circuit 108 according to this embodiment, and Figs. 12A - 12F are diagrams showing the correlation between the colors of the image of an original and outputted patterns. In Fig. 11, numeral 801 denotes a subordinate-scanning counter, numeral 802 denotes a main-scanning counter and numeral 803 denotes a ROM for patterns. Dot patterns corresponding to the colors of the kinds shown in Figs. 12A - 12F are written in the pattern ROM 803 in advance. As shown in Figs. 12A - 12F, the pattern of each figure consists of pattern data of 16 x 16 dots. The pattern ROM 803 generates patterns by the repeatedly outputting patterns corresponding to the color identification signal 117 in accordance with the signals from the main-scanning counter 802 and subordinate-scanning counter 801. The main-scanning counter 802 is loaded to an initial value by a horizontal synchronizing signal HSYNC and counts a video clock CLK so as to generate addresses in the main-scanning direction. The subordinate-scanning counter 801 is loaded to an initial value by an ITOP signal and counts the horizontal synchronizing signal HSYNC, thereby outputting addresses in the subordinate-scanning direction. The outputs of the counters 801, 802 each consist of four bits, and the color identification signal 117 consists of five bits. Thus, data consisting of a total of 13 bits enters the the ROM 803 as an address. In other words, the arrangement is such that a pattern consisting of 16 x 16 dots can be generated with regard to 32 types of read colors. The output from the pattern ROM 803 has a data length of eight bits, in which the MSB (the most significant bit) is used as the control signal (HIT signal 115) within the pattern synthesizing circuit 105, described later. The data is written in so that this MSB usually is "0" but always becomes "1" when a pattern is generated. It should be noted that the pattern ROM 803 may be substituted by a memory that is capable of being rewritten, such as a RAM. If a RAM or the like is used, the capacity thereof and the bit assignment of the address are the same is in the case of the ROM. [Pattern synthesizing circuit] The construction of the pattern synthesizing circuit 105 will now be described. Fig. 13 is a block diagram illustrating the construction of the pattern synthesizing circuit 105 according to this embodiment. In Fig. 13, numeral 501 denotes a selector which selects, in accordance with the HIT signal 115 from the pattern generating circuit 108, the luminance signal sampled by the AE data sampling unit 104 or the pattern signal 116 generated by the pattern generating circuit 108. Since an area for which the HIT signal 115 is "1" is an area in which the image of the original is judged to be chromatic, the pattern signal 116 corresponding to the color is selected and outputted to the LOG converter 106. For an area in which the HIT signal 115 is "0", the luminance signal is outputted to the LOG converter 106 as is. [LOG converter] The construction of the LOG converter 106 will be described next. The LOG converter 106 is constituted by a look-up table comprising a ROM or a RAM. For the sake of simplicity, the LOG converter 106 is assumed to be a ROM in this embodiment. The CPU 110 selects a suitable LOG conversion table from the sampled AE data and performs a LOG conversion. Figs. 14A - 14C are diagrams showing specific examples of the LOG conversion characteristics in the LOG converter 106 according to this embodiment. In Figs. 14A - 14C, Fig. 14A represents a conversion characteristic in which there is a linear conversion characteristic between input density and output density. Further, and by way of example, if an original is judged to be one having characters or the like and it is desired to eliminate the fog on white background of the original when sampling the AE data, a LOG characteristic of the kind shown in Fig. 14B is selected. In other words, in a case where the input density is rather high (white), the output density is replaced by "0", namely white, to eliminate the fog. If a certain constant density level is concentrated within the original when sampling the AE data, the characteristic shown in Fig. 14C is selected to widen the dynamic range of a certain density level. In accordance with the embodiment as described above, it is determined when performing a color-pattern conversion whether sampled luminance information lies within an area judged to have color. When the information does not lie in within this area and AE is applied, the luminance distribution of the entire original is sampled and a color-pattern conversion is performed. When the luminance information of the original lies within an area judged to have color, the sampled luminance information for AE is not used, thereby making it possible to realize accurate AE. <Second Embodiment> As a second embodiment of the invention, AE in a case where a difference in color is expressed by a difference in monochromatic density will be described. The basic concept of this embodiment is similar to that of the first embodiment described above. Precise AE is applied by discarding AE sampling data within an area in which a color-density conversion is performed. As for the circuitry of this arrangement, it will suffice to replace the pattern generating circuit 108 by a luminance generating circuit 721 (See Fig. 15) and write luminance data, which corresponds to each color, in the pattern ROM 803 instead of patterns corresponding to each of the colors. <Third Embodiment> A third embodiment of the invention will now be described. With regard to AE in a case where a color-density conversion is made, the third embodiment is such that sampling of luminance information for carrying out AE is performed by sampling the luminance of the original as is with regard to an area in which a conversion of color density is not made, and sampling the luminance information of the image after conversion with regard to an area in which the conversion of color density is made, whereby the end result is that accurate AE is applied to the output image. Such a case will now be described. By way of example, in a case were density after conversion of color density is close to black, the entire output image becomes relatively blacker by a corresponding amount, whereby an effect is obtained in which AE is applied to the overall output image. Fig. 15 is a block diagram illustrating the construction of an image processing apparatus according to the third embodiment of the present invention. In Fig. 15, numeral 721 denotes a luminance generating circuit which, in a manner similar to that described in connection with the second embodiment, is so designed that luminance data corresponding to colors is written in a pattern ROM 803 instead of patterns. Numeral 722 designates a luminance synthesizing circuit which selects, in accordance with the HIT signal, a luminance signal indicative of the original and generated by the luminance-signal generating unit 103, or a luminance signal 723 in which a difference in color is expressed as a difference in luminance. This can be realized by replacing the pattern signal 116, which enters the selector 501 in Fig. 13, by the luminance signal 723 from the luminance generating circuit 721. Numeral 720 denotes an AE-data sampling unit which, unlike the AE-data sampling unit 104 described in the first embodiment, is supplied with an input of the discrimination signal 117 indicating the type of color discriminated by the color discriminating circuit 107. This discrimination signal 117 is inputted to bits other than the bit of the HIT signal, which is the MSB. For example, if the RAM 603 has an eight-bit construction, bit 7 is the HIT signal, bits 5, 6 are for the discrimination signal 117, and bits 0 ∼ 4 are for the luminance signal from the luminance-signal generating unit 103. Though the delay relationships among the HIT signal, color-category signal and luminance signal are not shown, all of the delay relationships are made to conform when this arrangement is actually realized. The above-mentioned embodiment is such that when the entirety of an original has a background color such as light pink or the like, the background color also is replaced by a pattern so that the entire surface of a sheet that has been printed out takes on the form of a pattern image. As a result, the image is extremely difficult to see. An embodiment will now be described in which an output image converted into an excellent pattern can be obtained even if the original is of the above-mentioned kind. Fig. 16 is a block diagram showing the construction of an image processor according to a fourth embodiment of the present invention. When AE prescanning is performed, a CPU 110a in Fig. 16 causes an AE data sampling unit 730 to produce a histogram (see Figs. 17A and 17B) of the density of the original using a RAM 101a. The basic circuit operation of the AE data sampling unit 730 is the same as in the first embodiment described above. The AE data sampling unit 730 will be described with reference to Figs. 17A and 17B. An image signal I out , which has been subjected to a shading correction and converted into a luminance signal by the input image processing section 1000, is sampled line by line by the AE data sampling unit 730, and the level of this signal is read by the CPU 110a, which creates a histogram. As a result, the level limits of the read image data are detected and an AE correction in which the color of the background level of the original is not identified is applied. The sampling of the image data is carried out by the circuit shown in Figs. 17A and 17B. It should be noted that the sampling of the image data in the above-described AE correction is performed by prescanning the image of the original before the actual operation for reading the original image. That is, a gate 2103 is opened by a signal 1701 and a gate 2104 is closed by a signal 1702 in order that one line of the image data I out , which has been subjected to the shading correction and converted into the luminance signal I out , may be stored in a RAM 2105. More specifically, the data line takes on the form 2110 → 2111. Meanwhile, a selection signal 1700 applied to a selector 2102 is produced in order that an output 2113 of an address counter 2101, which is initialized by an inverted HSYNC signal and counts VCLK, will enter an address input 2112 of the RAM 2105. As a result, one line of the luminance signal data is stored in the RAM 2105. (The foregoing mode of operation is referred to an image-data sampling mode.) When an image is read in, the RAM 2105 is placed in a data read-out mode and one line of sampled image data is read in to the CPU 110a of Fig. 16 through a data bus (D-Bus) via the path composed of data line 2111 → 2115. At this time the image data read in the CPU 110a is not all of the pixel data of one line. Rather, one pixel every millimeter, i.e., every 16 pixels, for data of 293 pixels/line in the longitudinal direction of an A4 original, is read in the CPU 110a. Furthermore, in the subordinate scanning direction, the above-mentioned image-data sampling mode is executed at an interval of 1 mm, namely once every 16 lines, just as in the main scanning direction. For an original whose size is A4, the number of pixels of data sampled is as follows: 293 pixel/line x 206 lines = 60358 pixels. At this time the gate 2103 is closed by the selection signal 1701 and the gate 2104 is opened by the selection signal 1702. In addition, the selector 2102 selects the B input of the address bus (A-Bus) of CPU 110a in accordance with the selection signal 1700 and an address enters the address input of the RAM 2105 via the path composed of address lines 2114 → 2112. Here the selection signals 1700 - 1702 of the selector gates for the present control operation are outputted from a latch circuit 2106 allocated as the I/O of the CPU 110a. The data sampled in the case of an A4 original is processed by the CPU 110a and a histogram is produced in the manner described above. For example, in the case of an original such as a newspaper, in which the background is somewhat dark and characters or the like are included, a histogram of the kind shown in Fig. 18 is produced. More specifically, as shown in Fig. 18, a peak in the luminance of a background appears in the luminance-data value "EOH", and a peak in the luminance of a character portion appears in the luminance-data value "25H". Accordingly, if the color of the background is suppressed in order to inhibit the formation of a pattern, merely subjecting the luminance signal I out to a correction of the kind which makes the peak value "EOH" of the background become "FFH" causes the distribution of the histogram of the background to become a Gaussian-type distribution. As a result, it becomes impossible to effect complete elimination of the background. In consideration of the parameter 1 (H = 1OH) of the spread of the base of the histogram distribution of the background, a correction [2 ○ in Fig. 19) is applied such that "DOH" will become "FFH". In this embodiment, the correction indicated at 2 ○ in Fig. 19 is added to the LOG table of the abovementioned LOG converter 106. In Fig. 19, the characteristic 1 ○ is the usual; 2 ○ illustrates values of the table in which the image level "DOH" is converted to "FFH" (white); and 3 ○ illustrates values of the table in which a dark image "BOH" of the background is converted to "FFH" to eliminate the background. Fig. 20 is a block diagram showing the construction of the background-signal processor 731 of this embodiment. The processor is constituted by a comparator 141, a register 142 and an AND gate 143, as shown in Fig. 20. In operation, the CPU 101a sets the value "DOH" of the background level obtained by the aforementioned AE prescanning in the register 142 before the present scan. At the time of the present scan, the comparator 141 compares a video signal produced by the luminance signal generating unit 103 and the value "DOH" set in the register. If the video signal is smaller, i.e., darker, than the set value "DOH", a high-level signal is outputted to the AND gate 143. If the video signal is greater, i.e., brighter, than the set value "DOH", a low-level signal is outputted to the AND gate 143. In this way the color identification signal 117 outputted by the color identifying circuit 107 is turned on and off. The color identification signal 117 controlled in this manner is outputted to the pattern generating circuit 108, which is the next stage. Subsequent operation and control are the same as in the foregoing embodiments and need not be described again. In addition, this arrangement is applicable also to the above-described arrangement in which color is converted to luminance. Thus, AE is realized by adopting "DOH" - "FFH" as the luminance-signal area of the background and suppressing output of image data in this area. Thus, in accordance with the fourth embodiment, the background color of the original is detected and a pattern is not formed with respect to this background color. As a result, solely an image of the necessary location is converted into a pattern to provide an image that is easy to view. [Other embodiment of the white correcting circuit of the black-correcting/white correcting circuit] Fig. 21 is a block diagram showing the construction of another embodiment of a white correcting circuit of the black-correcting/white-correcting circuit according to the present invention. Portions similar to those in the white correcting circuit of the foregoing embodiment shown in Fig. 7 are designated by like reference characters and need not be described again. Here a multiplier 190a is inserted between a multiplier 179a and B out , and a signal from the data bus (D-Bus) enters the multiplier 190a via the register 191a. Control is performed in the same manner as in the example of the prior art up to the output of Di x FFH/Wi on signal line 1156a from the multiplier 179a. From this point onward, the CPU 110 sets data "1" in the register 191a in the ordinary mode so that this is outputted to B input of multiplier 190a. In the pattern substituting mode, the CPU 101 sets a signal corresponding to "P 1 /FFH", for example, in the register 191a so that this is outputted to the B input of the multiplier 190a. As a result, D i x FFH/W i is outputted at B out when the pattern substituting mode is not in effect and D i x P 1 /W i is outputted at Bout when the pattern substituting mode is in effect. Here the design is such that the multiplier 190a will output "FFH" if the result of the arithmetic operation exceeds "FFH". It should be noted that the method of obtaining the correction coefficient P 1 and the data in the correction table of the LOG converter 106 are the same as in the foregoing embodiment. In another possible embodiment of the white correcting circuit, control is the same as above up to the point where the CPU 110 is capable of accessing the data in the RAM 178a. From this point onward, in the ordinary mode, the CPU 110 performs calculations successively in the manner FFH/W 0 with regard to the leading pixel W 0 , FFH/Wi with regard to the next pixel W i , etc., and outputs the results. In the pattern substitutiing mode, if P 1 represents a correction coefficient greater than "FFH", the CPU 110 performs calculations successively in the manner P 1 /W 0 with regard to the leading pixel W 0 , P 1 /W i with regard to W i , etc., thereby performing a data substitution. This procedure is illustrated in the flowchart of Fig. 22. It should be noted that the present invention may be applied to a system composed of a plurality of devices or to an apparatus comprising one device. It goes without saying that the present invention can be applied also to a case where the above-mentioned effects are attained by supplying a program to a system or apparatus. In accordance with the present invention, as described above, the arrangement is such that when AE is applied, the luminance distribution of the entire original is sampled and is effectively converted into color patterns. With regard to areas in which the luminance signal of the original is not reflected in the output, it is possible to discard the AE sampling data. This makes it possible to realize accurate AE.

Claims: An image processing method comprising: reading (14) a colour image to generate colour signals representative of the image; processing (1000) the colour signals; detecting (103) luminance information of each pixel of the input image from the colour signals; discriminating (730) from the luminance information a threshold of background luminance of the colour image; identifying (107) the colour of each pixel of the input image from the colour signals; converting (108) the colour of each pixel of the image as represented by the colour signals into a corresponding pattern if the luminance of said pixel exceeds said threshold; and in response to the output of the conversion means and the detection means synthesising (105, 722) an output image signal from the pattern and the luminance information whereby the pattern is output in areas in which the luminance exceeds said threshold, and the luminance information is output in areas in which the luminance does not exceed said threshold. A method according to claim 1, wherein the image output is a monochrome image, the luminance data of the colour signal is sampled and in response to this sampling the base colour is output with a luminance distribution corresponding to the sampled luminance data. A method according to claim 1 or 2, wherein said discriminating step determines the frequency of occurrence of each signal included in the colour image signal; and discriminates the base colour in accordance with the frequencies so determined. A method according to claim 3, wherein the determining step determines the frequency of occurrence of luminance signals included in the colour image signal. An image processing apparatus comprising: means (14) for reading a colour image to generate colour signals representative of the image; means (1000) for processing the colour signals; means (103) for detecting luminance information of each pixel of the input image from the colour signals; means (730) for discriminating from the luminance information a threshold of background luminance of the colour image; means (107) for identifying the colour of each pixel of the input image from the colour signals; means (108) for converting the colour of each pixel of the image as represented by the colour signals into a corresponding pattern if the luminance of said pixel exceeds said threshold; means (105, 722) operative in response to the output of the conversion means and the detection means for synthesising an output image signal from the pattern and the luminance information whereby the pattern is output in areas in which the luminance exceeds said threshold, and the luminance information is output in areas in which the luminance does not exceed said threshold. Apparatus according to claim 5, wherein the output means output a monochrome image, the processing means include means for sampling the luminance data of the colour signals and the luminance distribution of the base area is determined in accordance with the output of said sampling means. Apparatus according to claim 6, wherein the discriminating means determine the frequency of appearance of each signal included in the colour signals and discriminates the base colour in accordance with the frequencies so determined. Apparatus according to claim 7, wherein the discriminating means determines the frequency of occurrence of luminance levels in the colour component signals.

Inventors: HASEGAWA SHIZUO, ICHIKAWA HIROYUKI, SUGIURA TAKASHI, TASHIRO HIROHIKO, HASEGAWA, SHIZUO, ICHIKAWA, HIROYUKI, SUGIURA, TAKASHI, TASHIRO, HIROHIKO, HASEGAWA, SHIZUO, C/O CANON KABUSHIKI KAISHA, ICHIKAWA, HIROYUKI, C/O CANON KABUSHIKI KAISHA, Sugiura, Takashi, c/o Canon Kabushiki Kaisha, Tashiro, Hirohiko c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N1
IPC codes: H04N1, G03G15, G06T1, G06T5