Multi-stage amplifier with capacity nesting and multi-path forward feeding for frequency compensation

Abstract: A multi-stage amplifier utilizes capacitive nesting of three or more amplifier stages in combination with multiple feedforward paths to achieve frequency compensation. Two stages (A M and A o ) in cascade are first nested with a pole-splitting capacitor (C1) to form a stable device. A stable three-stage amplifier is then created by nesting the two-stage device and a further stage (A I ) with another pole-splitting capacitor (C2) where feed-forward paths are provided from the further stage to both of the other stages.

Description: Field of use This invention relates to multi-stage amplifiers having frequency compensation and that are suitable for operational amplifiers made in semiconductor integrated circuit form and more particularly to an amplifier comprising: input means that amplifies an input signal received at least partly at an input to produce a main output signal at a main output thereof; intermediate means that amplifies an input signal received at least partly at an input coupled to the main output of the input means to produce a non-inverted output signal at an output thereof ; output means that amplifies an input signal received at least partly at an input coupled to the output of the intermediate means to produce an output signal at an output thereof ; a first capacitor coupled between the input of the output means and a node coupled to (a) the output of the output means if its output signal is inverted or (b) a source of a reference voltage if the output signal of the output means is non-inverted; and a second capacitor coupled between the input of the intermediate means and the node. Such amplifier is known from U.S. Patent 4,559,502 (= EP-A-0 159 099). Background art An operational amplifier ("op amp") is an electronic circuit that amplifies an input signal differentially supplied between a non-inverting input terminal and an inverting input terminal to produce an amplified output signal at an output terminal. An op amp is typically employed in an amplifier system having a feedback network connected between the output terminal (or simply "output") and one or both of the input terminals (or simply "inputs"). The gain in the negative feedback loop is -µβ, where µ is the forward gain of the op amp, and β is the gain of the feedback network. When the input signal varies at some frequency, the output signal varies similarly. At low frequency, the two signals are substantially in phase. As frequency increases, the phase of the output signal falls progressively behind that of the input signal. The magnitude of the loop gain decreases. If the phase difference between the signals reach 180° while |µβ| is greater than 1, the feedback becomes positive. The system oscillates and is thus unstable. The minimum acceptable stability margin is considered to occur when the loop phase difference equals 135° at the point where |µβ| is 1. Because the feedback network for a system utilizing an op amp is generally provided after op amp design is completed, the design is typically based on the "worst-case" assumption that β is 1. This leads to the stability criterion that forward gain µ not roll off more than 9 dB/octave out to the unity-gain frequency. An easy way to meet the preceding stability rule is with a single transconductance amplifier stage. Turning to the drawings, Fig. 1 illustrates a conventional bipolar differential stage A of this type. Input voltages V I+ and v I- , whose difference is amplifier input signal V I , are respectively supplied to the non-inverting and inverting inputs of stage A. Its non-inverting output provides amplifier output voltage V o . The frequency response of stage A is largely determined by a single dominant pole dependent on the parasitic capacitance CP at the output. Fig. 2 shows asymptotes for how µ varies with frequency f for stage A. The gain drops 6 dB/oct. as the frequency f o of the dominant pole is passed and then 6 dB/oct. more as the higher pole frequency f L that limits the bandwidth is passed. Bandwidth-limiting frequency f L , which is a characteristic of the overall amplifier system and cannot readily be altered, occurs beyond unity-gain frequency f U . Stage A thereby automatically satisfies the stability criterion. Unfortunately, the maximum gain is typically on the order of 40 dB. This is much too low for many applications. The gain can be increased by cascading two amplifier stages A I and A o as shown in Fig. 3. Output stage A o functions as an inverter. A capacitor C connected across stage A o provides frequency compensation for the amplifier. Fig. 4 shows a typical asymptotic frequency response for the two-stage amplifier in Fig. 3. Two dominant poles, represented by pole frequencies f o and f I which respectively depend on the parasitic capacitances at the A o and A I outputs, largely determine the frequency characteristics. The gain roll-off increases 6 dB/oct. in passing each of frequencies f o , f I , and f L . The upper curve in Fig. 4 shows how the asymptotic frequency response would appear if capacitor C were absent. The lower curve shows the actual compensated asymptotic response. In the absence of capacitor C, the combination A I and A o would not meet the stability rule because µ drops 12 dB/oct. between f I and the unity-gain frequency. Capacitor C splits the dominant poles further, causing f I to move beyond the unity-gain point. The gain asymptotically rolls off at a straight 6 dB/oct. between f o and f U so that the amplifier meets the stability criterion. The maximum gain of approximately 80 dB is an improvement. However, µ is still too low for many applications. Three or more amplifier stages can be placed in cascade to increase the gain further. While providing frequency compensation for such a device has generally been a complex process, U.S. Patent 4,559,502 ("US 502") describes an elegant capacitive-nesting solution to the problem. Fig. 5 illustrates a three-stage amplifier disclosed in US 502. The known amplifier in Fig. 5 is formed with input, intermediate, and output transconductance stages A I , A M , and A o . Stages A I and A M function as non-inverters. Stage A o again functions as an inverter. The A I non-inverting output is connected to the non-inverting input of stage A M whose non-inverting output is connected to the non-inverting input of stage A o . Its output is an inverting output. For convenience in later making a comparison to the present invention, the "non-inverting" and "inverting" labels used here for the A o inputs and output in Fig. 5 are actually opposite to those employed in US 502. However, this does not affect the function of stage A o whose output voltage V o is still inverted relative to the A o input signal difference. The capacitive nesting in Fig. 5 begins with the amplifier portion consisting of stages A M and A o . A capacitor C1 is connected between the non-inverting input of stage A o and its inverting output. The value of capacitor C1 is selected to make the portion A M and A o satisfy the stability rule. The frequency compensation is completed by connecting a capacitor C2 between the A M non-inverting input and the A o inverting output. Capacitor C2 is chosen to have such a value that the combination of stage A I with portion A M and A o likewise satisfies the stability criterion. Turning to Fig. 6 it depicts a typical version of the asymptotic frequency response for the amplifier of Fig. 5. The frequency characteristics are controlled by the two dominant poles represented by pole frequencies f o and f I (as described above) plus a third dominant pole represented by pole frequency f M dependent on the parasitic capacitance at the A M output. In the absence of capacitors C1 and C2, the gain roll-off at the unity-gain point would be far too much to satisfy the stability rule. See the upper curve in Fig. 6. Insertion of capacitor C1 causes poles f o and f M to be split further apart. See the intermediate curve in Fig. 6. Insertion of capacitor C2 then splits poles f o and f I . The lower curve in Fig. 6 shows the final compensated response. Lower pole f o has moved from starting point f os to lower final point f OF . Higher poles f I and f M have moved from starting points f IS and f MS to higher final points f IF and f MF beyond f U . The asymptotic gain roll-off is an acceptable straight 6 dB/oct. all the way out to f U . Fig. 6 illustrates typical values that f I , f M , f o f U , and f L might have in the amplifier of Fig. 5. These numerical values are not disclosed in US 502 but are presented solely for later comparison with the present invention. Note that poles f I and f M are separated from each other by approximately a factor of two in the final compensated amplifier. In particular, f IF is one half of f MF in Fig. 6. This separation results from usage of capacitor C2 and is needed to prevent the amplifier from going into resonance. Unfortunately, the separation leads to a factor-of-two reduction in frequency bandwidth. Providing the amplifier with additional nests to increase the gain further likewise reduces the bandwidth by an additional factor of two for each additional nest. A frequency compensation technique that employs the basic capacitive-nesting principle of US 502, but overcomes the bandwidth loss that occurs because of capacitor C2, would be quite advantageous. German Patent Publication 3829135 A1 ("German 135") describes a noteworthy approach to the matter of achieving high gain without significantly losing bandwidth. In German 135, the amplifier input signal is provided to two or more differential input stages connected in parallel. One of the input stages has a low gain and high bandwidth, while another has a high gain and a low bandwidth. Each remaining input stage (if any) has an intermediate gain and an intermediate bandwidth. The amplified output signals of the input stages are combined and supplied to a current-amplifying output stage that provides the amplifier output signal. German 135 states that frequency compensation need only be supplied for the input stage having the high bandwidth and low gain. While this may be true, German 135 seems to lack the advantageous straight 6 dB/oct. asymptotic gain roll-off between the lowest dominant pole frequency and the unity-gain point. In the preferred example, the frequency compensation for part of the frequency range is apparently achieved with a single capacitor connected across the input stages. German 135 does not use anything like capacitive nesting. The document Proceedings of the 1989 Bipolar Circuits and Technology Meeting, IEEE Circuits and Systems Society, 18, 19 September 1989, pages 112 - 115, Minneapolis, US; I.A. Koullias et al.: "A Complementary Bipolar Operational Amplifier with Feed-Forward Compensation" discloses a three-stage operational amplifier, the response of which is dominated at low frequencies by a two-stage amplifier while at high frequencies a single folded cascode stage takes over and reduces the overall phase shift. General disclosure of the invention The present invention employs a multi-path feed-forward technique in combination with capacitive nesting to provide frequency compensation in a multi-stage amplifier suitable for use in op amps. The basic principle of the invention entails first creating a stable two-stage amplifier by capacitively nesting a pair of amplifier stages in cascade. A stable threestage amplifier is then created by capacitively nesting the two-stage device and a further amplifier stage with feed-forward paths being provided from the further stage to both of the other stages. The parameters of the present three-stage amplifier can be chosen at such values that the low-frequency gain is slightly greater than that achievable in US 502. Importantly, the threestage amplifier of the invention avoids the approximate factor of-two loss in bandwidth that occurs in US 502. The multi-path forward feeding is responsible for these two advantages. The gain typically rolls off at a straight asymptotic 6dB/octave out to the unity-gain frequency. This is highly desirable. In short, the three-stage amplifier acts like an amplifier having the high-frequency response of a two-stage device and the low-frequency gain of a three-stage device. Furthermore, no bandwidth loss occurs if the further stage in the nested structure contains two or more capacitively nested substages provided with multiple feed-forward paths according to the invention. Before going more specifically into the structure of the invention, the following items should be noted. As used here to describe the relationship between an output signal produced by a device, such as an amplifying stage, in response to an input signal supplied to the device, the term "inverted" means that the output signal is substantially inverse -- i.e., reversed in polarity ignoring propagation delay -- to the input signal when the device is in its open-loop condition. Similarly, the term "non-inverted" means that the output signal is substantially in phase -- i.e., of the same polarity ignoring propagation delay --with the input signal when the device is in its open-loop condition. Turning now to the basic structure of the invention, the amplifier according to the invention is characterized in that the input means also amplify its input signal to produce a further output signal at a further output which is coupled to the input of the output means, the two output signal on the input means being of the same polarity and substantially electronically decoupled from each other. The present amplifier contains an input stage, an intermediate stage, and an output stage. The input stage amplifies an input signal received at least partly at an input to produce a pair of likepolarity output signals at a pair of corresponding outputs that are electronically decoupled from each other. The two output signals from the input stage typically are non-inverted but may be inverted. The intermediate stage amplifies an input signal received at least partly at an input coupled to one of the outputs of the input stage to produce a non-inverted output signal at an output. The output stage amplifies an input signal received at least partly at an input coupled to both the output of the intermediate stage and also coupled to the other output of the input stage to produce an output signal at an output. The coupling of the input stage to the output stage sets up a separate feed-forward path through the amplifier. The first capacitor coupled between the input of the output stage and the node provides frequency compensation for the intermediate and output stages. The second capacitor coupled between the input of the intermediate stage and the node provides frequency compensation for the entire amplifier. The values of the capacitors may be selected to make the forward gain of the amplifier roll off no more than 9 dB/octave out to its unity gain frequency. The amplifier thus satisfies the preceding gain roll-off stability rule. The combination of the capacitive nesting and the additional feed-forward path from the input stage to the output stage enables the invention to achieve the highly advantageous gain and frequency characteristics described above. The invention is relatively simple and can be implemented with conventional semiconductor elements. Consequently, the present amplifier provides a material advance over the prior art. Brief description of the drawings Figs. 1, 3, and 5 are diagrams of prior art amplifiers. Figs. 2, 4, and 6 are logarithmic graphs of asymptotic frequency response for the respective amplifiers of Figs. 1, 3, and 5. Fig. 7 is a block diagram of a generalized three-stage amplifier in accordance with the invention. Fig. 8 is a logarithmic graph of asymptotic frequency response for the amplifier of Fig. 7. Figs. 9, 11, and 12 are circuit diagrams for three different bipolar embodiments of the amplifier of Fig. 7. Figs. 10a and 10b are circuit diagrams for amplifier stages that can alternatively be used in the embodiment of Fig. 9. Figs. 13 and 14 are block diagrams for extensions of the amplifier of Fig. 7. Figs. 15a and l5b are block diagrams for implementations of the amplifier of Fig. 7 in which the input stage consists of two substages so as to effectively form a four-stage amplifier. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Non-inverting inputs and outputs are indicated with "+" signs in the drawings, whereas inverting inputs and outputs are noted with "-" signs. Due to spacing constraints, multiple outputs that provide like-polarity signals from an amplifier stage shown in symbolic (triangular) form are denoted with only a single "+" or "-" sign. The additional feed-forward paths of the invention are indicated in heavy lines in the drawings. Description of preferred embodiments Referring to Fig. 7, it illustrates a general version of a three-stage amplifier that is frequency compensated in accordance with the invention. This amplifier contains input stage A I , intermediate stage A M and output stage A o arranged in cascade. Each of stages A I , A M , and A o is a transconductance amplifier. In the frequency-compensation technique of the invention, capacitor C1 is first nested with stages A o and A M to form a two-stage device whose gain falls well within the 9 dB/oct. roll-off stability rule. Capacitor C2 is then nested with this two-stage device and stage A I from which feed-forward paths are provided to both of stages A M and A o . The resulting three-stage amplifier meets the stability criterion separately for each feed-forward path and, consequently, for the entire amplifier. In more detail, each stage A I , A M , or A o has either a single input or a non-inverting input and an inverting input. In the single-input case, the input is inverting for both stages A M and A o but may be either non-inverting or inverting for stage A I . In the two-input case, each stage A I , A M or A o may function as a "differential" amplifying device having little input offset voltage. Alternatively, each stage A I , A M , or A o may function as a "non-differential" amplifying device for which a selected non-negligible offset voltage exists between the device inputs. With the foregoing in mind, input stage A I preferably has non-inverting and inverting inputs for respectively receiving input voltages V I+ and V I- , either of which may be substantially fixed. The difference V I between voltages V I+ and V I- is then the amplifier input signal. Alternatively, if stage A I has only one input, the amplifier input signal is voltage V I+ or voltage V I- depending on which input is present. Stage A I amplifies the amplifier input signal (V I , V I+ , or V I- ) to produce a main output signal S M1 at a main non-inverting output. Stage A I also amplifies the amplifier input signal to produce a further output signal S M2 at a further non-inverting output. Signals S M1 and S M2 are of the same polarity. Both are non-inverted relative to the amplifier input signal if it consists of voltage V I or voltage V I+ . Signals S M1 and S M2 are inverted if the amplifier input signal is voltage V I- . The two A I non-inverting outputs are substantially (electronically) decoupled from each other. As a result, undesired feedback into one of the A I outputs does not significantly affect the signal characteristics at the other A I output. The main (S M1 ) non-inverting output of stage A I is connected to the non-inverting input of intermediate stage A M . Signal S M1 and signal V M , which is provided to the A M non-inverting input, are the same voltage but differ in current level. Stage A M amplifies signal V M to produce a non-inverted output signal S N at a non-inverting output. If stage A M has an inverting input, signal S N is produced by amplifying signal V M relative to the signal at the A M inverting input. The non-inverting output of stage A M is connected to the non-inverting input of output stage A o . The further (S M2 ) non-inverting output of stage A I is also connected to the A o non-inverting input to set up a separate feed-forward path through the amplifier. Signals S M2 and S N and signal V N , which is provided to the A o non-inverting input, are the same voltage but differ in current level. Stage A o amplifies voltage V N to produce a single amplifier output signal or a pair of opposite polarity amplifier output signals. If stage A o has an inverting input, the amplification is done relative to the signal at the A o inverting input. Fig. 7 indicates that voltages V o- and V o+ are present at nodes O₋ and O+ respectively connected to inverting and non-inverting outputs of stage A o . Fig. 7 also indicates that either voltage V o+ or voltage V o- may be substantially fixed. Consequently, there are three basic versions of the present amplifier: (1) Stage A o provides voltage V o- as an inverted amplifier output signal, node O+ being connected to a source of a substantially constant reference voltage; (2) Stage A o provides voltage V o+ as a non-inverted amplifier output signal, node O₋ being connected to a source of a substantially constant reference voltage; and (3) Stage A o provides voltages V o+ and V o- respectively as non-inverted and inverted amplifier outputs signals, their difference being output voltage v o which is inverted relative to signal v N . The A o inverting input, if present, is typically connected to node O+. The A M inverting input, if present, is likewise typically connected to node O+. The A M and A o inverting inputs thereby either receive the non-inverted amplifier output signal (V o+ ), when it is provided, or a reference voltage. Capacitor C1 is connected between the A o non-inverting input and node O₋. By suitably choosing the value of capacitor C1, it enables the gain of amplifier portion A M and A o to roll off much less than 9 dB/oct. out to its unity-gain frequency. Capacitor C2 is connected between the A M non-inverting input and node O₋. The values of capacitors C1 and C2 are selected to make the gain of the full amplifier roll off no more than 9 dB/oct. out to its unity-gain frequency. In view of the three amplifier versions discussed above, the right-hand plates of capacitors C1 and C2 receive either the inverted amplifier output signal (V o- ), when it is provided, or a reference voltage. Fig. 8 shows a typical asymptotic frequency response for the amplifier of Fig. 7. As with the prior art device in Fig. 5, the frequency characteristics are largely determined by the three dominant poles dependent on the parasitic capacitances at the outputs of stages A I , A M ' and A o . These poles are again respectively represented by pole frequencies f I , f M , and f o . For convenience, the amplifier of Fig. 5 is referred to as the "prior art device" in the following discussion about Figs. 8 and 6. If capacitors C1 and C2 were absent, poles f I , f M , and f o would be at starting points f IS , f MS , and f OS . To enable the performance of the present amplifier to be compared directly to that of the prior art device, the values for f IS , f MS , and f OS in Fig. 8 are respectively the same as in Fig. 6. With capacitors C1 and C2 absent, the variation in frequency response for the present amplifier would be largely the same as that for the prior art device with capacitors C1 and C2 missing. Compare the upper curve in Fig. 8 to the upper curve in Fig. 6. The gain roll-off at the unity-gain point would be 18 dB/oct. Oscillations could occur at high frequency if the amplifier were used in a feedback arrangement. Inserting capacitor C1 into the present amplifier splits poles f M and f o in generally the same way as in the prior art device. Compare the intermediate curve in Fig. 8 to the intermediate curve in Fig. 6. Lower pole f o moves down to a lower value, while higher pole f M moves up to final position f MF . As indicated in Figs. 8 and 6, the value of f MF is the same for both amplifiers. As with the prior art device, next inserting capacitor C2 into the present amplifier causes poles f o and f I to be split further apart. Compare the lower curve in Fig. 8 to the lower curve in Fig. 6. Lower pole f o moves further downward to final position f OF , while higher pole f I moves upward to final position f IF . The forward gain for the present amplifier asymptotically rolls off no more than a straight 6 dB/oct. out to unity-gain frequency f U . The present amplifier thereby satisfies the gain roll-off stability rule. Importantly, optimum choice for the capacitor values enables poles f o and f I to move further apart in the present amplifier than in the prior art device. More specifically, f I moves all the way up to f M in the present amplifier. That is, f IF equals f MF so as to create a double pole. In contrast, as mentioned above, f IF is approximately a factor-of-two less than f MF in the prior art device. The extra feed-forward path from stage A I to stage A o is responsible for the capability to choose the capacitor values so as to obtain the additional movement of poles f I and f o in the present amplifier. In particular, the extra feed-forward path overcomes part of the phase lag through stage A M . Insofar as frequency compensation is concerned, the amplifier of Fig. 7 acts much like a two-stage device rather than a three-stage amplifier. Because the factor-of-two separation between f IF and f MF is eliminated in the present amplifier, its unity-gain frequency is twice that of the prior art device. For example, Fig. 8 indicates that f U is about 20 MHz in the specific example of the present amplifier. Conversely, Fig. 6 indicates that f U is only 10 MHz in the specific example of the prior art device. Accordingly, the frequency range of the present amplifier is approximately twice that of the closest prior art device. The extra feed-forward path in the present amplifier results in approximately 12 dB of additional gain at low frequency --i.e., a factor of four increase. For example, the maximum low-frequency gain is about 132 dB in the specific example of the present amplifier but is only 120 dB in the specific example of the prior art device. The f OF value in the present amplifier is approximately one half the f OF value in the prior art device: However, due to the increased gain in the invention, this is not a problem. Examination of the numerical values shown in Figs. 8 and 6 indicates that the low-frequency gain of the present amplifier does not drop down to the maximum low-frequency gain of the prior art device until the frequency reaches a value f E that is approximately twice the f OF value of the prior art device. The present amplifier therefore has better gain/frequency characteristics than the closest prior art device at all relevant points. To stabilize amplifier portion A M and A O in the invention, capacitor C1 has a value much greater than G MM /4πf U , where G MM is the transconductance of stage A M along its output. Also, to stabilize the entire amplifier, the preferred value of capacitor C1 is G MI2 /2πf U , where G MI2 is the transconductance of stage A I along its further (S M2 ) output. Similarly, the preferred value of capacitor C2 is G MI1 /2πf U , where G MI1 is the transconductance of stage A I along its main (S M1 ) output. The specific examples of Figs. 8 and 6 apply to the condition in which f os < f MS < f IS . Nonetheless, the frequency response is similar if a different inequality exists among f IS , f MS , and f OS . The only difference is in which poles move to the positions represented by f IF , f MF , and f OF Turning to Fig. 9, it depicts a typical bipolar embodiment of the present three-stage amplifier. Stages A I , A M , and A O in Fig. 9 are connected between a source of a high supply voltage V CC and a source of a low supply voltage V EE . Input stage A I consists of NPN input transistors Q I1 , Q I2 , Q I3 , and Q I4 and (substantially constant) current sources II1, II2, II3, and II4 arranged as shown. Voltage V I+ is supplied to the Q I3 and Q I4 bases, while voltage V I- is supplied to the QI1 and QI2 bases. Transistors QI1 and QI3 operate as a conventional differential pair in parallel with transistors QI2 and QI4 which also operate as a conventional differential pair. The main (S M1 ) and further (S M2 ) non-inverting outputs of stage A I are respectively taken at the Q I1 and Q I2 collectors. Signals S M1 and S M2 are non-inverted. Intermediate stage A M is formed with NPN intermediate transistors QM1 and QM2, current sources I M1 and I M2 , and a voltage source BM1 interconnected as shown. Signal V M is supplied to the QM1 base, while voltage source BM1 provides a reference voltage to the QM2 base. Transistors Q M1 and Q M2 operate as a conventional differential pair. The A M non-inverting output is taken at the QM2 collector. Output stage A O consists of an NPN output transistor QO1, a current source IO1, and an optional voltage source BO1 arranged as shown. Signal V N is supplied to the base of transistor QO1 whose collector is connected to node O₋ at the A O inverting output. Transistor QO1 functions as an inverter. Node O+ is tied to the V EE supply. Consequently, the device in Fig. 9 is an embodiment of amplifier version (1) discussed above. Fig. 10a illustrates an example of how input stage A I in Fig. 9 could be modified. Elements QI4 and II4 have been deleted in Fig. 10a. The QI1 - QI3 emitters are now all connected to current source II3 so that transistors QI1 - QI3 operate together in a differential manner. Elements QI3 and II3 could also be deleted in Fig. 10a. The QI1 and QI2 emitters would then be connected directly to the V EE supply. Only voltage V I- would be supplied as an input signal to stage A I . Signals S M1 and S M2 then become inverted signals. Fig. 10b illustrates an example of how intermediate stage A M in Fig. 9 could be modified. Elements QM2, IM1, IM2, and BM1 have been deleted in Fig. 10b and replaced with PNP transistors QM3 and QM4 and an optional voltage source BM2 arranged as shown. Transistor QM1 now operates as an inverter. Transistors QM3 and QM4 function as a current mirror that performs a reinversion. The A M non-inverting output is now taken at the QM4 emitter. Fig. 11 shows another bipolar implementation of the amplifier of Fig. 7. Stages A I and A M in Fig. 11 are respectively the same as in Figs. 10a and 10b. Again, stage A I could be further simplified in the manner described above for Fig. 10a. Stage A O in Fig. 11 is formed with transistor QO1 and a current source IO2 interconnected as shown. Signal V N is again supplied to the base of transistor QO1. However, its emitter is now connected to node O+ at the A O non-inverting output. Transistor QO1 functions as a voltage follower here. Node O₋ is tied to the V CC supply. As a result, the implementation of Fig. 11 is an example of amplifier version (2). A current source could be inserted between node O₋ and the V CC supply in stage A O of Fig. 11. Stage A O would then provide voltage V O- from the inverting output at node O₋. As so modified, the implementation of Fig. 11 would then be an example of amplifier version (3). Fig. 12 illustrates a further bipolar embodiment of the present amplifier. Stage A I now consists of NPN transistors QI5 and QI6, PNP transistors QI7 and QI8, NPN transistors QI9 and QI10, currents source II5, II6, and II7, and voltage sources BI1 and BI2 arranged as shown. Voltages V I- and V I+ are respectively supplied to the bases of transistors QI5 and QI6 which operate as a differential pair. Transistors QI7-QI10 provide a voltage level shift in addition to decoupling the two A I outputs. The A I main output is taken at the junction of the QI7 and QI9 collectors. The A I further output is taken at the junction of the QI8 and QI10 collectors. Stage A M in Fig. 12 is formed simply with a PNP transistor QM5 whose base receives signal V M . The A M non-inverting output is taken at the QM5 emitter. Transistor QM5 functions as a voltage follower. Stage A O in Fig. 12 consists of a PNP transistor QO2 and a current source I03 arranged as shown. Signal V N is supplied to the base of transistor QO2 whose collector is connected to node O₋ at the A O inverting output. Transistor QO2 functions as an inverter. Node O+ is tied to the V CC supply. The embodiment of Fig. 12 is thus another example of amplifier version (1). Each bipolar transistor in stage A I of Fig. 9, 1Oa, 11, or 12 could be replaced with a field-effect transistor ("FET") of the insulated-gate or junction type. Like replacements could be made for many of the other bipolar transistors in stages A M and A O of Fig. 9, 10b, 11, or 12. More generally, each such transistor could be represented as having a first flow electrode, a second flow electrode, and a control electrode for controlling current flow between the flow electrodes. In the case of a bipolar transistor, its emitter, collector, and base respectively are the first, second, and control electrodes. These elements are the source, drain, and gate for an FET. Moving to Fig. 13, it shows an extension of the amplifier of Fig. 7. This extension contains components A I , A M , A O , C1, and C2 interconnected as described above, except that the A M and A O inverting inputs are now explicitly connected to a source of a reference voltage V R . Only inverting voltage V O- is supplied as an A O output signal. The extension includes an additional output stage A OA that operates in parallel with stage A O in a complementary manner. For this purpose, stage A M amplifies signal V M relative to voltage V R to produce an additional non-inverted output signal S NA at an additional substantially decoupled non-inverting output connected to the A OA non-inverting input. Also, stage A I amplifies the amplifier input signal to produce an additional non-inverted output signal S M2A at an additional substantially decoupled non-inverting output. The additional (S M2A ) non-inverting output of stage A I is similarily connected to the A OA non-inverting input to set up a separate feed-forward path through the amplifier. Stage A OA amplifies signal V NA at its non-inverting input relative to another reference voltage V RA at its inverting input to produce an inverted output voltage V OA- at an inverting output connected to node O₋. An additional capacitor C1A is connected between the A OA non-inverting input and node O₋. Signals V O- and V OA- are combined at node O₋ to produce an inverted voltage V OC- as the final output signal of the extension. The value of capacitor C1A is chosen so as to make the gain of amplifier portion A M and A OA fall well within the 9dB/oct. roll-off stability rule. More specifically, the C1A value is much greater than G MMA /4πf U , where G MMA is the transconductance of stage A M along its additional (S NA ) output. To stabilize amplifier portion A I , A M , and A OA and thus the entire device, the preferred C1A value is G MI2A /2πf U , where G M12A is the transconductance of stage A I along its additional (S M2A ) output. Capacitors C1 and C2 in the extension of Fig. 13 preferably have the values given above for the amplifier of Fig. 7. Fig. 14 shows another extension of the amplifier of Fig. 7. The extension in Fig. 14 similarly contains components A I , A M , A O , C1, and C2 interconnected as described above, except that the A O inverting input is connected to the V R source. Again, stage A O only supplies inverting voltage V O- as an output signal. Also, the A M inverting input is connected in the manner discussed below. The extension of Fig. 14 includes an additional output stage A OB that operates in parallel with stage A O in a push-pull manner. To accomplish this function, stage A I amplifies amplifier input signal V I to produce main and further inverted output signals S M1B and S M2B at respective main and further substantially decoupled inverting outputs. The main (S M1B ) inverting output of stage A I is connected to the A M inverting input. Stage A M amplifies signal V M relative to signal V MB at its inverting input to produce an inverted output signal S NB at an inverting output connected to the A OB inverting input. The further (S M2B) inverting output of stage A I is also connected to A OB inverting input to set up a separate feed-forward path. Stage A OB amplifies the signal at its non-inverting input relative to signal V NB at its inverting input to produce an inverted output voltage V OB- at an inverting output connected to node O₋. Signal V OB- is non-inverted relative to signal V NB . The A OB non-inverting input is normally also connected to node O₋. Signals V O- and V OB- are combined at node O₋ to produce inverted voltage V OC- as the final output signal of the amplifier. Stage A OB has a non-inverting output connected by way of an additional node O B to a source of an additional reference voltage V RB . An additional capacitor C1B is connected between the A OB inverting input and node O B . Capacitor C1B is selected to have such a value that the gain of amplifier portion A M and A OB falls well within the stability criterion. An additional capacitor C2B is connected between the A M inverting input and node O B . The values of capacitors C1B and C2B are chosen to make the gain of the combination A I , A M , and A OB meet the stability rule. In particular, capacitors C1B and C2B preferably have values respectively analogous to the preferred C1 and C2 values given below. The principles of the present invention can be extended to amplifiers having four or more stages in cascade. Equivalently, stage A I can consist of two or more capacitively nested substages that have multiple feed-forward paths in accordance with the invention. Turning to Fig. 15a, it depicts an embodiment of how the invention can be extended in this way. Stage A I in Fig. 15a contains substages A I1 and A I2 , each of which has a non-inverting input, an inverting input, and a non-inverting output. The non-inverting and inverting inputs of substage A I1 are respectively connected to the A I non-inverting and inverting inputs. Substage A I1 amplifies the amplifier input signal to produce (a) a main non-inverted output signal S J1 at a main non-inverting output and (b) first and second further non-inverted output signals S J2 and S J3 at respective first and second further non-inverting outputs. The three A I1 outputs are substantially decoupled from one another. The main (S J1 ) non-inverting output of substage A I1 is connected to the A I2 non-inverting input. Substage A I2 amplifies signal V J at its non-inverting input relative to the signal at its inverting input to produce main and further non-inverted output signals S K1 and S K2 at respective main and further substantially decoupled non-inverting outputs. The first further (S J2 ) non-inverting output of substage A I1 and the main (S K1 ) non-inverting output of substage A I2 are both connected to the main (S M1 ) non-inverting output of stage A I . The second further (S J3 ) non-inverting output of substage A I1 and the further (S K2 ) non-inverting output of substage A I2 are both connected to the further (S M2 ) non-inverting output of stage A I . The further (S J2 , S J3 , and S K2 ) output connections all provide separate feed-forward paths. When the invention is extended in the preceding way, the value of capacitor of C2 is selected to make the gain of amplifier portion A I2 , A M , and A O fall well within the stability rule. A capacitor C3 is connected between the A I2 non-inverting input and node O₋. Capacitors C1, C2, and C3 are chosen to have such values that the gain of the entire amplifier meets the stability criterion. Unity-gain frequency f U for this "four-stage" device is usually the same as f U for the "three-stage" amplifier of the invention. Consequently, usage of capacitor C3 does not result in any loss in frequency range. In Fig. 15a, the A I2 , A M , and A O inverting inputs are all connected to node O+. The device is thereby an example of amplifier version (3). Any single one of the three extra feed-forward paths in stage A I could be deleted. Fig. 15b illustrates an example of Fig. 15a in which the S J3 feed-forward path is absent. Similarily, either the S J2 or S K2 feed-forward path could be deleted from stage A I . While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, resistors could be placed in series with the compensating capacitors. Inverters could be inserted into parts of the signal paths in such a manner that the overall gain/frequency behavior is not significantly affected. As an example, low-gain inverters could be placed in all of the S M1 , V M and C2 signal paths without significantly affecting the amplifier performance. Various modifications and applications may thus be made by those skilled in the art without departing from the true scope and spirit of the invention as defined in the appended claims.

Claims: An amplifier comprising: input means (AI) that amplifies an input signal received at least partly at an input to produce a main output signal at a main output thereof ; intermediate means (AM) that amplifies an input signal received at least partly at an input coupled to the main output of the input means (AI) to produce a non-inverted output signal at an output thereof ; output means (AO) that amplifies an input signal received at least partly at an input coupled to the output of the intermediate means (AM) to produce an output signal at an output thereof ; a first capacitor (C1) coupled between the input of the output means (AO) an a node coupled to (a) the output of the output means if its output signal is inverted or (b) a source of a reference voltage if the output signal of the output means is non-inverted; and a second capacitor (C2) coupled between the input of the intermediate means (AM) an the node, characterized in that the input means (AI) also amplify its input signal to produce a further output signal at a further output which is coupled to the input of the output means (AO), the two output signals of the input means being of the same polarity and substantially electronically decoupled from each other. An amplifier as in Claim 1 wherein the two outputs of the input means (AI) are directly coupled to the input of the output means. An amplifier as in Claim 1 or 2 wherein the forward gain of the amplifier does not roll off more than 9 dB/octave out to its unity-gain frequency. An amplifier as in Claim 1 or 2 wherein the output signal of the output means (AO) is inverted, and the output means also amplifies its input signal to produce a non-inverted output signal at a further output. An amplifier as in Claim 4 wherein the input signal to the output means (AO) is supplied between its input and another input coupled to the further output of the output means. An amplifier as in Claim 1 or 2 wherein the output signal of the output means (AO) is non-inverted, and the input signal to the output means is supplied between its input and another input coupled to the output of the output means. An amplifier as in Claim 1 or 2 wherein the input means comprises: first and second transistors (QI1, QI2) each having a first flow electrode, a second flow electrode, and a control electrode for controlling current flow between the flow electrodes, the control electrodes being responsive to the input signal to the input means, the second electrodes of the first and second transistor being respectively coupled to the main and further outputs of the input means (AI); and first and second current supplies (II1, II2) respectively coupled to the main and further outputs of the input means. An amplifier as in Claim 7 wherein the input means further includes: a third transistor (QI3) having a first flow electrode, a second flow electrode, and a control electrode for controlling current flow between that transistor's flow electrodes, the control electrode of the third transistor being coupled to the input of the input means (AI), the control electrodes of the first and second transistor (QI1, QI2) being coupled to another input of the input means such that its input signal is differentially supplied between its inputs; and a third current (II3) supply coupled to the first electrodes of the three transistors. An amplifier as in Claim 7 wherein the input means further includes: third and fourth transistor (QI3, QI4), each having a first flow electrode, a second flow electrode, and a control electrode for controlling current flow between that transistor's flow electrodes, the control electrodes of the third and fourth transistors being coupled to the input of the input means (AI), the control electrodes of the first and second transistors being coupled to another input of the input means such that its input signal is differentially supplied between its inputs; a third current supply (II3) coupled to the first electrodes of the first and third transistors; a fourth current supply (II4) coupled to the first electrodes of the second and fourth transistors. An amplifier as in Claim 1 or 2 wherein the input means (AI) comprises: first submeans (AI1) that amplifies an input signal received at least partly at an input coupled to the input of the input means to produce a main output signal at a main output; second submeans (AI2) that amplifies an input signal received at least partly at an input coupled to the main output of the first submeans (AI1) to produce a main non-inverted output signal at a main output coupled to the main output of the input means; and a third capacitor (C3) coupled between the input of the second submeans (AI2) and the node, the input means being configured to accomplish at least two of the following three functions: (1) the first submeans also amplifies its input signal to produce a further output signal at a further output coupled to the main output of the input means, (2) the first submeans also amplifies its input signal to produce a further output signal at a further output coupled to the further output of the input means, and (3) the second submeans also amplifies its input signal to produce a further non-inverted output signal at a further output coupled to the further output of the input means, each further output signal of the first submeans being of the same polarity as its main output signal, each output of each submeans being substantially electronically decoupled each other output of that submeans.

Inventors: FONDERIE MAARTEN JEROEN, HUIJSING JOHAN HENDRIK, FONDERIE, MAARTEN JEROEN, HUIJSING, JOHAN HENDRIK
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H03F1
IPC codes: H03F1