Testing circuit provided in digital logic circuits

Abstract: In a digital logic circuit including a scan-pass registers (101 - 104) for holding outputs of a combined circuit, each of the scan-pass registers comprises first and second holding means (110, 111) and first and second selecting means (112, 113). Upon test mode, the output of the holding means is selected as a signal for a shift-out terminal (SO), whereby one of the value of the selected holding means can be detected for a desired test in real time.

Description: BACKGROUND OF THE INVENTION The present invention relates to a testing circuit provided in a digital logic circuit for testing itself. In a digital logic circuit such as an LSI, it is important to test whether its operation is normal or not. The test is usually carried out for analyzing a possible trouble occurring in the circuit, or for determining upon checking whether it is good or not. Testing of the digital logic circuit, in general, is carried out by entering a test pattern from the outside, and a resulting output pattern is analyzed to test the circuit. In such tests, in particular, for LSIs, one of the most simple methods for observing the condition of the circuit is to connect the internal nodes to be observed to the pins of the package. However, the number of input and output pins of the LSI package is finite, and it is impossible to take out all the great number of internal nodes to the outside. Therefore, in order to increase the observability of the internal node, a scan-pass method has been considered. Fig. 1 shows an example of a digital logic circuit including a testing circuit which comprises a first combined circuit 1 having inputs of m-bits connected to an input terminal 11 and plurality of outputs; a second combined circuit 2 having a plurality of inputs and outputs of n-bits connected to an output terminal 12; and a plurality of scan-pass registers depicted by numerals 201 to 204. The construction and function of the scan-pass register depicted by numerals 201 to 204 are similar to each other and the scan-pass register 201 will be described below with reference to Fig. 2. The scan-pass register 201 comprises a multiplexer 210 and a data-type flip-flop 211. The multiplexer 210 has three inputs connected to a test input TS, a data input DI, and a shift signal input SI terminals, respectively, and an output O. The flip-flop 211 has an input D connected to the output 0 on the multiplexer 210, a clock input connected to a clock terminal CK and a Q-output connected to a data output DO and a shift signal output SO terminals. Each of the data input terminals DI of the scan-pass registers 201 to 204 is connected to an output of the combined circuit 1, and each of the data-output terminals to an input of the combined circuit 2. In addition, the shift signal input terminal of the first scan-pass register 201 is connected to a main shift-in terminal 13 and the shift signal output terminal thereof is connected to the shift signal output terminal SI of the second scan-pass register 202, and this connection is repeated with the remaining scan-pass registers 202 to 203, and the shift-out terminal SO of the final stage of scan-pass register 204 is connected to a main shift-out terminal 14. Also, the test terminals of scan-pass registers 201 to 204 are connected to a test terminal TS, and the clock terminals of scan-pass registers to a clock terminal 15. The signal supplied to the terminal TS switches the scan-pass register 201 into a normal mode and the test mode. During the normal mode, the multiplexer 210 allows to pass a signal supplied to DI to the input D of the flip-flop 211 through the output O, so that the multiplexer 210 functions as an ordinary flip-flop. On the other hand, during the test mode, the multiplexer 210 selects the signal SI which passes through the flip-flop 211 and is thensupplied to the SI terminal of the following scan-pass register 202. All the scan-pass registers perform the same function, the scan-pass registers act as a shift register . Therefore, the output on the terminal SO indicates the function of all the scan-pass registers in accordance with the timing of the clock signal on the terminal CK in a serial manner. In the conventional testing circuit according to the scan-pass method as described above, since the internal flip-flops form a shift register during the test mode, data does not come out to the observing point unless numerous clocks are entered, when one wants to know the status of the flip-flop of interest. Furthermore, since, in the test mode, the internal FF operates as the shift register, execution of the program must be stopped, which lacks a real time performance. Still further, as shown in Fig. 2, since data is entered to flip-flop via a multiplexer, some extent of delay results, which degrades the performance further than at the original maximum operating frequency of the circuit. In the document EP-A-0 444 825 a register circuit for scan pass is disclosed. It comprises a selector responsive to a shift control signal for selecting either a scan input or a data input, a D-type flip-flop responsive to a clock signal for operating, a selector for selecting either the data applied to the scan input or the output data from the flip-flop, and a latch circuit for holding a signal controlling the selector. The selector thereby has one input connected so as to receive the output data from the flip-flop. A bypass line is connected between the other input of the selector and the scan input. Accordingly, an object of the present invention is to provide a testing circuit which allows the register within the circuit to be specified in a programmable manner while allowing the value of that register to be emitted to the outside in real time without interrupting the execution of the program. SUMMARY OF THE INVENTION A testing circuit provided in digital logic circuits according to the present invention is disclosed in claim 1. Claims 2 to 8 disclose further embodiments of the invention. There is provided a testing circuit in a digital logic circuit which comprises a combined circuit having a plurality of outputs and said testing circuit comprising scan-pass registers each connected to the respective output of said combined circuit; each of said scan-pass register comprising a data input, a clock input, a shift signal input a test input, a data output and a shift signal output, and the register being serially connected such that said shift signal output is connected to the shift signal input of the adjacent scan-pass register to form a serial circuit, the shift signal input of the foremost scan-pass register being connected to a main shift-in terminal and the shift signal output of the rearmost scan-pass register being connected to a main shift-out terminal; each of said scan-pass registers comprising a first holding means for holding one of the outputs of said combined circuit, a second holding means for holding a signal on said shift-in terminal when a signal on said test signal input is active, a first selecting means for selecting between said shift signal input and the signal from said first holding means in response to the output from said second holding means, and a second selecting means for selecting between the output of said second holding means and the output of said first selecting means in response to the signal on a test input. The present invention will be more clearly understood from the detailed description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a conventional testing circuit; Fig. 2 is a block diagram of a scan-pass register of the circuit shown in Fig. 1; Fig. 3 is a block diagram illustrating an arrangement comprising a testing circuit in a digital logic circuit according to one embodiment the present invention; Fig. 4 is a block diagram of a scan-pass register of the circuit shown in Fig. 3; and Fig. 5 is a timing chart of the signals on various points of the scan-pass register of Fig. 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 3 illustrates an arrangement comprising a testing circuit according to a embodiment of the present invention. The arrangement comprises first and second combined circuits 1 and 2 and four scan-pass registers 101, 102, 103 and 104 for holding the state of the circuit. The number of the scan-pass registers is not restricted in the present invention. The connection between these elements are substantially the same as those illustrated in Fig. 1 and the detailed explanation will be omitted here to avoid repetition. The construction and function of the scan-pass registers 101, 102, 103 and 104, however, are critical and different from those of the conventional testing circuit as illustrated in Figs. 1 and 2. Referring now to Fig. 4 which illustrates the first scan-pass register 101 of the testing circuit, the scan-pass registers 101 comprises first and second data type flip-flops 110 and 111. The first flip-flop 110 has a data D and a clock CLK inputs connected to a data-input DI and the clock CK terminals, respectively. Also, the second flip-flop 111 has a data D a clock CLK and an enable EN inputs connected to a shift signal input SI, a clock CK and test TS terminals, respectively. The scan-pass register 101 further comprises first and second multiplexers 112 and 113, each having two inputs, a selecting signal input SEL and an output. The first input of the first multiplexer 112 is connected to the shift signal input terminal SI, the second input to the Q output of the first flip-flop 110, the selecting signal input SEL to the Q output of the second flip-flop 111, and the output to the second input of the second multiplexer 113. Also, the first input of the second multiplexer 113 is connected to the Q output of the second flip-flop 111 and the selecting signal input SEL of the first multiplexer 112, and the selecting signal input SEL of the second multiplexer 113 to the test terminal TS. The shift-out terminal SO is connected to the output of the second multiplexer 113, and the data output terminal DO to the Q output of the first flip-flop 110. When the signal on the test terminal TS is active, the second flip-flop 111 stores the value on the shift-in terminal SI, and the first flip-flop 110 stores the value on DI. The first multiplexer 112 selects the value on Q terminal of the first flip-flop 110 when the value on Q terminal of the second flip-flop 111 is active, and the value on the terminal SI is inactive. While, the second multiplexer 113 selects the value on Q terminal of the second flip-flop 111 when the value on terminal TS is active, and the output of the first multiplexer 112 is inactive. The remaining scan-pass registers 102 to 104 have the same construction and function as that of the first scan-pass register 101. The operation of the testing circuit will be hereinafter described with reference to the drawings. For the testing circuit having four scan-pass registers as illustrated in Fig. 3, in the following example, the data-output DO for the scan-pass register 103 is observed. In order to observe the output of any one of the scan-pass registers 101-104, the register must be set by activating the test input TS. In this state, if the second flip-flops 111 have been reset, then they operate as a shift register. At the same time, the test terminal TS is turned active, a shift-in terminal SI is turned active over a single clock. The timing chart of the signals on the terminals are shown in Fig. 5. This shift operation causes the test terminal active over three clocks in this case, until the second flip-flop 111 of the register 103 to be observed has been set. By this operation, the second flip-flops 111 of the registers 101, 102, 103, 104 are each turned into "reset", "reset", "set" and "reset" states, respectively, and the register 103 is selected. When the test terminal TS is turned inactive, a program, pattern and the like to be tested are entered to the circuit. At this time, a value equal to DO of the register 103 is generated to SO of the register 103. In addition, since a value equal to SI of the register 104 is supplied to SO of the register 104, the value on DO of the register 103 can be observed at the shift-out terminal SO. Furthermore, it can be realized that by setting the flip-flop 111 of any one of the registers 101-104, the value DO of the register can be observed. Although the above description was made for a testing circuit including four scan-pass registers, the present invention can be applied for a circuit having more than four registers. As described above, the value of any arbitrary register within the circuit can be emitted to the outside to readily detect whether the circuit operation is good or not, or any trouble is present or not. In addition, since the value can be observed in real time without interrupting the execution of the program, it is possible to carry out an efficient test in a short period of time. In addition, even if the present invention is used, any extra delay is not caused to the original logic of the circuit, so that it can be avoided that the performance of the maximum operating frequency of the circuit is degraded.

Claims: A testing circuit provided in a digital logic circuit comprising a combined circuit (1) having a plurality of outputs and said testing circuit comprising scan-pass registers (101-104) each connected to a respective output of said combined circuit, each of said scan-pass registers comprising: a data input (DI) connected to an output of said combined circuit (1); a clock input (CK); a shift signal input (SI); a test input (TS); a data output (DO); and a shift signal output (SO), wherein said scan-pass registers (101-104) are serially connected such that said shift signal output (SO) of one of said scan-pass registers is connected to the shift signal input (SI) of an adjacent one of said scan-pass registers to form a serial circuit having a foremost scan-pass shift register and a rearmost scan-pass shift register, the shift signal input (SI) of the foremost scan-pass register (101) being connected to a main shift-in terminal (13) and the shift signal output (SO) of the rearmost scan-pass register (104) being connected to an observation shift-out terminal (14); characterized in that each of said scan-pass registers (101-104) comprises: a first holding means (110) connected to said data input for holding one of the outputs of said combined circuit; a second holding means (111) connected to said shift signal input and responsive to a signal on said test input for holding a signal on said shift signal input (SI) when a signal on said test input (TS) is active, said first and second holding means each being responsive to a clock signal on said clock input; a first selecting means (112) connected to said shift signal input and to receive an output signal of said first holding means for selecting between said shift signal input and the output signal from said first holding means in response to an output from said second holding means; and a second selecting means (113) connected to receive output signals from said second holding means and from said first selecting means for selecting between the output signal of said second holding means and the output signal of said first selecting means in response to the signal of said test input (TS). A testing circuit according to claim 1 wherein said first and second holding means (110, 111) are flip-flops. A testing circuit according to claim 1 wherein said first and second selecting means (112, 113) are multiplexers. A testing circuit according to claim 1 which further comprises a second combined circuit (2) having a plurality of inputs connected to said data outputs of each of said scan-pass registers. A testing circuit according to claim 1 for testing a combined logic circuit (1), wherein an individual one of said scan-pass registers (101-104) is progammably selected for observation at said shift signal output (SO) of the rearmost shift scan-pass register (104) by holding said test signal (TS) active over a number of clock cycles corresponding to one of said scan-pass registers to be observed, and wherein in each scan-pass register (101-104) a data input (DI) is connected to a corresponding output of the combined logic circuit (1) to be tested; said first holding means (110) is a flip-flop having a set input connected to said data input (DI); said second holding means (111) is a flip-flop having a set input connected to said shift signal input (SI); and said second selecting means (113) selects the output of said second holding means (111) when said test input (TS) is active. A testing circuit for testing an integrated circuit as recited in claim 5 wherein said first and said second selecting means (112, 113) are multiplexers. A testing circuit for testing an integrated circuit as recited in claim 5 wherein said first and said second flip-flops are D-type flip-flops. A testing circuit for testing an integrated circuit as recited in claim 5 wherein each of said scan-pass registers further has a data output (DO) connected to the output of said first holding means (110), said data outputs of said scan-pass registers being connected to corresponding inputs of a second combined logic circuit (2).

Inventors: SUZUKI HIROAKI, SUZUKI, HIROAKI, SUZUKI, HIROAKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G06F11
IPC codes: G01R31, G06F11, G11C29, H03K19