Improved microprocessor synchronous timing system

Abstract: There is disclosed a timing system for use in a microprocessor for initiating microprocessor outputs onto an input sampling from an external bus in synchronism with a bus timing clock. The timing system is operative in a first mode for internally generating the bus timing clock and in a second mode for being driven from an externally generated bus timing clock. In the first mode, the timing system generates first and second inverse phase timing clocks responsive to an external clock source and independently generates the internally generated bus timing clock with the rising edges of the bus timing clock coinciding with the rising edges of the first microprocessor timing clock and the falling edges of the second microprocessor timing clock. In the second mode, the timing system generates the first and second microprocessor timing clocks in response to the externally generated bus timing clock. In both modes, the timing system initiates an output onto the bus upon the common assertion of the first microprocessor timing clock and the bus timing clock and initiates sampling of an input from the external bus upon the inverse assertion of the second microprocessor timing clock and the bus timing clock.

Description: The present invention generally relates to a timing system for use in a microprocessor for initiating microprocessor outputs onto and input sampling from an external bus in synchronism with a bus timing clock on the bus. The present invention more particularly relates to such a timing system which is configurable for providing the external bus with the bus timing clock or being driven by an externally generated bus timing clock. The timing system of the present invention is configured to provide the bus with the bus timing clock and when so configured, is also arranged to minimize the time required to provide an output onto the bus (clock to output time). The timing system is also configured to be readily driven by an externally generated bus timing clock. Processing systems which incorporate at least one processor and at least one device, such as a memory, external to the microprocessor generally include an external bus to permit the microprocessor to perform external accesses. When such external accesses are required, such as when the microprocessor provides an output onto the external bus or samples an input from the external bus, the external accesses must be performed by the microprocessor in synchronism with the bus timing clock which controls the timing of the external bus. Such synchronization is required because the bus timing clock may or may not be at the same frequency as the microprocessor timing clocks and, in either case, is generally not in phase with the microprocessor timing clocks. In addition, such synchronization is further required because the external bus timing generally only permits microprocessor outputs onto the external bus when the bus clock is in a predetermined portion of its cycle, such as when the bus clock is at a high level, and only permits input sampling from the external bus when the external bus timing clock is in another predetermined portion of its clock cycle, such as when the bus timing clock is at a low level. Hence, microprocessors generally require a timing system for synchronizing external bus accesses with the bus timing clock which controls the timing of the external bus. In one microprocessing system, the synchronizing timing depends on the occurrence of the rising edges of the bus timing clock. Upon a rising edge of the bus timing clock, the external bus is ready to receive outputs, such as data, from the microprocessor. The time required for the microprocessor to provide an output from the rising edge of the bus timing clock is referred to as the clock to output time and is an important parameter since, as the clock to output time is shortened, the time that the external system has for sampling the microprocessor outputs is lengthened. Also of importance is the set-up time which is the time from when an input to be sampled by the microprocessor is provided by the external bus to the next rising edge of the bus timing clock. As the set-up time is shortened, the time in which the external bus must hold the input data valid is decreased. Also, a shortened set-up time gives the external system more time to sample a responsive output from the microprocessor, such as when the microprocessor must change the state of the bus during the next bus timing clock cycle. Patent specification US-A-4 409 671 discloses a timing circuit for use in a microprocessor, which uses an external clock signal for generating complementary microprocessor clock signals and for synchronizing microprocessor input/outputs on an external bus. Patent application FR-A-2 553 542 discloses a timing circuit for generating a timing signal for an external bus by delaying a system clock. Microprocessors are also often required to generate the bus timing clock for the external bus and the external system in addition to generating its own internal timing clocks. The timing system of one known microprocessor is adapted to be coupled to an external clock source having a frequency twice that of the bus timing clock and the microprocessor internal timing clocks. In this microprocessor, the timing system uses the external clock to derive an intermediate clock from which it generates the bus timing clock. The bus timing clock is then used to generate the internal microprocessor timing clocks. While this configuration is satisfactory, the clock to output time is lengthened since the rising edges of the internal microprocessor clock controlling outputs is necessarily delayed with respect to the rising edges of the bus timing clock. The timing systems of microprocessors are also called upon to be driven by an externally generated bus timing clock, as for example in multiprocessor systems. The aforementioned prior art processor still generates its own internal timing clocks in response to the externally generated bus timing clock. Unfortunately, the implementation of this system leaves much to be desired. For example, required internal duty cycles, to satisfy microprocessor speed path requirements, must be met. This problem is aggravated by the requirement that the externally generated bus timing clock be a CMOS input requiring TTL (transistor-transistor logic) level translation which skews the duty cycles from which the microprocessor internal timing clocks are derived. This makes it difficult for duty cycle requirements of the internal microprocessor timing clocks to be met for high frequency microprocessor operation. There is therefore a need in the art for a new and improved timing system for use in a microprocessor for synchronizing microprocessor external accesses to the bus timing clock of an external bus. Such a timing system should be configured to be readily implemented to be driven by an externally generated bus timing clock. Such a timing system should be further configured for providing the external bus with the bus timing clock and, when so configured, should additionally be capable of reducing the clock to output times. The present invention provides a timing system for use in a microprocessor for synchronizing the supply of microprocessor output data from said microprocessor to an external bus with a bus timing clock on the external bus. The timing system is adapted to be coupled to an external clock source and includes buffer means including an input adapted to be coupled to the external clock source for generating an intermediate clock in response to the external clock source, first generating means coupled to the buffer means for generating first and second microprocessor timing clocks responsive to the intermediate clock, the first and second timing clocks being of inverse phase relation and second generating means coupled to the buffer means and adapted to be coupled to the external bus for providing the external bus with the bus timing clock responsive to the intermediate clock. The second and first generating means are arranged such that the rising edges of the bus timing clock substantially coincide with the rising edges of the first timing clock and the falling edges of the second timing clock. The timing system further includes output means coupled to the first and second generating means and adapted to be coupled to the external bus for initiating said supply of output data from said microprocessor to the external bus upon the common assertion of the bus timing clock and the first timing clock. The timing system may also include input means adapted to be coupled to the external bus and coupled to the first and second generating means for initiating the reception of an input from the external bus upon inverse assertion of the bus timing clock and the second timing clock. The present specification further describes a timing system for use in a microprocessor for synchronizing microprocessor external bus outputs with a bus timing clock. The timing system provides improved flexibility by being configured for either generating the bus timing clock when in a first mode of operation or being driven by an externally generated bus timing clock when in a second mode of operation. The timing system includes buffer means having an input adapted to be coupled to an external clock source for generating a first intermediate clock when said timing system is operable in said first mode or coupled to an externally generated bus timing clock for generating a second intermediate clock when the timing system is operable in the second mode and first generating means coupled to the buffer means for generating first and second microprocessor timing clocks in response to the first intermediate clock when the timing system is in the first mode and in response to the second intermediate clock when the timing system is in the second mode. The first and second timing clocks are opposite in phase relation. The timing system further includes second generating means coupled to the buffer means when said timing system is in the first mode for internally generating the bus timing clock in response to the first intermediate clock. The second generating means also includes an output adapted to be coupled to the bus for providing the bus with the internally generated bus timing clock when the timing system is in the first mode and also being adapted to be coupled to the bus when the timing system is in the second mode for receiving the externally generated bus timing clock. The timing system further includes enable means responsive to a select signal for coupling the second generating means to the buffer means when the timing system is in the first mode and decoupling the second generating from the buffer means when the timing system is in the second mode and output means coupled to the first generating means for receiving the first timing clock and coupled to the second generating means output for receiving the internally generated bus timing clock when the timing system is in the first mode or the externally generated bus timing clock when the timing system is in the second mode. The output means is also coupled to the bus and is arranged to initiate an output onto the bus upon the common assertion of the first timing clock and the internally generated bus timing clock when the timing system is in the first mode or upon the common assertion of the first timing clock and the externally generated bus timing clock when the timing system is in the second mode. In the accompanying drawings, by way of example only: Figure 1 is a schematic circuit diagram of a timing system embodying the present invention; Figure 2 is a plurality of wave forms illustrating the operation of the timing system of Figure 1 when operative in a first mode of operation; and Figure 3 is a plurality of wave forms illustrating the operation of the timing system of Figure 1 when operative in a second mode of operation. Referring now to Figure 1, it illustrates a timing system 10 embodying the present invention. The timing system 10 generally includes a buffer 12, first generating means 14, second generating means 16, output means 18, input means 20, and enable means 22. The timing system 10 is preferably implemented within the integrated circuit of the microprocessor and is thus preferably implemented using CMOS technology. The buffer 12 includes an input 24 which is coupled to an external input pin 26 of the integrated circuit. As will be described more fully hereinafter, the timing system 10 is configured for operation in a first mode wherein the timing system provides an external bus with its bus timing clock in response to an external clock source being coupled to the input pin 26 and operative in a second mode of operation wherein the timing system 10 is driven by an externally generated bus timing clock which is coupled to the input pin 26. The buffer 12 has an output 28 which is coupled to the first generating means 14. When the timing system is in the first mode of operation, the buffer 12 provides at its output 28 a first intermediate clock in response to the external clock source coupled to input pin 26 and when the timing system is operative in the second mode of operation, the buffer 12 provides at its output 28 a second intermediate clock in response to the externally generated bus timing clock coupled to input pin 26. The intermediate clocks are utilized by the first generating means 14 for providing at outputs 30 and 32 first and second microprocessor timing clocks PH1 and PH2 respectively. The buffer 12 buffers the input clocks that it receives and provides TTL translation when the input clock to buffer 12 is an externally generated bus timing clock. In addition, the buffer 12 provides duty cycle adjustments to accommodate speed paths within the microprocessor. Preferably, the buffer 12, in practicing the present invention, is a self-regulating clock generator. The first generating means 14, responsive to the intermediate clocks provided by the buffer 12 at output 28, generates at outputs 30 and 32 first and second microprocessor timing clocks PH1 and PH2 respectively which are of inverse phase relation. The first generating means includes a first NOR gate 34, a first plurality of buffering inverters 36, 38, 40 and 42, a second NOR gate 44, a second plurality of buffering inverters 46, 48, 50 and 52, and another inverter 54. The first plurality of inverters, 36, 38, 40 and 42, are coupled between the output of NOR gate 34 and the output 30 of the first generating means. The second plurality of buffering inverters, 46, 48 50 and 52 are similarly coupled between the output of NOR gate 44 and the output 32 of the first generating means 14. NOR gate 44 has an input coupled directly to the output 28 of buffer 12 and NOR gate 34 has an input which is coupled to the output 28 of buffer 12 through the inverter 54. The NOR gates 34 and 44 each have their outputs and one input crosscoupled. By virtue of this circuit configuration, the first generating means 14 provides the first and second microprocessor timing clocks at outputs 30 and 32 respectively which are in inverse phase relation in response to the intermediate clocks received from the output 28 of the buffer 12. The second generating means 16 includes a plurality of serially coupled inverters 56, 58, 60 and 62, an N-Channel filed-effect transistor 64, and a P-Channel field-effect transistor 66. The second generating means further includes an output 68 which is coupled to an external pin 70. As will be described hereinafter, when the timing system 10 is in the first mode of operation, the second generating means 16 generates the bus timing clock for the external bus. For that purpose, the pin 70 is adapted to be coupled to the external bus for providing the external bus with the bus timing clock generated by the timing system 10 when the timing system 10 is in the first mode of operation. When the timing system is in the second mode of operation, the external pin 70 is adapted to be coupled to the external bus as an input for receiving an externally generated bus timing clock. When the timing system in the second mode of operation, the enable means 22 decouples the second generating means 16 from the buffer 12 in a manner to be described hereinafter and the external pin 70 is coupled to the external pin 26 as indicated by the dashed line 72. The enable means 22 includes a NAND gate 74, a NOR gate 76 and an inverter 78. The inverter 78 and NAND gate 74 have inputs coupled to an external select pin 80 for receiving an externally generated mode select signal. When the select signal applied to external pin 80 is a high logic level, the NAND gate 74 and NOR gate 76 couple the output of inverter 62 to the gates of the field-effect transistors 66 and 64 to permit the second generating means 16 to generate the bus timing clock at output 68 which is applied to the external pin 70. Hence, when the timing system is in the first mode of operation, the external pin 70 serves as an output pin to provide the external bus with the bus timing clock. When the select signal applied to external pin 80 is a low logic level, corresponding to the second mode of operation, the NAND gate 74 and NOR gate 76 decouple the output of inverter 62 from the second generating means 16 by turning off field-effect transistors 64 and 66. As a result, in the second mode of operation, the external pin 70 is utilized as an input pin for providing an externally generated bus clock to the output 68 of the second generating means. The input of inverter 56 is coupled to the output 28 of buffer 12 by a multiplexer 82. The multiplexer 82 has a first input 84 which is coupled directly to the output 28 of buffer 12. A frequency divider 88 couples the other input 86 of multiplexer 82 to the output 28 of buffer 12. The multiplexer further includes a select input 90 for coupling either input 84 to the input of inverter 56 or the input 86 to the input of inverter 56 responsive to a select signal applied at the select input 90. The frequency divider 88 is preferably a divide-by-two frequency divider. This arrangement permits the second generating means 16, when the timing system 10 is in the first mode of operation, to generate a bus timing clock which is either at a frequency equal to the first and second microprocessor timing clocks or at a frequency which is a fraction (one-half) of the first and second microprocessor timing clocks. As can thus be seen from the foregoing, when the select signal at external pin 80 is at a high logic level, the timing system 10 is configured for operating in the first mode of operation wherein the second generating means 16 provides the external bus with the bus timing clock at external pin 70. The field-effect transistors 64 and 68 by being coupled to the output of inverter 62 when the timing system is in the first mode of operation will provide an internally generated bus timing clock in response to the first intermediate clock provided at output 28 of buffer 12. When the mode select signal at external pin 80 is at a low logic level, the field-effect transistors 66 and 64 are turned off and thus decoupled from the output of inverter 62 for disabling the second generating means 16. In this mode of operation, the external pin 70 is adapted to be coupled to the external bus for receiving an externally generated bus timing clock which is provided at the output 68 of the second generating means 16. The plurality of inverters, 56, 58, 60 and 62, are provided to impose an analog delay together with the analog delays imposed by NAND gate 74 and NOR gate 76 so that the rising edges of the internally generated bus timing clock provided by the second generating means 16 when the timing system 10 is in the first mode of operation substantially coincide with the rising edges of the first microprocessor timing clock (PH1) at output 30 and also substantially coincide with the falling edges of the second microprocessor timing clock (PH2) at output 32. As will be appreciated by those skilled in the art, the number of serially coupled inverters may be increased or decreased depending upon the amount of analog delay necessary to substantially coincide the rising edges of the internally generated bus timing clock with the rising edges of the first microprocessor timing clock and the falling edges of the second microprocessor timing clock. In accordance with this preferred embodiment, the microprocessor, for which the timing system 10 provides timing control, is arranged to provide outputs onto the external bus when the bus timing clock is at a high logic level and to sample inputs from the external bus when the bus timing clock is at a low logic level. To synchronize outputs onto the external bus, the output means 18 includes gate means 92 including NAND gate 94 and inverter 96, an output buffer 98, inverters 100 and 102, and N-Channel field-effect transistors 104 and 106. NAND gate 94 includes a first input 108 coupled to the output 30 of the first generating means 14 for receiving the first microprocessor timing clock and a second input 110 which is coupled to the output 68 of the second generating means 16 for receiving the internally generated bus timing clock when the timing system 10 is operative in the first mode and the externally generated bus timing clock when the timing system is operative in the second mode. The output of NAND gate 94 is coupled to the input of inverter 96 which has its output coupled to the clock input 112 of the output buffer 98. The output buffer 98 includes a data input 114 which is coupled to the output of inverter 100. Inverter 100 has an input which is coupled to the source of field-effect transistor 104. The drain of field-effect transistor 104 is adapted to be coupled to the source of data within the microprocessor which provides the data to be outputted onto the external bus. The output buffer 98 also includes an enable input 116 which is coupled to a data enable through inverter 102 and field-effect transistor 106. The gates of the field-effect transistors 104 and 106 are coupled to the output 32 of the first generating means 14 for receiving the second microprocessor timing clock. By virtue of this arrangement, data to be outputted is updated by transistors 104 and 106 during a high phase of PH2 and then outputted under the control of NAND gate 94 as described hereinafter. The output buffer also includes an output 118 which is coupled to an output pin 120 of the integrated circuit. Hence, the output buffer 98 is arranged to receive and hold data transferred to it during the high phase of PH2 and to output data onto the external bus during the high phase of PH1 after the falling edge of PH2. A tristatable I/O could also be employed by linking output pin 120 within input pin 122. When the timing system 10 is in the first mode of operation and data is to be outputted onto the external bus, the output means 18 initiates the microprocessor output onto the external bus upon the common assertion of the internally generated bus timing clock and the first microprocessor timing clock. When in the second mode of operation, the output means initiates the microprocessor output onto the external bus upon the common assertion of the externally generated bus timing clock and the first microprocessor timing clock. The common assertion corresponds to the bus timing clocks and the first microprocessor timing clock being at a high logic level. The reason that the assertion is delayed on both of these edges is to insure positive clock to output and zero hold time on the previous state (for input 110) and to insure no internal speed path from late signals into the output buffer (for input 108). Upon such common assertion, the output buffer is clocked at its clock input 112 to shift the data being held therein to the output 118 and to the output pin 120 for placement onto the external bus. The output onto the external bus will occur after an output delay represented by the delays imposed by the NAND gate 94, the inverter 96 and the output buffer 98. However, when in the first mode of operation, because the rising edges of the internally generated bus timing clock and the rising edges of the first microprocessor timing clock substantially coincide, the clock to output delay will only be the aforementioned output delay plus the slight offset between the rising edges of the internally generated bus timing clock and the first microprocessor timing clock. Thus, the clock to output time is minimized in this system over the aforementioned prior art without inducing any on chip speed paths for signals setting up to the clock late. The data to be outputted is transferred to and held by the output buffer upon the immediately preceding rising edge of the second microprocessor timing clock combined with an enable data signal applied to the field-effect transistor 106. Since the gates of field-effect transistors 104 and 106 are coupled together, the data to be outputted is latched to the data input 114 of output buffer 98 upon the falling edge of the second microprocessor timing clock which immediately proceeds the common assertion of the first microprocessor timing clock and the bus timing clock. For sampling inputs from the external bus, the input means 20 of the timing system 10 is coupled to an external input pin 122 adapted to be coupled to the external bus. The input means 20 includes a pair of buffering inverters 124 and 126, first and second N-Channel field-effect transistors 128 and 130 respectively, and a latch 132 comprising reversed coupled inverters 134 and 136. The gate of the first field-effect transistor 128 is coupled to the output 68 of the second generating means 16 through an inverter 138. The gate of field-effect transistor 130 is coupled to the output 32 of the first generating means 14 for receiving the second microprocessor timing clock (PH2). This then allow sampling only the combined signals of PH2 and the bus timing clock, giving synthesizing to internal clocks as well as meeting the setup and hold time of the external system using the bus timing clock. By virtue of inverter 138, the input means 20 is arranged for initiating the reception of an input from the external bus upon the inverse assertion of the second microprocessor timing clock and the internally generated bus timing clock when the timing system 10 is operative in the first mode or the externally generated bus timing clock when the timing system 10 is operative in the second mode. Such inverse assertion corresponds to the second microprocessor timing clock being at a high logic level and the bus timing clock being at a low logic level. The low logic level of the bus timing clock is inverted by inverter 138 such that upon such inverse assertion, both field-effect transistors 128 and 130 will be turned on to transfer input data from the external bus into the latch 132. The latch 132 is provided to stabilize the sampled data before the sampled data is acted upon by the microprocessor at the beginning of the next clock period of the first microprocessor timing clock (PH1). Referring now to Figure 2, the waveforms there depicted illustrate the manner in which the timing system 10 is operative in the first operating mode for initiating outputs onto the external bus and for initiating the sampling of inputs from the external bus. More specifically, Figure 2 illustrates the first intermediate clock 140, the first microprocessor timing clock (PH1) 142, the second microprocessor timing clock (PH2) 144, the internally generated bus timing clock 146, a microprocessor output 148, and an external bus input 150. As will be noted, the rising edges of the bus timing clock substantially coincide with the rising edges of the first microprocessor timing clock and the falling edges of the second microprocessor timing clock. The clock to output time 152 is represented by the aforementioned output delay and the slight difference between the phase relationship of the bus timing clock and the first microprocessor timing clock which substantially coincide. As a result, the clock to output delay is substantially only the output delay of the microprocessor. For external bus inputs, it will be noted that the external bus input occurs when the bus timing clock is at a low logic level and the second microprocessor timing clock is at a high logic level. The set-up time therefore is indicated at 154 and is the time between the time at which the input occurs on the external bus and the next rising edge of the bus timing clock. Referring now to Figure 3, it illustrates waveforms which depict the operation of the timing system 10 when operative in the second mode wherein the bus timing clock is provided from an external source and the first generating means 14 generates the first and second microprocessor timing clocks in response to the second intermediate clock which is in turn derived by the buffer 12 from the externally generated bus timing clock. Illustrated in Figure 3 is the second intermediate timing clock 160, the first microprocessor timing clock (PH1) 162, the second microprocessor timing clock (PH2) 164, a microprocessor output 166 and an external bus input 168. For purposes of this discussion, it is assumed that the delay imposed upon the externally generated bus timing clock by the buffer 12 is negligible and therefore the second intermediate clock 160 substantially corresponds to or, in other words, is in phase with the externally generated bus timing clock. With respect to the microprocessor output 166, it will be noted that the output occurs after the aforementioned output delay which begins upon the common assertion of the first microprocessor timing clock 162 and the second intermediate clock 160. The total clock to output time is equal to the clock delay imposed by the first generating means 14 in generating the first microprocessor timing clock in response to the second intermediate clock plus the microprocessor output delay. With respect to the input 68 on the external bus to be sampled by the microprocessor, the set-up time is illustrated at 170 and is the time from the occurrence of the input on the external bus to the next rising edge of the second intermediate clock. This is the set-up time seen by the external system. The real set-up time also includes an additional time period running from the rising edge of the second intermediate clock signal to the next rising edge of the first microprocessor timing clock and is represented at 172. This additional time period represents the time in which the microprocessor will next be able to initiate an output onto the external bus as, for example, when the microprocessor must change the condition of the external bus in response to the input 168. All of the clock to output and set-up times depicted in Figures 2 and 3 are well within acceptable limits for high-speed microprocessor operation, such as, at a frequency of 25 Megahertz. While the clock to output illustrated in Figure 3 is substantially equal to the clock to output times of prior art timing systems, the present invention exhibits a distinct advantage over prior timing systems in that the first and second microprocessor timing clocks are only loosely coupled to the externally generated bus timing clock and the timing system of the present invention may be more readily implemented for being driven by an externally generated bus timing clock. This is due to the fact that the externally generated bus timing clock need no longer be specified as a CMOS input and the output and input means 18 and 20 respectively are configured for accommodating required duty cycles to accommodate microprocessor speed paths. Also, this system allows a processor to be configured to be optimized for minimizing either clock to output times or set-up times. While a particular embodiment of the present invention has been shown and described, modifications may be made, and it is therefore intended to cover in the appended claims all such changes and modifications which fall within the scope of the invention.

Claims: A timing system for use in a microprocessor for synchronizing the supply of output data (104) from said microprocessor to an external bus with a bus timing clock (BCLK) on said external bus and adapted to be coupled to an external clock source, said timing system comprising: buffer means (12) including an input (24) adapted to be coupled to said external clock source for generating an intermediate clock (28) in response to said external clock source; first generating means (14) coupled to said buffer means (12) for generating first (PH1) and second (PH2) internal microprocessor timing clocks responsive to said intermediate clock (28), said first and second timing clocks being of inverse phase relation; second generating means (16) coupled to said buffer means (12) and adapted to be coupled to said external bus for providing said external bus with said bus timing clock (BCLK, 68, 146) responsive to said intermediate clock (28), said second and first generating means being arranged such that the rising edges of said bus timing clock (146) substantially coincide with the rising edges of said first timing clock (PH1) and the falling edges of said second timing clock (PH2); and output means (18) coupled to said first and second generating means and adapted to be coupled to said external bus for initiating said supply of output data from said microprocessor to said external bus upon the common assertion of said bus timing clock (BCLK) and said first timing clock (PH1). A timing system as defined in claim 1 wherein said output means (18) includes output gate means (92) for initiating said supply of said output data when said bus timing clock (BCLK) and said first timing clock (PH1) are at a high logic level. A timing system as defined in claim 1 or claim 2 further including input means (20) adapted to be coupled to said external bus and coupled to said first (14) and second (16) generating means for synchronizing the reception of input data, to be supplied to said microprocessor, from said external bus with said bus timing clock responsive to an inverse assertion of said bus timing clock (BCLK) and said second timing clock (PH2). A timing system as defined in claim 3 wherein said input means (20) includes input gate means (128, 130) for initiating said reception of said input data when said bus timing clock (BCLK) is at a low logic level and said second timing clock (PH2) is at a high logic level. A timing system as defined in claim 1 wherein said second generating means (16) further includes a mode select input (80) for receiving a mode select signal for selecting a first mode or a second mode, wherein said second generating means is responsive to said mode select signal for operating in said first mode for providing said bus timing clock (BCLK, 146) at a second generating means output (68), and wherein said timing system is responsive to said mode select signal for operating in said second mode for receiving an externally generated bus timing clock (BCLK, 160) at said second generating means output and for initiating said supply of microprocessor data onto said external bus upon the common assertion of said externally generated bus timing clock (BCLK, 160) and said first timing clock (PH1). A timing system as defined in claim 5 wherein said second generating means output (68) and said buffer means input (24) are arranged to be coupled together (72) when said timing system is operative in said second mode to permit said first generating means to generate said first and second timing clocks responsive to said externally generated bus timing clock (BCLK, 160). A timing system as defined in claim 6 wherein said second generating means further includes enable means (22) for disabling said second generating means responsive to said mode select signal selecting said second mode. A timing system as defined in any one of claims 5 to 7 wherein said output means includes output gate means (92) for initiating said supply of said microprocessor output data responsive to said first timing clock (PH1) and said bus timing clock (BCLK, 146) being at a high logic level when said timing system is operative in said first mode, and said first timing clock (PH1) and said externally generated bus timing clock (BCLK, 160) being at a high logic level when said timing system is operative in said second mode. A timing system as defined in any one of claims 5 to 8 further including input means (20) coupled to said first generating means (14) and to said second generating means output (68) for initiating the reception of input data from said bus upon inverse assertion of said bus timing clock (BCLK, 146) and said second timing clock (PH2) when said timing system is operative in said first mode and for initiating the reception said input data from said bus upon inverse assertion of said externally generated bus timing clock (BCLK, 160) and said second timing clock (PH2) when said timing system is operative in said second mode. A timing system as defined in claim 9 wherein said input means (20) includes input gate means (128, 130) for initiating said reception responsive to said second timing clock (PH2) being at a high logic level and said bus timing clock (BCLK, 146) being at a low logic level when said timing system is operative in said first mode and responsive to said second timing clock (PH2) being at a high logic level and said externally generated bus timing clock (BCLK, 160) being at a low logic level when said timing system is operative in said second mode. A timing system as defined in any one of claims 2 to 4 or 8 to 10 wherein said output gate means (92) includes a first input (108) coupled to said first timing clock (PH1) and a second input (110) coupled to said bus timing clock (BCLK, 146; BCLK, 160). A timing system as defined in claim 11 wherein said output gate means (92) comprises a NAND gate (94) and an inverter (96), said NAND gate and said inverter being series coupled. A timing system as defined in claim 12 wherein said output means further includes an output buffer (98) having a data input (114) for receiving and holding said microprocessor output data to be supplied to said external bus, a clock input (112) coupled to said inverter (96), and an output (118) adapted to be coupled to said external bus. A timing system as defined in claim 13 wherein said output buffer (98) is configured to receive and hold said microprocessor output data upon the rising of said second timing clock (PH2). A timing system as defined in claim 14 wherein said output buffer (98) further includes an enable input (116) for enabling said output buffer to hold said microprocessor output data responsive to said rising edge of said second timing clock (PH2). A timing system as defined in claim 4 or claim 10 wherein said input gate means includes first (128) and second (130) series coupled field-effect transistors, wherein the gate of said first field-effect transistor (128) is coupled to said bus timing clock (BCLK, 146; BCLK, 160) and wherein the gate of said second field-effect transistor (130) is coupled to said second timing clock (PH2). A timing system as defined in claim 16 further including an inverter (138), wherein said first (128) and second (130) field-effect transistors are N-channel transistors and wherein said gate of said first field-effect transistor (128) is coupled to said bus timing clock by said inverter (138). A timing system as defined in claim 16 or claim 17 wherein said input means further includes a latch (132) for stabilizing said received input. A timing system as defined in any one of claims 1 to 18 wherein said second generating means (16) includes delay means (56-62) for substantially synchronizing said rising edge of said internally generated bus timing clock (BCLK, 146) with said rising edge of said first timing clock (PH1) and said falling edge of said second timing clock (PH2). A timing system as defined in claim 19 wherein said delay means (56-62) comprises a plurality of serially coupled inverters (56-62). A timing system as defined in any one of claims 1 to 20 further including a frequency divider (88) and select means (82) for selectively coupling said frequency divider (88) between said buffer means (12) and said second generating means (16) for rendering said internally generated bus timing clock (BCLK, 146) at a frequency which is a fraction of the frequencies of said first (PH1) and second (PH2) timing clocks. A timing system as defined in claim 21 wherein said frequency divider (88) is a divide-by-two frequency divider. A timing system as defined in claim 21 or claim 22 wherein said select means (82) comprises a multiplexer (82) having a first input (84) coupled to said buffer means (12), a second input (86) coupled to said frequency divider (88), an output coupled to said second generating means (16), and a control input (90).

Inventors: WITT DAVID BRUCE, WITT, DAVID BRUCE
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1992
Main classification: G06F13
IPC codes: G06F1, G06F13