Phase divider for complex signals

Abstract: In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.

Description: The present invention relates generally to phase dividers, and more particularly to a frequency divider for quadrature signals. In synchronous detectors for M-ary phase shift keyed signals, a series of an M-th power multiplier, a low-pass filter and a 1/M frequency divider is connected to the output of an A/D converter to recover the transmitted carrier for synchronously detecting the original signal. The 1/M frequency divider comprises an xy-to- (phase) conversion table which detects the phase angle of quadrature (complex) signals from the A/D converter and supplies it to a phase divider that divides the detected phase angle with a ratio 1/N. The output of the phase divider is coupled to a sine translation table and a cosine translation table to generate cosine (real part) and sine (imaginary part) wave signals. The phase  i of the input signal to the 1/M frequency divider is defined within the range between -π and +π. If there is a phase change of 2π, the input phase can be represented as ' i =  i + 2π. However, the phase conversion table cannot discriminate between ' i and " j and treats the input phase equivalently as " i =  i (mod 2π). Under such circumstances, the division by the phase divider results in a phase angle " i /M =  i /M. Since it must be ' i /M =  i /M + 2π/M, a phase error of 2π/M results. IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, Vol. 5, No. 3, April 1987, New York, U.S., pp. 524-533, RUSTAKO A.J. et al.: "Using Times-Four Carrier Recovery in M-QAM Digital Radio Receivers" discloses time-four carrier recovery in a digital radio receiver. The twofold function of the PLL is to extract the line component and to filter out most of the random component. Part of what remains of this random component causes phase jitter of the VCO output. By virtue of using a x4 circuit between the VCO and the PLL phase detector, the VCO can be centred near the desired intermediate frequency. Its output is thus the desired local frequency reference and can be applied to the coherent demodulation circuit. It is therefore an object of the present invention to provide a phase divider capable of phase division without introducing quantum variations of phase. This object is solved with the features of the claims. The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a phase divider of the present invention; Fig. 2 is an equivalent block diagram of Fig. 1; Fig. 3 is a circuit diagram of the loop filter of Fig. 1; and Fig. 4 is a block diagram of a synchronous detector for an M-ary PSK signal incorporating the phase divider of the present invention. In Fig. 1, a phase divider of the present invention comprises a first complex limiter 1 for receiving through input terminals A 1 , A 2 a variable amplitude input complex signal which is a sequence of digital samples of real and imaginary values for limiting the amplitude of the input complex signal to a constant amplitude of unit value. A first complex multiplier 2 is connected to the outputs of the first complex limiter 1 for multiplying the complex signal from the first complex limiter 1 with a first feedback complex signal supplied from a complex multiplier 8 of M-th power which is connected to the outputs of one-sample delay circuits 6, 7. The M-th power complex multiplier 8 is a series of complex multipliers 8 1 , 8 2 , ..... 8 (M-1) , each multiplying the input complex signal from one-sample delay circuits 6, 7 with the output of the preceding stage. A complex low-pass (loop) filter 3 is connected between the first complex multiplier 2 and a second complex multiplier 4 having identical configuration to multiplier 2 to remove high frequency components. The second complex multiplier 4 multiplies the outputs of low-pass filter 3 with a second complex feedback signal from the output terminals B 1 , B 2 . A second complex limiter 5, identical to limiter 1, is connected to the outputs of multiplier 4 for limiting the amplitude of the input complex signal therefrom to a constant amplitude of unit value. One-sample delay circuits 6 and 7 are provided for introducing a one-sample interval to the outputs of limiter 5 for application to output terminals B 1 , B 2 , on the one hand, and to the second complex multiplier 4 as the second feedback complex signal, on the other. As illustrated, complex limiter 1 is made up of squaring circuits 11 and 12 connected to input terminals A 1 and A 2 , respectively, the outputs of squaring circuits 11, 12 being summed by an adder 13 and fed to a inverse square root circuit 14. Multipliers 15 and 16 are respectively connected to input terminals A 1 and A 2 to multiply the real and imaginary components of the input complex signal with the output of the inverse square root circuit 14. If the input complex signal is represented as W 1 = u 1 + j · v 1 , where u 1 and v 1 are the real and imaginary parts of the signal, respectively, then the outputs of multipliers 15 and 16 form an output complex signal W 2 which is given by: W 2 = u 2 + j · v 2 = u 1 + j ·v 1 u 2 1 +v 2 1 Since |W 2 | 2 = u 2 1 +v 2 1 u 2 1 +v 2 1 = 1, the amplitude of the input complex signal of limiter 1 is normalized to a constant amplitude of unit value. Complex multiplier 2 comprises a first pair of multipliers 21 and 22 and a second pair of multipliers 23 and 24. The first input of multipliers 21 and 23 is connected to the output of multiplier 15 and the first input of multipliers 22 and 24 is connected to the output of multiplier 16. A subtractor 24 is connected between the outputs of the multipliers of the first pair to produce a signal which forms the real part of the complex output of multiplier 2. An adder 25 is connected between the outputs of the multipliers of the second pair to produce a signal which forms the imaginary part of the output. The second input of multipliers 21 and 24 is connected to one output of multiplier 8, the second input of multipliers 22 and 23 being connected to the other output of multiplier 8. If the feedback complex signal from multiplier 8 is represented as W 3 = u 3 + j v 3 = r 3 e j3 and the complex signal from the preceding stage is represented as W 2 = u 2 + v 2 = r 2 ej2, then the complex output of multiplier 2 is: W 2 x W 3 = (u 2 u 3 - v 2 v 3 ) + j(u 2 u3 + v 2 j 3 ) = (u 2 + j v 2 )(u 3 + j v 3 ) = r 2 r 3 e j(2 + 3). Since W 2 and W 3 are both normalized to unit value, W 2 x W 3 is equal to e j(2 + 3) , It is seen that by normalizing the amplitude of complex signals to a unit value the multiplication of these signals is equivalent to a summation of their phase components. An equivalent circuit of the phase divider can be represented is shown in Fig. 2 as comprising a subtractor 30 corresponding to multiplier 2, loop filter 31 corresponding to filter 3, an adder 32 corresponding to multiplier 4, delay operator 33, and a M-fold phase multiplier 34 corresponding to M-th power multiplier 8. In Fig. 2, the signals are represented by z-transform of input phase  i (t) and output phase  o (t), where z = e jωT (T = sampling intervals) and the following relations hold: Since Θ o (z) = H(z)·z -1 /(1 - z -1 ) {Θ i (z)- M·Θ o (z)}, the transfer function T(z) of the phase divider is given by the following relation: T(z)= Θ o (z) Θ i (z) = H(z) z -1 1-z -1 1+M·H(z) z -1 1-z -1 = 1 M · M·H(z) z -1 1-z -1 1+M·H(z) z -1 1-z -1 Since the M·H(z) terms of Equation (2) imply that the loop filter has a gain M, and so Equation (2), as a whole, indicates that the phase divider of the present invention has the effect of dividing an input phase with a ratio M without introducing undesirable quantum phase "jumps". If loop filter 3 is constructed as shown in Fig. 3 having the following z-transform function H(z): H(z) = α + β·z -1 1-z -1 then, the transfer function T(z) is given by: By denoting Mα=A, Mβ=B, Equation (4) can be rewritten as: T(z)= 1 M · A z -1 1-z -1 + B z -1 1-z -1 1+A z -1 1-z -1 + B z -1 1-z -1 If z=e s/fs , (where fs is the sampling frequency), and if the sampling frequency is sufficiently high, z=e s/fs ≈ H·s/fs, and z ≈ 1, and T(z) is represented as:. T(z) ≈ T(s) = 1 M · A ·fs·S+B·fs 2 S 2 + A · fs·S+B·fs 2 = 1 M · 2ζ·ω n ·S+ω n 2 S 2 + 2ζ · ω n ·S+ ω n 2 where, ω n = √B · fs and ζ = 1 / 2 - A / √B. Equation (6) indicates that the phase divider operates in a manner similar to conventional phase locked loops. The phase divider of the present invention is incorporated in a synchronous detector for M-ary phase-shift keying signals as shown in Fig. 4. The synchronous detector comprises mixers 40, 41 for mixing an incoming IF (intermediate frequency) signal with an in-phase carrier from a local oscillator 42 and a quadrature-phase carrier supplied from a phase shifter 43. The outputs of mixers 40, 41 are converted to digital signals of complex values by an A/D converter 44 in response to a sampling pulse from a pulse generator 45. The digital complex signal from A/D converter 44 is applied to a M-th power frequency multiplier 46 where the frequency is raised to M-th power of the input frequency and fed through a low-pass filter 47. The 1/M phase divider 48 of the present invention takes its input from the low-pass filter 47, where the phase angle  is divided by a factor M as described above so that the frequency of the signal from multiplier 46 is reduced to the baseband frequency. The output of A/D converter 44 is coupled through an appropriate delay circuit 49 to a complex multiplier 50 where it is multiplied with the output of phase divider 48 to synchronously detect the original digital signal. It is seen the present invention eliminates the need for xy-to- conversion table and cosine and sin tables which are required with the prior art phase dividers.

Claims: A phase divider comprising: a first complex limiter (1) for receiving a variable amplitude input complex signal formed by a sequence of samples of real and imaginary values for limiting the amplitude of said complex signal to a constant amplitude of unit value; a first complex multiplier (2) for multiplying the complex signal from said first complex limiter (1) with a first feedback complex signal applied thereto; loop filter means (3) connected to the output of said first complex multiplier (2); characterized by: a second complex multiplier (4) for multiplying a complex signal from said loop filter means (3) with a second feedback complex signal applied thereto; a second complex limiter (5) for limiting the amplitude of a complex signal from said second complex multiplier (4) to a constant amplitude of unit value; one-sample delay means (6) for delaying the complex signal from said second complex limiter (5) for a sample interval and applying the delayed complex signal to said second complex multiplier (4) as said second feedback complex signal; and a complex multiplier (8) of M-th power for raising the delayed complex signal to an M-th power and applying the M-power raised complexed signal to said first complex multiplier as said first feedback complex signal. A phase divider as claimed in claim 1, wherein each of said first and second complex limiters (1 and 5) comprises: first and second squaring circuits (11 and 12) for respectively squaring the real and imaginary components of an input signal applied to the limiter (1). an adder (13) for summing outputs of the first and second squaring circuits; an inverse square root circuit (14) for detecting a square root of an output signal of said adder (13) and dividing a unit value by the detected square root; and first and second multipliers (15 and 16) for multiplying the real and imaginary components of said input signal with an output signal of said inverse square root circuit (14). A synchronous detector having a frequency multiplier (46) for multiplying frequency of a digital complex signal from an analog-to-digital (A/D) converter (44), a low-pass filter (47) connected to the output of said frequency multiplier (46), and a complex multiplier (50) having a first input for receiving said complex signal from said A/D converter (44) through delay means (49) and a second input, and having a phase divider (48) comprising: a first complex limiter (1) for limiting amplitude of a complex signal from said low-pass filter (47) to a constant amplitude of unit value; a first complex multiplier (2) for multiplying the complex signal from said first complex limiter (1) with a first feedback complex signal applied thereto; loop filter means (3) connected to the output of said first complex multiplier (2); characterized by : a second complex multiplier (4) for multiplying a complex signal from said loop filter means (3) with a second feedback complex signal applied thereto; a second complex limiter (5) for limiting the amplitude of a complex signal from said second complex multiplier (4) to a constant amplitude of unit value; one-sample delay means (6) for delaying the complex signal from said second complex limiter (5) for a sample interval and applying the delayed complex signal to said second complex multiplier (4) as said second feedback complex signal and applying the delayed complex signal to the second input of the complex multiplier (50) of the synchronous detector; and a complex multiplier (8) of M-th power for raising the delayed complex signal to an M-th power and applying the M-power raised complexed signal to said first complex multiplier (2) as said first feedback complex signal. A synchronous detector, as claimed in claim 3, wherein each of said first and second complex limiters (1,5) of the phase divider (48) comprises: first and second squaring circuits (11 and 12) for respectively squaring the real and imaginary components of an input signal applied to the limiter; an adder (13) for summing outputs of the first and second squaring circuits; an inverse square root circuit (14) for detecting a square root of an output signal of said adder (13) and dividing a unit value by the detected square root; and first and second multipliers (15 and 16) for multiplying the real and imaginary components of said input signal with an output signal of said inverse square root circuit (14).

Inventors: ICHIYOSHI OSAMU, ICHIYOSHI, OSAMU, Ichiyoshi, Osamu, c/o NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H04L27
IPC codes: H04L27, H03H17