Method to produce complementary bipolar transistors

Abstract: Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile (14) by molecular beam epitaxy on an appropriate substrate (12) and then depositing a layer of silicon nitride (16) on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask (20) and resist layer (18) are used to produce the desired PNP profile patterns. The NPN profile (22) is deposited on the area of the substrate (12) etched away as well as on the silicon nitride layer (16) protecting the already deposited PNP layers. The NPN profile (22) is then patterned using a resist (24) and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to a method for fabricating complementary NPN and PNP bipolar transistors on a single substrate, and more particularly, to a method of molecular beam epitaxy for fabricating complementary NPN and PNP heterojunction bipolar transistors on a single substrate. 2. Discussion of the Related Art Different methods are known in the art for fabricating desirable NPN or PNP type semiconductor devices. When fabricating circuits which include both NPN and PNP bipolar transistors it is sometimes thought to be necessary to develop the transistors on separate substrates. It is known, however, to be extremely advantageous in many applications to develop complementary NPN and PNP bipolar transistors on the same substrate. Applicability for these complementary devices include, but are not limited to, push-pull power amplifiers and circuits incorporating active loads, both known to those skilled in the art. For a more in-depth discussion of the advantages of complementary NPN/PNP bipolar transistors over separate NPN and PNP transistors, see P.R. Gray and R.G. Meyer, "Analysis and Design of Analog Integrated Circuits", (John Wiley & Sons, New York, 1977). For semiconductor devices which are fabricated from silicon it is possible to produce bipolar NPN and PNP transistors into useful circuits on the same substrate with certain existing fabrication techniques, such as diffusion and ion implantation. In view of present day frequency and speed requirements of bipolar transistors, a much more useful device would be a heterojunction bipolar (HBT) transistor i.e., bipolar transistors which include at least one PN junction of dissimilar materials generally comprised of GaAs/AlGaAs (gallium arsenide/aluminum gallium arsenide) or InGaAs/InAlAs/InP (indium gallium arsenide/indium aluminum arsenide/indium phosphide). Fabrication techniques applicable to complementary silicon NPN and PNP bipolar transistors are generally not adequate for these types of GaAs/AlGaAs and InGaAs/InAlAs/InP HBTs. Molecular beam epitaxy is one of the most popular methods of producing semiconductor devices requiring high precision doping and thickness constraints. Whether it be silicon homojunctions or GaAs/AlGaAs or InGaAs/InAlAs/InP heterojunction transistor devices, it has been heretofore thought impossible to fabricate NPN and PNP transistors on the same substrate using molecular beam epitaxy which result in high quality devices. One not pre-published method attempted in the art has been to fabricate either an NPN or PNP layered structure on a substrate and then coat the just formed layered structure with a layer of silicon dioxide. The silicon dioxide is then removed by an appropriate method from the area of the substrate on which the opposite NPN or PNP layered structure was to be grown. This procedure has met with limited success in that the silicon dioxide layer has allowed damage to the already grown NPN or PNP layered structure during the process of growing the other structure. Consequently, such a procedure has degradated the response characteristics of the final device. A method of using metal organic vapor phase epitaxy (MOVPE) has been recently reported in the literature to develop a complementary HBT, see David B. Slater, Jr. et al. "Monolithic Integration of Complementary HBT's By Selective MOVPE", IEEE Electron Device Letters, Vol. 11, No. 4, April 1990, p. 146. procedure, the first PNP or NPN structure is developed using the MOVPE process and then a silicon nitride mask is deposited over the structure. The silicon nitride mask is then selectively etched away so that the remaining NPN structure can be developed. Although this procedure has met with some success, the performance of the ultimate complementary HBT device is poor. In addition, the MOVPE process does not have the same parameter control as can be accomplished by molecular beam epitaxy. What is needed then is a molecular beam epitaxy procedure capable of growing complementary NPN and PNP HBT devices on a common substrate. It is therefore an object of the present invention to provide such a method. SUMMARY OF THE INVENTION The object is achieved with a method as defined in claim 1. Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(A)-1(F) show the stages in fabricating the complementary NPN and PNP profiles on a single substrate; FIG. 2 shows the doping concentration of the different layers of the NPN and PNP profiles of FIG. 1; FIG. 3 shows in a block diagram flow chart the processing steps necessary to develop the HBT transistor circuits from the profiles of FIG. 2; FIGS. 4 (A)-4 (B) show the I-V characteristics of the NPN and PNP HBT complementary transistors developed by the processes above; and FIG. 5 shows the S-parameters of the frequency versus gain curve of the PNP and NPN transistors. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention or its application or uses. First turning to FIG. 1, a method of fabricating complementary NPN and PNP type profiles on a common substrate is shown. In this illustration, reference numeral 10 represents the fabricated structure as it appears throughout different development stages according to one preferred embodiment of the present invention. It is noted that structure 10 will be positioned within an appropriate vacuum chamber (not shown) in each of the different fabrication stages shown in FIGS. 1(A)-1(F). Furthermore, the profiles discussed will be deposited by molecular beam epitaxy, the procedure of which is well known to those skilled in the art. First viewing FIG. 1(A), a semi-insulating GaAs substrate 12 is shown. On substrate 12, a PNP profile 14 has been grown by molecular beam epitaxy to a desirable thickness. In FIG. 1, profile 14 (as well as profile 22 below) is shown as a single layer, however, it will be understood that this layer actually includes a series of accurately grown films, as will be described hereunder with reference to FIG. 2. In addition, the GaAs substrate 12 is used by way of example, and can equally be replaced with other appropriate substrates such as InP. Finally, PNP profile 14 is grown first because this profile will be used in a larger area than the NPN profile of the final device, and as such, it is more applicable to produce a higher quality device if the PNP profile is laid down before the NPN profile. It will be understood, therefore, that depositing an NPN profile first is within the scope of the invention. FIG. 1(B) shows a silicon nitride layer 16 which has been deposited by a process such as plasma enhanced chemical vapor deposition on PNP profile 14 opposite to substrate 12. Silicon nitride layer 16 will be used as a blocking layer to shield the grown PNP layers in areas where the PNP HBTs are to be fabricated. It should be noted that other methods of depositing silicon nitride layer 16 onto PNP profile 14 are within the scope of the present invention. Next, a resist layer 18 is deposited by a well known process on the silicon nitride layer 16. Configured above layer 18 is a mask 20 which is used to establish a desirable pattern of PNP profile areas on substrate 12. Mask 20 is shown here at some appropriate distance above resist layer 18, but it is known to position mask 20 at other levels including on resist layer 18. Resist layer 18 is exposed to radiation through configured holes in mask 20 to expose certain areas on resist layer 18 to the radiation in order to establish the desirable PNP areas on the silicon nitride layer 16. The resist layer 18 is then developed by an appropriate solvent such that the resist areas exposed to the radiation are dissolved, but the unexposed resist areas are not dissolved. Next, an etchant solution is applied to the silicon nitride layer 16 to remove the silicon nitride in the areas which coincide with the dissolved region of the resist layer 18 in order to expose the PNP profile layer below. The view of FIG. 1(B) shows the structure 10 after the resist layer 18 has been etched to expose and remove the silicon nitride layer 16 as set forth by the pattern of mask 20. In FIG. 1(C), the patterned silicon nitride layer 16 on PNP profile layer 14 is shown in which the area of substrate 12 on which the NPN profile will be grown has been cleared. Specifically, profile layer 14 and the corresponding silicon nitride layer 16 are etched by an appropriate solution, as discussed above, in areas where the complementary NPN profile layers are to be deposited. In addition, the remaining resist layer 18 has also been dissolved by an appropriate solution. The GaAs substrate 12 is then etched at the areas where exposed so that a clean surface is available for proper epitaxial growth. Further, the remaining silicon nitride masking layer 16 is densified by heating the entire structure 10 in a vacuum to approximately 350°C. This provides a clean, degassed and dense silicon nitride layer 16 before the structure 10 is re-introduced into the molecular beam epitaxial growth chamber. Now turning to FIG. 1(D), it is shown that an NPN profile layer 22 has been grown by molecular beam epitaxy on the remaining silicon nitride layer 16 over the PNP profile 14 and the clean, etched portion of substrate 12, as shown. By this procedure, a high quality crystalline epitaxial film layer is formed on the clean areas of substrate 12 and a polycrystalline material is formed on the silicon nitride layer 16. The NPN profile layer 22 is then coated with a second resist layer 24 and an appropriate mask 26 is positioned as shown in FIG. 1(E) according to the desirable NPN pattern. Once the radiation step has been performed, the resist layer 24 is then accordingly dissolved, as discussed above for the PNP profile. FIG. 1(E) shows structure 10 after resist layer 24 has been irradiated through mask 26 and etched at the irradiated locations by the appropriate solution. Next, the polycrystalline portion of the NPN profile 22 is etched by the appropriate solution, as is the remaining resist layer 24, to form two adjacent regions of PNP profile 14 and NPN profile 22, as shown in FIG. 1(F). FIG. 2 shows the different layers of the PNP profile 14 and the NPN profile 22 having been grown by molecular beam epitaxy as depicted in FIG. 1(F). In this Figure, the NPN and PNP profiles have been reversed to that of FIG. 1(E) in that the PNP profile 14 is on the right side and the NPN profile 22 is on the left side. The heterojunction NPN and PNP profiles themselves are known in the art, and therefore, their operation need not be elaborated on here. More particularly, however, the PNP profile 14 includes a first P-type GaAs contact layer 32 having a thickness of approximately 6000 angstroms (1 Ångstrom = 10 -10 m) and being doped with beryllium dopant atoms to approximately 6 x 10 18 atoms/cm -3 . Formed on top of GaAs contact layer 32 is a P-type GaAs collector layer 34 having a thickness of approximately 7000 angstroms and being lightly doped with beryllium dopant atoms to approximately 7 x 10 15 atoms/cm -3 . Formed on top of the GaAs collector layer 34 is an N-type GaAs base layer 36 having a thickness of approximately 1400 angstroms and being doped with silicon dopant atoms to approximately 6 x 10 18 atoms/cm -3 . Formed on top of base layer 36 is a P-type AlGaAs emitter layer 40 having a thickness of approximately 1800 angstroms and being doped with beryllium dopant atoms to approximately 5 x 10 17 atoms/cm -3 . Formed on top of emitter layer 40 is a P-type GaAs contact layer 42 having a thickness of approximately 750 angstroms and being heavily doped with beryllium dopant atoms to approximately 1 x 10 19 atoms/cm -3 . Regions 38 and 44 represent areas of layer 40 in which the doping is graded to meet the doping of the adjacent layers 36 and 44, respectively. Regions 38 and 44 have a thickness of approximately 300 angstroms each such that the remaining region of layer 40 is approximately 1200 angstroms. Now focusing on the NPN region 22, it is shown that an N-type GaAs contact layer 46 is first grown on substrate 12 adjacent region 14. Contact layer 46 is approximately 6000 angstroms thick and is doped with silicon atoms to approximately 6 x 10 18 atoms/cm -3 . Formed on top of contact layer 46 is an N-type GaAs collector layer 48 having a thickness of approximately 7000 angstroms and being lightly doped with silicon atoms to approximately 7 x 10 15 atoms/cm -3 . Grown on top of collector layer 48 is a P-type GaAs base layer 50 having a thickness of approximately 1400 angstroms and being heavily doped with beryllium atoms to approximately 1 x 10 19 atoms/cm -3 . Grown on top of base layer 50 is an N-type AlGaAs emitter layer 54 having a thickness of approximately 1800 angstroms and being doped with silicon atoms to approximately 5 x 10 17 atoms/cm -3 . The top layer is an N-type contact layer 58 having a thickness of approximately 750 angstroms and being doped with silicon atoms at approximately 6 x 10 18 atoms/cm -3 . Regions 52 and 56 represent areas of layer 54 in which the doping is graded to meet the doping of the adjacent layers 50 and 58, respectively. Regions 52 and 56 have a thickness of approximately 300 angstroms each, such that the remaining region of layer 54 is approximately 1200 angstroms. Once the NPN and PNP profiles as shown in FIG. 2 have been developed by the process as discussed above in FIG. 1, it is then necessary to develop the two profiles into final desirable components. In this example, as discussed above, the NPN and PNP profiles will be developed into heterojunction bipolar transistors. Turning to FIG. 3, a process for further developing the circuit incorporating both of the NPN and PNP type heterojunction bipolar transistors simultaneously from the profiles in FIG. 2 is shown in a flow chart form. The first step of developing the structure 10 as shown in FIG. 2 into a desirably configured complementary array of heterojunction bipolar transistors (as well as support devices) involves the step designated by box 64 as aligning the structure 10 in an appropriate machine for etching the emitter mesas and base mesa of both the PNP and NPN HBTs as depicted by the steps of boxes 66 and 68. The steps of etching the emitter and base mesas involves the process of using resists and appropriately configured masks, as is known in the art. The next step represented by box 70 is one of the critical steps of the formation of the complementary heterojunction bipolar transistors which enables them to be developed simultaneously in a common process. More particularly, box 70 is a P-type ohmic evaporation step in which ohmic contact layers are configured on a P-type material for both NPN and PNP profiles by an appropriate evaporation process in a single step. This step involves the use of resist layers and masks to pattern the desirable evaporation. In the NPN transistor it is the P-type base which gets the P-ohmic contact and in the PNP transistor it is the emitter and collector which get the P-ohmic contact. In a preferred embodiment, the P-ohmic contacts are a gold-beryllium composite which are formed at the desirable location on the developing NPN and PNP profiles by an electron beam evaporation process well known to those skilled in the art. Box 72 represents a first silicon nitride deposition process which forms a dielectric layer over the developing NPN and PNP profiles for providing the dielectric for certain resistor and capacitor components, and also providing a protection layer to the structure being developed. Box 74 represents a P-type ohmic anneal process following the first silicon nitride deposition step in which the wafer is heated in an appropriate chamber and allowed to cool in order to provide the desirable ohmic contacts. Box 76 represents the N-type ohmic evaporation step for developing the ohmic contacts on the N-type material of both the NPN and PNP type profiles. In the NPN type profile it is the emitter and collector which gets the N-ohmic contact and in the PNP profile it is the base which gets the N-ohmic contact. The process is by an electron beam evaporation of a gold-germanium composite. The gold-germanium contacts just deposited are then heated and selectively cooled to provide the annealing of the contact layers as represented by the step of box 78. Next, an implant isolation process is performed as represented by the step of box 80 in order to further define certain transistor areas of the NPN and PNP profiles. The implant isolation step 80 generally involves implanting boron at selective energy levels in order to damage the GaAs of the profiles and thus separate certain transistor areas. This implant isolation reduces the size of the transistors in order to reduce the capacitance and increase the speed of the transistors. A second silicon nitride layer is then deposited by an appropriate evaporation method as depicted by the step of box 82. This silicon nitride layer is a passivation layer for insulating the layers below it. An etching process is then performed in order to open selective holes in the second silicon nitride layer just deposited in order to make contact with a thin film resistor layer which is later deposited as depicted by the step of box 86. The thin film resistor layer is formed by an appropriate resist and sputtering process to form desirable resistive contacts with the transistor circuits being developed depending on the application in which they are to be used. A contact layer is next deposited in the holes formed by the step of box 86 by a vapor deposition process as represented by the interconnect step of box 88. This provides contact between the resistor layer and the desirable contacts of the transistors. Next, a third silicon nitride insulating layer is deposited on top of the contact layer of step 88 as depicted by the step of box 90 such that the thin film resistor laid down in the step of box 88 is sandwiched between two insulating layers, one by the silicon nitride deposition layer of the step of box 82 and the other by the silicon deposition layer of the step of box 90, to form the desirable circuitry. The third silicon nitride layer is also a passivation layer to protect the underlying circuit. Next, holes are opened through the third silicon nitride insulating layer as represented by the step of box 92, in a masking and etching process well known to those skilled in the art, in order to make appropriate contact to a top metal contact layer which is formed to the top of the circuit as depicted by the step of box 94. Once the steps above are performed on the PNP and NPN profiles developed in FIG. 1, a workable complementary heterojunction bipolar transistor combination circuit has been developed for a specific application. The process described above produces a complementary heterojunction bipolar transistors having exceptionally good performance for both DC and microwave performance. FIG. 4 exhibits common current-voltage (I-V) emitter characteristics for typical heterojunction bipolar transistor devices having an emitter area of approximately 30 µm 2 developed by the above process. More particularly, the I-V curves of FIG. 4(A) is of the NPN type heterojunction bipolar transistors and the I-V curves of FIG. 4(B) is of the PNP type heterojunction bipolar transistors. As is apparent, both of these devices exhibit good DC characteristics having good bulk and contact resistances. The NPN curves have 25 µA step sizes starting with a 10 µA base current. The PNP curves have 75 µA step sizes, starting with a -10 µA base current. In addition, the common emitter gains for this example were typically 50-60 for the NPN HBT and 6-10 for the PNP HBT. Now turning to FIG. 5, S-parameter (scattering parameter) measurements are depicted as a graph of frequency versus gain from 1-26 GHz. More particularly, the maximum stable gain (MSG) and maximum available gain (MAG) are shown as a function of frequency for the complementary HBT devices. This frequency response is for complementary NPN and PNP devices having a 30 µm 2 emitter area. Both the DC and microwave results match closely to those obtained from the devices produced using conventional molecular beam epitaxy on separate wafers, thus indicating that the additional growth and process steps required to fabricate these devices did not adversely affect the performance of the devices. The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. Other applications include the integration of high electron mobility transistors (HEMT) and HBTs, lasers and HBTs, etc. on the same wafer.

Claims: A method of producing complementary bipolar transistors on a common substrate (12) in side-by-side relationship, said method comprising the steps of: fabricating NPN and PNP layered structures (14,22) adjacent to each other on the substrate (12), the NPN and PNP layered structures each including at least an emitter region, a base region, and a collector region; developing emitter mesas and base mesas on each NPN and PNP layered structure; simultaneously evaporating P-ohmic contacts on the base regions of the NPN layered structures and the emitter and collector regions of the PNP layered structures; simultaneously evaporating N-ohmic contacts on the emitter and collector regions of the NPN layered structures and base regions of the PNP layered structures; characterised in that the P-ohmic and N-ohmic contacts are annealed, and the PNP and NPN layered structures are fabricated by the steps of: depositing one of either an NPN or PNP layered structure (14) on the substrate by the molecular beam epitaxy process; depositing a silicon nitride layer (16) on the NPN or PNP layered structure; etching away the NPN or PNP layered structure and silicon nitride layer at a selected area on the substrate; heating the substrate to a predetermined temperature in order to densify the remaining silicon nitride layer; depositing the opposite PNP or NPN layered structure (22) not deposited in the step of depositing one of either an NPN or PNP layered structure on the remaining silicon nitride layer and the selectively etched area of the substrate by the molecular beam epitaxy process; and etching away the remaining silicon nitride layer and the opposite NPN or PNP layered structure which was deposited on the remaining silicon nitride layer to form adjacent NPN and PNP layered structures on the substrate. The method according to claim 1 further comprising the steps of depositing a resist (18) on the silicon nitride layer (16) prior to the silicon nitride layer (16) being selectively etched and selectively developing the resist (18) into desirable geometric patterns by irradiating a masking layer(20) to form a desirable NPN or PNP layered structure pattern. The method according to claim 1 further comprising the step of depositing a resist layer (24) on the opposite deposited NPN or PNP layered structure prior to etching the remaining silicon nitride layer and selectively developing the resist into desirable geometric patterns by irradiating a masking layer (26) to form a desirable NPN or PNP layered structure pattern. The method according to claim 1 wherein the steps of depositing the NPN layered structure and the PNP layered structure by the molecular beam epitaxy steps includes depositing heterojunction bipolar transistor layered structures. The method according to claim 1 wherein the step of etching away the first deposited NPN or PNP layered structure and silicon nitride layer further includes the step of etching the substrate at the selected area to prepare a clean surface for the step of depositing the opposite NPN or PNP layered structure. The method according to claim 1,2 or 3 wherein the step of evaporating P-ohmic contacts and N∼ohmic contacts includes evaporating gold-beryllium contacts by means of electron beam evaporation. The method according to claim 1 in which a further dielectric layer of silicon nitride is deposited over the NPN and PNP layered structures after the step of evaporating the ohmic contacts, but prior to the step of annealing the ohmic contacts. The method according to claim 1 further comprising the steps of depositing subsequent layers including further silicon nitride layers, a thin film resistance layer and associated contact layers to provide the desirable configuration of transistor devices and associated electrical components to form the circuit. The method according to claim 1 wherein the step of heating the substrate includes heating the substrate to approximately 350°C in a vacuum chamber. The method according to claim 4 wherein the steps of depositing the NPN and PNP layered structures includes depositing GaAs/AlGaAs heterojunction layered structures. The method according to claim 4 wherein the steps of depositing the NPN and PNP layered structures includes depositing InGaAs/InA1As/InP heterojunction layered structures.

Inventors: OKI AARON KENJI, STREIT DWIGHT CHRISTOPHER, UMEMOTO DONALD K, VELEBIR JAMES RUSSELL JR, OKI, AARON KENJI, STREIT, DWIGHT CHRISTOPHER, UMEMOTO, DONALD K., VELEBIR, JAMES RUSSELL, JR.
Applicants: TRW INC, TRW INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27