A drive circuit for a display apparatus

Abstract: A drive circuit for a display apparatus having a display section including a pixel, a switching element connected to the pixel and a scanning electrode connected to the switching element, and a pixel electrode and a counter electrode being provided on the opposite sides of the pixel, includes a circuit for applying a first oscillating voltage to the counter electrode, and for applying a second oscillating voltage having the same phase and the same amplitude as the first oscillating voltage to the scanning electrode during a period when the switching element is to be in off-state.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a drive circuit for a display apparatus, and more particularly to a drive circuit for driving a display section comprising a plurality of parallel signal electrodes and a plurality of parallel scanning electrodes crossing each other, pixel electrodes disposed near the respective crossings of the signal electrodes and the scanning electrodes, and a counter electrode facing the pixel electrodes. In this specification, a matrix type liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatus such as an electroluminescence (EL) display apparatus and a plasma display apparatus. 2. Description of the Prior Art: A conventional matrix type liquid crystal display apparatus is schematically shown in Figure 7 , which comprises a TFT liquid crystal panel 100 using thin film transistors (TFTs) 104 as switching elements for driving pixel electrodes 103 arranged in a matrix. The TFT liquid crystal panel 100 also comprises a plurality of scanning electrodes 101 disposed in parallel to one another, and a plurality of signal electrodes 102 disposed in parallel to one another so as to cross the scanning electrodes 101 . The TFTs 104 for driving the pixel electrodes 103 are disposed near the respective crossings of the scanning electrodes 101 and the signal electrodes 102 . A counter electrode 105 is disposed facing the pixel electrodes 103 . In Figure 7 , the counter electrode 105 is schematically shown, but it is generally a conductive layer formed as a common counter electrode for all of the pixel electrodes. An oscillating voltage is applied to the counter electrode 105 so as to reduce amplitudes of signal voltages applied to the signal electrodes 102 . Hereinafter, the oscillating voltage applied to the counter electrode 105 is referred to as a counter voltage. The TFT liquid crystal panel 100 is driven by a drive circuit including a source driver 2 and a gate driver 3 , which are connected to the signal electrodes 102 and the scanning electrodes 101 , respectively. The source driver 2 samples analog image signals or analog video signals input thereto, holds the sampled signals, and then applies them to the signal electrodes 102 . The gate driver 3 sequentially applies scanning pulses as drive signals to the scanning electrodes 101 . Control signals such as timing signals are applied to the source driver 2 and the gate driver 3 by a control circuit 4 . Figure 6 shows waveforms of scanning pulses supplied to the scanning electrodes 101 in a conventional matrix type liquid crystal display apparatus. Figure 3 shows a relationship between a scanning pulse applied to the scanning electrodes 101 and the counter voltage in a conventional drive circuit. As shown in Figure 3 , the scanning pulse takes a high-level value and a low-level value periodically. A period when the scanning pulse takes the high-level value is referred to as a "gate on period". A period when the scanning pulse takes the low-level value is referred to as a "gate off period". The counter voltage is applied to the counter electrode 105 during the gate on period and the gate off period. Generally, the low-level value of the scanning pulse is lowered so as to ensure that the TFT 104 is completely in off-state during the gate off period. However, when the low-level value of the scanning pulse is excessively lowered, the TFT 104 can not be completely in off-state. As a result, it is difficult to secure the complete off-state of the TFT 104 during the gate off period. Referring to Figures 4 and 5 , the above problem will be described in detail. While the counter voltage is applied to the counter electrode 105 , a voltage applied to a drain D of the TFT 104 varies by Δ V x in the following expression: Δ V x = ±V c / (1 + C GD / C LC ) wherein ± V c represents the counter voltage which has an oscillating component, C GD represents a stray capacitance between a gate G and the drain D of the TFT 104 , C LC represents a capacitance between the pixel electrode 103 and the counter electrode 105 . Figure 5 shows a relationship between a voltage V g applied to the gate and a drain current I D . As shown in Figure 5 , an optimal voltage to be applied to the gate to secure a complete off-state of the TFT 104 varies between voltages V L and V H . This makes it difficult to set the low-level value of the scanning pulse to the optimal voltage during the gate off period. As a result, since the complete off-state of the TFT 104 cannot be secured, a deterioration of the liquid crystal elements occurs, and a reliability of the display apparatus is lowered. EP-A-0 079 496 discloses a drive circuit and driving method for a display apparatus according to the preamble of claim 1 and claim 5 respectively. The objective of the present invention is to provide a drive circuit for a display apparatus which ensures that pixel electrodes of the display apparatus are completely put into the non-driving state when the pixel electrodes are not driven (i.e. during the gate off period) and the non-driving state is sustained for a long period, thereby preventing a deterioration of the display apparatus. SUMMARY OF THE INVENTION In one aspect, this invention provides the drive circuit defined by claim 1. Claim 3 defines a display apparatus including this drive circuit. The subclaims 2 and 4 are directed to embodiments of the invention. In another aspect, this invention provides the method of driving a display apparatus defined by claim 5. The invention makes possible attainment of the objective of providing a drive circuit for a display apparatus which ensures that pixel electrodes of the display apparatus are practically put into the non-driving state when the pixel electrodes are not driven (i.e. during the gate off period), thereby preventing a deterioration of the display apparatus and improving the reliability thereof. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram showing an embodiment of a drive circuit according to the present invention; Figures 2a, 2b and 2c show signal waveforms for the embodiment of Figure 1 ; Figures 2d shows a relationship between a scanning pulse and a counter voltage. Figure 3 shows a relationship between a scanning pulse and a counter voltage in a conventional drive circuit; Figure 4 is an equivalent circuit diagram of a portion around a pixel electrode of a display apparatus; Figure 5 is a graph showing a relationship between a voltage applied to a gate of a TFT and a drain current in a conventional display apparatus; Figure 6 shows scanning pulses applied to scanning electrodes; and Figure 7 shows a configuration of a conventional liquid crystal display apparatus. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 shows a configuration of a portion around a gate driver 3 of a drive circuit as one embodiment according to the present invention. The configuration of this embodiment other than the portion shown in Figure 1 can be the same as that shown in Figure 7 . As shown in Figure 1 , a voltage output from a counter voltage generating circuit 8 is not only used as a counter voltage similarly in the conventional drive circuit, but also used as a voltage input to an electric source circuit 9 . The electric source circuit 9 supplies a plurality of operational voltages to the gate driver 3 . The counter voltage generating circuit 8 includes an amplifier 84 . A reverse input terminal of the amplifier 84 receives line reverse pulses from a control circuit 4 through a resistance 81 , while a non-reverse input terminal thereof is connected to a source for supplying a variable direct-current (DC). The counter voltage ±V c which oscillates with a desired amplitude can be obtained by setting the values of the resistance 81 and a resistance 82 appropriately. The electric source circuit 9 includes a sequential circuit composed of a resistance 91 , three Zener diodes 93a to 93c , and a resistance 92 . One end of the sequential circuit on the side of the resistance 91 is connected to a source for supplying a high-level gate voltage V GH . The other end of the sequential circuit on the side of the resistance 92 is connected to a source for supplying a low-level gate voltage V GL . An output terminal of the amplifier 84 is connected to a node of the Zener diodes 93b and 93c . The electric source circuit 9 further includes another sequential circuit composed of three capacitors 95a to 95c which are connected in parallel to the Zener diodes 93a to 93c . More specifically, one end of the capacitor 95a is connected to a node of the resistance 91 and the Zener diode 93a . A node of the capacitors 95a and 95b is connected to a node of the Zener diodes 93a and 93b , a node of the capacitors 95b and 95c is connected to a node of the Zener diodes 93b and 93c , and the other end of the capacitor 95c is connected to a node of the Zener diode 93c and the resistance 92 . It is supposed that the Zener voltages of the Zener diodes 93a , 93b and 93c are V Z1 , V Z2 and V Z3 , respectively. In the above-described configuration, three types of voltage pulses V DD , V CC and V EE ( V DD > V CC > V EE ) are output from the electric source circuit 9 to the gate driver 3 . The voltage pulse V CC is only used for the logical control of the gate driver 3 and not applied to the scanning electrode 101 . Figures 2a and 2c show waveforms of the voltage pulses V DD and V EE , respectively. Figure 2b shows a waveform of a counter voltage V COM for driving the counter electrode 101 . The voltage pulse V DD and the voltage pulse V EE are pulse signals which oscillate with the same phase and the same amplitude as the counter voltage V COM . In Figures 2a , 2b and 2c , V Z1 +V Z2 represents a potential difference between the voltage pulse V DD and the counter voltage V COM . V Z3 represents a potential difference between the voltage pulse V EE and the counter voltage V COM . Scanning clock pulses and scanning start pulses as control signals are supplied to the gate driver 3 from the control circuit 4 through photocouplers 501 and 502 , respectively. The gate driver 3 applies the voltage pulse V DD or V EE as a scanning pulse to the scanning electrode 101 at the same timing as in a conventional gate driver. More specifically, the voltage pulse V DD is selected during a period when the TFT 104 connected to the scanning electrode 101 is to be in on-state (i.e. the gate on period), and applied to the scanning electrode 101 . On the other hand, the voltage pulse V EE is selected during a period when the TFT 104 is to be in off-state (i.e. the gate off period), and applied to the scanning electrode 101 . Figure 2d shows a waveform of a scanning pulse generated by the voltage pulse V DD and the voltage pulse V EE being selectively applied in the above-mentioned manner. The scanning pulse may be generated by selectively superposing the voltages V EE and V DD upon a scanning pulse given in the conventional drive circuit. As shown in Figure 2d , the scanning pulse (shown by the solid line) during the off period has the same phase and the same amplitude as that of the counter voltage (shown by the dotted line). Since a potential difference V gd between the scanning pulse and the counter voltage is kept constant during the gate off period, the potential variation ± V c /(1+ C GD / C LC ) at the drain caused by the counter voltage given in the conventional drive circuit is stabilized. As a result, the optimal voltage applied to the gate of the TFT 104 is determined from the potential difference V gd . Thus, it is possible to apply the optimal voltage so as to secure the complete off-state of the TFT 104 . The potential difference V gd can be set to an arbitrary value by changing the Zener voltage V Z3 . The above configuration of the present invention can also be applied to a drive circuit for a display apparatus provided with auxiliary capacitances formed near the pixel electrodes and a display apparatus for an office automation system. The invention may be embodied in other specific forms and manners without departure from the scope thereof as defined by the claims.

Claims: A drive circuit for a display apparatus having a display section (100) including a pixel, a switching element (104) associated with said pixel and a scanning electrode (101) connected to said switching element through a gate electrode of the switching element, and wherein a pixel electrode (103) and a counter electrode (105) are provided on opposite sides of said pixel, said drive circuit comprising: first means (8,9:93a,93b,95a,95b) for applying a first oscillating voltage (V COM ) to said counter electrode during a period when said switching element (104) is set to be in an off-state in between successive periods when said switching element is set to be in an on-state; characterized by: second means (8,9:93c,95c) for applying a second oscillating voltage (V EE ) having the same phase and the same amplitude as said first oscillating voltage (V COM ) to said scanning electrode (101) during said period when said switching element (104) is set to be in said off-state. A drive circuit for a display apparatus according to claim 1, wherein said second means selectively applies said second oscillating voltage (V EE ) having the same phase and the same amplitude as said first oscillating voltage (V COM ) and a third oscillating voltage (V DD ) having the same phase as said first oscillating voltage (V COM ) to said scanning electrode (101), depending on whether said switching element (104) is set to be in said off-state or in said on-state. A display apparatus comprising a display section (100) including a pixel, a switching element (104) associated with said pixel and a scanning electrode (101) connected to said switching element through a gate electrode of the switching element, and wherein a pixel electrode (103) and a counter electrode (105) are provided on opposite sides of said pixel, and further comprising a drive circuit (3), as defined by claim 1 or claim 2, for driving said display section (100). A display apparatus according to claim 3, wherein said switching element is a thin film transistor (104). A method of driving a display apparatus having a display section (100) including a pixel, a switching element (104) associated with said pixel and a scanning electrode (101) connected to said switching element through a gate electrode of the switching element, and wherein a pixel electrode (103) and a counter electrode (105) are provided on opposite sides of said pixel, said method comprising: applying a first oscillating voltage (V COM ) to said counter electrode (105) during a period when said switching element (104) is to be set in an off-state in between successive periods when said switching element is to be set in an on-state; characterized by: applying a second oscillating voltage (V EE ) having the same phase and the same amplitude as said first oscillating voltage (V COM ) to said scanning electrode (101) during said period when said switching element is set to be in said off-state.

Inventors: IEMOTO TAKAAKI, KUMADA KOJI, OHNISHI TAKASHI, YAKUSHIGAWA HIDEKI, IEMOTO, TAKAAKI, KUMADA, KOJI, OHNISHI, TAKASHI, YAKUSHIGAWA, HIDEKI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: G09G3
IPC codes: G09G3, G02F1