Voltage regulator for memory devices

Abstract: A voltage regulator for electrically programmable, non-volatile memory devices, having an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit means (MW,MB) and comprising at least first (R1) and second (R2) resistive elements connected between first and second terminals of a voltage supply. The regulator further comprises at least a second circuit means (MWd,MBd) being the homolog of the selection circuit means for programming the memory element, said second circuit means being connected serially to the resistive elements (R1,R2) across the two terminals of the voltage supply. Also provided is at least one controlled current generator (G1,G2) connected between one of the two voltage supply terminals and a linking node to one of the resistive elements and an operational amplifier (A) whose non-inverting (+) input is connected to a linking node to at least one of the resistive elements and whose output terminal is the output terminal of the regulator.

Description: This invention relates to monolithically integrated voltage regulators, and particularly to a voltage regulator for use in electrically programmable, non-volatile memory integrated circuits implemented in CMOS technology. A non-volatile memory cell consists of a MOS transistor wherein the gate electrode which overlies the channel region is a floating electrode (i.e. one having a high DC impedance toward all the other nodes of the cell and the external circuit in which the cell is connected). The cell further includes a second gate electrode, referred to as the control gate, which is driven by appropriate control voltages. The other electrodes of the transistor are standard drain, source, and body electrodes. By the use of suitable techniques, the amount of charge present on the floating gate can be varied, and with it can be varied the threshold voltage as "seen" from the control gate (commonly referred to as the threshold voltage of the transistor for simplicity). This enables the transistor to enter either of two logic states, one at a "high" threshold voltage and one at a "low" threshold voltage. When the control gate is applied an intermediate voltage to the two threshold voltages, it becomes possible to "read out" the transistor state, because of the transistor either having a low or a high impedance across its drain and source electrodes contingent on the value of its threshold voltage. The transistor can be viewed, therefore, as a memory-type of logic element. Since the floating gate has a very high impedance toward any other node, its charged state can be retained over a fairly long time period, thereby the cell will exhibit "non-volatile memory" features; the logic state of the cell is, in fact, maintained for an indefinite time even if the power supply to the circuit in which it is connected is cut off. The operation whereby charge is stored in the floating gate is defined "programming", and the operation whereby the charge present in the floating gate is removed therefrom is called "clearing". Reference will be made for simplicity to the instance of a cell comprising an n-channel transistor; the charge that can be stored in the floating gate is composed of electrons; the cell threshold voltage is brought to a high by the programming operation. The problem underlying this invention relates to the cell programming operation. To carry out this operation, both the drain electrode and the control gate of the cell must be brought to adequate levels of positive voltage while holding the source electrode at the negative supply voltage, VSS, which can be assumed to be the same as ground voltage, and to which the body electrode can also be assumed to be connected. This induces a positive voltage in the floating gate. By virtue of the voltage levels applied to its electrodes, the cell transistor is driven to work in the saturation range and traversed by a high current. This situation results, where suitable voltage levels are applied, in electrons passing through the silicon oxide that separates the channel region from the floating gate; the flow of electrons is directed to the latter, which then becomes charged negatively. The threshold voltage of the transistor changes during the programming operation, and accordingly, the intensity of the current flowing through it becomes variable over time. Where, with the transistor control gate being applied the required positive voltage for the programming operation, and no positive voltage being applied to its drain electrode, no current is flowed through the cell, and therefore, the latter is not programmed. Oftentimes, the cell programming is carried out by means of a set of short programming pulses rather than of a single pulse of longer duration ("pulsive programming"). An electrically programmable non-volatile memory circuit usually includes a very large number of cells. The cells are organized into rows and columns (bit lines). Cells in one bit line have the drain electrodes in common. Each cell is identified univocally by activating a row line. At system level, there are two voltages which are supplied to the memory device from an external source, namely: a supply voltage VDD and a programming voltage VPP. Typical ratings for these voltages are 5 V and 12 V, respectively (such values being referred to VSS). Applicational specifications usually provide for a smaller percent variation tolerance for VPP than VDD. In order to program a given cell, the row line and bit line which identify it must be brought to suitable positive voltage levels, as disclosed in the IEEE Journal of Solid-State Circuits, vol. 23, No. 5, October 1988, pages 1157-1163, Kynett et al.: "An In-System Reprogrammable 32Kx8 CMOS Flash Memory" which reflects the preamble of claim 1, and in the US Patent No. 5,086,238. The bit line is usually brought to the proper level by activating two selection transistors MW and MB which are operatively connected in series with each other and to the memory cell. It is only when the selected cell is to be programmed that the two transistors are turned on simultaneously to enable the selected bit line to be brought to a high voltage. The two transistors may be complemetary types, e.g. n-channel for MB and p-channel for MW. Activation of the bit line is accomplished using two signals Se1W and Se1B which are applied to the gate terminals of both transistors MW and MB; MW will be on with Se1W at a logic low, and MB will be on with Se1B at a logic high. (It is obviously necessary that the voltage values attained by the signals at the two logic levels be appropriate.) The programming of a memory cell is markedly affected by the voltage applied to the drain, that is by the voltage VBL present on its respective bit line. A low voltage value would result in inefficient and slow programming of the cell, whereas too high a value would bring about a phenomenon known as soft-erasing which consists of the cell becoming partly cleared. The optimum range for VBL is a fairly narrow one (typically within about 5 V to 6 V). Thus, a highly accurate voltage regulator is required to provide the right voltage for the bit line during the programming step. As previously mentioned, during this step the cells being programmed draw a large amount of current, which is to be supplied through the regulator. In order to speed up the programming operation, the regulator ought to provide a very rapid response to a demand for current from the memory cells, especially where the programming is performed using the pulsive technique. It matters to observe, however, that the requisite accuracy and ability to supply high currents with short response times may still be insufficient to invariably ensure optimum performance under any programming conditions. In fact, owing to the bit line being selected through two transistors, where the value of the current iBL drawn by the bit line is a relatively high one (on the order of a few mAmps), the resistances of the selection transistors in the on state occasion a voltage drop vBL that causes the voltage vBL on the bit line to differ significantly from the output voltage VREG from the regulator; and this results in the system performance in terms of cell programmability deteriorating. Depicted in Figure 1 of the drawings is a diagram of the circuit approach proposed in the afore mentioned Kynett article. The required current for programming is supplied to the bit line through a programming voltage line, VPP. Between said programming voltage line and ground there is provided a voltage regulator which comprises a voltage divider formed of three resistors R1, R2, R3 having four transistors M1, M2, M3 and M4 connected in parallel therewith and in series with one another via their source and drain terminals. The gate terminals of the transistors M1, M4 and M3 are respectively connected to a node between resistors R1 and R2, a node between resistors R2 and R3, and the programming voltage line. The voltage present on the bit line is equal to the voltage WREF present on the gate terminal of transistor M2, which is connected in a diode configuration, but for a negative level translation due to a transistor pair M6, M7 being traversed by a current during the programming operation, which transistors constitute -- in the configuration illustrated -- the bit line selection transistor and write selection transistor, respectively. The voltage V1 on the source of the p-channel transistor M4 is set by the resistive divider formed of R1, R2 and R3, and given by: V1 = VPP *[R1 + R3/(R1 + R2 + R3)] The divider is sized to have the voltage rating V1 equal to the required value on the bit line for the programming operation to be performed in an optimum manner under nominal conditions. The actual voltage output from the regulator, WREF, is raised above the value V1 by means of a positive level translation, to be effected by the n-channel transistors M3 and M2. The two transistors M2 and M3 connected in the regulator final stage (which stage comprises the transistors M1 : M4) are matched to transistors M6 and M7, respectively. The dimensions of transistor M1, functioning as a current source, are selected such that the current density through transistors M2 and M3 is the same as the rating one being flowed, as designed, through the two transistors M6 and M7 during the programming step. Thus, the voltage drop across WREF and the bit line will be equal to that present across the series formed of the transistors M2 and M3. Accordingly, if the current flowing through M6 and M7 during the programming step is the same as the design current, then the voltage on the bit line will be the target value V1. However, that technique is not so effective and some drawbacks become noticeable. In fact, the programming current draw by the selected cell may vary between integrated circuits due to unavoidable variations in the manufacturing process. It may also undergo variations with changes in the integrated circuit environmental and applicational conditions. Consequently, it would be quite arbitrary to define the value of the current flowing through the two transistors M6 and M7, and set the value of the current to be flowed through M2 and M3, from the drawing board. In actual practice, the designer can only fix the typical value of the current that should flow through the bit line during the programming step, and based on it, fix the current through transistor M1. However, if the current that actually traverses the bit line during the programming step differs from that flowing through the regulator output stage in accordance with this design option, then the voltage on the bit line will be incorrect. Further, at the designing stage, the threshold voltage of the memory cell tends to become gradually higher, such that the cell current draw will decrease over time. A voltage regulation effected on an estimate of a mean value for the programming current cannot, therefore, yield satisfactory results each time. It is an object of this invention to arrange for the output voltage from the regulator to be such that the voltage present at each time on the bit line during the programming step will actually be the same as the voltage required to implement the programming operation in an optimum manner. This object is achieved by a voltage regulator as indicated being characterized as in the appended claim 1. The features and advantages of a regulator according to the invention can be more clearly understood from the following detailed description of some embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings. In the drawings: Figure 1 is a diagram of a programming circuit incorporating a prior art voltage regulator; Figure 2 is a general diagram, partly in block form, of a voltage regulator according to the invention, to which a programming circuit is linked in its simplest form; Figure 3 shows a simpler, but less accurate, circuit layout for a voltage regulator according to the invention; Figure 4 shows a further circuit layout for the inventive voltage regulator; and Figure 5 illustrates an example of a complete circuit diagram implementing a voltage regulator according to the invention. The voltage regulator circuit arrangement according to the invention, as shown in Figure 2, comprises an operational amplifier (A) being connected in a unitary gain configuration and having a voltage VREF applied to its non-inverting input which is to be duplicated on the output for powering the load. The output voltage VREG from the regulator is ideally equal to VREF. The voltage VREF applied to the non-inverting input of the amplifier is obtained through a divider formed of two resistors R1 and R2, between which resistors there are connected two transistors MWd and MBd respectively matched to the selection transistors MW and MB of the bit line (i.e. having the same characteristics as the latter transistors but for a suitable scaling factor in the ratio W/L of the channel actual width to the channel actual length, as explained hereinafter). The transistors MWd and MBd are not effective to carry out any selection, and would be commonly referred to as dummy transistors in the relevant art. Command signals Se1Wd and Se1Bd are applied to the gate terminals of such transistors which may be typically coincident with the signals Se1W and Se1B, respectively, being applied to the selection transistors MW and MB. The circuit further includes controlled current generators, G1 and G2, which supply a current iS equal to the current iBL which is output from the regulator and drawn by the bit line. These generators may be implemented by current mirror circuits. The voltage VREF is: VREF = VPROG + vd where VPROG = VPP*[(R2+Ron.d)/(R1+R2+Ron.d)], and vd = iSRon,d*R1/(R1+R2+Ron.d) = βiSRon,d Ron,d = Ron,MWd+Ron,MBd being the sum of the resistances in the on state of the transistor pair MWd and MBd. In the above relation, it has also been assumed that β = R1/(R1+R2+Ron.d) By suitable selection of the scaling factor between the transistor pairs MWd, MBd and MW, MB, i.e. if:(W/L)MWd/(W/L)MW=(W/L)MBd/(W/L)MB)=R1/(R1+R2+Ron.d)=β (6)then Ron,d = (1/β)Ron,BL, and therefore, since iS=iBL, it shows that: vd = vBL Thus, the voltage vBL on the bit line will be: vBL = VREG- vBL=VREF-vBL = VPROG+ vd- vBL = VPROG The divider sizing is arranged to have the voltage VPROG equal to the required voltage on the bit line for optimum implementation of the cell programming. Accordingly, the compensation for the voltage drop across the bit line selection transistors will be applied to the value of the current being instantaneously supplied to the load, rather than to the mean current value. The voltage on the bit line will, therefore, be at all times its ideal value (VPROG) regardless of process variations and the resistance of the selection transistors in the on state (provided that a good matching is ensured between them and the dummy transistors). Conveniently, the voltage drop across the dummy transistors should in no case shift the voltage VREF applied to the non-inverting input terminal of the amplifier upwards enough for the latter voltage to depart from the range of values encompassed by the amplifier input dynamic range. The resistance of these transistors in the on state should not be too high, if excessively high time constants are to be avoided, because said resistance is in series with large capacitances. Within the regulator response time limits, the ideal voltage value is held each time constant on the bit line. Understandably, the same results can be obtained by having the dummy transistors MWd and MBd identical with transistors MW and Mb, and the current iS from the generators G1 and G2 made equal to iBL/β. Alternatively, a circuit could be provided wherein the current iS is decreased by a factor from iBL(iS=iBL/ ) and the factor W/L for the dummy transistors is divided through that same factor compared to the provision of relation (6); thus, Ron,d=( ,β)Ron,BL, and relation (7) is still valid. This affords a reduction in the occupied area and the structure power dissipation (especially during the transition phase). The programming of a memory device usually takes place in parallel on all the cells of one word; understandably, only those cells are programmed for which an increase in the value of the threshold voltage is envisaged, because corresponding data to a given logic level, 0 or 1, is to be stored therein according to the agreed correspondance between the logic value and the threshold voltage of the cell. The output current from the regulator should be equal to the combined currents drawn by the cells being actually programmed. In order to provide proper compensation for the voltage drop appearing across the selection transistors of the selected bit lines, the current density through the dummy transistors should be equal to that through the bit line selection transistors. This can be accomplished by connecting in the divider a number of parallel-connected dummy transistor pairs MWd and MBd equal to the number of cells making up a word. During a programming operation, the same number of dummy pairs will be activated as the number of the cells actually to be programmed. This can be readily obtained with conventional techniques, such as by linking the gate electrodes of the dummy transistors in each pair to appropriate command signals. Reference will be made hereinafter to a single dummy transistor pair, it being understood that the discussion covers the provision of plural dummy transistor pairs to be activated to suit the data being programmed in the cells of the selected word. Similar considerations would apply, of course, to multiprogramming techniques as well, whereby several n-bit words are programmed in parallel. The diagram shown in Figure 2 provides ideal matching of the selection transistors to their corresponding dummy transistors connected in the resistive divider, since they are both in the same bias conditions; for the corresponding transistors, the threshold voltages VTH (including, where applicable, the contribution from "body effect") and the overdrive voltages (Vgs-VTH) are, in fact, the same. With this structure, the same current iS should be injected into and picked up from the divider (across the series of the dummy transistors). This requires good matching of the current generators G1 and G2 and increased area for the structure. The provision of two matched generators, of which one is supplying current and the other drawing current, moreover, requires some power to be dissipated; in actual practice, once the current from one generator (e.g., G1) has been obtained, it is mirrored in a structure which fixes the current from the other generator (G2) through a further current mirror circuit. A simpler, albeit less accurate, solution consists of shifting the dummy switches to the low end of the resistive divider, as shown in Figure 3. (The dummy transistors involved are MWd' and MBd', whose gate electrodes are driven by command signals Se1Wd' and Se1Bd', respectively) In this way, it no longer becomes necessary to pick up current from the divider, thereby a single current generator iS will be adequate, with the advantage over the structure shown in Figure 2 of having less area occupied and less power dissipation. This solution, while being qualitatively equivalent to the previous embodiment, involves nonetheless greater design accuracy and some compromising, because the voltages appearing on the source and drain electrodes of transistors MW and MB, and respective dummy transistors, are no longer equal when the transistors are turned on. This can be compensated for to some extent by suitably varying the size (i.e. the value of the ratio W/L) of the dummy transistors from that of their homolog transistors, and using appropriate voltage values for the command signals Se1Wd' and Se1Bd'. Another circuit diagram for implementing the voltage regulator of this invention is shown in Figure 4. The operational amplifier consists here of a gain stage Av having a source-follower stage (transistor MOUT biased by the constant current generator IB) in cascade connection thereto. But for the bias current IB of the output branch, the current iOUT flowing through the transistor MOUT is equal to that being supplied each time to the load and through the bit line selection switches. The current iOUT is mirrored into the generator G1 and passed through the two dummy transistors MWd' and MBd', thereby permitting of the compensation for the voltage drop vBL, which will take place across the bit line selection transistors. Understandably, the contribution from the bias current IB to the current iS being injected into the two dummy transistors originates a contribution to the value of the voltage VREF which is substantially unrelated to the value of the current supplied by the regulator to the load. This contribution should be taken into account in sizing the divider if the value VREF is to be the target value. Figure 5 shows a complete circuit diagram for a regulator implemented in accordance with the last-mentioned inventive technique. The operational amplifier Av comprises here transistors M1 : M5 and MPR1 and a capacitor Cc. The source-follower stage consists of the transistor MOUT connected serially to MPR2 and biased by the current generator provided through transistor M9. The resistive divider is formed of the resistors R1 and R2 and the transistor pair MD and ME, into which the current iS is injected as obtained by means of the current mirror formed of the transistors MPR2 and MIRROR. Transistor MPR1 improves the structure reliability by preventing the appearance, on the source electrodes of transistors M3 and M4, of an excessively high voltage apt to degrade the transistor pair. Transistors MPR2 and MIRROR provide the required current mirror to inject a current into transistors MD and ME which is matched to that supplied to the load. The capacitor CREF is effective to improve the circuit stability frequency-wise. To close with, the advantage of a voltage regulator according to the invention is that it can output a voltage whose value is changed each time to suit the current being supplied to the load to thereby obtain, at a given node of the load itself, a substantially constant voltage regardless of the value of the current actually drawn by it. This regulator is, therefore, adapted to power the bit lines of an electrically programmable non-volatile memory by means of electric impulses which result in a high current being drawn into the memory cells in order to generate those charge carriers therein which enable the logic state of the cell to be changed. It will be appreciated that the embodiments described and illustrated hereinabove may be altered and modified in many ways without departing from the scope of this invention.

Claims: A voltage regulator for electrically programmable non-volatile memory devices having an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit means (MW,MB) and comprising at least first (R1) and second (R2) resistive elements connected between first and second terminals of a voltage supply, at least a second circuit means (MWd,MBd), being the homolog of the selection circuit means for programming the memory element, said second circuit means being connected serially to the resistive elements (R1,R2) between the two terminals of the voltage supply and an output operational amplifier (A) having a non-inverting input terminal (+) connected to a node between the resistive elements, and at least one controlled current generator, characterized in that said controlled current generator (G1,G2) is connected between one of the two voltage supply terminals and the node between the resistive elements and controlled so that the current through the second circuit means is equal to the current through the selection circuit means. A voltage regulator according to Claim 1, characterized in that the second circuit means (MWd,Mbd) is driven sinchronously with the selection circuit means (MW,MB). A voltage regulator according to Claim 1, characterized in that the operational amplifier (A) includes a gain stage (Av) and a source-follower output stage. A voltage regulator according to Claim 3, characterized in that the source-follower output stage comprises a transistor (MOUT) driven by the gain stage (Av) and connected, with a first terminal, to one of the two voltage supply terminals via a constant current generator (IB), said first terminal being the output terminal of the operational amplifier (A). A voltage regulator according to any of the preceding claims, characterized in that the second circuit means, being the homolog of the selection circuit means, comprises at least one transistor having a control terminal which forms an input terminal of the voltage regulator. A voltage regulator according to Claim 5, characterized in that the transistors comprising the regulator are field-effect transistors whose control terminal is the gate terminal.

Inventors: FLOCCHI CARLO, TORELLI GUIDO, FLOCCHI, CARLO, TORELLI, GUIDO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: G11C16
IPC codes: G11C17, H03F3, G11C16