Integrated current-limiter device for power MOS transistors and process for the manufacture of said device

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer (2) superimposed over a semi-conductor substrate (1) of a first type of conductivity, a base region (3, 4, 5, 7, 18) of a second type of conductivity accessible from a base contact and regions of collector (6) and emitter (8) of the first type of conductivity contained in the base region (3, 4, 5, 7, 18) and accessible from respective collector and emitter contacts (11, 13). The base region (3, 4, 5, 7, 18) comprises at least one highly-doped deep-body region (3) which contains almost completely said emitter region (8), a lightly-doped body region (5) which contains the collector region (6) and an intermediately-doped region (7) which co-operates with the first deep-body region (3) to completely contain the emitter region (8) and a surface area (9) of the base region (3, 4, 5, 7) that is included between the regions of collector (6) and emitter (8). There is also at least one first portion (10) of a layer of polysilicon superimposed and self-aligned with the surface area (9) between the regions of collector (6) and emitter (8) and electrically connected to the collector contact (11) of the bipolar transistor.

Description: The present invention relates to an integrated current-limiter device for power MOS transistors and a process for the manufacture of said device. A current limiter for an MOS power transistor can be accomplished through the use of an MOS current-sensing transistor connected in parallel with the power transistor and in series with a sensing resistance. The voltage produced across this resistance drives the base of a bipolar control transistor so as to cause its firing, and thus the limiting of the gate voltage of the sensing and power transistors, when the voltage across the resistance and thus the current flowing through the sensing and power transistors exceeds a pre-set threshold. A known monolithic integrated embodiment of that current limiter provides for the formation of MOS transistors of the vertical type with the drain coincident with a semi-conductor substrate of a first type of conductivity with a superimposed epitaxial layer of the same type of conductivity, but less highly doped, and of a bipolar transistor of the lateral type in a surface area of said epitaxial layer. More precisely, inside said epitaxial layer there is a base region of the second type of conductivity, inside which there are highly-doped regions of emitter and collector of the first type of conductivity. This integrated embodiment of the current limiter has the drawback that with the lateral bipolar transistor there is associated a vertical bipolar parasite transistor with base regions and emitter coincident with those of the lateral bipolar transistor and a collector region coincident with the substrate and thus with the drains of the MOS transistors. The maximum operating voltage of the device is thus determined by the breakdown voltage of the vertical bipolar parasite transistor, rather than by the breakdown voltage of the power MOS transistor. DE-A-3821065 discloses a current limiting bipolar transistor comprising a base region extending to the top surface of the epitaxial layer between the emitter and collector. The object of the present invention is to provide an integrated current-limiter device of said type and a corresponding process of its manufacture, wherein the effects of the vertical bipolar parasite transistor are reduced to a minimum while the conduction of the lateral bipolar transistor is fostered in the presence of a base bias. According to the invention such object is attained with an integrated current-limiter device as defined in claim 1. According to the invention there is also provided for a process of the manufacture of said current-limiter device, which includes the sucession of steps of claim 6. There is thus obtained a lateral bipolar control transistor for a current-limiter device for an MOS power transistor, wherein the emitter region is completely enclosed by the deep-body region and by the intermediately-doped region; it is thus possible to reduce to a minimum the gain of the associated vertical bipolar parasite transistor. Such gain is further reduced thanks to the alignment between the intermediately-doped region and the first portion of the layer of polysilicon, whose connection to the collector contact determines the reversal of the conductivity of the body region in the proximity of the collector region and thus fosters the conduction of the lateral bipolar transistor, conduction that takes place only in the presence of a direct bias of the base-emitter junction. The reduction of the gain corresponds to the increase in the breakdown voltage of the vertical bipolar parasite transistor, and thus the maximum voltage at which the device can operate is no longer limited by this parasite component, but by the breakdown voltage of the power MOS transistor. These and other features of the present invention shall be made more clear by the following detailed description of its embodiments illustrated, as a non-limiting example, in the enclosed drawings, wherein: Fig. 1 shows a first integrated structure for a bipolar control transistor for a current-limiter device for a power MOS transistor; Fig.s 2-7 indicate different steps for the manufacture of the bipolar control transistor of Fig. 1; Fig. 8 shows a second integrated structure for a bipolar control transistor. With reference to Fig. 1, a first integrated structure for a bipolar control transistor for a current-limiter device for a power MOS transistor comprises a semi-conductor substrate 1 of the type N+ over which there is superimposed an epitaxial layer 2 of the type N-. Inside the epitaxial layer 2 there is a base region, that is formed by a first and a second deep-body region 3, 4 of the type P + , a body region 5 of the type P - that contains a collector region 6 of the type N + , and an intermediately-doped region 7 between the deep-body regions 3, 4 and the body region 5. Such intermediately-doped region 7, together with the first deep-body region 3, completely contains an emitter region 8 of the type N + . Between the emitter region 8 and that of the collector 6 there is defined a surface area 9, that lies below, with the interposition of gate oxide (not shown), a first portion 10 of a layer of polysilicon, that is connected to the collector contact C connected to the collector region 6. Over the deep-body region 3, again with the interposition of gate oxide, there is superimposed a second portion 16 of said layer of polysilicon, that is connected to an emitter contact E connected to the emitter region 8. There are also base contacts B connected to the deep-body regions 3, 4. Due to its embodiment in the form of an integrated device, the bipolar control transistor is associated with a vertical bipolar parasite transistor with base and emitter coincident with those of the control transistor and collector coincident with the substrate 1. The fact of enclosing the emitter region 8 inside the unit formed by the deep-body region 3 and by the intermediately-doped region 7 allows the gain of the associated vertical bipolar parasite transistor to be reduced to a minimum. On the contrary, the presence of the first portion 10 of the layer of polysilicon, whose connection to the collector contact C determines the reversal of the polarity of the surface area 9, fosters the conduction (and thus the gain) of the lateral bipolar transistor should a base bias be present. The presence of the second portion 16 of the layer of polysilicon, connected to the emitter contact E, contributes to avoiding the reversal of the polarity in the absence of base bias and increases the strength of the device. The deep-body region 4 has the functions of a channel stop and can in turn be used as base contact. Fig s from 2 to 7 illustrate successive steps of a process for the manufacture of the integrated structure of Fig. 1. With reference to Fig. 2, the process provides for the formation of field oxide 14 on an epitaxial layer 2 of the type N - grown on a substrate 1 of the type N + . It then provides for the definition and the implantation of a first and of a second deep-body region 3, 4 of the type P + followed by the definition of active areas of the substrate by means of the selective removal of the field oxide, by the growth of a thin layer of gate oxide 23 and by the deposition and doping of a layer of polysilicon. This is then followed by the definition of a first portion 10 of this layer between the deep-body regions 3, 4, and of a second portion 16 of the same layer of polysilicon on the deep-body region 3. With reference to Fig. 3, the process then provides for the implantation of body regions 5, 18 with B + ions, self-aligned with the portions 10 and 16 of the layer of polysilicon. With reference to Fig. 4, the process also provides for the definition, by means of an appropriate resist 30, and the implantation of an intermediately-doped region 7 of the type P, which is self-aligned with the portion 10 of the layer of polysilicon and is between the deep-body region 3 and the body region 5. With reference to Fig. 5, the process continues with the diffusion of the body regions 5 and 18 and of the region 7. Due to the higher doping, the region 7 diffuses to a greater depth with respect to the region 18 and thus the latter, for reasons of intelligibility, is no longer indicated in Fig.s 5, 6, 7, and in Fig.s 1 and 8. With reference to Fig. 6, the process then provides for the definition, by means of resist 31, and the implantation of regions of collector 6 and of emitter 8 of the type N + . The collector region 6 is contained inside the body region 5, the emitter region 8 is contained in the deep-body region 3 and in the intermediately-doped region 7. With reference to Fig. 7, the process comes to an end with the deposition of oxide 20 and the creation of base contacts 12, 13 for the deep-body regions 3, 4, of emitter contacts 11 for the emitter region 8 and of collector contacts 15 for the collector region 6. Contact areas for the portions 10 and 16 of the layer of polysilicon are not shown in Fig. 7, but are in any case defined in order to allow the connection to the contact areas 15 and 11, respectively. The operation of the lateral bipolar transistor and that of the device as a whole are not jeopardized by the absence of the second portion 16 of the layer of polysilicon. A second structure alternative to that of Fig. 1 is represented in Fig. 8. It differs from that of Fig. 1 due to the fact that the second portion 16 of the layer of polysilicon is not defined, and the deep-body regions 3 and 4 are self-aligned with the portion 10 of the layer of polysilicon, according to the process described in EP-A-0481153. In this way the effects of the bipolar parasite transistor are further reduced. It is also possible to provide for the definition of active areas of the device by means of LOGOS-type processes, according to techniques known to the practitioners of the art, without, on the other hand, going outside the scope of the invention as defined in the following claims.

Claims: Integrated current-limiter device with bipolar control transistor for power MOS transistors, comprising: a semiconductor substrate (1) of a first type of conductivity; an epitaxial layer (2) of said first type of conductivity, arranged on said substrate (1) and having a top surface; a base region (3, 4, 5, 7) of a second type of conductivity, contained in said epitaxial layer (2); a collector region (6) and an emitter region (8), both of the first type of conductivity, contained in said base region (3, 4, 5, 7) and extending to the top surface; and base (B), collector (C) and emitter (E) contacts electrically connected to said base (3, 4, 5, 7), collector (6) and emitter (8) regions respectively; said base region (3, 4, 5, 7) comprising a lightly-doped base region (5), an intermediately-doped base region (7) and a highly-doped base region (3), wherein said highly-doped base region is laterally separated from said lightly-doped base region by said intermediately-doped base region; said lightly-doped region (5) containing said collector region (6); wherein said intermediately-doped region (7) and said highly-doped region (3) contact with each other to surround said emitter region (8); such that said emitter region is contained in said intermediately-doped base region and said highly-doped base region; said collector and emitter regions (6, 8) are laterally spaced from each other by a portion of said lightly-doped base region extending to the top surface and by a portion of said intermediately-doped base region extending to the top surface between said emitter region and said lightly-doped base region to define a top surface area (9) between said collector and emitter regions; and wherein a polysilicon layer (10) on gate oxide electrically connected to the collector contact (C) is provided above said top surface area and capacitively coupled through the gate oxide to said top surface area (9) between the collector and emitter regions (6, 8). Integrated device according to claim 1, characterized in that said base region (3, 4, 5, 7) comprises a further highly-doped base region (4) arranged at one side of the lightly-doped region (5) opposite to said top surface area (9) to act as a channel stop. Integrated device according to claim 1, characterized in that said base region (3, 4, 5, 7) comprises first and second highly-doped base regions (3, 4) contained within said intermediately-doped region (7) and said lightly-doped region (5), respectively, and aligned with said polysilicon layer (10). Integrated device according to claim 1, characterized in that said emitter and collector regions (8, 6) are aligned with said polysilicon layer (10). Integrated device according to claim 1, characterized in that a further polysilicon layer (16) electrically connected to the emitter contact (E) is provided above and capacitively coupled through a gate oxide to said highly-doped region (3) at one side thereof opposite to said top surface area (9). Process of manufacturing a current-limiter device according to claim 1 comprising the following succession of steps: growing a lightly-doped epitaxial layer (2) of a first type of conductivity on a highly-doped substrate (1) of said first type of conductivity; forming field oxide (14) on said epitaxial layer (2); implanting a highly-doped base region (3) of a second type of conductivity in the epitaxial layer (2); defining active areas of the epitaxial layer (2) by selective removal of the field oxide (14); growing a gate oxide (23); depositing and doping a polysilicon layer; defining a portion (10) of said polysilicon layer at one side of said highly-doped base region (3); implanting a lightly-doped base region (5) of said second type of conductivity, laterally spaced from said highly-doped base region (3) at said one side thereof, and implanting an intermediately-doped base region (7) of said second type of conductivity between said highly-doped base region (3) and said lightly-doped base region (5) self-aligned with said portion of said polysilicon layer, and diffusing the base regions; implanting highly-doped collector (6) and emitter (8) regions of the first type of conductivity inside said lightly-doped base region (5) and inside said highly-doped and intermediately-doped regions (3, 7), respectively, said collector and emitter regions having facing sides aligned with respective sides of said portion (10) of said polysilicon layer; providing base, emitter and collector contacts (12, 11, 15) for said highly-doped base region (3), said emitter region (8) and said collector region (6), respectively; and providing electrical connection between said portion (10) of said polysilicon layer and said collector contact (15). Process according to claim 6, characterized in that a further highly-doped base region (4) of a second type of conductivity is implanted in the epitaxial layer (2) simultaneously with and laterally spaced from said highly-doped base region (3). Process according to claim 6, characterized in that a further portion (16) of polysilicon layer is defined above said highly-doped base region (3) and aligned with the opposite side of said emitter region (8) simultaneously with the said portion (10) of said polysilicon layer.

Inventors: ZAMBRANO RAFFAELE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1992
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21