PHASE-SENSITIVE RECTIFIER

Abstract: A phase-sensitive rectifier (PSR) system uses phase reversal modulation (PRM) to remove the effects of offsets. A switching circuit (51) is controlled by the reference and PRM signals in combination, to perform a first demodulation of an input signal. The switching circuit (51) is connected to a current source (52) in parallel with a capacitor (C1). The capacitor (C1) is connected, via resistor (R1), to a switching circuit (53), which is controlled by the PRM signal to perform a second demodulation. This switching circuit is connected to a capacitor (C2), which is connected in turn to a difference circuit means (54).

Description: PHASE-SENSITIVE RECTIFIER The present invention relates to phase-sensitive rectifiers (PSRs) , also known as phase-sensitive detectors. There are many situations, e.g. in electrical, electronic, and other physical experimentation, where a desired signal of known frequency (which can be termed the carrier frequency) is accompanied by noise such as signals of other frequencies. Detector circuitry is required which will detect and amplify the desired signal while being unresponsive to the accompanying noise. One well-known detector for detecting such a signal is a phase-sensitive rectifier (PSR) . This gives an output whose DC-like component is proportional to the amplitude of the desired signal input (an input voltage of known frequency and phase) , even when the desired signal input is accompanied by additive noise at other frequencies. This additive noise input gives rise to additive noise at the output, but this output noise can be attenuated to any required extent by low pass filtering. The basic PSR detects a desired signal which is cf known phase as well as known frequency, and thus varies only in amplitude. The PSR, which is inherently a type of demodulator, has two inputs and one output. One of the inputs (the analog input) is an analog voltage, consisting of the signal to be rectified (the desired signal) accompanied by additive noise. The other input: (th_= ef rence input) is a square wave of fixed amplitude with frequency and phase exactly equal cc the frequency and phase of the signal to be detected. The output consists of the rectified signal, multiplied by a gain factor GO which is dependent on the design of the PSR, and accompanied by additive noise. The simplest type of PSR contains just two switches connected to amplifiers of gain +1 and -1 (the effect of which is equivalent to multiplication of the signal by +1 and -1 alternately) and a low pass filter. In practice, the switches generally feed, via a resistor, the summing junction of an operational amplifier with a feedback resistor and capacitor. The output noise consists of the input noise components shifted by the carrier (reference) frequency and its harmonics, and attenuated by any first-order filtering which may be incorporated in the PSR. The time constant of any such filtering is called the time constant of the PSR. The output of the PSR will often be connected to an analog-to-digital converter (ADC) , either directly or via an additional low-pass filter. In many practical situations the input signal to noise ratio is much less than 1; i.e. the magnitude of the input signal is much less than the required full-scale rectified output. A high gain is therefore required between the input and the final (analog) output. This high gain can of course be split between the inherent gain GO of the PSR and subsequent amplifying stages. The circuitry used for processing the kind of signals we are concerned with normally uses operational amplifiers (op amps) as its active components. Design techniques for such circuicry are well established, and generally permit accurate control of the circuit parameters such as gains. This is achieved primarily by the use of feedback using passive components (resistors) , the values of which can readily be controlled accurately; the feedback can be arranged to compensate for variations in the gain of an operational amplifier. However,- the effects of the DC offset and offset temperature coefficient of an operational amplifier are more difficult to compensate for, as these cannot easily be counteracted by the use of feedback. A development of the basic PSR has been described by Princeton Applied Research Corporation in their Instruction Manual for the Synchro-Het™ Lock-In Amplifier, Model 186, 1973 (ref MDL 186; 5/74-A) , which explains: "... finding a method of differentiating detector output due to signal from that caused by spurious responses is a very worthwhile objective. It turns out that, if the phase of the reference drive to the synchronous detector is shifted 180°, the polarity of the dc output caused by the signal will reverse. The polarity of the spurious dc output, however, will remain unchanged. Consequently, if the detector output is measured at 0°, and measured again at 180°, the observed change in dc level indicates the signal amplitude.... This method of eliminating the effects of detector non-linearity and output drift is the basis for the synchronous heterodyning technique. ... the input from the experiment is amplified and passed through an 11 Hz phase reversing modulator, which is essentially a reversing switch being thrown between its inverting and non-inverting positions at an 11 Hz rate. The chopped input is applied to a standard phase sensitive detector operating at the reference frequency in exactly the same manner as it would in a conventional lock-in anrolifier. The detector output is passed through an attenuator and applied to a unique 'rotating capacitor' filter synchronized with the 11 Hz chopping rate. ... The output of the filter is ... amplified and ac coupled to a demodulator synchronized to the 11 Hz chopping rate The output demodulator is another reversing switch synchronized to the 11 Hz phase chopper operating on the input The Rotating Capacitor Filter is basically a xl operational amplifier having a capacitor connected between its output and summing junction with provision for reversing the capacitor direction in step with the 11 Hz signal " This system can be briefly summarized as applying phase reversal modulation in conjunction with a rotating capacitor to a PSR. This system has however proved to be unsatisfactory for various applications. A major problem is the way in which the system responds to noise signals at "beat" frequencies of the reference frequency plus or minus the PRM (phase reversal modulation) frequency of 11 Hz or some multiple thereof. Also, the amplifier driving the rotating capacitor is repeatedly driven into saturation, which is liable to produce non-linearity. The general object of the present invention is to provide an improved PSR system in which the effects of DC offsets and thermal voltages are kept small by the use of phase reversal modulation (PRM) and which achieves a substantial improvement as compared with the earlier system discussed above. Accordingly the present invention provides a phase sensitive rectifier (PSR) system employing phase reversal modulation (PRM) characterized by the combination of: means for generating a switching signal (the reference signal) at a reference frequency; means for generating a PRM control signal; means for combining the reference signal with the PRM control signal; means for using the combined signal to perform a first demodulation of the input signal; and second demodulating means including current source means; switching means for performing demodulation switching at the PRM frequency, a first capacitor connected to the current source means and connected via resistor means to the switching means, a second capacitor connected across the switching means, and difference circuit means connected to the second capacitor. A PSR system embodying the invention, and modifications thereof, will now be described, by way of example, with reference to the drawings, in which: Figs. 1A and 13 together are a block circuit diagram of a PSR system (in which capacitor C2 is shown twice fcr convenience) ; Fig. 2 shows the control waveforms occurring in that circuit; Fig. 3 is a block circuit diagram of a modification of a part of that circuit; Fig. 4 is a stylized block diagram of the Model 186 Lock-In Amplifier; and Fig. 5 is a similarly stylized block diagram of the present circuit. The circuitry shown in Fig. 1 is divided broadly into analog circuitry in the upper parts and digital circuitry in the lower parts. The analog circuitry consists mainly of operational amplifiers, switches, resistors, and capacitors. Considering first the general organization of the circuitry, amplifiers Al and A2 produce the input signal I/P in direct and inverted form; switches SI and S2 perform a first demodulation switching, feeding (via resistor RO) a summing junction at the input to amplifier A3, the feedback path of which acts as a current controlled current source (CCCS) ; and switches S3-S6 perform a second demodulation switching. An output is taken from across capacitor C2 by amplifiers A4-A6 forming a difference circuit. This is connected to a filter 12 which in turn is connected to an anaiog-to-digital converter 13 the sampling of which is timed by the PRM timing. Considering the circuitry now in more detail, all the unmarked resistors are connected in standard configurations around the operational amplifiers, and for the purpose of understanding the circuit operation can all be assumed to have the same value, say 10 kilo-ohms. The factors άetεrminincr the values of the other components are discussed below. The switches (SI to S6) are fast semiconductor switches, the state of each being determined by the signal applied to it from the logical circuitry in the lower part cf the circuit (l (high) = closed, 0 (low) = open) . The input signal I/P, which includes the desired signal (of known frequency and phase) is fed to the two amplifiers Al and A2, Al being non-inverting and A2 being inverting. The two switches SI and S2 are driven by a switching signal produced by an Exclusive-OR gate 24. This switching signal is the logical combination (Exclusive-OR) of a logical reference signal REF (which may for example be obtained from a reference signal source 20) and a phase reversal modulation control signal PRM. Switch SI is driven by the switching signal Dl from gate 24 directly while switch S2 is driven by this signal via an inverter 25 (signal D2) . The reference signal REF is fed to a divider 21 which is connected to a one-shot 22 which produces enable pulses A/D EN for the analog-to-digital converter 13. These enable pulses are also fed to a divide-by-2 circuit 23, which produces a square wave phase reversal modulation control signal, indicated as PRM. For simplicity, the operation of the circuit will be discussed on the assumption that the input signal is a reference-frequency sinusoid of constant amplitude. Within any given half cycle of the PRM control signal, switches SI and S2 perform reference frequency demodulation switching. For each cycle of the desired signal, switch SI passes the first half-cycle in direct form and switch S2 passes the second half-cycle in inverted form, so achieving demodulation at the junction of their outputs. Noise signals (i.e. signals at other frequencies) will be modulated to various AC frequencies, which are filtered out, primarily by capacitor C2 (filter circuit 12 performing further filtering) . Considering now the effect of the PRM control signal; this reverses the polarity of the reference frequency demodulated signal with each change of the PRM control signal. This results in a signal at the PRM frequency and its harmonics appearing at the outputs of the switches SI and S2. The signals from the switches SI and S2 are summed by a resistor RO, which is connected to amplifier A3, which has a feedback resistor R2, in parallel with a feedback capacitor CI as shown. The upper ends of resistor R2 and capacitor CI thus form a virtual earth (ground) . A second demodulation is performed by switches S3 to S6, which are arranged in a reversing configuration to connect the output of the primary PSR demodulator across a capacitor C2 alternately one way and the other. These switches are driven by the PRM control signal, switches S4 and S5 directly and switches S3 and S6 via an inverter 26. The desired signal thus appears across C2. This capacitor performs the main filtering out of any AC components (e.g. those resulting from modulation of AC noise with the reference frequency) . A signal output is taken from across C2 by a difference circuit comprising three operational amplifiers A4 to A6 and four resistors. The resulting desired signal is fed to the low pass filter 12, further reducing any AC components. The filter 12 is connected to the analog-to-digital converter 13, which samples the filter output in response to the A/D EN pulses, the frequency of which is twice the PRM frequency. As noted above, the purpose of the present PSR system is to keep the effects of DC offsets and thermal voltages small. Any DC offsets from amplifiers Al to A3 are connected alternately to one end and the other of C2 in any PRM cycle, and so contribute no total charge to C2. This action constitutes an error correction mechanism. More specifically, any DC offset produced by amplifier A3 is applied to one side of C2 in the first half of each PRM cycle and to the other side in the second half, giving cancellation. Any DC offsets produced by amplifiers Al and A2 are applied to one side of C2 in one half of each REF cycle and to the other side in the other half of the REF cycle (within a PRM half-cycle) , also giving cancellation; although the association between the REF half-cycle (first cr second) and the side of C2 is reversed on each PRM half-cycle, this does not affect the cancellation. The bias currents of amplifiers A4 and A5, and the offset voltages of these two amplifiers and of amplifier A6, give rise to errors which are not corrected by the error correction mechanism. The circuit should therefore be designed so that the bias current is small enough and the gain preceding these amplifiers is large enough for these uncorrected errors to be small compared to the desired signal. The effect of any DC offsets and thermal voltages in subsequent amplifying stages will then be small. For correct operation, the values cf the components (apart from the amplifiers) must be ' suitably chosen, and these values determine the gain GO. The value of capacitor CI is chosen to be much less than that of C2, but sufficiently large to ensure that its charge remains substantially constant during the change-over of switches S3 to S6 in spite of feed- hrough via switch gate capacitance and other unwanted capacitive effects. At each change-over in the state of switches S3 to S6 there is a stepwise change in the voltage across Rl equal to twice the voltage across C2, followed by an exponential decay as charge is shared between C2 and CI. The time constant of this decay is approximately the product of Rl and CI, and the value of Rl is chosen to make this time constant much shorter than the system time constant while being long enough to prevent the operational amplifiers from going into slew-rate limit. The effective resistance Reff across C2 is approximately the parallel combination of R2 with a notional resistance which is the reciprocal of the product of CI and the PRM frequency, and which represents the effect of the charge-sharing between C2 and CI. The time constant of the system is approximately the product of C2 with Reff, and the DC gain GO is approximately the ratio of Reff and RO. The PRM frequency is exactly half the sample frequency of the ADC. Successive pairs of ADC samples must be averaged to eliminate the effect of imbalances between successive PRM half-cvcles. Block 14 is shown as p erforming such averaging, though it will be realized that this will normally be done by software rather than hardware, block 14 being shown in phantom to indicate this. If a true averaging analog-to-digital converter is used (for instance one based on a sigma-delta modulator) , it is sufficient to use an averaging interval equal to an integral number of PRM cycles; in this case, the functions of both the blocks 13 and 14 would be performed by the converter. This PSR system allows a value of GO typically equal to 1000 to be implemented. The application of phase reversal modulation (PRM) converts the effects of DC offset and offset temperature coefficient to an AC output voltage at the PRM frequency and its odd harmonics, and the effects of unwanted DC voltages can be completely eliminated. The gain GO is applied only to the required DC-like signal output and not to the DC offsets of the components nor to the thermal voltages that may exist because of temperature gradients. In some cases, for instance where amplifier slew-rate limitations present problems, it is preferable not to connect C2 in the feedback path of an operational amplifier but to drive it from a grounded voltage-controlled current source (VCCS) . In its simplest form this consists of two complementary current mirrors and two resistors, but various other forms have been described in the literature. The required circuit configuration, with a generalized VCCS, is obtained by replacing the portion of circuit shown in the block III in Fig. l by the portion shown in Figure 3. Fig. 5 is a more stylized block diagram of the present circuit, and can be compared with Fig. 4, which is taken from the Model 186 Lock-In Amplifier manual mentioned above. The Model 186 Lock-In Amplifier has a pre-amplifier stage 30' the output: of which is PRM " modulated by a PRM modulator 31' , with the output of that modulator being detected Jphase sensitive rectified) by a PSR demodulator 32'; there is actually an isolator between these two units. The present system has a first demodulation switching circuit 51 (amplifiers Al and A2 and switches SI and S2) , which is controlled by the REF and PRM control signals in combination. The Model 186 Lock-In Amplifier has a rotating filter capacitor Crot fed via a resistor Rx from the PSR demodulator 32'. This is connected to an amplifier 33' which is AC coupled via a coupling capacitor Cc to a PRM demodulator 35', which in turn is connected to a low pass filter 37' . The signal between resistor Rx and amplifier 33' is an AC signal; the capacitor Crot acts as an n-path (in this case, 2-path) filter tuned to the reference frequency to select this signal by virtue of its polarity being reversed in synchronism with the phase reversals of the signal. In the present system, the switching circuit 51 is connected to a current source 52 (the feedback path of amplifier A3 of Fig. 1 or the voltage controlled current source of Fig. 3) . This is connected, via resistor Rl, to a further switching circuit 53 (switches S3 to S6) , which is controlled by the PRM control signal to perform a second demodulation. This switching circuit 23 is connected to the capacitor C2, which is connected to a di ference circuit means 54 (amplifiers A4 to A6) . Capacitor C2 effects the major smoothing of the signal to a DC-like form. " 5 The crux of the distinction between the Model 186 circuit and the present PRM system can be seen by considering the manner in which the rotating capacitor Crot of the Model 186 circuit behaves, in comparison with the capacitor C2 of the present system. In the Model 186 circuit, the desired signal is generated as an AC signal, and the rotating capacitor Crot acts as a filter for this AC signal, which is subsequently amplified and demodulated. In the present system, the capacitor C2 acts not as a filter but as part of the PRM demodulator, which has high gain for the desired signal but low gain for offsets. Although the voltages appearing at the two ends of capacitor C2 are both square waves, they are in phase. The difference circuit means 54 is insensitive to these square waves (at the PRM frequency) , and its output is just the difference between them, which is the desired DC-like signal. Figure 1 shows the simplest type of primary demodulator, containing just two switches connected to amplifiers of gain +1 and -l and to one resistor. In some applications it is preferable to use a more complicated switching arrangement (for instance to implement Walsh functions) with several switches controlled by waveforms derived from the reference waveform by appropriate logic operations and/or phase shifts, and several resistors. The principle illustrated in Figure 1 applies equally to these more complex systems, all switching waveforms being reversed in phase by the PRM waveform. Although in the preceding description it has been assumed that the required system output is digital, under suitable conditions the circuit described here can give outstandingly good results in situations where a purely analog output is required. The PRM frequency has been described above as a submultiple of the PSR reference frequency; that is, the PSR frequency is a true (integral) multiple of the PRM frequency. This arrangement will often be the most convenient. However, the PRM frequency can instead be a true multiple of the PSR frequency if the PSR frequency is low enough. In fact, the two frequencies need not be locked together at all, though suitable averaging or filtering will then be required to minimize the resulting pseudo-random noise at the output. The best relationship will depend on circumstances, e.g. the PSR frequency (which may not be readily controllable) and its variability. The reference signal generator 20 will in practice be coupled to the experimental apparatus which is producing the input signal I/P, to ensure that frequencies of the reference signal and the desired signal are locked together.

Claims: CLAIMS l. A phase sensitive rectifier (PSR) system employing phase reversal modulation (PRM) characterized by the combination of: means (20) for generating a switching signal (the reference signal) at a reference frequency; means (20 to 23) for generating a PRM control signal; means (24) for combining the reference signal with the PRM control signal; means (51; 25, Al, A2, SI, S2) for using the combined signal to perform a first demodulation of the input signal; and second demodulating means including current source means (52; the feedback path of A3 or VCCS) ; switching means (53; S3 to S6) for performing demodulation switching at the PRM frequency, a first capacitor (CI) connected to the current source means (52; the feedback path of A3 or VCCS) and connected via resistor means (Rl) to the switching means (53; S3 to S6) , a second capacitor (C2) connected across the switching means (53; S3 to S6) , and difference circuit means (54; A4 to A6) connected to the second capacitor (C2) . 2. A PSR system according to claim 1 characterized in that the first demodulation means comprises a set of switches (SI, S2) driven by a logical combination of the reference and PRM signals. 3. A PSR system according to either of claims 1 and 2, characterized in that the current source means comprises the feedback path of an operational amplifier (A3) . 4. A PSR system according to either of claims 1 and 2 characterized in that the current source comprises a voltage controlled current source (Fig. 3) . 5. A PSR system according to any previous claim characterized by an analog-to-digital converter (13) at the output of the difference circuit means (36; A4 to A5) or at the output of a low pass filter connected to said difference circuit means. 6. A PSR system according to claim 5 characterized in that the analog-to-digital converter is a sigma- elta converter. 7. A PSR system according to claim 6 characterized in that the analog-to-digital converter is an averaging converter having an averaging period equal to a multiple of the PRM period. S. A PSR system according to claim 6 characterized in that the analog-to-digital converter is sampled at the PRM signal reversal rate. 9. A PSR system according to any previous claim characterized in that the first demodulation means implements a Walsh function. 10. Any novel and inventive feature or combination of features specifically disclosed herein within the meaning of Article 4H of the International Convention (Paris Convention) . 11. A PSR system according to claim 1 and substantially as hereinbefore described with reference to any one or more of Figures 1 to 3 of the accompanying drawings.

Inventors: FAULKNER ERIC ANDREW, FAULKNER, ERIC, ANDREW
Applicants: ALTEC RESEARCH LTD, ALTEC RESEARCH LIMITED
Application year: 1992
Main classification: G01R25
IPC codes: H03D1, H03D3