Image processing apparatus

Abstract: An image processing apparatus including: an input unit for inputting image data; a smoothing process unit for smoothing image data of a subject pixel, in accordance with the image data of the subject pixel and peripheral pixels of the subject pixel, respectively inputted from the input means; a judgment unit for judging the level of the image data of the subject pixel and the peripheral pixels; and an output control unit for selectively outputting one of the image data smoothed by the smoothing process unit and the image data of the subject pixel inputted from the input unit, in accordance with a judgment result of the judgment unit. Also provided is an image processing method having the steps of: inputting image data; smoothing image data of a subject pixel, in accordance with the image data of the subject pixel and peripheral pixels of the subject pixel, respectively inputted at the input step; judging the level of the image data of the subject pixel and the peripheral pixels; and selectively outputting one of the smoothed image data smoothed at the smoothing step and the image data of the subject pixel inputted at the input step, in accordance with a judgment result at the judgment step.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an image processing apparatus capable of eliminating noises contained in image signals. Related Background Art An image processing apparatus has been used which processes image data read by a line sensor made of charge coupled devices (CCDs) or contact sensor (CS) and prints out it from a printer. Multi-value signals of an image read by a line sensor are converted into density signals which are then binarized by a pseudo half-tone process using an error distribution method, a dither method, or another method, and printed out from a printer. Such a conventional apparatus uses a density-luminance conversion table which is not linear as shown in Fig. 2. Therefore, for example, a change in luminance level by one step at a low luminance level corresponds to M steps of the density level. If noises are contained in a luminance signal read by a line sensor, the noises are emphasized at a low luminance level, i. e., at a high density level. Even if one step of the luminance level may produce a conspicuous white or black line on an output image. Smoothing filters, median filters and the like are known as the means for eliminating such noises. However, use of these filters eliminates noises on one hand, and lowers the resolution of an image on the other hand. An image processing apparatus comprising a smoothing filter is for example described in EP-A-0216536 or EP-A-0 415 648. It is a concern of the present invention to eliminate the disadvantages of conventional technique and provide an image processing apparatus capable of eliminating random noises contained in image signals. It is another concern of the present invention to provide an image processing apparatus capable of effectively eliminating noises by filtering signals only at an image area greatly affected by noises, without lowering an image resolution. An embodiment of the present invention to provide an image processing apparatus capable of eliminating noises contained in image signals and improving an image resolution by performing an edge emphasis process of an area where a noise eliminating process is not applied. In accordance with a first aspect of the present invention there is provided image processing apparatus as set out in claim 1. In accordance with a second aspect of the invention there is provided a method of image processing as set out in claim 6. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the structure of an image processing apparatus according to a first embodiment of the present invention; Fig. 2 is a graph showing the relation between density and luminance used for luminance-density conversion of an image read by a line sensor; Fig. 3 is a block diagram showing the structure of a smoothing circuit of the first embodiment; Fig. 4 is a block diagram showing the structure of a luminance judgment circuit of the first embodiment; Fig. 5 is a graph showing an example of luminance data to be processed by the first embodiment apparatus; Fig. 6 is a graph showing density data obtained through luminance-density conversion of luminance data shown in Fig. 5 without processing it; Fig. 7 is a graph showing density data obtained through luminance-density conversion of luminance data shown in Fig. 5 subject to a filtering process of the embodiment; Fig. 8 is a block diagram showing the details of a binarization circuit; Fig. 9 is a block diagram showing an image processing apparatus according to a second embodiment; Fig. 10 is a block diagram explaining the details of a delay circuit 3000 shown in Fig. 9; Fig. 11A is a diagram explaining the positions of pixels to be processed; Fig. 11B is a diagram explaining an edge emphasis process; Fig. 11C is a diagram explaining a smoothing process; Fig. 11D is a diagram explaining luminance level judgment; and Fig. 12 is a block diagram explaining the details of a smoothing circuit and an edge emphasis circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Fig. 1 is a block diagram showing an image processing apparatus according to the first embodiment of the present invention. A contact sensor (CS) 100 photoelectrically converts an intensity signal of light reflected from an original into electrical signals, and outputs luminance data having six bits per pixel (64 tonal levels). Latches 201 to 204 constructed of D-type flip-flops receive the luminance data synchronously with pixel clocks, and output luminance data of four pixels in the main scan direction. Representing the luminance data outputted from the latch 202 as a subject pixel, outputted are the luminance data for the subject pixel, and the luminance data for preceding two pixels, and the luminance data for one succeeding pixel. As shown in Fig. 3, a smoothing circuit 300 is constructed of adders 301 to 303 and a divider 304. The smoothing circuit 300 calculates a mean value of the luminance data for the four pixels in the main scan direction outputted from the latches 201 to 204, and outputs it to a selector 500. Namely, the adders 301 to 303 add together the data for the four pixels, and the divider 304 shifts the added data by two bits, i.e., the added data is divided by 4 to obtain a mean value. The luminance judgment circuit 400 shown in Fig. 1 is constructed of comparators 401 to 404 and an AND gate 405 as shown in Fig. 4. If the four luminance data outputted from the latches 201 to 204 are all smaller than a value set to the comparators 401 to 404, a level "1" signal (truth) is outputted. In the other cases, a level "0" signal (falseness) is outputted. A selector 500 shown in Fig. 1 selects a smoothed data from the smoothing circuit if the luminance judgment circuit 400 outputs the level "1" signal, and selects the data (subject pixel data) from the latch 202 if the circuit 400 outputs the level "0" signal. The data selected by the selector 500 is outputted to a binarization circuit 600. Namely, if all the values of the luminance data for the subject pixel and peripheral three pixels are smaller than a predetermined value, the smoothed data is selected. The binarization circuit 600 performs luminance-density conversion shown in Fig. 2 for the data selected by the selector 500, and thereafter performs a pseudo half-tone process such as an error distribution method to output binarized image data. Fig. 8 shows an example of the structure of the binarization circuit shown in Fig. 1. In the binarization circuit 600, a luminance-density conversion unit constructed of a ROM converts the luminance data into density data which is further converted into binarized data. Binarization may use a dither method, averaged error minimizing method, and the like. In this embodiment, an error distribution method is used which binarizes density data by distributing binarization errors to peripheral pixels to obtain a variable magnification image having a good density conservation. The details of the binarization circuit 600 using an error distribution process will be given with reference to Fig. 8. In Fig. 8, 651a to 651d represent D-type flip-flops for latching data, 652a to 652d represent adders, 630 represents a line memory for one line delay, 640 represents a comparator, and 660 represents an error distribution control circuit. In the binarization circuit 600, image data of a multi-value (0 to 63) density outputted from a luminance-density conversion unit 601 is inputted to an adder 652d. The inputted multi-value density data (original image multi-value data corresponding to subject pixel position (i, j)) is added by an adder 652a to the total error distributed to the pixel position, and the added value is outputted via a signal line 650 to the comparator 640 and error distribution control circuit 660. The comparator 640 compares the data on the signal line 650 with a predetermined threshold value TH (e.g., 32 for 6-bit data). If the data on the signal line 650 is larger than the threshold value TH, a level "1" signal (black) is outputted to a signal line 700, and if smaller, a level "0" signal (white) is outputted to the signal line 700. If the output of the comparator 640 is "0" (white), the error distribution control circuit 660 outputs the data on the signal line 650. If the comparator 640 outputs "1" (black), the error distribution control circuit 660 calculates error quantities 656a to 656d distributed to the peripheral pixels using as an error a difference between the data on the signal line 650 and a constant T (63 for 6-bit data). The error quantity signals 656a to 656d are added at the adders 652a to 652d to the error quantities already distributed to the peripheral pixels (i - 1, j + 1), (i, j + 1), (i + 1, j + 1), and (i + 1, j), respectively of the subject pixel (i, j). The four peripheral pixels of the subject pixel are used in this embodiment. The number of pixels is not limited to this, but it may be increased or decreased as desired. Next, the noise eliminating function of the image processing apparatus constructed as above will be described. A low luminance level, where a change in luminance level by one bit is luminance-density converted into M bits change in density level, is greatly influenced by external noises contained in the luminance signal. For example, the luminance signal shown in Fig. 5 is luminance-density converted into the density signal shown in Fig. 6. As shown, noises at a lower luminance level influence the density level more than noises at a higher luminance level. Noises at a higher luminance level are suppressed after luminance-density conversion as shown in Fig. 6. Accordingly, if a noise elimination filter is used only for a lower luminance level, it is possible to sufficiently eliminate external noises. Eliminating noises only at a lower luminance level results in use of a noise eliminating filter only for a small image data distribution area. Therefore, as shown in Fig. 7, the edge portion is not influenced by averaging of noise elimination, and is not degraded. As described above, a combination of a noise elimination filter and a luminance judgment circuit allows noise elimination without deteriorating an image resolution. In the above embodiment, with a noise eliminating filter, a mean value of peripheral four pixels is calculated. In this noise elimination, a mean value of n pixels in the main and sub scan directions may be used. Furthermore, a weighted filter such as a triangle filter may be used considering expected noise frequency components. A median filter for outputting a median value of reference pixel values may also be used in noise elimination. In the above embodiment, a noise eliminating filter operates when all reference pixel levels are lower than a predetermined luminance level, while considering a luminance-density conversion table. Instead, a noise eliminating filter may be used for a desired area in accordance with the characteristics of a conversion table. According to the first embodiment of the present invention, a filter is used only for an image area greatly influenced by noises. Therefore, noises can be effectively eliminated without deteriorating an image resolution. (Second Embodiment) Next, the second embodiment will be described. In addition to the function of the first embodiment, the second embodiment eliminates noises while performing an edge emphasis process for an area not using a noise eliminating filter, to thereby improve an image resolution. Fig. 9 is a block diagram showing the main part of an image processing apparatus according to the second embodiment of the present invention. A contact sensor (CS) 1000 photoelectrically converts an intensity signal (luminance signal) of light reflected from an original into electrical signals. A sensor is not limited only to CS, but a line sensor of CCDs using optical reduction may also be used. An A/D converter 2000 converts an analog signal corrected by a shading correction circuit (not shown) and the like into digital luminance signal of six bits per pixel. A delay circuit 3000 is constructed of two FIFOs for two-line delay and five D-type flip-flops. Image data of two lines is delayed by the FIFOs to obtain image data of three lines at a time. The image data of three lines is inputted to the D-type flip-flops to delay it in the main scan direction. The D-type flip-flops obtain matrix image data A, B, C, D, and X shown in Fig. 11A which is then outputted to an calculation circuit at the following stage. A pixel X is used as a subject pixel to output a corrected value for X. A symbol "*" means "don't care" and is not used for calculation. An edge emphasis process circuit 4000 performs an edge emphasis filter (Laplacian filter) calculation process shown in Fig. 11B for the matrix pixel data A, B, C, D, and X supplied from the delay circuit 3000, and outputs resolution-compensated pixel data to a selector 7000. An edge emphasis filter calculation may use optional Laplacian filter values. A smoothing process circuit 5000 smoothes, as shown in Fig. 11C, the matric pixel data A, B, C, and D outputted from the delay circuit 3000 through calculation of a mean value thereof by using mean value calculating means, and outputs the smoothed pixel data (mean value of A, B, C, and D) to the selector 7000. Instead of the mean value, a median value of A, B, C, and D may be used for a smoothing filter. A luminance level judgment circuit 6000 outputs a level H (truth) signal when all the luminance values of the matrix pixel data A, B, C, D, X shown in Fig. 11D and obtained from the delay circuit 3000 are within a predetermined range, and in the other case outputs a level L (falseness) signal. In this embodiment, if the luminance value is equal to or higher than a present luminance value, a level H signal is outputted. The predetermined range is set as desired. The selector 7000 selects the image data from the smoothing process circuit 5000 when the level H signal is outputted from the luminance level judgment circuit 6000, and selects the image data from the edge emphasis process circuit 4000 when a level L signal is outputted. The image data from the selector 7000 with noises eliminated is converted into density data by LOG conversion described with Fig. 8 of the first embodiment. The density data is subject to a pseudo half-tone process such as an error distribution method, and is printed out from a binary value printer. For a multi-value printer, the density data is subject to area modulation or the like to print it out. Fig. 10 shows the details of the delay circuit 3000. FIFO line buffers 2001 and 2002 delays the image data inputted from the A/D converter in the sub scan direction in units of line. One line is delayed by the FIFO line buffer 2001, and two lines are delayed by the FIFO line buffers 2001 and 2002. D-type flip-flops 2011 to 2018 delays the image data line-delayed by the FIFOs in the main scan direction in units of pixel, to thereby obtain the five matrix pixel data A, B, C, D, and X. Characters at upper right corners of the D-type flip-flops (D-FF) shown in Fig. 10 correspond to the pixel positions shown in Fig. 11A. Fig. 12 shows the details of the edge emphasis process circuit and smoothing circuit. An adder 4001 adds together the luminance signals for the peripheral pixels A, B, C, and D of the subject pixel. An output of the adder is used for both the smoothing process and edge emphasis process. A divider 5001 divides an output of the adder 4001 by 4 to obtain a mean value of the luminance signals. This division can be achieved by simply shifting two bits. A multiplier 4002 multiplies the luminance signal for the subject pixel by 4. This multiplication can be achieved by shifting two bits, similar to the case of the divider 5001. A sign inversion circuit 4003 inverts the sign of an output from the adder 4001 for the later subtraction. An adder 4004 adds together the outputs of the sign inversion circuit 4003 and the multiplier 4002. An output of the adder 4004 is a Laplacian filter value. A comparator 4005 determines whether the Laplacian filter value is within a predetermined range. If so, it supplies a selection signal to a selector 4009 to inhibit addition to the Laplacian value. A multiplier 4006 multiplies the Laplacian value to adjust the gain of the value. An adder 4007 adds the gain adjusted Laplacian value to the subject pixel value X. A limiter 4008 limits the data after addition of the Laplacian value to a minimum or maximum pixel value if the data is beyond the minimum or maximum pixel value. The selector 4009 selects the subject pixel value X if an output of the comparator 4005 indicates that the Laplacian value is within the predetermined range. In the other case, it selects the value after filtering. An output value of the selector 4009 becomes pixel data after the edge emphasis process. A block encircled by a broken line in Fig. 12 is a conventional edge emphasis circuit. In this embodiment, only the divider 5001 is added to provide the smoothing process. The advantageous effects of each block of the image processing apparatus will be described in detail. As shown in Fig. 2, a low luminance level area is gieatly influenced by external noises contained in a luminance signal at the time of LOG conversion (luminance-density conversion), a change in luminance level by one bit resulting in a change in density level by n bits. Therefore, the smoothing filter is used only at the lower luminance level area to eliminate noise effects. On the contrary, noises at a higher luminance level have a tendency to be suppressed after LOG conversion, because of missing bits. It is therefore possible to effectively eliminate noises by performing the smoothing process only for an area having greater noise effects after LOG conversion (i.e., a smaller luminance level area). Furthermore, since noises are eliminated only at the smaller luminance level area, the smoothing filter is used only for the area having a small distribution of image data. The area including edge portions of an image is generally has a large data distribution. Accordingly, the smoothing process is not performed for this area. This can be easily achieved by limiting the luminance level of pixels. As described above, a combination of a smoothing filter and a luminance judgment circuit allows noise elimination without deteriorating an image resolution. In the above embodiment, a mean value of the matrix pixel data A, B, C, and D is calculated using the smoothing filter as shown in Fig. 11C. Therefore, it is possible to simplify the circuit by sharing the addition of A, B, C, and D with the calculation of 4X - (A + B + C + D) by the edge emphasis filter as shown in Fig. 11B. It is therefore unnecessary to add an adder for the smoothing process. The noise eliminating circuit of this embodiment can be realized by adding only the comparator for the luminance level judging circuit 6000 and the selector 7000, to a conventional edge emphasis circuit. In the above embodiment, the edge emphasis calculation and smoothing calculation have been performed using the peripheral pixels at the upper and lower, right and left positions of the subject pixel. An edge emphasis calculation may use peripheral pixels at right, left, upper, and lower positions of the subject pixel, and a smoothing calculation may use a mean value of the subject pixel and right and left peripheral pixels in the main scan direction. Furthermore, although the embodiment uses a 3 x 3 matrix, other types of matrices may also be used. As described so far, according to the second embodiment of the present invention, noise components superposed on a line sensor can be effectively suppressed with a small number of added circuits, while minimizing the deterioration of an image resolution.

Claims: An image processing apparatus comprising: input means (100) for inputting luminance image data represented by pixels; smoothing process means (300) for smoothing the image data of a subject pixel, in accordance with the image data of the subject pixel and of predetermined pixels peripheral to said subject pixel respectively received from said input means; and characterised by judgement means (400) for judging whether or not the level of the luminance data of said subject pixel and said peripheral pixels is within a predetermined range; and output control means (500) for selectively outputting either the image data smoothed by said smoothing process means or the image data of said subject pixel as received from said input means, in accordance with a judgement result of said judgement means, the output control means outputting said smoothed image data when said judgement means judges that the luminance data of said subject pixel and said peripheral pixels is within said predetermined range. Apparatus according to claim 1, further comprising conversion means (601) for converting said luminance data from said output control means into density data. Apparatus according to claim 2, further comprising binarization means (600) for binarizing said density data from said conversion means by an error distribution method. Apparatus according to any preceding claim, wherein said smoothing process means outputs the mean value of the image data of said subject pixel and said peripheral pixels. Apparatus according to any preceding claim, further comprising edge emphasis processing means (4000) for executing an edge emphasis process for the input data of the subject pixel, and wherein said output control means outputs the edge emphasis processed data if said judgement means judges that the luminance data of the subject pixel and its peripheral pixels are not within the predetermined range. An image processing method comprising the steps of: inputting luminance image data in the form of pixels; smoothing image data of a subject pixel received from said inputting step in accordance with said image data of the subject pixel and predetermined pixels peripheral to said subject pixel; judging whether the level of said image data of said subject pixel and said peripheral pixels is within a predetermined range; and selectively outputting the smoothed image data smoothed at said smoothing step when it is judged that the luminance data of said subject pixel and the peripheral pixels is within said range, and otherwise outputs the unsmoothed pixel. A method according to claim 6, further comprising the step of converting said luminance data obtained at said output control step into density data. A method according to claim 7, further comprising binarizing said density data obtained at said conversion step by an error distribution method. A method according to any one of claims 6, 7 or 8, wherein said smoothing process step outputs a mean value of the image data of said subject pixel and said peripheral pixels. A method according to any one of claims 6 to 9, further comprising the step of executing an edge emphasis process for the input data of the subject pixel, and wherein in said output control step the edge emphasis processed data is output if it is judged in said judgement step that the luminance data of the subject pixel and its peripheral pixels are not within the predetermined range.

Inventors: USHIDA KATSUTOSHI, USHIDA, KATSUTOSHI, USHIDA, KATSUTOSHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N1
IPC codes: H04N1