Drive circuit, particularly for power MOS half-bridges

Abstract: A drive circuit (20) comprising a voltage source (21) supplying a reference voltage (V REF ) at its output (35); a voltage elevating circuit (23) connected to the supply (V S ) and to the output (35) of the voltage source, and supplying at its output (42), under normal operating conditions, a drive voltage (V CP ) greater than the supply voltage and increasing with the reference voltage. The input of the voltage source (21) is connected to the output (42) of the voltage elevating circuit (23), and defines a positive feedback resulting in an increase in the reference voltage (V REF ) alongside an increase in the drive voltage (V CP ), and therefore a corresponding increase in the drive voltage (V CP ) up to a maximum permissible value, thus providing for a sufficient drive voltage for driving the gate-source junction of power MOS transistors, even in the presence of a low supply voltage.

Description: The present invention relates to a drive circuit, particularly for power MOS half-bridges. Power MOS half-bridges comprise a pair of power MOS transistors, usually N-channel type, push-pull connected as shown by way of example in Fig.1, which shows a half-bridge 1 comprising two MOS (typically VDMOS-Vertical Double Diffused MOS) transistors M 1 and M 2 . Transistor M 1 (top transistor) presents its drain terminal connected to supply voltage V S , and its source terminal connected to the drain terminal of transistor M 2 (bottom transistor), the source terminal of which is grounded. The gate terminals of transistors M 1 and M 2 are connected respectively to top and bottom drivers T and B in turn connected to a synchronizing input signal IN, for producing drive signals whereby one of transistors M 1 , M 2 is turned off when the other is on. The output of half-bridge 1 thus presents a signal V OUT , the amplitude of which switches between R DSon2 * I (where R DSon2 is the equivalent resistance between the drain and source of transistor M 2 when saturated, and I the output current) and V S - R DSOn1 * I (where R DSON1 is the equivalent resistance between the drain and source of transistor M 1 when saturated). In half-bridge 1, to achieve a low voltage drop in whichever of transistors M 1 , M 2 is on at the time, and therefore a high excursion of output voltage V OUT , the transistor must be driven by a high gate-source voltage (V GS ), typically of about 10V, which provides for optimizing saturation resistance R DSon . Such a high voltage is usually achieved without difficulty as regards transistor M 2 , which permits the use of a reference voltage obtainable from the supply voltage. The situation is more complex, however, in the case of transistor M 1 , which requires a drive voltage of 10V + V OUT , i.e. 10V + V S - R DSon1 * I, which is higher than the supply voltage. A highly effective solution to the problem is to use a charge-pump or voltage doubling circuit, which gives a voltage higher than the supply voltage, and provides for driving one or more half-bridges. A simplified diagram of such a circuit, indicated by 2, is shown in Fig.2. Charge-pump circuit 2 substantially comprises an oscillator 3; two condensers 4 and 5; and two diodes 6 and 7. Oscillator 3 is connected to a reference voltage V REF and ground, so that its output 8 switches continually between V REF and 0V. In the first half-cycle, when output 8 is 0V, condenser 4 charges to V S via diode 6; whereas, in the second half-cycle, when output 8 equals V REF , condenser 4 (whose terminal 9, not connected to oscillator 3, switches to voltage V REF + V S in relation to ground) transfers the charge to condenser 5. In the second half-cycle, diode 6 disconnects condensers 4 and 5 from supply V S , while, in the first half-cycle, in which condenser 4 restores the charge transferred to condenser 5, diode 7 disconnects condenser 5 from condenser 4 and the supply voltage. Under normal operating conditions, if V CP is the output voltage of circuit 2 (drive voltage), and V be the voltage drop in diodes 6 and 7: V CP = V S - 2V be + V REF and, assuming in this particular case that V be = 0.7V and V REF = 10V: V CP = V S - 1.4V + 10V ≈ V S + 9.6V Charge-pump circuit 2 therefore provides a drive voltage ensuring a sufficient voltage drop V GS in transistor M 1 to effectively saturate it. Reference voltage V REF is usually produced using circuit 10 in Fig.3, which presents a minimum voltage difference D V between supply and reference voltages V S and V REF . Circuit 10 comprises a bipolar NPN transistor 11; a resistor 12 connected between the base and collector of transistor 11; and two diodes 13, 14, of which diode 13 is a Zener, connected in series between the base of transistor 11 and ground. The emitter of transistor 11 is connected to supply voltage V S , and the base defines the output of circuit 10. If R, in circuit 10, is the resistance of resistor 12; h fe the current gain for small signals of transistor 11; and I O the emitter current of transistor 11; when, as in this case, V S < V Z + V be (where V Z and V be are the voltage drop in Zener diode 13 and diode 14 respectively): DV = V S - V REF = (R*I O )/h fe + V be which, by appropriate sizing of the components, may be reduced to 1V, so that: V REF = V S - DV = 1V There are some situations, however, in which the Fig.3 circuit is impractical, as in the case of automotive applications, which require that the MOS half-bridge, operating normally with a supply voltage V S of 6V, should also be capable of operating with a minimum supply voltage V Smin of 5.4V, i.e. that the drive circuit of top transistor M 1 supply an output voltage V CP of at least roughly 9.3V. In fact, to achieve a fairly good saturation resistance, VDMOS transistors must be driven in such a manner as to present a voltage drop V GS of at least 4V. This is obtained easily, in the case of transistor M 2 , even with a minimum supply voltage V Smin . The same does not apply, however, to transistor M 1 , which, with a minimum supply voltage V Smin of 5.4V, requires that V OUT ≈ 5.3V and, therefore, V CP ≈ 9.3V. According to (2), however, the Fig.3 circuit provides at most for supplying an output voltage V REF of 4.4V, so that, according to (1), charge-pump circuit 2 provides solely for supplying a voltage V CP of: V CP = 5.4V - 1.4V + 4.4V = 8.4V The source-drain voltage drop of transistor M 1 therefore equals: V GS1 = V CP - V OUT = 3.1V which is well below the required value. Another known solution for generating reference voltage V REF comprises a PNP transistor in place of transistor 11, as shown in Fig.4, where PNP transistor 15 presents an emitter connected to supply voltage V S , and a collector defining the output of the circuit. A resistor 16 is connected parallel to the base-emitter junction of transistor 15; a current source 17 is connected between the base of transistor 15 and ground; and a Zener diode 18 is also connected between the output and ground. The above solution, however, despite providing for a voltage drop DV = V S - V REF equal to the emitter-collector saturation voltage of transistor 15 (and, therefore, below that of the Fig.3 circuit), is not used for the following reasons: a) the maximum output current I OUT required by the load must be supplied at all times by transistor 15, even when not needed (thus resulting in high power consumption and dissipation); b) for a given area, a PNP transistor provides for carrying a much smaller current than an NPN type, and the Zener must be sized to withstand all the current (thus increasing the size of the integrated circuit). It is an object of the present invention to provide a MOS half-bridge drive circuit enabling the half-bridges to operate even with a low supply voltage. According to the present invention, there is provided a MOS half-bridge drive circuit, particularly for power MOS half-bridges, as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Fig.1 shows a simplified diagram of a MOS half-bridge for which the drive circuit according to the present invention is designed; Fig.2 shows a simplified electric diagram of a known charge-pump circuit; Fig.3 shows an electric diagram of a known reference voltage source; Fig.4 shows an electric diagram of a further known reference voltage source; Fig.5 shows a simplified electric diagram of the drive circuit according to the present invention; Fig.6 shows an electric diagram of a variation of a detail in the Fig.5 circuit. No further description of Figs. 1-4, which have already been dealt with in the introduction, will be given herein, and any component parts of the known circuits (in particular, the charge-pump in Fig.2) forming part of the drive circuit according to the present invention will be indicated using the same numbering system. Drive circuit 20 in Fig.5 substantially comprises a linear voltage regulator 21; a firing circuit 22; a charge-pump circuit 23; a comparator stage 24; a load 25; a first group of bottom drivers B; and a second group of top drivers T. Linear voltage regulator 21 (defining a voltage source) comprises an operational amplifier 30, the output 31 of which is connected to the gate terminal of a preferably VDMOS transistor 32, the drain terminal of which is connected to supply line 29 (reference potential line on which voltage V S is present), and the source terminal of which is grounded via two series connected feedback resistors 33, 34. The mid point between the source terminal of transistor 32 and resistor 33 defines output 35 of regulator 21 at which reference voltage V REF is present; while the mid point between feedback resistors 33, 34 is connected to the inverting terminal of operational amplifier 30. The non-inverting terminal of amplifier 30 receives a precise, temperature-stable voltage V bg produced, for example, by a so-called band-gap circuit. Operational amplifier 30 also presents a supply input 36 connected to supply line 29. Regulator 21 also comprises a current mirror circuit 37 comprising two P-channel MOS transistors 38, 39. The gate and drain terminals of transistor 38 are shortcircuited and connected to a current source 40; while the drain terminal of transistor 39 is connected to output 31 of operational amplifier 30. The source terminals of both transistors 38, 39 are connected to output 42 of charge-pump circuit 23 over line 43. Firing circuit 22 comprises a bipolar NPN transistor 44 with its collector connected directly to supply line 29, the base connected to supply line 29 via a resistor 45, and the emitter connected to output 35 of regulator 21 and to input 46 of oscillator 3 of charge-pump circuit 23. As in the Fig.2 circuit, circuit 23 (which forms a voltage elevating circuit) also comprises a condenser 4 having one terminal connected to the output of oscillator 3, and the other terminal connected to the cathode of diode 6, the anode of which is connected to supply line 29. The cathode of diode 6 is also connected to the anode of diode 7, the cathode of which defines output 42 to which drive voltage V CP is supplied. Condenser 5 is located between output 42 and ground. Comparator stage 24 (defining switch means for turning off firing circuit 22) in turn comprises a comparator 48, the non-inverting input of which is connected to output 42 of charge-pump circuit 23, and the inverting input of which receives reference voltage V TR . The output of comparator 48 is connected to the gate terminal of a MOS transistor 49, the source terminal of which is grounded, and the drain terminal of which is connected to the base of transistor 44 of firing circuit 22. Load 25 and bottom drivers B are connected to output 35 of regulator 21, while top drivers T are connected to output 42 of charge-pump circuit 23. Bottom drivers B for driving respective bottom transistors M 2.1 -M 2.N of half-bridges 1.1-1.N, by switching them according to the operating frequency of the half-bridges, receive respective synchronizing input signals IN.1-IN.N, which are also supplied to respective top drivers T for driving top transistors M 1.1 -M 1.N of the same half-bridges 1.1-1.N in the same way as, but in phase opposition to drivers B, and with a higher voltage, as already described. Top and bottom drivers T and B are also grounded, while the respective half-bridges 1.1-1.N present outputs OUT1-OUTN. The Fig.5 drive circuit operates as follows. With a supply voltage V S of 5.4V on line 29, the firing circuit is designed to give a voltage drop V 1 of 1V, so that V REF = 4.4V. In the above condition, oscillator 46 of charge-pump circuit 23 comes into operation, and, on the basis of (1), circuit 23 supplies an operating output voltage of: V CP = V S + V REF - 2V be = 5.4 + 4.4 - 1.4 = 8.4V. The above voltage V CP is supplied to current mirror circuit 37, which therefore drives transistor 32 by bringing its gate terminal up to voltage V CP . Transistor 32 therefore presents a voltage drop V GS (overdrive) of: V GS = 8.4 - 4.4 = 4V. This is sufficient to saturate transistor 32, so that voltage V REF begins to rise, thus resulting, on the basis of (1), in a corresponding increase in voltage V CP , and a further increase in voltage V REF . A positive reaction is thus initiated, which continues until transistor 32 is fully saturated and (assuming a 100 mV drain-source saturation voltage V DSsat of transistor 32) reference voltage V REF reaches the maximum value V REF = 5.4V - 100 mV = 5.3V and V CP = 5.4 + 5.3 - 1.4 = 9.3V. Prior to reaching the normal operating condition, the reduction in the difference between V S and V REF is also accompanied by a reduction in the voltage drop at the base-emitter junction of transistor 44 of firing circuit 22, until transistor 44 eventually goes off. Under normal operating conditions, top and bottom drivers T and B function correctly, by virtue of the gate-source junction being supplied with a voltage V GS of at least 4V. In actual fact, the positive reaction, and therefore operation of the drivers and respective half-bridges, is also initiated at lower supply voltages (V S = 4V), even though the equivalent drain-source saturation resistance is less than optimum. Firing circuit 22 is also turned off by comparator stage 24, especially in the presence of a high supply voltage V S (which may be as high as 60V), and, in particular, when the output voltage V CP of charge-pump circuit 23 is such as to ensure the system is turned on, and prior to output voltage V REF of regulator 21 reaching the normal operating value. In fact, as soon as drive voltage V CP exceeds voltage V TR at the inverting input of comparator 48, the output of comparator 48 switches from low to high, thus turning on transistor 49, and the voltage at the drain terminal of transistor 49 becomes low, thus inversely biasing the base-emitter junction of transistor 44. Consequently, even in the presence of a high supply voltage V S output voltage V REF of regulator 21, on reaching the set value, maintains this value by virtue of being independent of supply voltage V S . A further advantage of actively turning off firing circuit 22 (by connecting the base terminal of transistor 44 to a voltage close to 0 V) is that it enables transistor 44 to withstand breakdown voltage BV CBO . As supply voltage V S increases beyond the value at which transistor 32 is no longer saturated, operational amplifier 30, which, with a low supply voltage V S , is incapable of supplying V REF , provides for supplying a precise, temperature-stable, regulated reference output voltage V REF = V bg (1+R 2 /R 1 ) where R 2 and R 1 are the respective resistances of resistors 33 and 34. By appropriate sizing, it is therefore possible to obtain an optimum voltage V REF of 10 V. The advantages of the Fig.5 circuit will be clear from the foregoing description. In addition to providing for turning on and driving one or more MOS half-bridges, even in the presence of a low supply voltage of 5.4V, the circuit according to the present invention also provides for generating an optimum reference voltage, e.g. of 10 V, as required for driving MOS half-bridges in the best possible manner. The circuit is also straightforward in design, and easily implementable, for example, as an integrated circuit. To those skilled in the art it will be clear that changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention as defined in the appended claims. In particular, should firing circuit 22 be insufficient for supplying the current required, it may be replaced by circuit 22' as shown in Fig.6. In place of one transistor 44, circuit 22' features two transistors: a PNP transistor 53 with its emitter terminal connected to supply line 29, its base terminal connected to one terminal of resistor 45 and to the drain terminal of transistor 49 of comparator stage 24, and its collector terminal connected to the base terminal of a second NPN transistor 54, the collector terminal of which is connected to supply line 29, and the emitter terminal to output 35 of regulator 21. Finally, a current source 55, supplying current I 1 , is provided between the base terminal of transistor 53 and ground. The Fig.6 circuit also presents a voltage drop V 1 = V S - V REF = 1V , but, in comparison with circuit 22, a much higher output current I 2 equal to: I 2 = β 1 β 2 I 1 where β 1 and β 2 are the current gain of transistors 53 and 54 respectively.

Claims: A drive circuit (20) for MOS half-bridges (1), particularly power MOS half-bridges, comprising a first reference potential line (29) set to a first reference potential (V S ); a voltage generating circuit (21) having an input (36) connected to said first reference potential line (29) and an output (35) supplying a second reference potential (V REF ); and a voltage elevating circuit (23) having a first and second (46) input connected respectively to said first reference potential line (29) and said output (35) of said voltage generating circuit (21); said voltage elevating circuit (23) also presenting an output (42) supplying, under normal operating conditions, a drive potential (V CP ) greater than said first reference potential (V S ) and increasing with said second reference potential (V REF ) ; characterized by the fact that said voltage generating circuit (21) presents a further input connected to said output (42) of said voltage elevating circuit (23), and comprises positive feedback means (37, 43) connected to said further input for increasing, in presence of a low first reference potential, said second reference potential (V REF ) to a maximum normal operating value alongside an increase in said drive potential (V CP ). A circuit as claimed in Claim 1, characterized by the fact that said voltage generating circuit (21) comprises a voltage regulator (30-34) having an input connected to said output (42) of said voltage elevating circuit (23) through said positive feedback means. A circuit as claimed in Claim 2, characterized by the fact that said voltage regulator (30-34) comprises output transistor means (32) having a control terminal connected through said positive feedback means to said output (42) of said voltage elevating circuit (23), and an output terminal defining said output (35) of said voltage generating circuit (21). A circuit as claimed in Claim 3, characterized by the fact that said output transistor means comprise a MOS transistor (32) having a gate terminal connected through said feedback means to said output (42) of said voltage elevating circuit (23), a source terminal defining said output terminal (35), and a drain terminal connected to said first reference potential line (29). A circuit as claimed in Claim 3 or 4, characterized by the fact that said voltage regulator (30-34) comprises an operational amplifier (30) having a non-inverting input connected to a third reference potential (V bg ), an inverting input connected to said output terminal (35) of said voltage generating circuit via a resistive feedback circuit (33, 34) also connected to a fourth reference potential line (ground), and an output (31) connected to said control terminal of said output transistor means (32). A circuit as claimed in any one of the foregoing Claims from 2 to 5, characterized by the fact that a current mirror circuit (37) is provided as said positive feedback means between said output (35) of said voltage generating circuit (21) and said output (42) of said voltage elevating circuit (23). A circuit as claimed in any one of the foregoing Claims from 1 to 6, characterized by the fact that it comprises a firing circuit (22; 22') between said first reference potential line (29) and said second input (46) of said voltage elevating circuit (23). A circuit as claimed in Claim 7, characterized by the fact that said firing circuit (22; 22') comprises transistor means (44; 53, 54) having a first terminal connected to said first reference potential line (29), a second control terminal connected to said first reference potential line via resistive means (45), and a third terminal connected to said second input (46) of said voltage elevating circuit (23). A circuit as claimed in Claim 8, characterized by the fact that said transistor means comprise a bipolar transistor (44). A circuit as claimed in Claim 8, characterized by the fact that said transistor means comprise two cascade-connected bipolar transistors (53, 54). A circuit as claimed in any one of the foregoing Claims from 7 to 9, characterized by the fact that it comprises switch means (24) connected to a control terminal of said firing circuit (22; 22'), for turning off said firing circuit prior to said drive circuit (20) reaching the normal operating condition. A circuit as claimed in Claim 11, characterized by the fact that said switch means comprise a comparator stage (24) having a first input connected to said output (42) of said voltage elevating circuit (23), a second input connected to a threshold potential (V TR ), and an output connected to said control terminal of said firing circuit (22; 22'). A circuit as claimed in any one of the foregoing Claims, characterized by the fact that said voltage elevating circuit (23) comprises a charge-pump circuit. A circuit as claimed in Claim 13, characterized by the fact that said charge-pump circuit (23) comprises an oscillator stage (3) having an input (46) connected to said output (35) of said voltage generating circuit (21), and an output connected to a first terminal of a first condenser (4) having a second terminal connected to said first reference potential line (29) via a first diode (6) and to said output (42) of said voltage elevating circuit (23) via a second diode (7); a second condenser (5) being provided between said output (42) of said voltage elevating circuit (23) and a fourth reference potential line (ground).

Inventors: GARIBOLDI ROBERTO, LEONE MARCELLO, GARIBOLDI, ROBERTO, LEONE, MARCELLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H03K17
IPC codes: H03K17, H03F3, H02M1