SELF-ALIGNED THIN FILM TRANSISTORS IN AN ACTIVE MATRIX ARRAY

Abstract: A method of providing a transistor as for use in an array includes using the gate structure as a mask, allowing phosphorus ion implantation of portions of an a-Si:H layer or by providing additional phosphorus-doped silicon portions for ohmic contacts to transistor source and drain. The crossovers of the source and gate connection lines are insulated by a-Si:H/SiNx layers or by insulating with a layer of a polyimide during the processing sequence. Redundancy of both transistor and crossover increase yield in an array.

Description: SELF-ALIGNED THIN FILM TRANSISTORS IN AN ACTIVE MATRIX ARRAY Cross Reference to Related Applications This application is a divisional application of U.S. Serial No. 290,986 titled "Self-Aligned Thin Film Transistors in an Active Matrix Array" by the Applicants filed December 28, 1988. BacKground Qf The Invention This invention relates to the field of thin film transistors and a method of making bottom gate thin film transistors (TFT's) utilizing self-alignment, and particularly to the integration of the TFT's into a large area electronic system such as a liquid crystal array. In the field of actively addressable liquid crystal displays, the pixels which make up the visible display are usually on a transparent plate, with each pixel comprising a capacitor. For each pixel, an adjacent transistor functions as a switch, allowing the capacitor to be charged from a voltage supply as required by the picture or data being displayed. The number of pixels and transistors depends on the desired size or resolution of the display, and may be as large as a million for a 10 inch by 10 inch plate. The requirements for such a display are: no line defects and no more than 1 pixel defect/in 2 , a yield of more than 99.99%. Thin film transistors are commonly used for charging the pixel capacitors, but most known manufacturing processes for TFT's include critical processing and/or critical masking steps. Any critical step causes a reduction in yield in such displays, therefore, the literature records many attempts to eliminate the critical steps. Still, high yield integration has not generally been successful. Another approach is to utilize vertical gate TFT's, and a patent application on several embodiments of this method has been filed by the assignee of the present invention (S.N. 152349, filing date, February 4, 1988). More details of the prior art will be given hereinbelow. Summary Of The Invention It is an object of the present invention to achieve a high yield in the processing of thin film transistors in an actively addressable liquid crystal array. This object and others which will become apparent are achieved in a device and method using a self-aligned, bottom gate thin film transistor with the ohmic contacts for source and drain created by implantation of phosphorus ions into a layer of amorphous silicon or by using microcrystalline, phosphorus doped silicon. By using the gate for masking, the overlap of gate and source/drain is reduced to 1.Oμm or less, parasitic capacitance being reduced accordingly. Crossovers are created by insulating with a-Si:H/SiN x layers or with a layer of a polyimide during the processing sequence. Redundancy is provided by additional transistors and crossovers which can easily replace a defective element. Brief Description Of The Drawing Fig. 1 is a perspective view of a lateral TFT of the prior art. Figs. 2A, 2B are cutaway views of two prior art top gate transistors. Fig. 3 is a cutaway view of a prior art bottom gate transistor. Fig. 4 is a series of cutaway views of the transistor of one embodiment of the present invention, illustrating the processing method. Fig. 5 is a series of cutaway views of the transistor of another embodiment of the present invention, illustrating the processing method. Fig. 6 is a perspective view of one embodiment of a crossover structure. Fig. 7 is a perspective view of the present invention, including transistor and crossover. Fig. 8 is a plan view of the device structure illustrating the redundancy feature. Detailed Description of the Invention The prior art TFT structure seen in Fig. 1 was taken from "Plasma Deposited Films", Chapter 8, edited by J. Mort and F. Jansen, CRC Press, Inc. (1986). The illustration shows a substrate 10 of glass or other suitable transparent material, with a lateral gate transistor, crossover and connection lines on one surface. "Suitable transparent material" in the context of this invention will be understood to mean a material transmitting at least 90% of the radiation used in a specific application, typically visible light. A portion of one pixel element 12 of tin oxide (approx. 1000 A in thickness) may be seen on the surface of the glass. This layer is typically formed by an atmospheric chemical vapor deposition processing at 500° C, using SnCI , 0 2 and F 2 . Standard photolithographical techniques are used to photoshape the pixel element 12, with the unwanted tin oxide etched away, leaving room for transistors and connection lines. Next, the entire substrate 10 is coated with a 1000 A layer 14 of a metal such as nickel chrome, then the NiCr layer is photoshaped and etched to provide gate area 14 and gate connection lines 14A. It should be noted that, while nickel chrome is the preferred material, other metals could be used and other electrically conducting materials such as conducting polymers and metal oxides are possibilities in some applications. The gate connection lines 14A connect to the gates of all transistor gates in a row of transistors (not shown). Subsequently, a 1500 A layer 16 of SiN x , a 1500 A layer 18 of intrinsic a-Si:H and a 500 A layer 20 of phosphorus-doped a-Si:H (n + a-Si:H) are deposited. The layers 16, 18, 20 are then photoshaped and etched, forming insulator areas 16A and 16B of the transistor and crossover, respectively, and regions 18A and 18B of the transistor and crossover, respectively. It is to be noted that where a-Si:H is mentioned herein, other silicon materials could usually be substituted; e.g., hydrogenated polycrystalline silicon or a mixture of microcrystalline and amorphous silicon. A 1 μm layer 22 of aluminum is deposited over all and is photoshaped and etched to form areas 22A and 22B of the transistor and area 22C of the crossover. Areas 22A, 22B form the drain and source of the transistor while area 22C is a source connection line which couples the source to the sources of all transistors in the column (not shown) and to the source voltage supply (not shown). In order to provide proper access to the accumulated electrons over the gate region 14, the drain and source 22A, 22B and the respective ohmic contact layers 20A, 20B must overlap the gate slightly, as indicated at the reference 24. Any misalignment of this overlap, such as a masking error, would likely result in one transistor element not overlapping the gate sufficiently so that the transistor would be permanently "off". Creating the correct overlap 24 (2-4 μm) is the critical masking step referred to above. Such dimensions are hard to achieve with the known designs, since very minute changes in the masks and in the temperature differences between the substrate and the mask can have serious effects on yield. Many manufacturers have therefore resorted to "stepper" technology wherein the yield is greatly increased but the rate of production is reduced. Next, the layer 20, which still has the same outline as the areas of layers 16, 18, is plasma or reactive ion etched. This is the critical processing step previously referred to. Overetching can cause complete removal of the underlying portions of layer 18, the intrinsic a-Si:H layer, causing a transistor to remain "off". On the other hand, incomplete removal of the doped layer 20 between source and drain can result in a transistor remaining "on" permanently. Figs. 2A, 2B, illustrate two known efforts to eliminate the above- described critical steps, using self-alignment techniques, and are also taken from "Plasma Deposited Films", Chapter 8, p. 219, edited by J. Mort and F. Jansen, CRC Press, Inc. (1986). Each figure shows a cutaway view of a top gate self-aligned transistor structure. In Fig. 2A, palladium suicide (Pd 2 Si) forms a source 26A, drain 28A and gate 30A of a transistor on the glass substrate 10 with the layer 18A of a-Si:H and an insulator layer 16A such as SiN x on the substrate. In this embodiment, the typical spacing between the source/drain and the gate is only a few hundred Angstroms. Thus, again a critical step is required to prevent any electrical shorting between the gate and the source/drain. Fig. 2B shows a structure that is processed using ion implantation and a metal lift-off techique. After deposition of the metal layer 30, SiNx layer 16 and a-Si:H 18, and application of a photoresist layer 25, the metal and insulating layers are overetched so that the photoresist forms an overhang as shown. Next, a second metal layer is applied and shaped to form a source and drain 26B and 28B within a spacing 29 of 0.3 to 0.5 μm of a gate 30B. After removal of the photoresist portion 25, a hot phosphorus ion implant into the exposed areas of an a-Si:H layer 18B forms the ohmic contacts 32A, 32B. The chief disadvantage of the structure is the relatively high series resistance of the doped layer between the channel portion of layer 18 and the source/drain metal. Fig. 3 illustrates a bottom gate structure wherein, after formation of a gate 30C by deposition of a metal such as NiCr and photoshaping, an insulator 32C layer (e.g., SiO x or SiN x ), an a-Si:H layer 34C, and a layer of SiO x 36 are deposited on the glass substrate 10, followed by photoresist material (not shown). The substrate is exposed to radiation from the back, using the gate as a mask, and after the photoresist material is cured, the SiOx is etched, leaving the portion 36C as shown. Without removing the resist layer from the SiOx portion 36C, a layer 40C of n+ a-Si:H and a layer 42C of NiCr are deposited at temperatures below 120° in order to avoid thermal degradation of the resist. The portions of the layers 40C, 42C on the portion 36C are lifted off during the photoresist stripping process. An important disadvantage of the approach of Fig. 3 is that the low deposition temperature of the n+ layer 40 results in poor ohmic contact due to the inferior quality of the a-Si:H film. Fig. 4 is a series of cutaway views of the bottom gate thin film transistor of one embodiment of the present invention, illustrating the steps of the processing method. It is to be noted that, while the following description for a single transistor for simplicity, normally a large number of transistors will be created at the same time. On the transparent substrate 10, preferably of glass, a 1000 A layer 50 of nickel chrome (NiCr) has been deposited by e-beam evaporation (Fig. 4A), then photoshaped and etched to produce a gate 50A for the transistor (Fig. 4B). Gate connection lines 50B (See Fig. 7) are also formed. The photoshaping process will preferably include spinning Shipley #1470 photoresist at 4000 rpm for 30 sec, prebaking at 90° C for 30 min, exposing to appropriate UV radiation (wavelength less than 500 nm) for 30 sec, developing with Shipley #351 developer for 60 sec, rinsing with deionized water (Dl) for 3 min, and blowing dry with N 2 . This is followed by another bake at 110° for 30 min. The etchant for the NiCr is a GFS etchant. Etching is done at room temperature. The resist is then stripped off with Shipley #1165 photoresist stripper and ultrasonic agitation, followed by another Dl rinse for 3 min and an N blow dry. Next (Fig. 4C), a 1500 A layer 52 of SiN x , a 600-1000 A layer 54 of a-Si:H and a 400-600 A layer 55 of n+ a-Si:H or μc-Si (microcrystalline n-type doped silicon) are deposited at temperatures of 320°, 250° and 250° C, respectively. A layer of photoresist 56 is then applied (Fig. 4D), and removed by development (Fig. 4E) except where the gate 50A prevented exposure to ultraviolet light shining through the substrate 10 from the rear surface. The wavelength of the ultraviolet radiation should be within the range of 350 nm to 500 nm, preferably closer to 500 nm to insure more efficient transmission through the silicon layers 54 and 55. The photoresist portion 56A is termed the "sacrificial layer" as will be seen hereinafter. After the exposed resist is removed, a 200-400 A layer 58 of nickel chrome is deposited by e-beam evaporation (Fig. 4F). Then a 1 μm layer 60 of aluminum is deposited all over the NiCr, then photoshaped and etched (Fig. 4G) to form source/drain 60. As seen in (Fig. 4H), the remaining photoresist 56A and the NiCr stripper and ultrasonic agitation. Finally (Fig. 4J), the exposed portion of the n+ layer 55 is removed by plasma or reactive ion beam etching, for example. In an alternate and only slightly different sequence of the steps of Fig. 4, the residual portion of photoresist 56A and the NiCr on top of the photoresist can be removed before the aluminum layer 60 is applied. After the aluminum layer 60 is photoshaped, the exposed n+ material is etched off. In the alternate version, the n+ material above the gate serves as a barrier to prevent the aluminum from diffusing into the amorphous silicon of layer 54. The typical on/off curent ratio of a device fabricated in this manner is greater than 1 x 10 7 , and the field effect mobility is approx. 0.2 cm 2 /Vsec. The device performance is equal to those devices having overlaps of source/drain and gate of 2.0 to 5.0 μm, without the yield problem of the prior devices. Typical overlaps produced by the method described above may vary from 0.0 to1.0 μm. The parasitic capacitances between gate and source and between gate and drain are typically reduced by around half in the design described here. Fig. 5 is a series of cutaway views of a second embodiment of the bottom gate transistor of the present invention, illustrating the steps of the processing method. On the transparent substrate 10, preferably of glass, the 1000 A layer 50 of nickel chrome (NiCr) has been deposited by e-beam evaporation (Fig. 5A), then photoshaped and etched to produce the gate 50A for the transistor (Fig. 5B). Gate connection lines 50B (See Fig. 7) are also formed. The photoshaping process will preferably be as described with respect to Fig.4. Next (Fig. 5C), the 1500 A layer 52 of SiN x and the 600-1000 A layer 54 of a-Si:H are deposited at temperatures of 320° and 250° C, respectively. The photoresist layer 56 (approx. 1 μm thickness) is then applied (Fig. 5D), and removed by development (Fig. 5E) except where the gate 50A prevented exposure to ultraviolet light shining through the substrate 10 from the rear surface. After the exposed resist is removed, portions 54B, 54C of the layer 54 (see Fig. 5G) are implanted with phosphorus ions 57, at a dose of 1.0 x 10 16 ions/cm 2 and at an energy of 35-40 keV (Fig. 5F) at room temperature. During this process the region 56A acts as a mask to prevent ion implantation of the portion 54A of the layer 54, positioned above the gate region. Subsequently (Fig. 5G), a 200-400 A layer 58 of NiCr is deposited by e-beam evaporation, forming portions 58A, 58B, 58C. The remaining photoresist portion 56A is then lifted off (Fig. 5H), along with the overlying NiCr portion 58A, by Shipley #1165 photoresist stripper, which does not affect the a-Si:H layer 54. The source 58B and drain 58C are then defined fully (Fig. 5J) by photoshaping and etching the NiCr layer 58, the a-Si:H layer 54 and the SϊN x layer 52. The etchants here will be GFS, CF 4 /4% 02, and 10:1 HF, respectively, or GFS and reactive ion etching in a CHF 3 /10% 0 etch gas. The device is then annealed in forming gas for 30 min at 200° (step not illustrated). Fig. 6 shows one way of creating crossovers for the gate and source lines; i.e., utilizing the identical method steps as used for the transistor. This method produces a crossover having the NiCr gate line 50B on the substrate 10 with SiN x layer 52, ion-implanted portion 54D and non-implanted portion 54E of the a-Si:H layer 54, and portions of the NiCr layer 58 superimposed. Thus, the crossover is basically another self-aligned transistor. The source supply line 22C which is orthogonal to the gate line as shown in Fig. 1 is shown here by dashed lines for clarity. The disadvantage of the embodiment of Fig. 6 is that, since the a-Si:H material of layer 54 is a strong absorber of UV, the thickness of the layer 54 must be limited to a maximum thickness of 600- 1000 A to avoid excessively long exposure times. The combined insulating thickness of the SiN x layer 52 and layer 54 is therefore limited to less than 4000 A and may result in insufficient insulation between the gate line 50B and the source line 22C. In principle, the thickness of the layer 52 could be increased to as much as 1 μm but this would increase the threshold voltage of the TFT's which is not desirable from an electronics point of view since higher voltage driver chips would then be required in the peripheral circuitry. This crossover is described with respect to the processing method of Fig. 5. A similar crossover is formed with respect to the method illustrated in Fig. 4. With the requirement for very high yields in the devices, however, a better way of providing crossovers is desirable. Fig. 7 is a perspective view of a transistor and a crossover according to the invention, and relates to Fig. 5. On the transparent substrate 10, preferably of glass, is the transparent pixel element 12 of tin oxide, the NiCr gate 50A and gate line 50B, the SiN x layer 52, and the ion-implanted and non-implanted portions of the a-Si:H layer 54. While the structure thus resembles that of Fig. 1 , it is to be noted that relatively wide overlap 24 of Fig. 1 is missing and the overlap has been reduced to between 0.0 and 1.0 μm. As is known, this reduces the variable capacitance between gate and drain and gate and source. In this preferred embodiment the crossover insulation is formed from a 1.0 μm layer 60 of a polyimide, deposited by spin deposition, cured, and photoiithographically defined. Polyimides of 1.0 μm thickness have been determined to provide extremely low leakage currents and excellent dielectric breakdown strengths. The curing temperature will range from 250 to 400° C, depending on the type of polyimide used. Other suitable materials include SiN x , Si0 2 , and various combinations of the three materials. The required characteristics of the insulating layer are freedom from pinholes and a dielectric strength sufficiently high so that the insulation will withstand the operating voltage with some margin for safety. After photoresist developing, the excess polyimide is removed in an oxygen plasma. At this point, the crossover resembles the crossover of Fig. 6. The transistor is then fabricated as shown in Fig. 5. Subsequently, a 1.0 μm layer 22 of aluminum (Al) is deposited, photoshaped and etched to form the drain connection 22A, source connection 22B, and source supply line 22C crossing over the polyimide or other insulator material. The polyimide is preferably deposited before the transistor is formed since the oxygen plasma used in the etching of the polyimide could degrade the electrical characteristics of the silicon material. Use of the polyimide material for the crossover insulation requires an additional masking step, but improves the yield of the entire process. Fig. 8 is a plan view of the invention illustrating the feature of providing increased yield by including redundancy in both the transistor and the crossover. Thus, in case of failure of either component, the failed component can be taken out of the circuit and the corresponding additional component inserted via laser processing as described below. On the substrate 10 is the pixel element 12, two transistors T1 , T2 and two crossovers C1 , C2. T2 and C2 denote the additional elements of the redudancy. A gate line 50B connects to an extended gate, providing gate 50A-1 and a gate 50A-2. The line 50B-2 is the redundant gate connection. 22B-1 and 22A-1 are the source and drain connections, respectively, of transistor T1. Areas 22B-2 and 22A-2 are the source and drain, respectively, of transistor T2. If transistor T1 does not turn on, no modification of T1 is required, but if T1 is shorted between source connection 22B-1 and drain connection 22A-1 , a laser beam would be employed to sever the undesired connection by thermal evaporation along the dashed lines referenced "X1". Transistor T2 would be connected into the circuit by means of a laser-assisted, vapor deposition, metal writing process at the points referenced Y1. Such processes using laser beams or ion beams are known in the art. If the crossover C1 includes a short between the source and gate lines, C1 can be disconnected by directing a laser beam along the dashed lines referenced X2. The crossover C2 would then be connected into the circuit by metal writing as at points Y2. It will be apparent that the above-described methods of providing a thin film transistor are also suitable for providing driver circuits (not separately illustrated) on an active array at the same time and with the same steps as shown for the switching transistors. Also, in many instances hereinabove, specific materials, voltages and temperatures have been given to enable practice of the invention with greater facility; however, such terms and values should not be construed as limiting the scope of the invention. Thus, there has been shown and described a device and method for providing said device on the substrate of an actively addressable liquid crystal array which will control the individual pixels of the array and which can be produced by simple processing steps with suitably high yields. The device includes both bottom gate thin film transistors and connection line crossovers, with the possibility of providing redundancy for both transistors and crossovers to further increase the yield. The transistor component utilizes self-alignment to eliminate a critical masking step and may include ion implantation to eliminate a critical processing step. The crossovers utilize a polyimide or similar material as an insulation layer, and are produced by one additional masking step in the production of the transistors.

Claims: That which is claimed is: 1. A method of providing a thin film transistor and comprising the steps of: depositing a first layer of an electrically conductive material over a first surface of a substantially ultraviolet radiation transparent substrate; removing portions of said first layer to form remaining portions of said first layer into a transistor gate and gate connection line; depositing a second layer of a substantially ultraviolet radiation transparent insulating material over said remaining portions of said first layer and exposed portions of said first surface; depositing a third layer of substantially ultraviolet radiation transparent amorphous silicon material over said second layer; depositing a fourth layer of photoresist material on said third layer; irradiating said fourth layer with ultraviolet radiation transmitted through a second surface of said substrate opposite said first surface; removing said irradiated portions of said fourth layer to expose portions of said third layer in adjacent alignment with said transistor gate; implanting said exposed portions of said third layer with phosphorus ions to form ion implanted transistor source and drain regions in adjacent alignment with said transistor gate; depositing a fifth layer of an electrically conductive material over said transistor source and drain regions and said remaining portion of said fourth layer; removing a portion of said fifth layer overlaying said remaining portion of said fourth layer by removing said remaining portion of said fourth layer to form transistor source and transistor drain contact regions in adjacent alignment with said transistor gate; and removing portions of said remaining portions of said second, third and fifth layers to form a transistor source, a transistor drain and connection lines. 2. The method according to claim 1 wherein the first layer is deposited by electron-beam evaporation. 3. The method according to claim 1 wherein the transistor gate is formed by photoshaping and includes the steps of: spinning onto the substrate a photoresist material; prebaking said material; exposing said material to ultraviolet radiation; developing said material; rinsing said material with deionized water; removing said water; baking said photoresist material; etching said first conductive layer; and removing the remaining photoresist material. 4. The method according to claim 1 wherein the step of depositing said second layer is done at approximately 320° C. 5. The method according to claim 1 wherein the step of depositing said third layer is done at approximately 250°C C. 6. The method according to claim 1 wherein the step of implanting phosphorous ions is done at room temperature with a dose of approximately 1.0 x 10 16 ions/cm 2 at an energy of 35-40 keV. 7. The method according to claim 1 wherein the steps of depositing the first and fifth layers is done by electron-beam evaporation. 8. The method according to claim 1 wherein the step of forming said remaining portions of the second, third and fifth layers includes the steps of; . spinning onto the substrate a photoresist material; prebaking said material; exposing said material to ultraviolet radiation; developing said material; rinsing said material with deionized water; removing said water; baking said photoresist material; etching said second, third and fifth layers; and removing the remaining photoresist material. 9. The method according to claim 1 and further including the step of annealing the entire structure in forming gas. 10. The method according to claim 9 wherein the step of annealing the structure is done at approximately 200° C. for approximately 30 minutes.

Inventors: BUSTA HEINZ HERMANN, POGEMILLER JAY EVAN, BUSTA, HEINZ, HERMANN, POGEMILLER, JAY, EVAN
Applicants: AMOCO CORP, AMOCO CORPORATION
Application year: 1992
Main classification: H01L29
IPC codes: H01L29