Method and circuit for correcting track zero-crossing signal in optical disk system

Abstract: In order to correct a track zero-crossing signal TZC generated from a signal detected by an optical head of an optical disk system, an expected edge pulse (NP) and a window signal (WD) are generated at the position at which the appearance of the edge of the track zero-crossing signal is expected. Among the edge pulses of the actual track zero-crossing signal, only those that exist inside a window are allowed to pass through. When the edge pulses do not exist within the window, the expected pulse is inserted so as to generate a corrected edge pulse, and a corrected track zero-crossing signal is generated from this corrected edge pulse.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and circuit for correcting a track zero-crossing signal generated from a signal detected by an optical head, in an optical disk system for effecting seek control by a track crossing signal obtained by irradiating an optical beam from the optical head to an optical disk, in order to make the seek control more reliable. In comparison with a magnetic disk system, an optical disk system and an opto-magnetic disk system have the advantage that memory capacity is greater, but their application is limited because access speed is low. For the most part, the access speed is affected by the seek operation. If this seek can be carried out at high speed and moreover, accurately, the access speed can be improved and the range of the application of the optical disk'system and opto-magnetic disk system can be expanded. Therefore, a high speed and accurate seek operation is required. 2. Description of the Related Art In an optical disk system, an optical head for irradiating an optical beam to an optical disk and a motor (a voice coil motor) for driving the optical head in a radial direction of the optical disk are provided to the optical disk (opto-magnetic disk), which is rotated by a spindle motor. In the optical disk, on the other hand, a track is disposed between guide grooves and the reflected beam of the optical beam, irradiated from the optical head, from the optical disk, provides a track error signal. A track servo control circuit obtains the track position error of the optical beam from a track error (tracking error) signal TES from the optical head, and controls the optical head so that the optical beam irradiates the track. This track error signal TES is a sinusoidal wave for each track crossing period and the actual speed of the optical head can be measured from the period of this track error signal, and the number of crossed tracks can be known from the number of the track error signals TES. A seek control unit acquires the actual speed of the optical head and the present track position from the track error signal TES, effects the seek control of a motor and positions the optical head to a desired track position. In the optical disk, a mirror portion is disposed at the tail of an ID portion preformatted for each track (address information which is in advance recorded), and the guide grooves are interrupted at this mirror portion. In an optical disk system employing a system that detects tracking offset by this interrupted portion, the mirror portion is used for the detection of tracking offset. Incidentally, the optical disk system disclosed in this specification does not positively use said mirror portion. Since said mirror portion is thus disposed, the track error signal TES is broken from the ID portion to its tail part when a seek is carried out at a relatively low speed of the track crossing period of 50 to 100 msec, and an excess of pulses appear in a track zero-crossing signal TZC generated by slicing the track error signal TES by a zero level. A frequency of the track error signal TES is about 500 KHz during the high speed seek. Therefore, the amplitude itself of the track error signal TES becomes small because of the frequency characteristics of an amplifier, and if the ID noise appears on the signal, track crossing cannot be detected by the zero-crossing signal TZC. To correct this phenomenon, Japanese Unexamined Patent Publication (KOKAI) No. 2-137129, for example, discloses a method that corrects the track zero-crossing signal by providing a correction circuit that generates pseudo pulse signals. This prior art method measures the period T of the track zero-crossing signal TZC, generates the pseudo pulse when an edge pulse of the track zero-crossing signal TZC does not appear within an interval 1.5T and adds it to the edge pulse to thereby correct the track crossing pulse. However, the conventional technique involves the following problems. (i) Since the pseudo pulse is merely inserted, the excess track zero-crossing signal TZC resulting from the breakage of the track error signal TES described above cannot be eliminated, and an error occurs in the number of crossed tracks and an accurate seek operation cannot be made. (ii) Since the pseudo pulse is generated at the position of 1.5 times of the period T described above, the speed greatly deviates from actual speed and the speed control cannot be made correctly when the speed is obtained from the period of the track zero-crossing signal TZC. (iii) The edge pulses of the track zero-crossing signals TZC within the 1.5 times of the previous period are all handled as correct pulses even though the waveform of the track error signal TES is previously disturbed. Therefore, the detected speed deviates greatly from the actual speed when the speed is obtained from the period of the track zero-crossing signal TZC, and the speed control cannot be correctly made. (iv) If the amplitude of the track error signal TES is small as described above, the pseudo pulse cannot be generated because the track zero-crossing signal TZC cannot be continuously obtained. Accordingly, an error occurs in the number of crossed tracks an accurate seek operation cannot be made. The preambles of claims 1 and 5 respectively define a method and apparatus for correcting a raw track zero-crossing signal from an optical head in a disk read and/or write system as known from document EP-A-0 401 973. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method and circuit that can prevent the occurrence of an error in the number of crossed tracks and detect accurately the actual speed. According to the present invention, there is provided a method of producing corrected track error signals from the raw output of track error detector used for positioning a read head in an optical disk system, comprising the steps recited in claim 1. The present invention also relates to a track error correcting circuit and an optical disk read and/or write apparatus based on this method, as specified in claims 5 and 10 respectively. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an embodiment of the present invention; Fig. 2 is a structural view of an optical head according to the embodiment of the present invention; Fig. 3 is a block diagram of a track servo control circuit according to the embodiment of the present invention; Fig. 4 is a block diagram of a VCM servo circuit according to the embodiment of the present invention; Fig. 5A and 5B are waveform diagrams for explaining a seek operation in the embodiment of the present invention; Fig. 6 is a block diagram of a TZC signal correction circuit in the embodiment of the present invention; Fig. 7 is a circuit diagram of a mask signal generation circuit in the embodiment of the present invention; Fig. 8 and 9 are circuit diagrams of control signal generation circuits in the embodiment of the present invention; Figs. 10 and 11 are circuit diagrams of window generation circuits in the embodiment of the present invention; Figs. 12 and 13 are circuit diagrams of sequence circuits in the embodiment of the present invention; Fig. 14 is a circuit diagram of a track counter circuit in the embodiment of the present invention; Figs. 15A to 15K are waveform diagrams for explaining an operation of the embodiment of the present invention; Figs. 15A to 16K are waveform diagrams for explaining another operation of the embodiment of the present invention; and Figs. 17A to 17I are waveform diagrams for explaining another operation of the embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Optical Disk System Fig. 1 is a block diagram of an embodiment of the present invention. In Fig. 1, an optical disk 10 is rotated at a constant speed by a spindle motor 12, and is read/written by an optical beam 16 from an optical head 14. The optical head 14 is moved for a seek operation by a voice coil motor 18 on a rail 20 in a radial direction of the optical disk 10, and a track servo control circuit 22 drives and controls an actuator for a later-appearing objective lens based on a track error signal TES from the optical head 14. Furthermore; a voice coil motor (VCM) servo circuit 24 drives and controls the voice coil motor 18. In this way, this system employs a double servo system for tracking and controlling the optical beam 16. A TZC correction circuit 26 corrects a track zero-crossing signal TZC from the track servo control circuit 22 and outputs a corrected track zero-crossing signals TZC . A track counter circuit 28 counts the number of crossed tracks and detects the actual speed, based on the corrected track zero-crossing signal TZC . A control unit 30 (MPU) consists of a microprocessor, determines a target speed from the number of crossed tracks counted by the track counter circuit 28 and outputs an instruction current corresponding to the error in the actual speed measured by the track counter circuit 28 to a VCM servo circuit 24 (in the case of an ordinary seek) or to the servo control circuit 22 (in the case of a lens seek). Fig. 2 is a structural view of the optical head 14 shown in Fig. 1. The outgoing beam of a semiconductor laser 32 is converted by a collimator lens 34, passes through a beam splitter prism 36, is reflected by a reflection mirror 38, is condensed by an objective lens (actuator) 40 and irradiates the surface of the optical disk 10. The reflected beam from the beam splitter prism 36 is incident into an optical sensor 42, and is utilized for stabilizing the output of the semiconductor laser 32. At this time, a magnet 44 disposed so as to face the optical disk 10 provides magnetic force, and the optical disk 10 is read/written/erased as an opto-magnetic disk. The reflected beam from the optical disk 10 is condensed by the objective lens 40, is reflected by the reflection mirror 38 and the beam splitter prism 36, is converted by a condenser lens 48 through a 1/2 wavelength plate 46, passes through a polarization beam splitter 50, irradiates a two-division photodetector 52 for tracking and is reflected to a four-division photodetector 54 for focusing. The two-division photodetector 52 for tracking is divided into two segments so that it can detect the moving distance in the track direction on the surface of the optical disk 10, and the outputs A and B pass through an automatic gain control (AGC) circuit 66 (see Fig. 3), and a differential amplifier 56 calculates the difference and provides a track error signal TES. The four-division photodetector 54 for focusing subtracts the output of two inner beam reception devices from the output of two outer beam reception devices by a differential amplifier 58 and provides a focus error signal FES. Furthermore, an addition amplifier 60 adds the output of the two outer beam reception devices of the four-division photodetector 54 for focusing to the output of the two inner beam reception devices, and an addition amplifier 62 adds the outputs A and B of the two-division photodetector 52 for tracking. This sum is subtracted from the sum of the addition amplifier 60 by a differential amplifier 64 to provide a reproduction signal RS. Fig. 3 is a block diagram of the track servo control circuit 22 shown in Fig. 1. The outputs A and B of the two-division photodetector 52 for tracking are subjected to AGC by an AGC circuit 66 and are converted from current signals to voltage signals and their difference is calculated by the differential amplifier 56 to provide a raw track error signal TES. The reason AGC is applied is to correct the change of optical power of the semiconductor laser and correct a reflection factor of a medium. The track offset from the MPU 30 is converted to an analog signal by a digital/analog convertor 68 and is added by an addition circuit 70 to the track error signal TES. The gain of this signal is adjusted by a gain control circuit 72 and its phase is advanced by a phase compensation circuit 74 to provide an actuator driving current. When the track servo is ON, a switch 76 is kept ON and a driving current is supplied to a driving unit 80 through an addition circuit 78. Therefore, an actuator coil 82 is driven and effects the track servo control by driving the objective lens 40. On the other hand, a comparator 84 slices the track error signal TES by the track offset from the digital/analog convertor 68, and generates a high level track zero-crossing signal TZC when the track error signal TES is above the track offset and a low level track zero-crossing signal TZC when the signal TES is below the track offset. A phase compensation circuit 86 and a switch 88 are disposed in order to prevent a run-away of the actuator 82 during the ordinary seek operation (position seek). The switch 88 is turned ON from a lens lock-on signal from the MPU 30 and the actuator 82 is kept fixed at a neutral point by a lens position signal LPOS from the optical head 14. Switches 90 and 92 from part of a circuit for effecting a kick control. Under the on-track state, this circuit jumps the optical beam by one track when the optical beam is about to move to the inner side. The switch 90 is turned ON by the control of the MPU 30 so as to apply a pulsed acceleration voltage in an outer direction to a driving unit 80, and the switch 92 is turned ON so as to apply a pulsed acceleration voltage in an inner direction to the driving unit 80. These switches 90 and 92 are used also for the purpose of deceleration at the time of stopping immediately before the arrival at a target track. A digital/analog convertor 94 is a circuit for seeking the lens by controlling the objective lens actuator 82. In order to effect the lens seek in a relatively short distance (1 to 100 tracks), it converts the actuator current, which is by far slower than the position seek by the MPU 30, to an analog quantity and applies it to the driving unit 80. The MPU 30 controls the actuator current so as to reach the target track. Fig. 4 is a block diagram of the VCM servo circuit 24 shown in Fig. 1. While the track servo is applied, a switch 96 is turned ON by a double servo-ON signal from the MPU 30. The phase of the lens position signal LPOS from the optical head 14 is advanced by a phase compensation circuit 98 and is converted to a speed signal, and mechanical resonance components f0, f1 are cut off by a notch filter 102 through an addition circuit 100. The signal is then applied to a driving unit 104 so as to drive the VCM. The switch 96 is turned OFF at the time of the position seek, and a VCM current in the form of a digital signal is applied from the MPU 30 to a digital/analog convertor 106. After mechanical resonance components f0, f1 are cut off by the notch filter 102 through the addition circuit 100, the current is applied to the driving unit 104 to drive the VCM 18. Figs 5A and 5B are waveform diagrams for explaining the seek operation. When a seek instruction is given from a controller not shown in the drawings, the MPU 30 turns ON the track servo (by turning OFF the switch 76 of the track servo circuit and turning ON the switch 88), and moves the optical head 14 in a designated direction and by a designated difference. There are two kinds of seek operations. One is the lens seek for controlling the objective lens actuator 40 and the other is the position seek for controlling the VCM 18. The position seek is a high speed seek operation for driving and moving the VCM, and this operation positions the optical head 14 to a target track at high speed. To accomplish this object, the MPU 30 sets a target speed from the seek direction and the difference as shown in Fig. 5A, determines a speed error, and applies a VCM current shown in Fig. 5B to a digital/analog convertor 106 of the VCM servo circuit 24 so that this speed error becomes zero. The MPU 30 reads the number of crossed tracks and the present speed from the track counter circuit 28 (see Fig. 1), subtracts the number of crossed tracks from the target number of tracks for determining the number of remaining tracks, calculates a target speed and a feedforward quantity in accordance with the number of remaining tracks, calculates the speed error from (target speed - present speed + feedforward quantity), and supplies the VCM current to the digital/analog convertor 106 of the VCM servo circuit 24 so that the speed error becomes zero. This feedforward quantity is the information necessary for decelerating the optical head 14 when the head reaches the target speed and comes close to the target track, and is in advance stored in the memory of the MPU 30. The lens seek is employed for the seek operation, which moves in a relatively short distance (1 to 100 tracks). The actuator current at a speed far slower than that of the position seek of the MPU 30 is output to the digital/analog convertor 94, is converted to the analog quantity, and is applied to the driving unit 80 so as to drive the objective lens actuator 82. The MPU 30 similarly controls the actuator current so as to reach the target track. Seek Control Circuit Fig. 6 is a block diagram of the TZC correction circuit shown in Fig. 1. In the drawing, a synchronization circuit 108 synchronizes the track zero-crossing signal TZC from the track servo control circuit 22 with a system clock SCL (about 10 MHz) having a sufficiently higher frequency than the track crossing period. An on-edge generation circuit 110 generates an on-edge pulse NP at the rise of the synchronized track zero-crossing signal TZC. An off-edge generation circuit 112 generates an off-edge pulse FP at the fall of the synchronized track zero-crossing signal TZC. A mask signal generation circuit 114 detects the period of the track zero-crossing signal TZC from the on-edge pulse NP, as will be described later with reference to Fig. 7, compares it with the maximum period set by the MPU 30, generates a mask signal MS when the detected period is greater than the maximum period and inhibits the operation of later-appearing sequence circuits 116 and 118. As will be explained later with reference to Fig. 12, the sequence circuit 116 outputs only the on-edge pulse NP within the period of a rise window signal WU from a later-appearing control signal generation circuit 122 as a corrected on-edge pulse ONP when the mask signal MS is not generated, and outputs an expected on-edge pulse HNP from the control signal generation circuit 122 as a corrected on-edge pulse ONP when the on-edge pulse NP does not exist within the period of the rise window signal WU. As will be explained later with reference to Fig. 13, the sequence circuit 118 outputs only the offedge pulse FP within the period of a fall window signal WD from a later-appearing control signal generation circuit 120 as a corrected off-edge pulse OFP when the mask signal MS is not generated, and outputs an expected off-edge pulse HFP from the control signal generation circuit 120 as a corrected off-edge pulse OFP when the off-edge pulse FP does not exist within the period of the fall window signal WD. As will be explained later with reference to Fig. 8, the control signal generation circuit 120 measures the interval between the normal on-edge pulse ONP output by the sequence circuit 116 and the normal off-edge pulse OFP output by the sequence circuit 118, generates the fall window signal WD with a position expected from the interval being the center, and generates an expected off-edge pulse HFP at the expected position. As will be explained later with reference to Fig 9, the control signal generation circuit 122 measures the interval between the normal off-edge pulse OFP output by the sequence circuit 118 and the normal on-edge pulse ONP output by the sequence circuit 116, generates the rise window signal WU with a position expected from the interval being the center, and generates an expected on-edge pulse HNP at the expected position. A flip-flop 124 for generating the track zero-crossing signal is set by the corrected on-edge pulse ONP from the sequence circuit 116, is reset by the corrected off-edge pulse OFP from the sequence circuit 118, and generates a corrected track zero-crossing signal TZC . Fig. 7 is a circuit diagram of the mask signal generation circuit 114 shown in Fig. 6. A one-period counter 125 is reset by a detected on-edge pulse NP from the on-edge generation circuit 110, starts counting, counts the number of system clocks SCL and counts the interval of the detected on-edge pulses NP (the period of the track zero-crossing signal TZC). A one-period retention flip-flop 127 holds the count value of the counter 125 by the detected on-edge pulse NP from the on-edge generation circuit 110. A comparison circuit 130 compares the time A of one period held by the flip-flop 127 with the maximum value B of one period from the MPU 30, and generates a high level mask signal MS when A > B. Therefore, when at a low speed and the period A of the track zero-crossing signal TZC exceeds the set maximum value B, it generates the high level mask signal MS and nullifies the operation of the sequence circuits 116 and 118. The TZC correction circuit 26 of the present invention corrects the zero-crossing signal TZC by limiting the change of the period of the zero-crossing signal TZC generated at irregular intervals within a predetermined range. When the seek speed is below a predetermined value, or in other words, when the pulse interval of the zero-crossing signal TZC is above a predetermined value, the value of the pulse interval as an inverse number of the speed is great. Accordingly, the change quantity of the value of the pulse interval is also great even in the normal zero-crossing signal. When the correction described above is effected, an undesirable result will occur. In such a case, the mask signal MS is generated in the afore-mentioned mask signal generation circuit 114 (see Fig. 7) and is applied to the sequence circuits 116, 118 so as to mask their operations and thus not effect the correction of the zero-crossing signal. Incidentally, the correction of the zero-crossing signal is not made because of the mask signal during the low speed seek operation. However, elimination of the noise components can easily be accomplished within the range where the frequency of the zero-crossing signal is low, by constituting the comparator 84 (Fig. 3) so as to have a suitable hysteresis. Figs. 8 and 9 are circuit diagrams of the control signal generation circuits 120 and 122 shown in Fig. 6, respectively. Figs. 10 and 11 are circuit diagrams of the window generation circuits 124 and 126 shown in Figs. 8 and 9, respectively. In the control signal generation circuit 120 shown in Fig. 8, a High time counter 128 is reset by the corrected on-edge pulse ONP from the sequence circuit 116, starts counting and counts the system clocks SCL. An AND gate 130 passes the normal off-edge pulse OFP from the sequence circuit 118 when the mask signal MS from the mask signal generation circuit 114 is at a low level. A High time holding flip-flop 132 holds the count value of the counter 128 by the off-edge pulse OFP from the AND gate 130. In an expected off-edge generation timer 134, the held value of the flip-flop 132 (the interval from the on-edge pulse ONP to the off-edge pulse OFP, i.e. the High time of the track zero-crossing signal TZC) TH is loaded by the corrected on-edge pulse ONP the system clocks SCL are counted down, and an expected off-edge pulse HFP is generated after the passage of the High time (expected time) of the track zero-crossing signal TZC. As will be explained with reference to Fig. 10, the window generation circuit 124 compares the last High time TH held by the flip-flop 132 with the count value of the counter 128 and when the High time and the count value coincide with each other (expected timing), generates a fall window signal WD of a predetermined width with this timing as the center. As will be explained later in further detail, the corrected on-edge pulses ONP are the OR of the normal on-edge pulses ONP and the expected on-edge pulses HNP. The normal on-edge pulses ONP are those pulses among the detected on-edge pulses NP, that exist within the rise window WU. Similarly, the corrected off-edge pulses OFP are the OR of the normal off-edge pulses OFP and the expected off-edge pulses HFP. The normal off-edge pulses OFP are those pulses among the detected off-edge pulses FP, that exist within the fall window WD. As shown in Fig. 8, the corrected on-edge pulse ONP is used for resetting the counters 128 and 134 but the normal off-edge pulse OFP is used for holding the High time in the flip-flop 132. As will be described later in detail, when the normal pulse ONP or OFP is output at a timing later than the expected pulse HNP or HFP, the two pulses are continuously output as the corrected pulse ONP or OFP . Therefore, the High time is held at the timing of the normal pulses ONP, OFP so as to obtain the newest High time. In this case, even when the counters 128 and 134 are reset by the expected on-edge pulse HNP, they are again reset by the normal on-edge pulse ONP succeeding immediately thereafter, so that the interval between the normal on-edge pulse ONP and the normal off-edge pulse OFP is held as the High time. In the window generation circuit 124 shown in Fig. 10, a shift circuit 136 consisting of a large number of multiplexers shifts the High time TH held by the flip-flop 132 to the right by the number of bits designated by a window margin Wm set from the MPU 30, and generates a window width W. An adder 138 adds the High time TH to the window width W, and a subtracter 140 subtracts the window width W from the high time TH. A comparator 142 compares the outputs A (= TH + W) of the adder 138 with the count value B of the counter 128 and generates a high level output when A > B. A comparator 144 compares the count value A of the counter 128 with the output B (= TH - W) of the subtracter 140 and generates a high level output when A > B. An AND gate 146 calculates AND (logical product) between the outputs of these comparators 142 and 144 and generates a fall window signal WD having a width ±W with the timing after the High time TH as the center. In the control signal generation circuit 122 shown in Fig. 9, a low time counter 148 is reset by the corrected off-edge pulse OFP from the sequence circuit 118, and counts the system clocks SCL. An AND gate 150 allows the passage of the normal on-edge pulse ONP from the sequence circuit 116 when the mask signal MS from the mask signal generation circuit 114 is at a low level. A low time holding flip-flop 152 holds the count value of the counter 148 by the on-edge pulse ONP from the AND gate 150. In the expected on-edge generation timer 154, the held value of the flip-flop 152 (the interval from the off-edge pulse OFP to the on-edge pulse ONP, that is, the low time of the track zero-crossing signal TZC) TL is loaded by the corrected off-edge pulse OFP the system clocks SCL are counted down, and an expected on-edge pulse HNP is generated after the passage of the low time TL (expected time) of the track zero-crossing signal TZC. As will be explained with reference to Fig. 11, the window generation circuit 126 compares the last low time TL retained in the flip-flop 152 with the count value of the counter 148, and generates a rise window signal WU of a predetermined width with the point of time (expected time), at which the low time TL coincides with the count value, as the center. For the same reason as has been explained with reference to the control signal generation circuit 120, the counters 148 and 154 are reset by the timing of the corrected off-edge pulse OFP , and the low time TL is held by the flip-flop 152 at the timing of the normal on-edge pulse ONP. In the window generation circuit 126 shown in Fig. 11, a shift circuit 156 consisting of a large number of multiplexers shifts the low time TL held by the flip-flop to the right by the number of bits designated by the window margin Wm and generates the window width W. An adder 158 adds the low time TL to the window width W and a subtracter 160 subtracts the window width W from the low time TL. A comparator 162 compares the output A (= TL + W) of the adder 158 with the count value B of the counter 148 and generates a high level output when A > B. A comparator 164 compares the count value A of the counter 148 with the output B (= TL - W) of the subtracter 160 and generates a high level output when A > B. An AND gate 166 generates a rise window signal WU of a width ±W with the timing at which the low time TL has passed, with the center by calculating the AND (logical product) between the outputs of the comparators 162 and 164. Figs. 12 and 13 are circuit diagrams of the sequence circuits 116 and 118 shown in Fig. 6, respectively. In Fig. 12, the rise window WU is input to the off-edge pulse generation circuit 168 and to the on-edge pulse generation circuit 170 and the off-edge pulse and on-edge pulse of the rise window WU are generated, respectively. An OR gate 172 calculates the OR (logical sum) between the on-edge pulse NP from the on-edge generation circuit 170 (see Fig. 6) and the off-edge pulse of the rise window WU from the off-edge generation circuit 168. A flip-flop 174 set by the on-edge pulse of the rise window WU from the on-edge generation circuit 170 is reset by the output of the OR gate 172 and generates a gate signal. An OR gate 176 calculates the OR (logical sum) between the gate signal from the flip-flop 174 and the inverted enable signal EN from the MPU 30. The inverted enable signal EN from the MPU 30 is supplied in order to nullify operations of this circuit 116 during the period in which the period of the track zero-crossing signal. TZC has not been stabilized sufficiently such as at the initial seek stage, and to initialize the circuit during the passage of two to three tracks until the period of the track zero-crossing signal TZC becomes stabilized. An AND gate 178 allows the passage of only those pulses among the on-edge pulses NP from the on-edge generation circuit 110 (Fig. 6) that exist during the period of the window signal from the OR gate 176 as the normal on-edge pulses ONP. A flip-flop 180 set by the output from the AND gate 178 is reset by the corrected off-edge pulse OFP output from the sequence circuit 118 and generates a gate signal for the expected pulse. An AND gate 182 is opened by the Q output of the flip-flop 180 and by the AND signal between the enable signal EN and the inverted mask signal MS , and allows the passage of the expected on-edge pulse HNP from the control signal generation circuit 122. An OR gate 184 calculates the OR between the normal on-edge pulse ONP passing through the AND gate 178 and the expected on-edge pulse HNP from the AND gate 182, and outputs the corrected on-edge pulse ONP . Accordingly, when the detected on-edge pulse NP appears in a period other than the period of the rise window WU, the pulse is cut off by the AND gate 178, and when the detected on-edge pulse NP appears within the period of the rise window WU, the expected on-edge pulse HNP is cut off by the AND gate 182 by the low level output of Q . If the detected on-edge pulse NP does not appear during the period of the rise window WU, the expected on-edge pulse HNP is output by the AND gate 182 by the high level output of Q . In Fig. 13, the fall window WD is input to the off-edge generation circuit 186 and to the on-edge generation circuit 188, and the on-edge pulse of the fall window and the off-edge pulse of the fall window are generated, respectively. An OR gate 190 calculates the OR (logical sum) between the off-edge pulse FP from the off-edge generation circuit 112 (Fig. 6) and the off-edge pulse of the fall window WD from the off-edge generation circuit 186. A flip-flop 192 set by the on-edge pulse on the fall window WD is reset by the output of the OR gate 190 and generates a gate signal. An OR gate 194 calculates the OR (logical sum) between the gate signal from the flip-flop 192 and the inverted enable signal EN from the MPU 30. An AND gate 196 allows the passage of only those pulses among the off-edge pulses FP from the off-edge generation circuit 112 that exist during the period of the window signal from the OR gate 194 as the normal off-edge pulses OFP. A flip-flop 198 set by the output of the AND gate 196 is reset by the corrected on-edge pulse ONP output by the sequence circuit 116 and generates the gate signal for the expected pulses. An AND gate 200 is opened by the Q output of the flip-flop 198 and by the AND signal between the enable signal EN and the inverted mask signal MS and allows the passage of the expected off-edge pulse HFP from the control signal generation circuit 120. An OR circuit 202 calculates the OR between the normal off-edge pulse OFP passing through the AND gate 196 and the expected off-edge pulse HFP passing through the AND gate 200, and outputs the corrected off-edge pulse OFP . Accordingly, when the detected off-edge pulse FP appears during the period other than the period of the fall window WD, it is cut by the AND gate 196, and when the detected off-edge pulse FP appears within the period of the fall window WD, the expected off-edge pulse HFP is cut by the AND gate 200 because of the low level output of Q and when the detected off-edge pulse FP does not appear during the period of the fall window WD, the AND gate 200 outputs the expected off-edge pulse HFP because of the high level output of Q . In Fig. 12 or Fig. 13, if the normal on-edge pulse ONP or the normal off-edge pulse OFP appears earlier than the expected on-edge pulse HNP or the expected off-edge pulse HFP, the expected on-edge pulse HNP or the expected off-edge pulse HFP is checked by the gate 182 or the gate 200. However, if the expected on-edge pulse HNP or the expected off-edge pulse HFP appears earlier, they are not checked. Accordingly, the two pulses continuously appear at the output of the OR gate 184 or the OR gate 202. Even if such a case occurs, the counters 128, 134, 148, 154 in the control signal generation circuit shown in Fig. 8 or 9 are again reset by the later pulse, and a retention operation is effected at the timing of the normal on-edge pulse ONP or the normal off-edge pulse OFP. For this reason, the windows WD, WU and the expected pulses HFP, HNP are always generated from the newest data. Fig. 14 is a block diagram of the track counter circuit 28 shown in Fig. 1. In Fig. 14, a zero-crossing pulse generation circuit 204 generates a zero-crossing pulse that is in synchronism with the clock at the rise or fall timing of the track zero-crossing signal TZC depending on whether a polarity signal POL indicating the inner or outer direction is at the H level or at the L level. A latch pulse generation circuit 206 generates a latch pulse in accordance with the latch signal from the MPU 30. A frequency division circuit 208 changes a frequency division ratio of the system clock in accordance with the frequency switch instruction from the MPU 30, and generates an operation clock. A load pulse generation circuit 210 generates a load pulse in accordance with the instruction from the MPU 30. An interval counter 212 measures the interval of the zero-crossing pulses by counting the operation clocks. An interval latch 214 latches the measured value (zero-crossing interval) of the interval counter 212 by the zero-crossing pulse. A data retention flip-flop 216 holds the latch content (the latest zero-crossing interval) of the interval latch 214 by the latch pulse. A data retention flip-flop 218 latches and holds the measured value (the number of counts from the latest zero-cross to the present) of the interval counter 212 by the latch pulse. An invertor 220 calculates a complement of the target number of tracks from the MPU 30 and the result is loaded to a crossed track number counter 222 in accordance with the load pulse. Since the zero-crossing pulse is applied to the enable terminal EN of the crossed track number counter 222, the number of remaining tracks is counted. A data retention flip-flop 224 holds the number of remaining tracks of the crossed track number counter 222 in accordance with the latch pulse. In this embodiment, the interval counter 212 counts the interval of the zero-crossing pulses to update the interval latch 214. The complement of the target number of tracks is loaded to the crossed track number counter 222 prior to the seek operation, which counts the zero-crossing pulses, and measures the number of remaining tracks. The MPU 30 generates the latch signal when reading the data to output the latch pulse, and lets the flip-flop 216 to hold the latest zero-crossing interval of the interval latch 214. The MPU 30 also lets the flip-flop 218 hold the number of counts up to the present from the latest zero-crossing pulses of the interval counter 212, and lets the flip-flop 224 hold the number of remaining tracks. The MPU 30 reads the data of the flip-flops 216, 218, 224, obtains the actual speed from the inverted number of the latest zero-crossing interval and calculates the target speed from the number of remaining tracks. The number of counts from the latest zero-crossing pulse to the present number of counts is used for position detection for the purpose of speed control at the time of the stop control. The frequency division ratio of the system clock is changed in accordance with the frequency switch instruction from the MPU 30 for the purpose of accommodating the one-track passage time within the bits of the counter 212 by the use of a high frequency (about 4 MHz) when the zero-crossing interval is short in the high speed operation mode such as during the seek operation, and by using a lower frequency (about 1 MHz) than the frequency at the time of acceleration, when the zero-crossing interval is relatively long. Seek Control Operation Figs. 15A to 15K are waveform diagrams explaining the operation of an embodiment of the present invention. Fig. 15A represents the case where the front edge of the track error signal TES is disturbed by the presence of the ID portion and the mirror portion. The High time counter 128 (see Fig. 8) of the control signal generation circuit 120 is reset by the corrected on-edge pulse ONP , and starts counting the High time of the track zero-crossing signal TZC. The high time of this high time counter 128 is always compared with the previous high time held by the flip-flop 132 in the comparators 142, 144 of the window generation circuit 124, and the fall window signal WD is generated with the timing, at which the previous High time has passed away, as the center as shown in Fig. 15E. In the off-edge generation timer 134 (see Fig. 8), the previous high time held by the flip-flop 132 is loaded by the corrected on-edge pulse ONP . When the system clocks SCL are counted down and the high time TH has passed away from ONP , the expected off-edge pulse HFP is generated as shown in Fig. 15H. Similarly, the low time counter 148 (Fig. 9) of the control signal generation circuit 122 is reset by the off-edge pulse OFP , and starts counting the low time of the track zero-crossing signals TZC. The low time of the low time counter 148 is always compared with the previous low time TL in the comparators 162, 164 of the window generation circuit 126, and the rise window signal WU is generated at the timing, at which the previous low time has passed away, with the center as shown in Fig. 15C. In the on-edge generation timer 154 (Fig. 9), the previous low time TL held by the flip-flop 152 is loaded by the off-edge pulse OFP , and counts down the system clocks SCL. When the low time TL passes away from OFP , the expected on-edge pulse HNP is generated as shown in Fig. 15G. When the detected on-edge pulse NP appears in the period other than the period of the rise window WU in the sequence circuit 116 (Fig. 12), it is cut off by the AND gate 128. When the on-edge pulse NP appears within the period of the rise window WU, the expected on-edge pulse HNP is cut off by the AND gate 182 by the low level output of Q of the flip-flop 180. When the detected on-edge pulse NP does not appear within the period of the rise window WU, the expected on-edge pulse HNP passes through the AND gate 182 because of the high level output of Q of the flip-flop 180. Similarly, when the detected off-edge pulse FP appears in the period other than the period of the fall window WD in the sequence circuit 118 (Fig. 13), it is cut off by the AND gate 196 and when the detected off-edge pulse FP appears within the period of the fall window WD, the expected off-edge pulse HFP is cut off by the AND gate 200 because of the low level output of Q . When the detected off-edge pulse FP does not appear within the period of the fall window WD, the expected off-edge pulse HFP passes through the AND gate 200 because of the high level output of Q of the flip-flop 198. In this way, as shown in Figs. 15A to 15K, the detected on-edge pulse NP represented by 5 ○ is cut by the rise window WU, the expected on-edge pulse HNP represented by 6 ○ is inserted, and the corrected track zero-crossing signal TZC can thus be obtained. Figs. 16A to 16K and Figs. 17A to 17I are waveform diagrams for explaining the operation of an embodiment of the present invention. Figs. 16A to 16K illustrate the case where the front edge of the track error signal TES is somewhat disturbed and Figs. 17A to 17I illustrate the case where the amplitude of the track error signal TES is disturbed and hence, zero-crossing cannot be detected. In Figs. 16A to 16K, the detected on-edge pulse NP represented by 5 ○ exists within the period of the rise window WU and is not therefore cut. The expected on-edge pulse HNP at the expected position of 6 ○ is cut because the detected on-edge pulse NP of 5 ○ first appears within the period of the rise window WU. When the detected off-edge pulse FP appears after the expected position within the period of the fall window WD as represented by 7 ○, the expected off-edge pulse HFP and the detected off-edge pulse FP are output as the off-edge pulse OFP after correction, but the flip-flop 124 (Fig. 6) neglects the detected off-edge pulse FP. The low time counter 148 (Fig. 4) of the control signal generation circuit 122 is once reset by the expected off-edge pulse HFP, but it is again reset by the detected off-edge pulse FP so that the measurement of the low time by the detected off-edge pulse FP becomes possible. In Figs. 17A to 17I, the expected off-edge pulse generation timer 134 and the high time measurement timer 128 are reset at 5 ○ and 7 ○ by the expected on-edge pulse HNP, and the expected on-edge pulse generation timer 154 and the low time measurement timer 148 are reset by the expected off-edge pulse HFP at 6 ○ and 8 ○ , Accordingly, the expected edge pulse and the window signal can be generated in succession. Another Embodiment Besides the embodiment described above, the present invention can be modified in the following ways. i) Though the present invention has been described with reference to the opto-magnetic disk system, it can be applied likewise to an optical disk system. ii) Though the embodiment described above uses both of the on-edge and off-edge pulses of the track zero-crossing signal TZC, correction may be carried out using either of them. Although the present invention has thus been described with reference to the preferred embodiment thereof, the invention can naturally be changed and modified in various ways without departing from the scope thereof, and such changes and modifications should not be excluded from the scope of the present invention. As explained above, the present invention provides the following effects. i) The present invention measures the period of the track zero-crossing signal, generates the window signal and the expected pulse at the expected position of the edge pulse of the next track zero-crossing signal from the period thus measured, and masks the detected pulse by the window signal. Accordingly, the pulses detected at positions other than the expected position can be cut and the excessive track zero-crossing signal TZC can be cut so that the track zero-crossing signal TZC, which is deviated by the disturbed track error signal TES, can be corrected. ii) When the detected edge pulse does not exist within the window signal, the expected pulse is output and when the detected pulse does exist within the window signal, the detected pulse is output and the corrected track zero-crossing pulse is output. Accordingly, the expected pulse can be inserted at the expected position, and the deviation of the period can be prevented and the actual speed can be accurately detected.

Claims: A method of producing corrected track crossing signals ( TZC ) from the raw track error signal (TES) obtained from a track error detector (56) used for positioning an optical head (14) in an optical disk system, comprising the steps of: detecting (at 132, 134) the zero-crossings of the raw track error signal (TES) and generating track crossing pulses (NP, FP) corresponding to said detected zero-crossings; generating (at 152, 154) expected pulses (HFP, HNP) whose timings are synchronous with the track crossing pulses (NP, FP) expected to be generated on the basis of past detected track crossing pulses; generating a timing signal defining respective expected time windows (WU, WD) within which said expected track crossing pulses are positioned; allowing (at 162, 164) the generated track crossing pulses to pass through as edges of the corrected track crossing signal ( TZC ) if those pulses are generated within their corresponding expected time windows (WU, WD); eliminating said generated track crossing pulses if they occur outside their corresponding expected time windows (WU, WD); and inserting said generated expected pulses (HFP, HNP) as edges of the corrected track crossing signal ( TZC ) when no track crossing pulses are generated within their respective expected time windows (WU, WD); characterized in that said raw track error signal (TES) from said track error detector (56) is transformed into a raw track zero-crossing square wave (TZC) by means of a zero-crossing detector (68, 84) and in that preceding edges of said square wave (TZC) are used to determine said time windows (WU, WD) and said expected pulses (HFP, HNP). A method as claimed in claim 1, wherein the edges of the raw track zero-crossing square wave (TZC), the expected pulses (HFP, HNP), and the expected time windows (WU, WD) include on-edges and off-edges of the raw track zero-crossing square wave (TZC), expected on-edge pulses and off-edge pulses, and expected time-windows of on-edges and off-edges, respectively. A method as claimed in claim 1 or 2, further comprising the step of determining the speed of said head in a seek mode by detecting time intervals between detected zero-crossings of the raw track zero-crossing square wave (TZC); wherein : said steps of eliminating said generated track crossing pulses if they occur outside their corresponding expected time windows (WU, WD) and inserting instead said generated expected pulses (HFP, HNP) of the corrected track crossing signal ( TZC ) are performed on condition that said head (14) has a seek speed above a predetermined limit; and all of the edges of raw track zero-crossing square wave (TZC) are allowed to pass through as edges of the corrected track zero-crossing signal if said seek speed is below said predetermined limit. A method as claimed in claim 1, 2 or 3, wherein, in the generating step, the expected pulses (HFP, HNP) and the expected time windows (WU, WD) are generated based on the past generated track crossing pulses that have been allowed to pass through in the allowing step. A circuit for producing corrected track crossing signals ( TZC ) from the raw track error signal (TES) from a track error detector (56) used for positioning an optical head (14) in an optical disk system, said circuit comprising : means for detecting the zero-crossings of the raw track error signal (TES) and for generating track crossing pulses (NP, FP) corresponding to said detected zero-crossings; means (152, 154) for generating expected pulses (HFP, HNP) whose timings are synchronous with the track crossing pulses (NP, FP) expected to be generated on the basis of past detected track crossing pulses; means for generating a timing signal defining respective expected time windows (WU, WD) within which said expected track crossing pulses are positioned; means (162, 164) for allowing the generated track crossing pulses to pass through as edges of the corrected track crossing signal ( TZC ) if those pulses are generated within their corresponding expected time windows (WU, WD); means for eliminating said generated track crossing pulses if they occur outside their corresponding expected time windows (WU, WD); and means for inserting said generated expected pulses (HFP, HNP) as edges of the corrected track crossing signal ( TZC ) when no track crossing pulses are generated within their respective expected time windows (WU, WD); characterized in that it further comprises zero-crossing detecting means (68, 84) for transforming said raw track error signal (TES) from said detector (56) into a raw track zero-crossing square wave (TZC), whereby [the] preceding edges of said square wave (TZC) are used to determine said time windows (WU, WD) and said expected pulses (HFP, HNP). A circuit as claimed in claim 5, wherein said zero-crossing detecting means (68, 84) comprises sequence control means having a first gate circuit allowing the generated track-crossing pulses (NP, FP) to pass therethrough as edge pulses for the corrected track crossing signal ( TZC ) while the window signal is active and a second gate circuit allowing the generated expected edge pulses (HFP, HNP) to pass therethrough as edge pulses for the corrected track crossing signal ( TZC ) when the detected edge pulse does not appear while the window signal (WU) is active. A circuit as claimed in claim 5 or 6, wherein the edges of the raw track crossing square wave (TZC), the expected pulses (HFP, HNP) and the expected time windows (WU, WD) include on-edges and off-edges of the raw track zero-crossing square wave, expected on-edge pulses and off-edge pulses, and expected time windows of on-edges and off-edges, respectively. A circuit as claimed in claims 5, 6 or 7, further comprising means for determining the speed of said head (14) by detecting time intervals between detected zero-crossings of the raw track zero-crossing square wave (TZC); and control means responsive to said speed determining means for : enabling the output of said generated expected pulse (HFP, HNP) inserting means if said head speed is above a predetermined limit; and inhibiting the output of said generated expected pulses (HFP, HNP) inserting means and causing said zero-crossing detecting means (68, 84) to pass through all of the edges of raw track zero-crossing square wave (TZC) as edges of the corrected track crossing signal if the seek speed is below said predetermined limit. A circuit as claimed in claim 5, 6, 7 or 8, wherein the expected pulses (HFP, HNP) and the expected time windows (WU, WD) are generated on the basis of past generated track crossing pulses that have been allowed to pass through. An optical disk drive for reading and/or writing on, an optical disk (10) having tracks, comprising : an optical head (14) generating a light beam irradiating the optical disk, receiving a light signal reflected from the optical disk, and converting the light signal into electrical signals, said electrical signals comprising a track error signal indicating a deviation of the irradiating position of the light beam from the tracks; actuator means (18, 82) for moving the irradiating position; servo means (22, 24) for driving the actuator means; and a circuit as claimed in any one of claims 5 to 9 for producing a corrected track crossing signals ( TZC ) from the raw track error signals (TES) from said optical head.

Inventors: TAKATA HIDEKAZU, YANAGI SHIGENORI, TAKATA, HIDEKAZU, YANAGI, SHIGENORI, Takata, Hidekazu, c/o Fujitsu Limited, YANAGI, SHIGENORI, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11B7
IPC codes: G11B7