Method and apparatus for manufacturing semiconductor devices

Abstract: A wafer(s) for producing semiconductor devices is subjected to heat treatment in a vertical thermal reactor, which is provided with an electric heating means (15) setting a first temperature and another electric heating means (15) setting a second temperature higher than the first temperature. The wafer(s) (2) is moved upwards and is subected to a treatment in the second region of the vertical thermal reactor (4); and, is reverted to the first region. Rapid thermal processing of 6 or 8 inch wafer(s) is possbile without causing slip lines.

Description: BACKGROUND OF INVENTION Field of Invention This invention is related to a method and apparatus for manufacturing semiconductor devices including Si devices, GaAs devices and TFT (thin film transistor). More particularly, the present invention relates to a technique which enables, by use of an electric vertical furnace, rapid thermal treatment. More specifically the present invention is related to a heating technique using a heating apparatus having simultaneous different temperature in the different sections along the axis of the electric vertical furnace and shortening the intermediate region between the high and low temperature regions by making the temperature gradient between these regions steep. Description of Related Arts In accordance with the development of semiconductor devices in recent years various heat-treatment techniques have been developed. These include such heat treatments as oxidation, diffusion, annealing, CVD and the like in the case of manufacturing ultra LSIs. A vertical or horizontal hot-wall type electric furnace has been used for the heat-treatments as described above. Meanwhile, along with larger scale integration and fine patterning of semiconductor devices, it is necessary to form a shallow junction and to suppress the re-distribution of impurities. In order to decrease the sum of total heat mass of the Si devices, rapid thermal treatment has been employed. The first described method using a hot-wall type electric furnace enables a batch treatment and has excellent temperature stability but involves difficulty in temperature-control. The second described method using a lamp-annealing furnace have advantages that a plurality of wafers can be treated, and, further the process-temperature can be controlled. This is therefore allegedly one of the most attractive methods in recent use. Regarding 64M-DRAMs, the pattern rule for manufacturing semiconductor devices is 0.35µm rule. In the manufacturing of such devices, a CVD oxide layer is formed as an inter-layer insulating beneath a B-PSG layer and the B-PSG layer is subjected to reflowing to flatten its surface. Total quantity of heat imparted to semiconductor devices is important for manufacturing 64M-DRAMs. Specifically, in the case of transistors produced by a conventional process, the sources and drains formed by the ion-implantation undergo a shape change when heat is imparted thereto at 850°C for 70 minutes or longer, so that characteristics of the transistors are impaired. Furthermore, monosilane could be used in the growth of CVD oxide film in the case of 16M-DRAM, whose pattern rule is 0.6 - 0.4µm, but could no more be used for 64M-DRAMs because a CVD oxide film is formed at 800 - 850°C, if retained for 60 - 120 minutes. In the manufacturing of 64M-DRAMs, a process frequently used comprises covering a polysilicon layer with a CVD oxide layer and forming a continuous B-PSG layer to be used as a flattening layer. The CVD oxide layer, which covers the polysilicon layer, prevents boron or phosphorous in the B-PSG layer from diffusing into the polysilicon layer. Thickness of the CVD-oxide layer required to attain this diffusion-preventing function is from 500 to 1000 angstroms. When an aluminum conductor layer is to be formed on the B-PSG layer, it is necessary to form a CVD oxide layer on the B-PSG layer after its reflowing. As is described hereinabove, a rapid thermal annealing method is appropriate for manufacturing semiconductor devices having a shallow junction. However, the lamp annealing method does not yet attain a temperature distribution on the wafer surface as uniform as that attained by an electric furnace. Therefore, when a wafer is subjected to the rapid thermal annealing method, thermal stress is caused under the temperature distribution provided by such a method and hence slip lines generate from the peripheral part of the wafer. Allegedly, the rapid thermal annealing method experimentally achieved success in the heat treatment of 6 inch wafers. However, even experiments, the slip lines are inevitably formed on the wafers, when the scale of the experiments is enlarged such that the number of wafers treated is comparable to that of mass production. In order to avoid the slip lines in mass production, the temperature elevating speed in a lamp-annealing furnace must be lowered to a significantly low level. Rapid-thermal processing of an 8-inch wafer, which must be used for the 16M or more DRAMs, is more difficult than that for 6-inch wafer. The rapid-thermal processing of an 8-inch wafer is hence not applied to an industrial production. A report is made in J. Vac. Sci, Technol. B. 8(6), Nov/Dec 1990, pp 1249-1259 (American Vacuum Society) that the rapid-heating annealing is tried by using a hot-wall type electric furnace including a silicon-carbide reaction tube. However, in the furnace reported in this journal a mere annealing is carried out. It is known that a high-temperature region and a low-temperature region are formed in a horizontal furnace, in which a number of wafers are subjected to diffusion sequentially in the above order. A number of wafers are carried on wafer holders successively connected with one another and are conveyed from one end to the other end of the furnace during diffusion. This diffusion method is in principle inappropriate for the formation of a CVD layer and rapid thermal annealing. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for manufacturing a semiconductor device, which method can apply a rapid thermal annealing to a large wafer with a diameter of 8 inch, and which realizes a clean process with is adaptable to various production processes of semiconductor devices. It is another object of the present invention to provide an apparatus for manufacturing semiconductor devices, which apparatus can be applied to a rapid-heating annealing of a large wafer with a diameter of 8 inch or more, and which realizes a clean process which is adaptable to various production processes of semiconductor devices. It is a further object of the present invention to provide a method and an apparatus for manufacturing semiconductor devices which can fulfill the objects described above and which can reduce particles generated during heat-treatment in the furnace. In accordance with the objects of the present invention, there is provided a method for manufacturing devices which is charcterized by the steps as set forth in claim 1. Preferred embodiments of this method are described in dependent claims 2-4. Also in accordance with the present invention an apparatus is provided which is characterized by the features as set forth in claim 5. Preferred embodiments of this apparatus are described in dependent claims 6-11. According to the present invention, the wafer subjected to the treatment in the second region is then reverted to the first region. The wafer may be held in the first region for any process or to adjust the temperature descending rate. The wafer may not be held in the first region but may be moved continuously through this region. n of the wafer to the first region is important for avoiding an abrupt temperature fall which may result in the formation of slip lines. The growth of a thin coating layer at a relatively low temperature may take place at a furnace temperature of approximately 700°C. Such growths are silicon dioxide from organic silane or disilane, or B-PSG layer from tetraethoxy silane (TEOS), tetramethoxy phosphorous (TMOP), tetramethoxy boron (TMOB) or tetramethoxy silicate boron (TMSB). The annealing or growth of a thin layer at high temperature comprises a heat treatment at approximately 850°C. It is for example the reflowing of the already formed layer or a conventional CVD for forming silicon dioxide using monosilane. Another feature provided by using two electric heating means for establishing the high temperature and low-temperature spaces in the vertical reactor resides in that: the temperature gradient realized between these spaces is gentle, so that a wafer can be quickly displaced into the high-temperature regions by means of elevating; a short-time process can be carried out in the high-temperature region; then, the wafer can be reverted to the low-temperature region immediately after the high-temperature process. As a result, a rapid thermal annealing can be carried out subsequent to the formation of the thin layer, which is one of the best embodiments of the present invention. The whole process as described above is clean. Thermal stability of an electric furnace has been actually verified by a vertical furnace. Rapid heating annealing of a large sized wafer with a diameter of 8 inch or more can be advantageously carried out without causing slip lines. As is described hereinabove, basically one wafer should be treated at one time. However, two or more wafers can be simultaneously treated, provided that they do not undergo heat history different from one another. A holding means for holding the wafers may not be specific but may be made of conventional quartz. The wafer holder is preferably rotated by a rotatable axis so as to ensure uniform temperature distribution on the wafer surface, as is carried out in a conventional vertical furnace. According to specific embodiments of the present invention, the following CVD methods can be carried out. Low temperature First region High temperature Second region Low temperature First region A. Growth of B-PSG Reflowing - B. Growth of silicon dioxide Growth of B-PSG C. Growth of silicon dioxide - Growth of B-PSG Reflowing - D. Growth of B-PSG Reflowing Growth of silicon dioxide E. Growth of silicon dioxide Growth of B-PSG Reflowing F. Growth of silicon dioxide Growth of B-PSG Reflowing Growth of silicon dioxide G. Sintering of Sputtered Ti to convert it to TiSi 2 RTP under N 2 atmosphere, or conversion of TiSi 2 by NH 3 to TiN In Item C, CAD for forming silicon dioxide and then growth of B-PSG are consecutively carried out in the low-temperature region. In Item E, growth of B-PSG and reflowing are carried out simultaneously in the high-temperature region. The reflowing mentioned in Items C through F can be carried out under condition of 850°C for 70 minutes (Condition 1). Under Condition 2 with temperature higher than Condition 1 by 50°C (900°C) the same diffusion depth of source and drain under Condition 1 is provided at a time one fifth as short as Condition 1, i.e., 14 minutes (840 seconds). The above mentioned reflow can be carried out at 900°C for 100 seconds (Condition 3). A wafer is preferably held or moved in a reaction tube in such a manner that the wafer is positioned vertical to direction of introduction into the reaction tube. A wafer may however be positioned slightly aslant of the direction of introduction. When the degree of rapid movement of wafers is low, they may be held or moved in a reaction tube in such a manner that the wafers are positioned parallel to the direction of introduction into the reaction tube. This parallel positioning enhances the treating efficiency. The present invention is hereinafter described with reference to the drawings. BRIEF DESCRIPTION OF DRAWING Fig. 1 illustrates an embodiment of the first apparatus according to the present invention and temperature distribution in this apparatus. Fig. 2 illustrates another embodiment of the first apparatus according to the present invention and temperature distribution in this apparatus. Fig. 3 illustrates a further embodiment of the first apparatus according to the present invention and temperature distribution in this apparatus. Fig. 4 illustrates a temperature gradient of the apparatus according to Fig. 3. Fig. 5 illustrates an embodiment of the first apparatus according to the present invention. Fig. 6 also illustrates an embodiment of the first apparatus according to the present invention. Fig. 7 illustrates an embodiment of the second apparatus according to the present invention. Fig. 8 illustrates an embodiment of the second apparatus according to the present invention. Fig. 9 illustrates an embodiment of the third apparatus according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 1, the heating means 15 comprising electric heaters are attached to surround an outer surface of a vertical quartz tube 4. The heating means 15 comprise four separate electric heaters. Although four separate heaters are shown in the drawing, one integral heater may be used, provided that it generates different temperatures. The vertical quartz tube 4 has an inlet at the top of the tube and gas is introduced from the inlet. The gas-introduction system is the one disclosed in United States Patent Application S.N. 07/611,386, the present inventor being one of the inventors of this application. The vertical quartz tube 4 abuts upon a susceptor 7 having a gas outlet. Basically a single wafer is mounted on the wafer holder 2 and the wafer holder 2 is set on a moving rod 6 which in turn is operably connected to a wafer-moving system comprising an outer tube 8, magnets 9, driving mechanism 10 and elevating mechanism 11 of the wafer holder. These components 7 - 10 are lowered as shown by the two-dot lines when the wafer is to be withdrawn from the vertical quartz tube 4. A heat-insulation tube is denoted by 5. A quartz tube for mounting the electric heaters is denoted by 14. The electric heaters 15 and the vertical quartz tube 4 are surrounded by the reflector 17. In a vertical reactor, reactant gas for CVD is generally introduced and withdrawn upwards, while gas used in diffusion, oxidation or heat treatment is generally introduced and withdrawn downwards. No matter which one of the directions of gas introduction and withdrawal is used, the electric heaters 15 are so designed that the temperature distribution rises successively in the vertical upward direction. When the heat mass of the whole processing apparatus is relatively small, and the electric heaters 15 are arranged with a space therebetween, stepwise temperature distribution is provided. An example of the stepwise temperature-distribution is shown in Fig. 1, that is, regions, in which temperatures of 500°C, 700°C, 900°C and 1100°C are maintained, are formed. Each region establishes a heating space, where the temperature in a wafer is stabilized. The temperature difference between the adjacent regions is determined depending upon the temperature elevating speed and the maximum temperature. When high heat-elevating speed and high maximum temperature are desired, the step is made great, that is, the difference in temperature between the adjacent regions is made greater. When the heat mass of the whole processing apparatus is relatively great, rapid heating of a wafer does not influence the temperature distribution in a processing reactor. In addition, although the electric heaters are spaced between one another, no stepwise temperature-distribution is formed between the electric heaters. Therefore in the case of a relatively great heat mass, the regions where the temperature is constant, are only two, e.g. at 500°C and 1100°C, as is shown in Fig. 2. An intermediate region between these regions has a gentle temperature- gradient. The processing apparatus as illustrated in Fig. 2 can be utilized for a process where the temperature-elevating speed may be low. In Fig. 3, there is shown an example of the first apparatus according to the present invention, which is the same as that shown in Fig. 2, except that the two electric heaters (included in the reactor body 1) are separated. The lower and higher electric heaters establish temperatures of 700°C and 850°C, respectively, as is shown in Fig. 4. An intermediate region is formed between these temperature levels, A wafer 2 is mounted on the wafer holder 3, whose heat mass is set low. The wafer 2 is positioned in a high temperature region and is annealed, while inert gas or nitrogen gas is introduced as is shown by an arrow in the right side of the drawing and is withdrawn as is shown by an arrow in the left side of the drawing. The high temperature region may have a temperature higher than 800°C, for example 950-1000°C. The low temperature region may have a temperature of 650-700°C. It was found that the intermediate region became as long as 400 - 800mm even in a processing apparatus, whose lower electric heater is omitted. In a processing apparatus with a lower electric heater the intermediate region becomes longer. If a plurality of wafers are heated at once, the intermediate region becomes longer than the above described value. When from ten to twenty five wafers are treated at once, their thickness amounting to from 150 to 250mm is added to the above mentioned 400 - 800mm, in each of the first and second regions, so that the total length of the processing apparatus becomes very long. As a result, the processing apparatus becomes very expensive and difficult to maintain and handle or install in a prevailing heat-treating room. In the first and second methods and apparatuses, the body of & vertical thermal reactor at the intermediate region is conventional and consists for example of a stainless steel sheet and refractory material. The body of a vertical thermal reactor at the intermediate region in the third method and apparatus is constructed such that the heat is positively absorbed. Such a construction may be one or a combination of the following methods: (1) forced cooling of the reactor body to absorb the convection heat, radiant heat and conduction heat attributable to both high and low-temperature electric heaters; (2) lessening the heat reflecting from a high-temperature region to a low-temperature region; and (3) constructing the furnace body to a cylindrical jacket with black plated inner surface for promoting the heat absorption. The heat-insulating zone provided with the heat shielding means may be provided with a gas-inlet and a gas-outlet, below and above said zone, respectively, so as to cool the heat-insulating zone with the gas admitted into the same through the gas-inlet. In the third method of the present invention, a wafer is moved through the intermediate region provided with the heat-shielding means for absorbing heat. Since the intermediate region is short, the third method is particularly appropriate for the rapid thermal annealing (RTP). According to a specific RTP method, a 6 inch wafer is subjected to a low-temperature heating of 500°C or 800°C and to a high-temperature of 750°C or 950°C in an upper high temperature region with a soaking length of 250mm, the length of intermediate region being 250mm. In the third method and apparatus according to the present invention, a heat-reflector plate is applied on the both ends of the heat-shielding means and, preferably, a heat-reflector film is applied on the heat-reflector plate. The heat-reflector plate and film reflect the heat from the electric heaters, thereby making the temperature gradient steep in the intermediate region and shortening its length. Gold is the most appropriate material for the heat-reflector film. Other metal having brightness can also be used without inconvenience. Heat radiation becomes prevailing in the heat transfer at a temperature of 800°C or more. Convection becomes prevailing at a temperature of 700°C or less. When it is intended to attain heating temperature of 800°C by the second electric heater and the desired low temperature by the first electric heater, and also attain desired temperature fall in the intermediate region as short as possible, it is necessary to effectively absorb the radiant heat. In addition, the gas convection makes the temperature gradient slow. It is therefore necessary to absorb the convection heat. The heat-shielding means is therefore provided between the first and second electric heaters. A method for producing a semiconductor device according to the present invention is hereinafter described with reference to Fig. 3. First, the wafer holder elevating system 11 and the magnets 9 for displacing magnets are lowered down to the lowest position as is shown by the two-dot chain line. One wafer 2 is taken out from the cassette (not shown in the drawing) for storing wafers and is placed on the wafer-holder 3. The wafer-holder elevating system 11 is then elevated to such a position that the wafer is situated in the region where the temperature is 700°C. The susceptor 7 is then abutted against the lower end of the quartz reaction tube 4 and they (7, 4) are tightly closed with respect to one another. Growth of a thin layer is carried out at the wafer position as described above. An example of such growth is the formation of a B-PSG layer using TEOS. When a B-PSG layer is to be formed on a 6-inch wafer, a source of TEOS, TMOP or TMOB, is maintained at a temperature of from 35 to 60°C, and nitrogen carrier gas is bubbled in and passed through the source and is then introduced into the quartz reaction tube, whose inner pressure is 0.3 torr. When the source gas is brought into reaction with a wafer at 700°C, a thin layer is caused to grown on the wafer at a rate of 100Å/minute. Subsequently, the magnets 9 for moving a wafer are driven to lift the wafer to a position as is shown in Fig. 3 where the temperature is 850°C. The wafer is then held at this temperature for 15 to 30 minutes. The magnets 9 for moving a wafer are then again driven to lower the wafer to the position where the temperature is 700°C. When the temperature of high-temperature region is 900°C, the wafer can be held in this region for 3 to 6 minutes. When the temperature of the high-temperature region is 950°C, the holding time of wafer in this region may be from 35 to 70 seconds. The total weight of wafer-holder 3 is kept so light that it can be advantageously quickly moved between the regions having temperature of 700°C and 850°C. The example as described above is the growth of a B-PSG layer on a wafer in the low-temperature region and annealing in the high-temperature region. Margin of the process parameters is broader for the case of heating one wafer than in a batch process, in which a plurality of the wafers are treated at once Therefore, a uniform layer can be formed on a wafer even at a temperature higher than 800°C. When N 2 O is added to silane or disilane, generation of particles is suppressed. When the boron concentration of the B-PSG is high, a B-PSG layer can be formed at a low temperature of from 820 to 850°C, while reflowing and flattening the B-PSG layer. The growth and reflowing of the B-PSG layer can therefore be carried out at high temperature side for a short period of time. The top end of the quartz reaction tube 4 is closed. That is, the end of the quartz reaction tube is located at the high-temperature region. This is one of the features of the present invention. A thin layer, which is formed at high temperature, is strongly adhered on the tube wall with the result that falling of particles from the tube wall onto the wafer surface is prevented. Fig. 5 is cross sectional view of another example of the vertical electric furnace. The features of this furnace is a dual tube type comprising a quartz reactor outer-tube 12 and a quartz reactor inner tube 13. The top of the vertical electric furnace shown in Fig. 5 is also closed at the top of the outer-tube 12. Fig. 6 is a cross sectional view of a yet another example of the vertical electric reactor, which is gold-furnace type comprising a quartz tube 14 for securing electric heaters, electric heaters 15, a water-cooled jacket 16, and a reflector 17. Heat ray is reflected from the reflector 17, so that the stepwise temperature-distribution can be easily realized. The top of the furnace is closed as well. The temperature distribution of the vertical electric reactor illustrated in Figs. 5 and 6 is the same as that shown in Fig. 3. The treatment in the former furnaces is the same as that in the latter furnace. Figs. 7 and 8 illustrate the second apparatus and a method for preventing the particles falling down and depositing ona wafer. The members of the electric furnace are denoted as follows: a reactor body including heaters - 21; upper electric heater - 22; a wafer-holder - 23; a quartz reactor-body - 24; a quartz heat insulating tube - 25; lower electric heater - 26; and, a quartz reaction tube - 27. The vertical thermal reactor having the structure of an electric furnace shown in Fig. 7 is a single-tube type having the following features. A space is formed between the lower electric heater 26 setting low temperature and the upper electric heater 27 setting high temperature to adjust the distance between the heaters 26, 27. The intermediate region corresponds to this space. Approximately twenty five wafers can be located in the inner space of the quartz reactor-body surrounded by each of the upper and lower electric heaters 22 and 26. A number of gas-exhausting holes 30 are provided as shown in the drawing in the intermediate region. Two gas inlets are provided as is shown in the drawing. The upper gas-inlet is used for introducing inert gas, while the lower gas-inlet is used for introducing reactant gas. The vertical thermal reactor utilizes a short inner tube located coaxially with respect to the quartz reaction tube 27 and ending at almost a half of this tube 27. Gas can be withdrawn from this vertical thermal reactor at the top of the short inner tube and through the ring-form clearance between the two tubes. Gas can therefore be withdrawn from the intermediate region formed between the higher and lower electric heaters, as in the case of the reactor shown in Fig. 7. The vertical thermal reactors shown in Figs. 7 and a can be used as follows. CVD Growth of PSG is carried out as follows. Wafers 2 are preliminarily set in a lower part of the vertical thermal reactors and is heated by the lower electric heater 26 to 680 - 750°C. TEOS and TMOP are kept in the sources at 60°C and are flown through the lower gas inlet at flow rate of for example, 2000cc/min in terms of overthrough for each of TEOS and TMOP. Inert gas, for example nitrogen gas, is flown through the upper gas-inlet at flow rate of for example 2000cc/min. Growth of B-PSG can be carried out by the above method, in which another reactant gas, i.e., TMB, is flown through the lower gas-inlet. Wafers, on which PSG or B-PSG is grown as described above, are immediately moved to the position of the upper electric heater 22 and are subjected to reflowing. Reflowing temperature of PSG is for example 1050°C. Diffusion from Glass Layer In order to deposit a layer containing impurities on the wafers, POCl 3 and O 2 are flown while the wafers are located at the position of the lower electric heater 26, the setting temperature of which may be 700 - 800°C. After the deposition, the wafers are moved to the position of the upper electric heater 22 and are then subjected to drive-in at temperature of 900 - 1100°C. Diffusion from Deped Polysilicon Wafers are located at the position of the lower electric heater 26, and polysilicon, in which one or more of phosphorous, boron, arsenic and antimony are doped, is deposited by a conventional growth method on the wafers. A reactant gas for the growth of polysilicon may be Si 2 H 6 . In this case, the growth temperature set by the lower electric heater 26 may be 500°C. A reactant gas for the growth of polysilicon may be SiH 4 . In this case, the growth temperature set by the lower electric heater 26 may be 610°C. After the growth, the wafers 2 are moved to the position of upper electric heater 22 and are subjected to the diffusion process of impurities at 900 - 1100°C. Referring to Fig. 9, an example of the vertical thermal reactor according to the present invention is illustrated. The elements 2, 7, 21 - 27 of the vertical thermal reactor denote the same elements as in Fig. 8. The heat-shielding means 36 has a cavity in the interior thereof to flow the cooling media, such as cooling water, compressed air, liquified gas or brine. The introduction conduit 32 and exhausting conduit 33 of the cooling media are attached to the heat-shielding means 36. The heat-shielding means 36 has a dual structure of stainless steel sheets which are bent to form therebetween a jacket for flowing the cooling media therethrough. Black plating may be applied on the inner surface of the heat-shielding means 6. In order to enhance the absorbing efficiently, the surface of the heat-shielding means 6 is increased. Radiant heat from the electric heater of the second region (the high-temperature region) passes across the reactor core and is then effectively absorbed by a portion of the heat-shielding means 36 located at the opposite side from the electric heater as seen from the reactor axis. Likewise, the convention heat is effectively absorbed by the heat-shielding means 36. Cooling water in the heat-shielding means is heated but is fed without interruption into the jacket so as to avoid the boiling of cooling water and to maintain effective heat-absorption. Although the cross sectional shape of the heat-shielding means 6 is semi-circular in the drawing, the shape is not limited to this one but the Japanese Katakana "J" shape can realize the same effects. Copper plates are assembled to form reflecting rings 4, 5, which have also jacket in the interior for flowing cooling water or the like. The conduits 11, 14 for introducing cooling water and outlets 11', 14' are attached to the reflecting rings 4, 5. An Au plating is applied on the copper sheets so as to enhance the reflecting ratio of convention heat. Radiant heat from the upper electrical heater is therefore reflected by the reflecting rings 4, 5 and is reverted into the second region (high-temperature region) of the vertical thermal reactor. Desirably, the reflecting rings 4, 5 should be protruded into the reactor interior as long as possible the structure of a vertical reactor permits. Length of the apparatus shown in Fig. 9 can be as short as 3m or less.

Claims: A method for manufacturing semiconductor devices by introducing a wafer or wafers into a vertical reactor from its lower end; characterized by: subjecting the wafer or wafers (2) to a first treatment in a first region of vertical thermal reactor (4) at a first temperature, which first region extending over a predetermined distance, heated by an electric heating means (15); moving the wafer or wafers (2) upwards from the first region to a second region which is heated by another electric heating means (15) and situated above the first region, extending over a predetermined distance and having a second temperature higher than the first temperature; subjecting the wafer or wafers (2) to a second treatment in the second region of the vertical thermal reactor (4); and, reverting the wafer or wafers (2) to the first region; and, occasionally, further comprising a third treatment, in which the wafer or wafers (2) are subjected to a heat treatment in a third region of the vertical thermal reactor (4), said third region being situated between said first and second regions, extending over a predetermined distance and having a third temperature higher the first temperature and lower than the second temperature; or a fourth treatment, in which the wafer or wafers (2) are heat treated in a fourth region of the vertical thermal reactor, said fourth region being situated between said first and third regions, extending over a predetermined distance and having a fourth temperature higher the first temperature and lower than the third temperature. A method for manufacturing semiconductor devices according to claim 1, further comprising steps of; moving the wafer or wafers (2) upwards from the first region to the second region through an intermediate region between the first and second regions, which intermediate region separating the first and second electric heating means (26, 22) from one another and generates a temperature gradient therein; and, withdrawing gas in the vertical thermal reactor for a port provided in the intermediate region or in at least one of the first and second regions in the vicinity of the intermediate region. A method for manufacturing semiconductor devices according to claim 2, wherein said temperature gradient is established by a means (36) for shielding and absorbing heat from both first and second electric heating means (26, 22). A method for manufacturing semiconductor devices according to claim 3, further comprising the steps of; introducing a gas into the first region from a first inlet near the introduction position of the wafer or wafer (2); and, introducing another gas into the second region from a second inlet, which is in an opposite position to the first inlet as seen in the vertical axis of the vertical thermal reactor. An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein, comprising: a reactor body (4) having a cylindrical outer surface portion being extending vertically and an open bottom end portion; a first electric heating means (15) for establishing a first region of the vertical thermal reactor, said first region extending over a predetermined distance and having a first temperature; a second electric heating means (15) for establishing a second region of the vertical thermal reactor, said second region situated above the first region, extending over a predetermined distance and having a second temperature higher than first temperature; and, a gas-inlet for introducing reaction gas or inert gas into an inner space of the reactor body, characterized by: setting the first temperature in said first region and a second temperature, in said second region, higher than said first temperature; and, further comprising a means (6, 8, 9, 10, 11) for moving the wafer or wafers (2) from said first region having the first temperature to said second regions having the second temperature and then from said second region to said first region and holding the wafer or wafers (2) in these regions for any processing. An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers (2) therein according to claim 5 further comprising: an intermediate region between the first and second regions, for separating the first and second electrical heating means (15) from one another, which region having an adjustable length; and, a port for withdrawing gas in the reactor body, formed through the body in the intermediate region or in the vicinity of at least one of the first and second regions. An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein according to claim 6, said intermediate region is provided with a means (36) for shielding and absorbing heat from both of said electric heating means. An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein according to any one of claims 5 through 7, wherein said reactor body has a closed top portion and an opening at said closed top portion. An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein according to claim 8, further comprising a conduit connecting said opening and placed along said outer surface of the reactor body (4). An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein according to any one of claims 5 through 9, further comprising a water-cooled jacket (16) positioned substantially coaxially with respect to said reactor body (4). An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein according to claim 7, wherein said heat-shielding and absorbing means (36) is a cavity formed in the intermediate region and cooling media flowing through the cavity. An apparatus for manufacturing semiconductor devices by processing one or more semiconductor wafers therein according to any one of claims 7 through 10, wherein a heat-reflector (34) is provided on the both end surfaces of the heat-shielding and absorbing means (36).

Inventors: TAKAGI MIKIO, TAKAGI, MIKIO
Applicants: F T L CO LTD, F.T.L. CO., LTD.
Application year: 1992
Main classification: C23C16
IPC codes: F27D3, H01L21, F27B17, C30B31, C23C16