Flash memory with improved erasability and its circuitry

Abstract: A substrate voltage control circuit comprises: a negative a negative-voltage source (860) for outputting negative voltage to a power line (V BS ) connected to a component whose voltage is controlled; a first n-channel transistor (867) whose substrate or well and source are connected to the power line (V BS ) and whose drain is connected to a ground power supply Vss; a second n-channel transistor (865) whose substrate or well and source are connected to the power line (V BS ) and whose drain is connected to the gate of the first n-channel transistor (867); a first switch (863) placed between the gate of the first n-channel transistor (867) and a positive power supply (Vcc); a second switch (864) for use in selecting whether the gate of the second n-channel transistor (865) is connected to the positive power supply (Vcc) or ground power supply (Vss), or opened; and a capacitative element (868) connected between the gate and source of the second n-channel transistor (865). When negative voltage is not to be applied, the negative-voltage source (860) is put into a non-output state, the first switch (863) is made, and the second switch (864) is connected to the ground power supply (Vss). When negative voltage is to be applied, the first switch (863) is opened, the second switch (864) is connected to the positive power supply (Vcc), and then the second switch (864) is opened, and the negative-voltage source (V BB ) is put into an output state.

Description: The present invention relates to a so-called flash memory or a nonvolatile semiconductor memory from which existent information can be electrically erased concurrently or block by block. In particular, this invention is concerned with improvements in erasing a flash memory and improvements in the associated circuitry. In recent years, a variety of semiconductor memories such as an electrically erasable programmable read only memory (EEPROM), which can be rewritten by electrically erasing data stored therein, have been developed in the field of nonvolatile memories. The semiconductor memories are nonvolatile memories which are made rewritable by electrically erasing specified data previously written therein. As for this kind of nonvolatile memory, in consideration of the use as a substitute for a magnetic storage or the like, efforts have been made to increase the capacity and decrease the cost. For use in a portable information processing terminal or the like, however, it is required to lower the voltage requirements. Known semiconductor memories, which are nonvolatile memories that are made rewritable by erasing specified data previously written therein, include an erasable programmable read only memory (EPROM) and the EEPROM. The EPROM has the advantage of a small cell size. However, data erasing is a nuisance because ultraviolet light must be used to erase data. As for the EEPROM, data erasing is easy to do because data can be erased electrically. However, the cell size in the EEPROM is larger than that in the EPROM, which makes it difficult to increase the capacity of an EEPROM. As a semiconductor memory having the advantages of the foregoing memories, for example, what is referred to as a flash memory has been developed. The term "flash memory" will be adopted in the succeeding description. The nonvolatile semiconductor memory has an overall configuration, for example, as that shown in Fig. 1. In Fig. 1, N cell blocks 11 1 to 11 N (for example, eight blocks) each having multiple transistor cells are arranged in a row. The cell blocks 11 1 to 11 N are provided with bit line select circuits 12 1 to 12 N and sense amplifiers/sense buffers 13 1 to 13 N respectively. A row address signal is supplied from a row address buffer to each of the cell blocks 11 1 to 11 N via a row decoder 15. A column address signal is supplied from a column address buffer 16 to each of the bit line select circuits 12 1 to 12 N via a column address decoder 17. A voltage V S sent from a source power supply circuit 18 is applied to each of source electrodes of the transistor cells of the cell blocks 11 1 to 11 N . Fig. 2 shows the cell block 11, one of the cells blocks in the aforesaid nonvolatile semiconductor memory, and its peripheral circuitry. In Fig. 2, components identical to those in Fig. 1 bear the same reference numerals, of which a description will be omitted. In Fig. 2, the bit line select circuit 12 comprises n-channel MOS field-effect transistors Q1 to Qn. Column address signals Yl to Yn are fed from the column decoder 17 to the gates of the transistors Q1 to Qn. The cell block 11 comprises a total of n by n field-effect transistors Q11 to Qnn having floating gates and control gates. The gates of n transistors Qil to Qin (where, i = 1, 2, etc., and n) arranged in tandem are provided with row address signals Xi sent from the row decoder 15 via word lines. The drains of the n transistors Qli to Qni arranged in tandem are connected to the drains of the transistors Qi in the bit line select circuit 12 via bit lines. Voltage from the source power circuit 18 is applied to each of the sources of the transistors Q11 to Qnn. A cell amplifier 13a and a write buffer 13b are connected to each of the sources of the transistors Q1 to Qn. In the foregoing semiconductor memory, when row addresses Xi and column addresses Yi are selected for writing, data read from the write buffer 13 are written in the transistors Qij of the cell blocks 11 1 to 11 N . Writing is performed simultaneously on one bit per each of the cell blocks 11 1 to 11 N or a total of N bits designated with the row addresses and column addresses. Data erasing is performed concurrently on all transistors in the cell blocks 11 1 to 11 N . In a flash memory, information is retained depending on the presence or absence of a charge in a memory cell. Fig. 3 shows an example of a structure of a memory cell. As shown in Fig. 3, a gate has a two-layered structure consisting of a control gate (CG) 25 and a floating gate (FG) 24. The control gate 25 is connected to a word line WLi and a drain (D) 23 is connected to a bit line BLi. Reference numeral 26 denotes a tunneling oxide film. The flash memory is broadly divided into two types of what are referred to as NOR and NAND. These types differ from each other in a method of writing, reading, or erasing information into or from a memory cell. Taking the NOR type flash memory as an example, writing, reading, or erasing information into or from a memory cell will be described below. When information is to be written in a memory cell having the aforesaid structure, as shown in Fig. 4, the word line WLi is set to Vpp (approx. 12 V), the bit line BLi is set to approx. 6 V, and the source S is set to 0 V. High voltage is then applied to the control gate CG and drain D. Current then flows into the memory cell. Part of the electrons flowing through the memory cell are accelerated due to the high electric field in the vicinity of the drain D, gain energy, and then goes beyond the energy barrier of an insulating film of the floating gate. The electrons are finally injected into the floating gate FG. The floating gate FG is not electrically coupled with other circuits, so it therefore can retain charges on a semi-permanent basis. When information is to be read from a memory cell, as shown in Fig. 5, the word line WLi is set to Vcc (about 5 V), the bit line BLi is set to about 1 V, and the source S is set to 0 V. The memory cell is then selected by specifying the word line WLi and bit line BLi. The threshold value of the cell transistor varies depending on the charges retained in the floating gate FG. Current flowing through the selected memory cell varies depending on the information stored therein. The information therefore can be read out by detecting and amplifying the current. The voltage levels of the control gate CG, drain D, source S, and substrate PS in the aforesaid operative states are set to the values listed in Table 1. Voltages in modes in a prior art CG D S PS Reading Vcc to 1 V 0 V 0 V Writing Vpp to 6 V 0 V 0 V Erasing 0 V Float Vpp 0 V When information is to be erased from a memory cell, as shown in Fig. 6, the word line WLi is set to about 0 V and the bit line BLi is opened. In this state, the drain D is opened, about 0 volt is applied to the control gate CG, and a high voltage of about 12 volts is applied to the source S. Since a high voltage is applied to the source S, deep diffusion is required in order to increase the resistivity of the diffused layer in the source. This hinders reduction in cell area. For divided erasing, it is required that the Vss line in the source must partly have a different voltage. This leads to disconnection or an increased number of drive circuits. Eventually, chip size increases. A solution to the above problem is to apply a negative voltage to the word line WLi. To be more specific, as shown in Fig. 7, a negative voltage (about - 10 V) is applied to the control gate CG and Vcc (about 5 V) is applied to the source S. The drain D is opened. Erasing is then executed. In this case, since a low voltage is applied to the source S, the resistivity of the source need not be intensified. This contributes to reduction in cell size. Partial erasing is enabled by selectively applying negative voltage to the control gates CG. The aforesaid erasing method is a source erasing method in which charges in the floating gate FG are routed to the source. A channel erasing method is also available, wherein charges in the floating gate are routed to a channel; that is, a substrate. Even in this method, negative voltage is applied to the control gate. The channel erasing method is sometimes employed for the aforesaid NAND-type flash memory. Figs. 8 to 11 show the states of a memory cell with voltage applied according to various erasing methods. In Figs. 8 to 11, the memory cell is an n-channel transistor. Fig. 8 shows a state in which positive voltage is applied according to a channel erasing method. The drain D and source S are opened, and the control gate CG is set to 0 V. The high voltage Vpp is applied to the P well equivalent to a channel. In channel erasing, a triple-well structure shown in Fig. 8 is adopted because positive bias is applied to the channel. Fig. 9 shows a state in which a positive voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to 0 V. The high voltage Vpp is applied to the source S. The substrate is opened or set to 0 V. Fig. 10 shows a state in which a negative voltage is applied according to the channel erasing method. The drain D and source S are opened, and the control gate CG is set to a negative voltage V BB . A positive voltage Vcc is applied to the p well equivalent to a channel. V BB - Vcc is applied between the control gate CG and channel. Fig. 11 shows a state in which negative voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to the negative voltage V BB . The source S is set to the positive voltage Vcc. For negative voltage erasing, bias voltage must be applied to a substrate or part of a well. Previously-proposed substrate bias circuits are realized with a p-channel depletion-type transistor. The manufacturing process is complex and downsizing is hard to do. Accordingly, it is desirable to realize a substrate (well) voltage control circuit that consumes limited power and can be downsized. According to an embodiment of an aspect of the present invention there is provided a substrate (well) voltage control circuit for use in a flash memory or the like. The substrate voltage control circuit comprises a negative voltage source for outputting a negative voltage to a power line connected to a component whose voltage is to be controlled, a first n-channel transistor whose substrate (well) and source are connected to the power line and whose drain is connected to a ground power supply, a second n-channel transistor whose substrate (well) and source are connected to the power line and whose drain is connected to the gate of the first n-channel transistor, a first switch installed between the gate of the first n-channel transistor and a positive power supply, a second switch for use in selecting whether the gate of the second n-channel transistor is to be connected to the positive power supply or ground power supply, or opened, and a capacitative element connected between the gate and source of the second n-channel transistor. When negative voltage is not applied, the negative voltage source is put into a non-output state, the first switch is closed, and the second switch is connected to the ground power supply. When negative voltage is to be applied, the first switch is opened and the second switch is connected to the positive power supply at the same time. Thereafter, the second switch is opened and the negative voltage source is put into an output state. In such a substrate (well) voltage control circuit, when negative voltage is applied, the gate-source voltage of the second n-channel transistor is held at a specified value owing to the charges retained in the capacitative element before switching is done. The second n-channel transistor therefore remains in the on state. The gate of the first n-channel transistor therefore assumes a negative voltage. The first n-channel transistor is then turned off. The power line is then disconnected from the ground power supply. A large voltage will not be applied between the gate and source of the second n-channel transistor, which obviates the need of improving resistivity, and downsizing becomes possible. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 shows an overall configuration of a flash memory in which the present invention is implemented; Fig. 2 is a circuit diagram showing a major section of Fig. 1; Fig. 3 shows a structure of a memory cell; Figs. 4 to 7 are explanatory diagrams for methods of reading, writing, and erasing a flash memory; Fig. 4 shows the conditions for writing; Fig. 5 shows the conditions for reading; Fig. 6 shows the conditions for erasing; Fig. 7 shows the conditions for erasing based on negative-voltage application; Fig. 8 is an explanatory diagram for channel erasing based on high-voltage application; Fig. 9 is an explanatory diagram for source erasing based on high-voltage application; Fig. 10 is an explanatory diagram for channel erasing based on negative-voltage application; Fig. 11 is an explanatory diagram for source erasing based on negative-voltage application; Fig. 12 shows a structure of a transistor cell; Fig. 13 is an explanatory diagram for excessive erasing; Fig. 14 shows a configuration for applying negative voltage to a word line using an independent negative power supply; Fig. 15 shows a functional structure of a row decoder when the row decoder applies negative voltage; Fig. 16 shows an example of a circuitry of a row decoder in a flash memory according to the fifth mode of the present invention; Fig. 17 shows an example of part of the circuitry in Fig. 36; Figs. 18 and 19 are diagrams for explaining problems occurring when negative voltage is applied to an example of a circuitry of a conventional row decoder; Figs. 20 and 21 show structures of a drive unit in a row decoder based on the fifth mode; Fig. 22 shows an example of a previously-proposed substrate (well) voltage control circuit; Fig. 23 shows other example of a previously-proposed substrate (well) voltage control circuit; Fig. 24 is a configurational diagram showing the principle of a substrate (well) potential control circuit embodying the present invention; Fig. 25 shows a substrate (well) voltage control circuit in the first embodiment; Fig. 26 is a timing chart showing the operations of the circuit in Fig. 25; Fig. 27 shows a substrate (well) voltage control circuit in the second embodiment; Fig. 28 shows an example of a structure of a previously-proposed substrate (well) voltage control circuit; Fig. 29 shows an example of a structure of the substrate (well) voltage control circuit in Fig. 27; Fig. 30 shows a substrate (well) voltage control circuit in the third embodiment; and Fig. 31 is a timing chart showing the control and operations of the circuit in Fig. 30. Prior to a description of the embodiments, pre-erase writing will be described. Fig. 12 shows a structure of a memory cell shown in Fig. 3 in more detail. A transistor serving as the memory cell has, as shown in Fig. 12, such a structure that n-type diffusive regions 32 and 33 are formed in a p-type substrate 31 with a certain space between them. A floating gate (FG) 34 and a control gate (CG) 35 are formed above the p-type substrate 31, and coated with an oxide film 36. The n-type diffusive regions 32 and 33 are coupled with a source electrode 37 and a drain electrode 39 respectively. The control gate 35 is coupled with a gate electrode 38. An insulating film for isolating between the floating gate (FG) and control gate (CG) in the stacked gate type memory cell transistor may be an oxide film or oxide nitride film. However, an ONO film; that is, a three-layered structure of an oxide film over a nitride film over an oxide film is preferred in an effort to prevent a time-sequential leakage of charges from the floating gate (FG). Using the same process for producing the insulating film between gate electrodes, an insulating film for a gate in a single gate-type transistor which is used in any region of peripheral circuits may be produced. In this case, the gate insulating film for the single gate-type transistor formed in a region of peripheral circuits may be the ONO film or oxide nitride film. The gate insulating films for transistors except memory cell transistors are not necessarily oxide films. Writing in a memory cell is achieved by injecting electrons into the floating gate (FG) 34, whereby "0" will be written. Erasing is achieved by removing electrons from the floating gate (FG) 34, whereby "1" will be written. When a source erasing method based on high-voltage application is performed to erase the transistor cell (to write "1"), as described previously, high voltage is applied to the source electrode 37, zero volt is applied to the gate electrode 38, and the drain electrode 39 is opened. The electrons retained in the floating gate 34 are thus removed. When "0" has been written in the transistor cell; that is, when electrons have been retained in the floating gate 34, the threshold for the cell, I, in Fig. 13 decreases to be lower than a threshold level for identifying data "1" for the period of an erasing time T. In contrast, when "1" has been written in the transistor cell; that is, when no electrons have been retained in the floating gate 34, since the threshold level is low, as the threshold of the cell decreases as indicated with II in Fig. 13 due to the erasing, the threshold level becomes 0 for a shorter period of time than the erasing time T. During the above erasing, too many electrons are removed from transistor cells in which "1s" have been written. The transistor cells consequently enter a Normally On state. In order to prevent the foregoing excessive erasing, it is necessary for a flash memory, in which cells are NORed, to write data "0" in each of the transistor cells in all cell blocks before concurrent erasing is performed. Writing data "0" is performed on all transistor cells, wherein the data values written in the transistor cells are not checked. Specifically, a source voltage Vs for the source electrode 37 in the transistor cell shown in Fig. 12 is set to 0 V, a gate voltage Vg for the gate electrode 38 is set to a high voltage, and a drain voltage V D for the drain electrode 39 is set to a high voltage. High-energy electrons developed by applying high voltage between the source and drain then reach the floating gate 84 through the oxide film 36. Data "0" is thus written in the transistor cell. As described previously, negative-voltage application in which negative voltage is applied to a control gate during erasing is helpful for downsizing a flash memory. Various methods are conceivable for application of negative voltage to a control gate; that is, application of negative voltage to a word line on which the control gate is connected. For example, a row decoder is used to apply negative voltage to a word line on which a memory cell that is to be erased is connected. Alternatively, a negative voltage source is connected to a word line, and a connection switch circuit is installed to operate complementarily to both pairs of a word line and a row decoder, and a word line and a negative voltage source. The switch circuit disconnects a negative voltage generator in either a write or read mode, and disconnects the row decoder for erasing. Fig. 14 shows an example of circuitry, wherein a negative-voltage generator 223 is installed on the opposite side of a row decoder 222 with a memory cell array 221 between them. The negative voltage generator 223 is connected to a word line WL i . P-channel transistors 224 and 225 are installed as disconnection switches between the row decoder 222 and memory cell array 221, and the memory cell array 221 and negative generator 223. To apply negative voltage selectively to word lines, a decoder similar to a row decoder must be installed in the negative voltage generator. The overall circuit thus becomes large in scale. To overcome this drawback, it is thought that a row decoder could be used to apply negative voltage to a word line. The row decoder applies a voltage indicated in Fig. 4 or 5 to a word line during writing or reading. Specifically, during writing, a high voltage Vpp is applied to a word line on which concerned memory cells are connected (selected word line), and a ground voltage Vss is applied to the other word lines (unselected word lines). About 6 V is applied to a selected bit line. Unselected bit lines are opened. Similarly, during reading, a positive voltage Vcc is applied to a selected word line, while a ground voltage Vss is applied to unselected word lines. About 1 V is applied to a selected bit line. Unselected bit lines are opened. In either case, the ground voltage Vss is applied to sources S. Memory cells are thus accessed independently. Information is then written into or read out from the memory cells. The row decoder selects a voltage to be applied to a word line from two supply voltages according to a row decode signal. The supply voltage must be changed from writing to reading. Specifically, a high voltage must be applied to a power terminal during writing, while a positive voltage must be applied during reading. The row decode signal to be fed to the row decoder is constant whichever mode is specified; a write or read mode. The row decoder has a level change function for changing a level of a signal to a different voltage level according to a select signal. The row decoder also applies negative voltage to a selected word line during erasing. For erasing, as shown in Fig. 7, drains D must be opened. A positive voltage Vcc must be applied to sources S, and a negative voltage V BB must be applied to control gates CG. Application of the negative voltage V BB to the control gates CG is performed block by block. The positive voltage Vcc is applied to the word lines in a block which are not subjected to erasing. In a flash memory, during reading or writing, a high voltage must be applied to selected word lines WLi, while a ground voltage'is applied to unselected word lines WLj (j ≠ i). During erasing, the selected word lines WLi must be set to a negative voltage, while the unselected word lines WLj must be set to a positive voltage. In short, the following formula is established for reading or writing: Voltage for selected word lines WLi > Voltage for unselected word lines WLj The following formula is established for erasing: Voltage for selected word lines WLi < Voltage for unselected word lines WLj The levels of the voltages must be reversed. For supplying negative voltage that is to be applied to a word line, a row decoder must have a conventional level change function as well as a level change function that can change levels between a negative voltage V BB and a positive voltage Vcc, and be able to reverse the levels of voltages to be applied to a word line according to the logic value of "selected" or "unselected." Fig.15 shows a functional structure of a row decoder for applying negative voltage to a word line. As illustrated, a row decoder 231 includes a decoding unit 232, a logic change unit 233, a level change unit 234, and a drive unit 235. The decoding unit 232 decodes a row decode signal RDC, and determines whether a word line connected to the row decoder 231 is selected or unselected. The drive unit 235 provides a large driving force for driving the word line. The decoding unit 232, logic change unit 233, and level change unit 234 except the drive unit can be arranged in any order. For example, the level change unit 234 may be located at a leading position. However, if the level change unit 234 is located at a leading position, the subsequent units must be able to operate at a voltage whose level has been changed. The logic change unit 233 may not be installed in the row decoder 231, but an address signal itself may be changed. In this case, a unit for changing the address signal is necessary. The row decoder for applying a negative voltage to a word line needs the foregoing functions, resulting in complex circuitry. Fig. 16 shows an example of a circuitry of a row decoder that is a main feature of a flash memory described in our copending European patent application publication EP-A-0961 289 Fig. 17 shows an example of a structure of a drive unit 245 shown in Fig. 16. Referring to these drawings, the basic components of such a flash memory will be described. Such a flash memory includes a memory cell array, and decoding units 241 for decoding multiple signals and accessing the memory cell array. The flash memory further includes drive units 247 each of which has a first power terminal 250 and a second power terminal 251, inputs an output of the decoding unit 241, and selectively outputs a voltage applied to the first power terminal 250 or a voltage approximate to the voltage, and a voltage applied to the second power terminal 251 or a voltage approximate to the voltage. The drive unit 247 assumes a first operation mode in which a first voltage is applied to the first power terminal 250 and a second voltage that is lower than the first voltage is applied to the second power terminal 251, and a second operation mode in which a third voltage is applied to the first power terminal 250 and a fourth voltage that is higher than the third voltage is applied to the second power terminal 251. Depending on whether the first or second operation mode is specified, output voltages are changed. In such a flash memory, the drive unit 247 in a row decoder performs a logic change. A logic change unit is thus eliminated. This realizes simpler circuitry. The drive unit 247 is designed to selectively output voltages V1 and V2 that are to be applied to the first and second power terminals 250 and 251. The levels of voltages to be applied to the first and second power terminals 250 and 251 are reversed depending on which operation mode is selected. The requirements for a drive unit to apply negative voltage to word lines will be described briefly. In Fig. 16, a level change circuit is arranged in front of the decoding unit 241 but not illustrated. Voltages V IH and V IN applied to the power terminals 245 and 246 of the decoding unit 241 vary depending on the level determined by the level change circuit. Voltages V1 and V2 are applied to power terminals 248 and 249 in the drive unit 250. The voltages V1 and V2 assume a high voltage Vpp and a zero voltage Vss respectively, a positive voltage Vcc and the zero voltage Vss respectively, or a negative voltage V BB and the positive voltage Vcc respectively depending on whether the writing, reading, or erasing mode is selected. In response to an input signal IDC, when the connected word line is selected, a signal ODC represents the voltage V IN . A p-channel transistor 248 is turned on. The voltage V1 is output from the power terminal 250. When the connected word line is unselected, an n-channel transistor 249 is turned on and the voltage V2 is output from the power terminal 251. The drive unit 247 has, as shown in Fig. 17, a dual-well structure. This structure resolves a problem that when negative voltage is applied to the power terminal 250 of the drive unit 247, a junction between a substrate and a diffused layer is forward-biased so that current flows and the output of a specified voltage is disabled. In Figs. 18 and 19, negative voltage is applied in an example of a structure of a drive unit in a previously-proposed flash memory that does not use a row decoder to apply negative voltage. Fig. 18 shows a structure based on a p-type substrate. Fig.19 shows a structure based on an n-type substrate having a p well. In Fig. 18, a p-type substrate is used and an n-type well is formed. In this case, if the voltage applied to the substrate itself decreases, the characteristics of portions operating at a normal voltage vary. This makes it impossible to apply negative voltage to only some portions, so a negative voltage generator must handle a heavy load. When an n-type substrate is used and a p-type well is formed, as shown in Fig. 19, negative voltage need be applied to only required portions of the p-type well. The above problem can thus be solved. However, the substrate bias of a p-channel transistor cannot be set partly to Vpp for writing. To avoid the above problems, the drive unit 247 for negative-voltage driving must have any of the following structures: (a) as shown in Fig. 20, a p-well region is formed within an n-well region on a p-type substrate, and an n-channel MOS transistor is formed in the p-well region; (b) as shown in Fig. 21, an n-well region is formed within a p-well region on an n-type substrate, and a p-channel MOS transistor is formed in the n-well region; or (c) a p-channel transistor and an n-channel transistor are formed on an insulating substrate and a p-well region is biased negatively, which is a silicon-on-insulator (SOI) structure. These structures enable application of negative voltage to a control gate CG of a memory cell. A drive unit can have any of the above structures, which enables a row decoder to perform negative-voltage application. As apparent from the previous description, in a semiconductor memory such as a flash memory, bias voltage is applied to a substrate or well. The present invention relates to a substrate (well) voltage control circuit. When a row decoder is used to apply negative voltage, as described previously (See Figs. 18 and 19), the substrate or well of a drive unit is biased with negative voltage in order to prevent forward-bias current from flowing between a diffused layer and the substrate or well. However, during writing or reading, the substrate or well is set to a supply voltage Vss because negative voltage is not used. A circuit shown in Fig. 22 has been used as a control circuit for the foregoing substrate (well) voltage in the past. In the circuit shown in Fig. 22, V BS denotes a substrate (well) voltage line. A p-channel depletion-type transistor 842 is employed to switch the voltage to be applied to the substrate (well) voltage line V BS from a negative voltage V BB provided by a negative voltage source 840 to a zero (ground) voltage Vss. When the gate voltage of the transistor 842 is switched between the normal supply voltage Vss and Vcc, voltages to be applied to the substrate voltage line Vss are changed. When the zero voltage Vss is placed on the substrate power line V BS , the negative voltage source 840 becomes inoperative and does not output the negative voltage V BB . In the circuit shown in Fig. 22, the p-channel depletion-type transistor 842 is used to switch supply voltages. When the threshold voltage Vth of the transistor 842 is set to an intermediate value between the zero voltage Vss and positive voltage Vcc, if a control signal G is high (Vcc, the transistor 842 is off. If the control signal is low (Vss), the transistor 842 is on. Table 2 shows a truth table for the circuit in Fig. 22. Truth table for the circuit in Fig. 22 G Transistor 842 V BS Negative-voltage generator Vss On Vss No output Vcc Off V BB Output The control circuit for a substrate (well) voltage shown in Fig. 22 has the advantage of a simple circuitry but poses the following problems: (1) Another process is needed to manufacture a p-channel depletion region, resulting in complex processes; (2) The threshold voltage Vth of a p-channel depletion-type transistor must be controlled precisely, resulting in demanding process management; (3) A p-channel transistor is larger in area than an n-channel transistor, resulting in a large-scale circuit; and (4) When the negative voltage V BB is applied to the substrate (well) power line V BS , the positive voltage Vcc is applied to the gate of the transistor 842. A difference between the positive voltage Vcc and negative voltage V BB is therefore applied between the gate and drain of the transistor 842. This increases an applied voltage, making it necessary to intensify the resistivity . between the gate and drain of the transistor 842. To intensify the resistivity, the gate oxide film must be made thicker. This results in an increased area. A circuit shown in Fig. 23 has been employed as a substrate (well) voltage control circuit using no p-channel depletion-type transistor in the past. Table 3 is a truth table for the circuit in Fig. 23. Truth table for the circuit in Fig. 23 G1 Node 91 Transistor 852 Transistor 853 Transistor 854 V BS Vcc V BB Off On Off Vss Vss Vcc On Off On V BB The circuit shown in Fig. 23 uses enhancement transistors alone. Another process is therefore unnecessary. When the substrate (well) power line V BS is set to the zero voltage Vss, the voltage at a point n91 must be held negative. To achieve this purpose, the negative voltage source 850 must output negative voltage all the time. The negative voltage source 840 must therefore be operative all the time. This results in increased power consumption. The above problem (3) of a large-scale circuit and problem (4) that a high resistivity is needed are not resolved. As mentioned above, a previously-considered substrate (well) voltage control circuit has such problems as a large chip area, a large power consumption in a standby state, and complex manufacturing processes. A circuit without these problems has been awaited. Fig. 24 is a configurational diagram for the principle of a substrate (well) voltage control circuit embodying the present invention which solves the above problems. As shown in Fig. 24, a substrate (well) voltage control circuit embodying the present invention comprises a negative voltage source 860 for outputting negative voltage to a power line V BS connected to a component whose voltage is to be controlled, a first n-channel transistor 867 whose substrate or well, and source are connected to the negative power line V BS and whose drain is connected to a power supply for outputting a zero voltage Vss, a second n-channel transistor 865 whose substrate or well and source are connected to the negative power line V BS and whose drain is connected to the gate of the first n-channel transistor 867, a first switch 863 placed between the gate of the first n-channel transistor 867 and a power supply for outputting a positive voltage Vcc, a second switch 864 for selecting whether the gate of the second n-channel transistor 865 is connected to the power supply for outputting the positive voltage Vcc or the power supply for outputting the zero voltage Vss, or opened, and a capacitive element 868 connected between the gate and source of the second n-channel transistor 865. When negative voltage is not applied, the negative voltage source 860 is put into a non-output state, the first switch 863 is closed, and the second switch 864 is connected to the zero-voltage terminal. When negative voltage is applied, the first switch 863 is opened. The second switch 864 is connected to the positive-voltage terminal at the same time. Thereafter, the second switch 864 is opened, and the negative voltage source 860 is put into an output state. Table 4 is a truth table for Fig. 24. Under the control shown in Table 4, the voltage at a point n101 at which negative voltage is applied is held at Vcc with respect to the substrate (well) of the transistor 865 owing to charges retained in the capacitive means C. The on state of the transistor 865 is maintained without a large potential difference. The switching transistor 867 is turned off. When the zero voltage Vss is applied, the transistor 865 is turned off, and the transistor 867 is turned on. The substrate (well) power line is then set to the zero voltage Vss. The circuit in Fig. 24 can be composed of enhancement transistors alone, which therefore is small in scale and has no problem concerning resistivity. Fig. 25 shows a circuitry of the first embodiment embodied according to the configurational diagram showing the principle of the circuit in Fig. 24. Fig. 26 and Table 5 indicate the operations of the circuit. Fig.26 shows voltage fluctuations at components, and Table 5 is a truth table. The step numbers of state transition in the truth table correspond to those on the temporal axis of the graph in Fig. 26. In the circuit of Fig. 25, the first switch 863 of Fig. 24 is realized by switching source voltages of a p-channel transistor 877. The circuit further includes a p-channel transistor 875 and an n-channel transistor 876, together serving as the second switch 864 shown in Fig. 25, that are connected in series with each other between a positive power supply Vcc and a zero voltage source Vss and that are used to make or break the second switch 864 and to switch voltages for the terminal of the second switch 864. The gates of the transistors 875 and 876 serve as control terminals which are controlled with amplitude signals G1 and G2 that are a positive voltage Vcc and a zero voltage Vss. Reference number 870 denotes a negative voltage generator, which generates negative voltage with complementary clock signals received through terminals o and /o. A transistor 878 has a large driving capacity for driving a power line V BS . The operations of the circuit in Fig. 25 will be described in conjunction with Fig. 26 and Table 5. During the first period, the signals G1 and G2 are driven high. A voltage signal S3 applied to a terminal 871 is then changed to Vss. The voltage at a node n101 is then driven high; that is, boosted to Vcc. A transistor 879 is turned on. The transistor 877 is turned off because the signal S3 is changed to Vss. The voltage at a node n102 is then driven low; that is, decreased to Vss. The transistor 878 is then turned off. During the third period, the level of the signal G1 is changed to high. The negative voltage generator 870 then starts operating. The node n101 is then disconnected. The voltage of the power line V BS drops toward V BB during the fourth and fifth periods. The voltage at the node n101 also decreases because the node n101 is connected to the power line V BS via a capacitor 880. In the meantime, the transistor 879 is on, the voltage at a node n102 decreases, and the transistor 878 remains off. The voltage at the node n101 remains higher by a voltage determined by charges retained in the capacitor 880 than that on the power line V BS , and decreases with a voltage drop on the power line V BS . However, when the voltage at the node n101 becomes slightly negative with respect to Vss and reaches the threshold voltage of the transistor 876, the voltage does not decrease any longer. The sixth period correspond to a duration of generative voltage application, during which the signal G2 is driven high. When negative voltage application terminates, the generative-voltage generator 870 stops operating. The voltage signal S3 applied to the terminal 871 is changed to Vcc. The transistor 877 is then turned on, and the voltage at the node n102 starts rising. Accordingly, the voltage on the power line V BS starts rising. At this time, the voltage at the node n101 is Vss. The transistor 879 is therefore off. When the voltage at the node n102 rises, the transistor 878 is turned on and the power line V BS is connected to the zero voltage source Vss. Fig. 27 shows a circuitry of a substrate (well) voltage control circuit of the second embodiment. The circuit of the second embodiment is substantially the same as that shown in Fig. 25 except that the source of the transistor 877 is fixed to a power supply for outputting a positive voltage Vcc and the gate voltage of the transistor 877 is controlled. An operation different from that of the circuit in Fig. 25 is that the voltage applied to the source of the transistor 877 is not changed to Vss but the transistor 877 is turned off. Except for this point, the circuit in Fig. 27 operates identically to that in Fig. 25 Table 6 is a truth table for the operations of the circuit in Fig. 27. For realizing the circuit in Fig. 27, a triple-well structure shown in Fig. 28 may be employed to prevent occurrence of forward bias current between a substrate or well and a diffused layer. For the circuit in Fig. 27, an n-substrate p-well structure shown in Fig. 29 can be employed. In the aforesaid first and second embodiments, a capacitor is used as shown in the configuration diagram showing the principle of a circuit in Fig. 24 in order to prevent the gate-source voltage of the transistor 865 from exceeding a specified value (Vcc). This obviates the need of intensifying the gate-source resistivity. Even when the gate voltage is controlled without using a capacitor, the same advantage is available. An example is presented in the third embodiment. Fig. 30 shows a circuitry of a substrate (well) voltage control circuit of the third embodiment. Fig. 31 shows control signals supplied by the substrate (well) voltage control circuit and voltage fluctuations on a power line V BS . The circuit in Fig. 30 has substantially the same circuitry as the one in Fig. 24 except that the capacitative means 868 is excluded. Reference numerals 891 and 892 denote control terminals. Signals A and B whose logical levels are Vss and Vcc are applied to the control terminals 891 and 892. The operations of the circuit in Fig. 30 will be described in conjunction with the graph in Fig. 31. As shown in Fig. 31, during Vss application, the signal A is set to Vcc and the signal B is set to Vss. The p-channel transistor 893 is turned on, and the n-channel transistor 895 is turned off. The gate voltage of the transistor 894 therefore becomes Vcc. The transistor 894 is turned on. Vss is then output to the power line V BS . During V BB application, the voltage of the signal A is switched to Vss and the voltage of the signal B is switched to Vcc. This causes the transistors 893 and 894 to turn off, and the transistor 895 to turn on. When the negative-voltage generator is actuated, the voltage on the power line V BS decreases gradually. When the voltage becomes lower than the threshold voltage of the transistor 895, the signal B is changed to Vss. The transistor 895 is still on. The voltage on the power line V BS decreases. Even when the voltage on the power line V BS decreases to be V BB , the gate-source voltage of the transistor 895 is Vss - V BB ; that is, - V B which is much lower than that in previously-considered circuitry. As described above, the substrate (well) voltage control circuits in the first to third embodiments do not use any depletion-type transistors. Another manufacturing process is therefore unnecessary. An area occupied by n-channel transistors is smaller than the one occupied by depletion-type transistors. Furthermore, resistivity improves. Downsizing of devices and reduction in the number of processes realize upgrading of a yield, improvement of reliability, and cutting of costs. Flash memories are expected to substitute for magnetic storages. For use in portable equipment on behalf of magnetic storages, in particular, the properties of flash memories; that is, small size and light weight will prove very helpful. For actual use in portable equipment in place of magnetic storage, the flash memory must further be innovated to achieve downsizing, an increase in operational speed, reduction in power consumption, and decrease in voltage requirements. Embodiments of the present invention provide innovative flash memory and solve some of the problems obstructing the widespread use of the flash memory.

Claims: A substrate voltage control circuit, comprising: a negative-voltage source (860) for outputting negative voltage to a power line (V BS ) connected to a component whose voltage is controlled; a first n-channel transistor (867) whose substrate or well and source are connected to said power line (V BS ) and whose drain is connected to a ground power supply Vss; a second n-channel transistor (865) whose substrate or well and source are connected to said power line (V BS ) and whose drain is connected to the gate of said first n-channel transistor (867); a first switch (863) placed between the gate of said first n-channel transistor (867) and a positive power supply (Vcc); a second switch (864) for use in selecting whether the gate of said second n-channel transistor (865) is connected to said positive power supply (Vcc) or ground power supply (Vss), or opened; and a capacitative element (868) connected between the gate and source of said second n-channel transistor (865) ; wherein when negative voltage is not to be applied, said negative-voltage source (860) being put into a non-output state, said first switch (863) being closed, and said second switch (864) being connected to said ground power supply (Vss); and when negative voltage is to be applied, said first switch (863) being opened, said second switch (864) being connected to said positive power supply (Vcc), and then said second switch (864) being opened, and said negative-voltage source (V BB ) being put into an output state. A substrate voltage control circuit according to claim 1, wherein said second switch (864) consists of a p-channel transistor (875) and an n-channel transistor (876) which are connected in series with each other between said positive power supply (Vcc) and ground power supply (Vss); and changes states of connection depending on signals applied to the gates of the p-channel transistor (875) and n-channel transistor (876). A substrate voltage control circuit according to claim 1 or 2, wherein said first switch (863) is a p-channel transistor (877). A substrate voltage control circuit, comprising: a negative-voltage source (870) for outputting negative voltage to a power line (V BS ) connected to a substrate or well; a first n-channel transistor (878) whose substrate or well and source are connected to said power line (V BS ) and whose drain is connected to a ground power supply (Vss); a second n-channel transistor (879) whose substrate or well and source are connected to said power line (V BS ) and whose drain is connected to the gate of said first n-channel transistor (878); a first gate voltage source (871,877) for selectively applying the voltages of a positive power supply (Vcc) and a ground power supply (Vss) to the gate of said first n-channel transistor (878); a switch (875,876) for selecting whether the gate of said second n-channel transistor (879) is connected to said positive power supply (Vcc) or ground power supply (Vss), or opened; and a capacitative element (880) connected between the gate and source of said second n-channel transistor (879); wherein when negative voltage is not to be applied, said negative voltage source (870) being put into a non-output state, said first gate voltage source (871,877) outputting the voltage of said positive power supply (Vcc), and said switch (875,876), to said ground power supply (Vss); and when negative voltage is to be applied, said first gate voltage source (871,877) being changed to output the voltage of said ground power supply (Vss), said first switch (875,876) connecting the gate of said second n-channel transistor (879) to said positive power supply (Vcc), and then said switch (875,876) being opened and said negative-voltage source (870) being put into an output state. A substrate voltage control circuit according to any of claims 1 to 4, wherein said first and second n-channel transistors (878 and 879) are formed in a p-well region on an n-type substrate. A flash memory including a substrate voltage control circuit claimed in any of claims 1 to 5.

Inventors: AKAOGI TAKAO, HAGIWARA RYOJI, ITANO KIYOSHI, KASA YASUSHI, KAWAMURA SHOUICHI, KAWASHIMA HIROMI, OGAWA YASUSHIGE, TAKEGUCHI TETSUJI, AKAOGI, TAKAO, HAGIWARA, RYOJI, ITANO, KIYOSHI, KASA, YASUSHI, KAWAMURA, SHOUICHI, KAWASHIMA, HIROMI, OGAWA, YASUSHIGE, TAKEGUCHI, TETSUJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11C16
IPC codes: G05F3, G11C16