Semiconductor integrated circuit having clock signal generator

Abstract: A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator (20), a divider (14), a phase comparator (15), and an up-down counter (16). The ring oscillator (20) provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider (14) divides the oscillation frequency from the ring oscillator (20) by a specified number. The phase comparator (15) compares the frequency of the signal from the divider (14) with the frequency of the external clock signal (S fe ). The up-down counter (16) controls the oscillation frequency of the ring oscillator (20) based on the comparison result from the comparator (15). The clock generator is controlled by an external clock signal (S fe ) to generate an Internal clock signal (S fc ) having a higher frequency and outputs both signals. By use of a digital integrated circuit technology alone, it becomes possible to include slow operating semiconductor elments and fast operating semiconductor elements on the same circuit chip without sacrificing the excellent characteristics of the latter.

Description: Field of the Invention: The present invention relates to a semiconductor integrated circuit in accordance with the precharacterizing part of claim 1. Such a semiconductor integrated circuit is known from Patent Abstracts Of JAPAN vol. 14, no. 312 (E-948) 5 July 1990 and JP-A-2100514 (RICOH CO LTD) 12 April 1990. Description of the Prior Art: As already known, semiconductors constituted by using compounds consisting of two or more elements such as GaAs, InP, AlGaAs and InGaAs have come into use these days. As compared with widely used Si semiconductors, these compound semiconductors provide high-speed operations, having particular utility in ultra high-speed and high-frequency devices. However, while realizing high-speed operations, compound semiconductors present such shortcomings as having many crystalline defects caused by the electronic instability on crystalline surfaces, a low mechanical strength, and a high production cost. These shortcomings make it difficult to provide all circuit elements necessary for constituting a circuit by using only compound semiconductors. Therefore, compound semiconductors are often used to supplement Si semiconductors in providing the characteristics which cannot be obtained from Si semiconductors alone. For these reasons, a combination of compound semiconductors and Si semiconductors are sometimes used on the same substrate constituting a circuit. To operate an entire circuit consisting of both compound semiconductors and Si semiconductors with a single clock signal, the clock signal must have a frequency suitable for driving the Si semiconductors which operate more slowly than the compound semiconductors on the same circuit, thereby making it impossible to make the most of the excellent characteristic of the compound semiconductors, namely a high-speed operation. A possible means for overcoming this problem to fully derive the advantage of the compound semiconductors is to operate the compound semiconductors and the Si semiconductors on the same circuit with separate clock signals. To generate the clock signal for driving the compound semiconductors, control must be provided so that this clock signal is put in a certain relationship with the clock signal for driving the Si semiconductors. A circuit for generating a clock signal in a certain relationship with another clock signal is generally comprised of a PLL circuit which consists of a phase comparator 1, a loop filter 2, a voltage controlled oscillator 3, and a l/N divider 4 as shown in Fig. 1. However, the PLL circuit shown in Fig. 1 is an analog circuit, making it impossible to constitute the entire clock signal generating circuit by the digital integrated circuit technology alone. Consequently, integrating a circuit including a clock signal generator has heretofore required a complicated process. The above mentioned Patent Abstracts of JAPAN vol. 14, no. 312 (E-948) 5 July 1990 and JP-A-2100514 (RICOH CO LTD) 12 April 1990 discloses control means to control highly precise integrated delay line. This document comes rather close to the prior art described above in regard of Fig. 1 of the application although it is directed to a different purpose. This document discloses a PLL circuit wherein the oscillation frequency obtained by a ring oscillator is divided by a programmable number, phase compared to a reference frequency and fed back in a loop to a voltage regulator controlling the ring oscillator. The voltage regulator and the ring oscillator thus correspond to the voltage controlled oscillator 3 in Fig. 1 mentioned above. It has, however, the same shortcomings since it is also an analog circuit. Patent Abstracts Of JAPAN vol. 7, no. 103 (E-173) 6 May 1983 and JP-A-58025710 (FUJITSU K.K.) 16 February 1983 discloses a variable frequency oscillator wherein a desired oscillation frequency is adjusted by selectively varying in an integrated circuit the number of digital delay elements connected in series in the delay loop of a ring oscillator. The digital delay elements are arranged in form of plural rows having each a different number of gates. One of said plural rows is selected responsive to a selecting signal controlled by a value obtained by a counter used for dividing the output frequency of the ring oscillator, thereby constituting a feedback loop. However, the functioning of the select signal generator is not detailed in the abstract. Further, this document does not show a phase comparison of an output frequency with an externally applied clock frequency and to control the output frequency in a certain relationship with an external clock signal. In this document the arrangement of plural rows of gates to be selected increases the integration area of said known variable frequency oscillator. Patent abstracts of JAPAN vol. 10, no. 117 (E-400) 2 May 1986 and JP-A-60250712 (Toshiba K.K.) 11 December 1985 shows another example of controlling the frequency of a ring oscillator by changing the number of its digital stages, specifically an odd number of inverters by means of switching elements responsive to frequency control signals. In this known circuit, four kinds of frequency levels can be generated and selected by said frequency control signals, but not controlled in a certain relationship with a clock signal applied from the outside. EP-A-0 357 527 describes an all digital count-locked-loop (CLL) timing generator which automatically adjusts its output pulse intervals to fit within the duration of periodic input pulses by using a direct digital feedback loop. The intervals are always synchronous with the leading edges of the input pulses and their number within the duration of the periodic input pulses is selectable in increments of 1. Responsive to the width of an input pulse, synchronizing logic gates a train of clock pulses provided by an oscillator to a divide-by-N first counter also receiving a signal of value N from a second counter. The digital feedback loop is closed by a third N-counter and a magnitude comparator receiving a reference interval count number on its second input. The second N-counter is incremented, decremented or left as it is according to the result of the comparison. In this way the divide-by-N counter is automatically conditioned by way of the digital feedback loop consisting of the third counter, the magnitude comparator and the second (N)-counter to adapt its terminal count timing to the input pulse duration. Thereby a time generator has an extended dynamic range which can be increased to accommodate different input pulse width. However, the pulse intervals of the output pulses within one input pulse width of said known digital count-locked-loop timing generator are constant and determined by a number (B) of intervals (programmed input signals) so that their frequency is predetermined, fixed and cannot be regulated according to an externally applied clock signal. OBJECT AND SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide by the digital integrated circuit technology alone a clock signal generator which generates a high-frequency clock signal controlled in a certain relationship with the clock signal given from the outside. According to an essential aspect the present invention provides a semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator providing at its output terminal oscillating frequencies determined by a sum of the delay times provided by circuit elements connected in series in said ring oscillator; a frequency divider coupled to said output terminal of said ring oscillator and dividing the oscillation frequency provided at said output terminal of said ring oscillator by a specified number; a phase comparator coupled with an output signal of said divider and comparing the frequency of said output signal from said divider with a frequency of a clock signal, characterized in that an up-down counter is provided generating a switching signal for selecting a number of said circuit elements of said ring oscillator and thereby said sum of the delay times provided by said circuit elements thereby controlling the oscillation frequency of said ring oscillator based on a comparison result on said phase comparator, and said ring oscillator includes selectors connected in series with said circuit elements and switched by said switching signal of said up-down counter so that the oscillation period of said ring oscillator is regulated to be lower than the oscillation period of said externally entered clock signal by said specified number, wherein said clock signal generator is controlled by said externally entered clock signal to generate its internal clock signal, the frequency of which is higher than the frequency of said externally entered clock signal by said specified number (claim 1). In an advantageous development, said clock signal generator comprises a clock regulator outputting both said externally entered clock signal and said internal clock signal of said higher frequency. A further advantageous development provides said semiconductor integrated circuit which is composed of both compound semiconductors and Si semiconductors. Each of the ring oscillator, the divider dividing the oscillation frequency from the ring oscillator by a specified number, the phase comparator for comparing the frequency of the output signal given from the divider with the frequency of the external clock signal given from the outside, and the up-down counter for controlling the oscillation frequency of the ring oscillator based on the comparison result from the phase comparator can be constituted by using the digital integrated circuit technology alone. Therefore, comprising a clock signal generator with these circuit elements makes it possible to provide, by the digital integrated circuit technology alone, a circuit which generates a high-frequency internal clock signal controlled by an external clock signal having a lower frequency. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a block diagram illustrating an example of a prior art clock signal generating circuit; Fig. 2 is a block diagram illustrating of a semiconductor integrated circuit practiced as a first embodiment of the present invention; Fig. 3 is a block diagram illustrating an example of the phase comparator on the semiconductor integrated circuit practiced as the first embodiment of the present invention shown in Fig. 2; Fig. 4 is a timing chart illustrating the phase lead operation of the phase comparator on the present invention shown in Fig. 3; Fig. 5 is a timing chart illustrating the phase lagging operation of the phase comparator on the present invention shown in Fig. 3; and Fig. 6 illustrates a clock signal generating circuit practiced as a second embodiment of the present invention as applied to a circuit constitution in which both low-speed and high-speed integrated circuits exist at the same time. DESCRIPTION OF THE PREFERRED EMBODIMENTS: Fig. 2 is a block diagram of a semiconductor integrated circuit practiced as the preferred embodiment of the invention. Referring to Fig. 2, the semiconductor integrated circuit of the present embodiment is constituted a ring oscillator 20, a divider 14, a phase comparator 15, and an up-down counter 16. The ring oscillator 20, consisting of first, second, and third selectors 11, 12, and 13, first, second, and third delay circuits 21, 22, and 23, and inverters 17, 18, and 19, oscillates at a frequency determined by a sum of the delay times provided by these delay circuits, the frequency being varied by a three-bit switching signal applied to the selectors 11, 12, and 13. In the embodiment, the delay times provided by the delay circuits 21, 22, and 23 are set to τ , 2τ , and 4τ , thus making it possible to vary the oscillation period of the ring oscillator 20 from t to (t + 7τ ) at an interval of τ by the switching signal. That is, the oscillation frequency can be varied from 1/t to 1/(t + 7τ ). Note that the interval t is the period provided by making the ring oscillator 20 operate in the mode in which the clock signal does not pass through all the delay circuits 21, 22, and 23. The delay circuits 21, 22, and 23 for varying the oscillation frequency can be respectively provided by an even number of inverters. The up-down counter 16 increments the output value by one when the count-up signal S U is applied to the count-up signal input terminal up and decrements the output value by one when the count-down signal S D is applied to the count-down signal terminal down. A divider 14 divides the frequency of the signal supplied to it by (N + 1). For example, suppose that a 16-bit multiplier is installed on an integrated circuit containing the clock signal generator of the embodiment; to generate the clock for operating the 16-bit multiplier, the divider 14 having a dividing factor of 1/17 is used because N is 16 in this example. A phase comparator 15 compares the divider output signal S fi with the external clock signal S fe . If the divider output signal S fi is found leading the external clock signal S fe in phase, the count-down signal S D is set to the logical high level. Conversely, if the divider output signal S fi is found lagging behind the external clock signal S fe in phase, the count-up signal S U is set to the logical high level. The phase comparator 15 thus operating may be constituted by using a plurality of NOR circuits 30 as shown in Fig. 3. Fig. 4 and Fig. 5 show the timing charts which represent how the output signals from the phase comparator 15 change in accordance with the input signals to the phase comparator 16. Particularly, Fig. 4 shows the state in which the divider output signal S fi is leading the external clock signal S fe in phase and Fig. 5 shows the state in which the divider output signal S fi is lagging behind the external clock signal S fe in phase. As clearly be understood from Fig. 4, if the divider output signal S fi is leading the external clock signal S fe in phase, the count-down signal SD is set to the logical high level; if the divider output signal S fi is lagging behind the external clock signal S fe in phase, the count-up signal S U is set to the logical high level. Based on the above-described circuit operations, the embodiment in its entirety is considered to operate in the following manner. Namely, if the frequency of the internally generated clock signal S fc is higher than (n + 1) or 17 times the frequency of the external clock signal S fe , the divider output signal S fi obtained by dividing the internally generated clock signal S fc by 17 by the divider 4 is compared with the external clock signal S fe by the comparator 5, thereby generating the count-down signal S D . This signal is applied to the count-down signal input terminal down of the up-down counter 6 to decrement the value of the three-bit output signal by one. The three-bit signal is applied to the selectors 11, 12, and 13 of the ring oscillator 20 to increment by τ the sum of the delay times provided by the delay circuits 21, 22, and 23, thereby lowering the oscillation frequency of the ring oscillator 20. The resulting frequency is compared by the phase comparator 15 again. This operation is repeated until the oscillation frequency of the internal clock signal gets lower than (n + 1) times the frequency of the external clock signal. If, on the other hand, the oscillation frequency of the internally generated clock signal S fc gets lower than (n + 1) times the frequency of the external clock signal S fe , the phase comparator 15 puts out the count-up signal S U , thereby raising the oscillation frequency of the ring oscillator 20. Thus, the internally generated clock signal S fc given from the ring oscillator 20 is controlled so that the period of the signal obtained by dividing the internally generated clock signal by (n + 1) gets in the range of 2τ around the period of the external clock signal S fe . That is, the frequency of the internally generated clock signal S fc is always controlled to a level near (n + 1) times the frequency of the external clock signal S fe . Suppose that the internal clock of a certain semiconductor integrated circuit is made to operate at a frequency higher than the external clock signal S fe given from an input terminal of the circuit, thereby providing a 16-bit time-division addition-type multiplier. In this case, one 16-bit multiplying operation can be replaced with 16 partial product adding operations. That is, the 16-bit time-division addition-type multiplier may be regarded as an adder which makes one multiplying operation by making 16 adding operations with one adder within one external clock period. Consequently, for the 16 adding operations to be made within one external clock period, the frequency of the internally generated clock signal S fc must be equal to or higher than 16 times the frequency of the external clock signal S fe . If the frequency of the internally generated clock signal S fc is raised more than necessary, the circuit becomes inoperable. It is therefore desired that the frequency of the internally generated clock signal S fc be set to a level not greatly exceeding 16 times the external clock signal S fe or to a level near 16 times the frequency of the external clock signal. As clearly be understood from the above description, generating an internal clock signal of which frequency is controlled to a level near 17 times as high as the frequency of the external clock enables the 16-bit time-division addition-type multiplier to always make 16 adding operations within one external clock period, thereby making the circuit operate correctly. As described above, forming the clock signal generator of the embodiment on a high-speed semiconductor integrated circuit may automatically generate the internal clock signal S fc of which frequency is an integral multiple of the frequency of the external clock signal, making the internal operation of the above-described circuit faster than the operation external to the circuit. Because the above-described constitution does not require to lay the wiring for transmitting the ultra high-speed clock signal on the circuit board, the constitution may be provided on a conventional circuit board, thereby making it possible to constitute the entire circuit based on the specifications for low-speed operations. As shown in Fig. 6, constituting the clock regulating circuit 38 which generates the internal clock signal S fc having a high frequency controlled by the external clock signal S fe by using the embodiment makes it possible to efficiently operate a circuit on which both low-speed and high-speed integrated circuits exist at the same time. On the circuit thus constituted, all the semiconductor integrated circuits can be constituted by using the digital process alone, providing great advantages in circuit design and process. . As described and according to the first aspect of the invention, the clock generator for generating a clock signal having a high frequency controlled by an external clock is constituted by using a ring oscillator for providing variable oscillating frequencies, a divider for dividing the oscillation frequency given from the ring oscillator by a specified number, a phase comparator for comparing the frequency of the output signal given from the divider with the frequency of the external clock signal given from the outside, and an up-down counter for controlling the oscillation frequency of the ring oscillator based on the comparison result from the phase comparator, so that the present invention may be constituted by using the digital integrated circuit technology alone. Consequently, the circuit for generating a clock signal necessary for efficiently operating a circuit on which both low-speed and high-speed semiconductor integrated circuits exist at the same time may be constituted by using the digital integrated circuit technology alone, thereby simplifying the design and manufacturing processes required for manufacturing the conventional clock signal generating circuit for generating a high-frequency clock signal controlled by a clock signal given from the outside. According to the second aspect of the invention, a circuit on which both low-speed and high-speed integrated circuits exist at the same time may be operated at speeds optimum for each of these circuits while providing an organic relationship between their operating timings. According to the third aspect of the invention, a semiconductor integrated circuit which operates on the internal clock signal faster than the external clock signal may be constituted by using the digital integrated circuit technology alone, thereby simplifying the process for manufacturing semiconductor integrated circuits which can provide the advantage of high-speed operation. In addition, when operating a circuit on which both low-speed and high-speed semiconductor integrated circuits exist at the same time, generating a high-frequency internal clock signal can make the most of the capability of the high-speed semiconductor integrated circuits in the state in which all semiconductor integrated circuits seem to be operating at low speeds when viewed from the outside. Consequently, it is not required to provide throughout the circuit board the ultra high-speed clock signal for driving the semiconductor integrated circuits which can provide high-speed operations, making a conventional circuit board available for constituting an ultra high-speed circuit.

Claims: A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator (20) providing at its output terminal oscillating frequencies (Sfc) determined by a sum of the delay times provided by circuit elements (21-23, 17-19) connected in series in said ring oscillator (20); a frequency divider (14) coupled to said output terminal of said ring oscillator (20) and dividing the oscillation frequency (Sfc) provided at said output terminal of said ring oscillator by a specified number (N+1); a phase comparator (15) coupled with an output signal (Sfi) of said divider (14) and comparing the frequency of said output signal (Sfi) from said divider with a frequency of a clock signal (Sfe), characterized in that an up-down counter (16) is provided generating a switching signal for selecting a number of said circuit elements of said ring oscillator (20) and thereby said sum of the delay times provided by said circuit elements thereby controlling the oscillation frequency (Sfc) of said ring oscillator based on a comparison result on said phase comparator (15), and said ring oscillator (20) includes selectors (11, 12, 13) connected in series with said circuit elements (21-23, 17-19) and switched by said switching signal of said up-down counter (16) so that the oscillation period of said ring oscillator (20) is regulated to be lower than the oscillation period of said externally entered clock signal (Sfe) by said specified number (N+1), wherein said clock signal generator is controlled by said externally entered clock signal (Sfe) to generate its internal clock signal (Sfc), the frequency of which is higher than the frequency of said externally entered clock signal (Sfe) by said specified number (N+1). The semiconductor integrated circuit having said clock signal generator according to claim 1, wherein said clock signal generator comprises a clock regulator (38) outputting both said externally entered clock signal (Sfe) and said internal clock signal (Sfc) of said higher frequency. The semiconductor integrated circuit having said clock signal generator according to claims 1 or 2, wherein said semiconductor integrated circuit is composed of both compound semiconductors and Si semiconductors.

Inventors: CHIAKI TAKANO, CHIAKI, TAKANO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: G06F1
IPC codes: H03L7, G06F1, H03K3, G11C11