Output circuit with buffer

Abstract: An output circuit having a buffer, the buffer including the first transistor (N1) which receives at a gate thereof a periodic input voltage (VIN) and the second transistor (N2), the first and the second transistors being connected in series across a power line (VDD) and a ground line (GND), a junction of the firs and second transistors being connected to an output terminal (TOUT). The output circuit includes a circuit (VG) for applying, to a gate of the second transistor, a first voltage (VIT) for the second transistor to serve as a bias transistor for charging a load (LD) connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit with a buffer. 2. Description of the Related Art Fig. 3 shows a prior output circuit. In the output circuit, a source follower transistor N1 and a bias transistor N2 constitute an output buffer. N4 denotes a discharge transistor whose drain is connected to an output terminal TOUT. The gate of the transistor N4 is given a periodic discharge pulse DIS for the purpose of discharging a load LD, and the gate of the transistor N2 is given a constant bias voltage Vb as shown in Fig. 4 . When an input voltage VIN is applied to the gate of the transistor N1 and the constant bias voltage Vb is applied to the gate of the transistor N2, an output voltage according to the input voltage VIN is supplied to the load LD. The discharge pulse DIS is applied to the gate of the transistor N4 in synchronism with the periodic input voltage VIN. After the load Ld is discharged through the transistor N4, the load LD is charged again according to the input voltage VIN. The above described output circuit has a problem in that it takes not a little time to discharge the load LD due to the limit of the discharge capacity of the transistor N4, and to charge the load LD to a sufficient voltage level for the output circuit to output a voltage corresponding to the input voltage since the load LD is completely discharged to the ground level. US-A-4 950 925 discloses an output circuit similar to that described above with reference to Fig. 3 and in which a load is charged by a first transistor via a bipolar transistor wired as an emitter follower. In one embodiment of this prior art, an additional transistor is connected in parallel with the discharge transistor (N4) so as to effect discharge within a short period. SUMMARY OF THE INVENTION The present invention provides the output circuit defined by claim 1, whose preamble reflects the state of the art according to US-A-4 950 925. In the output circuit according to the present invention, the second transistor constituting a buffer serves as a discharge transistor during a discharge period, thereby either shortening the discharge time or simplifying the circuit structure, according to whether or not the fourth transistor is included. Furthermore, by setting the first transistor constituting the buffer to an OFF state during the discharge period, a through current flowing through the first and the second transistors can be reduced. According to the preferred features of claim 2, by adjusting a period of time during which the third and fourth transistors are at ON state, it is possible to discharge the load to a certain level greater than the ground level, thereby shortening the charging time. Thus, the output circuit can operate at a high speed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of an output circuit with a buffer of an embodiment according to the present invention; Fig. 2 is a view showing waveforms of a discharge pulse and a bias voltage supplied to the output circuit of Fig. 1; Fig. 3 is a circuit diagram of a prior output circuit with a buffer; and Fig. 4 is a view showing waveforms of a discharge pulse and a bias voltage supplied to the output circuit of Fig. 3. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a circuit diagram of an output circuit with a buffer of an embodiment according to the present invention. In Fig. 1, each same element as that shown in Fig. 3 is given the same reference and explanation thereof is omitted. In Fig. 1, N3 denotes a transistor connected between the gate of the source follower transistor N1 and the ground GND. The gate of the transistor N3 is supplied with the disscharge pulse DIS shown in Fig. 2 which is also applied to the gate of the discharge transistor N4. The gate of the bias transistor N2 is supplied with a bias voltage VB generated by a voltage generating circuit VG, the bias voltage VB being at a level of VIT which is between VDD and GND except in the discharge period, and at the VDD level during the discharge period as shown in Fig. 2. Accordingly, when the input voltage VIN is applied to the gate of the source follower transistor N1 constituting the buffer and the bias voltage VB at the VIT level is applied to the gate of the transistor N2, a voltage corresponding to the input voltage VIN is outputted from the output terminal TOUT and supplied to the load LD. To discharge the load LD, the discharge pulse DIS is applied to the gates of the transistors N3 and N4, and at the same time, the level of the bias voltage VB applied to the gate of the transistor N2 is increased to a certain level greater than VIT, whereby the charges in the load LD are released through not only the transistor N4 but also the transistor N2. Accordingly, a large amount of charges can be released rapidly so that the time required for discharge can be reduced. Further, by adjusting the duration of the discharge pulse DIS, it is possible to discharge the load LD to a certain level greater than the ground level in order that the time required for charging the load LD again according to the level of the input signal VIN is reduced. While the load LD is discharged, the gate of the transistor N3 is at VDD level; therefore, the drain of the transistor N3 is at the ground level and the transistor N1 is at OFF state, whereby a through current flowing through the transistors N1 and N2 is reduced. In a case where high speed operation is not required, it is possible to carry out the discharge by the transistors N2 and N3 without the transistor N4; therefore, the number of transistors can be reduced in that case, thereby reducing the size of the output circuit.

Claims: An output circuit comprising a buffer having an input for receiving a periodic input voltage (VIN) and an output (TOUT) for connection to a load (LD) to be charged, in operation of the circuit, with a voltage corresponding to said input voltage, the circuit comprising a first transistor (N1) arranged to receive said input voltage (VIN) at its gate, a second transistor (N2) coupled to the first transistor so as to cause said charging of said load when a first voltage (VIT) is applied to the gate of said second transistor, means (VG) for selectively applying to said gate of said second transistor (N2) said first voltage (VIT) and a second different voltage (V DD ) to cause said second transistor to serve as a discharge transistor for discharging said load, said first transistor (N1) being arranged to be set to an OFF state in synchronism with the application of said second voltage to said second transistor (N2) by setting means (N3), characterised in that said applying means (VG) is arranged so that said first voltage (VIT) is a constant bias voltage between the level of said second voltage and ground applied to said gate of said second transistor except in the discharge period of application of said second voltage (V DD ), and in that said setting means (N3) consists of a third transistor (N3) whose drain and source are connected to said gate of the first transistor (N1) and to ground respectively, a gate of the third transistor receiving a periodic pulse signal (DIS) in response to which the third transistor switches the first transistor OFF. An output circuit according to claim 1, further comprising a fourth transistor (N4) whose drain and source are connected to said output and ground respectively, a gate of the fourth transistor receiving said periodic pulse signal (DIS) for setting the fourth transistor to an ON state for discharging said load (LD) therethrough.

Inventors: ORISAKA YUKIHISA, SANO YOSHIKI, TANAKA JUNJI, ORISAKA, YUKIHISA, SANO, YOSHIKI, TANAKA, JUNJI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: H03K19
IPC codes: H03K17, H03K19