Pictorial image compression device

Abstract: Disclosed is a pictorial image compression device comprising an A/D converter (1) converting an analog image input signal into digital image data, a clock dropout circuit (3) producing a dropout indication signal and a partly dropped-out clock on the basis of a write clock and data of a selected compression rate, an averaging circuit (2) averaging the image data according to the partly dropped-out write clock, a memory (5) successively storing the image output data from the averaging circuit (2) in response to the partly dropped-out write clock, a reading circuit (6) reading out the image data stored in the memory (5), and a D/A converter (7) converting the image data read out by the reading circuit (6) into an analog signal, so that images can be continuously compressed without highlighting undesirable discontinuity at the edge of each image. Thus, the device can continuously compress image data in spite of its simple circuit structure.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a pictorial image compression device, and more particularly to a device of the kind described above which is suitable for exhibiting a special video effect by compressing pictorial images. Description of the Prior Art A method well known in the art and commonly employed in a prior art pictorial image compression device comprises setting beforehand a plurality of specific rates of pictorial image data compression, determining one of the image data compression rates to select one of average image data corresponding to the determined image data compression rate, and writing the average image data in a memory in synchronism with a specific write clock. By the employment of such a method, the image data read out from the memory can be displayed in the compressed mode. However, in the prior art pictorial image compression device, the number of required image data averaging circuits must be equal to that of the image data compression rates, and also the number of required write clocks must be equal to that of the image data compression rates so as to successfully store the image data in the memory. Thus, the prior art device has the problem that, in order to achieve the objective of continuous compression of pictorial images, the circuit structure of the device inevitably becomes complex. In an article entitled "Èffets Spéciaux : Changements de Format d'une Image de Television" by A. Le Toquin (Toute l'Èléctronique, No. 460, January 1981, Paris, pages 23 to 28), there is described a video signal reduction system comprising the features in the preamble of claim 1, but wherein the clock signal is altered by multiplying the same by a reduction ratio and subsequently comparing the product with the output of a counter. SUMMARY OF THE INVENTION It would be desirable to provide a pictorial imaged compression device which can continuously compress pictorial images in spite of its simple circuit structure. In accordance with the present invention, there is provided a pictorial image compression device as defined by claim 1. The compressed images can then be displayed on the basis of the image data stored in the memory without highlighting undesirable discontinuity at the edge of the displayed compressed images. BRIEF DESCRIPTION OF THE DRAWINGS Fig, 1 is a block diagram showing the structure of an embodiment of the pictorial image compression device according to the present invention. Fig. 2 is a timing chart showing the signal processing timing in the embodiment of the pictorial image compression device of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described by reference to the drawings. Fig. 1 schematically shows the structure of a preferred embodiment of the pictorial image compression device of the present invention, and Fig. 2 is a timing chart showing the signal processing timing in the embodiment of the pictorial image compression device of the present invention. The structure and operation of the illustrated embodiment of the device of the present invention will now be described principally by reference to Fig. 1 while making partial reference to Fig. 2. Referring to Fig. 1, the pictorial image compression device comprises an A/D converter 1, an averaging circuit 2, a clock dropout circuit 3, a writing circuit 4, a memory 5, a reading circuit 6, and a D/A converter 7. The A/D converter 1 acts as a means for converting a pictorial image input signal into digital image data in synchronism with a write clock, and the A/D converted image data (the signal A in Fig. 2) is supplied as an input to the averaging circuit 2. The averaging circuit 2 includes delay circuits 11, 12, 13, full adders 14, 15, 16, a switch 17 and a dropout indication signal detector circuit 18. The delay circuits 11, 12 and 13 act to successively delay the input image data by a predetermined period of time (the period of one line, that is, about 63 µ sec in the case of the NTSC system), and the full adders 14, 15 and 16 act to successively average the image data and the delayed image data delayed by the respective delay circuits 11, 12 and 13 so as to successively output the averaged image data. The dropout indication signal detector circuit 18 consists of the combination of a delay circuit and a decoder, and the write clock and a dropout indication signal from the clock dropout circuit 3 are applied to this detector circuit 18. In response to the application of the dropout indication signal from the clock dropout circuit 3 together with the write clock, the detector circuit 18 detects the degree of continuity of the dropout indication signal and applies its detection output (the signal B in Fig. 2) to the switch 17. According to the input signal applied from the dropout indication signal detector circuit 18, the switch 17 selects one of the output image data appearing from the A/D converter 1, the full adder 14 and the full adder 16, so that the selected image data can be transferred to the memory 5 to be stored in the memory 5. The clock dropout circuit 3 includes a binary counter 21, AND gates 22, 23, 24, 25, a differentiating circuit 29, a NOR gate 30 and another AND gate 31 and acts as a means for dropping out part of the write clock thereby producing the dropout indication signal and the partly dropped-out write clock on the basis of the supplied write clock and the data of the selected compression rate. More precisely, the write clock applied to the binary counter 21 is subjected to frequency division, and the counter outputs (the signals 21A, 21B, 21C and 21D in Fig. 2) generated by the frequency division of the write clock are applied to the AND gates 25, 24, 23 and 22 respectively. In addition to the counter outputs generated by the frequency division of the write clock, the data of the compression rate are supplied to these AND gates 22 to 25 respectively. The output signals of the AND gates 22 to 25 are applied to the differentiating circuit 29. The differentiating circuit 29 detects the rising edge of each of the output signals of the AND gates 22 to 25, and the detection output signals of the differentiating circuit 29 are applied to the NOR gate 30, so that this NOR gate 30 generates dropped-out clock pulse information, that is, the dropout indication signal. This dropout indication signal (the dropped-out pulse signal C in Fig. 2) is applied to both the dropout indication signal detector circuit 18 and the AND gate 31. The partly dropped-out write clock (the compressed image write clock signal D in Fig. 2) representing the logical product of the supplied write clock and the dropout indication signal is applied from the AND gate 31 to the writing circuit 4. The writing circuit 4 acts as a means for generating a write instruction signal conforming to the partly dropped-out write clock. Under control of this write instruction signal applied to the memory 5, the image data are successively stored in the specified areas of the memory 5 respectively. The reading circuit 6 acts as a means for reading out the image data stored in the memory 5, and each image data read out from the memory 5 by the reading circuit 6 is transferred to the D/A converter 7 to be converted into an analog signal. The binary counter 21 is designed to be reset in the horizontal or vertical direction of the image and then counts up the binary code. The device is constructed so as to obtain the logical product of this binary code and the data of the compression rate, to obtain the logical product of the most significant bit (MSB) output of the binary counter 21 and the least significant bit (LSB) of the data of the compression rate and to obtain the logical product of the least significant bit (LSB) output of the binary counter 21 and the most significant bit (MSB) of the data of the compression rate. Thus, the NOR gate 30 can generate the dropout indication signal in which clock pulses corresponding to the number of the data of the compression rate are dropped out among sixteen clock pulses of the 4-bit system. The averaging circuit 2 carries out its image data averaging processing according to the partly dropped-out write clock. Therefore, because the write clock is partly dropped out, the image can be averaged according to the data of the image compression rate, so that compressed images that are quite natural and continuous can be displayed. The timing chart shown in Fig. 2 corresponds to that of the 4-bit system, and the image compression rate is selected to compress the image by the factor of 9/16. The binary counter 21 counts up the binary code each time the write clock is applied. In the output signals 21A, 21B, 21C and 21D appearing in the above order from the binary counter 21, the signal 21A represents the least significant bit (LSB), while the signal 21D represents the most significant bit (MSB). In the case shown in Fig. 2, the data of the image compression rate of 9/16 is "9" which is "1001" according to the binary code. The bits of this binary code "1001" are allotted to the compression rate data signals 28A, 28B, 28C and 28D respectively in which the signal 28A represents the least significant bit (LSB), while the signal 28D represents the most significant bit (MSB). The compression rate data signals 28A, 28B, 28C and 28D are applied together with the counter output signals 21D, 21C, 21B and 21A to the corresponding AND gates 22, 23, 24 and 25 respectively. The output signals of these AND gates 22, 23, 24 and 25 are then differentiated by the differentiating circuit 29 and are passed through the NOR gate 30 to produce the partly dropped-out pulse signal C. Then, this dropped-out pulse signal C is applied to the AND gate 31 together with the synchronous write clock to provide the compressed image write clock signal D. On the other hand, by the image compression and averaging function of the averaging circuit 2, sixteen signals V1, V2, ..., V15 and V16 shown in Fig. 2 are averaged into nine signals. That is, the sixteen signals V1 to V16 are averaged into the nine signals by the combination of the delay circuits 11, 12, 13 and the full adders 14, 15, 16. For example, the signal V1 delayed by the period of one line by the delay circuit 11 and the delay-free signal V2 are added in the full adder 14 to be averaged into the signal "(V1 + V2)/2". In the manner described above, the image signal is averaged according to the image compression rate, and, in response to the compressed image write clock signal, write address data A1 to A9 as shown in Fig. 2 are stored in the memory 5. The illustrated embodiment refers to the case where the number of bits of the data of the compression rate is four, and the binary counter is of the four bit type. However, it is apparent that the number of bits of both the image compression rate and the binary counter is in no way limited to the four, and any other suitable number can be used as desired. Further, although the averaging circuit 2 in the illustrated embodiment is composed of the three kinds of elements, it is apparent that the number of kinds of averaging elements may be more than that shown in Fig. 1. It will be understood from the foregoing description of the embodiment of the present invention that an analog image signal is converted into digital image data, and the digital image data is subjected to digital processing to produce compressed image data, so that the circuit structure of the device can be greatly simplified.

Claims: A pictorial image compression device comprising: analog/digital converter means (1) for converting a pictorial image input signal into digital image data in synchronism with a write clock; clock inhibiting means (3) for inhibiting part of the write clock in dependence on a selected compression rate to produce a compressed image write clock (D); averaging means (2) for averaging the image data in accordance with a clock inhibition indicating signal (C); writing means (4) for outputting a write instruction signal in response to said compressed image write clock (D); memory means (5) for storing the output data from said averaging means (2) in response to the write instruction signal; reading means (6) for reading out the image data stored in said memory means (5); and digital/analog converter means (7) for converting the image data read out by said reading means (6) into an analog signal; characterised in that: said clock inhibiting means (3) comprises a counter (21) for dividing the frequency of the write clock to generate output signals having different respective frequencies and gate circuits (22, 23, 24, 25, 29, 30, 31) for gating the output signals of said counter (21) under control of data indicating the compression rate. A pictorial image compression device according to Claim 1, wherein said averaging means (2) includes delay circuits (11, 12, 13) for delaying the image data by a predetermined period of time and full adder circuits (14, 15, 16) for adding the output signals of said delay circuits to said image data. A pictorial image compression device according to Claim 2, wherein the delay time of said delay circuits (11, 12, 13) is selected to be equal to the period of one line.

Inventors: KAWAMOTO SIGEHARU, NAKANISHI MASAHIRO, KAWAMOTO, SIGEHARU, NAKANISHI, MASAHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: H04N7
IPC codes: H04N1, G06F3, H04N5, G06T3, H04N7, G09G5, G06T9