Frequency synthesis using frequency controlled carrier modulated with PLL feedback signal

Abstract: In a frequency synthesizer, a phase detector receives an externally generated reference clock signal of a constant frequency and a feedback signal to produce an error signal, which is output through a loop filter to a voltage controlled oscillator. A direct digital synthesizer (DDS) receives the reference clock signal and externally generated phase data to produce a DDS output signal whose frequency is precisely controlled by the phase data. The DDS output signal is applied as a carrier to a differential detector where it is modulated with the output of the VCO to produce a signal corresponding to the lower sideband of the modulated carrier. The output of the differential detector is output to the phase detector as the feedback signal.

Description: The present invention relates generally to phase lock loop frequency synthesizers, and more specifically to a direct digital synthesizer driven phase lock loop frequency synthesizer which is particularly suitable for use in applications, such as digital cellular telephony, where communications channels are switched from one channel to another at significantly high speeds. As shown in Fig. 1a, a typical conventional phase lock loop frequency synthesizer synthesizes a frequency by using a control voltage to derive a voltage controlled oscillator 5 which generates a signal of frequency f o near the desired frequency. A frequency divider 6 is used to divide the VCO signal output frequency by an integer value N to produce a signal of frequency f s . The frequency-f s signal is input along with a signal of reference frequency f r to a phase detector 3. The phase detector compares the frequencies of the two input signals and outputs a voltage proportional to the difference in frequency of the two input signals. The output of the phase detector 3 is coupled through a loop filter 4, where it is input to the VCO 5 as the control voltage. The reference frequency (f r ) signal is derived by a divide-by-M frequency divider 2 which divides a signal of high accuracy frequency f x from a master oscillator 1 by a constant integer value M. The integer N of frequency divider 6 is variable by an incremental frequency control voltage so that if the VCO 5 were generating exactly the desired frequency, the resultant frequency-f s signal would be exactly the same frequency as reference frequency f r and the following relation holds: f o = (N)(f x /M) As the frequency control voltage is varied, the output frequency f o varies accordingly from one frequency, or channel, to another, and the minimum channel separation, or frequency step size or resolution, Δf o is given by: Δf o = f x /M To insure loop stability the loop filter needs to have a cutoff frequency much lower than the reference frequency. However, the lock-in time of the frequency synthesizer is inversely proportional to the cutoff frequency. Since the reference frequency is predetermined, the lock-in time cannot be reduced and hence, is a detrimental factor to achieve high speed channel switching. This slow lock-in operation is overcome by techniques shown and described in US-A-4,965,533. To provide mathematical analysis of this patent, two embodiments of the prior art PLL frequency synthesizer are shown respectively in Figs. 1b and 1c of this specification. One of the prior-art embodiments, shown in Fig. 1b, incorporates a direct digital synthesizer (DDS) 7 that is clocked by the master oscillator to serve as the source of the reference frequency for the phase lock loop. The DDS typically comprises a phase accumulator which receives a digital fine frequency control signal ΔX to determine the phase increment for accumulation at the master clock rate. The accumulated phase value is output to a sine lockup table, which stores sine values and provides an output signal, indicative of the digital representation of a periodic waveform, as an input to a digital-to-analog converter. The output of the D/A converter is filtered by a low-pass filter 8 and input to the frequency divider 2, whose output is used as a variable reference frequency input to the phase detector. Thus, frequency divider 6 operates as a constant-value divider. When the accumulated phase reaches a certain threshold, the phase accumulator automatically resets itself to repeat the accumulation process. Thus, the phase accumulator can be said to operate with a modulo value. If this modulo value is represented as L, the reference frequency f r is given by: f r = (f x )(ΔX)/L and the synthesizer output frequency f o is expressed by: f o = (N)(f r ) = (N)(f x )(ΔX)/L Since the frequency control is provided by DDS 7 in response to increment ΔX, the minimum frequency step size Δf o is equal to a variation in the output frequency f o that occurs in response to an increment of ΔX = 1. Therefore, the following relation holds: Δf o = (N)(f x /L) From Equations (3) and (5), the relation f r = (Δf o )(ΔX/N) is obtained. This implies that by setting the increment ΔX at a value greater than the integer N, the reference frequency f r can be set higher than the reference frequency of the Fig. 1a frequency synthesizer for a given minimum frequency resolution. For example, using a minimum frequency step size of 25 kHz, a master clock frequency f x = 12.8 MHz and an integer N = 1024, Equation (5) gives a modulo value L = 2 19 . If the output frequency f o is chosen at 1 GHz, Equation (4) gives an increment ΔX = 40000, a value much greater than the integer N = 1024. Thus, a reference frequency of 976.5625 kHz, much higher than Δf o = 25 kHz, is obtained. While high speed convergence of the phase lock loop can be achieved, variation of the reference frequency causes a control voltage variation at the input of the VCO, a variation known as "reference leak", which would result in the transmission of spurious frequencies. A band rejection filter must be provided as part of the loop filter 4 to eliminate the undesired spurious transmission. However, it is difficult to eliminate the undesirable components uniformly across all channels of the frequency synthesizer. According to the other prior art technique shown in Fig. 1c, DDS 7 and low-pass filter 8 are provided in the phase lock loop, following the output of divider 6, so that the divided frequency signal f s is caused to vary in response to phase increment ΔX, while reference frequency f r remains constant, thus giving the following relations; f s = (f o )(ΔX)/(N)(L) f x /M = (f o )(ΔX)/(N)(L) Thus, f o = (f x )(N)(L)/(M)(ΔX) While this technique eliminates the reference leak problem, the fact that the output frequency f o varies inversely proportional to the increment ΔX, as given by Equation (8), makes it impossible to set all channels of the synthesizer at precisely equal frequency intervals. US-A-4145667 discloses a PLL frequency synthesizer using digital modulo arithmetic. It is therefore an object of the present invention to provide a phase lock loop frequency synthesizer that allows high speed setting of a selected frequency from a plurality of precisely equally spaced apart frequencies without causing reference leak. This object is solved with the features of the claims. The frequency synthesizer as described comprises a phase detector having a reference input for receiving an externally generated reference signal of a constant frequency, a feedback input, and a phase detector output, a loop filter having an input coupled to the phase detector output, and a loop fiter output, and a voltage controlled oscillator having an input coupled to the loop filter output, and an oscillator output for providing a synthesizer output signal. A direct digital synthesizer (DDS) has a clock input for receiving the reference signal, a frequency control input for receiving externally generated phase data, and a DDS output. A differential detector means is provided having a first input coupled to the oscillator output, a second input coupled to the DDS output for producing a differential signal indicative of a frequency difference between signals at the first and second inputs, and a differential detector output coupled to the feedback input of the phase detector for providing thereto the differential signal. The direct digital synthesizer comprises a phase accumulator having a phase input for receiving the phase data, a clock input for receiving the reference signal for accumulating the phase data at the rate of the reference signal, and in accumulator output, a memory having a plurality of addressable storage locations each storing a predetermined sine value, an address input coupled to the accumulator output, and a memory output, and a digital to analog converter having a converter input coupled to the memory output, and a converter output coupled to the second input of the differential detector means. According to a first embodiment of the present invention, the differential detector means comprises a mixer having a first input coupled to the DDS output, a second input coupled to the oscillator output, and a mixer output, and a low-pass filter having an input coupled to the mixer output, and an output coupled to the feedback input of the phase detector. According to a second embodiment of the present invention, the differential detector means comprises an additional phase accumulator having a phase input for receiving constant value phase data, a clock input coupled to the oscillator output as the first input of the differential detector means, and an additional accumulator output, a subtractor having a first input coupled to the first-mentioned accumulator output and a second input coupled to the additional accumulator output, and a subtractor output coupled to the address input of the memory as the first-mentioned accumulator output, and a low-pass filter having an input coupled to the converter output as the second input of the differential detector means and an output coupled to the feedback input of the phase detector as the differential detector output. Preferably, the frequency synthesizer includes a divide-by-M frequency divider having an input for receiving the reference clock signal, and an output coupled to the reference input of the phase detector, and a divide-by-N frequency divider having an input coupled to the oscillator output and an output coupled to the first input of the differential detector means as the oscillator output. The present invention will be described in further detail with reference to the accompanying drawings, in which: Figs. 1a is a block diagram of a conventional phase lock loop frequency synthesizer, and Figs. 1b and 1c are block diagrams of the phase lock loop frequency synthesizers of the aforesaid U.S. patent; Fig. 2 is a block diagram of a first embodiment of this invention; and Fig. 3 is a block diagram of a second embodiment of this invention. Referring now to Fig. 2, there is shown a phase lock loop frequency synthesizer according to a first embodiment of the present invention. The PLL frequency synthesizer of the present invention comprises a direct digital synthesizer 10 which is clocked by the master oscillator 1. DDS 10 includes a phase accumulator 11 which operates with modulo L and receives a digital fine frequency control signal ΔX to determine the phase increment for accumulation at the master clock rate. The accumulated phase value is output to a sine lockup table 12, which stores sine values and uses the accumulated phase value as an address signal to provide an output signal, indicative of the digital representation of a sinusoidal waveform at frequency f k , as an input to a digital-to-analog converter 13. Sine lockup table 12 is typically implemented with a read only memory. The output of the D/A converter 13 is input to an analog mixer 14 as a local carrier and mixed with the output signal of frequency f d from frequency divider 6 to produce a signal that is indicative of the amplitude modulation of the divided frequency signal f d . The output of mixer 14 is filtered by a low-pass filter 15 to remove undesired higher frequencies and input to phase detector 3 as a signal of frequency f s . The embodiment of Fig. 2 can be analyzed as follows: f k = (f x )(ΔX)/L f d = f o /N f s = f d - f k = f o /N - (f x )(ΔX)/L Since f r = f x /M, and f r = f s when the frequency synthesizer converges, the following Equation holds: f x /M = f o /N - (f x )(ΔX)/L Thus, the output frequency f o and the minimum frequency step size Δf o of the frequency synthesizer are given as: f o = (N)(f x ){L + (ΔX)(M)}/(L)(M) Δf o = (N)(f x )/L Equation (12) indicates that all channels of the synthesizer can be set at precisely equal frequency intervals. In addition, since Equation (13) is identical to Equation (5), the minimum frequency step size of the present embodiment is as small as that of the prior art of Fig. 1b. A further advantage is that, by virtue of the constant reference frequency, reference leak can be easily removed by a simple band rejection filter 4B which forms the loop filter 4 with a low-pass filter 4A. Moreover, the reference frequency can be chosen at a desired high value regardless of the step size Δf o , the frequency synthesizer can be converged at a high speed. With a step size of 25 kHz, a master clock frequency f x = 12.8 MHz and an integer N = S12, Equation (13) gives a modulo value of L = 2 18 . If the integer M is set equal to 8 and the desired output frequency f o is 1 GHz, Equation (12) provides ΔX = 7232. A reference frequency f r of as high as 1.6 MHz can therefore be obtained, which is sufficiently high to achieve high speed convergence. It is preferable to implement phase lock loop frequency synthesizers using LSI technology. A second embodiment of the present invention, shown in Fig. 3, is suitable for the LSI implementation. This embodiment differs from the first embodiment by the use of a differential DDS 20 instead of the DDS 10 and mixer 14 of the previous embodiment. It is seen that differential DDS 20 is comprised of a first phase accumulator 21 clocked by the master oscillator 1 at frequency f x and a second phase accumulator 22 clocked by the frequency divider 6 at frequency f d . Each phase accumulator has a modulo value of L as the accumulator of the previous embodiment. Phase accumulators 21 and 22 feed their output signals to a digital subtractor 23 which detects the difference between the two inputs and outputs a signal indicative of the difference to a sine lockup table 24 as an address signal. A periodic signal is generated by sine lockup table 24 and output to D/A converter 25. The output of D/A converter 25 is coupled to the low-pass filter 15. Phase accumulator 21 receives a digital fine frequency control signal ΔXa to determine the phase increment for accumulation at the master clock rate, while phase accumulator 22 receives a fixed digital value ΔXb to determine the phase increment for accumulation at a clock rate which is 1/N of the VCO output frequency. By setting ΔXa equal to a non-zero value and ΔXb equal to zero, the differential DDS 20 operates as if it were a normal, single-accumulator DDS clocked at the master clock rate, and in this case, the output frequency f s1 of DDS 20 is given by: f s1 = (f x )(ΔXa)/L Conversely, if ΔXa is set equal to zero and ΔXb to a non-zero value, the differential DDS 20 operates as if it were a normal, single-accumulator DDS clocked at the rate of the output of frequency divider 6, and in this case, the output frequency f s2 of DDS 20 is given by: f s2 = (f d )(ΔXb)/L = (f o )(ΔXb)/(L)(N') where N' is the integer of divider 6 when the DDS 20 is clocked exclusively by the output of divider 6. Therefore, if both of the phase increments ΔXa and ΔXb are of non-zero value, the output frequency f s of DDS 20 is represented as: f s = f s2 - f s1 = (f o )(ΔXb)/(L)(N') - (f x )(ΔXa)/L By setting N' = (N)(ΔXb)/L, and ΔXa = ΔX, Equation (16) can be rewritten as: f s = (f o )(N) - (f x )(ΔX)/L Since Equation (17) is identical to Equation (11), the frequency synthesizer of the second embodiment operates exactly in the same manner as that of the first embodiment.

Claims: A frequency synthesizer comprising: a divide-by-M frequency divider (2) for dividing the frequency of an externally generated reference clock signal of constant frequency by an integer M; a phase detector (3) for producing a phase difference signal representing the phase difference between the output of the frequency divider (2) and a feedback signal; a loop filter (4) for filtering the phase difference signal; a voltage controlled oscillator (5) for producing a voltage-controlled frequency output according to the filtered phase difference signal; a divide-by-N frequency divider (6) for dividing the output frequency of the voltage controlled oscillator (5) by an integer N; a direct digital synthesizer (10) for producing a frequency signal from said externally generated reference clock signal according to externally generated phase data; and differential detector means (14, 15) for producing a differential signal indicative of a frequency difference between the frequency signal of the direct digital synthesizer (10) and the output of the divide-by-N frequency divider (6) and supplying the differential signal to said phase detector (3) as said feedback signal. A frequency synthesizer as claimed in claim 1, wherein said direct digital synthesizer comprises: a phase accumulator (11) for accumulating said phase data (ΔXa) at the rate of said reference dock signal; a memory (12) for storing sine values in locations addressable by the output of the phase accumulator (11); and a digital to analog converter (13) for converting the output of the memory (12) to an analog signal. A frequency synthesizer as claimed in claim 1 or 2, wherein said differential detector means (14, 15) comprises: a mixer (14) having a first input coupled to said DDS output, a second input coupled to said oscillator output, and a mixer output; and a low-pass filter (15) having an input coupled to the mixer output, and an output coupled to said feedback input of the phase detector. A frequency synthesizer comprising: reference clock means (1) for generating a reference clock signal; phase detector means (3) for receiving said reference clock signal and a feedback signal, detecting a phase difference between said reference clock signal and said feedback signal and producing a corresponding error signal; loop filter means (4) for filtering noise in said error signal and producing a filtered error signal; variable oscillator means (5) for generating a variable oscillator output signal in response to said filtered error signal; first phase accumulator means (21) for receiving a digital frequency control signal indicative of a first phase increment value and accumulating first phase increment values at a rate corresponding to said reference clock signal, and producing a first accumulator output signal corresponding to the accumulated first phase increment values; second phase accumulator means (22) for receiving a digital signal of a constant value indicative of a second phase increment value and accumulating second phase increment values at a rate corresponding to said variable oscillator output signal, and producing a second accumulator output signal corresponding to the accumulated second phase increment values; subtractor means (23) for receiving said first and second accumulator output signals, detecting accumulated phase difference values between the accumulated first phase increment values and the accumulated second phase increment values, and producing a corresponding subtractor output signal; memory means (24) for storing a plurality of digital amplitude values representing instantaneous amplitude values of an analog periodic signal and producing a memory output signal Indicative of the digital amplitude value corresponding to each accumulated phase difference value of said subtractor output signal; and converter means (25) for converting the digital amplitude values of the memory output signal to analog amplitude values, producing a corresponding analog periodic signal, and providing the analog periodic signal as said feedback signal. A frequency synthesizer as claimed in claim 4, further comprising: first divider means (2) for receiving the reference clock signal, dividing the reference clock signal frequency by M, and providing to said phase detector means (3) said reference clock signal corresponding In frequency to said reference clock frequency divided by M; and second divider means (6) for receiving the variable oscillator (5) output signal, dividing the variable oscillator output signal frequency by N, and providing to said second phase accumulator means (22) said variable oscillator output signal corresponding in frequency to said variable oscillator output signal frequency divided by N. A frequency synthesizer as claimed in any one of claims 1 to 5, wherein said loop filter means (4) comprises a series of a low-pass filter (4A) and a band rejection filter (4B).

Inventors: ICHIHARA MASAKI, ICHIHARA, MASAKI, ICHIHARA, MASAKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H03L7
IPC codes: H03L7