Static random access type semiconductor memory device

Abstract: An object of the present invention is to miniaturize a structure of a memory cell in an SRAM. The memory cell in the SRAM includes a pair of access transistors (Q 3 , Q 4 ), a pair of driver transistors (Q 1 , Q 2 ) and a pair of load transistors (Q 5 , Q 6 ). A first group of transistors is formed in a main surface of a silicon substrate, a second group of transistors is formed on an interlayer insulating layer covering the first group.

Description: The present invention generally relates to semiconductor memory devices and, more particularly, relates to cell structures in a static random access memory where integration density of memory cells can be increased. Fig. 20 is an equivalent circuit diagram of one memory cell in a conventional static random access memory (hereinafter referred to as SRAM). This memory cell includes six p-type MOS transistors as loads. A pair of driver (for driving) transistors Q 1 and Q 2 (n-type MOS transistors) are connected to a pair of load transistors Q 5 and Q 6 (p-type MOS transistors) to form a flipflop circuit. The sources 110 and 111 of the pair of load transistors Q 5 and Q 6 are connected to a power supply Vcc and the sources 112 and 113 of driver transistors Q 1 and Q 2 are connected to GND. A pair of access transistors Q 3 and Q 4 (n-type MOS transistors) are connected to storage nodes 114 and 115, respectively. A bit line 107 is connected to one source/drain of access transistor Q 3 and a bit line 108 is connected to one source/drain of access transistor Q 4 . The gates of access transistors Q 3 and Q 4 are connected to a word line 109. Figs. 21 to 23 are plan views of the structure of an SRAM, showing three stages in order from the bottom on the surface of the substrate, respectively. Fig. 24 is a cross-sectional view of the structure taken along the line A-A in Figs. 21 to 23. Referring to Figs. 20 to 24, a pair of driver transistors Q 1 and Q 2 and a pair of access transistors Q 3 and Q 4 are formed on a main surface of a p-type silicon substrate 148 of the memory cell. Driver transistor Q 1 includes a pair of source/drain regions 121 and 122 and a gate electrode 125. Driver transistor Q 2 includes a pair of source/drain regions 118 and 117 and a gate electrode 126. Access transistor Q 3 includes a pair of source/drain regions 119 and 120 and a gate electrode 109. Access transistor Q 4 includes a pair of source/drain regions 116 and 117 and a gate electrode 109. These transistors are n-type MOS transistors having source/drain regions formed on the main surface of p-type silicon substrate 148. Gate electrode 126 of driver transistor Q 2 is connected to source/drain region 120 of access transistor Q 3 through a contact 128. Gate electrode 126 of driver transistor Q 2 is connected to source/drain region 121 of driver transistor Q 1 through a contact 129. Gate electrode 125 of driver transistor Q 1 is connected to source/drain region 117 of access transistor Q 4 and source/drain region 117 of driver transistor Q 2 through a contact 127. A gate electrode 130 of a load transistor Q 5 is connected to a source/drain region 137 of a load transistor Q 6 through a contact 139. A gate electrode 131 of load transistor Q 6 is connected to a source/drain region 134 of load transistor Q 5 through a contact 138. A bit line 107 is connected to source/drain region 119 of access transistor Q 3 through a contact 146 and a bit line 108 is connected to source/drain region 116 of access transistor Q 4 through a contact 147. As stated above, in the memory cell of the conventional SRAM, four n-type MOS transistors are arranged on the silicon substrate and p-type thin film transistors are provided as loads above them. Such a memory cell is also described in US patent 5 001 539 forming the preamble of claim 1. A case where a p-type thin film transistor is used as a load of a memory cell in an SRAM has been described in IEDM 1990 Technical Digest pp. 477-480. Fig. 26 is a cross-sectional view of a typical structure of a thin film transistor used as load transistors Q 5 and Q 6 . The thin film transistor has a channel region 142 and a pair of source/drain regions 141 and 143 formed in a semiconductor layer such as polycrystalline silicon and a gate electrode 140 provided opposite to channel region 142 with an insulating layer interposed therebetween. Fig. 27 is a diagram showing a current characteristic of the thin film transistor. In such an SRAM, it is necessary to reduce an area occupied by each memory cell in order to increase the integration density of the memory cells. However, the conventional memory cell above had two problems to be described below. The first problem is that it is difficult to reduce an element isolation region between transistors making up the memory cell. Fig. 25 is a diagram showing by a model a cross-section of the structure of a LOCOS film 124 (Fig. 24) for insulating and isolating transistors from each other in the memory cell shown in Fig. 24. In this LOCOS film 152 (Fig. 25), regions X called "bird's beak" are formed at its both ends, which expand to the region where elements are formed, so that an isolation width W becomes larger than its desired value. For this reason, the width of the isolation region cannot be reduced, so that reduction in the size of the memory cell cannot be achieved. The second problem concerns a current handling capability ratio β of a driver transistor to an access transistor (= the current handling capability of the driver transistor/the current handling capability of the access transistor). If the current handling capability ratio β is small, data is destroyed when it is read out from a memory cell. This phenomenon will now be described below. Figs. 28(a) and (b) show two inverter circuits obtained by dividing the equivalent circuit of the memory cell shown in Fig. 20 in connection with the reading characteristic. In this case, load transistors Q 5 and Q 6 are not shown because the amount of the current flowing through these load transistors is little enough to be ignored compared with those of the access transistors and the driver transistors, so that is has no effect on the reading operation. The characteristic of reading from a memory cell is given from a change in voltage at one storage node obtained by fixing the bit line and the word line at Vcc and changing the gate voltage of the driver transistor (the voltage at the other storage node). Fig. 29(a) is a diagram showing the reading characteristic in a case where the current handling capability ratio β is large (about 3). The axis of abscissa represents a voltage at storage node 115 and the axis of ordinate represents a voltage at storage node 114. The curve α 1 represents the voltage change characteristic at storage node 114 in a case where the voltage at storage node 115 is changed. The curve γ 1 shows the voltage change characteristic at storage node 115 in a case where the voltage at storage node 114 is changed. The curves α 1 and γ 1 intersect each other at three points P 1 , P 2 and P 3 . At point P 3 , storage node 114 has "High" data stored, and storage node 115 has "High" data stored at point P 1 . Point P 2 is an unstable point and the condition at this point P 2 is not kept at the time of reading. In the figure, a region surrounded by a circle h is called "eye of a memory cell". As the current handling capability ratio β of the transistors is larger, the circle h becomes bigger and the reading operation is stabilized. In order to reduce the size of a memory cell, the size of an access transistor or a driver transistor is reduced. The access transistor or the driver transistor is reduced in size, for example, by shortening the gate length. If the transistor width of the access transistor is reduced to 1µm or less, a so-called narrow channel effect becomes significant, so that a threshold voltage Vth of the access transistor is increased. Fig. 29(b) shows the voltage change characteristic at the storage node in a case where the threshold voltage Vth of the access transistor is increased. In Figs. 29(a) and (b), Vcc- or Vcc-' corresponds to the threshold voltage Vth of the access transistor. As shown in Fig. 29(b), if the threshold voltage of the access transistor is increased, the curves α 2 and γ 2 intersect each other at one point P 2 only and the so-called "eye of a memory cell" region disappears. As a result, the stable points of the voltage at each storage node disappear, and data stored in the memory cell is destroyed at the time of the reading operation. For these reasons, the access transistor cannot be reduced in size even though the size of the driver transistor can be reduced. If only the driver transistor is reduced in size, the current handling capability ratio β of the both transistors becomes small, making the reading operation unstable. Therefore, it is an object of the present invention to reduce the size of a memory cell in an SRAM and to reduce an area of an element isolation region in such an SRAM. Such an object is solved by a semiconductor memory device according to the independent claim 1. Preferred developments of the invention are given in the dependent claims. In accordance with the present invention, the size of a memory cell can be reduced by forming on the main surface of the semiconductor substrate the pair of access transistors and one driver transistor among six transistors making up the memory cell and providing the remaining three transistors over them with the interlayer insulating layer interposed therebetween. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural plan view of a memory cell in an SRAM according to a first embodiment of the present invention. Fig. 2 is a structural plan view of an upper layer portion of the memory cell shown in Fig. 1. Fig. 3 is a structural plan view of a still upper layer portion of the memory cell shown in Fig. 2. Fig. 4 is a structural plan view of a still upper layer portion of the memory cell shown in Fig. 3. Fig. 5 is a structural cross-sectional view taken along the line D-D in Figs. 1 to 4. Fig. 6 is a structural cross-sectional view taken along the line H-H in Fig 2. Fig. 7 is a structural cross-sectional view taken along the line E-E in Fig 1. Fig. 8 is a structural cross-sectional view taken along the line G-G in Fig 1. Fig. 9 is a structural cross-sectional view taken along the line F-F in Fig 1. Fig. 10 is a structural cross-sectional view taken along the line I-I in Fig 3. Fig. 11 is an equivalent circuit diagram of the memory cell in the SRAM according to the first embodiment. Fig. 12 is an equivalent circuit diagram (a), (b) of two inverter circuits included in a flipflop circuit shown in Fig. 11. Fig. 13 is a diagram showing the characteristic curve of reading out data from the memory cell according to the first embodiment. Fig. 14 is a structural plan view of a memory cell in an SRAM according to a second embodiment of the present invention. Fig. 15 is a structural plan view of a still upper layer of the memory cell shown in Fig. 14. Fig. 16 is a structural plan view of a still upper layer of the memory cell shown in Fig. 15. Fig. 17 is a structural plan view of a still upper layer of the memory cell shown in Fig. 16. Fig. 18 is a structural cross-sectional view taken along the line J-J in Figs. 14 to 17. Fig. 19 is an equivalent circuit diagram of the memory cell in the SRAM according to the second embodiment. Fig. 20 is an equivalent circuit diagram of a memory cell in a conventional SRAM. Fig. 21 is a structural plan view of a memory cell in a conventional SRAM. Fig. 22 is a structural plan view of a still upper layer of the memory cell shown in Fig. 21. Fig. 23 is a structural plan view of a still upper layer of the memory cell shown in Fig. 22. Fig. 24 is a structural cross-sectional view taken along the line A-A in Figs. 21 to 23. Fig. 25 is a cross-sectional view of the structure in the vicinity of a LOCOS film used in isolating elements in a conventional memory cell. Fig. 26 is a cross-sectional view showing the structure of a typical cross section of a thin film transistor used as a conventional load transistor. Fig. 27 is a diagram showing an electrical characteristic of the thin film transistor shown in Fig. 28. Fig. 28 is an equivalent circuit diagram (a), (b) showing two inverter circuits obtained by dividing the flipflop circuit shown in Fig. 20. Fig. 29 is a diagram (a), (b) showing the characteristic curve of reading out data of a conventional memory cell. A memory cell according to a first embodiment includes pairs of access transistors Q 3 and Q 4 , driver transistors Q 1 and Q 2 and load transistors Q 5 and Q 6 . An equivalent circuit of this memory cell is equal to that shown in Fig. 39. The structure of the memory cell will now be described with reference to Fig. 20 and further to Figs. 1 to 10. The first embodiment will now be described. As shown in Fig. 11, in the memory cell according to the first embodiment, a pair of access transistors Q 3 and Q 4 and one driver transistor Q 1 are MOS transistors formed on the surface of a substrate and the other driver transistor Q 2 and a pair of load transistors Q 5 and Q 6 are thin film transistors. Figs. 1 to 4 are structural plan views of the memory cell and Figs. 5 to 10 are structural cross-sectional views of the memory cell. The memory cell according to this embodiment has a structure in which a plurality of polycrystalline silicon layers are stacked, forming a multilayer with interlayer insulating layers interposed therebetween. The structural plan views Figs. 1 to 4 show each layer in the plurality of stacked polycrystalline silicon layers in order starting with a lower layer. Referring to Figs. 1 to 10, a pair of access transistors Q 3 and Q 4 and one driver transistor Q 1 are arranged on a main surface of a silicon substrate 100. Access transistor Q 3 includes a pair of source/drain regions 31 and 32 and a gate electrode 33. Access transistor Q 4 includes a pair of source/drain regions 36 and 37 and a gate electrode 38. Driver transistor Q 1 includes a pair of source/drain regions 32 (21) and 22 and a gate electrode 23. These three transistors are n-type MOS transistors formed on the surface of the silicon substrate. The other driver transistor Q 2 and two load transistors Q 5 and Q 6 formed in upper layers of silicon substrate 100 are thin film transistors. Driver transistor Q 2 includes a pair of source/drain regions 26 and 27 formed in a polycrystalline silicon layer L2 and a gate electrode 28. Load transistors Q 5 and Q 6 are provided in a still upper layer over driver transistor Q 2 . In Fig. 3, load transistor Q 5 includes a pair of source/drain regions 47 and 41 formed in a polycrystalline silicon layer L4 and a gate electrode 43. Load transistor Q 6 includes a pair of source/drain regions 46 and 47 formed in polycrystalline silicon layer L4 and a gate electrode 48 (28). Gate electrode 48 which is gate electrode 28 is shared by load transistor Q 6 and driver transistor Q 2 . Bit lines 107 and 108 are provided above load transistors Q 5 and Q 6 . Bit line 107 is connected to source/drain region 31 of access transistor Q 3 through a contact 56. Bit line 108 is connected to source/drain region 37 of access transistor Q 4 through a contact 57. A contact 51 connects source/drain region 32 (21) shared by access transistor Q 3 and driver transistor Q 1 to gate electrode 28 (48) of driver transistor Q 2 and load transistor Q 6 . A contact 52 connects gate electrode 23 of driver transistor Q 1 to source/drain region 26 of driver transistor Q 2 . A contact 54 connects source/drain region 36 of access transistor Q 4 to gate electrode 43 of load transistor Q 5 . A contact 53 connects gate electrode 48 of load transistor Q 6 to source/drain region 41 of load transistor Q 5 . A contact 58 connects gate electrode 43 of load transistor Q 5 to source/drain region 46 of load transistor Q 6 . A description will now be made of the operation in reading from the memory cell according to the second embodiment. Fig. 12(a), (b) shows two inverter circuits divided in connection with the reading characteristic in the equivalent circuit of the memory cell shown in Fig. 11. Here, the first embodiment is different from the conventional technique in that the inverter circuit shown in Fig. 12(b) is a CMOS inverter circuit including two thin film transistors only. The reading characteristic of the memory cell is given by fixing bit line 107 and a word line 109a at Vcc and a word line 109b at GND. Fig. 13 shows a curve of a reading characteristic of the memory cell given in this way. Fig. 13 shows a reading characteristic in a case where the current handling capability ratio β of driver transistor Q 1 to access transistor Q 3 is small, i.e., in the order of 1.5. The axis of abscissas represents a voltage at a storage node 115 and the axis of ordinates represents a voltage at a storage node 114. In Fig. 13, a curve α 3 represents a voltage characteristic at storage node 114 when a voltage at storage node 115 of Fig. 12(a) is changed. A curve γ 3 represents a voltage characteristic at storage node 115 when a voltage at storage node 114 of Fig. 12(b) is changed. The curves α 3 and γ 3 intersect each other at three points P 1 , P 2 and P 3 . This memory cell is stabilized at the intersection P 1 or P 3 . At point P 1 , storage node 115 has "High" data stored, and storage node 114 has "High" data stored at point P 3 . The point P 2 is an unstable point and the condition at this point is not maintained in a reading operation. In the memory cell according to this embodiment, as the inverter circuit shown in Fig. 12(b) is a CMOS circuit, a voltage at each storage node rapidly changes from High level to Low level or from Low level to High level with a certain voltage (voltage of about 1/2Vcc) Accordingly, the voltage characteristic as indicated by the curve γ 3 is obtained, so that a large circle h called "eye of a memory cell" can be secured. Therefore, a stable operation can be performed in reading data from the memory cell. That is, even if the current handling capability ratio β-is small, the characteristic of a CMOS can be used by means of the n-type thin film transistor as the driver transistor and the p-type thin film transistor as the load transistor, thereby stabilizing the reading operation. In the operation of writing data into the memory cell, for example, in order to bring storage node 114 to High level, storage node 115 is brought to Low level and storage node 114 to High level by operating access transistor Q 4 only and bringing bit line 108 to Low level. In order to bring storage node 115 to High level, only access transistor Q 3 is operated and bit line 107 is brought to Low level, so that storage node 114 attains Low level and storage node 115 is set at High level. In this embodiment, the two access transistors Q 3 and Q 4 do not operate simultaneously. Accordingly, one bit line can be used as bit lines 107 and 108. A second embodiment is directed to a memory cell including a single bit line as stated above. As shown in Fig. 19, source/drain regions of a pair of access transistors Q 3 and Q 4 are connected to a common bit line 107. Six transistors making up the memory cell have the same structures as those in the second embodiment. Figs. 14 to 17 are structural plan views of the memory cell having a multilayered structure, showing each layer in order starting with a lower layer. Referring to Fig. 19, and further to Figs. 14 to 18, a pair of access transistors Q 3 and Q 4 and one driver transistor Q 1 are arranged on a main surface of a silicon substrate 100. One driver transistor Q 2 which is a thin film transistor is provided over it. Load transistors Q 5 and Q 6 which are thin film transistors are further provided over it. Furthermore, above it are provided one bit line 107 and a GND line 112 extending parallel to the bit line. Bit line 107 is connected to a source/drain region 31 of access transistor Q 3 through a contact 65 and is connected to a source/drain region 37 of access transistor Q 4 through a contact 66. In the figure, the same reference numerals designate the same elements as in the first embodiment. As stated above, if bit line 107 is used as one common interconnecting line, the other of the two heretofore used as bit lines can be employed as a GND line. Also, each memory cell can contact GND line 112 independently. Since a metal interconnecting line for a GND line in a conventional memory device was connected to a unit of a plurality of memory cells (for example, eight memory cells), there was a problem that the GND potential was likely to be raised in a memory cell far from this connection. However, the difficulty of the conventional art can be overcome as each memory cell can contact the GND line independently in accordance with this embodiment. Also as a modified embodiment, one GND interconnecting line may be provided for two memory cells adjacent to each other. In accordance with another aspect of the present invention, a stable operation of reading stored data as well as reduction in the size of a memory cell can be achieved with a structure in which three of the transistors making up the memory cell are thin film transistors stacked on the substrate.

Claims: A semiconductor memory device including a memory cell constituted by a pair of driver transistors (Q 1 , Q 2 ) of a first conductivity type and a pair of load transistors (Q 5 , Q 6 ) of a second conductivity type making up a flipflop circuit and a pair of access transistors (Q 3 , Q 4 ) of the first conductivity type, comprising: a semiconductor substrate (100) having a main surface; characterized by : a first group of transistors including said pair of access transistors (Q 3 , Q 4 ) and one (Q 1 ) of said driver transistors formed in the main surface of said semiconductor substrate; an interlayer insulating layer covering the surface of said first group of transistors; and a second group of transistors including the other (Q 2 ) of said driver transistors and said pair of load transistors (Q 5 , Q 6 ) formed on said interlayer insulating layer, each transistor in said first group of transistors being a MIS type transistor including source and drain regions (31, 32; 36, 37; 21, 22) formed in said semiconductor substrate (100), and each transistor in said second group of transistors being a thin film transistor including source and drain regions (26, 27; 41, 46, 47) formed in a semiconductor layer (L2, L4) on said interlayer insulating layer. The semiconductor memory device according to claim 1, wherein the other (Q 2 ) of said driver transistors included in said second group of. transistors includes source and drain regions (26, 27) formed in a first semiconductor layer (L2) on said interlayer insulating layer and each of said load transistors (Q 5 , Q 6 ) included in said second group of transistors includes source and drain regions (47, 41; 47, 46) formed in a second semiconductor layer (L4) above said first semiconductor layer (L2). The semiconductor memory device according to claim 2, wherein a gate electrode (48) of one (Q 6 ) of said load transistors included in said second group of transistors and a gate electrode (28) of the other (Q 2 ) of said driver transistors are formed of a common layer (L3), and said first semiconductor layer (L2) and said second semiconductor layer (L4) included in said second group of transistors are arranged opposing each other with said common layer (L3) interposed therebetween. The semiconductor memory device according to one of claims 1 to 3, further comprising: a first bit line (107) connected to one (31) of said source and drain regions formed in said semiconductor substrate included in one (Q 3 ) of said access transistors; and a second bit line (108) connected to one (37) of said source and drain regions formed in said semiconductor substrate included in the other (Q 4 ) of said access transistors. The semiconductor memory device according to one of claims 1 to 3, further comprising a common bit line (107) connected to one (31) of said source and drain regions formed in said semiconductor substrate included in one (Q 3 ) of said access transistors and to one (37) of said source and drain regions formed in said semiconductor substrate included in the other (Q 4 ) of said access transistors.

Inventors: KURIYAMA HIROTADA, KURIYAMA, HIROTADA, Kuriyama, Hirotada, c/o Mitsubishi Denki K.K. LSI
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1992
Main classification: H01L27
IPC codes: H01L27