Method of, and arrangement for, generating a clock signal from a biphase modulated digital signal

Abstract: A clock signal is generated, from a biphase modulated, digital signal, by means of two samples (TF, TB) per symbol interval, T. This pair of samples are spaced at about T / 4. The clock is generated by, firstly, shifting the pair of samples (TF, TB) until one of them (TF) is very close to the zero - crossing point of the biphase signal. The other sample (TB) will then be located at a maximum or minimum. During this procedure, the separation of the two samples remains fixed at T / 4. The separation is then made variable. In this way, TF can track the zero crossing point while TB remains at the maximum or minimum, despite jitter in the incoming signal.

Description: The invention relates to a method of generating a clock signal from a biphase modulated digital signal whose polarity is sampled in each symbol interval at a first and a second sampling instant at which instants the two polarity samples are compared with each other and a control signal in one sense is generated if there is equality of the polarity samples in response to which the two sampling instants are shifted relative to the biphase signal into a first direction, and if there is inequality of the polarity samples a control signal in the other sense is generated in response to which both sampling instants are shifted relative to the biphase signal into a second direction. A method of this type is known from EP-A-0 162 505 (PHN 11.019). A symbol interval having length T of a biphase-modulated signal always has a phase transition halfway the interval which phase transition is perceptible as a zero crossing if the maximum value of the biphase signal is positive and the minimum value is negative. At a distance of 1/4 T both to the left and right of this zero crossing the amplitude of the biphase signal presents a maximum (positive or negative) value and is a measure for the information content of the biphase signal in the symbol interval concerned. Hereinafter it will be assumed that the polarity of the maximum amplitude of the biphase signal is to be determined at a distance of 1/4 T to the left of the zero crossing. For the invention it does not matter at all whether this is effected to the left or right of the zero crossing. In order to be in a position to establish the polarity of the maximum amplitude of the biphase signal per symbol interval at a distance of T/4 to the left of the zero crossing, the biphase signal is to be sampled at the place of this maximum amplitude in each symbol interval. Since establishing the position of the maximum amplitude is much more difficult than establishing the position of the steep zero crossing, the biphase signal is sampled in each symbol interval at two instants which are mutually T/4 apart. If the second sampling instant coincides with the zero crossing, the first sampling instant will coincide with the maximum amplitude of which the polarity is to be determined. By comparing the two polarity samples with each other and shifting these instants slightly to the right when they are equal and slightly to the left when they are unequal, after a number of symbol intervals the position of the second sampling instant will come in the neighbourhood of the zero crossing. The time required to this end is called the adjusting time. If the second sampling instant then occurs slightly to the left of the zero crossing, the two polarity samples are equal and the two sampling instants shift to the right so that in the next symbol interval the second sampling instant ends up slightly to the right of the zero crossing, whereas the first sampling instant still occurs to the left of the zero crossing in the neighbourhood of the maximum amplitude. The polarity samples taken at these instants will then be different so that both instants will shift to the left and the second sampling instant will again end up to the left of the zero crossing in the next symbol interval, and so on. The two sampling instants continue to shift to the left and right retaining a mutual distance of T/4 once the second sampling instant has been situated in the neighbourhood of the zero crossing. The first sampling instant then presents a jitter extending across the step size with which both sampling instants shift back and forth. For example, in digital echo cancelling systems the jitter is required to have a maximum of one thousandth part of the symbol interval. Such a small jitter could be realised by selecting the step size to be equally small, whereas the adjusting time then becomes inversely proportionally large. This is undesirable. It is an object of the invention to provide a method according to which the first sampling instant does not present any more jitter after the adjusting time, without the adjusting time increasing. The method according to the invention is characterized in that the first sampling instant retains a fixed position relative to the biphase signal in dependence on an actual value and at least one previous value of the control signal, whereas the second sampling instant is shifted relative to the biphase signal. By determining the end of the adjusting time on the basis of an actual value and at least one previous value of the control signal, while the second sampling instant has reached the neighbourhood of the zero crossing, and by allowing this second sampling instant to move on the left and right of the zero, while the first sampling instant retains a fixed position relative to the biphase signal, it is achieved that the first sampling instant no longer presents any jitter. Even minor variations during the period of the biphase signal can be eliminated completely by the shifting of the second sampling instant. If these variations become too large, adjustments are again to be made during which adjustments the two sampling instants, mutually approximately 1/4 T apart, again shift until the second sampling instant has reached the neighbourhood of the zero crossing. The method according to the invention thus knows two situations: a first, dynamic adjustment state in which the two sampling instants have a mutual distance of approximately T/4, which first state of dynamic adjustment ends when the second sampling instant has reached the neighbourhood of the zero crossing, and a second, static adjustment state in which the first sampling instant retains a fixed position while the second sampling instant moves on the left and right of the zero. An embodiment of the method according to the invention is characterized in that the second sampling instant coincides with an instant from a group of instants which are predetermined relative to the first sampling instant. If the second sampling instant coincides with an instant from a group of predetermined instants, for example a, b and c, the second sampling instant is to coincide with instant b during the dynamic adjustment state. In the static adjustment state the second sampling instant can then move on the left and right of the zero by alternately coinciding with one of the instants a, b and c. The invention further relates to an arrangement for implementing the method, comprising: sampling means for sampling the polarity of the biphase modulated digital signal at the first and second sampling instants per symbol interval, comparator means coupled to the sampling means, for comparing the two polarity samples and generating in response thereto the control signal in one sense when the two polarity samples coincide and in the other sense when the two polarity samples differ, generator means coupled to the comparator means, for shifting the two sampling instants into the first direction relative to the biphase signal in response to the control signal in one sense and for shifting the two sampling instants into the second direction relative to the biphase signal in response to the control signal in the other sense. The arrangement according to the invention is characterized, in that the arrangement further includes control means for retaining the first sampling instant at a fixed position relative to the biphase signal in dependence on an instantaneous value and at least one previous value of the control signal and for shifting the second sampling instant relative to the biphase signal. A first embodiment of the arrangement according to the invention, wherein the sampling means have an input to which the biphase signal can be applied, a control input and an output, the comparator means have an input coupled to the output of the sampling means and have an output, the arrangement comprises a frequency controlled oscillator which has an input coupled to the output of the comparator means and has an output, the generator means are arranged for generating a pulse at the first and at the second sampling instant and have an input coupled to the output of the oscillator, a control input coupled to the output of the comparator means and have an output coupled to the control input of the sampling means, characterized in that the control means have a first input coupled to the output of the comparator means for receiving the control signal, a second input coupled to the output of the generator means for receiving the pulses, a first output coupled to the control input of the generator means for realising the coupling between the comparator and generator means, a second output coupled to the control input of the sampling means for supplying the pulse at the second sampling instant, and a memory circuit coupled to the first input, for generating a signal at the first output in dependence on an instantaneous value and at least one previous value of the control signal in response to which output signal the generator means generate the pulse at the first sampling instant with a fixed position relative to the biphase signal, and for generating a signal at the second output for supplying the pulse at the second sampling instant with a shifted position relative to the biphase signal. A second embodiment of the arrangement according to the invention is characterized in that the memory circuit comprises at least a combining circuit and a flip-flop, of which flip-flop an input forms the first input of the control means through the combining circuit, an output forms the first output of the control means through a logic circuit, and is coupled to the second output of the control means, and a clock input is coupled to the output of the generator means. The invention will be further explained on the basis of an exemplary embodiment represented in the drawing Figures in which the components denoted by like reference characters are identical in the Figures, in which: Fig. 1 shows the characteristic eye pattern of a biphase-coded signal; Fig. 2 shows a block diagram of a receiver for biphase-coded signals; Fig. 3 shows a block diagram of an exemplary embodiment of the arrangement according to the invention; and Fig. 4 shows a block diagram of an exemplary embodiment of the control means of the arrangement according to the invention. Fig. 1 shows the eye pattern of the biphase signal. In each symbol interval of length T a received biphase signal has a zero p that always occurs irrespective of the information content of the signal and a zero q that occurs only when the signal has specific information content. The second sampling instant T F is to coincide with the zero p so that at the time of the first sampling instant T B (which is approximately T/4 to the left of T F in the symbol interval) the information content of the biphase signal in the symbol interval concerned can be determined. In order to avoid that with a specific information content of the biphase signal T F coincides with the zero q, a false synchronisation detector can be used, as has been described in EP-A-0 162 505. This detector has been omitted from the exemplary embodiment for simplicity. In Fig. 2 the represented block diagram of a prior art receiver for biphase signals comprises a sampling circuit 1 to which the biphase signal is applied through input terminal 2 and which is connected to adjustable divider 3. Divider 3 generates the sampling instant signals destined for sampling circuit 1 at instants T B and T F . The polarity samples obtained at these instants are applied to comparator circuit 4 which, in response, generates a control signal for adjustable divider 3 and for a frequency controlled oscillator 5 (usually through low-pass filter 6). The oscillator signal originating from oscillator 5 is also applied to adjustable divider 3. If the frequency of the oscillator signal is higher, for example, by a factor of 16 than the symbol interval rate, the divider 3 divides this oscillator frequency by a factor of 15 or by a factor of 17 depending on the control signal. Consequently, the two sampling instants will shift to the left or to the right respectively, and after some time T F will be situated in the neighbourhood of the zero p. Subsequently, adjustable divider 3 will alternately continue to divide by 15 and 17 so that T F continues to move on the left and right of the zero p ("idle" state). T B continues to move along with T F at a specific distance therefrom and thus presents a jitter amounting to 1/16 of the symbol interval. Such a large jitter is undesirable. Sampling circuit 1 in Fig. 3 comprises decision circuit 20 whose input is connected to input terminal 2 for the biphase signal to be supplied. Decision circuit 20 decides at the sampling instants T B and T F , which are supplied via OR-gate 21, whether the biphase signal at these instants is positive (logic "one") or negative (logic "zero"). The two polarity samples are stored in the respective D flip-flops (DFF) 22 and (DFF) 23. The output of DFF 22 is connected to output terminal 7 on which the information content of the biphase signal appears. The outputs of the DFF 22 and DFF 23 constitute the outputs of sampling circuit 1 and are connected to the inputs of EXOR gate 30 of comparator circuit 4 which further includes a DFF 31 for the output signal of EXOR gate 30 to be stored. The output of DFF 31 constitutes the output of comparator circuit 4. The signal on this output has the logic value "one" if the two polarity samples are different and the logic value "zero" if they are equal and is applied through low-pass filter 6 to the frequency-controlled oscillator (VCO) 5 and to control means 10. VCO 5 generates a signal with a frequency that is higher by a factor of 16 than the symbol interval rate. Adjustable divider 3 connected to VCO 5 divides the oscillator frequency by a factor of 16, or by a factor of 15 or 17, depending on the control signals coming from the control means 10. Furthermore, adjustable divider 3 generates 16 equidistant pulses T1 to T16 per time period of the signal obtained by means of the divider. Pulse T5 (corresponding to the sampling interval T B ) is applied to OR gate 21, pulse T6 to the clock input of DFF 22 and pulse T12 to the clock input of DFF 31. The output of control means 10 is connected to OR gate 21 for the feeding of sampling instant T F and is connected to the input of DFF 40 for the storage of T F . The output of DFF 40 is connected to the clock input of DFF 23 and the clock input of DFF 40 is connected to VCO 5. This achieves that irrespective of the moment at which the sampling instant T F takes place, the associated polarity sample is correctly stored in DFF 23. Control means 10 comprises a memory circuit 50 having three inputs: step, direction and clock. Direction input is connected direct to the output of DFF 31 to receive the control signal; step input is coupled to this output by means of pulse generator 51 and divide-by-32 divider 52; and clock input is coupled to the adjustable divider 3 to receive pulse T13. Pulse generator 51 applies a single reset pulse to divide-by-32 divider 52 in response to every transition in the control signal and, after 32 pulses T12, divide-by-32 divider 52 applies a pulse to the step input so that this divide-by-32 divider is reset with each reset pulse coming from pulse generator 51. Memory circuit 50 has five outputs: LEFT, CENTRE, RIGHT, ÷15 and ÷17. LEFT output is connected to AND gate 53 which is furthermore coupled to adjustable divider 3 to receive pulse T8. CENTRE output is connected to AND gate 54 which is furthermore coupled to adjustable divider 3 to receive pulse T9 and RIGHT output is connected to AND gate 55 which is furthermore coupled to adjustable divider 3 to receive pulse T10. The three outputs of these three AND gates 53, 54 and 55 are connected to OR gate 56 whose output forms the output of the control means 10. Through this output sampling instant T F is generated which, in dependence on the output signal of memory circuit 50, coincides with pulse T8, T9 or T10 of adjustable divider 3. The ÷15 and ÷17 outputs are coupled to adjustable divider 3 which divides by a factor of 15, 16 or 17 in dependence on the output signal of the memory circuit 50. The operation of memory circuit 50 is represented in Table 1. Such a memory circuit 50 may be realised in various ways. A single exemplary embodiment in which flip-flops are used will be discussed with reference to Fig. 4. inputs outputs step, direction present state next state LEFT CENTRE RIGHT ÷15 ÷17 00 01 11 10 A B B A C 1 0 0 1 0 B B B A C 1 0 0 0 0 C C C B D 0 1 0 0 0 D D D C E 0 0 1 0 0 E D D C E 0 0 1 0 1 Table 1 is to be interpreted as follows. Supposing the present state is state C. Corresponding to this is an initial state of memory circuit 50 at which the CENTRE output has the logic value "one" (Fig. 3 shows that the second sampling instant T F then coincides with pulse T9). If, subsequently, the logic values "one" and "zero" are applied to the respective step and direction inputs, the next state will be state D. Corresponding to this is an initial state in which the LEFT output has the logic value "one" (T F then coincides with pulse T8). If, thereafter, the logic value "zero" is applied to the step input and direction input, the next state remains the state B, and so on. Needless to observe that the two sampling instants are shifted or not also in dependence on three or more different values of the control signal, in which case Table 1 and memory circuit 50 have to be extended accordingly. The operation of the exemplary embodiment represented in Fig. 3 is the following. The biphase coded signal is applied to input terminal 2 and sampled by sampling circuit 1 at the sampling instants T B and T F . T B coincides with pulse T5 from adjustable divider 3, and T F coincides with pulse T8, T9 or T10 depending on the initial state of the memory circuit 50. Assuming that the CENTRE output of this memory circuit has the logic value "one", T F then coincides with pulse T9 (state C in Table 1). The polarity samples taken at the two sampling instants T B and T F are stored in DFF 22 and DFF 23 respectively, and applied to EXOR gate 30 of comparator circuit 4. Let it be assumed that both T B and T F are situated to the left of point p of the eye pattern of the biphase signal, the two polarity samples will have the logic value "one" and EXOR gate 30 will produce an output signal having the logic value "zero" to be stored in DFF 31 and applied to VCO 5 through low-pass filter 6 and to control means 10. Consequently, the 16 x higher oscillator frequency of VCO 5 will be in synchronism with the symbol interval rate of the biphase signal. Since it has been assumed that memory circuit 50 is in state C, the two ÷15 and ÷17 outputs have the logic value "zero" and adjustable divider 3 divides by the factor of 16 in response thereto. During this operation a frequency occurs whose period is equal to the symbol interval of the biphase signal and adjustable divider 3 generates the equidistant pulses T1 to T16 in each period. The signal coming from DFF 31 and having the logic value "zero" is applied direct to the direction input of memory circuit 50 and to pulse generator 51 which generator will not generate a reset pulse for divide-by 32 divider 52 in response thereto, which divider as a result will assume the count 1 after clock signal pulse T12 is received if the previous count is assumed to have the value 0. Divider 52 will generate a signal having the logic value "one" only when the count 32 is attained. This is not yet the case and a signals having the logic value "zero" are applied to the step input as well as the direction input. From Table 1 it follows that the next state of memory circuit 50 is again state C so that the logic values of the five output signals do not change. Consequently, T F continues to coincide with pulse T9 and adjustable divider 3 continues to divide by the factor of 16, so that the two sampling instants do not shift relative to the symbol interval and the two polarity samples again have the logic value "zero". The only element that changes each next symbol interval is the count of the divide-by 32 divider 52 which is incremented each time by the value "one". After 32 symbol intervals this count attains the value 32 and counter 52 generates a pulse in response to which the logic value "one" is applied to the step input. Table 1 then shows that the next state of memory circuit 50 becomes state D in which the RIGHT output adopts the logic value "one". Consequently, T F will shift one pulse to the right (from T9 to T10), whereas T B relative to the symbol interval remains in place (because divider 3 continues to divide by a factor of 16 since the ÷15 and ÷17 outputs in state D generate the logic value "zero"). At these sampling instants the two polarity samples still have the logic value "one" due to which EXOR gate 30 through DFF 31 applies a signal having the logic value "zero" to control means 10. For 32 symbol intervals the count of counter 52 is incremented by the value "one", until this count has attained the value 32 in which case a signal having the logic value "one" is applied to the step input. Table 1 then shows that the next state becomes state E. In state E, RIGHT output retains the logic value "one" and ÷17 output also gets the logic value "one". Consequently, divider 3 divides the oscillator frequency of VCO 5 by a factor of 17 so that the two sampling instants relative to the symbol interval shift to the right. Two states may occur during this operation, state I in which the second sampling instant T F is still to the left of the zero p and state II in which T F has meanwhile adopted a position to the right of the zero p as a result of the shift to the right. In state I the polarity samples still have both the value "one" during the sampling instants that have shifted to the right, in response to which value EXOR gate 30 generates a signal having the logic value "zero". Consequently, memory circuit 50 adopts state D so that divider 3 starts to divide by 16 again. If counter 52 has attained the count of 32, memory circuit 50 again adopts state E and divider 3 divides by 17 so that the two sampling instants again move to the right relative to the symbol interval. This is continued until T F is situated slightly to the right of zero p, in which case state II is attained. In state II, T B is situated to the left and T F slightly to the right of zero p and the polarity samples taken at these instants have opposite values. Consequently, a logic "one" is applied to the direction input and a logic "zero" is applied to the step input and memory circuit 50 adopts state D: divider 3 then divides by 16 so that the two sampling instants are no longer shifted relative to the symbol interval. After 32 symbol intervals counter 52 attains the count 32 and a logic "one" is applied to both the step input and the direction input as a result of which the state C is attained: T F then shifts one pulse to the left and coincides with pulse T9, whereas T B remains in its place. If T F has now ended up to the left of zero p, state D will again be attained after 32 symbol intervals so that T F shifts to the right. If T F in state C is still on the right of zero p, the state B will be attained after 32 symbol intervals so that T F again shifts one pulse to the right and coincides with T8, so that T F has certainly ended up to the right of zero p. Subsequently, state C is again attained so that T F shifts to the right and so on. In this manner it is avoided that divider 3 is constantly to divide by 15 or 17 with T B also shifting. Once it has reached the neighbourhood of zero p, T F assumes an idle state (i.e. moving on the left and right of the zero by coinciding with pulse T8, T9 or T10), whereas T B remains in its place (by coinciding with T5, while the divider 3 constantly divides by the factor of 16). Not until T F is no longer situated in the neighbourhood of the zero p will the position of T B and T F be corrected by the modification of the divisor. As a rule, this will happen only sporadically. Fig. 4 shows an exemplary embodiment of the memory circuit 50 represented in Fig. 3, whose operation is described in Table 1. Memory circuit 50 comprises 6 combining circuits, that is to say, the ANDANDOR gates 70, 71, 72, 73, 74 and 75. An ANDANDOR gate is constituted by two AND gates which have each two inputs, whose outputs are connected to an OR gate, and thus has a first, a second, a third and a fourth input. The output signal of an ANDANDOR gate has the logic value "one" if from at least a single AND gate both inputs simultaneously receive a signal having a logic value "one". Naturally, an inverting input is then to receive a logic "zero". Memory circuit 50 further includes three DFFs 76, 77 and 78 whose clock inputs are coupled to divider 3 to receive pulse T13 and whose outputs form the LEFT output, the CENTRE output and RIGHT output respectively. The input of DFF 76, 77 and 78 is connected to the output of ANDANDOR gate 73, 74 and 75 of which a first input is connected to the output of DFF 76, 77 and 78 respectively. A second input (inverting) of each ANDANDOR gate 73, 74 and 75 is connected to a third input and to the step input and a fourth input is connected to the output of the ANDANDOR gate 70, 71 and 72 respectively. A first input of the ANDANDOR gate 70 is connected to the first input of ANDANDOR gate 73 and to a first input of ANDANDOR gate 71. A second input of the ANDANDOR gate 70 is connected to the direction input and to a second input (inverting) of both the ANDANDOR gate 71 and ANDANDOR gate 72. A third input of the ANDANDOR gate 70 is connected to the second input and a fourth input is connected to the first input of ANDANDOR gate 74 and to a fourth input of ANDANDOR gate 72. A third input of ANDANDOR gate 71 is connected to the second input (inverting) and a fourth input is connected to the first input of ANDANDOR gate 75 and to a first input of ANDANDOR gate 72 whose second input (inverting) is connected to a third input (inverting). Memory circuit 50 further comprises two AND gates 79 and 80 having each two inputs, one input of each AND gate 79, 80 being connected to the step input. The other input of AND gate 79 is connected to the LEFT output and the other input of the AND gate 80 is connected to the RIGHT output. The outputs of the respective AND gates 79 and 80 form the ÷15 and ÷17 outputs of the memory circuit 50. The operation as represented in Fig. 1 is the following. Let it be assumed that a signal having the logic value "one" is available at the CENTRE output at a specific moment (state C in Table 1) and signals having a logic value "zero" are applied to the step input and the direction input. Only the ANDANDOR gates 72 and 74 will then generate a signal having the logic value "one" because only the CENTRE output had the logic value "one". With pulse T13 a signal having the logic value "one" is then applied only to DFF 77 so that only the CENTRE output carries the logic value "one". The state then remains unchanged. Table I also shows the following: if both the step input and the direction input receive the logic value "zero" in state C, the next state will again be state C. If counter 52 attains the count 32, a pulse signal having the logic value "one" will be applied to the step input. As a result, the ANDANDOR gates 72 and 75 will generate a signal having the logic value "one" so that at the next pulse T13 only DFF 78 at the RIGHT output generates a signal having the logic value "one". This corresponds to the state D of Table 1: If a signal having the logic value "one" is applied to the step input and a signal having the logic value "zero" to the direction input in state C, the next state will be state D in which thus only the RIGHT output will generate a signal having the logic value "one".

Claims: Method of generating a clock signal from a biphase modulated digital signal whose polarity is sampled in each symbol interval at a first and a second sampling instant (T B ,T F ) at which instants the two polarity samples are compared with each other and a control signal in one sense is generated if there is equality of the polarity samples in response to which the two sampling instants are shifted relative to the biphase signal into a first direction, and if there is inequality of the polarity samples a control signal in the other sense is generated in response to which both sampling instants are shifted relative to the biphase signal into a second direction, characterized in that the first sampling instant retains a fixed position relative to the biphase signal in dependence on an actual value and at least one previous value of the control signal, whereas the second sampling instant is shifted relative to the biphase signal. Method as claimed in Claim 1, characterized in that the second sampling instant coincides with an instant from a group of instants predetermined relative to the first sampling instant. Arrangement for implementing the method of generating a clock signal from a biphase modulated digital signal as claimed in Claim 1, comprising sampling means (1) for sampling the polarity of the biphase modulated digital signal at a first and second sampling instants (T B ,T F ) per symbol interval, comparator means (4) coupled to the sampling means, for comparing the two polarity samples and generating in response thereto a control signal in one sense when the two polarity samples coincide and in the other sense when the two polarity samples differ, generator means coupled to the comparator means, for shifting the two sampling instants into a first direction relative to the biphase signal in response to the control signal in one sense and for shifting the two sampling instants into a second direction relative to the biphase signal in response to the control signal in the other sense, characterized in that the arrangement further includes control means (10) for retaining the first sampling instant at a fixed position relative to the biphase signal in dependence on an instantaneous value and at least one previous value of the control signal and for shifting the second sampling instant relative to the biphase signal. Arrangement as claimed in Claim 3, characterized in that the sampling means (1) have an input (2) to which the biphase signal can be applied, a control input and an output (7), the comparator means (4) have an input coupled to the output of the sampling means and have an output, the arrangement comprises a frequency controlled oscillator (5) which has an input coupled to the output of the comparator means and has an output, the generator means are arranged for generating a pulse at the first and at the second sampling instant and have an input coupled to the output of the oscillator, a control input coupled to the output of the comparator means and have an output coupled to the control input of the sampling means and in that the control means (10) have a first input coupled to the output of the comparator means for receiving the control signal, a second input coupled to the output of the generator means for receiving the pulses, a first output coupled to the control input of the generator means for realising the coupling between the comparator and generator means, a second output coupled to the control input of the sampling means for supplying the pulse at the second sampling instant, and a memory circuit (50) coupled to the first input, for generating a signal at the first output in dependence on an instantaneous value and at least one previous value of the control signal in response to which output signal the generator means generate the pulse at the first sampling instant with a fixed position relative to the biphase signal, and for generating a signal at the second output for supplying the pulse at the second sampling instant with a shifted position relative to the biphase signal. Arrangement as claimed in Claim 4, characterized in that the memory circuit comprises at least a combining circuit and a flip-flop, of which flip-flop an input forms the first input of the control means through the combining circuit, an output forms the first output of the control means through a logic circuit, and is coupled to the second output of the control means, and a clock input is coupled to the output of the generator means.

Inventors: RHEBERGEN GERTJAN, RHEBERGEN, GERTJAN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H04L25
IPC codes: H03M5, H04L7, H04L25