High electron mobility transistor having improved electron controllability

Abstract: First and second high-resistivity compound semiconductor channel layers (9,10) are formed between an undoped compound semiconductor layer (2) and a doped compound semiconductor layer (3) having an electron affinity smaller than the undoped compound semiconductor layer (2). The first high-resistivity compound semiconductor channel layer (9) is adjacent to the doped compound semiconductor layer (3), and has an electron affinity distribution that increases toward the undoped compound semiconductor layer (2). The second high-resistivity compound semiconductor channel layer (10) is located between the first high-resistivity compound semiconductor channel layer (9) and the undoped compound semiconductor layer (2), and has an electron affinity distribution that decreases toward the undoped compound semiconductor layer (2). A gate electrode (4) and cap layers (5) are formed on the doped compound semiconductor layer (3). Source and drain electrodes (6,7) are formed on the respective cap layers.

Description: BACKGROUND OF THE INVENTION The present invention relates to compound semiconductor devices such as a HEMT (high electron mobility transistor). A HEMT structure is now drawing much attention, which is a field-effect transistor utilizing a two-dimensional electron gas accumulated in a heterojunction interface. The HEMT structure is illustrated in Fig. 6. An undoped semiconductor layer 2 is formed on a substrate 1, and a doped semiconductor layer 3 having an electron affinity smaller than the layer 2 is formed on the layer 2. A gate electrode 4 is formed on the doped semiconductor layer 3. A source electrode 6 and a drain electrode 7 are formed on cap layers 5 that are formed on the doped semiconductor layer on both sides of the gate electrode 4. In this HEMT structure, all the donor impurities added to the smaller electron affinity doped semiconductor layer 3 are ionized, and electrons generated by this ionization are accumulated in the heterojunction interface with the larger electron affinity undoped semiconductor layer 2 to form a two-dimensional electron gas 8. The distribution of the electron gas 8 can he controlled by a voltage applied to the gate electrode 4, to enable control of a current flowing between the source and drain. Figs. 7(a) and 7(b) are energy band diagrams showing electron distributions D when no voltage is applied to the gate electrode 4 (Fig. 7(a)), i.e., the device is not in use, and when a certain negative voltage is applied (Fig. 7(b)). As shown in these figures, the distribution D of the two-dimensional electron gas 8 assumes a mountain-like shape having some spread which is larger when the negative voltage is applied to the gate electrode 4. The degree of expansion depends on the magnitude of the negative voltage. In other words, the center of gravity P of the electron distribution D goes farther away from the heterojunction interface as the negative voltage increases. Particularly in low-noise HEMTs in which a negative voltage is applied to the gate electrode to reduce the current, this phenomenon will deteriorate the electron controllability and make it difficult to realize satisfactory low-noise characteristics. The further prior art documents JP-A-1 014 972, JP-A-1 031 470 and EP-A-0 257 300 show election confinement using a graded composition of the active compound semiconductor layers. A similar principle is used in the present invention. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems in the art, and has an object of providing a high electron mobility transistor in which the center of gravity of the above-described electron distribution hardly moves. According to the invention, a high electron mobility transistor comprises: undoped compound semiconductor layer; doped compound semiconductor layer having an electron affinity smaller than the undoped compound semiconductor layer; a gate electrode and a pair of cap layers formed on the doped compound semiconductor layer; source and drain electrodes formed on the pair of cap layers, respectively; a first high-resistivity compound semiconductor channel layer formed adjacent the doped compound semiconductor layer and having an electron affinity distribution that increases toward the undoped compound semiconductor layer; and a second high-resistivity compound semiconductor channel layer formed between the first high-resistivity compound semiconductor channel layer and the undoped compound semiconductor layer and adjacent the former and having an electron affinity distribution that decreases toward the undoped compound semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of a high electron mobility transistor according to an embodiment of the present invention; Figs. 2 and 3 show a variation of the composition of first and second high-resistivity semiconductor layers; Figs. 4(a) and 4(b) are energy band diagrams of the high electron mobility transistor according to the embodiment; Fig. 5(a) is an enlarged energy band diagram of a part of Fig. 4(a); Fig. 5(b) is an energy band diagram of a part of a high electron mobility transistor according to a modification; Fig. 6 is a sectional view of a conventional high electron mobility transistor; and Figs. 7(a) and 7(b) are energy band diagrams of the conventional high electron mobility transistor. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 shows a high electron mobility transistor according to an embodiment of the present invention, in which the same parts as in the conventional device of Fig. 6 are represented by the same reference numerals and redundant descriptions therefor are omitted here. The main feature of this embodiment resides in that a first high-resistivity semiconductor channel layer 9 and a second high-resistivity semiconductor channel layer 10 are provided between the undoped semiconductor layer 2 and the doped semiconductor layer 3. The electron affinity of the first high-resistivity semiconductor channel layer 9 gradually increases toward the undoped semiconductor layer 2, and that of the second high-resistivity semiconductor layer 10 gradually decreases toward the undoped semiconductor layer 2. Each of the first and second high-resistivity semiconductor layers 9 and 10 has a composition of Al x In y Ga 1-x-y As, where x and y are determined, for example, as shown in Figs. 2 and 3. In Figs. 2 and 3, symbol d represents a position in the thickness direction of the first and second high-resistivity semiconductor channel layers 9 and 10, where d = 0 corresponds to the interface with the doped semiconductor layer 3 and d = d3 corresponds to the interface with the undoped semiconductor layer 2. The ordinate of Fig. 2 represents a mole ratio of aluminum, i.e., x, and the ordinate of Fig. 3 represents a mole ratio of indium, i.e., y. In the range of 0-d1, the composition takes a form of Al x Ga 1-x As. In the range of d1-d3, it takes a form of In y Ga 1-y As, where the mole ratio of indium, i.e., y, is maximum at a position d2. The position d2 corresponds to the interface between the first and second high-resistivity semiconductor channel layers 9 and 10. When added to GaAs, aluminum and indium serve to increase and decrease the potential, respectively. Therefore, as shown in an energy band diagram of Fig. 5(a), the position d2, where the mole ratio of indium is maximum, corresponds to the minimum position of a V-shaped portion. By providing the first and second high-resistivity semiconductor channel layers 9 and 10 in the above manner, the overall energy band takes a form as shown in Figs. 4(a) when no voltage is applied to the gate electrode 4, and it becomes as shown in Fig. 4(b) when a negative voltage is applied. As is understood from Figs. 4(a) and 4(b), the center of gravity P of the electron distribution D does not vary. As a result, when put into actual use, the device will have a superior electron controllability and low-noise characteristics. If it is difficult to produce the high-resistivity semiconductor channel layers 9 and 10 each having the continuous variation of the electron affinity, a generally V-shaped portion having a stepped variation may be provided as shown in Fig. 5(b). This is done by forming many layers having different compositions in each of the layers 9 and 10. In Fig. 1, the other layers may have the following compositions: undoped semiconductor layer 2, GaAs; doped semiconductor layer 3, n⁺-type AlGaAs; and cap layers 5, n⁺-type GaAs. According to the high electron mobility transistor having the above constitution, since the energy band structure in the electron accumulation layers assumes a generally symmetrical V shape, the center of gravity of the distribution of accumulated electrons does not move even if a negative voltage is applied to the gate electrode to raise the entire energy curve. As a result, the electron controllability and, therefore, noise characteristics can be improved. On the other hand, in the conventional device, the energy curve is steeper on the side of the doped semiconductor layer 3. Therefore, when the gate voltage is changed, it is considered that the energy curve varies only on the side of the substrate 1 and the center of gravity of the electron distribution is moved thereby. First and second high-resistivity compound semiconductor channel layers are formed between an undoped compound semiconductor layer and a doped compound semiconductor layer having an electron affinity smaller than the undoped compound semiconductor layer. The first high-resistivity compound semiconductor channel layer is adjacent to the doped compound semiconductor layer, and has an electron affinity distribution that increases toward the undoped compound semiconductor layer. The second high-resistivity compound semiconductor channel layer is located between the first high-resistivity compound semiconductor channel layer and the undoped compound semiconductor layer and is adjacent the former, and has an electron affinity distribution that decreases toward the undoped compound semiconductor layer. A gate electrode and cap layers are formed on the doped compound semiconductor layer. Source and drain electrodes are formed on the respective cap layers.

Claims: A high electron mobility transistor comprising: undoped compound semiconductor layer (2); doped compound semiconductor layer (3) having an electron affinity smaller than the undoped compound semiconductor layer; a gate electrode (4) and a pair of cap layers (5) formed on the doped compound semiconductor layer; source and drain electrodes (6,7) formed on the pair of cap layers, respectively; a first high-resistivity compound semiconductor channel layer (9) formed adjacent the doped compound semiconductor layer and having an electron affinity distribution that increases toward the undoped compound semiconductor layer; and a second high-resistivity compound semiconductor channel layer (10) formed between the first high-resistivity compound semiconductor channel layer and the undoped compound semiconductor layer and adjacent the former and having an electron affinity distribution that decreases toward the undoped compound semiconductor layer. The high electron mobility transistor of claim 1, wherein the electron affinity distributions of the first and second high-resistivity compound semiconductor channel layers are step-like distributions. The high electron mobility transistor of claim 1, wherein the first and second high-resistivity compound semiconductor channel layers have a composition of Al x In y Ga 1-x-y As, where x monotonously decreases to zero in the first high-resistivity compound semiconductor channel layer and y takes a maximum at a boundary between the first and second high-resistivity compound semiconductor channel layers.

Inventors: NAKAGAWA YOSHIKAZU, NAKAGAWA, YOSHIKAZU, NAKAGAWA, YOSHIKAZU, C/O ROHM CO., LTD.
Applicants: ROHM CO LTD, ROHM CO., LTD.
Application year: 1992
Main classification: H01L29
IPC codes: H01L21, H01L29