Binary to multilevel image data conversion

Abstract: When binary image pixel data is converted into multi-level pixel data, the values of multi-level pixel data are previously set in predetermined registers. A circuit is provided for deciding whether or not the values set in the register are written in memory (102) in accordance with the state of binary pixel data. N control circuits are provided in parallel, and N memory units (102a-102d) to be respectively connected to the control circuits are also provided. This simultaneously multi-levelizes N items of binary pixel data.

Description: The present invention relates to an image processing apparatus, and particularly to an image processing apparatus for converting input binary pixel data into multi-level pixel data. A multi-color printing apparatus which expands character information including color codes sent from a host computer or the like to an image in internal memory, and which then reads and outputs the image by printing is provided with separate memory units respectively corresponding to the three color components of Y (yellow), M (magenta) and C (cyan). Combination of the three color components enable multi-color display. However, when a color image with gradation is printed on the basis of the multi-level data obtained by showing each of the color components by multi-level data, i.e., by multi-levelizing each color component, not a binary image such as a character or the like is recorded by a limited small number of colors, there is the need for processing of assigning the data about each of the color components which indicates the specified color to the dots of the binary image and storing the data in memory. The processing thus requires much labor, and the total printing speed is decreased. German Patent Specification No. DE-A-3831817 discloses an image processing apparatus for converting first image data into second image data, the apparatus using a plurality of equally structured modules operating in parallel. International Patent Specification No. WO 90/02385 discloses a raster image color processor having a binary level conversion means for generating a desired first level and writing it in memory. The present invention has been achieved in consideration of the prior art, and a concern of the present invention is to provide an image processing apparatus for converting binary pixel data into desired multi-level pixel data at a high speed in image processing apparatus capable of handling both character and gradation images. In accordance with the present invention there is provided image processing apparatus as set out in claim 1. Further features and advantages of the present invention will become apparent from the following description based on the accompanying drawings and the claims depended thereto. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a drawing schematically showing the configuration of a memory read/write circuit in accordance with an embodiment of the present invention; Fig. 2 is a block diagram schematically showing the whole configuration of an image processing apparatus in accordance with the embodiment of Figure 1; Fig. 3 is a drawing showing the configuration of a binary/multi-level conversion unit in accordance with the embodiment of Figure 1; Figs. 4A to 4D are drawings for explaining the contents of binary/multi-level conversion processing in accordance with the embodiment of Figure 1; Fig. 5 is a timing chart for explaining the operation of the binary/multi-level conversion unit in accordance with the embodiment of Figure 1; Fig. 6 is a drawing showing the sectional structure of a multi-color printing apparatus; Fig. 7 is a drawing showing the state wherein image data is stored after binary/multi-level conversion; Fig. 8 is a flow chart of explaining the contents of the operations and processing of CPU in accordance with apparatus of Figure 6; Fig. 9 is a drawing showing the configuration of a binary/multi-level conversion unit in accordance with a second embodiment; Fig. 10 is a drawing showing the state wherein image data is stored after binary/multi-level conversion in accordance with the second embodiment; and Fig. 11 a drawing showing an example of the table used for indicating a background or a binary image by color numbers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments concern a multi-color printing apparatus. Fig. 6 shows the structure of a multi-color printing apparatus. In Fig. 6, a scanner section 711 has a laser output section (not shown) for converting the image signal supplied from a PWM (PULSE WIDTH MODULATION) section in a printer controller 700 into an optical signal, a polygon mirror 712 rotating at a constant speed, a motor (not shown) for rotating the polygon mirror 712 and an f/ lens (imaging lens) 713 and so on. The laser beam generated by the scanner section 711 is reflected by one side of the polygon mirror 712, and scans and exposes the surface of a photosensitive drum 715 through a reflecting mirror 714. Since the photosensitive drum 715 is rotated in the direction shown by an arrow in the drawing, a two-dimensional latent image is formed on the surface of the photosensitive drum 715. A primary charger 717, a total exposure lamp 718, a cleaner section 723 for recovering the toner remaining untransferred and a transfer pre-charger 724 are disposed around the photosensitive drum 715. Reference numeral 726 denotes a development unit for developing the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure. The development unit of the embodiment is configured as described below. Reference numerals 731Y, 731M, 731C and 731Bk respectively denote development sleeves which contact the photosensitive drum 715 so as to directly develop the image; reference numerals 730Y, 730M, 730C and 730Bk respectively denote toner hoppers for holding spare toners; and reference numeral 732 denotes a screw for conveying a developer. The sleeves 731Y to 731Bk, the toner hoppers 730Y to 730Bk and the screws 732 are disposed around the rotational shaft P of the development unit 726. The characters Y, M, C and Bk of the reference numerals respectively denoting the components of the apparatus show color components. Namely, "Y", "M", "C" and "Bk" show the color components of yellow, magenta, cyan and black, respectively. When a yellow toner image is formed, yellow toner development is performed at the position shown in the drawing. When a magenta toner image is formed, the development unit 726 is rotated around the shaft P shown in the drawing so that the development sleeve 731M in the magenta development portion is brought into contact with the photosensitive drum 715. A cyan or black toner image is formed by the same operation. Reference numeral 716 denotes a transfer drum for transferring the toner image formed on the photosensitive drum 715; reference numeral 719, an actuator plate for detecting the movement position of the transfer drum 716; reference numeral 720, a position sensor for detecting by approach to the actuator plate 719 that the transfer drum 716 is moved to a home position; reference numeral 725, a transfer drum cleaner; reference numeral; 727, a paper pressure roller; reference numeral 728, a destaticizer; reference numeral 729, and a transfer charger. These members 719, 720, 725, 727, 728 and 729 are disposed around the transfer drum 716. On the other hand, reference numerals 735 and 736 denote paper feeding cassettes for containing paper (paper sheet). In the embodiment, A4-size paper and A3-size paper are contained in the paper feeding cassettes 735 and 736, respectively. Reference numerals 737 and 738 denote paper feeding rollers for feeding paper from the cassettes 737 and 738, respectively, and reference numerals 739, 740 and 741 denote timing rollers for timing the feed of paper and conveyance thereof. The paper supplied and conveyed through the above members is guided by a paper guide 490, is wound on the transfer drum 716 while the tip thereof is held by the gripper described below, and is then subjected to the image-forming process. The selection of paper feeding cassette 735 or 736 is determined by the indication from a printer controller 700 so that the selected paper feeding roller alone is rotated. Reference numeral 550 denotes a drum rotation motor for synchronously rotating the photosensitive drum 715 and the transfer drum 716. Reference numeral 750 denotes a separation claw for separating the paper which electrostatically adheres to the transfer drum 716 therefrom after the image forming process. Reference numeral 742 denotes a conveyor belt for conveying the paper separated, and reference numeral 743 denotes an image fixing section for fixing the image to the paper conveyed by the conveyor belt 742. The image fixing section 743 has a pair of heat pressure rollers 744 and 745. In the above constitution, the paper wound on the transfer drum 716 is successively subjected to the image forming processes for the respective color components. When the image forming process for the last color component is completed, the paper subjected to transfer treatment is separated from the transfer drum 716 by the separation claw 750, is conveyed to the image fixing section 743 by the conveyor belt 742 and is then subjected to fixing treatment. The paper is then discharged to the outside of the apparatus. The structure for printing shown in Fig. 6 is referred to as "printer engine section" hereinafter. Fig. 2 is a block diagram showing the configuration of the printer controller 700 of the embodiment. In Fig. 2, reference numeral 100 denotes a CPU for controlling the printer controller 700 and the whole printing apparatus; and reference numeral 101 denotes a memory read/write circuit (described in detail below). Reference numeral 102 denotes a memory section for storing multi-level image data, the memory section being also described in detail below. Reference numeral 103 denotes main memory comprising an ROM for storing as a program the operating and processing procedure of the CPU 100 and an RAM used as a work area. Reference numeral 104 denotes a data input section for inputting printing data from an external host computer or the like, and reference numeral 105 denotes font memory for storing data for generating various font patterns. Namely, in the embodiment, data for drawing the outline of a character is stored in the font memory 105 so that the inside the outline drawn is painted to generate a character pattern. Like in a generally manner, a character pattern itself may be stored. Reference numeral 106 denotes a console panel for giving various indications; and reference numeral 107 denotes an RGB/YMCBk conversion section for converting R, G, B data into Y, M, C data and generating the image data about the black component Bk by under color removal. Conversion of the R, G, B data into Y, M, C, Bk is generally known and is thus not described below. However, the RGB/YMCBk conversion section 107 is operated under control of the CPU 100. For example, the operation when an image is recorded in the order of Y, M, C and Bk by the printer engine section shown in Fig. 6 is performed according to the following procedure: The RGB/YMCBk conversion section 107 first generates data about the component Y on the basis of the RGB data sent from the memory section 102 and then outputs the data to a PWM section 108. The PWM section 108 converts the multi-level data about the component Y supplied into an analog signal, and compares the analog signal with a chopping wave to generate a pulse signal having a width corresponding to the value of the multi-level data. The pulse signal is output to the printer engine section 109 (refer to Fig. 6). After the component Y is completely recorded for one sheet of paper, the component M is recorded. The components C and Bk are then recorded. When the recording of the component Bk is completed, the image is fixed to the paper, and the paper is discharged to the outside. Although the embodiment concerns a case where a gradation image is reproduced by the PWM section, a gradation image may be formed by another known technique such as a dither method, an error diffusion method or the like. In addition, although the embodiment concerns a laser beam printer as an example of printing apparatuses, the present invention is not limited to this. For example, the present invention can be applied to various printers such as an ink jet printer, heat transfer printer, a wire dot printer, an LED printer and the like. The contents of the operation of the embodiment configured as described above are briefly described below. Character code data, image data and control code data are sent as printing data from the host computer. The pixel data in the image data includes R, G, B data, and data about each of the color components is sent with 8 bits. Namely, data about a single pixel comprises 8 x 3 (= 24) bits. The input data (24 bits) of the pixels are successively stored in the memory section 102. On the other hand, in the case of the character code data, the host computer sends a command to specify the print color of the character before the character code sequence is output. The character is printed with the color based on the input command to specify the character color unless a new command to specify the character color is sent. The output color of the character is not specified only by the host computer, and the output color may be specified from the console panel (not shown). When image data is received, an image is formed in accordance with the above procedure, while when the character code data is received, a character is printed by the following method: When the character code data is received, the CPU 100 generates a character pattern on the basis of the data stored in the font memory corresponding to the character code. At this time, it is an important point that a single pixel of the character pattern comprises one bit to form a binary image. Namely, the character pattern in which a single pixel comprises one bit must be converted into a multi-level character pattern in which a signal pixel comprise 8 x 3 bits. Otherwise, the character pattern to be printed with the color designated by the memory section 102 cannot be expanded. For example, when the host computer gives instructions to record a character with a color of R = 32, G = 64 and B = 128, the pixel "1" of the character patter generated must be written as R = 32, G = 64 and B = 128 in the memory section 102. However, since the character pattern generated has many pixels, the conversion processing takes much time if the processing is performed for each of the pixels. In the present invention, this problem is solved by the memory read/write circuit 101. The CPU 100 sets R, G, B (8 bits each) data which expresses the character color designated by the host computer or the console panel, as described below. The generated binary character pattern is expanded as a multi-level image of the type in which the character of the corresponding color can be printed by simply writing the pattern in the memory section 102 through the memory read/write circuit 101. However, the embodiment concerns an example where the binary character pattern is written in units of four pixels, not units of one pixel. This enables an increase in the processing speed. Although the embodiment employs the units of four pixels, the units of five pixels or more may be employed. Fig. 1 shows details of the configuration of the memory read/write circuit 101 and the memory section 102 in the embodiment. In Fig. 1, arrows each indicate the flow of a signal or information, and numerals noted at intermediate positions of the arrows each indicate the number of bits which form the signal or information. Reference numeral 1 denotes a timing signal generation circuit which is started by a start signal 2 or a read/write (R/W) signal 3 output from the CPU 100 shown in Fig. 2 to generate various memory read/write timing signals. Reference numeral 11 denotes a binary/multi-level conversion signal which is activated by the CPU 100 when binary data is converted into multi-level data, i.e., when a character pattern is written in the memory section 102. When the image data received from the host computer is written in the memory section 102, the binary/multi-level conversion signal 11 is inactivated. As shown in the drawing, the memory section 102 comprises four RAM 102a, 102b, 102c and 102d. The RAM 102a to 102d are positioned in the same address space. In the RAM 102a are stored data about the pixel 0, the pixel 4, ... the pixel 4i. In this case, i shows 0 or an integer . If the values of the R, G, B color components (8 bits each) of the pixel n (n > 0) are shown by R n , G n , B n , the data about the pixel 4, R 4n , G 4n , B 4n , is stored in the RAM 102a. Similarly, data R 4n+1 , G 4n+1 , B 4n+1 , data R 4n+2 , G 4n+2 , B 4n+2 and data R 4n+3 , G 4n+3 , B 4n+3 are stored in the RAM 102b, 102c and 102d, respectively. In Fig. 1, reference numerals 8a, 8b, 8c and 8d denote the memory read/write signals for the RAM 102a, 102b, 102c and 102d, respectively, output from the timing signal generation circuit 1. The data is read in a high (H) level and written in a low (L) level. Reference numeral 4 denotes a buffer for the CPU 100 to read data from the memory section 102. Reference numeral 5 denotes a binary/multi-level conversion unit which converts the binary data supplied into multi-level data when the binary data about the character pattern is stored in the memory section 102. The converted multi-level data is written in each of the RAM 102a, 102b, 102c, 102d through data buses 9a, 9b, 9c, 9d, respectively. Reference numeral 10 denotes an address counter which outputs the address 6 supplied from the CPU 100 under control of the timing signal generation circuit 1. The address counter 10 loads the address by a counter load signal 14 and counts it by a count signal 15. The counter load signal 14 and the count signal 15 are also supplied to the binary/multi-level conversion unit 5. Signals 13a, 13b, 13c and 13d are byte enable signals showing one of 4 bytes, or 32 bits, on the data bus 7, which is made enable by the CPU 100. The byte enable signals are respectively denoted by BE0, BE1, BE2 and BE3 hereinafter. The enable signals BE0, BE1, BE2 and BE3 correspond to the RAM 102a, 102b, 102c and 102d, respectively. Reference numerals 16a, 16b, 16c and 16d denote write enable signals for the RAm 102a, 102b, 102c and 102d, respectively. The timing signal generation circuit 1 outputs the memory read/write signals respectively corresponding to the write enable signals 16a, 16b, 16c and 16d. Fig. 3 shows details of the configuration of the internal circuit of the binary/multi-level conversion unit 5. The drawing shows the configuration of a circuit corresponding to the RAM 102a alone, i.e., binary/multi-level conversion for only a single pixel. Since the configurations of the ARM 102b, 102c and 102d corresponding to the other three pixels are the same as that shown in Fig. 3, they are not shown and described below. Although, in Fig. 3, the bit supplied on the data bus 7 is D0 (LSB), the bits are respectively shown by D1 to D3, not D0, in the configuration of the circuit of binary/multi-level conversion for the other three pixels. In Fig. 3, reference numeral 201 denotes a counter which is cleared by the counter load signal 14 output from the timing signal generation circuit 1 and which counts the address by the counter signal 15. However, the frequency of the count signal is at least 3 times that of the clock with which the CPU 100 transmits data to the memory read/write circuit. Reference numerals 202a, 202b, 202c respectively denote 8-bit registers for setting desired data therein by the CPU 100. The registers 202a, 202b and 202c are described in detail below. When the binary pixel data about a character pattern or the like is "1', the multi-level data (8 bits) about the components R, G and B after conversion are set in the registers 202a, 202b and 202c, respectively. Reference numeral 203 denotes a selector for selecting one of the output 213a, 213b and 213c of the registers 202a, 202b and 202c on the basis of the output signals 211 and 212 of the counter 201. Reference numeral 203 also denotes a selector for selecting the data 7 (undermost 8 bits of 32 bits of the data bus) output from the CPU 100 or the output 210 from the selector 203 by the binary/multi-level conversion signal 11. The output of the selector 204 is supplied to a data bus 9a. The data on the data bus from the CPU 100 is connected directly to the RAM 102a in preparation for the case where the printing data received is image data. Namely, in the case of image data which needs not to be subjected to binary/multi-level conversion, data D 0 to D 7 on the data bus 7 may be written in the RAM 102a as it was. Hence data D 8 to D 15 , data D 16 to D 23 and data D 24 on the data bus are respectively supplied to the selectors 204 in the binary/multi-level conversion circuits for the other three pixels. Reference numeral 207 denotes an AND circuit for obtaining the logical product of the binary/multi-level conversion signal 11 and the byte enable signals BEO. Reference numeral 206 denotes an invertor circuit for inverting the binary/multi-level signal 11. Reference numeral 208 an AND circuit for obtaining the logical product of the data D0 (LSB) in the data bus 7 and the output signal 214 of the invertor circuit 206. Reference numeral 209 denotes an OR circuit for obtaining the logical sum of the output 215 and 216 of the AND circuits 207 and 208. The operation of the binary/multi-level conversion unit 5 of the embodiment configured as described above is described below with reference to Figs. 1, 3, 4 and 5. Fig. 4 is a drawing showing an example of the binary/multi-level conversion processing of the embodiment, and Fig. 5 is a timing chart explaining the operation of the embodiment. Fig. 4B shows an example of the value (8 bits) of each color component after binary/multi-level conversion, which is designated by the host computer or the console panel. In Fig. 4C, the color components R, G, B with the same number correspond a single pixel, and numbers 0, 1, 2 and 3 shows storage in the RAM 102a, 102b, 120c and 102d, respectively. The data corresponding to four pixels of each of the components R, G and B is in the same address, and is shown by R0 to R3, G0 to G3 or B0 to B3. The CPU 100 first sets 8-bit data indicating the gradation values of the color components R, G and B obtained when pixels in the bit state "1" are subjected to multi-level conversion in the registers 202a, 202b and 202c, respectively. In this example, R = 32, G = 64 and B = 128 are set, as shown in Fig. 4B. The same data is also set in the registers 202a to 202c in the circuit for binary/multi-level conversion corresponding to the RAM 102b to 102d, respectively. The CPU 100 outputs a binary pattern (4 bits = 4 pixels) to be expanded on the memory 102 to lower 4 bits of the data bus 7. Fig. 4A shows an example of the data. The data shown in Fig. 4A represents that the first binary pixel is "1", the second and third binary pixels are each "0", and the fourth binary pixel is "1". As described above, the data D1 indicating the state of the second pixel is supplied to the AND circuit 208 in the circuit for binary/multi-level conversion for the RAM 102b, and the data D2 and D3 are supplied to the AND circuits in the circuits for binary/multi-level conversion for the RAM 102c and 102d, respectively. The CPU 100 then outputs the start signal 2 to the timing signal generation circuit 1, and brings the read/write (R/W) signal 3 into the write state and the binary/multi-level conversion signal 11 into the low (L) level so that the binary/multi-level conversion unit 5 starts the binary/multi-level conversion operation. The timing of the start is shown by S1 in Fig. 5. The timing signal generation circuit 1 outputs the counter load signal 14 (S2). This causes the address counter 10 to receive the address 6 supplied from the CPU 100 and the counter 10 of the binary/multi-level conversion unit 5 to be cleared (S3). The selector 203 in the binary/multi-level conversion unit 5 selects the output of the register 202a, i.e., the gradation data about the component R, and outputs the data to the selector 204 when the output 211 and 212 of the counter 201 are in the logical levels (0, 0), respectively. When the logical levels of the output signals are made (0, 1) by counting up the counter by 1, the output of the register 202b, or the gradation data about the component G, is selected and output. When the logical levels of the signals are made (1, 0) by further counting up by 1, the output of the register 202c, or the gradation data about the component B, is selected and output. The selector 204 selects the data bus 7 from the CPU 100 when the multi-level conversion signal 11 is in the high (H) level, and selects and outputs the output 210 of the selector 203 when the signal 11 is in the low (L) level. A more detailed description is made. The address 12 input to the memory units 102a to 102d shows the value "N" loaded from the CPU 100. Since the counter 201 is cleared by the counter load signal 14, the output signals 211 and 212 of the counter 201 are (0, 0). The output of the register 202a, or the gradation data about the component R, is thus output as the output 210 of the selector 203 (S4). At this time, the AND circuit 207 is closed. The AND circuit 208 is opened when the data of D0 bit of the data bus from the CPU 100 is "1". As a result, the OR circuit 209 is opened to output the write enable signal 16a. When the binary data shown in Fig. 4A is set, the write enable signals 16a and 16d are output so that the data is written in the RAM 102a and 102d, respectively. The timing signal generation circuit 1 then outputs the memory read/write signals 8a and 8d corresponding to the write enable signals 16a and 16d, respectively, and writes the gradation data about the component R which has been previously set (S5). The read/write signals 8b and 8c corresponding to the write enable signals 16b and 16c, respectively, are not output so that the data already stored in the memory units is left (refer to Fig. 4D). The timing signal generation circuit 1 then outputs the count signal 15 (S6). The address counter 10 and the counter 201 in the binary/multi-level conversion unit 5 are counted up by "1" when receiving the count signal 15 so that the address of the RAM 102a to 102d becomes N+1, and the output 211 and 212 of the counter 201 become (0, 1) (S7). As a result, the output of the register 202b, or the gradation data about the color component G, is output from the selector 204 (S8). Similarly, the memory read/write signals 8a and 8b are output, and the gradation data about the component G is written in each of the RAM 102a and 102d (S9). When the same processing is performed for the memory of the address N+2, the CPU 100 finishes the memory write operation for four pixels (S11). Fig. 7 shows the data stored in the RAM 102a to 102d in the memory section 102 when the values of the components R, G and B of the pixel n are shown by R n , G n and B n , respectively. When the CPU 100 writes any desired data without multi-level conversion processing (for example, when background data is written, or when image data is input from the host computer or the like), the level of the binary/multi-level conversion signal 11 is made "H". This causes 32 bits in the data bus 7 to be connected to the memory section 102. In other words, when image data is stored in the memory section 102 by the CPU 100, the 8-bit components R of the first, second, third and fourth pixels are transmitted as data D0 to D7, data D8 to D15, D16 to D23, and D24 to D31, respectively. The components G and B are transmitted in the same manner. Since the level of the binary/multi-level conversion signal 11 is made "H", the selector 204 in each of the circuits of binary/multi-level conversion in the binary/multi-level conversion unit 5 selects 8 bits in the data bus 7 from the CPU 100. This permits the background color or the like to be freely changed. At this time, the AND circuit 208 in the binary/multi-level conversion unit 5 is closed, and the write enable signals 16a, 16b, 16c and 16d corresponding to the byte enable signals 13a, 13b, 13c and 13d, respectively, output from the CPU 100 are output. The timing signal generation circuit 1 performs write processing once and then completes the processing. As described above, in the embodiment, the gradation data on each of the color components R, G and B after conversion is previously set when binary data is converted into multi-level data. At this time, only the binary data on pixels of "1" are converted into the multi-level data designated. In addition, in the embodiment, since the four binary pixels are simultaneously converted into multi-level pixels, the binary/multi-conversion is speeded up. In addition, although the embodiment concerns the example in which the four pixels are processed in the binary pixel unit, if the number of the RAM in the memory section 102 is 32, and if 32 binary/multi-level conversion circuits are provided, binary/multi-level conversion using all bits in the data bus 7 can be made. When expansion processing of multi-level data for one page is completed, the CPU 100 transmits the image data stored in the memory section 102 to the RGB/YMCBk conversion section 107. When the image data is read from the memory section 102, the data is read in units of 8 bits from each of the RAM 102a to 102d in the memory section 102 through the buffer 4. In the embodiment, since the data bus 7 has 32 bits, pixel data for four pixels is read by one read processing. However, since data about only one of the three color components is read by one read processing, the CPU 100 performs three times of read processing to read the R, G, B data for four pixels. The RGB/YMCBk conversion section 107 contains a buffer memory having a predetermined capacity so as to receive the R, G, B data for four pixels sent from the CPU 100, generate multi-level data about the recording color components designated by the CPU 100 and output the data to the PWM section 108. A description will now be made of the contents of the operation of the CPU 100 until a character pattern is obtained on the basis of the character codes contained in the received printing data and is expanded in the memory section 102 with reference to the flow chart shown in Fig. 8. The program corresponding to the flow chart shown in Fig. 8 is stored in the ROM in the main memory 103. Character pattern expansion processing corresponding to a single character code is described below for the sake of simplification of the description. In Step S301, color data (each color having 8 bits) of a binary image of a character or the like after conversion is received from the host computer or the console panel. In the next Step S302, the gradation values (8 bits each) of the color components R, G and B for reproducing the specified color are set in the registers 202a to 202c in the binary/multi-level conversion unit 5. In Step S303, a font pattern corresponding to the character code received from the host computer is generated and is written in the memory section 102 in units of 4 pixels, or 4 bits. As described above, bits of "1" in the four bits are converted into the R, G, B data having the gradation values designated and are then written in the memory section 102. In Step S305, a decision is made as to whether or not all font patterns are completely expanded. If it is decided that the pattern of one character is not completely expanded, the flow returns to Step S304. When the pattern of one character is completely expanded, the processing is finished. When a control command to change the character color is sent from the host computer, the CPU 100 changes the multi-level data to be set in the registers 202a to 202c in order to record a subsequent character pattern with the changed color. As a result, the hue of a character can be changed from any desired position of a single page. When a character code and image data (R, G, B data each having 8 bits) are sent, the hue of a character alone can also be changed on the printer side. <Second Embodiment> Although, in the above embodiment, multi-level data about R, G, B are expanded in the memory section 102, and are converted into data about the recording color components by the RGB/YMCBk conversion section 107 in the recording step, data on the color components Y, M, C and Bk may be expanded directly in the memory section 102. In this case, the RGB/YMCBk conversion section 107 is unnecessary. Fig. 9 shows the configuration of the circuit of the binary/multi-level conversion unit 5 in the memory read/write circuit 102 according to a second embodiment. The second embodiment is different from the first embodiment shown in Fig. 3 in only the point that the number of the registers for setting the gradation data about the color components therein during binary/multi-level conversion is increased by one. The reason for increasing the number of the registers by one is that the four recording color components Y, M, C, Bk are recorded in the second embodiment, while the three color components R, G, B are recorded in the first embodiment. Namely, in Fig. 9, the gradation data (8 bits) about the components Y, M, C and Bk are set in registers 202a', 202b', 202c' and 202d', respectively. Since a selector 203' selects the output of one of the four registers and outputs the data selected, a signal of only 2 bits may be used as a selection signal. Namely, the signals 211 and 212 output from the counter 201 in the first embodiment may be used as they were. If the logical levels of the signal lines 211 and 212 are expressed by (a, b), when the logical levels are (0, 0), (0, 1), (1, 0) and (1, 1), 8 bits are selected and output from the registers 202a', 202b', 202c' and 202d', respectively. However, in the second embodiment, when a request for one writing is generated from the CPU 100, the binary/multi-level conversion unit 5 must perform four writing operations. This can be achieved by increasing the counting clock frequency of the counter 201 to at least four times that supplied to the CPU 100. If the values of the recording color components n are shown by Y n , M n , C n , Bk n , the multi-level data about each of the recording color components is written in the RAM 102a to RAM 102d in the memory section 102 in the state shown in Fig. 10. However, the binary data "0" of pixels of a character pattern or the like are not written in the RAM 102a to 102d, like in the first embodiment. When the values of the components Y, M, C and Bk of a desired color are previously written in all of the RAM 102a to 102d in the memory section 102, a character of a desired color can be recorded with a background of a desired color. The background color is designated by the host computer or the console panel 106. When the CPU 100 receives indications of the background color, the RAM 102a to 102d may be filled (painted out) with the values of each color component for reproducing the color specified. Thus this processing is not described below. However, the function of the binary/multi-level conversion unit 5 of the aforementioned first or second embodiment is employed for speeding up the processing of painting the background color. Namely, the multi-level data of each of the color components for reproducing the background color is set in the registers 202a to 202c or 202a' to 202d', all the lower four bits of the data bus 7 are made "1" and written. This causes four pixels of the background image to be written by one write processing, thereby speeding up the processing. In the second embodiment, since data is stored in the form of Y, M, C and Bk in the memory section 102, as shown in Fig. 10, the RGB/YMCBk conversion section 107 in the first embodiment need not be provided. The CPU 100 thus may transmit the data in the memory section 102 directly to the PWM section 108. If the component Y is recorded by the printer engine section 109, the first address A 0 of the memory section 102 is accessed to output color component data Y 0 to Y 3 , which is then transmitted to the PWM section 108. The data about unrelated color components is skipped, and the color component data Y 4 to Y 7 at the address A4 is transmitted to the PWM section 108. After the data about the component Y is completed transmitted, data about the color components M, C and Bk are transmitted in this order. The processing for storing a binary image in the memory section 102 by the CPU 100 in the second embodiment is substantially the same as that in the first embodiment shown in Fig. 8. However, in Step S302, the data about each of the color components Y, M, C and Bk for reproducing the specified color is set in the registers 202a to 202d. The other steps are the same as those shown in Fig. 8 and thus are not described below. As described above, the first and second embodiments permit binary data to be converted into multi-level data having the gradation specified only by writing the binary data if the gradation value of the multi-level data is previously set in a predetermined register. The processing by the CPU can thus be simplified and speeded up. In addition, in the above-described first and second embodiments, since a plurality of binary pixels can be simultaneously converted into multi-level pixels, the processing can be significantly speeded up. Further, in the first and second embodiments, the console panel 106 is used as an example of means for setting gradation data in the registers 202a to 202c or the registers 202a' to 202d', and the user directly sets the values of gradation data in the registers. However, data about the color components to be set is data in a level which is recognized by the CPU or the like, and is thus data which cannot be easily understood by human beings. A desired color may be thus numbered so that data about each of the color components can be set in the registers indirectly by specifying the number of a desired color. In this case, a table in which the value of a corresponding color component is stored in a color code may be prepared. This table is preferably stored, for example, in EEPROM or the like because the contents registered are not lost by power breakout, and the user can freely register a new color. Alternatively, a color may be specified by using a L*a*b* color specification space which can be easily understood by human beings. In this case, a program for realizing a operation expression used for converting into R, G, B or Y, M, C may be previously stored. The memory for storing image data therein may be either a static RAM or dynamic RAM. In a dynamic RAM, an attempt can be made to speed up the processing in any one of the fast page, nibble and static column modes because continuous three addresses are accessed. In addition, in the first and second embodiments, binary pixel data is transmitted by four signal lines of bits D0 to D3 in the data bus 7, and a circuit for binary/multi-level conversion is provided for each of the bits. However, since the multi-level data set in the register 202a in the conversion circuit for processing bit D0 is completely the same as that in the register 202a in each of the circuits for bits D1 to D3, the registers 202a to 202c or 202a' to 202d' may be one and the same. This decreases at least the number of the registers and can thus simplify the configuration of the circuit. Further, although four pixels are simultaneously processed in the above embodiments, the number of pixels to be processed may be changed. Particularly, when the number of pixels to be processed is a multiple of 4, for example, when processing is performed in units of eight pixels, means for latching 8 pixels (8 bits) set from the CPU 100 is provided so that after the lower 4 pixels of the latched 8 pixels are processed, the counter 201 is cleared, and the latched bits are shifted by 4 bits and then subjected to the same processing. Further, although the above embodiments concern a multi-color printing apparatus as an example, the present invention can of course applied to a single-color printing apparatus. The apparatus can be applied to a printing apparatus, and any other apparatuses for converting binary image data into multi-level image data. For example, the present invention can be applied to an apparatus for displaying a gradation image on a display such as CRT or the like. Further, although the above embodiments concern an example using the PWM section 108 and the laser printer for finally outputting an image, present invention is not limited to this. This is because examples of means for generating a gradation image, which can be used in the present invention, include the dither method, the error diffusion method and the like, and examples of printers which can be used in the present invention include a heat transfer printer, a wire dot printer, an ink jet printer and the like. As described above in the embodiments, the gradation values of a binary image or a desired color thereof can be set from the console panel 106. If the host computer simply receives information indicating a monochromatic binary image, the user can set a desired density or color by operating the console panel of the printer. As a result, only a character in the printing data sent can be printed with the density or color specified by the user.

Claims: An image processing apparatus for converting first image data into second data by means of a plurality N ≥ 2 of simultaneously working converting means and memories, characterised by: supply means for supplying each bit of N bit words (D0-D3) of binary first image data to a corresponding one of N binary/multi-level conversion means (5); N memory units (102a-102d) having the same address space for storing N groups of simultaneously processed multi-level pixel data; setting means (202a-202c) for setting multi-level data in each of said N conversion means to convert each bit (D0...D3) of received binary data having a predetermined level (1) into multi-level data according to the setting command; said N binary/multi-level conversion means (5) outputting multi-level data set by said setting means (202a-202c); means for writing the multi-level data output from the N binary/multi-level conversion means in a respective one of said N memory units at the same address (N, N+1...); and control means (209, 1) for deciding whether or not said writing means is energized. Apparatus according to claim 1, wherein said setting means comprise registers (202a-202c) and wherein a control unit (CPU 100) is adapted to set the multi-level data in said registers. Apparatus according to claim 1 or claim 2, wherein said control means (209) is adapted to energize said writing means when the binary data (D0...D3) supplied to the binary/multi-level conversion means assumes a first logical state (1), and to deenergize said writing means when the binary data supplied to the binary/multi-level conversion means assumes a second state (0). Apparatus according to any one of the preceding claims, wherein the multi-level data can be manually set by said setting means. Apparatus according to any one of the preceding claims, further comprising: read means for reading the multi-level pixel data stored in said N memory units; and image forming means for forming a visible image on the basis of the multi-level pixel data read. Apparatus according to any one of claims 1 to 5, wherein each said setting means is adapted to set multi-level data representing each of M color components, each of said N binary/multi-level conversion means successively outputting the multi-level pixel data about each of said M color components set by said setting means on the basis of a bit of binary data. Apparatus according to any preceding claim, further comprising: read means for reading the multi-level data stored in said N memory units; and image forming means for forming a color visible image on the basis of the read multi-level data of each color component. Apparatus according to claim 6, wherein said image forming means is a color printer. Apparatus according to claim 6, and comprising: M registers holding the multi-level data about M color components set by said setting means; a data bus having at least N bits; input means for inputting N bits of binary data parallel from said data bus; and N conversion means for converting the input binary data into multi-level pixel data, wherein the conversion means comprises: pulse signal generation means for successively generating pulse signals in a number corresponding to at least the number M of said color components each time binary data is input by said input means; count means for counting the number of pulses generated from said pulse signal generation means, said count means being reset when binary pixel data is input by said input means; output means for selecting one of said M registers on the basis of the number of pulses counted by said count means and for outputting the multi-level data of the color component held by the selected register to the memory unit; and output means for outputting a signal indicating whether or not writing in the memory unit is permitted in accordance with the state of the binary pixel data in said N items of binary pixel data. Apparatus according to claim 6, wherein said M color components for reproducing a color are red, green and blue. Apparatus according to claim 6, wherein said M color components for reproducing a color are yellow, magenta, cyan and black.

Inventors: OKAMOTO YOSHIFUMI, OKAMOTO, YOSHIFUMI, OKAMOTO, YOSHIFUMI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: G06K15
IPC codes: G06T5, G06T1, H04N1, G06K15, B41J5, G06T9, B41J2