Single chip microcomputer

Abstract: A single chip microcomputer comprises a central processing unit CPU (2), a on-chip RAM (3), a on-chip ROM (5), a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU(2) with the RAM (3) and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU (2) with the RAM (3) and passing address data corresponding to the data passed through the third bus SDBUS. The CPU (2) has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM (3) where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM (3) has a memory cell array (31), a bank address control circuit connected to the fourth bus BABUS, for generating a real address according to the contents of the bank specifying register BP (BP0, BP1), and a selection circuit (37) for selecting the real address generated by the bank address control circuit, or the address provided through the second bus ABUS.

Description: The present invention relates to a single chip microcomputer, and particularly to a high-speed single chip microcomputer which is compact and has a register bank function to form a high-performance system. MICROPROCESSORS AND MICROSYSTEMS, vol. 13, no. 9, November 1989, London, GB, pages 607-620; I. HAY et al.: "TRON-compatible 16/32-bit microprocessor" (abbreviated "D1" hereinafter) and WESCON CONFERENCE RECORD, vol. 31, 1987, Los Angeles, US, pages 1-8; J. WAINWRIGHT et al.: "Register banks boost 16/32-bit CPU performance" (abbreviated "D2" hereinafter) concern the same microprocessor, designated as model HD641016 (abbreviated H16). According to the title of document D1 and the abstract thereof, document D1 discloses a 16/32-bit microprocessor, that is a 16-bit microprocessor which internally has a 32-bit structure. According to page 608 of document D1, in particular fig. 1 thereof and the description relating thereto, this microprocessor has a two-layered internal bus structure which, among others, connects the CPU with on-chip RAM. The section "CPU overview" on page 608 in connection with fig. 2 on page 609 indicates that the on-chip RAM can be organized in two register files supporting two modes of operation, one of which is a global bank mode for high-speed context switching. The section "register architecture" on page 608 of D1 indicates that the RAM supports a maximum of 16 register banks, where each bank comprises 16 general-purpose registers, with 32-bit per register, and where all general-purpose registers can be used as either data registers, address pointers or index registers. The section "global bank mode operation" on pages 608, 609 of document D1 explains that, for overcoming the problem that an interrupt stacking procedure presents a major overhead reducing system performance because of the considerable amount of time involved, in the global bank mode for the ON-chip RAM, the RAM can be configured as 2, 4, 8, or 16 global banks. A global bank is essentially a work space that is associated with a particular task. The currently selected bank is identified by the global bank number GBNR. Any global bank can be selected at any time by suitably programming the GBNR. When the processor switches tasks, a new work space is specified via the change global bank number (CGBN) instruction. This instructions pushes the current value of the GBNR onto the stack, and sets the GBNR to the new value. When the original task is resumed, the corresponding GBNR is retrieved from the stack by the pull global bank number (PGBN). This so-called fast context switching is considered particularly effective for dealing with interrupts and for task switching in multi-tasking systems. As the register banks of the H16 are supported internally, and therefore no reference to external memory is necessary, this procedure is fast. In fig. 19 and the description relating thereto on pages 618, 619 of document D1 a typical system extension of the H16 microprocessor is shown where a ROM, a SRAM and a DRAM are connected to the H16 microprocessor. With respect to the bus structure according to document D1, fig. 18 of D1 only shows an address bus, and fig. 19 shows an address/data bus. As mentioned above, document D2 relates to the same microprocessor as described in document D1. Document D2 explains on page 1, left column, last paragraph that the H16-microprocessor is a 16/32-bit microprocessor, such that it has a 32-bit internal structure and a 16-bit external structure. According to the section "Register Banks" on page 5, right column of D2, the H16 unifies CPU registers and an on-chip RAM in a single 1K bite RAM. The H16 uses a 32-bit internal RAM data bus. As outlined in D2 on page 3, left column, last paragraph to the first paragraph in the right column, the CPU communicates with the outside word via a 16-bit multiplexed address/data bus. In summary, D1/D2 disclose a single chip microcomputer having the features according to the preamble of claim 1. EP-A-0 202 848 (abbreviated "D3" hereinafter) discloses according to the abstract thereof a microcomputer having a RAM 12 and a CPU 11 mounted on a single chip and connected by a bus line BUS. The bus line BUS is indicated in fig. 6 of document D3, and also in fig. 3 thereof. The connection "EBL" between RAM 12 and CPU 11 in fig. 3 of document D3 is not a bus, but an extended portion EBL of the bit lines of the RAM, as outlined in detail on page 5, line 29 to page 7, line 11 of document D3. In particular, page 6, lines 16 to 32 of document D3 discloses that a connecting portion of the RAM 12 and a common bus BUS are the same as usually used but, in document D3, in each pair of bit lines in the RAM, the ends opposite to the connecting portion are extended and connected via gates G to each bit position of the internal registers in the CPU 11. In this manner, the save and recapture of the data of the internal registers of the CPU are carried out directly via the extended portion EBL of the bit lines, without going via the common bus BUS. In other words, document D3 suggests a direct hardware-wired access of the CPU to the RAM. This access is provided by the hardware-wired EBL. However, such hardware-wired connection like the EBL disclosed in document D3 where one wire is used to directly connect a bit position in the CPU with a corresponding bit position in the RAM, can only be used for this particular purpose. This is in marked contrast to a bus which, as any person skilled in the art knows, designates a set of shared lines for exchange of digital words, which set of lines is shared by different devices. As illustrated in Fig. 3 of D3, bit lines BL, BL of the memory are extended to internal registers of the central processor unit. The connecting portion 10 is provided therebetween. One context can be quickly replaced by another context. However, there is no address bus for the connecting portion 10. Absent the address bus, the entirety of the register set has to be saved or restored at once. This corresponds to a typical hardwired implemented task switch. There are only two modes, i.e., a saving mode or a restoring mode, so that this is utilized only for the purpose of task switching. The user can not freely make use of register banks in the memory. For example, a part of one register bank cannot be accessed unless all the information in the current bank is released from the register set. Also, many compilers make use of parts of registers in order to transfer parameters from one function to another function. The arrangement according to D3 is not suited for this purpose. The technical background of the present invention will be briefly outlined below. General purpose microcomputers (MCUs) and microprocessors (MPUs) used for built-in control devices usually employ a register bank function to process interrupts at high speed or to deal with multitasking and multiprogramming systems. The MCUs and MPUs usually incorporate a set of general purpose registers (for example, eight 16-bit registers), a program counter, and a processor status word. These registers are selected by a user program and used for holding various data such as operation results and program statuses. When an interrupt occurs to execute an interrupt processing program, or when a request (task switch) of executing an urgent program arises under a multitask environment, or when a subroutine call occurs for shifting control from a main program to a subroutine program during the execution of a program, the MCUs and MPUs temporarily suspend the presently executing program and start a different program. At this time, data held in the registers must be temporarily saved in another location (usually, an external memory), and data necessary for the different program must be newly read from the outside and set in the registers. After the different program is completed, the saved data must be restored in the registers to resume the suspended program. If the MCUs and MPUs have no register bank function, the contents of the registers must be saved in the external memory, or in a RAM in the case of single chip MCUs. Generally, the external memory is accessible only at low speed, so that it takes a very long time for saving and restoring data of the registers to and from the external memory. This is a bottleneck for the built-in control devices that must quickly respond to an interrupt request in real time, and deteriorates system reliability. To solve the problem and improve system performance, the MCUs and MPUs often employ the register bank function. The register bank function involves several sets of general purpose registers which are built in the processor. Each set comprises, for example, sixteen 16-bit general purpose registers. If the register bank function uses eight register banks, eight sets of general purpose registers, i.e., 128 (8 x 16) 16-bit general purpose registers must be prepared. These general purpose register sets (register banks) are properly switched from one to another when an interrupt or a task switch occurs, to shorten an interrupt response time or a task switching time and improve system performance. When it is necessary to save and restore the contents of one general purpose register set due to an interrupt or a task switch, the register bank function is very useful to eliminate saving the contents of the general purpose register set into the external memory at slow speed and slowly restoring the data from the external memory. The register bank function internally switches the general purpose register sets from one to another at high speed without using the slow-speed external memory. Thus, the register bank function improves a register bank switching speed and shortens an interrupt and task switch handling time. Figure 1 shows a single chip microcomputer employing the conventional register bank function, and Fig. 2 shows a CPU core disposed in the single chip microcomputer. In Fig. 1, the single chip microcomputer 100 comprises the CPU core 101, a on-chip RAM 103, a on-chip ROM 105, a bus controller 107, an interrupt controller 109, a timer 111, a serial I/O 113, etc. These elements send and receive data through a system bus SYSBUS (including an address bus ABUS and a data bus DBUS) in the chip. Data communication with the outside of the chip is carried out through the bus controller 107 and an I/O pad. In Fig. 2, the CPU core 101 incorporates a plurality of general purpose register sets RF1 through RF8 forming register banks. These register sets are connected to a plurality of internal data buses IDBUS1 through IDBUS3 in the CPU core 101, so that data are transferred and processed between the register sets RF1 to RF8 and an ALU (arithmetic and logic unit) 125, etc. It is important for efficiently processing data in the CPU core 101 that the register sets RF1 to RF8 are accessible from a plurality of the data buses IDBUS1 to IDBUS3. Generally, the number of ports of a memory that forms the register sets is at least three, i.e., two for reading and one for writing. When another writing port is added to provide four ports in total, data processing efficiency will be improved. Accordingly, the register sets are usually formed from a RAM having three or four ports. The CPU core 101 also includes a bank specifying register 127 for specifying one register bank (general purpose register set) to use, a processor status word 128 for storing the statuses of the CPU, and a program counter 129 for storing the address of a program presently executed. The bank specifying register 127 holds the number of the register bank presently used for executing the program, i.e., the register 127 represents which bank is currently used. Switching the register banks from one to another is carried out by rewriting the bank specifying register 127. After the present program is suspended and the bank specifying register 127 is rewritten, the general purpose register set corresponding to the newly specified number starts to be used. From this moment, the previously used register set will not be used. The contents of the previously used register set, however, will be preserved. When an interrupt occurs, the contents of a general purpose register set are saved as follows: (1) The contents of the processor status word, program counter, and bank specifying register are saved into an external memory (stack) through the system bus. (2) The bank specifying register is updated to specify another general purpose register set to be used. Once the interrupt process is completed, the original program is resumed in the following manner: (1) The previously saved data of the program counter, processor status word, and bank specifying register are restored from the external memory through the system bus. This method eliminates to save and restore the contents of the general purpose register set to and from the external memory through the system bus at slow speed, and instead, enables the general purpose register sets in the CPU to be switched from one to another at high speed.In these days, requirements for functions of the MCUs and MPUs for built-in control devices are increasing. As a result, the number of register banks is increasing from around 4 to 8 banks to 16, 32, 64, and even 256 banks. As the number of the register banks increases, the conventional register bank method has raised the following problems.In designing a multiport memory, a space or silicon area occupied by a unit memory cell increases in proportion to the number of ports of the memory because the number of transistors and wiring increase in proportion to the number of the ports. Namely, the multiport general purpose register set inevitably needs a large space.If the number of banks is around four, the silicon area problem is not too severe even if the bank involves large memory cells, because the total number of memory bits needed is not so large (if the size of each general purpose register set is 16 bits x 16 registers, 1024 bits in total for four banks). In this case, the multiport memory does not cause serious trouble in terms of the die area.When the number of the banks increases, the number of bits of each memory cell proportionally increases, and the area of the multiport memory becomes not ignorable. In addition, the multiport memory involving a large number of bits is difficult to design, consumes a lot of power, and operates at slow speed. The multiport memory of large size, therefore, is not preferable in LSI designing.The conventional register bank memories must use multiport memory cells, so that, when the number of register banks is increased, a chip space greatly increases and large electric power is consumed. In addition, the large-scale multiport memory is difficult to design and its operation speed is slow to limit a chip operation speed. Further, the conventional register bank memory is exclusively used for register banks, so that, when only one register set is used without using the register bank function, the other unused register sets will be wasteful.When the MCUs and MPUs execute a program written by a high-level language such as C, the register bank function can be used to switch to a subroutine program from a main program. At this time, the main program frequently passes data as arguments over to the subroutine program, or the subroutine program returns operation results to the main program. It is advantageous if part of the data is shared by (transferred between) register banks when one register bank is switched to another due to the subroutine call. The conventional register banks, however, are formed from different general purpose register sets, i.e., physically different storage elements, so that data are hardly shared by the register banks.Namely, the single chip microcomputer having the conventional register banks has the following drawbacks: (1) Increasing the number of the register banks drastically increases chip space and power consumption and limits a chip operation speed. (2) When the register bank function is not used, unused register sets will be wasteful. (3) It is difficult to realize a mechanism for transferring data between the register banks. SUMMARY OF THE INVENTION The object of the invention is to provide a single chip microcomputer which efficiently uses chip space and is more flexible. According to the invention, a single chip microcomputer has the features recited in claim 1. Preferred embodiments of the invention are indicated in the dependent claims 2-8. If there is a request of executing a different program, the CPU of the single chip microcomputer suspends a presently executing program, saves data held in the CPU through the exclusive-use data bus into a region of the RAM specified by an address provided through the bank address bus, starts the different program, completely executes the different program, restores the saved data into the CPU through the exclusive-use data bus from the region of the RAM specified by the address provided through the bank address bus, and resumes the suspended program. The CPU includes (1) a general purpose register set for holding operation data, (2) a program counter for holding the address of a presently executing program, (3) a processor status word register for holding the statuses of the CPU, and (4) a bank specifying register. When data are saved and restored to and from a register bank defined in the RAM, an address held in the bank specifying register (4) is provided to the bank address bus. At the same time, the general purpose register set (1), or the program counter (2) and processor status word register (3) are selectively connected to the exclusive-use data bus. A value in the bank specifying register to be provided to the bank address bus may be smaller than the total number of bytes of the general purpose register set, so that mapping regions of different register banks secured in the RAM may partly overlap one upon another. In the single chip microcomputer according to the invention, the bit width of the exclusive-use data bus (SDBUS) is wide, and the bank address bus (BABUS) transfers address data corresponding to data transferred through the bus SDBUS. These buses SDBUS and BABUS are disposed between the CPU and the RAM, so that data are transferred between the CPU and the RAM at high speed. The CPU may have one or a small number of data memories (RFs) serving as general purpose register sets for providing internal data to the bus SDBUS. The CPU also has the program counter (PC) and program status word (PSW). Data processing in the CPU is carried out with use of these registers. Data in the RAM are mapped into the register sets RFs of the CPU through the bus SDBUS. Data in different locations in the RAM prepare different data in the register sets RFs of the CPU. Since the mapping is carried out at high speed, i.e., since data are transferred between the register sets RFs of the CPU and the RAM at high speed, it seems as if the CPU incorporates a large number of register sets RFs (register banks). When the register banks are switched from one to another, the contents of the register set RF are saved and restored through the bus SDBUS, which transfers the data between the RAM and the register set RF at high speed. The CPU may have only one or a small number of the general purpose register sets, program counter, and processor status word, so that the register sets will not occupy large space because the register sets have multiple ports. In addition to the bank specifying register BP for specifying a register bank number, the CPU incorporates a bank address control circuit. According to data held in the bank specifying register BP, the bank address control circuit produces the address of a mapping area in the on-chip RAM where data to and from the CPU are stored, and provides the address to the bus BABUS. The bank address control circuit also provides an instruction to read or write the general purpose register sets, program counter, and processor status word. The single chip microcomputer according to the invention may set the start addresses (byte addresses) of mapping regions at intervals each being smaller than the size (total number of bytes) of the register set RF. The invention may properly set start addresses so that mapping regions in the RAM for storing data of different register sets RFs may partly overlap one upon another. This enables the different register banks to share data. When the register banks are switched from one to another, data can be partly passed over from one register bank to another. This method easily realizes many register banks without increasing chip space. When different register banks are overlapped in the RAM, they can share the same data, to achieve a parameter sharing function used by a subroutine call. These and other objects, features and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a single chip microcomputer employing a register bank function according to a prior art; Fig. 2 is a schematic view showing a CPU core mounted on the single chip microcomputer according to the prior art; Fig. 3 is a schematic view showing a single chip microcomputer according to a first embodiment of the invention; Fig. 4 is a schematic view showing a CPU core of the single chip microcomputer according to the first embodiment of the invention; Fig. 5 is a schematic view showing a general purpose register set disposed inside the CPU core of the single chip microcomputer according to the first embodiment of the invention; Fig. 6 is a schematic view showing a on-chip RAM of the single chip microcomputer according to the first embodiment of the invention; Fig. 7 is a memory map of the on-chip RAM of the single chip microcomputer of the invention, with mapping regions for the register set overlapping between different register banks (n=3 and m=4); Fig. 8 is a memory map of the on-chip RAM of the single chip microcomputer of the invention, with mapping regions for the register set overlapping between different register banks (n=6 and m=4); Fig. 9 is a schematic view showing a CPU core of a single chip microcomputer according to a second embodiment of the invention; and Fig. 10 shows a state of the on-chip RAM after the completion of the saving process. DETAILED DESCRIPTION OF THE EMBODIMENTS The embodiments of the invention will be explained with reference to the drawings. Figure 3 shows a single chip microcomputer according to the first embodiment of the invention. The single chip microcomputer 1 comprises a CPU (central processing unit) core 2, a on-chip RAM (data memory) 3, a on-chip ROM (program memory) 5, a bus controller 7, an interrupt controller 9, a timer 11, and a serial I/O 13. These elements receive and transmit data through a 32-bit system bus SYSBUS (involving a 16-bit address bus ABUS (second bus) and a 16-bit data bus DBUS (first bus)) disposed in the chip. Data to and from the outside of the chip are passed through a bus controller 7 and an I/O pad. According to one of the features of the invention, the CPU core 2 is connected with the RAM 3 through exclusive-use buses, which include a 64-bit bidirectional data bus SDBUS and an 8-bit bank address bus BABUS for indicating an address in the RAM 3. Figure 4 shows the inside of the CPU core 2. The CPU core 2 includes a general purpose register set RF (made of sixteen 16-bit registers), an ALU 25, three 16-bit internal data buses IDBUS1 to IDBUS3, a decoder/control circuit 21, a controller 23, a program counter PC, a processor status word PSW, etc. The decoder/control circuit 21 decodes instructions and controls the CPU core 2 as a whole. The controller 23 serves as an interface to the system bus SYSBUS, to read instructions and data necessary for operating the CPU core 2 and provide necessary data to the system bus SYSBUS. The general purpose register set RF is connected to the three 16-bit internal data buses IDBUS1 to IDBUS3 and to the 64-bit data bus SDBUS. The program counter PC holds the address of a program which is presently executed. The processor status word PSW defines the internal statuses of the CPU. The program counter PC and processor status word PSW are both connected to the data bus SDBUS. The CPU core 2 also includes a bank pointer (bank specifying register) BP and a bank address control circuit. The bank pointer BP indicates the bank number of a presently used register bank specified by an instruction from the controller 23. The bank address control circuit controls an address to be provided to the bank address bus according to a value held in the bank specifying register. The bank address control circuit also provides an instruction to read or write the program counter PC, processor status word PSW, and register set RF, as well as an address to read or write the register set RF. These instructions and address data provided by the bank address control circuit and bank pointer BP are passed through the bank address bus BABUS and used to access the RAM 3. In this way, the CPU core 2 has two data routes, i.e., the system bus SYSBUS and exclusive-use data bus SDBUS. The system bus SYSBUS is used for passing normal addresses and data, the bank address bus BABUS for passing a bank number, and the data bus SDBUS for exclusively passing data saved from or restored to the register set RF, program counter PC, and processor status word PSW. When the CPU core 2 normally processes data, the register set RF transmits and receives data to and from the ALU 25, etc., through the three 16-bit internal data buses IDBUS1 to IDBUS3. The 64-bit data bus SDBUS transfers data of four 16-bit registers (16 bits x 4 = 64 bits) of the general purpose register or PC or PSW at a time, and is exclusively used for transferring data between the RF/PC/PSW and the RAM 3 at high speed. The bank pointer BP is an 8-bit register, which can designed up to 256 banks, for holding a value that determines the start address of a mapping region in the on-chip RAM 3. According to the embodiment, the value held by the bank pointer BP is multiplied by 8 (adding "000" to the lower side of the bank pointer BP) to provide the byte address of a start point of a mapping region in the RAM 3. Namely, the start addresses of mapping regions in the RAM 3 are set at 8-bit intervals. The bank address control circuit produces an address which is used when the CPU transfers data to and from the RAM 3. The bank address control circuit increments a value of the bank pointer, multiplies the value by 8 to provide an address, which is provided as a data transfer address to the bank address bus BABUS. Figure 5 shows the inside of the general purpose register set RF disposed in the CPU core 2. The register set RF comprises a memory cell block (64 bits x 4) 26; a read/write controller 27 for the block 26; a first address selector 28 for selecting an address XAD (3:2) of the register set RF from which data is read for an XBUS, or an address BNKAD (1:0) of the register set RF from which data is sent to the on-chip RAM 3, according to a signal BNKTX indicating that data is transferred to the RAM 3, and providing the selected address to the controller 27; a second address selector 29 for selecting the address BNKAD (1:0) to send data to the RAM 3, or an address ZAD (3:2) of the register set RF from which data is read for a ZBUS, according to the signal BNKTX for transferring data to the RAM 3, and providing the selected address to the controller 27; a third selector 30 for selecting a signal BNKWR indicating that data is written from the RAM 3 to the register set RF, or a signal ZWRITE indicating that data is written from the ZBUS to the register set RF, according to the signal BNKTX indicating that data is transferred to the RAM 3, and providing the selected address to the controller 27; and fourth and fifth selectors 32 and 34 for converting 64-bit data from the block 26 into 16-bit data according to addresses XAD (1:0) and YAD (1:0), and providing the converted data to the XBUS and YBUS, respectively. A 64-bit BNK-BUS is connected to the exclusive-use data bus (third bus) SDBUS, which transfers data at high speed when data is saved from or restored to the register set RF. The buses ZBUS, XBUS, and YBUS are connected to the buses IDBUS1, IDBUS2, and IDBUS3 of Fig. 4, respectively. The buses IDBUS1, IDBUS2, and IDBUS3 transfer data under a normal operating state other than saving and restoring data from and to the register set RF. The signals BNKAD(1:0), BNKWR, BNKTX are generated by the bank address control circuit, and the signals XAD(3:0), YAD(3:0), ZAD(3:0), and ZWRITE are generated by the controller in the CPU. Figure 6 shows the inside of the on-chip RAM 3. The RAM 3 comprises a memory cell array 31 and peripheral elements, which include an address decoder circuit 33 and a peripheral selection circuit 37. The RAM 3 also includes signal lines such as the system bus SYSBUS made of the 16-bit address bus ABUS and the 16-bit data bus DBUS, the 11-bit bank address bus BABUS, the 64-bit data bus SDBUS, and read/write control signal line directly connected to the CPU core 2. When the on-chip RAM 3 is normally used as a main memory, data in the memory is accessed in a unit of 16 bits at relatively low speed through the system bus SYSBUS according to bus access rules. When the CPU core 2 switches one register bank to another to save or restore data from or to the register set, data is transferred in a unit of 64 bits at high speed through the exclusive-use data bus SDBUS according to an address provided through the bank address bus. Data of 8 bytes (16 bits x 4) stored in the general purpose registers of the register set RF of the CPU core 2 or in the memory cell array 31 of the RAM 3 may be transferred at a time. Since the register set RF is made of 16 bits x 16 registers, all data in the register set RF can be completely transferred within four cycles. A process of switching one register bank to another when an interrupt occurs will be explained. (1-1) When the interrupt occurs to execute an interrupt processing program during the execution of a program, or when an urgent program is carried out under a multitask environment due to task switching, or when a main program calls a subroutine, the program presently being executed must be suspended to start the different program. In this case, data in the program counter PC (24 bits) and processor status word PSW (32 bits) are passed through the exclusive-use data bus SDBUS and written in the RAM 3 at an address obtained by multiplying a value in the bank pointer BP by 8. The bank address control circuit provides an instruction to read the program counter PC and processor status word PSW through the data bus SDBUS, and multiplies the bank pointer value by 8 to provide the address to the bank address bus. (1-2) The bank address control circuit adds +1 to the bank pointer value and multiplies the addition result by 8 ((BP+1) x 8) to provide an address to the bank address bus. The bank address control circuit then provides an instruction to read data of 64 bits out of the registers R0 through R3 of the general purpose register set, so that the data from the registers R0 through R3 are written in the RAM 3 at the address of (BP+1)x8. (1-3) The bank address control circuit provides an address of (BP+2)x8 to the bank address bus, so that data of 64 bits of the registers R4 through R7 are written in the RAM 3 through the data bus SDBUS. (1-4) The same process is carried out for an address of (BP+3)x8 with R8 through R11. (1-5) The same process is carried out for an address of (BP+4)x8 with R13 through R15. In this way, the data of the program counter PC, processor status word PSW, and general purpose register set (involving the registers R0 through R15) are saved in the RAM 3. Figure 10 shows a state of the RAM 3 after the completion of the saving process. (2) The controller 23 updates the bank pointer BP. (3) If required, data in a 40-byte memory region in the RAM 3 starting from an address indicated by the updated bank pointer BP, i.e., data necessary for the subroutine program, or for the interrupt processing program, or for the urgent program are transferred to the register set RF, program counter PC, and processor status word PSW of the CPU core 2 through the 64-bit data bus SDBUS. As will be explained later in detail, part of the data saved in the step (1) is again readable from the memory region of the RAM 3 in the step (3). For example, part of the data for the main routine program data related to the subroutine can be collectively read from the RAM 3. Namely, the same data are sharable by different register banks. This may improve data processing efficiency. (4) After the subroutine program, or the interrupt processing program, or the urgent program is completed, a restoration instruction is issued. The controller 23 changes the bank pointer BP to indicate a value corresponding to the start address of the region where the data have been saved in the step (1). According to the changed value of the bank pointer BP, the bank address control circuit generates a bank address, and sends it to the on-chip RAM 3 through the bank address bus BABUS. After that, the data saved in the step (1) are restored in the program counter PC, processor status word PSW, and general purpose register set RF of the CPU core 2 through the exclusive-use 64-bit data bus SDBUS. Thereafter, the suspended program is resumed. The data sharing will be explained in detail. Data can be shared by a plurality of register banks if mapping regions of the register banks in the on-chip RAM 3 overlap one upon another. This may be achieved by setting proper values in the bank pointer BP one after another. According to the embodiment, a value in the bank pointer BP is converted into a byte address that is a multiple of 8. The program counter PC (24 bits), processor status word PSW (32 bits), and general purpose register set RF involving 16 bits x 16 registers occupy a 40-byte region in the RAM 3. If the step (1) sets "n" in the bank pointer BP, a write start address in the RAM 3 will be 8n, so that the contents of the register set RF, program counter PC, and processor status word PSW will be written in the region starting from addresses 8n to 8n+39 in the RAM 3. The step (2) may set "m" in the bank pointer BP, and the step (3) reads data from the region having addresses 8m to 8m+39 in the RAM 3 and restores them in the RF, PC, and PSW. In this way, the values n and m to be set in the bank pointer may be properly selected so that data mapping regions for different register banks in the RAM 3 may partly overlap one upon another to enable data to be partly shared by the different register banks. According to the invention, if 8n<=8m<=8n+39 or 8m<=8n<=8m+39 , data can be shared by different register banks. Figure 7 shows overlapped mapping regions in the RAM 3 for storing data of different register banks with n=3 and m=6. Figure 8 shows overlapped mapping regions in the RAM 3 for storing data of different register banks with n=5 and m=3. In this way, the register bank arrangement according to the embodiment easily enables data to be shared by or passed over between different register banks before and after a register bank switching operation. This improves data processing efficiency. Figure 9 shows the inside of a CPU core 2 according to a second embodiment of the invention. In this embodiment, the CPU core 2 incorporates two general purpose register sets RF0 and RF1. Other arrangements of this embodiment are the same as those of the first embodiment. The CPU core 2 comprises the two register sets RF0 and RF1 each having sixteen 16-bit registers; an ALU 25; three 16-bit internal data buses IDBUS1 through IDBUS3; a bank pointer BP0 for indicating the register bank number of the register set RF0; a bank pointer BP1 for indicating the register bank number of the register set RF1; and a 1-bit bank specifying F/F 41 for specifying a valid one of the register sets RF0 and RF1. When the F/F 41 is "1," the register set RF1 is valid, and when it is "0," the register set RF0 is valid. The two register sets RF0 and RF1 are connected to the three 16-bit internal data buses IDBUS1 to IDBUS3, and selectively connected to the 64-bit exclusive-use data bus SDBUS through a multiplexer MUX1. Outputs of the two bank pointers BP0 and BP1 are selectively provided to a bank address control circuit. The bank address control circuit adds +1 to a value held in a bank address pointer and multiplies the addition result by 8 to provide an address. Also, the bank address control circuit controls to write and read data to and from the register sets, a program counter PC, and a processor status word PSW through the SDBUS. The multiplexers MUX1 and MUX2 carry out the selection according to the contents of the bank specifying F/F 41. When the CPU core 2 is normally executing a program, one general purpose register set RFi specified by the bank specifying F/F 41 is used, and data are processed between the register set RFi and the ALU 25 through the 16-bit internal data buses IDBUS1 to IDBUS3. When one register bank is switched to another, data in the register set RFi are saved and restored as follows: (1) When an interrupt occurs or an interrupt processing program is executed during the execution of a program, or when an urgent program is carried out under a multitask environment due to task switching, or when a main program calls a subroutine program, the program presently being executed must be suspended to start the different program. In this case, a controller 23 changes a value in the bank specifying F/F 41, to disable the register set RF0 which is presently used. (2) If required, data in the on-chip RAM 3 starting from an address indicated by the bank pointer BP1 updated, i.e., data necessary for the subroutine program, or for the interrupt processing program, or for the urgent program are transferred to the register set RF1 specified by the bank specifying F/F 41 through the 64-bit exclusive-use data bus SDBUS. (3) Data in the disabled register set RF0 are saved in a region of the RAM3 starting from an address specified by the corresponding bank pointer BP0, through the 64-bit data bus SDBUS. (4) After the subroutine program, or the interrupt processing program, or the urgent program is completed, a restoration instruction is issued. The controller 23 changes the bank pointer BPi to indicate a value corresponding to the start address of the region where the data have been saved in the step (3). The changed value in the bank pointer BPi is sent to the on-chip RAM 3 through the bank address bus BABUS, and the data saved in the step (3) are restored in the register set RFi of the CPU core 2 through the exclusive-use 64-bit data bus SDBUS. Thereafter, the suspended program is resumed. The step (3) is not necessarily carried out just after the register banks are switched from one to another. It may be carried out at proper timing after the different program is started and the banks are switched from one to another. This is because the contents of the disabled register set RF0 are held until the next register bank switching is carried out. Namely, a bank switching time will be a sum of processing time of the step (1) and that of the step (2).Compared with the first embodiment, the second embodiment is speedier because the saving of the register set RF0 in the step (3) is not included, in appearance, in the bank switching time. In summary, the invention realizes the register bank function in a single chip microcomputer by mapping data between a on-chip RAM and a data memory (register set) of the microcomputer. To physically transfer data for the mapping at high speed, the invention employs a wide bandwidth third bus (the exclusive-use data bus SDBUS) between the RAM and the data memory. As a result, a CPU core according to the invention may have at least one multiport data memory because simultaneous read and write operations don't occur. Namely, it is not necessary to implement a large-scale multiport memory for register banks. The invention thus realizes a compact single chip microcomputer which is easy to design and operates at high speed. Namely, data are written to and read from the on-chip RAM through the system buses (A(23:0), D(15:0)) and through the exclusive-use bank buses (SDBUS, BABUS). To prevent a simultaneous access of the on-chip RAM through the system buses and exclusive-use bank buses, memory cells of the on-chip RAM have a single port. Through the wide bandwidth third bus of the invention, the contents of the data memory are saved and restored at high speed when the register banks are switched from one to another. Due to the third bus, a system bus (first bus) of the microcomputer will be free during the switching, so that the first bus may be used for other purposes such as transferring instructions from a on-chip ROM to a central processing unit, or first and second bus rights may be given to another bus master in the system to let the bus master use the buses. As a result, the single chip microcomputer may form a high performance system. Namely, a conventional system bus is connected to various elements such as an on-chip ROM, a serial I/O, and controllers in a chip, so that it must bear large load capacity and wiring capacity. This is the reason why the conventional system bus has a slow data transmission speed to hinder a high-speed operation. To solve this problem, the present invention employs an exclusive-use bus extending between, for example, a CPU core and an on-chip RAM. Since the load capacity and wiring capacity of this exclusive-use bus are smaller than those of the conventional system bus, the exclusive-use bus is suitable for a high-speed operation. In designing a single chip microcomputer, particularly in laying out blocks of the single chip microcomputer, the CPU core and on-chip RAM may be arranged close to each other to minimize the length of the exclusive-use bus disposed between them, to thereby reduce the wiring capacity of the exclusive-use bus. The invention sets a proper value in a bank specifying register so that different register banks may be partly overlapped one upon another when they are mapped in the on-chip RAM. This enables the different register banks to partly share data, or data may be handed over from one register bank to another when the banks are switched from one to another. As a result, the single chip microcomputer according to the invention may easily transfer parameters, for example, from a main routine program to a subroutine program. Although the entities of data of the register banks are in the on-chip RAM, this RAM is usable as a standard main memory, so that the memory can be effectively used even when the register bank function is not needed. The invention is applicable for cell base LSIs of semi-custom LSIs. In this case, a CPU core having a bank address control circuit, a bank pointer, etc., is prepared as a cell and combined with a on-chip RAM cell having a required capacity. This technique simplifies LSI designing and reduces a development period and cost. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof as set out in the appended claims.

Claims: A single chip microcomputer (1) comprising: a system bus (SYSBUS); a random access memory (3) within said single chip and connected to said system bus (SYSBUS), a plurality of register banks being formed in said random access memory (3); an I/O device (13) within said single chip and connected to said system bus (SYSBUS); a CPU core (2) within said single chip and connected to said system bus (SYSBUS) for performing data processing in cooperation with said random access memory (3), said CPU core (2) including an interface controller (23) for controlling data exchange through said system bus (SYSBUS), a decoder and control circuit (21) for decoding instructions to generate control signals, an arithmetic logic unit (25) for executing instructions, at least one register set (RF), consisting of a plurality of general purpose registers (R0, R1, R2, .., R15) for providing temporary storage in connection with a current task, a bank pointer (BP) for indicating a location of one of said register banks in said random access memory (3), and internal data bus means (IDBUS1, IDBUS2, IDBUS3) through which data exchange is performed among said interface controller (23), said arithmetic logic unit (25) and said register set (RF); characterized by an exclusive-use data bus (SDBUS) connected between said register set (RF) and said random access memory (3) for data exchange therebetween and provided separately from said system bus (SYSBUS); and a bank address bus (BABUS) for indicating an address,connected between said random access memory (3) and said bank pointer (BP) and provided separately from said system bus (SYSBUS) for the purpose of accessing said random access memory (3) to perform data transfer between said register set (RF) and said random access memory (3) through said exclusive-use data bus (SDBUS). A single chip microcomputer according to claim 1, wherein said bank pointer (BP) secures mapping regions for a plurality of the register banks in said random access memory (3), and said bank pointer (BP) may receive different values one after another so that the mapping regions in said random access memory (3) may partly overlap one upon another. A single chip microcomputer according to claim 1, wherein said CPU core (2) has a register (PC) for holding control data relating to a currently executing program, said register (PC) being connected to said exclusive-use data bus (SDBUS), and the contents of said register (PC) being saved to and restored from said random access memory (3) through said exclusive-use data bus (SDBUS). A single chip microcomputer according to claim 1, wherein said CPU core (2) has a plurality of register sets (RF0, RF1); a first multiplexer (MUX1) for selecting one of said register sets (RF0, RF1) and providing an output of said selected register set to said exclusive-use data bus (SDBUS); a plurality of bank specifying registers (BP0, BP1) for holding positional data of mapping regions in said random access memory (3) where the contents of said register sets (RF0, RF1) are mapped; a second multiplexer (MUX2) for selecting one of said bank specifying registers (BP0, BP1) and providing an output of said selected bank specifying register to said bank address bus (BABUS); and a bank specifying flag (41) for indicating the presently used register set. A single chip microcomputer according to claim 1, wherein said random access memory (3) has a memory cell array (31) and an address selection circuit (37) connected to said system bus (SYSBUS) and said bank address bus (BABUS) to selectively provide an address to said memory cell array (31). A single chip microcomputer according to one of claims 1-5, wherein said system bus (SYSBUS) includes a first bus (DBUS) for transferring data and a second bus (ABUS) for transferring address data. A single chip microcomputer according to claim 6, wherein the number of bits of said exclusive-use data bus (SDBUS) is larger than that of said first bus (DBUS). A single chip microcomputer according to claim 7, wherein said first bus (DBUS) is a 16-bit bus, said second bus (ABUS) is a 16-bit bus, said exclusive-use data bus (SDBUS) is a 64-bit bus, and said bank address bus (BABUS) is an 8-bit bus.

Inventors: KANUMA AKIRA, NISHIMURA AKIRA, OGAWA SUNAO, YAMADA YASUO, KANUMA, AKIRA, NISHIMURA, AKIRA, OGAWA, SUNAO, YAMADA, YASUO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: G06F15
IPC codes: G06F9, G06F15