DATA STORE AND IMAGE PROCESSING SYSTEM COMPRISING SAID DATA STORE

Abstract: In bringing data lines of VRAMs (105 - 108) into agreement with data lines of CPU in an image processor of the invention, bus conversion circuits (101 - 104, 150) are provided between the CPU and the VRAMs (105 - 108) and between the VRAMs (105 - 108) and a display system in order to constitute two or more independent screens using two or more VRAMs (105 - 108). Their independence is maintained by the bus conversion circuits (101 - 104, 150) and by address control of VRAMs (105 - 108), such that access can be made to many bits simultaneously from a drawing device (100).

Description: FIELD OF TECHNOLOGY This invention relates to application of a construction system of an image control device for use in a computer, and particularly to a device applicable to a case where it is required for an image drawing portion (hereinafter referred to as "drawing portion") such as a central processing unit (CPU) or an exclusively-used image drawing processor, a DMA control device or the like to carry out an access operation at plural times when the number of input/output terminals of a dynamic RAM (D-RAM) used as an image storing element or a dual port video RAM (hereinafter referred to as "VRAM") is smaller than a data processing unit of the drawing portion. DESCRIPTION OF RELATED ART A bit map display having display resolution of 512 X 512 (which is an image display device having a one-bit storing element at each picture element and is called as a graphic display; hereinafter referred to as "image control device") is required to have image storing capacity of 256K-bits at minimum. When a general 256K-bit VRAM is used, information of one frame (hereinafter referred to as "plane") can be stored in one element of VRAM, and an image data can be output to an image display device or the like at high speed without modification by a built-in serial output terminal. The 256K-bit VRAM is equipped with a 4-bit input/output data terminal, and thus the drawing portion can simultaneously access four bits. Fig. 17 shows a general image control device which is constructed by a drawing portion having a 4-bit data bus and four 256-Kbit VRAMs. The 4-bit data bus which is connected to the drawing portion 500 is connected to VRAMs 501 to 504 each constituting a plane. Serial output signals 511 to 514 of the VRAMs are directly output to a display portion. When 8-bit data A0 to A7 are written in the head address of a plane "0" by the drawing portion 500, twice access operations in which the data A0 to A3 are first written in an address "0" of the plane "0" and then the data A4 to A7 are written in an address "1" at a next cycle in the same manner are required because the data processing unit of the drawing portion 500 is 4-bit. The data A0 to A7 in the VRAM are successively output from the output terminal 511 in synchronism with an frame control signal in order of A0, A1, A2 to A7 for a frame display. This operation is conducted on the VRAMs 502 to 504 of the other planes which are originally independently provided. Figs. 18 and 19 show conventional devices whose drawing portions have 8-bit data processing unit. In the conventional device as shown in Fig. 18, the capacity of one plane is set to 256K-bits like that of Fig. 17, and the processing unit of a drawing portion 600 is also set to 8-bit. However, since the drawing portion 600 has the 8-bit data processing unit, an auxiliary circuit 607 including a 4-bit latch circuit 605 and a selection circuit 606 is required between a 8-bit data bus 610 extending from the drawing portion 600 and a 4-bit data bus 611 which is connected to each of planes 601 to 604. High-order four bits of a 8-bit data which is output from the drawing portion 600 are temporally held in the latch circuit 605 while only the remaining low-order four bits are directly transmitted through the selection circuit 606 to the planes 601 to 604. Thereafter, the high-order four bits which have been held are transmitted. This indicates that the auxiliary circuit carries out the transmission operation twice while the drawing portion 600 carries out the transmission operation once, so that no improvement is performed for the access system to a plane. In addition, when the drawing portion has a 16-bit data bus width, the temporally-storing latch is used for 12 bits, so that the access number is increased to four. Fig. 19 shows a frequently-used conventional system in which the capacity of one plane is set to two times of an originally-required capacity. Each of planes 701 to 704 has two 256K-bit VRAMs to enable direct connection to the 8-bit data bus. In this case, there occurs no problem in the access number as described above, but an originally-unnecessary capacity must be provided, so that cost of the device is necessarily increased. In a case where the bit width of the drawing portion is set to 16 bits, if the same system is applied to this case, the total memory capacity is increased to four times, and further it is increased to eight times for 32-bit width. The CPU, serving as a central unit for the drawing portion though it is a compact image control device, has been improved in its performance by replacing 8-bit to 16-bit or 32 bit. Further, the 256K-bits VRAM has been also improved in its packaging density through replacement to a 1-Mbits VRAM (256K X 4 and 128K X 8 are mainly used). That is, it is no exaggeration to say that the bit width of the drawing portion tends to be enlarged and the data width of the VRAM constituting the storing portion tends to be reduced. Every time performance and packaging density are intended to be improved, inconsistent matters conflicting to the intention of improvement appear. JP-A-1111278 and Patent Abstracts of Japan, vol. 13, no. 351 (P-912), 07.08.89, Matsushita Electric Ind. Co., Ltd. describe an image memory in which n-bit pixel data are stored in n memory elements with each bit of a pixel being stored in a respective one of the memory elements. A CPU address and a display address, n address calculators and n selectors co-operate to access data bits from the n memory elements. The accessed data are then formed into 8-bit words which are output on to a display bus a word at a time. Fortunately, makers for supplying a VRAM have made an effort to achieve a multiple-bit performance when a next-generation VRAM is developed. Therefore, in order to supply an image control device having low price and high performance, there is a problem to supply an image control device capable of performing a high-speed access without changing the total capacity of the image memory even when the data bus width of the CPU is enlarged two times or four times. SUMMARY OF THE INVENTION The present invention aims to solve the above mentioned problem in known image control devices. According to the present invention in one of its aspects, there is provided a data store comprising: an input data bus for receiving a plurality of multiple-bit data words, one at a time, the input data bus comprising a plurality of input data lines and receiving each word as a plurality of groups of data bits which groups are input simultaneously on respective ones of the data lines; a plurality of storing units; a first data bus converting unit connecting the plural input data lines to the plural storing units, the first data bus converting unit being controllable to connect different ones of the plural storing units at different times to each of the plural input data lines and thereby to distribute the groups of data bits comprising a data word among the plural storing units; a plurality of output data lines; and a second data bus converting unit connecting the plural storing units to the plural output data lines, characterised in that the second data bus converting unit is controllable to connect different ones of the plural storing units at different times to the plural output data lines and thereby to cause a plurality of data words to be output simultaneously on respective ones of the plural output data lines. According to another aspect of the invention, there is provided an image processing system comprising: a data store as claimed in any preceding claim; and an image drawing portion connected to the input data bus of the data store for outputting thereto a plurality of multiple-bit data words, one at a time, as a plurality of groups of data bits which groups are output simultaneously on respective ones of the data lines of the input data bus. According to an embodiment of the invention, the number of groups of data bits in each data word is equal to the number of storing units. Advantageously, the storing units may be in the form of a random access memory (RAM) device, for example in an image RAM. Further, the first data bus converting unit may comprise a plurality of converting circuits, and the second data bus converting unit may comprise a plurality of selection circuits. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing the construction of a first bus converting circuit and peripheral circuits thereof; Fig. 2 shows memory charts of VRAMs; Fig. 3 is a schematic diagram showing the construction of a second bus converting circuit; Fig. 4 is a time chart for an operation of an embodiment of this invention; Fig. 5 is a block diagram of an example to which this embodiment is applied; Fig. 6 is a block diagram for an address control circuit; Fig. 7 is a diagram showing the relationship between each plane and each RAM; Fig. 8 is a schematic diagram showing an image data to be written in each RAM; Fig. 9 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 10 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 11 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 12 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 13 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 14 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 15 is a schematic diagram showing the construction of an image data to be written in each RAM; Fig. 16 is a schematic diagram showing the construction of an image data to be read out of each RAM; Fig. 17 is a block diagram for a conventional image control device; Fig. 18 is a block diagram for a conventional image control device; and Fig. 19 is a block diagram for a conventional image control device. PREFERRED EMBODIMENTS FOR THIS INVENTION Fig. 1 shows an embodiment of this invention, and the function of a device is expanded by replacing a conventional 4-bit drawing portion to a 16-bit drawing portion. The drawing portion 100 is operated with 16 bits, and has four 4-bit data buses 120 to 123. Each of planes 105 to 108 comprises a single 256K-bit VRAM, and the total memory capacity thereof is equal to the capacity required to obtain display resolution. A first data processing unit comprises an assembly of 16 bits which serves as a data processing unit of the drawing portion, and a second processing unit comprises an assembly of 4 bits whose number is equal to the number of data terminals. Therefore, the first processing unit is different from the second processing unit. The data buses 120 to 123 extending from the drawing portion 100 are connected to first data bus converting circuits 101 to 104, and data buses 125 to 128 extending from the data bus converting circuits 101 to 104 are connected to VRAMs 105 to 108 each serving as a plane, respectively. One-bit serial video data buses 140 to 143 output from the respective VRAMs are transmitted through the second data bus converting circuit 150 (as shown in detail in Fig. 3) to the display portion. The data buses 120 to 123 are constructed by four buses each having four bits as an unit. An image data of 16 bits which serves as a data processing unit of the drawing portion 100 is divided into 4-bit units, and the 4-bit units thus divided are provided with data buses 120, 121, 122 and 123 in order from the highest order. The data bus converting circuits 101 to 104 are connected to common-control lines 129 and 130. As shown, both of selection signals to be supplied to the control lines 129 and 130 are set to "0". The data bus 125 is connected to the highest-order data bus 120, and the subsequent data buses 126, 127 and 128 are connected to the data bus 121, the data bus 122 and the data bus 123, respectively. The control lines 129 and 130 are used as the low-order two bits for an address line of each of the VRAMs 105 to 108. However, each lowest-order address of the VRAMs 105 and 108 is connected to a control line 131 which is connected through an inversion element 110 to the control line 129, and a next lowest-order address of each of the VRAMs 107 and 108 is connected to a control line 132 which is connected through an inversion element 109 to the control line 130. Therefore, in this embodiment, the lowest-order two bits of the addresses of the VRAMs 105, 106, 107 and 108 are specified to be in "00", "01", "10" and "11" states, respectively. Fig. 2 shows a memory content of each VRAM. When "0" and "0" are first specified to signals 129 and 130 respectively and then 16-bit data "A0 to AF" is simultaneously written in the head of each VRAM, 4-bit data "A0 to A3" is written in the address "00" of the VRAM 105, 4-bit data "A4 to A7" is written in the address "01" of the VRAM 106, 4-bit data "A8 to AB" is written in the address "10" of the VRAM 107, and 4-bit data "AC to AF" is written in the address "11" of the VRAM 108. Next, when "1" and "0" are specified to the signals 129 and 130 respectively and 16-bit data "b0 to bF" is written in, 4-bit data "b4 to b7" is written in the address "01" of the VRAM 105, 4-bit data "b0 to b3" is written in the address "00" of the VRAM 106, 4-bit data "bC to bF" is written in the address "11" of the VRAM 107 and 4-bit data "b8 to bB" is written in the address "10" of the VRAM 108. Further, when "0" and "1" are specified to the signals 129 and 130 respectively and 16-bit data "c0 to cF" are written in, 4-bit data "c8 to cB" is written in the address "10" of the VRAM 105, 4-bit data "cC to cF" is written in the address "11" of the VRAM 106, 4-bit data "c0 to c3" is written in the address "00" of the VRAM 107 and 4-bit data "c4 to c7" is written in the address "01" of the VRAM 108. Still further, when "1" and "1" are specified to the signals 129 and 130 respectively and 16-bit data "d0 to dF" are written in, 4-bit data "dC to dF" is written in the address "11" of the VRAM 105, 4-bit data "d8 to dB" is written in the address "10" of the VRAM 106, 4-bit data "d4 to d7" is written in the address "01" of the VRAM 107 and 4-bit data "d0 to d3" is written in the address "00" of the VRAM 108. It is clearly found out from this operation that at least 16 bits can be simultaneously written in or read out by one access operation to the drawing portion. Fig. 2 means a pattern in which the contents of the VRAMs 105 to 108 are sequentially output to the serial video data buses 140 to 143. Fig. 3 is a detailed diagram of the second bus converting circuit 150 as shown in Fig. 1. Data buses 311 to 314 serving as four inputs of the second bus converting circuit 150 are connected to selection circuits 301 to 304 to select any one of the data buses 311 to 314, and an output signal thereof is supplied to data buses 315 to 318. In addition, control lines 320 and 321 are commonly input to the selection circuits 301 to 304 so that a point of each circuit is selected. As shown, both signals are set to "0". Figs. 4(a) to 4(j) show time charts at the output side of this embodiment. Figs. 4(a) to 4(d) are signal diagrams for a serial video data output in accordance with a memory map as shown in Fig. 2, and show waveforms of input signals supplied to the data buses 311 to 314. Further, Figs. 4(e) and (f) show waveforms of selection signals supplied to the control lines 320 and 321, and Figs. 4(g) to 4(j) show waveforms of output signals to be supplied to the terminals 315 to 318. Since both of the selection signals supplied to the control lines 320 and 321 are kept to "0" during a period from T0 to T3 (Figs. 4(e), (f)), the data bus 315 is connected to the data bus 311, the data bus 316 is connected to the data bus 312, the data bus 317 is connected to the data bus 313, and the data bus 318 is connected to the data bus 314. During a period from T4 to T7, the selection signal supplied to the control line 320 is kept to "1", and the selection circuits 301 to 304 are switched so that all of them select "1". Therefore, the data bus 315 is connected to the data bus 312, the data bus 316 is connected to the data bus 311, the data bus 317 is connected to the data bus 314, and the data bus 318 is connected to the data bus 313. Subsequently, the selection circuits are successively switched between a period from T8 to T11 and a period from T12 to T15 to finally obtain A0 to AF, b0 to bF, c0 to cF and d0 to dF which are simultaneously written in by the drawing portion. The above embodiment is described particularly in a case where the drawing portion is constructed with 16 bits and the plane is constructed with 4 bits. The capacity of the VRAM is set to the minimally required capacity, and in addition the drawing portion can access 16-bit data at one normal cycle, so that the access operation at plural times as described in the conventional device is not required. When the drawing portion is constructed with 8 bits, it can be constructed with simple construction using the bus converting circuits provided at the front and rear stages. When the drawing portion is constructed with 32 bits, the conventional system is partly used in combination. However, the display device of this class is improved in its multiple-plane performance and high-resolution, so that the number of the used VRAMs is increased to some extent. Therefore, the data line number which can be simultaneously accessed is also increased, and thus there are many cases where only this embodiment is sufficient. Next, a modification of the above embodiment in which the drawing portion is constructed with eight 32-bit RAMs each having 4-bit data terminal number will be described with reference to Figs. 5 to 16. Fig. 5 is a block diagram showing the construction of this modified embodiment. In Fig. 5, the image control device comprises an address control circuit 400, a first rearrangement circuit 430, RAMs 450 to 457 each constituting a plane, a second rearrangement circuit 460 and a parallel/serial converter 470. A 32-bit image data transmitted from the CPU data bus is divided into 4-bit units, and then input to the first rearrangement circuit 430. The first rearrangement circuit 430 has an arrangement structure as shown in the figure, and is supplied with a plane signal from a signal line 421 of the control circuit 400 to rearrange the image data. The arrangement structure of the first rearrangement circuit 430 visually represents a connection state between 4-bit input data buses 431 to 438 and 4-bit output data buses 441 to 448, and actually it is constructed by plural logical circuits. Here, the input data buses 431 to 438 and the output data buses 441 to 448 are designed so as to be connected to one another at positions (oblique portions) "3" of the first rearrangement circuit 430 when the plane signal from the signal line 421 is a plane 3. That is, the input data bus 431 is connected to the output data bus 444, the input data bus 432 is connected to the output data bus 443, the input data bus 433 is connected to the output data bus 442, and the input data bus 434 is connected to the output data bus 441. Also, the input data bus 435 is connected to the output data bus 448, the input data bus 436 is connected to the output data bus 447, the input data bus 437 is connected to the output data bus 446, and the input data bus 438 is connected to the output data bus 445. The image data of the 4-bit units are rearranged so as to be connected as described above, and these are simultaneously written in addresses indicated by the address control circuit, into RAM 450-457. Thereafter, the image data stored in each of the RAMs 450 to 457 is read out and transmitted through the second rearrangement circuit 460 and the parallel/serial circuit 470 to a color table of a display portion. The second rearrangement circuit 460 switches the connection between the output data buses 441 to 448 and the data buses 461 to 468 in accordance with times (T0 to T7) which are defined by a timing signal. That is, when the timing signal is set at the time T0, these buses are connected to one another so as to be intersected to one another at the positions "0" of the second rearrangement circuit 460. Likewise, every time the timing signal is switched at any one of the times T1 to T7, the connection between the output data buses 441 to 448 and the data buses 461 to 468 is successively switched. Through this rearrangement operation, the image data of the plane 3 which are dispersively stored in the RAMs 450 to 457 are output from the data bus 464. This is because the connection between the data bus 464 and the output data buses 441 to 448 is varied with time in order of the numbers of the oblique portions of the second rearrangement circuit 460. Concretely, the output data bus 444 is connected at the time T0, the output data bus 443 is connected at the time T1, and the similar connecting operation is carried out for the other output data buses at the time T3 and the subsequent times. Through this operation, the image data of the plane 0 and the image data of the plane 2 are output from the data bus 461 and the data bus 462, respectively. Likewise, the image data of the planes 3 to 8 are output from the data buses 463 to 468, respectively. The image data of the respective planes are output in parallel, so that all data are supplied to the color table during a period from the time T0 to the time T7. In this embodiment the image data from the 32-bit CPU data bus is divided into 4-bit units, and the divided 4-bit units are parallel written in or read out of the RAMs 450 to 457 each having 4-bit access unit. In such a processing, it is possible that the write-in or read-out operation to a 32-bit plane is apparently carried out with an access unit by cooperating the address control circuit 400, the first rearrangement circuit 430 and the second rearrangement circuit 460. In this modified embodiment, the circuit may be constructed by four RAMs each having 8-bit access unit. Next, the address control circuit 400 for controlling the addresses of the RAMs 450 to 457 will be described with reference to Fig. 6. In Fig. 6, the address control circuit 400 includes a register 401 for storing plane numbers to be accessed, and switches 402 to 409 for switching write-in addresses and read-out addresses to the RAMs 450 to 457. The register 401 is equipped with signal lines 411 to 413 to which signals representing plane numbers from the CPU are supplied on bit-basis, a signal line 414 to which a register set signal from the CPU is supplied, signal lines 481, 483 and 485 which output signals representing plane numbers on bit-basis, and signal lines 482, 484 and 486 which output inversion signals of the signals of the signal lines 481, 483 and 485. Desired three signal lines of these signal lines 481 to 486 and the high-order bit of the address bus 415 are synthesized and then supplied to each of the switches 402 to 409 as a write-in address to the RAM. In addition, the switches 402 to 409 are supplied with a read-out address from the address bus 416 of a display system. The switching operation of these switches 402 to 409 is carried out in accordance with the instruction of the CPU, and any one of the write-in or read-out addresses is supplied through the address buses 422 to 429 to the RAMs 450 to 457. The relationship between the plane number stored in the register 401 and the write-in addresses supplied to the RAMs 450 to 457 is shown in Fig. 7. The addresses as shown in Fig. 7 are supplied to the respective RAMs 450 to 457 for the write-in operation to the plane, and the image data is rearranged in the first rearrangement circuit 430, so that the image data written in the RAMs 450 to 457 every plane is constructed as shown in Figs. 8 to 15. In the read-out operation from the plane, the read-out address from the address bus 416 is supplied to each of the RAMs 450 to 457, and the image data is rearranged in the second rearrangement circuit 460, so that the image data supplied to the color table is constructed as shown in Fig. 16. The same element may be used for the first and second rearrangement circuits. Further, the second rearrangement circuit 460 may be provided between the parallel/serial converter 470 and the color table. Still further, a DRAM or VRAM may be used for the RAMs 450 to 457, and other memory elements may be also used. UTILITY OF INDUSTRIAL FIELD As described above, according to the image control device of this invention, the drawing portion can reduce the number of access operations of a memory exclusively used for video which require relatively more time than a main memory, etc., and thus a reduced time can be provided to a data processing time which must be originally carried out by the drawing portion, or another input/output device. Therefore, not only high-speed image drawing can be performed, but also performance of the whole device can be improved. In addition, even when this invention is used in combination with the solving means of the prior art, the total memory capacity and the access speed of the drawing portion are clearly superior over those of a device to which this invention is not applied.

Claims: A data store comprising: an input data bus for receiving a plurality of multiple-bit data words, one at a time, the input data bus comprising a plurality of input data lines (120 to 123, 431 to 437) and receiving each word as a plurality of groups of data bits which groups are input simultaneously on respective ones of the data lines; a plurality of storing units (105 to 108, 450 to 457); a first data bus converting unit (101 to 104, 430) connecting the plural input data lines to the plural storing units, the first data bus converting unit being controllable to connect different ones of the plural storing units at different times to each of the plural input data lines and thereby to distribute the groups of data bits comprising a data word among the plural storing units; a plurality of output data lines (315 to 318, 461 to 468); and a second data bus converting unit (301 to 304, 460) connecting the plural storing units to the plural output data lines, characterised in that the second data bus converting unit is controllable to connect different ones of the plural storing units at different times to the plural output data lines and thereby to cause a plurality of data words to be output simultaneously on respective ones of the plural output data lines. A data store as claimed in claim 1, wherein the number of groups of data bits in each word is equal to the number of storing units. A data store as claimed in claim 1 or 2, wherein each of the storing units is a random access memory (RAM) device. A data store as claimed in claim 3, wherein each of the storing units is an image RAM. A data store as claimed in any preceding claim, wherein the first data bus converting unit comprises a plurality of converting circuits (101 to 104). A data store as claimed in any of claims 1 to 4, wherein the first data bus converting unit comprises a first rearrangement circuit (430). A data store as claimed in any of claims 1 to 5, wherein the second data bus converting unit comprises a plurality of selection circuits (301 to 304). A data store as claimed in any of claims 1 to 4 or 6, wherein the second data bus converting unit comprises a second rearrangement circuit (460). A data store as claimed in claim 8, further comprising a parallel serial converter (470) between the second rearrangement circuit and the plural output data lines. An image processing system comprising: a data store as claimed in any preceding claim; and an image drawing portion (100) connected to the input data bus of the data store for outputting thereto a plurality of multiple-bit data words, one at a time, as a plurality of groups of data bits which groups are output simultaneously on respective ones of the data lines of the input data bus. An image processing system as claimed in claim 10, wherein the image drawing portion (100) is connected to output control signals to control the first data bus converting unit. An image processing system as claimed in claim 10 or 11, further comprising an image display portion connected to the plural output data lines.

Inventors: NAKAMURA KATSUTOSHI, NAKAMURA, KATSUTOSHI, NAKAMURA, KATSUTOSHI SEIKO EPSON CORP.
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1992
Main classification: G06T1
IPC codes: G06T1, G09G5