Delay correcting system in a multi-channel PCM switching system

Abstract: A delay-in-frames correction system in a switch unit in a PCM transmission line is used in the data communication field. It comprises a channel data storage unit (7,8) for temporarily storing data corresponding to each channel on the output side or the input side of the switch (6) in each direction in the PCM transmission line, and a data delay control unit (9) for delaying data among the data corresponding to channels and stored in the channel data storage unit (7,8), the data corresponding to a plurality of channels, being outputted in order in the same frame, and being delayed by the number of frames indicated by the most delayed data corresponding to channels, and for outputting frame correction instruction information for outputting a data string in the same frame.

Description: Background of the Invention The present invention relates to data communication, specifically to a delay-in-frames correcting system in a PCM transmission line for correcting delays of data in frames at a switch unit in the PCM transmission line. The system configuration shown in Figure 1 is used in transmitting data between a subscriber terminal and another subscriber terminal in wide-band data transmission using, for example, 64Kbps x N (N equals 1 - 30 channels) in a PCM transmission line (2.048MHz in Europe, and 1.544MHz in the U.S. and Japan). In Figure 1, subscriber terminals A and B are connected to a PCM transmission line terminal unit which is also called "Digital Terminal" (DT) 1 through a PCM transmission line L. 2 is a digital terminal common (hereinafter abbreviated as DTC). A delay-in-frames arises at a switch unit 3 having a configuration T-S-T, for example. The above described switch unit 3 comprises a multiplexer (MPX) 4 for multiplexing a transmission signal, a primary time switch TSW1, a space switch SSW, a secondary time switch TSW2, and a demultiplexer (DMPX) 5. The primary time switch TSW1 and the secondary time switch TSW2 comprise memories MEM1 and MEM2 individually. The above described PCM transmission line L is set to 2.048MHz in Europe and 1.544MHz in the U.S. and Japan, carrying 64Kbps data per channel (ch). This enables the data transmission of 64Kbps x 30 channels at maximum in Europe and 64Kbps x 24 channels at maximum in the U.S. and Japan. For example, in transmitting video signals each carrying 384Kbps data, a signal is transmitted through 6 channels (64Kbps x 6 = 384Kbps). Figure 2A shows the data configuration of 128 channels on the output side of the DTC 2 shown in Figure 1, that is, the input side of the switch unit 3. In the configuration, control channels TS 0 - TS 3 control the PCM transmission line terminal unit 1; TS 4 - TS 63 and TS 68 - TS 127 are voice channels; and TS 64 - TS 67 are call control channels. That is, the data comprises 120 voice channels and 8 control channels. Eight units of the above described data form one block, and are multiplexed by the multiplexer 4 to finally form 1024 channels shown in Figure 2B. Then, they are switched through the primary time switch TSW1, the space switch SSW, and the secondary time switch TSW2, demultiplexed by the DMPX 5, and transmitted to the subscriber B through the DTC 2 and the DT 1. The path of this signal is shown in Figure 1 as a bold line. The method of transmitting data from a terminal to the input side of the primary time switch in the switch unit 3 is described below in detail. A line is connected to each of the digital terminals 1 shown in Figure 1, and the digital terminal common 2 multiplexes/demultiplexes the data applied from a plurality of lines. In Europe, 1 line equals 30 channels, and 4 lines are connected to the digital terminal commons 2. In the U.S., 1 line equals 24 channels, and 5 lines are connected to the DTCs 2. The DTCs 2 are operated as an interface between the digital terminals 1 and the switch unit 3. They multiplex/demultiplex data for the voice channels, transmit an operation mode of the DT1 through the control channel, and notify the switch unit 3 of the alarm state of the PCM transmission line L. Each memory in the primary time switch TSW1 and the secondary time switch TSW2 has the capacity of 1028 channels and receives data consisting of 128 channels from each of the DTCs 2. Therefore, the MPX 4 and the DMPX 5 shown in Figure 1 multiplex/demultiplex signals for eight DTCs 2. In the flow of a signal described above, data may delay in frames at the switch unit 3. Assume that, for example, information comprising three data A, B, and C are applied to the switch unit 3. When the information is switched and outputted, the data in channel C can delay and enter the frame next to its own frame. The delay may be caused by an erroneous allocation of the memory MEM1 in the primary time switch SW1 or the memory MEM2 in the secondary time switch SW2. Thus, information comprising three data pieces A, B, and C often becomes meaningless if they suffer delays in their frames during the switching operation. Figure 3 shows how the delays-in-frames take place. In Figure 3, α 1 indicates the state of each signal on the input side of the primary time switch TSW1; α 2 indicates the state of each signal between the primary time switch TSW1 and the secondary time switch TSW2; and α 3 indicates the state of each signal on the output side of the secondary time switch TSW2, wherein frames are named frame N, frame N+1, frame N+2, ..., each comprising 1024 channels from channel 0 to channel 1023. In Figure 3, data A in channel 0 in the state α 1 , for example, delay a little in phase and enter the second channel in the stated α 2 . Then, they enter the 514th channel in the state α 3 . However, they are still in frame N, the same frame as that in which the data were inputted. In the meantime, data B in the second channel in the state α 1 enters frame N+1 in the state α 3 , and data C in the 510th channel in the state α 1 enters frame N+2 in the state α 3 . Thus, they delay and enter the frames different from those where they were in when inputted. As described above, data can be detected in the different frames on their input and output sides of the switch unit 3. In Figure 3, the output frame of the secondary time switch TSW2 leads by 513 time slots because the upstream data and downstream data are allocated separately in the switch unit. Figure 4 shows the difference in the allocation. Assuming that, in Figure 4, the transmission line from terminal A to terminal B is an upstream line and that from terminal B to terminal A is a downstream line, a channel allocated the stated α 2 in the upstream path is allocated α 2 +512 in the downstream path. Therefore, the output side of the upstream path leads by 513 time slots. When data are transmitted in the PCM transmission line through the wide-band of 64Kbps x Nch (N equals 30 channels in Europe, and 24 channels in the U.S. and Japan), video data are transmitted through 64Kbps x 6 channels, wherein the data in 1 - 6 channels must be transmitted at the same timing. Therefore, as described above, a delay of data in frames caused in the switch unit 3 must be corrected appropriately. To correct the delays, the prior art technology controls such that the necessary number of channels are retained in order and a significant data string is outputted in the same frame without data delays in frames under software control. However, in this method, channels cannot be allocated such that they are retained in order with a significant data string outputted in the same frame without delay when a number or calls are required, thereby causing a problem of an unpractically high call loss rate. A "call loss rate" means a rate of calls which cannot be connected to a receiving side due to the congestion at a switch unit, etc., that is, a rate of channel allocations which fails in retaining the order of data. The following documents disclose some possibilities for retaining the order of data. FR-A-2 634 083 relates to a terminal of a telecommunication network wherein plural independent channels are connected. For increasing its performance a receiver unit and a buffer are provided for each of sending/receiving channels 1 to n, and as for the control of a delay, the order of receiving the receiver frames is controlled. EP-A-0 229 365 relates to a method and an apparatus for establishing a wideband communication facility through a communications network having narrow bandwidth channels. For ensuring that all data received in one time frame from a given facility segment is assembled only into the same time frame for transmission on an outgoing facility segment buffer, memories are provided in the initial and final stages of a space-time switching network. Data to be output in a same frame are output as a same frame, but its delay is a fixed value. A double buffer method is used for assuring the data sequence. SECOND IEE NATIONAL CONFERENCE ON COMMUNICATIONS, 2 April 1989, YORK UK, pages 321 - 326 XP130153, MADDERN "Analysis of multi-slot connections" relates to terminals for supporting multi-slot services, wherein single buffered and double buffered time switching stages are compared. There exists a possibility for controlling the delay by storing the data for a certain period. EP-A-0 057 758 relates to a switching system for PCM telecommunication using a multiplexing device. For solving the problem of undesired delays time slots provided in the last coupling stage will send out a part of information in delayed frames. The delaying time is determined in accordance with the difference between the frame period and the sum of possible maximum propagation delays. GB-A-2 000 418 relates to a method for bit-switching word synchronized data. For avoiding the problem of the delay of bits a delay equalizer is provided for delaying bits for a predetermined period of time. Further, according to this document the method is also applicable to switches with PCM multiplexers. FR-A-2 301 136 relates to a system for correctly assigning time intervals between data wherein data are buffered for a certain time and transmitted after a transmission line has been found. Summary of the Invention Starting from the disclosure of EP-A-0 229 365, it is the object of the present invention to realize a delay-in-frames correcting system in the PCM transmission line wherein the control of a delay of data for maintaining the order of data in a frame is improved. This object is solved by a system according to claim 1. The dependent claims show advantageous further developments of the system according to claim 1. Especially, the data delay control means of the delay-in-frames correcting system according to claim 1 controls the delay of data corresponding to the number of frames indicated by the most delayed data and outputs frame correction instruction information for outputting a data string in the same frame. Thus, the delay controlled according to the system of the present invention is not a fixed value but can vary with the most delayed data. A feature of the present invention resides in a delay-in-frames correcting system operated in a switch unit in a PCM transmission line in which each piece of data corresponding to each channel is transmitted in a frame comprising a plurality of time slots corresponding to a plurality of channels, the system comprising channel data storage means for temporarily storing data corresponding to each channel on the output side or the input side of the switch unit in each direction of the transmission line, and data delay control means for delaying data among the data corresponding to channels and stored in the channel data storage means, the data corresponding to a plurality of channels, being outputted in order in the same frame, and being delayed by the number of frames indicated by the most delayed data corresponding to channels, and for outputting frame correction instruction information for outputting a data string in the same frame. Brief Description of the Drawings One of skill in the art can easily understand additional features and objects of this invention from the description of the preferred embodiments and some of the attached drawings. In the drawings: Figure 1 is a block diagram showing the configuration of the PCM transmission system; Figure 2 shows the configuration of the data inputted to the switch unit; Figure 3 shows the positions of data and the delays in frames; Figure 4 is a block diagram for explaining the allocation of time slots in the switch unit; Figure 5 is a block diagram for explaining the principle of the present invention; Figure 6 shows determinative conditions on delays of data in frames; Figure 7 is a block diagram for explaining the outline of the data delay correcting system of the present invention; Figure 8 is a block diagram indicating the configuration of the embodiment of the digital terminal common (DTC); Figure 9 shows the data inputted from the switch unit to the DTC and clock used in the embodiment; Figure 10 shows the storage state in the memory and the relationship between the input and the output of the memory; Figure 11 shows an example of writing information to each bit from control channels; Figure 12 shows the frame correction instruction information for each channel of input data; Figure 13 is a flowchart for explaining the arithmetic operation performed by the CPR to calculate the data delay in frames; Figure 14 is a block diagram for explaining the operation of the counter shown in Figure 8; Figure 15 is a block diagram showing the detailed configuration of the digital terminal common (DTC); Figure 16 is a time chart explaining the operation of each unit shown in Figure 15; and Figure 17 shows an example of the relationship between the frame correction instruction information shown in Figure 15 and the read address in the data from the memory. Description of the Preferred Embodiment Figure 5 is a block diagram for explaining the principle of the present invention, and shows the method of correcting at a switch unit the delays of data allocated to channels in the PCM transmission line for transmitting data in each frame comprising a plurality of channels. In Figure 5, channel data storage units 7 and 8 temporarily store data allocated to each channel. Both channel data storage units 7 and 8 are provided on the output side of the switch unit 6 in Figure 5 but can also be located on the input side. A data delay control unit 9 retains the order of data allocated to each channel and stored in the channel data storage units 7 and 8, and outputs a data string, which is allocated to a plurality of channels and should be outputted in the same frame, exactly in the same frame after delaying them around the point of the most delayed data in a plurality of channels. The delay-in-frames between the data inputted to the switch unit 6 and the data outputted therefrom is explained below. The delay-in-frames is caused by the delay between the input side of the primary time switch and the output side of the secondary time switch in the switch unit 3 shown in Figure 1. Whether or not the data inputted to the primary time switch are outputted, on the output side of the secondary time switch, in the frame in which they are inputted depends on the relationship among the signal states α 1 on the input side of the primary time switch described by referring to Figure 3, the signal state α 2 between the primary time switch and the secondary time switch, and the signal state α 3 on the output side of the secondary time switch. Figure 6 shows the condition for determining the delay-in-frames. It shows the condition for determining whether a piece of data in frame N are outputted in frame N, in frame N+1 after delaying by one frame, in frame N+2 after delaying by two frames, or in frame N+3 after delaying by three frames. In Figure 6, if the relationship among the data states α 1 , α 2 , and α 3 is represented as: α 1 ≦ α 2 < 510 channels and α 2 + 513 channels ≦ α 3 , the data are inputted in frame N and outputted in frame N, that is, they do not delay to a different frame. If α 1 ≦ α 2 < 510 channels and α 2 + 513 channels > α 3 , the data are inputted in frame N and outputted in frame N+1, that is, they are delayed in phase by one frame. In the principle configuration shown in Figure 5, data inputted to the switch 6 through the PCM transmission line can be outputted in a different frame due to a delay caused in the switch 6. For example, data A, B, C in three channels are assumed to be inputted in the switch unit 6, and only data C among them are delayed by one frame on the output side of the switch 6. In this case, when data A, B, and C are allocated to corresponding channels, the delay of data can be preliminarily calculated by software as explained above by referring to Figures 3 and 6. For example, if data C delay by one frame when data A, B, and C are inputted to the switch unit 6 shown in Figure 5 through the PCM transmission line terminal unit 1 shown in Figure 1, switched in the switch unit 6, and outputted therefrom, then the data delay control unit 9 receives from the software the correction value to the delay and controls the output of the data temporarily stored in the channel data storage unit 7. In this case, as data C is delayed by one frame, data A and B are controlled to be delayed by the same number of frames. Thus, when data are allocated to corresponding channels, the anticipated delay-in-frames is calculated by the software based on the allocated channels of data, the calculation results are stored in the channel data storage unit, and the delay-in-frames at the switching of data is corrected according to the correction value provided by the software. That is, if the most delayed data are C, which indicates the largest delay value among data A, B, and C in three channels, other data A and B are also delayed corresponding to the delay value of data C in order to output data A and B in the same frame for data C. Thus, data A, B, and C are corrected to be retained in order and can be significant as one data string, thereby reducing a call loss rate. Figure 7 is a view for explaining the outline of the delay-in-frames correcting method of the present invention. In Figure 7, 10a and 10b are digital terminals (DT); 11a and 11b are digital terminal common (DTC); 12 is a switch unit having the T-S-T configuration; 13a and 13b are memories corresponding to the channel data storage units 7 and 8; and 14 is a call processor (CPR) containing a data control unit 15 for controlling a read of data, etc. from memories 13a and 13b. In Figure 7, memories 13a and 13b are provided in the DTCs 11a and 11b respectively on the output side of the switch unit 12. They can also be provided on the input side of the switch unit 12. In Figure 7, the data control unit 15 stores a software program for calculating the delay of data in frames. When switching control determines for data the channel allocation states α 1 , α 2 , and α 3 as described in Figure 6, the delay-in-frames is calculated on the condition shown in Figure 6, and the CPR 14 controls the allocation of the path in the switch unit and the correction of the delay in frames. Figure 8 shows the configuration of an embodiment of the digital terminal common (DTC) of the present invention. In Figure 8, 21 is a serial/parallel converting circuit (hereinafter referred to as an S/P converting circuit); 22 is a counter; 23 is a control (CNTL) data dropper; 24 is a read address control (CNTL); 25 is a memory; 26 is a first selector; 27 is a second selector; and 28 is a parallel/serial converting circuit (hereinafter referred to as a P/S converting circuit). Figure 8 shows only the units directly associated with the present invention. The data applied here have the configuration shown in Figure 9. The data are outputted by the switch unit 12 shown in Figure 7, and are configured in the 16-multiframe format. Each format comprises channels TS0 - TS127, a total of 128 channels, and each channel comprises B1 - B8, a total of 8 bits. Figure 9B shows a clock CK; and Figure 9C is a signal FCK indicating the leading bit of the multiframe, and outputting "1" at frame=0, TS=0, and B=1. In this format, one frame consists of 128 time slots, and the frame is outputted from the DMPX 5 and inputted to the DTC 2, for example, as shown in Figure 1. As described above, the DMPX 5 demultiplexes the 1024 time slot data in the format (shown in Figure 2) in the switch into eight lines, that is, into eight DTCs. The cycle of one frame in a switch is the same as that in a DTC. The above described S/P converting circuit 21 performs a 8-bit parallel conversion on the data (Figure 9A) in synchronism with the clock (Figure 9B). The signals thus obtained are sequentially written at the address 000, 001, 002, ... in the memory 25 starting with TS0 in frame 0 according to a write address signal (WA signal) from the counter 22. The writing operation is repeated up to TS127 in frame 15. The software issues a frame correction instruction to each piece of written data. In Figure 10A, for example, the frame correction instruction is "0" for the data in TS4 of frame 0 at address 004, and "1" for the data in TS5 of frame 0 at address 005. Thus, if the frame correction instruction indicates "0", the output from a memory (read output), compared with the input to a memory (write input), is outputted in the frame where it was inputted as indicated in Figures 10B and 10C, while it is outputted in the frame following the one where it was inputted if the frame correction instruction indicates "1". In Figures 10A and 10B, "frame" is abbreviated to "F". For example, frame 0, frame 1, ... are represented as F0, F1, ... For detailed explanation about Figure 10, the horizontal direction in Figures 10B and 10C indicates a time axis. In Figure 10B, data are written in a memory sequentially at input addresses. In Figure 10C indicating memory output addresses, the data in TS5 having a correction instruction are buffered for the time for one frame and then outputted. A frame correction instruction is issued through the control channels TS0 - TS3 in the data configuration shown in Figure 9A. In the DTC unit, the TS number designation information for designating the TS number whose frame must be corrected, a flag indicating whether or not the data is valid, and the frame correction instruction information for indicating how far the data must be moved are written to the control channel. The DTC unit receives all the above described information from the switch unit. Figure 11 is an example of setting for two control channels in frames 0 - 15 the above described flag, designating a TS number, and allocating the above described flag. In designating a TS number, seven bits are used to designate 128 TSs. Four bits of D 0 , D 1 , D 2 , and D 3 indicate frame correction instruction and written by the software as a predetermined frame correction data. For example, if D 0 - D 3 indicate 0000, the data in the channels require no frame correction. That is, frame F n is used as frame F n as is. If D 0 - D 3 indicate 0001, the data in the channels must be moved by one frame from frame F n to frame F n+1 . If they indicate 0010, the data must be moved by 2 frames from frame F n to frame F n+2 The CNTL data dropper 23 is a circuit for dropping the above described information transmitted through the above described control channel. Each piece of the dropped information is applied to the read address CNTL 24. In the read address CNTL 24, the frame correction instruction information D 0 , D 1 , D 2 , and D 3 for instructing how far the data are moved are converted to data synchronized with the data shown in Figure 9A. That is, as shown in Figure 12, the frame correction instruction information D 0 - D 3 is converted such that it is synchronized with the data in channels 0 - 127 of one frame. The frame correction instruction information D 0 - D 3 corresponds to each piece of the data in channels 0 - 127. For example, if the data D 0 - D 3 in the 0-th channel indicate 0000, the data in the 0-th channel require no frame correction. If the data D 0 - D 3 in the 1-th channel indicate 0000, the data in the 1-th channel require frame correction from F n to F n+1 . Thus, data are written to the memory 25 as shown in Figure 8 in order to obtain the information about the delay of data, that is, the information about what data is delayed by how many frames, calculated and provided by the software. Then, according to the 4-bit frame correction instruction information in D 0 - D 3 , the corresponding data are outputted without delay or outputted from the memory 25 after being delayed by the specified number of frames. For example, if the frame correction instruction information D 0 - D 3 for the data in channel 0 of frame 0 indicates 0000, the data are outputted without delay. If D 0 - D 3 indicate 0001, the data are controlled to be delayed by one frame from F n to F n+1 . In this case, all data are retained in order by delaying them to the point around the most delayed piece of data in a data string such that all pieces of data forming the data string are outputted in the same frame. For example, among data A, B, and C in three channels, if data C are delayed by two frames, the software instructs data A and B to be also delayed by two frames. In this case, the frame correction instruction information D 0 - D 3 for data A and B indicates 0010, and data A and B are outputted as delayed by two frames. Accordingly, data A, B, and C enter the same frame in order. The control of the delay of data in frames is explained below in detail in the cases where data A are not instructed to be delayed, data B are instructed to be delayed by one frame, and data C are instructed to be delayed by two frames. The explanation includes the operation of each part shown in Figure 8. Frame correction instruction information shown in Figure 11 is sent from the CPR 14 shown in Figure 7, and the information is written by the digital terminal common (DTC) to the control channel in the frame. In Figure 8, the data in each channel of multiframes are inputted by the switch unit, converted into an 8-bit parallel signal by the S/P converting circuit 21, and sequentially written to the memory 25 according to write addresses generated by the counter 22. The counter operates in synchronism with multiframes shown in Figure 9, and generates addresses according to the order from TS 0 of Frame 0 to TS 127 of frame 15. Read addresses from the memory 25 are controlled by the read address control 24. Flags in the data channel, TS number designation data, and frame correction instruction information are read from the frame inputted by the switch unit by the control data dropper 23. According to the above described information, read addresses from the memory 25 are controlled by the read address control 24. According to the content of frame correction instruction information, the whole data are read at the time depending on the address obtained by adding a 1-frame address for data B and a 2-frame address for data C. The second selector 27 outputs inputted data without delay if the data is not instructed to be frame-delayed, and outputs data outputted to a serial signal by the P/S converting circuit 28 after being read from the memory 25 of the data is instructed to frame-delayed. The important part of the embodiment of the present invention is explained furthermore in detail. Figure 13 is a flowchart for explaining the arithmetic operation performed by the data control unit 15 shown in Figure 7 for obtaining the delay of data in frames. In step S 30 shown in Figure 13, if a call is issued from line A to line B, for example, a time slot α 2 indicating the idle state as a signal state between the primary time switch and the secondary time switch in the switch unit is allocated in step S 31, an arithmetic operation is performed for obtaining the delay of data in frames on the condition shown in Figure 6 in step S 32, the information to be written to the control channel shown in Figure 11 is calculated in step S 33, data in the format shown in Figure 11 are set and a data delay correction instruction signal is outputted in step S 34, and a subscriber in line B is called in step S 35. Figure 14 shows the operation of the counter 22 shown in Figure 8. As shown in Figure 14, the counter is reset by the signal FCK indicating the start of a multiframe explained by referring to Figure 9, and the output value of the counter is stepped up each time a clock signal CK is inputted. According to the multiframe format shown in Figure 9, three bits in the lowest order among fourteen bits outputted from the counter represent a bit condition indicating the position of eight bits in a time slot, the next seven bits represents a time slot condition indicating the position of 128 time slots in one frame, and four bits in the highest order represents a frame condition indicating the position of 16 frames in multiframes. As shown in Figure 8, since data are written to the memory 25 in 8-bit units in parallel, a time slot condition and a frame condition determine a write address to the memory 25. Figure 15 is a block diagram indicating the detailed configuration of the embodiment of the digital terminal common shown in Figure 8. In Figure 15, the control data dropper 23 shown in Figure 8 comprises a first flipflop 30 for latching the information written in response to the output from the S/P converting circuit 21 to the control channels described in Figure 11, that is, flags, TS number designation, and frame correction instruction information. The read address control 24 comprises a correction data memory 31, a first three-state buffer 32, a third selector 33, a gate 34, a second flipflop 35, an adding circuit 36, and a zero detecting unit 37. The correction data memory 31 stores the frame correction instruction information from the output of the first flipflop 30. The first three-state buffer 32 is provided between the first flipflop 30 and the correction data memory 31. The third selector 33 selects a write address or a read address from the correction data memory 31 and outputs it. The gate 34 outputs a write enable signal for the correction data memory 31. The second flipflop 35 latches the frame correction instruction information read from the correction data memory 31. The adding circuit 36 adds the frame correction instruction information outputted by the second flipflop 35 to the lowest order 4-bit frame condition in the output from the counter 22 and outputs the result to the first selector 26. The zero detecting unit 37 detects zero in the output from the second flipflop 35, and has the second selector 27 select and output the data inputted from the switch unit when all the four bits outputted from the second flipflop 35 are are zero. In addition to these units, Figure 15 contains a second three-state buffer 38 provided between the S/P converting circuit 21 and the input terminal of the memory 25, a third flipflop 39 provided between the memory 25 and the P/S converting circuit 28, a memory gate control 40 for outputting a control signal to the first and second three-state buffers 32 and 38 and the gate 34, and a data latch control 41 for outputting a clock for a data latching to the three flipflops 30, 35, and 39. Figure 16 is a time chart indicating the operation of each unit shown in Figure 15. Figure 17 shows the relationship between the frame correction instruction information shown in Figure 15 and the read address of the data read from a memory. The operation of each unit shown in Figure 15 is explained in detail by referring to Figures 16 and 17. The data inputted by the switch unit in the format described in Figure 9 are converted to 8-bit parallel data by the S/P converter 21 as shown in Figure 16. The conversion causes a delay by one time slot as shown in Figure 16. If the counter 22 synchronizes with multiframes as described above, the outputs from the counter 22, that is, a time slot condition and a frame condition, are delayed by one time slot and stored in the memory 25 as a write address so that the memory 25 stores the data of TS 0 in frame 0 starting from address 0. The memory gate control 40 shown in Figure 15 issues a control signal, used in writing data in the memory 25, to the second three-state buffer 38, and outputs a write enable signal to the memory 25. The write enable signal is commonly used by the correction data memory 31 as shown in Figure 16. A write address and a read address for the memory 25 are assigned by a switching operation by the selector 26 such that, as shown in Figure 16, the area from bit B1 to bit B4 contains a write address, and the area from bit B5 and bit B8 contains a read address. The first flipflop 30 shown in Figure 15 latches data in control channels as described above, and a clock for the latch is generated by the data latch control 41 according to the 4-highest-order-bit frame condition and the next 7-bit time slot condition in the output from the counter 22. The frame correction instruction information in the output from the first flipflop 30 is provided as data for the correction data memory 31. The TS number designation information is provided as a write address for the correction data memory 31 through the third selector 33. A 1-bit flag is provided for the gate 34. If the flag indicates "1", a write enable signal is outputted from the gate 34 to the correction data memory 31 according to the data latch clock. At this time, the frame correction instruction information is stored in the correction data memory 31. In reading data from the correction data memory 31, a time slot condition outputted by the counter 22 is provided as a read address to the memory 31 through the third selector 33, and the read data are latched in the second flipflop 35. The latch clock is generated by the data latch control 41 as described above, and the clock is positioned at a switch point from bit B1 to bit B8 as shown in Figure 16. As a result, the frame correction instruction information is outputted in synchronous with the input data as explained by referring to Figure 12. The output from the second flipflop 35 is added by the adding circuit 36 to the four highest order bits in the output from the counter 22, that is, a frame condition, and provided through the first selector 26 as the four highest order bits in a read address of the memory 25. The four highest order bits in the read address correspond to a frame condition as described above, and the data outputted from the memory 25 are delayed in frames according to the frame correction instruction information by adding the frame condition outputted by the counter 22 to the output from the second flipflop 35, that is, frame correction instruction information. This is indicated in Figure 17. For example, the output from the second flipflop 35, that is, the frame correction instruction information, is "0001" for the inputted data in TS1 of frame 0. According to this, the inputted data are delayed and outputted to frame 1. In Figure 15, the data outputted from the memory 25 are latched in the third flipflop 39 in an 8-bit length, and the latched data are converted to a serial signal in the format of the inputted data by the P/S converting circuit 28. The second selector 27 selects whether the data inputted from the switch unit are outputted without delay, or the data from the memory 25 are outputted after being delayed. The selection condition is provided by the zero detecting unit 37. The zero detecting unit 37 detects according to the output from the second flipflop 35 whether or not the frame correction instruction information is "0000". If the information indicates "0000", the second selector 27 is controlled such that the data inputted from the switch unit are selected. Thus, the inputted data, the output from the P/S converting circuit 28, and the frame correction instruction information outputted by the second flipflop 35 are synchronized. As described above in detail, in the present invention, transmission data are temporarily stored in a memory to control the data in order according to the software-predetermined delay information for each piece of data corresponding to a channel. Thus, a data frame synchronous method can be realized in the PCM transmission line, and can be utilized efficiently in practical use. Since the present invention corrects data delay in frames in the PCM transmission line, it can be applied in various fields in data communication technologies. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A delay-in-frames correcting system operated in a switch unit in a PCM transmission line in which each piece of data corresponding to each channel is transmitted in a frame comprising a plurality of time slots corresponding to a plurality of channels, said system comprising: channel data storage means (7, 8) for temporarily storing data corresponding to each channel on the output side or the input side of said switch unit (6) in each direction of said transmission line, and data delay control means (9) for delaying data corresponding to channels and stored in said channel data storing means (7, 8) and outputting data in order in the same frame, characterized in that said data delay control means (9) controls said delay of data corresponding to the number of frames indicated by the most delayed data and outputs frame correction instruction information for outputting a data string in the same frame. The delay-in-frames correcting system according to Claim 1, wherein said switch unit (6) is provided with a T-S-T switch to which a data frame is applied to a primary time switch, a space switch, and a secondary time switch in that order, said data frame in said T-S-T switch comprises 1,024 time slots, and call processor means (14) forming said data delay control means (9) defines no delay if the following equations exist: α 1 ≦ α 2 510 and α 2 + 513 ≦ α 3 when, the position of data in each channel in said frame at the input to said primary time switch is "α 1 ", the position between said primary time switch and said secondary time switch is "α 2 ", and the position at the output from said secondary time switch is "α 3 ". The delay-in-frames correcting system according to Claim 1, wherein said switch unit is provided with a T-S-T switch to which a data frame is applied to a primary time switch, a space switch, and a secondary time switch in that order, said data frame in said T-S-T switch comprises 1,024 time slots, and call processor means (14) forming said data delay control means (9) defines a 1-frame delay if one of the following conditions exists: α 1 ≦ α 2 < 510, and α 2 + 513 > α 3 or α 1 ≦ α 2 , α 2 ≧ 511, and α 2 - 511 ≦ α 3 or α 1 > α 2 , α 2 < 511, and α 2 + 511 ≦ α 3 when, the position of data in each channel in said frame at the input to said primary time switch is "α 1 ", the position between said primary time switch and said secondary time switch is "α 2 ", and the position at the output from said secondary time switch is "α 3 ". The delay-in-frames correcting system according to Claim 1, wherein said switch unit (6) is provided with a T-S-T switch to which a data frame is applied to a primary time switch, a space switch, and a secondary time switch in that order, said data frame in said T-S-T switch comprises 1,024 time slots, and call processor means (14) forming said data delay control means (9) defines a 2-frame delay if one of the following conditions exists: α 1 > α 2 , α 2 < 511, and α 2 + 513 > α 3 or α 1 > α 2 , α 2 ≧ 511, and α 2 - 511 ≦ α 3 or α 1 ≦ α 2 , α 2 ≧ 511, and α 2 - 511 > α 3 when, the position of data in each channel in said frame at the input to said primary time switch is "α 1 ", the position between said primary time switch and said secondary time switch is "α 2 ", and the position at the output from said secondary time switch is "α 3 ". The delay-in-frames correcting system according to Claim 1, wherein said switch unit (6) is provided with a T-S-T switch to which a data frame is applied to a primary time switch, a space switch, and a secondary time switch in that order, said data frame in said T-S-T switch comprises 1,024 time slots, and call processor means (14) forming said data delay control means (9) defines a 3-frame delay if the following equations exist: α 1 > α 2 , α 2 ≧ 511, and α 2 - 511 > α 3 when, the position of data in each channel in said frame at the input to said primary time switch is "α 1 ", the position between said primary time switch and said secondary time switch is "α 2 ", and the position at the output from said secondary time switch is "α 3 ". The delay-in-frames correcting system according to Claim 2, 3, 4, or 5, wherein said call processor (14) means allocates to a call from line A to line B a time slot in the idle state in said switch unit as said position α 2 , a delay in frames is calculated using the values of said positions α 1 and α 3 , frame correction instruction information is calculated according to said calculation result, an instruction is issued to set said frame correction instruction information and to correct said delay in frames, and a subscriber in line B is called. The delay-in-frames correcting system according to Claim 1, wherein a frame applied to said channel data storage means (7, 8) has a multiframe configuration in which one time slot comprises t bits, one frame comprises n time slots, and one multiframe comprises N frames. The delay-in-frames correcting system according to Claim 1, wherein said channel data storage means (7, 8) comprises: S/P converting circuit means (21) for parallelly converting data corresponding to each channel in said frame, memory means (25) for storing the output from said S/P converting circuit means (21) corresponding to each channel, and P/S converting circuit means (28) for serially converting the parallel output obtained from said memory means corresponding to each channel. The delay-in-frames correcting system according to Claim 1, wherein said channel data storage means (7, 8) comprises: S/P converting circuit means (21) for parallelly converting data corresponding to each channel in said frame, memory means (25) for storing the output from said S/P converting circuit means (21) corresponding to each channel, and P/S converting circuit means (28) for serially converting the parallel output obtained from the memory means corresponding to each channel, said delay-in-frames control means (9) comprises call processor means (14) for setting a path in said switch unit (6) and outputting said frame correction instruction information, and further comprising: counter means (22) for generating a write address in writing the output from said S/P converting circuit means (21) to said memory means (25) for said channel data storage means (7, 8) and said data delay control means (9), first selector means (26) for providing the output from said counter means (22) as a writing address for said memory means (25), second selector means (27) for selecting and outputting either a frame inputted to said S/P converting circuit means (21) or the output from said P/S converting circuit means (28), control data dropper means (23) for searching the output from said S/P converting circuit means (21) for delay-in-frames correction instruction information outputted by said call processor means (14), and read address control means (24) for providing a data read address from said memory means (25) for said memory means (25) through said first selector means (26) according to the output from said control data dropper means (23), and for outputting a selection control signal for said second selector means (27). The delay-in-frames correcting system according to Claim 9, wherein said control data dropper means (23) searches the output from said S/P converting circuit means (21) for, in addition to said frame delay correction instruction information written to a control channel in a frame applied to said S/P converting circuit means (21), a flag indicating the validity/invalidity of data and a time slot number indicating the number of a time slot to be corrected for its frame. The delay-in-frames correcting system according to Claim 9, wherein a frame inputted to said channel data storage means (7, 8) has a multiframe configuration where one time slot comprises t bits, one frame comprises n time slots, and one multiframe comprises N frames, said counter means (22) is reset at the start of said multiframe, stepped up by a clock having a cycle corresponding to one bit in t bits forming said time slot, and outputs as a write address to said memory means (25) a frame condition bit, the highest order bit in the outputs from said counter means (22), indicating the frame position in said multiframe, and a time slot condition bit, the second-highest order bit in the outputs from said counter means (22), indicating the time slot position in said frame. The delay-in-frames correction system according to Claim 11, wherein said read address control means (24) outputs to said first selector means (26) as a read address of the data from said memory means (25) the sum of said frame delay correction instruction information outputted by said control data dropper means (23) and said frame condition bit outputted by said counter means (22). The delay-in-frames correcting system according to Claim 11, wherein said control data dropper means (23) comprises first flipflop means (30) for latching, in addition to said frame correction instruction information, a flag indicating the validity/invalidity of data and a time slot number to correct a delay in frames, and said read address control means (24) comprises: correction data memory means (31) for storing said frame correction instruction information in the outputs from said first flipflop means (30), first three-state buffer means (32) for controlling the time of storing in said correction data memory means (31) said frame correction instruction information outputted by said first flipflop means (30), said third selector means (33) for selecting either a time slot number outputted by said first flipflop means (30) or a time slot condition bit outputted by said counter means (22), and providing the result for said correction data memory means (31) as a write address or a read address, gate means (34) capable of outputting a write enable signal to said correction data memory means (31) when a flag outputted by said first flipflop means (30) indicates the validity of data, second flipflop (35) means for latching said frame correction instruction information outputted from said correction data memory means (31); adding circuit means (36) for adding said frame correction instruction information outputted by said second flipflop means (35) to a frame condition bit outputted by said counter means (22), and providing the sum for said first selector means (26) as a data read address from said memory means (25), and zero detecting means (37) for selecting and outputting data inputted to said S/P converting circuit means (21) to said second selector means (27) when detecting as totally zero said frame correction instruction information outputted by said second flipflop means (35), and further comprising: second three-state buffer means (38) provided between the output terminal of said S/P converting circuit means (21) and the data input terminal of said memory means (25), third flipflop means (39) provided between the data output terminal of said memory means (25) and the input terminal of said P/S converting circuit means (28), memory gate control means (40) for receiving a bit condition, outputted by said counter means (22), indicating a bit position in a time slot, and outputting a control signal to said first selector means (26), first three-state buffer means (32), gate means (34), and second three-state buffer means (38), and data latch control means (41) for receiving a frame condition bit and a time slot condition bit in the outputs of said counter means (22), and outputting a data latch clock to said first flipflop means (30), second flipflop means (35), and third flipflop means (39).

Inventors: KAKUMA SATOSHI, OKUYAMA YUZO, KAKUMA, SATOSHI, OKUYAMA, YUZO, Kakuma, Satoshi, c/o Fujitsu Limited, Okuyama, Yuzo, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H04Q11
IPC codes: H04J3, H04L7, H04Q11