Semiconductor input protective device against external surge voltage

Abstract: A semiconductor input protective device has an NPN type bipolar transistor (Q) and an N-channel MOS transistor (M3). In the NPN type bipolar transistor, the collector is connected to a signal line (8) and the emitter and the base are commonly connected to a ground line (6). In the N-channel MOS transistor (M3), either the drain or the source is connected to the signal line (8) and the other of either the drain or the source is connected to the signal line (8) and the gate is connected to either the signal line or the power source line. The N-channel MOS transistor has a threshold voltage higher than the power source voltage. The NPN type bipolar transistor (Q) and the N-channel MOS transistor (M3) having a thick gate insulation film are used as input protection elements so that, even when a high voltage interface is effected, the function of the protective MOS transistor is not interfered with.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a semiconductor input protective device, and more particularly to a semiconductor input protective device for protecting internal circuits against an abnormal voltage (hereinafter referred to as a "surge voltage") externally applied to a signal line. (2) Description of the Related Art A conventional semiconductor input protective device has CMOS semiconductor device, of the kind to which the present invention relates, is shown in Fig. 1A. As shown therein, the semiconductor input protective device is constituted by an N-channel MOS transistor M1 having a drain (an N-type diffusion layer 103-1) connected to a signal line 8 which is in turn connected to a pad 9, a source (an N-type diffusion layer 103-2) and a gate electrode 5N both connected to a ground line 6, and a P-channel MOS transistor M2 having a drain (a P-type diffusion layer 102-2) connected to the signal line 8, a source (a P-type diffusion layer 102-1) and a gate electrode 5P both connected to a power source line 7. Fig. 1B is an equivalent circuit diagram of the above semiconductor input protective device. The above conventional input protective device operates as follows. When a surge voltage positive with respect to the ground line 6 is applied to the signal line 8, the surge voltage is released or discharged to the ground line 6 by the lateral NPN bipolar action of the N-channel MOS transistor M1 and, when a negative surge voltage is applied to the signal line 8, a parasitic PN-diode D1 existing between the drain 103-1 of the MOS transistor M1 and a P-type silicon substrate 1 is forwardly biased, so that the surge voltage can be released to the ground line 6. Similarly, when a surge voltage positive with respect to the power source line 7 is applied to the signal line 8, a parasitic PN-diode D2 existing between the drain 102-2 of the P-channel MOS transistor M2 and an N-well 10 is forwardly biased, so that the surge voltage can be released to the power source line 7. On the other hand, when a negative surge voltage is applied to the signal line 8, the surge voltage can be released to the power source line 7 due to a drain breakdown of the P-channel MOS transistor M2. The MOS semiconductor device used in the above conventional semiconductor input protective device normally has a gate oxide film the thickness of which is the same as that in the MOS semiconductor device of an internal circuit. Therefore, assuming that, for example, the thickness of the gate oxide film is 10 nm, the operating voltage is 3.3 V and the input signal has a TTL (Transistor-Transistor-Logic) level of 5 V, the gate oxide film 11 of the protective MOS semiconductor device will be subjected constantly to an electric field at a maximum of 5.5 MV/cm, thereby allowing the flow of the tunnel current (Fowler-Nordheim current) through the semiconductor device concerned. This state constantly continues during the operation of the semiconductor device, so that the gate oxide film gradually deteriorates, thereby leading eventually to insulation breakdown and to the inability of the MOS semiconductor device to function as a protective device. This is one of the problems in the conventional semiconductor input protective device which is to be solved by the present invention. The document "Proceedings of the IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCE, ROCHESTER, MAY 16-19, pages 27.2.1-27.2.4" discloses a resistor less ESD protection device. SUMMARY OF THE INVENTION It is, therefore, an object of the invention to overcome the problems in the conventional semiconductor input protective device and to provide an improved semiconductor input protective device in which the resistance against surge voltages externally applied to a signal line is effectively enhanced. A semiconductor input protective device according to the present invention is defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be apparent from the following description of a preferred embodiment of the invention explained with reference to the accompanying drawings, in which: Fig. 1A is a schematic sectional view showing a conventional semiconductor input protective device of the type to which the present invention relates; Fig. 1B is an equivalent circuit diagram of the conventional circuit shown in Fig. 1A; Fig. 2A is a schematic sectional view showing a semiconductor input protective device not covered by the present invention; Fig. 2B is an equivalent circuit diagram of the circuit shown in Fig. 2A; and Fig. 3 is an equivalent circuit diagram of a device according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Now, an embodiment not covered by the present invention is explained with reference to the appended drawings in which the same or similar reference symbols or numerals refer to the same or like elements. Figs. 2A and 2B are respectively a schematic sectional view and an equivalent circuit diagram thereof showing a semiconductor input protective device not covered by the present invention. As shown in the drawings, there are formed on a surface portion of a P-type silicon substrate 1 a lateral NPN bipolar transistor Q and an N-channel Metal-Insulator-Semiconductor (MIS) transistor including, for example, a MOS transistor M3 having as an insulating gate oxide film, a field oxide film 4 of 0.6 µm thick. Specifically, the lateral NPN bipolar transistor Q has an emitter (an N-type diffusion layer 3-4) and a base (the P-type silicon substrate 1) both connected to the ground line 6, and a collector (an N-type diffusion layer 3-3) connected to the signal line 8. Next, the N-channel MOS transistor M3 has a source (an N-type diffusion layer 3-1) and a gate electrode 5 both connected to the power source line 7, and a drain (an N-type diffusion layer 3-2) connected to the signal line 8. In Figs. 2A and 2B, a pad 9 is a bonding terminal formed on the semiconductor chip and is connected to a signal terminal (not shown in the drawings) of the IC package. A similar pad is provided correspondingly to the ground terminal GND and the power source terminal V CC in the semiconductor chip. The ground line 6, the power source line 7 and the signal line 8, etc. are, for example, aluminum interconnecting layers fabricated in the semiconductor chip. The gate electrode 5 of the N-channel MOS transistor M3 is made of the same material as that of the MOS transistor constituting an internal circuit (not shown). Furthermore, the N-type diffusion layers 3-1 to 3-4 are formed simultaneously with the source/drain regions of the N-channel MOS transistors of the internal circuit. Hereunder, how the surge voltage externally applied to the semiconductor device is released will be explained. When a surge voltage positive with respect to the ground line 6 is applied to the signal line 8 through the pad 9, the lateral NPN bipolar transistor Q operates, thereby releasing the surge voltage to the ground line 6. On the other hand, when a negative surge voltage is applied to the signal line 8, the PN-diode formed by the collector 3-3 and the base (the P-type silicon substrate 1) of this transistor Q is forwardly biased thereby releasing the surge voltage to the ground line 6. Similarly, when a surge voltage positive with respect to the power source line 7 is applied to the signal line 8, this surge voltage can be released to the power source line 7 due to the punch-through of the N-channel MOS transistor M3 and, when a negative surge voltage is applied to the signal line 8, the N-channel MOS transistor M3 becomes conductive and the surge voltage can be released to the power source line 7 through the MOS transistor M3. In this embodiment, the gate electrode 5 of the N-channel MOS transistor M3 is connected to the power source line 7 but, this may instead be connected to the signal line 8 as shown by a dotted line in Figs. 2A and 2B. Furthermore, if two N-channel MOS transistors M3 and M4 are connected in parallel between the power source line 7 and the signal line 8 as shown in Fig. 3, with one of the gate electrodes being connected to the power source line 7 and the other being connected to the signal line 8, it is possible to further enhance the effect of the input protection performance.

Claims: A semiconductor input protective device formed between a power source line (7) and a ground line (6) and connected via a signal line (8) to an internal circuit, said semiconductor input protective device comprising: an NPN type bipolar transistor (Q) having a collector (3-3) connected to the signal line (8) extending to a pad (9), and an emitter (3-4) and a base (1) commonly connected to the ground line (6); a first N-channel MIS transistor (M3) in which one of a drain (3-2) and a source (3-1) thereof is connected to said signal line (8) and the other one of the drain and the source is connected to said power source line (7), said first N-channel MIS transistor (M3) having a threshold voltage higher than a power source voltage (V CC ) supplied to said power source line (7) and having a gate insulation film (4) thicker than a gate insulation film of a MIS transistor constituting said internal circuit; characterized by a second N-channel MIS transistor (M4) connected in parallel with said first N-channel MIS transistor (M3), with a gate of one of said first and second N-channel MIS transistors (M3, M4) being connected to the signal line (8) and a gate of the other one of said first and second N-channel MIS transistors being connected to the power source line (7).

Inventors: MURAYAMA MOTOAKI, MURAYAMA, MOTOAKI, Murayama, Motoaki, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01L27
IPC codes: H01L27