Data processing apparatus

Abstract: Disclosed is a data processing apparatus comprising a decode device for decoding an instruction code including an operation code and two register designation codes and an instruction execution device for executing appropriate process according to the results decoded by the decode device, wherein the instruction execution device executes a first process when the two register designation codes are different from each other and executes a second process when they are equal.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention This invention relates to a data processing apparatus, which is referred to as a central processing unit (CPU), a microprocessor or the like. (2) Description of the Related Art Some conventional data processing apparatuses are constructed so that memory is exclusively used as the operand of operations by operational instructions. In such apparatuses, predetermined operations are executed on the basis of an instruction consisting of an operation code indicating the type of the operation, two operand addresses indicating the locations of data in the memory, for example, a source operand address and a destination operand address. Some conventional data processing apparatuses are provided with a register called an accumulator and other registers also, the accumulator being implicitly used as an operand. In such apparatuses, operations are executed on the basis of an instruction consisting of a single register designation code indicating the register to operate besides the accumulator. Other conventional data processing apparatuses are provided with general-purpose registers, any of which can be combined to be the operands and operations are executed on the basis of an instruction consisting of an operation code indicating the type of an operation and two register designation codes indicating the register to operate. However, according to the firstly-mentioned apparatuses using memory exclusively as the operand, the instruction word is rather long because it demands an operand field having bit-length to accommodate two operand addresses. As a result, programs written by the use of such apparatuses tend to be large-sized. According to the secondly-mentioned apparatuses provided with an accumulator, the instruction word can be short because the instruction merely needs a register field which can accommodate a single register designation code whose bit-length is shorter than that of the operand address. However, operations are assigned mainly to the accumulator, so that frequent moves of data are required between the accumulator and either the other registers or the memory. Such an increase in the number of instructions to be written in programs may decrease the speed of process of the programs as well as increase the program sizes. According to the last-mentioned apparatuses provided with general-purpose registers, the number of instructions to be written in programs can be fairly decreased because any combination of the registers can be the operands. The instruction word can be comparatively short because the bit-length of the register designation code to be used is shorter than that of an operand address. Nevertheless, it is difficult for such apparatuses to be constructed so that the sizes of programs can be minimized both by various kinds of operations being executed and they are executed in short instruction word length because of the following problem: When an data processing apparatus is provided with, for example, 8 general-purpose registers, the bit-length of the register designation code to specify a register is made 3 bits; the instruction requires a total of 6-bit register field. Thus, 8-bit instruction word length is not practical because usable instructions in that case are at most 4 types while 16-bit instruction word length is actually demanded to get sufficient numbers of instructions types. SUMMARY OF THE INVENTION In view of the above problem, the object of this invention is to provide a data processing apparatus, which can minimize the sizes of programs by various types of operations being executed in a short instruction word length. The above object can be achieved by a General Purpose Register Architecture data processing apparatus arranged to process an 8-bit instruction, wherein the 8-bit instruction includes a first field for a 4-bit operation code, a second field for a first 2-bit register designation code, and a third field for a second 2-bit register designation code, the apparatus comprising: instruction execution means for executing an operation, the instruction execution means including two register groups each having a different function and each of which is composed of four registers; and selection means for selecting one of the two register groups, the selection of the register group, and the type of operation to be executed by the instruction execution means, being determined by the value of the 4-bit operation code. Other preferred features of the present invention are set out in the appended dependent claims. Thus, according to the above constructions, various types of operations can be executed in a short instruction word length, and the sizes of programs can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate a specific embodiment of the invention. In the drawings:- FIG. 1 is a block diagram showing the construction of the main part of a data processing apparatus of this invention. FIG. 2 is an illustration showing the detailed construction of a register array. FIG. 3 is an illustration showing the detailed construction of a status register. FIG. 4 shows examples of the constructions of instruction codes. FIG. 5 is a table showing examples of assigning different operations to different instruction codes. DESCRIPTION OF THE PREFERRED EMBODIMENT The embodiment of this invention is described as follows with reference to FIGS. 1 through 5. FIG. 1 includes components 11-17. The instruction buffer 11 temporarily stores instructions fetched from an unillustrated memory. The instruction register 12 holds instructions outputted from the instruction buffer 11 until they are decoded or executed. The register designation code identification inquiry unit 13 inquires, when two register designation codes are included in one instruction, as to whether they are equal or not. The instruction decoder 14 decodes instructions held in the instruction register 12 and outputs a control signal to control the operation of each unit of the data processing apparatus. The instruction decoder 14, when the operation code included in an instruction is a predetermined one, conducts different controls (described later) depending on the results inquired by the unit 13: they are equal or different from each other. The detailed description of the construction of the circuit to conduct such control is omitted because the circuit can be a microprogram circuit or a hardware logic circuit as well-known processors can. The register array 15, as shown in FIG. 2, has a data register group consisting of data registers D0-D3 each having 16-bit length, an address register group consisting of address registers A0-A3, a program counter PC holding the storing address of the instruction in execution, and a status register PSW (processor status word) indicating the status of the data processing apparatus. The data registers D0-D3 are mainly used for storing data, as working storage. On the other hand, the address registers A0, A1, and A2 are used for storing addresses indicating a source operand, a destination operand, or a frame pointer, A3 being used for storing an address indicating a stack pointer. Although the address registers A0-A2 are usually assigned in the above order when a program is made, their hardware is constructed so that the assignment of the address registers A0-A2 can be flexible and the assignment of the address register A3 can be fixed to use for a stack pointer. All the data registers D0-D3 and all the address registers A0-A3 are designated by register designation codes of 00-11 (binary characters) in the instruction codes. The status register PSW, as shown in FIG. 3, consists of a trace flag T designating a single step execution of a program during an operation in a debug mode, interruption mask flags IM3-IM0 designating 16-level interruption masks, an overflow flag V, a carry flag C, a negative flag N, and a zero flag Z all indicating the results of operations. The execution unit 16 inputs data and addresses outputted from the register array 15, immediate data outputted from the instruction buffer 11, data fetched from the unillustrated memory through the internal data bus 17 and executes predetermined operations such as arithmetic operations, logical operations, and moves according to a control signal from the instruction decoder 14. The results obtained by the execution of the execution unit 16 are moved to the register array 15 and the memory through the bus 17 and held by specific registers corresponding to the instructions or by other units. The data processing apparatus of this embodiment is further provided with a data bus interface connected to the data bus of the unillustrated external portion of the data processing apparatus, an address bus interface connected to an address bus, and other units. These units are not described here because they are not directly related to this invention. The following is a description of the construction of the instruction code assigned to the data processing apparatus and an example of assigning operations to operation codes with reference to FIGS 4 and 5. The instruction system described here is a read/store instruction system, which can simplify the construction of the apparatus and easily increase the processing speed, that is, an instruction system capable of mainly moving data between each register and the memory. FIG. 4 shows examples of the constructions of instruction codes. The code (a) consists of a 4-bit operation code, two 2-bit register designation codes, Dn and Dm, or Dn and Am (both n and m are integers of 0-3). The code (b) includes either 8-bit immediate data (imm8), 8-bit displacement of an address (d8), or an 8-bit absolute address (abs8), in addition to the same operation code and the register designation codes as the code (a). The code (d), which is not part of the present embodiment, consists of an 8-bit operation code and an appended portion of either 8, 16, or 24 bits such as an expansion instruction, immediate data, or addressing displacement. In FIG. 5 showing an example of assigning instruction codes, the symbols "***" and "**" indicate that any one of the operations shown in the column of operation is executed according to the value of 3-bit or 2-bit respectively. The following is a description of each instruction code according to each instruction type. An instruction type [R-R] is a dyadic operation instruction between two data registers and is expressed by an instruction code "0***DnDm" (n≠m). This instruction code indicates 8 different types of operation instructions as follows, depending on the 3-bit values, "***". (1) Moving data from a data register indicated by the data register designation code Dn (hereinafter referred to as data register Dn) to the data register Dm. (2) Adding data held in the above data registers without carries. (3) Subtracting the same without borrows. (4) Comparing the same. (5) Adding the same with carries. (6) Subtracting the same with borrows. (7) Logically producing the same. (8) Logically adding the same. The results of each execution are stored in the data register Dm. An instruction type [imm8-R] can be distinguished from the instruction type [R-R] because its two register designation codes are equal (n=m). The data register Dn data and 8-bit immediate data (imm8), which follows an instruction code, "0***DnDm" are processed by the same dyadic operation as the instruction type [R-R]. Even if 8-bit immediate data is used for operations, 16-bit data is inputted to the execution unit 16; however, its high-order 8 bits are provided with zero filling (for example in logical operations), sign bit filling (for example in arithmetic operations), or the like, according to the type of the operation. The instruction types [LD] and [ST] are respectively a data move instruction (load) from the memory to the data register Dn and a reverse data move instruction (store). The sources and destinations in the memory are indicated by 4 types of addressing modes. The symbol "@" in the column of operation in FIG. 5 is put before the value which is the address of the area to/from which data is moved, and the symbol "( , )" indicates the sum of the values of both sides of comma. The addressing mode of each move instruction indicates the followings. (1) When the source or destination of data is "@Am", it represents address register indirect addressing, which has a value stored in the address register Am as its address. (2) When the source or destination of data is "@(Am, d8)", it represents address register indirect addressing with 8-bit displacement, which uses 8-bit displacement d8 following the instruction codes "1001DnAm" or "1101DnAm", and which has the sum of d8 and a value stored in the address register Am as its address. (3) When the source or destination of data is "@(Am, D0)", it represents index addressing, which uses the address register Am (m≠3) and the data register DO (fixed), and which has the sum of a value stored in the address register Am and a value stored in the data register D0. (4) When the address or addressee of data is "@abs8", it represents 8-bit absolute addressing, which has 8-bit absolute address abs8 following the instruction code as its address. In the index addressing of (3) above, the address registers A0-A2 are exclusively used, the address register A3 being excepted. This is because this type of addressing is usually used to move data such as strings or arrays, which are rarely moved to the stack area of the memory. In the 8-bit absolute addressing of (4) above, the register designation code m=3 representing the address register A3 excepted in the index addressing is used as a dummy and an instruction code, where the data register D0 of the source or the destination is definitely used is assigned thereto. When data move is performed in 8-bit absolute addressing, a predetermined value such as "00000000" can be outputted as the high-order 8 bits out of 16-bit address from the data processing apparatus. There are two groups of three instruction codes whose high-order 4 bits are respectively "1010" and "1110", which are not assigned any operation in the above example. These instruction codes are used to move their addresses to the address registers A0-A3, to assign unillustrated other instructions, to expand instruction codes to more than 16 bits, and other purposes. Thus, instructions with few frequency of use and with little effect on program sizes can be set as expansion instruction codes. The detailed description of such an expansion is omitted because it is not directly related to this invention. When an instruction code whose most significant bit is zero, like "01110001" is inputted to the data processing apparatus constructed as above, the register designation code identification inquiry unit 13 compares the least and second least significant bits "01" to the third and forth least significant bits "00", and then outputs a signal indicating that n of Dn and m of Dm are not identical, to the instruction decoder 14. The unit 14, then, outputs a control signal to the data registers D0 and D1, and makes them output data held in them to the execution unit 16 through the internal data bus 17. The unit 14 also outputs to the execution unit 16 a control signal by which a logical add operation is executed on the basis of the second, third, and forth most significant bits of the instruction code, "111". Responding to this, the execution unit 16 executes a logical add operation of data outputted from the data register D0 and D1. The results are stored in the data register D1 through the internal data bus 17. On the other hand, when the data processing apparatus is inputted a code "01110000" and the succeeding 8-bit immediate data, the register designation code identification inquiry unit 13 confirms n and m being equal. Then, data held in the data register D0 and 8-bit immediate data accumulated in the instruction buffer 11 are inputted to the execution unit 16 through the internal data bus 17, and a logical add operation is executed and the results are stored in the data register D0. In other words, according to the conventional data processing apparatuses, if two identical register designation codes are used to execute the same operation as non-identical register designation codes, the value of, for example, the data register D0 will not change. In contrast, according to the data processing apparatus of this invention, 16 types of instructions can be assigned in 3-bit field indicated by the symbol "***" in FIG. 5, by being made to execute a different operation in such a case. Consequently, various types of operations can be performed even if the basic instruction word length is 8 bits. However, some instructions may be designed to execute the same operations as non-identical register designation codes by, for example, using the execution of subtraction in the identical register designation codes as a clear instruction of the register. In the above case, one register can be designated in a 2-bit field by dividing 8 registers in the register array 15 into two groups having different functions: the data registers D0-D3 and the address registers A0-A3. Therefore, even if the 8-bit instruction code is made to include two register designation codes: a source register and a destination register, the type of the operation can be designated by the remaining 4 bits long; consequently, various types of operations can be executed in much shorter basic instruction word length. As a result, frequently used eight basic operations such as operations among data registers, operations between the data registers and immediate data, moves between the data registers and the memory, and single-operand operations assigned to one data register can be executed by an instruction having a short word length. According to the registers and operation instructions of the above construction, the environment of minimum requirements can be provided in order to effectively execute processing by a high-level language such as C language, the sizes of programs can be minimized, and the speed of process can be increased. Although the immediate data and the absolute address in the instruction codes are 8 bits in length and are expanded to 16 bits long according to the instruction in the above embodiment, 16-bit immediate data may be designed to be used if necessary. Although the instruction code is decoded into an instruction including an appended portion as immediate data when the two register designation codes are identical in the above embodiment, it may be designed to be decoded into an instruction including an appended portion as an immediate address or an instruction including no appended portion. Furthermore, this invention is applicable also to the constructions of registers and instruction codes, the types of operations, and bit assignments of operation codes, all of which are different from those in the above embodiment in order to adjust to the various use of the data processing apparatuses. Moreover, the instruction decoder 14 may be constructed so that it decodes the two register designation codes as different instructions depending on whether they are identical or not, instead of providing the register designation code identification inquiry unit 13. Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art.

Claims: A General Purpose Register Architecture data processing apparatus arranged to process an 8-bit instruction wherein the 8-bit instruction includes a first field for a 4-bit operation code, a second field (Dn) for a first 2-bit register designation code, and a third field (Dm,Am) for a second 2-bit register designation code, the apparatus comprising: instruction execution means (16) for executing an operation, the instruction execution means including two register groups (D0-D3,A0-A3) each having a different function and each of which is composed of four registers; and selection means for selecting one of the two register groups (D0-D3,A0-A3), the selection of the register group, and the type of operation to be executed by the instruction execution means, being determined by the value of the 4-bit operation code. Apparatus according to Claim 1, further comprising: instruction read means (11) for reading an instruction which includes a 4-bit operation code and first and second 2-bit register designation codes; and instruction decode means (14) for decoding the instruction read by the instruction read means; wherein the instruction execution means (16) is arranged to execute an operation based on the instruction decoded by the instruction decode means (14), and the instruction execution means includes a plurality of register groups (D0-D3, A0-A3) each having a different function and each of which is composed of four registers; a first operand of the operation is specified by one of the four registers belonging to a register group selected from the plurality of register groups, the one of the four registers being designated by the first 2-bit register designation code; a second operand of the operation is specified by one of the four registers belonging to a register group selected from the plurality of register groups, the one of the four registers being designated by the second 2-bit register designation code, the two register groups to be selected in relation to the first operand and the second operand are designated by a 4-bit operation code, and the type of operation executed by the instruction execution means is also designated by the 4-bit operation code. Apparatus according to Claim 2, wherein the first operand is a value stored in one of the four registers (D0-D3) designated by the first 2-bit register designation code. Apparatus according to Claim 2, wherein the first operand is a value stored in an area designated by the value stored in one of the four registers (A0-A3) designated by the first 2-bit register designation code. Apparatus according to Claim 2, wherein the second operand is a value stored in one of the four registers (D0-D3) designated by the second 2-bit register designation code. Apparatus according to Claim 2, wherein the second operand is a value stored in an area designated by the value stored in one of the four registers (A0-A3) designated by the second 2-bit register designation code. Apparatus according to any of Claims 1 to 6, wherein the instruction further comprises a numeral code appended to the 8-bit instruction code. Apparatus according to Claim 7, wherein the numeral code is a code which represents one of an immediate value (imm8), a displacement value (d8), and an absolute address value (abs8). Apparatus according to any of Claims 2 to 6, wherein the operation executed by the instruction execution means (16) is one of: a calculation (MOV, ADD, SUB,...,OR) between the plurality of registers in the register groups (D0-D3); and a data transfer (LD,ST) between a memory and one of the plurality of register groups (D0-D3,A0-A3).

Inventors: DEGUCHI MASASHI, MATSUZAKI TOSHIMICHI, DEGUCHI, MASASHI, MATSUZAKI, TOSHIMICHI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: G06F9
IPC codes: G06F9