Bit timing recovery circuit

Abstract: A base-band delayed detector has an operation circuit (1 - 59) for performing a delayed detecting operation with respect to an input signal, the operation circuit (1 - 59) outputting an altered signal having a predetermined symbol rate. The base-band delayed detector includes a clock generator (31, 33) for generating a clock signal having a frequency twice as large as the symbol rate, the clock signal being used, as a timing signal, in the operation circuit (1 -59), a synchronizing circuit (2, 32, 35) for synchronising the clock signal with the altered signal output from the operation circuit; and a data determination circuit (60, 61, 62) for obtaining output data from the altered signal at a predetermined timing defined based on the clock signal synchronized with the altered signal.

Description: The invention refers to a base-band delayed detector and in particular to a bit timing recovery circuit for deriving a clock signal from an altered signal which has been digitally generated by an operation means from an input signal and which has a predetermined symbol rate, wherein said clock signal is used as a timing signal in said operation means, according to the preamble of claim 1. Such a circuit is known from document EP-A-0 079 107. EP-A-0 079 107 discloses a circuit for deriving a clock signal from a received signal which has been digitally processed in a processing unit and is available only as a sampled signal at discrete time intervals. The clock signal is derived such that at least some of the samples are taken at intervals which correspond to nominal zero crossings. The output of two sampling circuits produce an error signal which is used to control the frequency of an oscillator which drives a timing generator. The clock signal is further used for clocking a flip-flop for transferring the information of the incoming signal to a processing output. A problem of such a circuit is the fact that the synchronizing means is realized by a conventional voltage controlled oscillator which is expensive and which is large in scale. Furthermore, a conventional base-band delayed detector operating in accordance with a π/4 shifted QPSK (Quadrature Phase Shift Keying) is shown in FIG. 1. Referring to FIG. 1, this base-band delayed detector has mixers 51 and 52, a local oscillator 53, a shifter 54, low pass filters 55 and 56, analogue to digital converters 57 and 58, an operation circuit 59 and clock generator 63. The mixer 51 converts an IF signal supplied from a circuit (not shown) provided prior thereto into a base band signal having a frequency falling within a base band, by using a local signal output from the local oscillator 53. The shifter 54 shifts a phase of the local signal by π/2. The mixer 52 converts the IF signal into a base band signal by using the shifted local signal. Each of the low pass filters 55 and 56 damps a sum component of a corresponding base band signal and makes a differential component thereof pass through it. The operation circuit 59 carries out a delayed detecting operation with respect to I-channel data and Q-channel data which are obtained through the base band signals supplied thereto respectively via the analogue to digital converters 57 and 58. The analogue to digital converters 57 and 58 and the operation circuit 59 are operated in synchronism with a timing clock signal output from the clock generator 63. The base-band delayed detector also has data discriminators 60 and 61, a serial to parallel converter 62 and a BTR (Bit Timing Recovery) circuit 64. Each of the data discriminators 60 and 61 generates discriminated data from the output data of the operation circuit 59 in synchronism with a clock signal. The serial to parallel converter 62 converts serial data supplied from each of the discriminators 60 and 61 into parallel data. The BTR circuit 64 generates the clock signal used for operation of the discriminators 60 and 61 and the serial to parallel converter 62. The IF signal is defined as cos(ω c ·t +) and the local signal is defined as cos(ω L ·t + ), where  is a modulation signal component and a relationship ω c ≒ ω L stands. In this case, the above base-band delayed detector operates as follows. The mixer 51 converts the IF signal cos(ω c ·t + ) into the base band signal by using the local signal cos(ω L ·t + ). The mixer 52 converts the IF signal cos(ω c ·t + ) into the base band signal by using the shifted local signal - sin(ω L ·t + ). As the sum components of the base band signals are respectively damped by the low pass filters 55 and 56, the differential component cos (Δω·t +  - ) of the base band signal is output from the low pass filter 55, and the differential component sin(Δω · t +  - ) of the base band signal is output from the low pass filter 56. Δω is defined as Δω = ω c - ω L . In a case where Δω = 0, the differential components are respectively represented by cos( - ) and sin( - ). In this case, as only  varies with the passage of time in the signal after passing through each of the low pass filters 55 and 56, an eye pattern in which signals are superimposed seems to stop. There is a phase difference  between the IF signal and the local signal, so that the eye pattern seems to stop in either a state (A) shown in FIG.2A, a state (B) shown in FIG.2B or an intermediate state between the states (A) and (B). In a case where Δω ≠ 0, the eye pattern seems to gradually vary with the passage of time, in an order of states:(A) → (B) → (A) → (B) → .... In the base-band delayed detector, as ω c and ω L are in synchronism with each other, the eye pattern normally seems to vary. The analog to digital converters 57 and 58 respectively output the following signals X k and Y k in synchronism with the clock signal. X k = cos(Δω·t k +  k - ) Y k = sin(Δω·t k +  k - ) The operation circuit 59 carries out the following operation with respect to the above signals X k and Y k in synchronism with the clock signal: I k ' = X k X k-1 + Y k Y k-1 = cos[Δω·(t k -t k-1 ) + ( k - k-1 )] Q k ' = Y k X k-1 + X k Y k-1 = sin[Δω·(t k -t k-1 ) + ( k - k-1 )] where t k is a k-th time at which the analog to digital converters 57 and 58 samples t k-1 is a time prior to the time t k by one symbol time, X k , Y k and  k are respectively X, Y, and o at the time t k , and X k-1 , Y k-1 and  k-1 are respectively X, Y, and  at the time t k-1 . As one symbol time Δt = t k -t k-1 is constant and the difference Δω is approximately equal to zero (Δω ≒ 0), I k ' and Q k ' can be represented by the following formulas. I k ' = cos( k -  k-1 ) Q k ' = sin( k -  k-1 ) In a case where data (I, Q) is transmitted by a transmitter in accordance with the following relationship between the data (I, Q) and the amount of phase shift Δ (=  k -  k-1 ), [I] [Q] [Δ ] 1 1 π/4 0 1 3·π/4 0 0 -3·π/4 1 0 -π/4 the following received data (I k , Q k ) is obtained. If I k ' > 0, I k = 1. If I k ' < 0, I k = 0. If Q k ' > 0, Q k = 1. If Q k ' < 0, Q k = 0. In the base-band delayed detector described above, it is necessary to supply the clock signal to the analog to digital converters 57 and 58, the operation circuit 59, the data discriminators 60 and 61 and the serial to parallel converter 62. However, in a circuit provided prior to the operation circuit 59, the eye pattern varies with the passage of time, it is hard to detect edges of modulated signals and to generate a clock signal having a pertinent phase. Thus, in the conventional base-band delayed detector, the clock generator 63 must generate a clock signal having a frequency greatly larger than a symbol rate of the base band signal. The clock signal, having a frequency which is, for example, 36 times of the symbol rate, is used in operations in the analog to digital converters 58 and 57 and the operation circuit 59. In addition, it is possible to propose a base-band delayed detector in which the clock generator generates a clock signal having a frequency slightly higher than the symbol rate of the base band symbol, and output data from the operation circuit 59 is converted into an analogue signal by a digital to analogue converter. However, in a case where a clock signal having a frequency greatly higher than the symbol rate is used, the amount of electric power used in the base-band delayed detector is increased. In a case where the digital to analogue converter is provided in the base-band delayed detector, a circuit in the base-band delayed detector becomes of a large scale. It is an object of the invention to provide a bit timing recovery circuit which can cheaper be integrated in a processor of an operation circuit. This object is solved by the features of the claim 1. Additional objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a conventional base-band delayed detector. FIGs. 2A and 2B are diagrams illustrating eye patterns. FIG. 3 is a block diagram illustrating an essential configuration of a base-band delayed detector according to a first embodiment of the present invention. FIG. 4 is a timing chart illustrating a relationship between clock signals and a base band signal in the base-band delayed detector according to the embodiment of the present invention. FIG. 5 is a block diagram illustrating a base-band delayed detector according to the first embodiment of the present invention. FIG. 6 is a timing chart illustrating signals generated in the base-band delayed detector shown in FIG.5. FIG.7 is a block diagram illustrating a modification of the first embodiment. FIG.8 is a block diagram illustrating a base-band delayed detector according to a second embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will now be given of the principle of a fist embodiment of the present invention with reference to FIGS.3 and 4. Referring to FIG.3, which shows an essential part of a base-band delayed detector, a base band signal Si varying in accordance with a predetermined symbol rate (f) is supplied to an analog to digital converter 101. A clock generator 21 generates a clock signal having a frequency (2f) twice as large as the symbol rate (f) of the input base band signal. The analog to digital converter 101 converts the input base band signal Si into digital data in synchronism with the clock signal. A delayed detecting operation unit 100 carries out a delayed detecting operation with respect to the data, supplied from the analog to digital converter 101, in synchronism with the clock signal. A data sampling unit 92 samples the output data from the delayed detecting operation unit 100, at a point close to an opening of the eye pattern in which base band signals are superimposed, in synchronism with a data sampling clock having a frequency (f) half that of the clock signal (2f). A zero-cross point sampling unit 93 samples the output data from the delayed detection operation unit 100, at a zero-cross point of the eye pattern, in synchronism with a zero-cross sampling clock signal having a frequency (f) half that of the clock signal (2f). There is a reversal relationship (where one is high, the other is low and vice versa) between the data sampling clock signal and the zero-cross point sampling clock signal. A detection unit 94 detects an amount of phase shift of the clock signal (2f) with respect to the output data from the delayed detecting operation unit 100 based on a variation of polarities of data sampled by the data sampling unit 92 and the zero-cross point sampling unit 93. The amount of phase shift obtained by the detection unit 94 is supplied to a phase control unit 95. The phase control unit 95 controls a phase of the clock signal (2f), generated by the clock generator 91, based on the amount of phase shift supplied thereto. When the output data from the delayed detecting operation unit 100 and the clock signal (2f) become in synchronism with each other, a data recognition unit 102 recognizes detection data So in synchronism with the same clock signal as the data sampling clock. The output data from the delayed detecting operation unit 100 is sampled, in synchronism with the clock signal (2f), alternatively, by the data sampling unit 92 and the zero-cross sampling unit 93. In a case where data sampled by the zero-cross sampling unit 93 at a time t k has the same polarity as data sampled by the data sampling unit 92 at the next time t k+1 in the clock signal (2f), as shown in FIG.4 (a), the detection unit 94 determines that there is phase lag of the clock signal (2f) with respect to the output data from the delayed detecting operation unit 10. In a case where data sampled by the zero-cross sampling unit 93 at a time t s has the same polarity as data sampled by the data sampling unit 92 at the prior time t s-1 in the clock signal (2f), as shown in FIG.4 (b), the detection unit 94 determines that the phase of the clock signal (2f) precedes the output data from the delayed detecting operation unit 10. A description will now be given of the first embodiment of the present invention with respect to FIGS.5 and 6. In FIG.5, those parts which are the same as those shown in FIG.1 are given the same reference numbers. The base-band delayed detector shown in FIG.5 is provided, for example, in a mobile station carrying out a mobile communication to a base station. Referring to FIG.5, which shows a base-band delayed detector operating in accordance with π/4 shift QPSK, The base-band delayed detector has the mixers 51 and 52, the local oscillator 53, the shifter 54, the low pass filters 55 and 56, the analog to digital converter 57 and 58, the operation circuit 59, the discriminators 60 and 61, and the serial to parallel converter 62. A BTR (Bit Timing Recovery) circuit 1 is provided with the base-band delayed detector. The BTR circuit 1 has a phase comparison result detection unit 2 and a digital PLL unit 3. The operation circuit 59 outputs data I' (a) from an I-channel and data Q' from a Q-channel. The BTR circuit 1 generates a data sampling clock signal (d) having a frequency fs equal to a symbol rate of a base band signal operated in this base-band delayed detector. The data sampling clock signal (d) is supplied to the discriminators 60 and 61 and the serial to parallel converter 62. The BTR circuit 1 also generates a clock signal (b) having a frequency (2fs) twice as large as the symbol rate of the base band signal. The clock signal (b) is supplied to the analog to digital converters 57 and 58, the operation circuit 59, discriminators 60 and 61 and the serial to parallel converter 62. The phase comparison result detection unit 2 has a first flip flop 21, a second flip flop 22, a first exclusive OR circuit 23 (EOR circuit 23) and a second exclusive OR circuit 24 (EOR circuit 24). The first flip flop 21 samples a MSB (Most Significant Bit) of the data I' output from the I-channel of the operation circuit 59 in synchronism with the data sampling clock signal (d). The MSB of the data I' represents a polarity thereof. The data sampling clock signal (d) is inverted by an inverter 25, so that a zero-cross sampling clock signal (c) is obtained. The second flip flop 22 samples the MSB of the data I' output from the I-channel of the operation circuit 59 in synchronism with the zero-cross sampling clock signal (c). A first output signal of the fist flip flop 21 and a second output signal of the second flip flop 22 are input to the first EOR circuit 23. An output (f) of the first EOR circuit 23 is supplied to the second EOR circuit 24 controlled by the zero-cross sampling clock signal (c). An output (g) is supplied to the digital PLL unit 3. The output (f) of the first EOR circuit 23 is referred to as a changing point detection signal, and the output (g) of the second EOR circuit 24 is referred to as a phase comparison signal. When the polarity of the data I' is changed, the changing point detection signal is activated. When the zero-cross sampling clock signal (c) has a phase lag with respect to each zero-cross point of the eye pattern, the phase comparison signal (g) has a low level (L). When the zero-cross sampling clock signal (c) of has a phase preceding each zero-cross point of the eye patter, the phase comparison signal (g) has a high level (H). The digital PLL unit 3 has a sequential filter 35, an oscillator 31, a pulse control circuit 32, a first divider and a second divider 34. The oscillator 31 outputs a clock signal having a predetermined frequency. The pulse control circuit 32 adds one or plurality of pulses to the clock signal output from the oscillator 31 in accordance with the phase comparison signal (g) supplied thereto via the sequential filter 35. The first divider 33 divides a pulse signal output from the pulse control circuit 32 so that a clock signal having a frequency (2f) twice as large as the symbol rate. The second divider 34 divides the clock signal having the frequency (2fs) output from the first divider 33 so to output the clock signal having a frequency (fs) equal to the symbol rate. The sequential filter 35 has an up-down counter. The up-down counter respectively carries out an up-count operation and down-count operation in synchronism with the changing point detection signal (f) in accordance with the levels (H) and (L) of the phase comparison signal (g). When a count value in the up-down counter reaches upper limit value, the pulse control circuit 32 subtracts one or a plurality of pulses from a pulse signal output from the oscillator 31 so that a phase of the clock signal (2fs) precedes. When a count value in the up-down counter reaches a lower limit value, the pulse control circuit adds one or plurality of pulses to the pulse signal output from the oscillator 31 so that a phase of the clock signal (2fs) lags. Due to the sequential filter 35, errors based on jitter of the clock signal can be prevented from generating. The BTR circuit 1 is operated in accordance with a timing chart shown in FIG.6. The I-channel data (a), the clock signal (b), the zero-cross sampling clock signal (c), the data sampling signal (d), a polarity bit (e), the changing point detection signal (f) and the phase comparison signal (g) are indicated in FIG.6. The polarity bit (e) is the MSB of the data I' output from the I-channel of the operation signal, so that the polarity bit (e) represents a polarity of the I-channel data (a) sampled in synchronism with the clock signal (b). The clock signal (b) can be divided into the zero-cross sampling clock signal (c) and the data sampling clock signal (d). The zero-cross sampling clock (b) is used for sampling the level (data) of the base band signal at a point close to each zero-cross point of the eye pattern. The data sampling clock signal (d) is used for sampling the level (data) of the base band signal at a point close to each opening of the eye pattern. A relationship between the polarity of the data sampled in synchronism with the data sampling clock signal (d) and the polarity of the data sampled in synchronism with the zero-cross sampling clock signal (c) represents a condition of the phase of the clock signal (b) with respect to the eye pattern (the base band signal). That is, in a case where the polarity of the data sampled in synchronism with the zero-cross sampling clock signal (c) at a time (zero-cross sampled time) is equal to the polarity of the data sampled in synchronism with the data sampling clock signal (d) at a time prior to the zero-cross sampled time by one clock of the clock signal (b), there is no zero-cross point between a raising point of the zero-cross sampling clock signal (c) and a raising point of the data sampling clock signal (d). Thus, in this case, it can be determined that a phase of the clock signal (b) precedes a phase of the eye pattern. Alternatively, in a case where the polarity of the data sampled in synchronism with the zero-cross sampling signal (c) at a time (zero-cross sampled time) is equal to the polarity of the data sampled in synchronism with the data sampling signal (d) at a time after the zero-cross sampled time by one clock of the clock signal (b), there is a zero-cross point between a raising point of the zero-cross sampling clock signal (c) and a raising point of the data sampling clock signal (d). Thus, in this case, it can be determined that a phase of the clock signal (b) lags from a phase of the eye pattern. In the phase comparison result detection unit 2, signals are generated as follows. The first EOR circuit 23 carries out an exclusive OR operation of the output signals of the first and second flip flops 21 and 22 (a differential full-wave rectification), so that the changing point detection signal (f) is output from the first EOR circuit 23. The changing point detection signal represents a point at which the polarity of the I-channel data (a) is changed. Further, the second EOR circuit 24 carries out an exclusive OR operation of the changing detection signal (f) and the zero-cross sampling clock signal (c), so that the phase comparison signal (g) is output from the second EOR circuit 24. In a case where the changing point detection signal (f) has a high level (H), a high level (H) of the phase comparison signal (g) represents that a phase of the clock signal (b) preceeds that of the eye pattern, and a low level (L) of the phase comparison signal (g) represents that a phase of the clock signal (b) lags from that of the eye pattern. In a case where each raising point of the zero-cross sampling clock signal (c) corresponds to each zero-cross point of the eye pattern corresponds to each other, the clock signal (b) has an appropriate phase. In this case, data can be sampled in synchronism with the data sampling clock signal (d) at a centre point in the opening of the eye pattern, so that the data is stably demodulated. Thus, the digital PLL unit 3 control the phase of the clock signal (b) based on the phase comparison signal (f). In the digital PLL unit 3, the pulse control circuit 32 adds to or subtracts from, one or a plurality of pulses, the pulse signal output from the oscillator 31 in accordance with the phase comparison signal (g) supplied from the phase comparison unit 2. As a result, a phase of the clock signal (b) output from the first divider 33 and a phase of the data sampling clock signal (d) are controlled. In an equilibrium state, the level of the phase comparison signal (g) is alternatively changed from high level (H) to the low level (L) and vice versa. The phase comparison signal (g) can be generated from an exclusive OR operation between the changing point detection signal (f) and the data sampling clock signal (d). In this case, a relationship between levels (H and L) of the phase comparison signal (g) and the phase shift (preceding and lagging) of the clock signal (b) is reversed. A description will now be given of a modification of the first embodiment of the present invention with reference to FIG.7. In the modification shown in FIG.7, the base-band delayed detector is provided with a PLL unit 4, formed of a analog circuit, substituted for the digital PLL unit 3 shown in FIG.5. In FIG.7, those parts which are the same as those shown in FIG.5 are given the same reference numbers. Referring to FIG.7, the phase comparison signal (g) output from the phase comparison result detection unit 2 of the BTR circuit 1' is supplied to an analog PLL unit 4. The analog PLL unit 4 has a charge pump 40, a loop filter 44, a voltage control oscillator (VCO) 41, a first divider 42 and a second divider 43. The BTR circuit 1' operates in the same manner as that shown in FIG.5. The phase comparison signal (g) is supplied, as a control voltage, from the phase comparison result detection unit 2 to the voltage control oscillator 31 via the charge pump 40 and the loop filter 44. A frequency of an output signal from the voltage control oscillator 43 is controlled in accordance with the phase comparison signal (g). Thus, a phase of the clock signal (b) output from the first divider 42 and a phase of the data sampling clock signal (b) output from the second divider 43 are controlled. When the changing point detection signal (f) has a high level (H), the charge pump 40 outputs a voltage level corresponding to the phase comparison signal (g). When the changing point detection signal (f) has a low level (L), the output of the charge pump 40 becomes a high impedance. A description will now be given of a second embodiment of the present invention with reference to FIG.8. A base-band delayed detector shown in FIG.8 is provided, for example, in a base station carrying out a mobile communication to a mobile station. In the base station, a symbol rate of a transmission signal from the base station is equal to that of a received signal. Thus, a clock signal having a frequency (fs) equal to the symbol rate of the received signal can be provided with the base station by itself. In FIG.8, those parts which are the same as those shown in FIG.5 are given the same reference numbers. Referring to FIG.8, a clock regenerative circuit 7 is connected to the phase comparison result detection unit 2. The clock regenerative circuit 7 has a multiplication circuit 71, a phase shifter 72, a divider 73 and a sequential filter 74. A clock signal, having a frequency (fs), generated by a device in which the base-band delayed detector itself is provided, is supplied to the multiplication circuit 71. The multiplication circuit 71 increases a frequency of the input signal, so that the clock signal (b) having a frequency (2fs) twice as large as that (fs) of the input signal. The phase shifter 72 shifts a phase of the clock signal output from the multiplication circuit 71 in accordance with the phase comparison signal (g) supplied from the phase comparison unit 2 to the phase shifter 72 via the sequential circuit 74. The clock signal whose phase is shifted by the phase shifter 72 is supplied to the divider 73, so that the data sampling clock signal (d) having a frequency (fs) is output from the divider 73. The base-band delayed detector shown in FIG.8 operates in the approximately same manner as that shown in FIG.5. In the above embodiments, a phase of the clock signal (b) is detected based on the output data I' from the I-channel of the operation circuit 59. However, a phase of the clock signal (b) can be detected based on the output data Q' from the Q-channel of the operation circuit 59. In addition, a phase comparison signal, which is a logical sum of a first phase comparison signal generated based on the data I' from the I-channel and a second phase comparison signal generated based on the data Q' from the Q-channel, can be used for controlling a phase of the clock signal (b). In this case, reliability of the base-band delayed detector can be further improved. Further, in the above embodiments, the clock signal (b) having a frequency (2fs) twice as large as the symbol rate of the base band signal to be processed in the operation circuit 59 is used as a time clock of the analog to digital converters 57 and 58, the operation circuit 59 and so on. However, a clock signal having a frequency (2n·fs) 2n times as large as the symbol rate can be used as the timing clock signal. The present invention is not limited to the aforementioned embodiments, and variations and modifications may be made without departing from the scope of the claimed invention. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: Bit timing recovery circuit for deriving a clock signal from an altered signal which has been digitally generated by an operation means from an input signal and which has a predetermined symbol rate, said clock signal being used as a timing signal in said operation means, the circuit comprising: clock generation means (31, 33) for generating said clock signal having a frequency 2n times as large as the symbol rate, wherein n is an integer number and synchronizing means (2, 32, 35) for synchronizing said clock signal with said altered signal based on whether a phase of said clock signal lags or precedes the phase of said altered signal, characterized in that the synchronizing means comprises: first generation means (25, 34) for generating a first clock signal based on said clock signal generated by said clock generation means (31, 33), said first clock signal having a frequency half that of said clock signal, second generation means (34) for generating a second clock signal based on said clock signal generated by said clock generating means (31, 33), said second clock signal having a frequency half that of said clock signal and being the logic inversion of said first clock signal, first sampling means (22) for obtaining a first polarity of said altered signal output from said operation means in synchronism with said first clock signal, second sampling means (21) for obtaining a second polarity of said altered signal output from said operation means in synchronism with said second clock signal, and determination means (2) determining whether a phase of said clock signal lags or precedes the phase of said altered signal based on a comparison between said first and second polarity respectively sampled by said first and second sampling means (21, 22). Bit timing recovery circuit according to claim 1, characterized in that the frequency of said clock signal generated by said clock generation means (31, 33) is twice as large as the symbol rate. Bit timing recovery circuit according to claim 1 or 2, characterized in that said synchronizing means further comprises a shifter means (32, 35) for adding to, or subtracting from said clock signal one or a plurality of pulses, based on the result of said determination means (2). Bit timing recovery circuit according to claim 3, characterized in that said shifter means (32, 35) comprises means (32) for shifting a phase of said clock signal generated by said clock generation means (31, 33) so that said first clock signal generated by said first generation means (25, 34) is synchronized with zero-cross points of an eye pattern of said altered signal. Bit timing recovery circuit according to one of the claims 1-4, characterized in that said input signal is a π/4 shifted QPSK signal, and wherein either an I-channel signal or a Q-channel signal of said operation means is used as said altered signal.

Inventors: ONODA MASAHIRO, TODA YOSHIFUMI, ONODA, MASAHIRO, TODA, YOSHIFUMI, Onoda, Masahiro, c/o Fujitsu Limited, Toda, Yoshifumi, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H04L7
IPC codes: H04L7, H04L27