Series ferroelectric capacitor structure for monolithic integrated circuits and method of fabrication

Abstract: A ferroelectric capacitor for a memory device including a substrate (10), a bottom electrode (20) and a top electrode (40). Between the bottom and the top electrodes is either an alternating plurality of layers (30a, 30b) of ferroelectric material and intermediate electrodes or a plurality of layers (30a, 30b, 30c) of ferroelectric material. A method for forming the same through establishing one layer over the other is also disclosed.

Description: The present invention is directed to a ferroelectric capacitor and a method for forming the same, as defined in the preambles of Claim 1 and Claim 6, respectively. A current method for producing ferroelectric capacitors for integrated ferroelectric memories involves depositing a single layer of a ferroelectric/dielectric material between a bottom electrode and a top electrode. See US-A-4 918 654 ("SRAM With Programmable Capacitance Divider") and US-A-5 005 102 ("Multilayer Electrodes For Integrated Circuit Capacitors") assigned to Ramtron Corporation. The result is a capacitor having a bottom electrode, a single layer of ferroelectric material, and a top electrode. A problem with this configuration is that if a defect is somehow introduced to either the bottom electrode or the ferroelectric layer, such as during the deposition process or during subsequent processing, the defect may propagate through the entire structure. A defect propagates as either the bottom electrode or ferroelectric layer is deposited or as the ferroelectric layer is annealed and undergoes a phase transformation. A defect can cause an electrical short between the top and bottom electrodes and thereby render the capacitor useless. Furthermore, the existence of such a defect in the capacitor can lead to instability in the electrical properties of the capacitor, for example in the breakdown voltage, leakage current, and dielectric constant. Hence, such a defect will cause the electrical properties of the capacitor to be degraded. A defect such as described above is a frequent occurrence in the capacitor production process. In fact, unwanted defects are typically the single largest yield limiter in the production process. As a result, manufacturing yield is decreased which affects the product manufacturing costs. Therefore, defects cause a great deal of wasted time, effort, and money for a manufacturer. In commercial integrated circuit memory devices, a large number of capacitors are fabricated and incorporated into each device. In order for the memory device to operate properly, each capacitor must possess good electrical characteristics. Therefore, a random defect, which degrades the electrical performance of one capacitor, will also degrade the electrical performance of the memory device and result in a defective memory device. Accordingly, the probability of making a good memory device is greatly dependent on the effect of these random defects. In order to prevent defects in a ferroelectric capacitor in Patent Abstracts of Japan, vol. 15, No. 165; and JP-A-3 034 580 there is suggested a capacitor structure of the kind defined in the preamble of Claim 1, in which a series of ferroelectric/dielectric and intermediate electrode layers are established sequentially between a bottom electrode and a top electrode. Such a structure thus comprises many electrode-dielectric interfaces which entail difficult manufacturing and process control issues. The object of the present invention is to provide an improved ferroelectric capacitor and method. This object is achieved according to the invention by the capacitor defined in Claim 1 and the method defined in Claim 6. In a capacitor according to the invention the total thickness of the dielectric layers will be equal to the thickness of the dielectric of a prior art single dielectric layer capacitor. Therefore, the capacitor of the present invention will have a similar size and similar electrical characteristics as said prior art capacitor. However, the capacitor of the present invention has two major advantages over the prior art devices. A random defect occurring in any one of the ferroelectric/dielectric layers is less likely to propagate throughout the entire capacitor structure. These defects usually occur during the depositing of a layer. Therefore, by alternately deposited the layers, i.e. electrode/dielectric/dielectric, etc., as in the present invention, defects are confined to a single dielectric layer. Accordingly, since the structure of the present invention comprises a plurality of dielectric layers, a randomly occurring defect in only one of the dielectric layers is less likely to cause a catastrophic failure of the device. As a result, a more robust capacitor with a lower probability of failing as a result of a random defect is achieved. The present invention is further directed to a method for fabricating the ferroelectric capacitor of the present invention. In general, the method comprises a sequence of deposition steps followed by annealing and defining the structure to form a ferroelectric capacitor having a series of ferroelectric/dielectric layers. Considering the method of the present invention in one of its embodiments, the top electrode of the capacitor is defined first, then the dielectric/ferroelectric layers, and finally the bottom electrode. In still a further embodiment of the invented method, the top electrode and the dielectric/ferroelectric layers are defined simultaneously so that they are coincident. The bottom electrode is then defined in a separate step. In another aspect, annealing is done after all the ferroelectric/dielectric layers are established. In another embodiment, annealing is done after each layer of ferroelectric/dielectric material is established. In describing the preferred embodiment, reference is made to the accompanying drawings wherein like parts have like reference numerals, and wherein: Fig. 1 is a cross-sectional view of a ferroelectric capacitor produced by a prior method; Fig. 2 is a cross-sectional view of a portion of a ferroelectric capacitor showing a bottom electrode over a substrate; Fig. 3 is a cross-sectional view of a portion of the first embodiment of the present invention showing ferroelectric material over the structure of Fig. 2; Fig. 4a is a cross-sectional view of a portion of a first embodiment of the present invention; Fig. 4b shows a cross-sectional view of the structure of Fig. 4a with layers of ferroelectric material over the bottom electrode; Fig. 4c shows structure of Fig. 4b with the addition of a top electrode; Fig. 4d shows a cross-sectional view of the completed structure of the first embodiment; Fig. 5a shows a cross-sectional view of a portion of the structure of a further embodiment of the present invention; Fig. 5b shows a cross-sectional view of the completed structure of said further embodiment of the present invention; Fig. 6 shows a plan view of the structure of the first, embodiment of the present invention after the top electrode has been established and defined but before the dielectric has been established; and Fig. 7 shows a plan view of the structure of said further embodiment of the present invention after the top electrode has been established and defined but before the dielectric has been established. Fig. 1 shows a cross-sectional view of the structure produced by a current method for fabricating ferroelectric capacitors for integrated ferroelectric memories. In this structure, a substrate 10 is provided. Over it is a bottom electrode or "plate" 20. A single layer of ferroelectric/dielectric material 30 is deposited between the bottom electrode 20 and a top electrode 40. As stated previously, a defect in the bottom electrode or the ferroelectric/dielectric layer can easily propagate throughout the structure, resulting in degraded electrical properties in the capacitor and severely limiting the electrical capability of any memory device the capacitor is incorporated within. The ferroelectric capacitor of the present invention is intended to decrease the probability of a random defect affecting the quality of the capacitor of a memory device in which the capacitor is incorporated. The present invention is illustrated by four embodiments. The four embodiments, illustrated in the drawings, are described below with reference to a method for fabricating each embodiment. Generally, in Fig. 2, a bottom layer or electrode 20 is established over a substrate 10. The substrate can be comprised of any basic material, such as silicon and silicon dioxide, germanium, gallium arsenide for example, as long as there is not a material mismatch between substrate 10 and bottom electrode 20. Substrate 10 can be fabricated by thermal oxidation or chemical vapor deposition (CVD), for example. The bottom electrode can be established, for example, by deposition or other commonly used techniques. For example, sputtering deposition or molecular beam epitaxy (MBE) may be used. Bottom electrode 20 preferably comprises platinum (Pt), palladium (Pd), or an alloy of these two materials, and it has a thickness in the range from 500 Å (50 nm) to 5,000 Å (500 nm). One of the embodiments of the present invention is then established over the bottom electrode structure. FIRST EMBODIMENT The method for fabricating the first embodiment of the present invention is shown in Figs. 3 and 4a-4d. In this method, a dielectric, such as a ferroelectric material 30a, is established over bottom electrode 20, as shown in Fig. 3. Ferroelectric material 30a can be established by a number of different methods. For example, the material can be deposited by sputtering, evaporation, or chemical vapor deposition (CVD), or a spin-on method such as sol-gel or metal-organic decomposition (MOD). The composition of the ferroelectric material is preferably a lead zirconate titanate composition having the chemical composition of Pb(Ti x Zr 1-x )O 3 , wherein x is in the range from 0.2 to 1.0. Further, the ferroelectric material can be doped with, for example, niobium (Nb) or lanthanum (La) in the range of 0.5% to 5.0%, atomic percentage. Thereafter, the process of establishing a layer of ferroelectric material is repeated until the desired number of layers is obtained. These layers can be established in a manner and with material similar to that used in layer 30a. Fig. 4a shows an example of this structure with one additional layer of ferroelectric material 30b. A further layer of ferroelectric material 30c is then established over the other ferroelectric layers 30a, 30b, as shown in Fig. 4b. Layer 30c can be established in a manner similar to that used for layer 30a. The entire structure is then annealed to form the proper ferroelectric phase. Annealing may be performed, for example, by a rapid thermal anneal (RTA) or by furnace annealing. The ambient used for the annealing is, for example oxygen, oxygen-argon, or oxygen-nitrogen mixtures at a temperature in the range of 500°C to 900°C. Preferably, a furnace anneal in 100% oxygen for 30 to 90 minutes is done. The anneal is performed to convert the deposited dielectric into a material with ferroelectric characteristics. A top electrode 40 is then established over layer 30c. The top electrode can be established, for example, by deposition using the same method and material as used in bottom electrode 20. Top electrode 40 is then defined. Electrode 40 may be defined by sputtering, for example. Preferably, the thickness of top electrode 40 is in the range from 500 Å (50 nm) to 5,000 Å (500 nm). The resulting structure is shown in Fig. 4c. The capacitor stack, comprising ferroelectric layers 30a, 30b, 30c, is then defined. The capacitor stack may, for example, be defined by sputtering or an anisotropic etch process. Bottom electrode 20 is then defined, for example by sputtering. Preferably, bottom electrode 20 is larger in at least one transverse direction than the capacitor stack. This relationship exists so that subsequent contact may be made from other circuits or elements to bottom electrode 20. Fig. 4c shows the resulting structure. In Fig. 4d, a dielectric material 50 is then established over the structure in order to passivate the edge of the capacitor stack. Dielectric material 50 can be, for example, silicon dioxide or silicon nitride. Dielectric material 50 can be established, for example, by deposition such as by CVD. Dielectric material 50 is used to minimize the leakage current of the capacitor. Contact windows 60, 70 are then defined through dielectric material 50 to top electrode 40 and bottom electrode 20, respectively. Contact window 60, 70 can be defined by conventional photopatterning and etching. Fig. 4d illustrates the completed structure of the first embodiment of the present invention, it being understood that contacts are to be added. SECOND EMBODIMENT The method for fabricating the second embodiment of the present invention includes all the steps in the method for fabricating the first embodiment. However, in the method for fabricating the second embodiment, we anneal after establishing each layer of ferroelectric material, instead of annealing the structure only after establishing the last layer of ferroelectric material (i.e. 30c in Fig. 4c), as in the first embodiment. Accordingly, the diffusion of active species, such as oxygen and lead oxide, in the second embodiment can occur from the top surface of each layer as it is annealed. This provides a much greater opportunity for diffusion than in the first embodiment wherein any diffusion must occur through the edges of the ferroelectric layers. Preferrably, each anneal is a furnace anneal at a temperature between 500°C to 800°C for 30 to 90 minutes. The preferred embodiment of the present invention is produced utilizing this method and comprises a capacitor stack having preferably two to four ferroelectric layers. THIRD EMBODIMENT The method for fabricating the third embodiment of the present invention involves the same steps as were described above, referring to Figs. 3 and 4a-4c, for the method for fabricating the first embodiment. For example, after ferroelectric layer 30c is established, the structure is annealed, and top electrode 40 is then established in a manner similar to that described above in the method for the first embodiment. However, unlike in the method for fabricating the first embodiment, in this method the top electrode is not defined at this point in time. Rather, top electrode 40 is defined later -- simultaneously with defining the capacitor stack. As a result, the capacitor structure and the top electrode are congruent (coincident) in plan view (See Fig. 7). Accordingly, one less definition step is necessary than in the method for fabricating the first embodiment. Therefore, the manufacturing cost for fabricating this embodiment is less than the cost for fabricating the first embodiment. Unfortunately, this embodiment has a disadvantage in that there is an increased sensitivity to leakage and breakdown at the edges which can cause a higher leakage current or lower breakdown voltage. After defining the edges of layers 30a, 30b, 30c, and 40, the bottom electrode 20 is then defined as described above in the method for fabricating the first embodiment. Electrode 20 is larger in plan view in at least one dimension then the stack above it (See Fig. 7). Fig. 5a shows the resulting structure. Next, dielectric material 50 is established and windows 60, 70 are defined in a manner similar to that described for the first embodiment. Fig. 5b shows the completed structure for the third embodiment of the present invention. FOURTH EMBODIMENT The method for fabricating this embodiment includes all the steps of the method for fabricating the third embodiment of the present invention (Figures 5a, 5b). However, as described in the method for fabricating the second embodiment, in the fabrication of this embodiment, we anneal not only after we establish the last (uppermost) ferroelectric layer but also after we establish each ferroelectric layer. As a result, the structure shown in Fig. 4b is formed but has the advantage in that there has been a greater opportunity for diffusion of active species than in the third embodiment. Accordingly, the capacitor of the fourth embodiment is more robust than the capacitor of the third embodiment. The method of fabrication according to the invention is advantageous because there are only two electrode-dielectric interfaces which entail more difficult manufacturing issues. Therefore, this method of fabrication has easier manufacturing and process control. Fig. 6 shows a plan view of the structure of the first and second embodiments after top electrode 40 has been established and defined but prior to the establishment of dielectric 50. Fig. 7 shows a plan view of the structure of the third and fourth embodiments after top electrode 40 has been established and defined but prior to the establishment of dielectric 50. Once the capacitor of the present invention has been fabricated, it can be incorporated into a memory device or an array of capacitors. This description has been offered for illustrative purposes only and is not intended to limit the invention of this application, which is defined in the claims below. The present invention is not dependent on any particular substrate material.

Claims: A ferroelectric capacitor comprising a substrate (10), a bottom electrode (20) over said substrate, a plurality of layers (30a, 30b, 30c) of ferroelectric material over said bottom electrode, each of said plurality of layers located directly over each other, and a top electrode (40) over said plurality of layers of ferroelectric material; characterised in that said plurality of layers (30a, 30b, 30c) of ferroelectric material are located directly one on top of the other. The capacitor of Claim 1 further characterised by said ferroelectric material being a lead zirconate titanate composition defined by the chemical composition Pb(Ti x Zr 1-x ) O 3 , wherein x is from 0.2 to 1.0. The capacitor of Claims 1 or 2 further characterised by said ferroelectric material further comprising a dopant. The capacitor of Claim 3 further characterised by said dopant being selected from the group comprising niobium and lanthanum and being in a range of 0.5% to 5.0% atomic percentage. The capacitor of Claims 1 to 4 further characterised by a dielectric material (50) being established over said capacitor and contact windows (60, 70) are defined to said top electrode (40) and said bottom electrode (20). A method for forming a ferroelectric capacitor comprising the steps of forming a substrate (10), establishing a bottom electrode (20) over said substrate, establishing a plurality of layers (30a, 30b, 30c) of ferroelectric material over said bottom electrode, and establishing a top electrode (40) over said layers of ferroelectric material; characterised in that said plurality of layers (30a, 30b, 30c) of ferroelectric material are established directly one on top of the other. The method of Claim 6 further characterised by first the top electrode (40) being defined, then the layers (30a, 30b, 30c) of ferroelectric material being defined, and then the bottom electrode (20) being defined so that at least one edge of the bottom electrode is unobstructed. The method of Claim 6 further characterised by the top electrode (40) and layers (30a, 30b, 30c) of ferroelectric material being defined at the same time so that the edges of each layer are coincident. The method of Claims 6 to 8 further characterized by the step of annealing after said plurality of layers (30a, 30b, 30c) of ferroelectric material have been established. The method of Claims 6 to 8 further characterized by the step of annealing after each layer of ferroelectric material is established.

Inventors: DAVENPORT THOMAS, DE SMITH CONSTANCE, LARSON WILLIAM, DAVENPORT, THOMAS, DE SMITH, CONSTANCE, LARSON, WILLIAM
Applicants: RAMTRON INT CORP, RAMTRON INTERNATIONAL CORPORATION
Application year: 1992
Main classification: H01L27
IPC codes: H01L21, H01G4, H01L27, H01G7