A graded bandgap single-crystal emitter heterojunction bipolar transistor

Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region (604), a base region (606) formed on the collector region, and a single-crystal emitter region (608) grown on the base region (606) by low temperature epitaxy. During the formation of the base region (606), a graded profile of 5-23% germanium is added to the base, as the distance to the collector region (604) decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region (608), a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

Description: The present invention relates to a heterojunction bipolar transistor, and more particularly to a bipolar transistor having a graded bandgap emitter region. Bipolar transistors are important components in, for example, logic circuits, communications systems, and microwave devices. A bipolar transistor is essentially a three terminal device having three regions, an emitter, base and collector region, wherein the emitter and collector regions are of one conductivity type and the base is of another. Since the advent of bipolar transistors, many attempts have been made to improve the performance of the transistor. Some of these attempts have focused on increasing the current gain by improving the injection efficiency of the minority carriers from the emitter to the base. In order to accomplish this, wide bandgap transistors have been fabricated wherein the bandgap of the emitter is wider than the bandgap of the base. The wide bandgap transistor has been described in many publications and patents, some of which include Herbert Kromer's "Theory of Wide Gap Emitter for Transistors" reported in The Proceedings of IRE, 1957, p. 1535; U.S. Patent No. 2,569,347; and U.S. Patent No. 4,716,445. In United States Patent No. 4,716,445 entitled "Heterojunction Bipolar Transistor Having A Base Region of Germanium", and assigned to NEC Corporation, a wide bandgap heterojunction bipolar transistor is described. The transistor includes a collector region of gallium arsenide, a base region of germanium and an emitter region having a semiconductor layer of mixed crystal of silicon and germanium. The mixed crystal semiconductor layer may have a uniform distribution of silicon in germanium or a graded distribution of silicon. If the graded distribution is provided, the content of silicon increases with distance from the interface between the base and emitter regions. The silicon is added to the emitter region in order to increase the bandgap of the emitter region so that it is larger than the base bandgap. With the above described structure of a wide bandgap transistor and the fact that germanium has a large electron mobility, performance of the transistor is enhanced. IEEE ELECTRON Device Letters, vol. EDL-8, no. 7, July 1987, pp. 303-305 (Chang et al.) describes a self-aligned heterojunction-bipolar-transistor process based on a simple dual-lift-off method. Transistor with emitter width down to 1.2 µm and base doping 1 x 10 20 /cm 3 have been fabricated. Extrapolated current gain cutoff frequency of 55 GHz and maximum frequency of oscillation of 105 GHz have been obtained. Current-mode-logic ring oscillators with propagation delays as low 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both milimeter-wave devices and large-scale integrated circuit fabrication. Patent Abstract of Japan, vol. 10, no. 251 (E-432), August 28, 1986, & JP-A-61 79 255 describes the manufacturing of a hetero-junction transistor. To form a collector electrode easily by a method wherein a semi-conductor film of a different kind is shaped between a collector layer and a connecting layer for the collector layer, only the collector layer and the connecting layer for the collector layer are etched selectively, only the collector layer is etched, and a collector connecting layer is formed. An N〈+〉 GaAs collector connecting layer N-Ga0.7a10.3As, an N-GaAs collector layer, a P〈+〉 GaAs base layer, an N-Ga0.7A10.3As emitter layer, an N-Ga1-xA1xAs layer while (x) is decreased gradually to 0 from 0.3, an N-GaAs base connecting layer and an N〈+〉 GaAs emitter connecting layer are superposed on semi-insulating GaAs. A mask is formed and the GaAs emitter connecting layer is shaped through etching, and Mg is implanted and activated to form a P-external base. According to the method, a collector electrode can be formed easily to a hetero-junction transistor, and characteristic distribution in a wafer is improved. In Patents Abstract of Japan, vol. 15, no. 265 (E-1086), July 5, 1991, & JP-A-3 88 335 a semiconductor device is described, to achieve a high speed and low power consumption by interposing a compound semiconductor thin film for wide energy band gap wherein the composition for widening an energy band gap continuously toward a base from and emitter becomes larger in a graded mode and which serves the role of an etching stopping layer between a compound-semiconductor emitter layer and a compound semiconductor base layer. A compound-seciconductor layer for wide energy band gap is provided between a compound-semiconductor emitter layer and a compound-semiconductor base layer. In said semiconductor layer, the composition for widening an energy band gap continuously toward the bse from the emitter becomes larger in a graded mode. The semiconductor layer serves the rold of an etching stopping layer. For example, the constituent material of the emitter layer E is n-type GaAs. An n-type AlGaAs graded layer G having the thickness of, e.g. about 60 nm (about 600 Angstrom), is an inverted graded layer. Therefore, the emitter layer can undergo selective mesa etching, and a heterojunction bipolar transistor having the constitution that can perform high speed operation is obtained. The transistors mentioned in the above three documents have a graded emitter layer having a bandgap decreasing towards the emitter contact, i.e., decreasing as the distance from the base region increases. Many attempts in improving transistor performance have focused on, for example, decreasing the width of the base region of a transistor and decreasing the base transit time for a constant base width. In one example, in order to decrease both the base width and the base transit time, a bipolar transistor having a graded silicon/-germanium base is fabricated. The silicon/germanium base is epitaxially grown on an N-type collector, which is formed on a silicon substrate. Subsequently, the emitter region is formed on the base. In order to form the emitter, a window is opened and polysilicon is deposited. The polysilicon is heavily doped with an N-type dopant, such as arsenic. For example, the arsenic is implanted in the polysilicon and then a high temperature anneal cycle (e.g. 850°C for 15 minutes) is used to diffuse the arsenic through the polysilicon, the polysilicon/silicon interface of the emitter and into the base. This process enables bases of approximately 60 nm (600 Angstroms) to be formed. However, the above-described process places a limitation on how thin the bases can be fabricated. This limitation is due to the fact that the high temperature anneal cycle causes the P-type dopant, e.g. boron, in the base to diffuse thereby causing the base width to increase. Therefore, there is a limitation as to how thin the bases can be fabricated when the emitter is formed and contacted by polysilicon. In order to fabricate transistors with thinner bases, it has been suggested to eliminate polysilicon emitter contacts and to use single-crystal emitters contacted by metal. A problem associated with single- crystal emitters, however, is that in order to obtain a reasonable current gain, the single-crystal emitter must have an emitter thickness greater than 30 nm (for instance, 200 nm) and, therefore, the emitter charge storage is very large causing the device to be slow. IEEE Electron Device Letters, Vol 10, No. 12, December 1989, pp. 534 - 536 (Patton et al.) describes the formation of Si/Si 1-x Ge x heterojunction bipolar transistors (HBT's) using a low-temperature epitaxial technique to form the SiGe graded-bandgap base layer. These devices were fabricated on patterned substrates and subjected to annealing cycles used in advanced bipolar processing. Excellent junction quality is demonstrated for these devices, which have base widths under 75 nm. Due to the small bandgab of SiGe, the collector current at low bias is ten times higher than that for Si-base devices that have the same pinched base resistance. This collector current ratio increases to more than 40 at LN 2 temperature, resulting in current gains of 1600 for the SiGe-base transistors despite base sheet resistances as low as 7,5 kΩ/□. Accordingly, a need exists for a transistor having a single-crystal emitter with reduced charge storage. In addition, there still exists a need to increase device performance. Further, a need still exists to reduce the width of a base region in the device. The shortcomings of the prior art are overcome and additional advantages are provided in accordance with claims 1 and 5 of the present invention through the provision of a heterojunction bipolar transistor having a graded emitter bandgap. In accordance with the principles of the present invention, a heterojunction transistor having a first region of a first conductivity type, a second region of a second conductivity type formed on the first region and a third region of the first conductivity type formed on the second region is provided. The third region has a bandgap which decreases as the distance from the second region increases. In one embodiment, a heterojunction bipolar transistor including a first region of a first conductivity type, a second region of a second conductivity type formed on the first region and a third region of the first conductivity type formed on the second region is provided. The third region has a contact and the second region and third region define a junction. The second and third regions have a first and second bandgap, respectively, wherein the second bandgap is narrower at the contact than the first bandgap at the junction. In yet another aspect of the invention, a method for reducing charge storage in the emitter region of a bipolar transistor is provided. This method includes the step of grading the bandgap of the emitter region such that the bandgap decreases as the distance to the emitter contact decreases. In one particular embodiment, the grading of the emitter bandgap is accomplished by adding an increasing amount of germanium to the emitter region. The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The invention, however, may best be understood by reference to the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 represents one example of a graded germanium composition of the emitter profile, in accordance with the principles of the present invention; FIG. 2 illustrates one example of a graded germanium composition of the emitter profile and a graded germanium composition of the base profile, in accordance with the principles of the present invention; FIG. 3 depicts a graph showing emitter charge storage time and maximum cut-off frequency versus maximum germanium content in the 200 nm thick emitter region of a simulation run of the present invention for a transistor with a fixed current gain of 80; FIG. 4 is a band diagram for a transistor having the emitter bandgap profile and the base bandgap profile in accordance with the principles of the present invention; FIG. 5 is a bandgap versus position diagram for a transistor having graded silicon germanium emitter and base bandgap profiles in accordance with the present invention; FIG. 6 is a cross-sectional view of an example of a transistor which may be structured according to the present invention; and FIG. 7 is a cross-sectional view of another example of a transistor which may be structured according to the present invention. The fabrication of a heterojunction bipolar transistor having a single-crystal emitter is desirous, since a thinner base may be fabricated with such a design, thereby improving the cut-off frequency performance of the transistor. However, one disadvantage of the single-crystal emitter is that the thinner the emitter, the higher the base current and the lower the current gain. Thus, if, for example, an emitter is approximately 30 nm or less, the base current is very large and the current gain is unacceptably low. (As is known, current gain = collector current ÷ base current. A preferable current gain is approximately 100). Therefore, in order to decrease the base current, a thick single-crystal emitter is formed, e.g. 200 nm. A thicker emitter leads to another problem, however, and that is increased emitter charge storage. As the charge storage increases, the cut-off frequency (f τ ) decreases and, device performance is degraded. Thus, it is important to decrease the emitter charge storage in a single-crystal emitter. In accordance with the principles of the present invention, the emitter charge storage is decreased by grading the bandgap of the single-crystal emitter. Referring to FIG. 1, a schematic representation of a bipolar transistor 100 is illustrated. As is shown, the transistor includes an emitter contact 102, a single-crystal emitter region 104, a base region 106, and a collector region 108. (Each of these regions is known in the art. In addition, it is known in the art that there are quasi-neutral regions within the emitter and base region (not shown) and that there is virtually no electrostatic electric field in the quasi-neutral regions). In a preferred embodiment, emitter contact 102 is, for example, metal and emitter region 104 is approximately 200 nm thick and would be fabricated of a silicon/germanium alloy. In particular, in accordance with the principles of the present invention, the bandgap of the quasi-neutral region of the emitter is graded using as one example, a germanium profile 110 illustrated in FIG. 1. In one example, the germanium profile starts at approximately 0% and increases to 20% as the distance from the base region increases. This bandgap grading results in a quasi- electric field which drives the minority carriers towards the emitter contact thereby decreasing emitter charge storage. However, when the germanium is added to the emitter region, the base current increases and thus, the current gain decreases to significantly below 80, thereby degrading device performance. In order to restore the current gain to an acceptable level (e.g. 80), germanium is also added to base region 106. In a preferred embodiment, the base is approximately 25 nm and a graded profile of germanium 200 (FIG. 2) is added to the base. As illustrated in FIG. 2, in one example, the germanium profile in the base starts at approximately 5% and increases to 23% as the distance to the collector region decreases. The grading in the base advantageously increases the collector current at a given emitter-base voltage which increases the current gain. Thus, the grading profiles associated with the quasi-neutral region of the emitter and the base enable the current gain to remain at, for instance, approximately 80. In addition, by introducing a graded germanium profile in the emitter from 0-20% and a graded germanium profile in the base from 5-23%, simulations have shown, as depicted in FIG. 3, that the cut-off frequency is approximately 116 GHz, and the emitter charge storage time (τe) is approximately 0.23 psec. This is an increase in the cut-off frequency by a factor of 1.55 from the 75 GHz frequency achieved with no germanium in the emitter and a 0-15% germanium graded base and the relative contribution of the emitter charge storage time to the cut-off frequency drops from 40% to 16% (note that in this simulation, the emitter was doped with arsenic at 1 x 10 19 cm -3 and the base was 25 nm (250 Angstroms) with an intrinsic base sheet resistance of 10kΩ/square). Furthermore, as depicted in the band diagram of FIG. 4, as a result of placing a graded profile of germanium in the quasi-neutral region of the emitter, an emitter bandgap 402 decreases as the distance from an emitter-base junction 404 increases and the distance to the emitter contact 102 decreases. (As is known, Ec represents the conductance band and Ev represents the valence band.) In one example, the emitter bandgap is decreased by a value of 0.15 eV (electron volts), which is reflected in FIG. 4 as ΔE gE . This narrowing of the bandgap creates a quasi-electric field which sweeps the carriers towards the metal emitter contact 102, thereby reducing charge storage in the emitter. With this design, the minority carriers are forced out of the emitter. Furthermore, this bandgap narrowing possibly leads to a reduction in resistance of the metal contact, thus leading to lower emitter resistance. In addition, by grading the base as described above, a base bandgap 406 decreases as the distance from emitter-base junction 404 increases and the distance to the base-collector junction (not shown) decreases. In one example, the base bandgap is decreased by a value 0.17eV, which is reflected as ΔE gB . In accordance with the principles of the present invention, the bandgap of the emitter is narrower at the emitter contact than the bandgap of the base at the emitter-base junction 404. In one example, as depicted in FIG. 5, the emitter bandgap equals 0.95eV at emitter contact 102, while the base bandgap at emitter-base junction 404 is 1.06eV. As described previously, the narrowing of the emitter bandgap is achieved, in accordance with the principles of the present invention, by grading the emitter bandgap with germanium. Some emitter bandgap narrowing caused by the grading of the dopant profile of the emitter may also occur. (A reduction in bandgap with germanium incorporation in the silicon crystal is more effective however, and thus, preferred). This is accomplished by increasing the dopant concentration in the emitter as the distance to the emitter contact decreases. By using dopant grading in conjunction with bandgap grading, bandgap grading may be enhanced, especially when a high concentration of dopant is used. One example of a device which could be structured in accordance with the principles of the present invention is depicted in FIG. 6. Referring to FIG. 6, on a silicon substrate 600 of P-type conductivity, an N+ silicon layer 602 is formed with a thickness of 1000 nm and is heavily doped with arsenic. On layer 602, an N-silicon layer 604 with a thickness of 400 nm and a 1x10 16 cm -3 impurity concentration of arsenic is formed by epitaxy. The N+ silicon layer 602 and N-silicon layer 604 form the collector region 108 (FIG. 1). Once layer 604 is formed, deep trench isolation (not shown) between the devices is formed. Subsequently, a base region of P silicon/germanium layer 606 is formed by low temperature epitaxy such as MBE (Molecular Beam Epitaxy) or UHV/CVD (Ultra-High Vacuum/Chemical Vapor Deposition). The base has a final thickness of 25 nm and a boron impurity concentration of typically 1x10 19 cm -3 . In accordance with the principles of the present invention, in a preferred embodiment, as the base is grown, an increasing amount of germanium is added to the silicon at selective points in the base. As one example, a grading profile of 5%-23% of germanium is added to the base wherein the amount of germanium increases as the distance to the collector region decreases. After the base is epitaxially grown, the emitter region is grown by defining an emitter window by known methods and then using low-temperature epitaxy to deposit an N+ silicon/germanium layer 608 having a thickness of 200 nm and an arsenic impurity concentration of 1x10 19 cm -3 . A material 610 is an insulator such as oxide, nitride, or composite stack. Also, in accordance with the principles of the present invention, as the emitter region is formed, an increasing amount of germanium is added to the emitter. As one example, a grading profile of 0-20% of germanium is added to the emitter wherein the amount of germanium increases as the distance to the emitter contact decreases and the distance from the emitter-base junction increases. As previously described, by grading the base and emitter bandgaps in accordance with the principles of the present invention, device performance is significantly enhanced. While the structure of an N-P-N transistor is described herein, the invention is also applicable to P-N-P transistors. Very heavily doped emitters of silicon germanium P-N-P transistors can be grown by low-temperature temperature epitaxy and the presence of germanium in the emitters counteracts the strain associated with the large concentration of boron atoms. Another example of a device structured in accordance with the principles of the present invention is depicted in FIG. 7. Referring to FIG. 7, on a P-type silicon substrate 700, a heavily doped (with e.g. arsenic) N+ silicon layer 702 having a thickness of typically 1000 nm is formed. On layer 702, an N-silicon layer 704 with a thickness of 400 nm and a 1x10 16 cm -3 impurity concentration of arsenic is formed by epitaxy. Subsequently, a P-type base region of a silicon/germanium layer 706 is formed by low- temperature epitaxy. The base has a thickness of 25 nm and a boron impurity concentration of 1x10 19 cm -3 . In accordance with the principles of the present invention, in a preferred embodiment, as the base is grown, an increasing amount of germanium is added to the silicon at selective points in the base. As one example, a grading profile of 5%-23% of germanium is added to the base wherein the amount of germanium increases as the distance to the collector region decreases. After the base is epitaxially grown, a single-crystal emitter having an N+ silicon/germanium alloy layer 707 having a thickness of 100-200 nm and an impurity concentration of 5x10 18 -1x10 19 cm -3 is formed thereon by low-temperature epitaxy. The electrical emitter dimensions are defined by an extrinsic P+ base 708 which is formed on either side of an emitter contact window 710. Thereafter, a contact window 710 is opened on top of emitter 707. The insulated layers 714 isolate the emitter contact from the extrinsic base. Also, in accordance with the principles of the present invention, as the emitter region is formed, an increasing amount of germanium is added to the emitter. As one example, a grading profile of 0-20% of germanium is added to the emitter wherein the amount of germanium increases as the distance to the emitter contact decreases and the distance from the emitter-base junction increases. Once again, while an N-P-N silicon/germanium transistor is described, the invention is not limited to such a structure but can also be used with P-N-P silicon/germanium transistors and transistors of other materials. As described previously, grading the emitter bandgap reduces current gain. Therefore, this grading profile may be used whenever the current gain needs to be decreased. For instance, as is known, if the current gain is too high (e.g. significantly greater than 100), then the breakdown voltage BVceo may decrease to unacceptable levels. Thus, the emitter bandgap grading profile of the present invention may be used to reduce the current gain and establish an acceptable level for the breakdown voltage BVceo.

Claims: A heterojunction bipolar transistor (100) comprising: a collector region (108) of N-type; a base region (106) of P-type formed on said collector region; a single crystal emitter region (104) of N-type made of a silicon-germanium alloy formed on said base region, said single crystal emitter region having a bandgap wich decreases as the distance from the emitter-base junction (404) increases, said bandgap being narrower at all points within said emitter region than at said emitter-base junction junction; The heterojunction bipolar transistor of claim 1, wherein said base region has a bandgap, said emitter region has a contact formed thereon and the bandgap of said emitter region being narrower at said contact than said bandgap of said base region at said junction. The heterojunction transistor of claim 2 wherein said bandgap of said base region is graded. The heterojunction transistor of any of the claims 1 to 3, wherein said emitter region has a thickness greater than 30 nm. A method of fabricating a heterojunction bipolar transistor (100) according to any of the claims 1 to 4 having a single-crystal emitter region (104) including an emitter contact (102), a base region (106), and a collector region (108), comprising the step of grading a bandgap in said emitter region wherein said emitter region is made of a silicon-germanium alloy and said grading step includes adding an increasing amount of germanium to said emitter region as the distance from said base region increases whereby said bandgap in said emitter region decreases as the distance from the emitter-base junction (404) increases, whereby charge storage in said emitter region is reduced, said bandgap being narrower at all points within said emitter region than at said emitter-base junction (404). The method of claim 5 wherein the amount of said germanium increases from 0% to 20%. The method of any of the claims 5 to 6 wherein said base region is made of a silicon-germanium alloy having an increasing amount of germanium added as the distance to said collector region decreases whereby said bandgap of said base region decreases as the distance to said collector region decreases. The method of claim 7, wherein the amount of said germanium increases from 5% germanium to 23% germanium.

Inventors: CRABBE EMMANUEL F, HARAME DAVID L, MEYERSON BERNARD S, PATTON GARY, STORK JOHANNES M C, CRABBE, EMMANUEL F., HARAME, DAVID L., MEYERSON, BERNARD S., PATTON, GARY, STORK, JOHANNES M.C.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES
Application year: 1992
Main classification: H01L29
IPC codes: H01L29, H01L21