Insulating film manufacturing method for a semiconductor device

Abstract: In forming an insulating film inside the contact hole or via contact hole of a semiconductor device, to fill an insulator into a contact hole without creating air holes, thereby forming an insulating film with a flat surface. An insulating film formation solution such as SOG, having the prescribed concentration of solid constituents, is applied and hardened a number of times to form an insulating film. The concentration of solid components in the SOG solution should be in the range of 9.5-12 wt%, and when the SOG solution is applied to a flat substrate in a single layer, the thickness of the SOG insulating film should be in the range of 2000-4000 Å.

Description: Field of the Invention The present invention pertains to a method for manufacturing a semiconductor device, and pertains in particular to a method by which an insulator is filled into the contact holes or via contact holes inside a semiconductor device. Prior Art Conventionally, the procedures shown in Figure 5 (a) and (b) are used to flatten interlayer insulating films in order to form multilayer wiring such as TLM (triple level metal). In Figure 5 (a), a contact hole (21) is connected to a diffusion layer (2) formed on a semiconductor substrate (1), and aluminum (Al) wiring (3) is formed on top of an SiO 2 film (9), etc., which is formed on top of the semiconductor substrate (1). This Al film (3) is also formed (adhered) to the inner walls of the contact hole (21) to be electrically connected to the diffusion layer (2) via the contact hole (21). Once the desired patterning has been formed, the top of the Al wiring (3) is coated with a vapor phase growth insulating film (4), on top of which a resistor film (5) is then formed. Next, as shown in Figure 5 (b), flattening (resistor etching) is carried out by an etching method such that the resistor film (5) and vapor phase growth insulating film (4) will have the same etching rate. A number of layers may be formed on top of the etched vapor phase growth insulating film (4). For the via contact holes used for making interlayer connections in this case, the procedures of Al wiring formation, vapor phase growth insulating film formation, resistor film formation, and resistor etching are carried out in the same manner as for the contact hole. When the vapor phase growth insulating film (4) is formed on the contact hole (21) as shown in Figures 5 (a) and (b), air holes (7) will often form, thus lowering reliability. In particular, if the diameter of the contact hole (21) is less than 1.2 µm, then the air holes (7) will be exposed when resistor etching is carried out, thus creating empty spots (depressions), which are problematic. In order to solve this problem, there have been attempts to use methods in which spion [sic; spin-on] glass (SOG), an insulating film formation solution containing SiO 2 , is utilized. GB-A-2 191 338 discloses a planarization process for a double metal VLSI technology. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface. A further example of this will be described with reference to Figure 6 (a) and (b) . The numbers (1, 2, 3, 4, 7, and 9) refer to the same items as those shown in Figure 5 (a) and (b). Figure 6 (a) shows an example in which SOG with a high concentration of SiO 2 solid components is applied on top of the vapor phase growth insulating film (4) to form an SOG applied insulating film (6a). In addition, Figure 6 (b) shows an example in which SOG with a low concentration of SiO 2 solid components is applied to the vapor phase growth insulating film (4) to form an SOG applied insulating film (6b). Problems for the Invention to Solve Due to the high concentration of SiO 2 solid components, the formation of an insulating film using the SOG applied insulating film (6a) shown in Figure 6 (a) often results in the formation of air holes (7), as when the insulating film is formed inside the contact hole (21) using the vapor phase growth insulating film (4) shown in Figure 5 (a). When the insulating film is formed using the SOG application insulating film (6b) shown in Figure 6 (b), although the SOG fills the gaps in the vapor phase growth insulating film (4) on the inner walls of the contact hole (21), since the concentration of SiO 2 solid components is low, empty spaces (depressions) (8) are formed on top of the contact hole (21). The formation of air holes (7) shown in Figure 6 (a), and the formation of depressions (8) shown in Figure 6 (b) are problematic in causing cracks and line breaks in the subsequent procedures. The example described above was related to contact holes, but the same type of problems occur when the insulating film is formed with a via contact hole formed on the upper layer. Thus, the present invention has the objective of forming a flat insulating film with small depressions on the contact hole or via contact hole, without creating air holes in the insulating film area on the contact hole or via contact hole. Means for Solving the Problems In order to solve the aforementioned problems, with the present invention, an insulating film formation solution having the desired concentration of solid components, such as an SOG solution, is applied and hardened a number of times, thereby filling the contact hole area or via contact hole area of the semiconductor device with the insulator, without creating air holes inside the contact hole or via contact hole. The insulating film formation solution on the lower layer is semi-hardened after being applied so that the insulation on the lower level will not be affected by the following insulation solution, which is used to form the upper level. Specifically, the present invention offers a method of making a semiconductor device as defined in claim 1. Embodiments Figure 1 shows a cross section of the first application example of the present invention, in which an SOG insulating film is formed on the contact hole area. Figure 2 shows an enlarged view of the contact hole area. The contact hole (21), which is connected to the diffusion layer (2) formed inside the semiconductor substrate (1), is formed through an SiO 2 film (9). The Al wiring (3) is formed and adhered to the upper surface of the SiO 2 film (9) and the inner walls of the contact hole (21). After the desired patterning has been carried out, the vapor phase growth insulating film (4) is formed. In the present application example, the inner diameter Dc of the contact hole (21) is set to 1.7 µm (17000 Å); and the depth Hc of the contact hole (21) is set to 1.2 µm (12000 Å). The air hole diameter D4 of the vapor phase growth insulating film (4) inside the contact holes (21) is 0.5 µm (5000 Å); and the depth H4 of the vapor phase growth insulating film (4) from the top of the Al wiring (3) to the bottom of the contact hole (21) is 2.1 µm (21000 Å). The thickness H3 of the Al wiring (3) is 0.8 µm (8000 Å). Under the aforementioned conditions, the lower SOG applied film (10) is first formed, after which the upper SOG applied film (11) is formed, thereby filling the empty space in the contact hole (21) through the top of the vapor phase growth insulating film (4). (1-1) Application of lower SOG applied film (10) a) In a static state, 9.5 wt% of the SOG solution is applied through the top of the vapor phase growth insulating film (4). b) Rotation is carried out for approximately one second at a low speed, such as 700 RPMs. c) Rotation is carried out for approximately 30 seconds at a high speed, such as 4000 RPMs. (1-2) First baking procedure a) Bake for two minutes on a hot plate at 100°C. b) Bake for two minutes on a hot plate at 180°C. c) Bake for two minutes on a hot plate at 260°C. (1-3) Cooling Cool for two minutes on a cooling plate at a normal temperature, such as 23°C. The lower SOG applied film (10) is thus hardened (thermally hardened). This hardening process is carried out in order to prevent the lower SOG applied film (11) [sic (10)], already formed, from being affected during the following procedure, in which the upper SOG applied film (11) is formed. The process for hardening the SOG solution by baking can be expressed in the following chemical formula. "R" denotes an alkyl group in the chemical formula. (Chemical formula 1) [see page 15] (2-1) Application of upper SOG applied film (11) a) In the still state, 12 wt% of the SOG solution is applied through the vapor phase growth insulating film (4). b) Rotation at low speed in the same manner as in (1-1) step b described above. c) Rotation at high speed in the same manner as in (1-1) step c described above. (2-2) Second baking procedure The baking procedure is the same as in steps a-c in (1-2) described above. (3) Main hardening procedure Heat at 250°C for 30 minutes, then at 400°C for 60 minutes, in a low pressure nitrogen atmosphere. As shown in Figures 1 and 2, with the aforementioned procedures, after the Al wiring (3) and vapor phase growth insulating film (4) are adhered to the inner walls of the contact hole (21), the diameter is D4 = 0.5 µm and depth is H4 = 2.1 µm. However, the lower SOG applied film (10) is properly filled into the space of the contact hole (21) without creating air holes, and the upper SOG applied film (11), which is formed on top of the lower SOG applied film (10), is formed to be almost completely flat on the upper surface of the vapor phase growth insulating film (4). Although there is a slight depression (empty space), the depth d is in the range of 1-0.3 µm. As described above, when the lower SOG applied film (10) and the upper SOG applied film (11) are formed together in two layers, in order to prevent the occurrence of air holes, it is best that the concentration of solid components in the SOG solution of the lower layer SOG applied film (10) be set to 9.5 wt%, which is lower than the 12 wt% concentration of solid components in the SOG solution of the upper layer SOG applied film (11), in the aforementioned manner. In addition, experiments have confirmed that it is possible to obtain the same effects as those described above, even if the lower SOG applied film (10) and upper SOG applied film (11) are set to have the same SOG concentration, without changing the SOG concentrations of the lower level and upper level in the manner of the aforementioned application example. According to the experiments, the concentration of solid components in the SOG solution should be set in the range of 9.5 wt% to 12 wt%, and when the SOG solutions form a single film on a flat substrate, the thickness of the SOG insulating film should be in the range of 200-400 nm (2000-4000 Å). Table I on page 14 shows the experimental data obtained under a variety of conditions when the lower layer SOG applied film (10) and upper layer SOG applied film (11) were set to have the same SOG solution concentration. (Table I) The depth, height, and inner diameter units in Table I are in µm. In addition, Figure 3 shows a features graph which illustrates the relation between the thickness of the upper SOG applied film (11) and the degree of flatness P on the surface of the upper SOG applied film (11). The horizontal axis represents the thickness of the SOG film, and the vertical axis represents the degree of flatness P. In addition, the degree of flatness P is defined by the following equation. P = (1 - d/1 . 2) x 100 (%) d is the depth of the depression in the upper SOG applied film (11). In terms of manufacturing efficiency for the semiconductor device, the SOG insulating film formation procedure should be short, i.e., the number of formations should be small. Thus, it is preferable to form the lower SOG applied film (10) and upper SOG applied film (11) in two layers, as in the aforementioned application example. However, with the present invention, it is possible to obtain the same effects as those described above even if the SOG insulating films are formed in three or more layers. In such cases, the SOG solution should have a concentration in the range of 9.5 wt% to 12 wt%, and when the SOG solutions are applied to a flat substrate to form a single film, the thickness of the SOG insulating film should be in the range of 200-400 nm (2000-4000 Å), as described above. Figure 4 shows a cross section in which the semiconductor device shown in Figure 1 is formed in a greater number of layers. In Figure 4, the following are sequentially laminated onto the upper surface of the upper SOG applied film (11) shown in Figure 1: a second vapor phase growth insulating film (14) layer, second Al wiring (15) layer, third vapor phase growth insulating film (18) layer, and fourth vapor phase growth insulating film (19) layer. In addition to the contact hole (21), a via contact hole (22), which electrically connects the first Al wiring (3) layer with the second Al wiring (15) layer, and a via contact hole (23), which electrically connects the Al wiring (15) with the Al wiring (20), are formed. The Al wiring (15) and third vapor phase growth insulating film (18) are adhered to the inner walls of the via contact hole (22), while a second lower layer (No. 2-1) SOG applied film (16), and then a second upper (No. 2-2) SOG applied film (17), are formed in the empty space. The No. 2-1 SOG applied film (16) formation method and SOG solution solid component concentration are the same as in the lower SOG applied film (10), and the No. 2-2 SOG applied film (17) formation method and SOG solution concentration are the same as in the upper SOG applied film (11). In the same manner as the case described for Figure 1, it is possible to form not only a two layer structure, as with the No. 2-1 SOG applied film (16) and No. 2-2 SOG applied film (17), but also multiple layers consisting of three or more layers. In addition, with the via contact hole (23), it is also possible to adhere a vapor phase growth insulating film (not shown) on top of the Al wiring (20), after which SOG films which are the same as the No. 2-1 SOG applied film (16) and No. 2-2 SOG applied film (17) are formed. In Figure 4, it is possible to form the SOG insulation films in the same manner even if more layers are formed on top. The present invention is not limited to the aforementioned examples, but may also be applied in a variety of altered forms and in a variety of situations. For example, although the aforementioned application example was described in Figure 1 for a case in which the contact hole (21) is connected to the diffusion layer (2), it is not restricted to the diffusion layer (2), but may be connected to the desired conductive layer. The case is the same with regards to using conductive interlayers other than the Al wiring (3) for connecting the via contact hole (22) of Figure 4. In addition, the various data described above, such as the inner diameter and depth of the contact hole (21) are only examples. The present invention may be applied in the same manner to other cases, and the same results will be obtained. The aforementioned application example was described for a case in which an SOG solution was used as the insulating film formation solution. However, in forming the insulating film of the present invention, it is possible to form the same type of insulating film using other insulating film formation solutions, such as polyimides. Effects of the Invention As described above, with the present invention, insulating solutions with the prescribed concentrations of solid components are used in the contact hole area or via contact hole area, in forming an insulating film having at least two layers, such that when the solution is applied to a flat surface in a single layer, the prescribed insulating film thickness will be obtained. Thus, it is possible to form an insulating film with proper flatness in the contact hole area or via contact hole area without generating air holes in the holes, thereby making it possible to improve the production quality and yield for semiconductor devices. Brief Explanation of the Figures (Figure 1) A partial cross section of the first application example of a semiconductor device which illustrates the insulating film formation method of the present invention. (Figure 2) A partially enlarged view of Figure 1. (Figure 3) A graph of experimental results based on the application examples of the present invention. (Figure 4) A partial cross section of another application example of a semiconductor device which illustrates the insulating film formation method of the present invention. (Figure 5) A partial cross section of a semiconductor device which illustrates the insulating film formation method used in a conventional semiconductor device. (Figure 6) A partial cross section of a semiconductor device which illustrates another insulating film formation method used in a conventional semiconductor device. Explanation of the Numbers 1. Semiconductor substrate 2. Diffusion layer 3. Al wiring 4. Vapor phase growth insulating film 9. SiO 2 film 10. lower SOG applied film 11. upper SOG applied film 14. Second vapor phase growth insulating film 15. Al wiring 16. No. 2-1 SOG applied film 17. No. 2-2 SOG applied film 18 Third vapor phase growth insulating film 19. Fourth vapor phase growth insulating film 20. Al wiring 21. Contact hole 22, 23. Via contact holes SOG Solution Concentration 12 wt% 9.5 wt% Contact Hole Diameter Dc 1.6 - 1.8 1.28 - 1.8 Contact Hole Depth Hc 0.9 - 1.2 0.8 - 1.3 Inner Diameter D4 with Insulating Film (4) Adhering 0.45 - 0.8 0.15 - 0.7 Insulating Film (4) Depth H4 1.7 - 2.1 1.4 - 2.2 Depression Depth d 0.1 - 0.3 0.15 - 0.35

Claims: A method of making a semiconductor device having a contact hole (21) extending through an insulation layer (9) to expose an electrically conductive element (2) and a patterned layer of electrically conductive material disposed on said insulation layer (9) and within the contact hole (21) to define an electrical contact member (3) covering the bottom and side walls of the contact hole (21) and in engagement with said electrically conductive element (2), wherein the contact hole (21) is only partially filled by said electrical contact member (3), the steps comprising: forming a second insulation layer (4) by vapor phase growth over the exposed portions of said first insulation layer (9) and said patterned electrical contact member (3) so as to provide a coating of said second insulation layer (4) thereover, applying a first insulating film formation solution onto the second insulation layer (4) by spinning on the first insulating film formation solution, and hardening the first insulation film formation solution to provide a first insulating film (10) partially filling the remainder of the unoccupied portion of the contact hole (21) within said second insulation layer (4); characterized by said first insulating film formation solution having a first solids concentration selected to be low enough that the contact hole (21) is only partially filled by the first insulating film, such that no voids (7) are entrapped therein, and by subsequently applying a second insulating film formation solution onto the first insulating film (10) by spinning on the second insulating film formation solution to fill the remainder of the unoccupied portion of the contact hole (21) with a second insulating film (11), said second insulating film formation solution having a second solids concentration selected to be low enough that the contact hole (21) is filled with the second insulating film (11) with no voids (7) entrapped therein but high enough that no depression (8) will occur in the second insulating film (11) over the contact hole (21); hardening the second insulating film formation solution to provide the second insulating film (11) covering said first insulating film (10) and defining a substantially flat surface spanning the contact hole (21); and further hardening the first and second insulating films (10, 11) by heating the semiconductor device. A method as set forth in claim 1, further characterized in that first insulating film formation solution and the second insulating film formation solution are hardened by baking. A method as set forth in any of claims 1-2, further characterized in that said first insulating film formation solution is a 9.5 wt. % spin-on glass solution, and said second insulating film formation solution is a 12 wt. % spin-on glass solution. A method as set forth in any of claims 1-3, further characterized by applying the first insulating film formation solution onto the second insulation layer (4) by successive spinning steps including spinning said first insulating film formation solution at a relatively low speed of rotation during a first spinning stage onto the second insulation layer (4) and thereafter further spinning said first insulating film formation solution at a relatively high speed of rotation during a second spinning stage onto the second insulation layer (4), hardening the first insulating film formation solution by subjecting said first insulating film formation solution to a plurality of baking stages at ascending temperatures to provide a first insulating film (10) partially filling the remainder of the unoccupied portion of the contact hole (21) within said second insulation layer (4) coating the surface of said electrical contact member (3) within the contact hole (21), cooling the first insulating film (10), subsequently applying the second insulating film formation solution onto the first insulating film (10) by successive spinning steps including spinning said second insulating film formation solution at a relatively low speed of rotation during a first spinning stage onto the first insulating film (10) and thereafter further spinning said second insulating film formation solution at a relatively high speed of rotation during a second spinning stage onto the first insulating film (10) to complete filling of the remainder of the unoccupied portion of the contact hole (21), and hardening the second insulating film formation solution by subjecting said second insulating film formation solution to a plurality of baking stages at ascending temperatures to provide a second insulating film (11) covering said first insulating film (10) and defining a substantially flat area spanning the contact hole (21) over the top thereof. A method as set forth in claim 4, further characterized in that said first spinning stage in applying each of said first and second insulating film formation solutions is carried out at a speed of 700 RPMs for approximately one second, and said second spinning stage in applying each of said first and second insulating film formation solutions is carried out at a speed of 4000 RPMs for approximately 30 seconds. A method as set forth in either of claims 4 or 5, further characterized in that said plurality of baking stages to which each of said first and second insulating film formation solutions are subjected includes respective baking stages of two minutes duration each at temperatures of 100°C, 180°C, and 260°C. A method as set forth in any of claims 4-6, further characterized in that the step of further hardening the first and second insulating films (10, 11) subjects said first insulating film (10) and said second insulating film (11) to sustained heat over an extended time period and includes a first phase with heat being applied at 250°C for 30 minutes, followed by a second phase with heat being applied at 400°C for 60 minutes in a low pressure nitrogen atmosphere. A method as set forth in any of claims 1-4, wherein said first and second insulating films (10, 11) are formed from solutions having the same solids concentrations, and have a combined thickness in the range of 200 to 400 nm (2000 to 4000 Å) on planar surfaces of said second insulating layer (4).

Inventors: KOBAYASHI SHOJI, YOSHIKAWA MITSURU, KOBAYASHI, SHOJI, YOSHIKAWA, MITSURU
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1992
Main classification: H01L21
IPC codes: H01L21