Automatic signal control for a solid-state image sensor having multiple output registers

Abstract: A signal processing apparatus includes a first loop circuit for adjusting gains of a plurality of variable gain amplifiers (11,13) to which signals output from a charge-coupled device (CCD) imager (1) of multiple-channel (3,5) reading type are applied, a control circuit (4) for driving and controlling an iris (I) in accordance with output signals from the plurality of variable gain amplifiers, a second loop circuit for adjusting levels of pilot (P) signals to be superimposed upon the output signals of the CCD imager at a desired level, respectively, a third loop circuit for controlling levels of the pilot signals which are superimposed upon the output signals of the CCD imager so as to be coincident with each other, and a control unit (4) for controlling the first loop circuit and the control circuit, the second loop circuit, and the third loop circuit so that they are operated in a time-division fashion.

Description: The present invention relates to a signal processing apparatus for use with a video camera, for example, having a CCD (charge-coupled device) or charge transfer device imager having multiple channel outputs. When a signal is processed in previously proposed video cameras having a CCD imager which derives multiple channel outputs, signal processing such as a sample and hold (S/H) processing, automatic gain control (AGC) processing or the like is effected in a parallel fashion, which unavoidably causes a mismatch between channels to occur. A technique is proposed that a pilot signal P which is superimposed upon an output signal M of the CCD imager is detected in the later stage of the parallel processing and used as a feedback signal to cancel a mismatch between channel, as shown in FIG. 1 of the accompanying drawings. FIG. 2 of the accompanying drawings shows in block form a circuit that realizes the above technique. As shown in FIG. 2, output signals from horizontal registers 3, 5 of a CCD imager (2 channels in this example) 1 are respectively supplied to sample and hold circuits 7, 9 whose output signals are respectively supplied to variable gain amplifiers or automatic gain control amplifiers (AGCs) 11, 13. Output signals of the automatic gain control amplifiers 11, 13 are supplied to a signal processor circuit 15 and detector circuits 17, 19 of the succeeding stage. The signal processor circuit 15 processes the output signals of the automatic gain control amplifiers 11, 13 in a predetermined signal processing fashion, and the detector circuits 17, 19 detect the levels of the output signals of the automatic gain control amplifiers 11. 13. An output signal of the detector circuit 17 is compared with a reference level a by a comparator 21 and a signal representative of a compared level is fedback to the automatic gain control amplifiers 11, 13. An output signal of the detector circuit 19 is supplied to a buffer 23 and a comparator 25. An output developed at an inverting terminal of the buffer 23 is supplied to the automatic gain control amplifier 13 and an output developed at the noninverting terminal thereof is supplied to the automatic gain control amplifier 11. The input signal is compared with a reference level b by the comparator 25 and a compared value is fedback to the horizontal registers 3, 5. The output signals of the sample and hold circuits 7, 9 are supplied to a detector circuit 27, in which they are detected in level. An output signal of the detector circuit 27 is supplied to and compared with a reference level c by a comparator 29. A compared output from the comparator 29 is used to control an iris I of a video camera (not shown). The above circuit arrangement, however, has multiple loop circuits operating at the same time. As a consequence, the time constant and response of the circuit cannot be set accurately. There is then the risk that a mismatch between channels cannot be cancelled properly. Patent Abstracts of Japan, vol. 14, no. 105 (E-895) 26 February 1990 and JP-A-1305672 discloses another example of a signal processor for a CCD imager wherein feedback is applied to a sampling circuit to minimise differences between the gains of output amplifiers in two channels. European patent application no. EP-A-0466647 discloses a video camera including a CCD imager, an optical detector and a system controller. The CCD output is supplied to the optical detector via an AGC circuit. The optical detector includes auto-focus, auto-exposure and auto-white balance detector circuits which produce respective detection signals which are supplied by way of a serial interface to the system controller. The system controller controls the opening and closing of an iris and the gain of the AGC circuit in dependence on the auto-exposure detection signal. European patent application no. EP-A-0342708 discloses a video camera in which automatic iris operation and automatic focusing of a lens system are carried out in a time division manner. According to the present invention there is provided signal processing apparatus comprising: (a) a first loop circuit, comprising a detector circuit, a controller and a plurality of variable gain amplifiers, for adjusting the gains of the variable gain amplifiers to which are supplied signals output from a charge-coupled device imager of a multiple-channel read-out type; (b) a control circuit, comprising a detector circuit and the controller, for controlling an iris on the basis of signals output from the variable gain amplifiers while the iris is being driven; (c) a second loop circuit, comprising a plurality of horizontal registers of the imager the variable gain amplifiers, a detector circuit, and the controller, for holding pilot signals which are superimposed upon the output signals the imager at a desired level; and (d) a third loop circuit, comprising the variable gain amplifiers, a detector, a buffer having a normal and an inverting output, and the controller, for holding the pilot signals superimposed on the respective output signals of the imager at substantially the same level; wherein the controller is arranged to control the first loop circuit, the control circuit, the second loop circuit and the third loop circuit such that the operations performed by the respective circuits are carried out in a time division fashion. In embodiments of the invention, since the first loop circuit, the control circuit for controlling the iris, the second loop circuit, and the third loop circuit are controlled so that they are operated in a time division fashion, the first to third loop circuits are not operated in the same time interval. Therefore, there is the advantage in actual practice that mismatching between channels of the CCD imager can be cancelled. Therefore, embodiments of the invention provide a signal processing apparatus for a video camera having a CCD imager with multi-channel outputs in which the aforementioned shortcomings and disadvantages of the previous proposals can be eliminated. More specifically, embodiments of the invention provide a signal processing apparatus for a video camera having a CCD imager with multi-channel outputs which can cancel a mismatch between channels while the respective loop circuits are not operated in the same time interval. A preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which: FIG. 1 is a diagram of waveforms of a pilot signal and an output signal of a CCD imager and to which references will be made in explaining the present invention; FIG. 2 is a block diagram showing a previously proposed signal processing apparatus; FIG. 3 is a block diagram showing a signal processing apparatus according to an embodiment of the present invention; and FIG. 4 is a flowchart to which references will be made in explaining operation of the embodiment of the present invention. A signal processing apparatus according to an embodiment of the present invention will now be described with reference to the drawings. In FIG. 3, parts and elements identical to those of FIG. 2 are marked with the same references and therefore need not be described. As shown in FIG. 3, the output signals of the automatic gain control amplifiers 11, 13 are supplied to a detector circuit 2, in which the levels thereof are detected. Signals representative of the detected levels are supplied to a microcomputer 4. The microcomputer 4 controls the automatic gain control amplifiers 11, 13 on the basis of the signal input from the detector 2. A loop formed of the automatic gain control amplifier 11 (automatic gain control amplifier 13), the detector circuit 2 and the microcomputer 4, in that order, constructs a first loop circuit. A loop formed of the automatic gain control amplifier 11 (automatic gain control amplifier 13), the detector circuit 2, the microcomputer 4 and the buffer 23, in that order, constructs a third loop circuit. A loop formed of the horizontal register 3 (horizontal register 5), the automatic gain control amplifier 11 (automatic gain control amplifier 13), the detector circuit 2 and the microcomputer 4, in that order, constructs a second loop circuit. The iris I is driven under the control of the microcomputer 4. The second loop circuit operates to match the absolute values (pilot levels) of the pilot signals, which are superimposed upon the output signals of the horizontal registers 3, 5, with a desired level. The third loop circuit operates to hold the pilot signals in each channel at substantially the same level (i.e., pilot signal control operation). A processing procedure that the microcomputer 4 executes will be described with reference to a flowchart forming FIG. 4. When the microcomputer 4 is powered and activated, the first initialization is executed at step S1. In the first initialization, the iris I is closed, the outputs of the variable gain amplifiers 11, 13 are set to minimum values, the pilot level is set to a minimum value, and the level of the pilot control signal is set to zero. After this setting mode, the optimum opening amount of the iris I and optimum output values of the automatic gain control amplifiers 11, 13 are detected and stabilized. In decision step S2, it is determined by the microcomputer 4 on the basis of a timer (not shown) or the level change of AGC outputs whether or not the iris I and the automatic gain control amplifiers 11, 13 are stabilized. If a YES is output at decision step S2, then the processing proceeds to the next step S3, whereat the ordinary AGC control operation is carried out. Then, the processing proceeds to the next decision step S4. It is determined in decision step S4 whether or not the AGC outputs have changed. If the AGC outputs have changed as represented by a YES at decision step S4, then the processing proceeds to step S5.Further, this process is executed during a vertical blanking period. Then, the levels of the automatic gain control amplifiers 11 and 13 are controlled and locked at the controlled levels in step S5, whereat the second initialization is executed. In step S6, the desired or suitable level of the pilot signal which is within a dynamic (D) range is calculated on the basis of the output signal of the detector 2 at this time point. In the second loop circuit, the number of the second loop control is decreased so as to match the most significant bit (MSB). The second loop control is executed in a horizontal blanking period. If it is determined that the calculated level is suitable one as represented by a YES at decision step S7, then the processing proceeds to step S8. In step S8, a difference B between levels of the pilot signals are detected and the third loop control or pilot control is executed so that the pilot signals superimposed on the output signals of the horizontal registers 3 and 5 are held at substantially the same level in each channel. The third loop control is executed in a horizontal blanking period and in accordance with up/down of the least significant bit (LSB). If it is determined that the levels of the pilot signals are made coincident each other as represented by a YES at decision step S9, then the processing proceeds to step S10. In step S10, other processing is executed. Then, it is determined in decision step S11 whether or not the microcomputer 4 is disabled. If it is determined that the microcomputer 4 is not disabled as represented by a NO at decision step S11, then the processing returns to step S3. If it is determined that the microcomputer 4 is disabled as represented by a YES, then the processing is ended automatically. The processing at steps S3 to S10 is executed in a period of time shorter than one vertical blanking period. When the processing at step 10 is ended, new data or signals are output to the iris I and from the automatic gain control amplifiers 11 and 13, so that in the next vertical blanking period both the pilot level control and the pilot control are performed at steps S3 to S10 when the outputs of the automatic gain control amplifiers 11 and 13 are changed considerably. In other processing at step S10, both the second and third loop circuits for the pilot level control and the pilot control are locked but the first loop circuit for AGC is placed in an unlocked state. As described above, in accordance with the embodiment of the present invention, since both the second and third loop circuits for the pilot level control and the pilot control are controlled so as to be operated in a time division fashion together with the first loop circuit for the AGC and the control of the iris I, the first to third loop circuits are not operated in the same time interval. Therefore, mismatching between channels can be cancelled.

Claims: Signal processing apparatus comprising: (a) a first loop circuit, comprising a detector circuit (2), a controller (4) and a plurality of variable gain amplifiers (11, 13), for adjusting the gains of the variable gain amplifiers to which are supplied signals output from a charge-coupled device imager (1, 3, 5) of a multiple-channel read-out type; (b) a control circuit, comprising a detector circuit (2) and the controller (4), for controlling an iris (I) on the basis of signals output from the variable gain amplifiers (11, 13) while the iris (I) is being driven; (c) a second loop circuit, comprising a plurality of horizontal registers (3, 5) of the imager (1, 3, 5), the variable gain amplifiers (11, 13), a detector circuit (2), and the controller (4), for holding pilot signals which are superimposed upon the output signals the imager (1, 3, 5) at a desired level; and (d) a third loop circuit, comprising the variable gain amplifiers (11, 13), a detector (2), a buffer (23) having a normal and an inverting output, and the controller (4), for holding the pilot signals superimposed on the respective output signals of the imager (1, 3, 5) at substantially the same level; wherein the controller (4) is arranged to control the first loop circuit, the control circuit, the second loop circuit and the third loop circuit such that the operations performed by the respective circuits are carried out in a time division fashion. Apparatus according to claim 1, wherein the detector in each of the said circuits is the same detector (2). Apparatus according to claim 1 or claim 2, wherein the controller (4) is arranged to control the said circuits such that the first, second and third loop circuits operate in that order.

Inventors: TANAKA KENJI, YAGI OSAMU, TANAKA, KENJI, YAGI, OSAMU, TANAKA, KENJI, PATENTS DIVISION, SONY CORPORATION, YAGI, OSAMU, PATENTS DIVISION, SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H04N5
IPC codes: H04N5