Printing method and an apparatus therefor

Abstract: A printing method comprises the steps of sampling a video signal two times for a duration of one horizontal scanning line within one frame to generate digitally converted pixel data, alternately writing the digitally converted pixel data in two line memories by frame periods, and alternately reading the digital data which is stored in the two line memories to perform printing of the read digital data. Here, two vertical lines are written in a first line memory during one frame, and the written two vertical lines are printed for a subsequent frame while alternately writing in a second memory two more vertical lines which are sequential to the printed vertical lines. Accordingly, a doubled printing speed is obtained compared with the conventional method of alternately printing single lines. Apparatus for performing the method is also disclosed.

Description: The present invention relates to printing, and more particularly to colour video printers. Colour video printers output a hard copy of an input still image signal. In printers using a sublimation thermal transfer system, current corresponding to a video signal to be written is supplied to a thermal printing head (TPH: a write electrode composed of a series of heat emitting devices), and dyes adhered to a transfer film disposed adjacent thereto are allowed to sublimate by heat generated from the TPH, so that image information is written on a sheet of paper. Printers using the sublimation thermal transfer system separate a video signal of one frame into a colour signal having RGB components, and perform printing by sequential frames of each colour component. Figure 1 of the accompanying diagrammatic drawings is a block diagram showing a conventional colour video printer. The colour video printer shown in Figure 1 carries out printing by selectively receiving a composite video signal from a display (e.g., a TV receiver or video recorder) and a super video signal from a graphic apparatus (e.g., a computer). A signal in the form of a composite video signal is supplied to a luma/chroma signal (Y/C) separator 1. The output from Y/C separator 1 is supplied to one input of an input selector 2. In the meantime, the other input of input selector 2 is supplied with a signal in the form of a super video signal. The signal selected in input selector 2 is supplied to a colour difference signal decoder 3. The colour difference signal in colour decoder 3 is supplied to a still/moving picture selecting unit comprising a first selection switch 4a and a second selection switch 4b. The colour difference signal output from one output of first selection switch 4a is input to a still picture memory 5 whose output is supplied to one input of second selection switch 4b. Meanwhile, the colour difference signal from the other output of first selection switch 4a is directly supplied to the other input of second selection switch 4b. The colour difference signal in second selection switch 4b is supplied to an RGB decoder 6. The colour signal output from RGB decoder 6 is simultaneously supplied to an encoder 7 and a printing unit 10. The composite video signal from encoder 7 is monitored via a display 8. Meanwhile, the colour signal supplied to printing unit 10 is hard-copied via a TPH 20. Hereinbelow, the construction of printing unit 10 will be described in detail. The colour signal input to printing unit 10 is first supplied to an RGB selector 11. The colour signal selected in RGB selector 11 is supplied to an analog-to-digital (A/D) converter 12. The signal digitized in A/D converter 12 is supplied via n bit lines to an input switch 14. The signal from input switch 14 is supplied to a line memory 16. The signal from line memory 16 is supplied to an output switch 18. The signal from output switch 18 is supplied to an intermediate gradation converter (IGC) 19. A pulse-width' modulated signal from IGC 19 is supplied to TPH 20 which then carries out the printing. A sampling pulse generator 13 generates a sampling pulse required in A/D converter 12 and a line memory controller 17 which, using the sampling pulse, produces an address and control signal required in line memory 16. An I/O switching controller 15 generates a signal for controlling both input and output switches 14 and 18. Now, the operation of the printer having the above-described construction will be described. The "composite video signal separated into luma/chroma" or "super video" signal selected corresponding to a composite/super selection signal in input selector 2 is supplied to colour difference signal decoder 3. The colour difference signal having R-Y, B-Y and Y components in colour difference signal decoder 3 is supplied to the still/moving picture selector unit (4a and 4b). In conjunction with the still/moving picture selector unit, still picture memory 5 is provided to store a video signal in frames, for the case of the input signal being a moving image signal. When the moving picture is selected by means of a still/moving picture selection signal, first selection switch 4a is controlled to output the input signal to a first output, and second selection switch 4b is controlled to output the signal input to its first input. By this operation, a video signal of one frame in the moving video signal input to the colour video printer is separated, to thereby be stored in still picture memory 5; otherwise, the still picture signal stored in still picture memory 5 is output to be printed. On the other hand, when the still picture is selected, first selection switch 4a is controlled to output the input signal to its second output, and second selection switch 4b is controlled to output the signal input to its second input. Accordingly, the still picture signal input to the colour video printer is thus printed. Since the moving picture signal input to the colour video printer is composed of a video signal having several frames, one frame is separated to thereby be stored as a still picture. In this state, the video signal input to still picture memory 5 is digitized in an analog-to-digital (A/D) converter 5a and then stored in a memory 5b. Therefore, when the still image signal stored in memory 5b is to be printed, it is first read out and converted into an analog signal via a digital-to-analog (D/A) converter 5d, and then the analog signal is output. The colour difference signal from second selection switch 4b is converted into R, G and B signals suitable for use in printing unit 10 by means of RGB decoder 6, and then is supplied to RGB selector 11 of printing unit 10. The R, G or B signal selected in RGB selector 11 is supplied to a cyan/magenta/yellow transfer film, and then hard-copied onto a sheet of paper. In accomplishing such a hard copy, the B signal is first selected to print the B component of the still picture, followed by the G signal being selected to print the G component, and then the R signal is selected to print the R component. This printing method is called the "frame-sequential" method because a still picture's RGB components are sequentially printed in frame units. Next, the printing of the selected R, G or B signal will be described in more detail. The signal selected in RGB selector 11 is digitized in A/D converter 12, and then supplied to input switch 14. In performing the frame-sequential printing of one frame of a still picture, the colour video printer having the structure shown in Figure 1 sequentially prints the pixels in the vertical direction of the pixel array constituting one frame, from left to right by columns. By this operation, A/D converter 12 must perform the sequential sampling of the vertical lines of the pixel array constituting one frame, from left to right. The sampling pulse corresponding to this sampling is produced in sampling pulse generator 13. The digitized pixel signal from input switch 14 is stored in line memory 16 to be output to IGC 19 via output switch 18, thereby being pulse-width-modulated. The pulse-width-modulated signal is supplied to TPH 20 so that the printing can be executed. Line memory 16 for the reading and writing of pixels in the column direction which are digitized in A/D converter 12, includes two line memories (LM) for performing high-speed printing, so that the read/write operations are carried out by the complementary operation of first and second line memories 16a and 16b. The control signal needed in input and output switches 14 and 18 is supplied from I/O switching controller 15, and the address and control signal for read/write operation of line memory 16 is supplied from line memory controller 17. During printing by printing unit 10, the picture being printed is monitored via encoder 7 and display 8. Figure 2 of the accompanying diagrammatic drawings shows the relation between the pixel array and the line memory in one frame. Here, oblique solid lines indicate horizontal scanning lines in an odd field, and oblique dotted lines indicate horizontal scanning lines in an even field. In the NTSC system, each field has 262.5 horizontal scanning lines which are interleaved with each other. For convenience of explanation, the first horizontal line of an odd field is called a first scanning line, the first horizontal line of an even field is a second scanning line, the second horizontal line of an odd field is a third scanning line, and the second horizontal line of an even field is a fourth scanning line, and so on. Accordingly, in Figure 2, the odd field consists of the odd-numbered horizontal lines, and the even field consists of the even-numbered horizontal lines. The pixel array of one frame is formed by a number of pixels X per horizontal scanning line and a number of pixels Y in the vertical direction. For example, in the NTSC system, X is 600 and Y is 525 which is the same as the number of horizontal scanning lines. Also, assuming that an interval of the horizontal scanning line from the first pixel to the last pixel is an effective horizontal scanning duration T VH , sampling frequency fs becomes equal to the number of pixels per horizontal scanning line divided by the effective horizontal scanning duration, that is, X/T VH . The printing of one frame is achieved by successively printing one line in the vertical direction of the pixel array from left to right. First, in the first frame period, the pixels of the first vertical line denoted by x's at the left are consecutively sampled from top to bottom, thereby being written in first line memory 16a. In the second frame period, the pixels of the second vertical line (denoted by circles) are sampled to be written in second line memory 16b and, at the same time, the pixels of the first vertical line written in first line memory 16a are read out to be printed via IGC 19 and TPH 20. Then, in the third frame period, the above-described operation is reversely performed, so that the writing of the pixels of the third line (denoted by ⊗) in first line memory 16a and the reading out of second line memory 16b are carried out. Next, the pixels of the fourth line (denoted by □) are read into the second line memory 16b whilst the third line pixels are read out of the first line memory 16a - and so on. By repeating these steps, the printing of 600 vertical lines is completed, which results in the printing of one colour. The still picture on one frame is printed by repeating the above printing operation for each of the three colours. Figure 3 of the accompanying diagrammatic drawings is a timing chart showing read/write operations of line memory. During the first frame period, the first vertical line is written in first line memory 16a. During the second frame period, the pixels written in first line memory 16a are read out during the odd-field period, thereby being printed. The even-field period is provided as a heat-emission period of the TPH. During the third frame period, the third vertical line is written in first line memory 16a. Meanwhile, the second vertical line is written in second line memory 16b during the second frame period. In the third frame period, the pixels written in second line memory 16b are read out during the odd-field period, thereby being printed. The even-field period is provided as the heat-emission period of the TPH. During the fourth frame period, the fourth vertical line will be written in second line memory 16b. In the above-described colour video printer, given the frame period of the NTSC system as 1/30th of a second (≈33ms), the time required for printing one colour of the still picture of one frame can be calculated thus: 33ms x 600 lines = 19.8s, so that the time require for printing one frame is 19.8S x 3 = 59.3S. Therefore, if the time for paper-feeding and paper-discharge takes twenty seconds, the total printing time for the still picture of one frame becomes approximately 80 seconds. Experimentation shows that picture quality remains unaffected even though the printing is successively performed by eliminating the heat-emission period illustrated in Figure 3. US-A-5,045,951 concerns a processor and a method for a video printer which is capable of sampling a high frequency video circuit signal without raising the operating speed of the sampling circuit. To do this, sampling of an input video signal is carried out, not in a pixelwise manner (i.e. one pixel sampled after another) but, for example, at 32 pixel intervals so as to allow a relatively slow sampling speed to be utilised. Whilst -A-US5,045,951 does provide an efficient means of sampling an input video signal, it does not address the basic problem of overall system speed being dictated by the operational speed of the printer, which is a common problem. Preferred embodiments of the present invention aim to provide a printing method for increasing the printing speed by doubling the number of vertical lines printable for one frame period in a colour video printer. It is another aim to provide a printing apparatus suitable for the printing method. According to one aspect of the present invention, there is provided a printing method for printing by vertical lines one frame of a still video signal having a horizontal and vertical pixel arrangement, the method comprising the initial step of sampling a video signal twice at successive pixel locations for each horizontal scanning period of a frame to generate digitized pixel data, the method being characterized in that it includes the further steps of: writing said digitized pixel data, which corresponds to a pair of vertical lines, into a first of first and second two line memories; during said writing step, reading out digitized pixel data previously written to the second of said two line memories, so as to print the read data; and in a subsequent operation, repeating the sampling step to subsequently write new digitized pixel data into the second of said two line memories, whilst reading out digitized pixel data from the first of said two line memories and repeating this sequence of steps until a full frame of the video signal has been printed out. Preferably, said sampling step is further characterized in that it comprises the steps of: incrementing an up-counter whenever a frame signal is received; loading said counted-up value as a preset value to a down-counter whenever a horizontal sync signal is generated and counting down in accordance with a clock signal applied to its clock input terminal; and inputting said counted down value to a pulse generator to generate a sampling pulse to sample pixels of a first contiguous pair of vertical lines during a one frame, those of a second contiguous pair of vertical lines during a next frame etc. Preferably, the up counter is incremented whenever a pair of vertical sync signals are received. Preferably, said up-counter is reset following the printing of a final vertical line. Preferably, to generate a correct sampling pulse during first and second frames the down counter is loaded with a predetermined offset value. Preferably, loading of the counted-up value from the up-counter to the down-counter is blocked during the first and second frames. Preferably, in said writing step, contiguous pixels of odd and even fields are stored in contiguous writing addresses. Preferably, in said writing step, a preceding vertical line and a succeeding vertical line are stored in non-contiguous writing addresses. Preferably, in said reading-out step, a pair of vertical lines stored in one of said two line memories are read out and printed during odd and even fields of a frame. According to a second aspect of the invention, there is provided a printing apparatus for printing by vertical lines one frame of a still video signal having a horizontal and vertical pixel arrangement, the apparatus comprising an analog-to-digital convertor for sampling a video signal twice at successive pixel locations for each horizontal scanning period of a frame and obtaining samples of a contiguous pair of vertical lines of a frame to generate digitized pixel data, a sampling pulse generator for generating sampling pulses for use in said analog-to-digital converter, memory means for storing said digitized pixel data, an input switch for inputting said digitized pixel data into said memory means, an output switch for outputting said digitized pixel data from said memory means, an input/output switching controller for generating signals which control said input switch and output switch and a line memory controller for generating a writing/reading address of said memory means, the apparatus being characterized in that said memory means comprises first and second two line memories, each being adapted to store a pair of vertical lines of a frame, the first of said two line memories being adapted to be written to whilst the second is being read from and vice versa and, in that said input and output switches are controlled to alternately switch between said first and second line memories according to which memory is to be written to and which memory is to be read from at any given time; the read data being supplied to a printer. Preferably, said analog-to-digital converter further comprises a tri-state buffer for keeping a high output impedance when an analog-to-digital converting operation is not performed. Said sampling pulse generator preferably comprises: an up-counter for up-counting whenever a frame signal is received; a down-counter for loading said counted value of said up-counter as a preset value whenever a horizontal sync signal is generated and down counting in accordance with clock signals applied to its clock terminal; a pulse generator for detecting said counted value of said down-counter so as to generate a sampling pulse to sample pixels of a first contiguous pair of vertical lines during one frame and those of a second contiguous pair of vertical lines during a next frame etc.; and a clock generator for generating the clock signals. Said up-counter is preferably incremented whenever a pair of vertical sync signals are received. Preferably, said sampling pulse generator further comprises a delay line for blocking the loading of the counted up value from the up-counter to the down-counter during the first and second frames. Said sampling pulse generator may further comprise a reset circuit for clearing said counted-up value after a final vertical line is printed. Said clock generator preferably generates a clock signal having a period which is determined by dividing the duration of effective horizontal scanning by the number of pixels in the horizontal direction. Preferably, to generate a correct sampling pulse during first and second frames said down-counter is loaded with a predetermined offset value. Preferably, said pulse generator comprises: a sampling pulse location detector for detecting the counted-down values of said down-counter to detect a final value or the final value minus one; and an AND gate for logically operating the outputs of said sampling pulse location detector and the clock signal. The input/output switching controller preferably comprises: a sync separator for separating a horizontal sync signal and a vertical sync signal from a composite sync signal; a field identifier for generating a field identification signal from the composite sync signal and vertical sync signal; and a frame identifier for dividing said field identification signal by two so as to generate a frame identification signal. Preferably, said line memory controller comprises: a read address counter for generating a read address; a write address counter for generating a write address; a read address switch for selectively outputting the address of said read address counter to a first line memory or a second line memory; and a write address switch for selectively outputting the address of said write address counter to the first line memory or the second line memory. Preferably, said write address counter generates recording addresses in accordance with sampling pulses generated by said sampling pulse generator. Preferably, the least significant bit of the address output from said write address counter is replaced with an odd/even field identification signal. Preferably, the most significant bit of the address output from said write address counter is replaced with a signal which is obtained by dividing the sampling pulses by two. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 4 to 10 of the accompanying diagrammatic drawings, in which: Figure 4 is a view showing the relation between the pixel array and a line memory in one frame in one example of the present invention; Figure 5 is a timing chart showing a printing operation in one example of the present invention; Figure 6 is a block diagram showing the construction of one example of a printing apparatus according to the present invention; Figures 7A, 7B and 7C are waveforms showing the operation of a sampling pulse generator shown in Figure 6; Figures 8A-8F are waveforms showing the operation of an I/O switching controller shown in Figure 6; Figures 9A-9F is a timing chart showing the I/O operations of the line memory shown in Figure 6; and Figure 10 is a block diagram showing the construction of a line memory controller shown in Figure 6. In the figures, like reference numerals denote like or corresponding parts. In the example of Figure 4, the operation of printing one frame is accomplished by printing two vertical lines of the pixel array from left to right in succession. Firstly, in the duration corresponding to one frame, the pixels designated by "x" in the first vertical line and pixels designated by "0" in the second vertical line on the left side of Figure 4, being sampled in sequence from top to bottom, are stored in a first line memory. After all of the pixels of the first and second vertical lines are stored in the first line memory, the pixels in the third and fourth vertical lines (shown as "⊗" and "□") are sampled to be written in a second line memory and simultaneously the pixels of the first and second vertical lines are read from the first line memory and printed via IGC 19 and TPH 20. When the write operation into the second line memory and the read operation from the first line memory are completed, the above operations are conversely executed, i.e., writing into the first line memory and reading from the second are performed. As shown in the timing diagram of Figure 5, during the first frame, the pixels of the first and second vertical lines are written in the first line memory. During the odd field of the second frame the pixels of the first vertical line having been written in are read out therefrom to be printed, and during the even field, the pixels of the second vertical line are read out therefrom and printed. The pixels of the fifth and sixth vertical lines are written in the first line memory during the third frame. On the other hand, the third and fourth vertical lines are written in a second line memory during the second frame. During the odd field of the third frame the pixels of the third vertical line having been written in the second line memory are read out therefrom to be printed, and during the even field, the pixels of the fourth vertical line are read out therefrom and printed. The pixels of the seventh and eighth vertical lines are written in the second line memory during the fourth frame. In the colour video printer of Figure 6, like reference numerals corresponding to like parts of Figure 1 are adopted, and so a detailed description thereof will be omitted. In the colour video printer apparatus of Figure 6, line memory 26 corresponds to line memory 16 of Figure 1, sampling pulse generator 23 to sampling pulse generator 13 of Figure 1, input/output switch controller 25 to input/output switch controller 15 of Figure 1, and line memory controller 27 to line memory controller 17 of Figure 1. First line memory 26a and second line memory 26b of line memory 26 have capacities adapted to store the pixels of two vertical lines as shown in Figure 4. In the NTSC method, since the number of pixels of one vertical line is 525 (equal to the number of the horizontal scanning lines), memory capacities of 1,050 (525x2) are necessary to store two vertical lines. Accordingly, the number of bits for address assignment should be 10. A/D converter 13 comprises tri-state buffer 12b for maintaining a high-impedance output thereof, when the A/D conversion is not performed. Sampling pulse generator 23 comprises an up-counter 23a for counting the frame period a down-counter 23b for loading and counting the value counted in up-counter 23a as a preset value by the period of the horizontal scanning line, a pulse generator 23c for generating a sampling pulse for a binary value of "10" or "01" by detecting the counted value from down-counter 23b, a delay circuit 23d for delaying the operation of down-counter 23b from the vertical sync pulse to the effective horizontal scanning line pulse, a clock generator 23e for generating a clock signal having the period of the sampling pulse, and a reset circuit 23f for resetting up-counter 23a. Two resistors 42 and 44 are connected in parallel to preset input terminals of down-counter 23b. These resistors 42 and 44 provide the offset for the second lowest bit (LSB1) and the least significant bit (LSB0) of the preset input value, respectively. Pulse generator 23c comprises a sampling pulse location detector 23c-1 for detecting the final value, or final value minus one, by detecting the downcounted value of down-counter 23b, and an AND gate 23c-2 for generating the sampling pulse being supplied to A/D converter 12 by logically AND operating the output of sampling pulse location detector 23c-1 and the clock signal. Sampling pulse location detector 23c1 comprises m - 1 inverters 32a, 32b... 32(m - 1) corresponding to the m - 1 output lines excluding the second lowest bit (LSB1) among the m-bit output lines from down-counter 23b, and AND gate 34 which receives the respective outputs of inverters 32a through 32(m - 1) and the LSB1 output, m - 1 inverters 36a, 36b...36(m - 1) corresponding to the m - 1 output lines excluding the least significant bit (LSB0) among the m-bit output lines from down-counter 23b, and AND gate 38 which receives the respective outputs of inverters 36a through 36(m - 1) and the LSB0 output, and an OR gate 39 which receives the outputs of the above two AND gates 34 and 38. Delay circuit 23d comprises a monostable multivibrator 23d-1 for generating an interval signal corresponding to effective horizontal scanning duration T VH in response to the input vertical sync signal, and a NAND gate 23d-2 which receives the interval signal and the horizontal sync signal. Clock generator 23e generates a clock signal having a period which is determined by dividing the duration of effective horizontal scanning by the number of pixels in the horizontal direction. Reset circuit 23f clears up-counter 23a after the final vertical line has been printed. Figures 7A, 7B and 7C are waveform diagrams showing the operation of the sampling pulse generator shown in Figure 6. Figure 7A shows the waveform of the vertical sync signal being input to up-counter 23a. Up-counter 23a counts by one for every two vertical sync signals (one frame) input and supplies the output thereof to down-counter 23b. Figure 7B shows the waveform of the horizontal sync signal being input to an inverted load terminal of down-counter 23b. Down-counter 23b loads the preset value being applied thereto for each horizontal sync signal being input, and downcounts in accordance with the clock signal input via its clock input terminal. Figure 7C shows the waveform of the sampling pulse being supplied to A/D converter 12 of Figure 6. Pulse generator 23c detects the counted value of down-counter 23b, thereby for a binary counted value of "10" or "01", gating the clock signal to supply a sampling pulse. As shown in Figure 4, A/D converter 12 should control the sampling position so as to sample the pixels of the first and second vertical lines during the first frame and those of the third and fourth vertical lines during the second frame. To perform the above operation the lapsed frame duration is counted and the counted value is downcounted by subtracting the period of the clock signal therefrom, so that the sampling position can be changed. Here, since an accurate sampling pulse is not obtainable for the counted values of "1" and "2" in the first and second frames an offset of "11" is added to the preset value of down-counter 23b. In addition, a delay circuit 23d limits the input of the horizontal sync signal from the vertical sync duration to the effective horizontal scanning duration. Input/output switch controller 25 includes a sync separator 25a for separating the horizontal sync signal and vertical sync signal from the composite sync signal, a field identifier 25b for generating the field identification signal from the composite sync signal and vertical sync signal, and a frame identifier 25c for generating the frame identification signal by dividing-by-two the field identification signal. Here, field identifier 25b comprises two serially connected monostable multivibrators 72 and 74 for generating the detected pulse of Figure 8C, an AND gate 76 which receives the detected pulse and the composite sync signal, and a D flip-flop 78 for receiving the output of AND gate 76 and generating the field identification signal of Figure 8E. Also, frame identifier 25c comprises a D flip-flop 82 for dividing the field identification signal by two and generating the frame identification signal of Figure 8F, and an inverter 84 for inverting the frame identification signal from D flip-flop 82. Figures 8A through 8E are waveform diagrams showing the operations of input/output switch controller 25. Figure 8A shows a waveform of the composite sync signal including the equalization pulse. Odd fields include the sixth equalization pulse following the vertical sync signal but even fields do not have this kind of pulse which enables a field identification signal to be generated. To detect the sixth equalization pulse (shown in Figure 8D) by using the vertical sync signal shown in Figure 8B, the detected pulse shown in Figure 8C is generated, and then the signals represented by the waveforms of Figures 8A and 8C are logically AND-operated through the AND gate of input/output switch controller 25. The equalization pulse and vertical sync signal shown in Figure 8D are used to generate the field identification signal shown in Figure 8E. Moreover, the field identification signal of Figure 8E is divided by two so as to generate the frame identification signal shown in Figure 8F. Figures 9A through 9F are timing diagrams showing the input/output operation of line memory 16 shown in Figure 6. Figure 9A shows the waveform of the vertical sync signal. Figure 9B shows the waveform of the frame identification signal. Figures 9C and 9D show the operations of input switch 13 and output switch 18, respectively, corresponding to the timing of the frame identification signal shown in Figure 9B. Figures 9E and 9F show the read/write timings of line memories 16a and 16b, respectively, corresponding to the timing of the frame identification signal shown in Figure 9B. Figure 10 is a block diagram showing line memory controller 27. Line memory controller 27 comprises a read address counter 27a for generating the read address, a write address counter 27b for generating the write address, a read address switch 27c for selectively outputting the address of read address counter 27a to first line memory 16a or second line memory 16b, and a write address switch 27d for selectively outputting the address of write address counter 27b to first line memory 16a or second line memory 16b. Read address counter 27a generates the addresses to read the pixels of the odd-and even-field vertical lines during one frame, respectively. Write address counter 27b counts the recording address by the period of sampling pulses, and the least significant bit (LSB) of the address output therefrom is replaced with the odd/even field identification signal, so that the pixels of the odd and even fields constituting one vertical line have successive addresses. The most significant bit (MSB) of the addresses output from write address counter 27b is replaced with a signal which is obtained by dividing by-two the sampling pulse supplied to A/D converter 12, so that the write addresses of the preceding vertical line and the succeeding vertical line become discontinuous. The above-described example of a printing apparatus according to the present invention has an advantage of decreasing the time necessary in printing a still image of one frame to half that of a conventional printer apparatus, by writing two vertical lines in the first line memory during one frame, and then writing two vertical lines in the second line memory during the following frame. Simultaneously, the printing apparatus reads the pixels of two vertical lines from the first line memory to be printed, and repetitively performs operations which are the reverse of those above, during the following frame. Therefore, the illustrated embodiment of the present invention enhances the competitiveness of the printer apparatus, by satisfying user requirements for high-speed printing. In the above embodiment, a colour video printer having colour difference memories is described. However, it is to be noted that the concept of the present invention can be also applied to a colour video printer having R, G and B memories. While a particular embodiment of the present invention has been particularly shown and described, it will be understood by those skilled in the art that various changes in form and details may be effected therein without departing from the scope of the invention as defined by the appended claims. The invention may be applied to systems other than NTSC systems - such as, for example, the PAL and SECAM systems used in Europe and elsewhere.

Claims: A printing method for printing by vertical lines one frame of a still video signal having a horizontal and vertical pixel arrangement, the method comprising the initial step of sampling a video signal twice at successive pixel locations for each horizontal scanning period of a frame to generate digitized pixel data, the method being characterized in that it includes the further steps of: writing said digitized pixel data, which corresponds to a pair of vertical lines, into a first of first (26a) and second two line memories (26a, 26b); during said writing step, reading out digitized pixel data previously written to the second (26b) of said two line memories (26a, 26b), so as to print the read data; and in a subsequent operation, repeating the sampling step to subsequently write new digitized pixel data into the second (26b) of said two line memories (26a, 26b), whilst reading out digitized pixel data from the first (26a) of said two line memories (26a, 26b) and repeating this sequence of steps until a full frame of the video signal has been printed out. A printing method as claimed in claim 1, wherein said sampling step is further characterized in that it comprises the steps of: incrementing an up-counter (23a) whenever a frame signal is received; loading said counted-up value as a preset value to a down-counter (23b) whenever a horizontal sync signal (HSYNC) is generated and counting down in accordance with a clock signal applied to its clock input terminal; and inputting said counted down value to a pulse generator (23c) to generate a sampling pulse to sample pixels of a first contiguous pair of vertical lines during one frame, those of a second contiguous pair of vertical lines during a next frame etc. A printing method as claimed in claim 2, wherein, the up counter (23a) is incremented whenever a pair of vertical sync signals (VSYNC) are received. A printing method as claimed in claim 2 or 3, wherein said up-counter (23a) is reset following the printing of a final vertical line. A printing method as claimed in claim 2, 3 or 4, wherein, to generate a correct sampling pulse during first and second frames the down counter (23b) is loaded with a predetermined offset value. A printing method as claimed in claim 5, wherein loading of the counted-up value from the up-counter (23a) to the down-counter (23b) is blocked during the first and second frames. A printing method as claimed in any of the preceding claims, wherein, in said writing step, contiguous pixels of odd and even fields are stored in contiguous writing addresses. A printing method as claimed in any of the preceding claims, wherein, in said writing step, a preceding vertical line and a succeeding vertical line are stored in non-contiguous writing addresses. A printing method as claimed in any of the preceding claims, wherein, in said reading-out step, a pair of vertical lines stored in one of said two line memories (26a, 26b) are read out and printed during odd and even fields of a frame. A printing apparatus for printing by vertical lines one frame of a still video signal having a horizontal and vertical pixel arrangement, the apparatus comprising an analog-to-digital convertor (12) for sampling a video signal twice at successive pixel locations for each horizontal scanning period of a frame and obtaining samples of a contiguous pair of vertical lines of a frame to generate digitized pixel data, a sampling pulse generator (23) for generating sampling pulses for use in said analog-to-digital converter (12), memory means (26a, 26b) for storing said digitized pixel data, an input switch (13) for inputting said digitized pixel data into said memory means (26a, 26b), an output switch for outputting said digitized pixel data from said memory means (26a, 26b), an input/output switching controller (25) for generating signals which control said input switch (13) and output switch (18) and a line memory controller (27) for generating a writing/reading address of said memory means (26a, 26b), the apparatus being characterized in that said memory means (26a, 26b) comprises first and second two line memories (26a, 26b), each being adapted to store a pair of vertical lines of a frame, the first (26a, 26b) of said two line memories being adapted to be written to whilst the second (26b, 26a) is being read from and vice versa and, in that said input and output switches (13, 18) are controlled to alternately switch between said first and second line memories (26a, 26b) according to which memory is to be written to and which memory is to be read from at any given time; the read data being supplied to a printer. A printing apparatus as claimed in claim 10, wherein said analog-to-digital converter (12) further comprises a tri-state buffer (12b) for keeping a high output impedance when an analog-to-digital converting operation is not performed. A printing apparatus as claimed in claim 10 or 11, wherein said sampling pulse generator (23) comprises: an up-counter (23a) for up-counting whenever a frame signal is received; a down-counter (23b) for loading said counted value of said up-counter (23a) as a preset value whenever a horizontal sync signal is generated and down counting in accordance with clock signals applied to its clock terminal; a pulse generator (23c) for detecting said counted value of said down-counter so as to generate a sampling pulse to sample pixels of a first contiguous pair of vertical lines during one frame and those of a second contiguous pair of vertical lines during a next frame etc.; and a clock generator (23e) for generating the clock signals. A printing apparatus as claimed in claim 12, wherein said up-counter (23a) is incremented whenever a pair of vertical sync signals are received. A printing apparatus as claimed in claim 12 or 13, wherein said sampling pulse generator (23) further comprises a delay line (23d) for blocking the loading of the counted up value from the up-counter (23a) to the down-counter (23b) during the first and second frames. A printing apparatus as claimed in claim 12, 13 or 14, wherein said sampling pulse generator (23) further comprises a reset circuit (23f) for clearing said counted-up value after a final vertical line is printed. A printing apparatus as claimed in claim 12, 13, 14 or 15, wherein said clock generator (23e) generates a clock signal having a period which is determined by dividing the duration of effective horizontal scanning by the number of pixels in the horizontal direction. A printing apparatus as claimed in any of claims 12 to 16, wherein to generate a correct sampling pulse during first and second frames said down-counter (23b) is loaded with a predetermined offset value. A printing apparatus as claimed in any of claims 12 to 17, wherein said pulse generator (23c) comprises: a sampling pulse location detector (23c-1) for detecting the counted-down values of said down-counter to detect a final value or the final value minus one; and an AND gate (23c-2) for logically operating the outputs of said sampling pulse location detector and the clock signal. A printing apparatus as claimed in any of claims 10 to 18, wherein said input/output switching controller (25) comprises: a sync separator (25a) for separating a horizontal sync signal and a vertical sync signal from a composite sync signal; a field identifier (25b) for generating a field identification signal from the composite sync signal and vertical sync signal; and a frame identifier (25c) for dividing said field identification signal by two so as to generate a frame identification signal. A printing apparatus as claimed in any of claims 10 to 19, wherein said line memory controller (27) comprises: a read address counter (27a) for generating a read address; a write address counter (27b) for generating a write address; a read address switch (27c) for selectively outputting the address of said read address counter (27a) to a first line memory or a second line memory (26a, 26b); and a write address switch (27d) for selectively outputting the address of said write address counter (27b) to the first line memory or the second line memory (26a, 26b). A printing apparatus as claimed in claim 20, wherein said write address counter (27b) generates recording addresses in accordance with sampling pulses generated by said sampling pulse generator (23). A printing apparatus as claimed in claim 20 or 21, wherein the least significant bit of the address output from said write address counter (27b) is replaced with an odd/even field identification signal. A printing apparatus as claimed in claim 20, 21 or 22, wherein the most significant bit of the address output from said write address counter (27b) is replaced with a signal which is obtained by dividing the sampling pulses by two.

Inventors: KWAK HEUI-KUK, KWAK, HEUI-KUK
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1992
Main classification: H04N1
IPC codes: B41J2, H04N5, H04N1