Quantum phase interference transistor

Abstract: A quantum phase interference transistor according to the invention comprises an emitter (5) for emitting electron waves into a vaccum, a gate electrode (7) for controlling the phase difference between a plurality of electron waves, and a collector (6) for collecting the electron waves. The characterizing feature is that the gate electrode (7) has the construction of a capacitor or a plurality of capacitors. Various methods of manufacturing are described. This type of quantum phase interference transistor can be operated with very high modulation efficiency at room temperature.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a transistor based on the principle of vacuum microelectronics and, more particularly, to a quantum phase interference transistor. Description of the Prior Art Recent progress in microstructure fabricating techniques has activated studies of electron wave interference devices utilizing the coherence of electron waves. An electron wave interference transistor utilizing the Aharonov-Bohm effect (hereinafter referred to as "AB effect transistor") employing AlGaAs/GaAs double heterojunction has been proposed in, for example, Technical Digest of IEDM 86, pp. 76-79. This previously proposed AB effect transistor, however, must be cooled at a very low temperature below the temperature of liquid helium (4.2°K) to maintain the coherence of electrons. Therefore this AB effect transistor is difficult to apply to simple purposes and is disadvantageous in cost. SUMMARY OF THE INVENTION It is a first object of the present invention to provide a quantum phase interference transistor capable of efficiently using the variation of the interference pattern of electron waves caused by phase control as the variation of collector current. A second object of the present invention is to provide a quantum phase interference transistor capable of operating at a room temperature at a high modulation efficiency and of increasing current that flows between the emitter and the collector. A third object of the present invention is to provide a quantum phase interference transistor based on vacuum microelectronics, capable operating at a room temperature, and having a sufficiently high quantum-mechanical transition probability modulating efficiency. A fourth object of the present invention is to provide a quantum phase interference transistor capable of operating at a room temperature and of readily emitting electrons from the emitter. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view of a quantum phase interference transistor in a first embodiment according to the present invention; Fig. 2 is a sectional view of the quantum phase interference transistor shown in Fig. 1; Figs. 3A to 3C are sectional views of assistance in explaining an etching process in a method of fabricating the quantum phase interference transistor shown in Figs. 1 and 2; Figs. 4A to 4D are sectional views of a method of fabricating the quantum phase interference transistor shown in Figs. 1 and 2; Fig. 5 is an enlarged fragmentary sectional view of assistance in explaining a modulation system employed by the quantum phase interference transistor shown in Figs. 1 and 2; Fig. 6 is a perspective view showing the construction of a quantum phase interference transistor; Fig. 7 is a sectional view of the quantum phase interference transistor shown in Fig. 6; Fig. 8 is an enlarged fragmentary sectional view of assistance in explaining a modulation system employed by the quantum phase interference transistor shown in Figs. 6 and 7; Fig. 9 is a perspective view of assistance in explaining a method of fabricating the quantum phase interference transistor shown in Figs. 6 and 7; Fig. 10 is a perspective view of assistance in explaining epitaxial growth on the tip of the emitter of a quantum phase interference transistor; Fig. 11 is a perspective view of a quantum phase interference transistor in a second embodiment according to the present invention; Fig. 12 is a sectional view of the quantum phase interference transistor shown in Fig. 11; Figs. 13A to 13J are sectional views of assistance in explaining a method of fabricating the quantum phase interference transistor shown in Figs. 11 and 12; Fig. 14 is a sectional view of a quantum phase interference transistor in a third embodiment according to the present invention; Fig. 15 is a fragmentary sectional view of assistance in explaining a method of fabricating the quantum phase interference transistor shown in Fig. 14; Fig. 16 is a perspective view of a quantum phase interference transistor in a fourth embodiment according to the present invention; Fig. 17 is a sectional view of the quantum phase interference transistor shown in Fig. 16; and Fig. 18 is a sectional view of assistance in explaining a method of fabricating the quantum phase interference transistor shown in Fig. 16. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Quantum phase interference transistors in preferred embodiments according to the present invention will be described hereinafter with reference to the accompanying drawings, in which the same or corresponding parts are denoted by the same reference characters. Fig. 1 is a perspective view of a quantum phase interference transistor in a first embodiment according to the present invention, and Fig. 2 is a sectional view taken on line 2-2 in Fig. 1. Referring to Figs. 1 and 2, the quantum phase interference transistor in the first embodiment according to the present invention has supports 1a and 1b formed opposite to each other with a predetermined space therebetween on, for example, a semi-insulating GaAs substrate, not shown. An n-type GaAs layer 2, a semi-insulating GaAs layer 3 and an n-type GaAs layer 4 are formed sequentially in that order on each of the supports la and 1b. The n-type GaAs layer 2, the semi-insulating GaAs layer 3 and the n-type GaAs layer 4 formed on the support la, and those formed on the support 1b form projections projecting from the respective opposite side surfaces thereof toward each other. The projection projecting from the n-type GaAs layer 2, the semi-insulating GaAs layer 3 and the n-type GaAs layer 4 formed on the support 1a is an emitter 5, and the projection projecting from those formed on the support 1b is a collector 6. The emitter 5 and the collector 6 have the shape of, for example, a quadrangular prism, and their center axes are in alignment with each other. The size of the cross section of each of the emitter 5 and the collector 6 is, for example, about 5000 Å × about 5000 Å. A gate electrode 7 is extended perpendicularly to a straight line connecting the emitter 5 and the collector 6. The gate electrode 7 has a narrower middle portion, and wider opposite ends. The gate electrode 7 is supported in suspension at its opposite ends on supports, not shown. The gate electrode 7 is symmetrical with respect to the straight line connecting the emitter 5 and the collector 6. The gate electrode 7 has a parallel flat capacitor construction consisting of an n-type GaAs layer 2, a semi-insulating GaAs layer 3 and an n-type GaAs layer 4. The conductive n-type GaAs layers 2 and 4 serves as electrodes. The surfaces of the n-type GaAs layers 2 and 4 serving as electrodes are parallel to the straight line connecting the emitter 5 and the collector 6. The emitter 5 and the collector 6 have tips having the shape of, for example, a quadrangular pyramid and formed of a semi-insulating GaAs layer 8. The sharp points of the tips of semi-insulating GaAs layers 8 of the emitter 5 and the collector 6 are opposite to each other. Semi-insulating GaAs layers 8 are formed on the opposite sides of the gate electrode 7. The operation of the quantum phase interference transistor thus constructed will be described hereinafter. In this quantum phase interference transistor, the potential of the collector 6 is higher than that of the emitter 5. Suppose that the respective potentials of the n-type GaAs layer 2 and the n-type GaAs layer 4 of the gate electrode 7, i.e., the electrodes of a parallel flat capacitor, are V 1 and V 2 , and the mean of the potentials V 1 and V 2 , i.e., (V 1 + V 2 )/2, is negative relative to the potential of the emitter 5. Then, the gate electrode 7 acts as a blocker to electron waves emitted from the emitter 5 into a vacuum. Consequently, the electron waves emitted into a vacuum by field emission from the emitter 5 are divided into an electron wave traveling over the gate electrode 7 to the collector 6 and an electron wave traveling under the gate electrode 7 to the collector 6, as viewed in Figs. 1 and 2. The phase difference between the two electron waves is dependent on the difference between the respective potentials V 1 and V 2 of the n-type GaAs layer 2 and the n-type GaAs layer 4, i.e., the electrodes of the parallel flat capacitor forming the gate electrode 7. Therefore, interference between the two electron waves on the collector 6 is controlled by controlling the phase difference between the two electron waves by the difference between the potentials V 1 and V 2 . Thus, the quantum-mechanical transition probability of the electrons traveling from the emitter 5 to the collector 6 is modulated for transistor action. A method of fabricating the quantum phase interference transistor in the first embodiment according to the present invention will be described hereinafter. First an etching process employed in the method will be described. In etching, for example, a GaAs substrate by a dry etching process, such as a reactive ion etching process, using an etching gas, such as CCl 2 F 2 , the GaAs substrate is etched in a direction perpendicular to its surface when the etching gas is supplied at a relatively low flow rate, and then the GaAs substrate is etched laterally when the flow rate of the etching gas is increased. The rate of lateral etching is dependent on crystal orientation. Figs. 3A to 3C show steps of forming a stripe extending along the direction of [1 1 0] on a (0 0 1) semi-insulating GaAs substrate 21 by a dry etching process. As shown in Fig. 3A, in forming the stripe on the semi-insulating GaAs substrate 21 by a dry etching process using a mask, not shown, the semi-insulating GaAs substrate 21 is etched in a direction perpendicular to its surface in both directions [1 1 0] and [1 -1 0] while the flow rate of the etching gas is relatively low, so that a stripe 21a is formed. When the flow rate of the etching gas is increased for successive dry etching, the etching rate with respect to the direction [1 -1 0] is higher than the etching rate with respect to the direction [1 1 0] and, consequently, the side surfaces of the stripe 21a are etched laterally as shown in Fig. 3B. When the etching process is continued further, the stripe 21a is separated from the semi-insulating GaAs substrate 21 as shown in Fig. 3C. The backside of the stripe 21a extending in the direction [1 1 0] is formed of Ga, and the surface formed of Ga is hard to etch. Thus, the etching rate for the stripe 21a extending in the direction [1 1 0] is different from the etching rate for a stripe extending in the direction [1 -1 0]. Therefore, when the straight line connecting the emitter 5 and the collector 6 of the quantum phase interference transistor shown in Figs. 1 and 2 extends in the direction [1 1 0] and the gate electrode 7 extends in the direction [1 -1 0], i.e., the direction perpendicular to the direction [1 1 0], the gate electrode 7 is formed in a thickness smaller than that of the emitter 5 and the collector 6. Accordingly, the symmetry of the gate electrode with respect to the straight line connecting the emitter 5 and the collector 6 is deteriorated, and hence the symmetry of the path of electrons traveling over the gate electrode 7 and the path of electrons traveling under the gate electrode 7 is deteriorated. Consequently, the interference between the electron wave traveling over the gate electrode 7 and the electron wave traveling under the gate electrode 7 is deteriorated and, consequently, the modulation efficiency of the gate electrode 7 is deteriorated. Accordingly, the method of fabricating the quantum phase interference transistor in the first embodiment forms the emitter 5 and the collector 6 on the (0 0 1) semi-insulating GaAs substrate so that the straight line connecting the emitter 5 and the collector 6 extends in the direction [1 0 0], and the gate electrode 7 extends in the direction [0 1 0] perpendicular to the straight line. Thus, the gate electrode 7 can be formed symmetrically with respect to the straight line connecting the emitter 5 and the collector 6. It is also possible to form the emitter 5 and the collector 6 so that the straight line connecting the emitter 5 and the collector 6 extends in the direction [0 1 0] and the gate electrode 7 extends in the direction [1 0 0]. Referring to Fig. 4A, an n-type GaAs layer 2, a semi-insulating GaAs layer 3 and an n-type GaAs layer 4 are formed sequentially in that order on a semi-insulating GaAs substrate 1 by epitaxial growth by, for example, a metal organic chemical vapor deposition process (MOCVD process). Then, a mask, such as an aluminum film, having a pattern corresponding to an emitter, a collector and a gate electrode to be formed is formed over the n-type GaAs layer 4. Then, the work, namely, the semi-insulating GaAs substrate 1 coated with the laminate layer of the n-type GaAs layer 2, the semi-insulating GaAs layer 3 and the n-type GaAs layer 4, coated with the mask 9, is subjected to, for example, a RIE process for dry etching to form a stripe corresponding to a gate electrode 7 as shown in Fig. 4B. Then, the flow rate of the etching gas is increased for further dry etching to etch the lower portion of the stripe laterally as shown in Fig. 4C. The RIE process is continued further until the gate electrode 7 supported in suspension at its opposite ends, and the emitter 5 and the collector 6 projecting toward each other respectively from the supports 1a and 1b are formed. Thus, the gate electrode 7 is symmetrical with respect to a straight line connecting the emitter 5 and the collector 6. Then, the mask 9 is removed. Then, semi-insulating GaAs layers 8 are formed on the respective tips of the emitter 5 and the collector 6 and on the opposite side surfaces of the gate electrode 7 as shown in Figs. 1 and 2 by epitaxial growth by , for example, a MOCVD process. The semi-insulating GaAs layers 8 are formed in the shape of a quadrangular pyramid on the tips of the emitter 5 and the collector 6. Thus the quantum phase interference transistor is completed. Since the gate electrode 7 has the construction of a parallel flat capacitor, the potentials of spaces over and under, respectively, of the gate electrode 7 are fixed and hence there is no potential difference between the paths of electrons traveling over and under the gate electrode 7. Accordingly, the efficiency of modulation of the quantum-mechanical transition probability of electrons from the emitter 5 to the collector 6 is sufficiently high. Furthermore, since electrons travel through a vacuum in the quantum phase interference transistor in the first embodiment, the quantum phase interference transistor is capable of operating at a room temperature. Still further, since the gate electrode 7 is symmetrical with respect to the straight line connecting the emitter 5 and the collector 6, the path of electrons traveling over the gate electrode 7 and the path of electrons traveling under the gate electrode 7 are satisfactorily symmetrical. Accordingly, the interference between the electron wave traveling over the gate electrode 7 and the electron wave traveling under the gate electrode 7 is satisfactory. Thus, the gate electrode 7 further enhances the modulation efficiency. Incidentally, the quantum phase interference transistor in the first embodiment controls the phase difference between the electron waves traveling over and under, respectively, the gate electrode 7 by the potential difference between the electrodes of the parallel flat capacitor forming the gate electrode 7 to modulate the quantum-mechanical transition probability of electrons traveling from the emitter 5 to the collector 6. However, a relatively long time is necessary for charging the parallel flat capacitor forming the gate electrode 7 and hence, in some cases, the quantum phase interference transistor is unable to operate at a sufficiently high operating speed. This problem can be solved by utilizing the finite resistance R of the semi-insulating GaAs layer 3 formed between the electrodes of the gate electrode 7. The n-type GaAs layer 2 and the n-type GaAs layer 4 of the gate electrode 7 is connected by a circuit including a switch S as shown in Fig. 5. When the movable contact of the switch S is connected to a contact B, no current flows between the n-type GaAs layers 2 and 4 of the gate electrode 7 and hence there is no potential difference between the n-type GaAs layers 2 and 4. When the movable contact of the switch S is connected to a contact A, a current I flows from the n-type GaAs layer 4 to the n-type GaAs layer 2 and thereby the potential difference IR is created between the n-type GaAs layers 2 and 4. The phase difference between the electron wave traveling over the gate electrode 7 and the electron wave traveling under the gate electrode 7 is controlled by this potential difference IR. The time required for the potential difference between the opposite sides of the semi-insulating GaAs layer acting as a resistor to reach a fixed potential difference is far shorter than the time necessary for charging the capacitor, so that modulation by the gate electrode 7 can be achieved rapidly. Thus, the gate electrode 7 having the construction of a parallel flat capacitor ensures a high modulation efficiency to enable the quantum phase interference transistor to operate at a high operating speed. Fig. 6 is a perspective view of an example of a quantum phase interference transistor, Fig. 7 is a sectional view taken on line 9-9 in Fig. 6, and Fig. 8 is an enlarged fragmentary sectional view taken on line 10-10 in Fig. 6. Referring to Figs. 6, 7 and 8, the quantum phase interference transistor has an emitter 35, a collector 36 and a gate electrode 37. A portion of the gate electrode 37 lying between the emitter 35 and the collector 36 is formed of, for example, a semi-insulating GaAs layer 38. The size of the sectional area of the semi-insulating GaAs layer 38 decreases gradually toward the intersection of a straight line connecting the emitter 35 and the collector 36 and the longitudinal center axis of the gate electrode 37, and the semi-insulating GaAs layer 38 is divided at the intersection into two parts lying with their tips having the shape of a quadrangular pyramid facing opposite to each other. The quantum phase interference transistor of this example is the same in the rest of details of construction as the quantum phase interference transistor in the first embodiment. A method of fabricating the quantum phase interference transistor of the foregoing example will be described hereinafter. First a structure as shown in Fig. 9 is formed by an etching process similar to that employed in fabricating the quantum phase interference transistor in the first embodiment. The size of the cross section of a pair of projections forming the emitter 35 and the collector 36 may be, for example, about 5000 Å × about 5000 Å, and the interval between the tips of the pair of projections may be on the order of 8000 Å. Then, a semi-insulating GaAs layer is formed over the entire surface by epitaxial growth by, for example, a MOCVD process. Semi-insulating GaAs layers 38 are formed on the tips of the pair of projections in the shape of a quadrangular pyramid by the MOCVD process. The height of the semi-insulating GaAs layers 38 formed in the shape of a quadrangular pyramid on the tips of the projections is, for example, on the order of 2500 Å. Semi-insulating GaAs layers 38 are formed likewise on the opposite tips of projections for the gate electrode 37 and, finally, the semi-insulating GaAs layers 38 become continuous Thus, a portion of the gate electrode 37 formed between the emitter 35 and the collector 36 is formed of the semi-insulating GaAs layer 38 as shown in Figs. 6, 7 and 8. The size of the cross section of the narrowest portion of the semi-insulating GaAs layer 38 is determined selectively by selectively determining the time for epitaxial growth. When the epitaxial growth of the semi-insulating GaAs is continued over a predetermined time, a semi-insulating GaAs layer 38 is formed on the tip of the projection forming the emitter 35 as shown in Fig. 10. The side surfaces of the semi-insulating GaAs layer 38 formed in the shape of a quadrangular pyramid on the tip of the projection for the emitter 35 are (1 -1 1) faces and (1 -1 -1) faces, and the side surfaces of the semi-insulating GaAs layer 38 formed over the side surfaces of the projection are (0 -1 1) faces and (0 -1 -1) faces. The angle of the tip of the semi-insulating GaAs layer 38 formed on the tip of the projection in the shape of a quadrangular pyramid is about 90° with respect to the direction of the center axis of the projection, namely, the direction [1 0 0]. The same conditions apply to the semi-insulating GaAs layer 38 formed on the projection for the collector 36. In the quantum phase interference transistor in this example, a current is supplied, for example, from the n-type GaAs layer 34 through the semi-insulating GaAs layer 38 having a finite resistance to the n-type GaAs layer 32 as indicated by an arrow in Fig. 10 to create a potential difference between the n-type GaAs layer 34 and the n-type GaAs layer 32. The phase difference between the electron wave traveling over the gate electrode 37 and the electron wave traveling under the gate electrode 37 can be controlled by the phase difference. Since the portion of the gate electrode 37 lying between the emitter 35 and the collector 36 can be formed in a cross section having a relatively small size, the emitter 35 and the collector 36 can be formed with a relatively small interval on the order of several thousands angstroms therebetween; consequently, the interference between the electron wave traveling over the gate electrode 37 and the electron wave traveling under the gate electrode 37 can be enhanced, the modulation efficiency of the gate electrode 37 can be enhanced, the rate of collection of electrons emitted from the emitter 35 by the collector 36 can be increased and hence the current flowing between the emitter 35 and the collector 36 can be increased. Furthermore, since the interval between the emitter 35 and the collector 36 is reduced, the voltage applied across the emitter 35 and the collector 36 can be reduced accordingly, and hence the quantum phase interference transistor is able to operate at reduced power consumption. In the first embodiment, either or both of the n-type GaAs layers forming the electrodes of the parallel flat capacitor may be formed of a p-type GaAs layer, and the semi-insulating GaAs layer formed between the electrodes of the parallel flat capacitor forming the gate electrode may be formed of a substance having a finite resistance other than the semi-insulating GaAs. A quantum phase interference transistor in a second embodiment according to the present invention will be described hereinafter. Fig. 11 is a perspective view of the quantum phase interference transistor in the second embodiment according to the present invention, and Fig. 12 is a sectional view taken on line 2-2 in Fig. 11. Referring to Figs. 11 and 12, the quantum phase interference transistor in this embodiment has an emitter 51 having the shape of a quadrangular prism with a pointed tip having the shape of a quadrangular pyramid, and a collector 52 having the shape of a quadrangular prism with a pointed tip having the shape of a quadrangular pyramid. The emitter 51 and the collector 52 are formed on a substrate, such as a semi-insulating GaAs substrate, not shown, with their tips facing each other and with their center axes in alignment with each other. The emitter 51 and the collector 52 are formed of, for example, GaAs. The size of the emitter 51 and the collector 52 is, for example, about 0.5 µm × about 0.5 µm. A gate electrode 53 is supported at its opposite ends on supports, not shown, in suspension. The middle portion of the gate electrode 53 corresponding to the emitter 51 and the collector 52 is perpendicular to a line connecting the emitter 51 and the collector 52. The end portions of the gate electrode 53 on the opposite sides of the middle portion are bent toward the collector 52. the gate electrode 53 has a laminate construction, similar to the construction of a parallel flat capacitor, consisting of, for example, an n-type GaAs layer 54, a semi-insulating GaAs layer 55 and an n-type GaAs layer 56. The n-type GaAs layer 54 and the n-type GaAs layer 56 serve as electrodes. The n-type GaAs layer 54, the semi-insulating GaAs layer 55 and the n-type GaAs layer 56 are parallel to the line connecting the emitter 51 and the collector 52. The width of the gate electrode 53 along the line connecting the emitter 51 and the collector 52 is, for example, on the order of 0.5 µm. In this embodiment, a pulling-out electrode 57 is formed between the emitter 51 and the gate electrode 53. The middle portion of the pulling-out electrode 57 corresponding to the emitter 51 and the collector 52 is perpendicular to the line connecting the emitter 51 and the collector 52 and parallel to the gate electrode 53. The end portions on the opposite sides of the middle portion of the pulling-out electrode 57 consists of a lower pulling-out electrode 57a and an upper pulling-out electrode 57b, which are spaced by an opening. The width of the upper pulling-out electrode 57b and the lower pulling-out electrode 57a along the line connecting the emitter 51 and the collector 52 is, for example, on the order of 0.5 µm. The operation of the quantum phase interference transistor thus constructed will be described hereinafter. A voltage is applied across the emitter 51 and the collector 52 of the quantum phase interference transistor so that the potential of the collector 52 is higher than that of the emitter 51. A voltage high enough to obtain field emission from the emitter 51 is applied across the emitter 51 and the pulling-out electrode 57 so that the potential of the pulling-out electrode 57 is higher than that of the emitter 51, namely, so that the pulling-out electrode 57 is biased positively relative to the emitter 51. Thus, the emitter 51 emits electron waves, and the lower pulling-out electrode 57a and the upper pulling-out electrode 57b biased positively relative to the emitter 51 divides electron waves into an electron wave that travels over the gate electrode 53 to the collector 52 and an electron wave that travels under the gate electrode 53 to the collector 52 as shown in Figs. 11 and 12. The phase difference between the two electron waves is dependent on the difference between the potential V 1 of the n-type GaAs layer 54 of the gate electrode 53 and the potential V 2 of the n-type GaAs layer 56 of the gate electrode 53. The difference between the potentials V 1 and V 2 is controlled to control the interference between the two electron waves through the control of the phase difference between the two electron waves. thus, the quantum-mechanical transition probability of the electrons traveling from the emitter 51 to the collector 52 is modulated for transistor operation. A method of fabricating the quantum phase interference transistor in this embodiment thus constructed will be described hereinafter with reference to sectional views taken on line 52-52 in Fig. 11. First, as shown in Fig. 13A, an n-type GaAs layer 72 is formed in a shape corresponding to that of the pulling-out electrode 57 on, for example, a semi-insulating GaAs substrate 71. The n-type GaAs layer 72 is formed, for example, by forming an epitaxial n-type GaAs layer over the entire surface of the semi-insulating GaAs substrate 71 by a metal organic chemical deposition process (MOCVD process), and by etching the n-type GaAs layer in a desired pattern. Then, a resist film 73 having an aperture 73a corresponding to an area in which the gate electrode 63 and the pulling-out electrode 67 are to be formed is formed by lithography, and a SiO 2 film 74 is formed in the aperture 73a of the resist film 73. Then, the resist film 73 is removed and a resist film 75 having an aperture 75a corresponding to an area in which the gate electrode 63 is to be formed is formed as shown in Fig. 13B. Then, the SiO 2 film 74 is etched perpendicularly to the surface of the substrate by, for example, a reactive ion etching process (RIE process), using the resist film 75 as a mask to remove the SiO 2 film partially as shown in Fig. 13C. The surface of the etched portion of the SiO 2 film 74 is flush with the lower surface of the gate electrode 63. Subsequently, the resist film 75 is removed, an n-type GaAs layer 64, a semi-insulating GaAs layer 65 and an n-type GaAs layer 66 are formed sequentially by an epitaxial growth process, and then the surface of the work is coated entirely with, for example, a SiO 2 film 76 as shown in Fig. 13D. Then, as shown in Fig. 13E, a resist film 77 is formed over the SiO 2 film 76 in a pattern corresponding to the shape of the gate electrode 63. Then, the resist film 76 is etched perpendicularly to the surface of the substrate, using the resist film 77 as a mask to remove the SiO 2 film 76 partially as shown in Fig. 13F. Then, the resist film 77 is removed and a resist film 78 is formed in a pattern corresponding to the shapes of the gate electrode 63 and the pulling-out electrode 67 as shown in Fig. 13G. Then, the SiO 2 film is etched perpendicularly to the surface of the substrate, using the resist film 78 as a mask to remove the SiO 2 film partially as shown in Fig. 13H. Subsequently, the resist film 78 is removed and an n-type GaAs layer 79 is formed by an epitaxial growth process so that the upper surface of the n-type GaAs layer 79 is flush with the pulling-out electrode 67 as shown in Fig. 13I. Then, a resist film, not shown, is formed over the n-type GaAs layer 79 and the SiO 2 film 76 in a pattern corresponding to the gate electrode 63 and the pulling-out electrode 67, and the n-type GaAs layer 79 is etched perpendicularly to the surface of the substrate to remove the n-type GaAs layer 79 partially, using the resist film as a mask. Then, the resist film is removed to obtain a work in a state as shown in Fig. 13J. Then, the SiO 2 films 74 and 76 are removed by a wet etching process to form the gate electrode and the pulling-out electrode as shown in Figs. 11 and 12. The emitter 61 and the collector 62 are formed either before or after forming the gate electrode 63 and the pulling-out electrode 67. The emitter 61 and the collector 62 are formed by forming a pair of protrusions having the shape of a quadrangular prism opposite to each other, and forming tip portions having the shape of a quadrangular pyramid on the opposite ends of the pair or protrusions, respectively, by an epitaxial growth process. In the quantum phase interference transistor in this embodiment, the lower pulling-out electrode 67a and the upper pulling-out electrode 67b formed between the emitter 61 and the gate electrode 63 make the emitter 61 emit electron waves and divide the electron waves into an electron wave traveling over the gate electrode 63 and an electron wave traveling under the gate electrode 63. Accordingly, the quantum phase interference transistor need not be provided with a negatively biased blocker for diving electron waves emitted by the emitter 61 into two electron waves, and hence the reduction of the intensity of the electric field in the vicinity of the emitter 61 can be obviated. Therefore, electrons are easy to be emitted from the emitter 61. Furthermore, since the emitter 61 and the pulling-out electrode 57 can be formed so that the distance therebetween is as small as, for example, about 1500 Å by the combined application of dry etching techniques and epitaxial growth techniques and hence it is possible to make the emitter 61 emit electrons by field emission by applying a relatively low voltage across the emitter 61 and the pulling-out electrode 57. Since the gate electrode 63 has the construction of a parallel flat capacitor, the respective potentials of the upper and lower sides of the gate electrode 63 can be held constant. therefore, there is no potential difference between the electron path extending over the gate electrode 63 and one electron path extending under the gate electrode 63 and the quantum-mechanical transistion probability modulation efficiency is sufficiently high. Since the gate electrode 63 can be formed in a very small thickness, the curvature of the electron paths extending between the emitter 61 and the collector 62 is not very large. Therefore, the collector 62 is able to collect the electrons emitted from the emitter 61 at a comparatively high collecting efficiency. Since the electrons travel through a vacuum the quantum phase interference transistor in this embodiment is able to operate at a room temperature. The gate electrode 63 having the construction of a parallel flat capacitor may be substituted by a gate electrode of a construction other than the construction of a parallel flat capacitor. Thus, the pulling-out electrode is disposed between the emitter and the gate electrode to make the emitter emit electron waves and to divide the electron waves into a plurality of electron waves. Accordingly, the quantum phase interference transistor is capable of operating at a room temperature and electrons are easy to be emitted from the emitter. A quantum phase interference transistor in a third embodiment according to the present invention will be described hereinafter Referring to Fig. 14, the quantum phase interference transistor in the third embodiment according to the present invention has an emitter 81 having the shape of, for example, a quadrangular prism with a tip having the shape of a quadrangular pyramid formed on, for example, a semi-insulating GaAs substrate, not shown. A portion having the shape of the quadrangular prism of the emitter 81 has a cross section of, for example, about 0.5 µm × about 0.5 µm. A collector 82 is formed opposite to the emitter 81. The collector 82 is a fine metal line of a thin metal film having a sufficiently small thickness and a small width. Indicated at 83 is an insulating film, such as a SiO 2 film, and at 84 and 85 are external electrodes. A gate electrode 86 and a blocker 87 are formed between the emitter 81 and the collector 82. The gate electrode 86 and the blocker 87 are supported at their opposite ends on supports, not shown, so that their middle portions are in suspension. Portions of the gate electrode 86 and the blocker 87 extending between the emitter 81 and the collector 82 are perpendicular to a line connecting the emitter 81 and the collector 82. The gate electrode 86 has the laminate construction of a parallel flat capacitor consisting of, for example, an n-type GaAs layer 86a, a semi-insulating GaAs layer 86b and an n-type GaAs layer 86c. The n-type GaAs layer 86a and the n-type GaAs layer 86c serve as electrodes. The n-type GaAs layer 86a and the n-type GaAs layer 86c, i.e., the electrodes, are parallel to the line connecting the emitter 81 and the collector 82. The width of the gate electrode 86 along the line connecting the emitter 81 and the collector 82 is, for example, on the order of 0.5 µm. The operation of the quantum phase interference transistor thus constructed will be described hereinafter. Suppose that the respective potentials of the n-type GaAs layer 86a and the n-type GaAs layer 86c of the gate electrode 86, i.e., the electrodes of a parallel flat capacitor, of the quantum phase interference transistor in this embodiment are V 1 and V 2 , and the mean of the potentials V 1 and V 2 , i.e., (V 1 + V 2 )/2, relative to the emitter 81 is high enough to make the emitter 81 emit electrons by field emission. Thus, the emitter 81 emits electrons. When the potential difference between the emitter 81 and the gate electrode 86 is V. then, electrons emitted from the emitter 81 have kinetic energy of e V, where e is the absolute value of the charge of electrons. The blocker 87 is biased negatively relative to the emitter 81. Then, electron waves emitted from the emitter 81 are divided into an electron wave traveling over the blocker 87 and an electron wave traveling under the blocker 87, as viewed in Fig. 14, by the blocker 87. When the potential of the collector 82 is lower than the potential V of the gate electrode 86 by ΔV, the electrons emitted from the emitter 81 are decelerated and hence the kinetic energy of the electrons is reduced accordingly to e(V - ΔV). The potentials of the external electrodes 84 and 85 are lower than that of the collector 82 and, consequently, the electrons traveling over and under the gate electrode 86 are subjected to force acting in directions indicated by arrows in Fig. 14, so that the electrons are collected efficiently by the collector 82. The phase difference between the electron waves divided by the blocker 87 is controlled by the gate electrode 86 for transistor action. A method of fabricating the quantum phase interference transistor in this embodiment will be described hereinafter. The emitter 81, the gate electrode 86 and the blocker 87 can be formed by an epitaxial growth process or a dry etching process. The collector 82 and the external electrodes 84 and 85 can be formed by the following process. Referring to Fig. 15, a metal thin film is formed on a substrate 91, such as a semi-insulating GaAs substrate, by a vacuum evaporation process or a sputtering process, and then the metal thin film is etched in a predetermined pattern to form the lower external electrode 84. Then, a resist film 92 of a predetermined pattern is formed by lithography, and an insulating layer 83 is formed in an opening in the resist film 92. After forming a metal thin film over the insulating layer 83, the metal thin film is etched in a predetermined pattern to form the collector 82. After forming another insulating layer 83 over the collector 82, the upper external electrode 85 is formed on the insulating layer 83 by the foregoing method. Then, the resist film 92 is removed and the insulating layer 83 is etched lightly by an wet etching process. Of the insulating film 83 is a SiO 2 film, a hydrofluoric acid etching liquid is used. Thus, the quantum phase interference transistor as shown in Fig. 14 is fabricated. As stated above, since the electrons emitted from the emitter 81 are decelerated before the electrons reach the collector 82, the kinetic energy of the electrons on the collector 82 is lower than the kinetic energy of the same immediately after being emitted from the emitter 81 and hence the wavelength of the electron waves can be increased accordingly. Furthermore, since the collector 82 is a metal thin film, the collector 82 can be formed in a very small width in a plane including the path of electrons between the emitter 81 and the collector 82 on the order of several tens angstroms. Accordingly, only one maximum in an interference pattern produced by the interference between the electron wave traveling over the gate electrode 86 to the collector 82 and the electron wave traveling under the gate electrode 86 can be measured by the collector 82, and the variation of the interference pattern of the electron waves caused by phase control can efficiently be used as the variation of collector current. Since the gate electrode 86 has the construction of a parallel flat capacitor, the potentials of spaces over and under the gate electrode 86 can be maintained constant. Therefore, there is no potential difference between the electron paths respectively extending over and under the gate electrode 86 and hence the efficiency of modulation of the quantum-mechanical transition probability of electrons traveling from the emitter 81 to the collector 82 is satisfactorily high. Furthermore, since the gate electrode 86 can be formed in a very small thickness, the curvature of the electron paths between the emitter 81 and the collector 82 need not be very large and hence the electrons emitted from the emitter 81 can be collected at a high collection efficiency by the collector 82. Still further, since electrons travel through a vacuum, the quantum phase interference transistor in this embodiment is capable of operating at a room temperature. The collector 82 formed of a metal thin film may be substituted by a collector formed of a thin film of a conductive material other than the metal. The gate electrode 86 need not necessarily of the construction of a parallel flat capacitor. A quantum phase interference transistor in a fourth embodiment according to the present invention will be described hereinafter. Fig. 16 is a perspective view of the quantum phase interference transistor in this embodiment, and Fig. 17 is a sectional view taken on line 102-102 in Fig. 16. Referring to Figs. 16 and 17, the quantum phase interference transistor in this embodiment has an emitter 101 and a collector 102 formed opposite to each other on a substrate, not shown. The emitter 101 and the collector 102 have the shape of, for example, a quadrangular prism having a point having the shape of a quadrangular pyramid. The emitter 101 and the collector 102 may be formed of a conductive material, such as a semiconductor or a metal. A portion having the shape of a quadrangular prism of each of the emitter 101 and the collector 102 has a cross section of, for example, about 0.5 µm × 0.5 µm. Seven parallel flat capacitors C1 to C7 are arranged in parallel to each other between the emitter 101 and the collector 102 with their lengths perpendicular to a line connecting the emitter 101 and the collector 102. Indicated at 103 and 104 are the electrodes of the parallel flat capacitors C1 to C7. The electrodes 103 and 104 are supported at their opposite ends on supports, not shown, so that the electrodes 103 and 104 are in suspension. The electrodes 103 and 104 are formed of, for example, aluminum (Al). The widths of the parallel flat capacitors C1 to C7 and intervals between the same with respect to a direction along the line connecting the emitter 101 and the collector 102 are, for example, on the order of several hundreds angstroms. The parallel flat capacitors C1 to C7 inclusively serve as a gate electrode, in which, for example, the parallel flat capacitor C1 serves as a blocker, and the parallel flat capacitor C2 serves as a pulling-out electrode. The respective potentials V Cm (lower) and V Cm (upper of the electrodes 103 and 104 of the parallel flat capacitors C1 to C7 (hereinafter represented by Cm, where m = 1 to 7) are determined so as to meet the following conditions. A predetermined voltage is applied across the emitter 101 and the collector 102 so that the potential of the collector 102 is higher than that of the emitter 101. The electrodes 103 and 104 of the parallel flat capacitors C1 and C2, i.e., the blocker and the pulling-out electrode, are equipotential, namely, V C1 (lower) = V C1 (upper) and V C2 (lower) = V C2 (upper), to make the emitter 101 emit electrons. The values of V C1 (lower) = V C1 (upper) and V C2 (lower) = V C2 (upper) are determined so that electron waves emitted from the emitter 102 are divided into an electron wave traveling over the parallel flat capacitor C1 and an electron wave traveling under the parallel flat capacitor C1 as viewed in Figs. 16 and 17, and the electron waves converge satisfactorily on the collector 102. In this state, no voltage is applied across the electrodes 103 and 104 of the other parallel flat capacitors C3 to C7. After thus determining the potentials of the electrodes 103 and 104 of the parallel flat capacitors C1 and C2, the potentials of the other five parallel flat capacitors C3 to C7 are determined so that the potential distribution between the emitter 101 and the collector 102 is not disturbed, and the electrodes 103 and 104 of the parallel capacitors C3 to C7 are equipotential, namely, V Cm (lower) = V Cm (upper) (m = 3 to 7). In this state, potentials of the electrodes 103 and 104 of the parallel flat capacitors C1 to C7 are changed, for example, V Cm (lower) → V Cm (lower) -ΔV/2, and V Cm (upper) → V Cm (upper) + ΔV/2 (m = 1 to 7). Then, the potential difference between the electrodes 103 and 104 of the parallel flat capacitors C1 to C7 is ΔV. Consequently, a phase difference according to the potential difference ΔV appears between the electron waves respectively traveling over and under the parallel flat capacitors C1 to C7. The potential difference ΔV is varied to control the phase difference between the electron waves for transistor action. As mentioned above, the average potentials of the electrodes 103 and 104 of the parallel flat capacitors C1 to C7 are maintained at the optimum potentials even if the potential V Cm (upper) and V Cm (lower) are changed respectively by ±ΔV. A method of fabricating the quantum phase interference transistor in this embodiment will be described hereinafter. First, the emitter 101 and the collector 102 are formed by an epitaxial growth process or a dry etching process, and then the parallel flat capacitors C1 to C7 are formed by the following processes. Referring to Fig. 18, a SiO 2 film 105, an Al film 106, A SiO 2 film 107 and an Al film 108, for instance, are formed sequentially in that order on a substrate, not shown. The SiO 2 films 105 and 107 may be formed by a CVD process or a sputtering process. The substrate is placed in the evacuated chamber of an electron beam irradiation system, not shown, and then a source gas, such as alkylnaphthalene gas, is supplied into the evacuated chamber. Molecules of the source gas are adsorbed by the Al film 108. Then, the surface of the Al film 108 is irradiated with a very narrow electron beam in a pattern corresponding to the pattern of the parallel flat capacitors C1 to C7 in the atmosphere of the source gas. Portions of the molecules of the source gas on the Al film 108 irradiated with the electron beam are decomposed to form a resist film 109 of an amorphous hydrocarbon in a pattern corresponding to the pattern of the parallel flat capacitors C1 to C7. Such a resist produced by irradiation with an electron beam is called an EBIR (electron beam induced resist), which is highly resistant to dry etching. Then, the Al film 108, the SiO 2 film 107 and the Al film 106 are etched sequentially by, for example, a reactive ion etching process (RIE process) using the resist film 109 as a mask, and then the resist film 109 is removed. Then, the SiO 2 films 105 and 107 are etched by wet etching using, for example, a hydrofluoric acid etching liquid. Thus, the parallel flat capacitors C1 to C7 supported in suspension at their opposite ends are formed to complete the quantum phase interference transistor. The quantum phase interference transistor in this embodiment makes electrons converge satisfactorily on the collector 102 by optimizing the potentials of the electrodes 103 and 104 of the parallel flat capacitors C1 to C7 and thereby the current that flows between the emitter 101 and the collector 102 can be increased. The use of the parallel flat capacitors C1 to C7 as a gate electrode increases the efficiency of the modulation of the quantum-mechanical transition probability of electrons traveling from the emitter 101 to the collector 102 to a satisfactory extent. Furthermore, the quantum phase interference transistor in this embodiment is capable of operating at a room temperature because the electrons travel through a vacuum. Since the parallel flat capacitors C1 to C7 can be formed in a very small thickness, the curvature of paths along which the electrons travel from the emitter 101 to the collector 102 need not be very large and hence the electrons emitted from the emitter 101 can be collected at a high collection efficiency. Although the quantum phase interference transistor in this embodiment is provided with the seven parallel flat capacitors C1 to C7 between the emitter 101 and the collector 102, a quantum phase interference transistor in accordance with the present invention may be provided with any optional number of parallel flat capacitors and the number of parallel flat capacitors may be determined as occasion demands. However, in general, it is preferable that the quantum phase interference transistor is provided with a greater number of parallel flat capacitors to optimize the potential distribution between the emitter 101 and the collector 102, and it is preferable to arrange parallel flat capacitors of smaller width at smaller intervals. Although the quantum phase interference transistor in this embodiment uses the parallel flat capacitors C1 and C2 among the parallel flat capacitors C1 to C7 respectively as a blocker and a pulling-out electrode, it is possible to determined the uses of the parallel flat capacitors C1 to C7 as occasion demands; for example, it is possible to use the parallel flat capacitors C1 and C2 as blockers, and to use the parallel flat capacitors C3 and C4 as pulling-out electrodes. Furthermore, although the electrodes 103 and 104 of the parallel flat capacitors C1 to C7 are formed of aluminum, naturally, the electrodes 103 and 104 may be formed of a nonmetallic conductive material or a metal other than aluminum. As is apparent from the foregoing description, the quantum phase interference transistor in accordance with the fourth embodiment of the present invention is provided with the plurality of parallel flat capacitors in a parallel arrangement between the emitter and the collector, and hence the quantum phase interference transistor is capable of operating at a room temperature at a high modulation efficiency, and improves the convergence of electrons on the collector to increase the current flowing between the emitter and the collector.

Claims: A quantum phase interference transistor comprising: an emitter (5; 35; 51; 81; 101) for emitting electron waves into vacuum; a collector (6; 36; 52; 82; 102) for collecting said electron waves; a gate electrode (7; 37; 53; 86; 103, 104) arranged between said emitter and said collector, said gate electrode controlling the phase difference between an electron wave travelling over the gate electrode and an electron wave travelling under the gate electrode, said gate electrode having the construction of a capacitor including an upper and a lower capacitor electrode. The quantum phase interference transistor of claim 1, further comprising a pulling out electrode (57; C2) disposed between the emitter (51; 101) and the gate electrode (53; C3 to C7) to make the emitter emit the electron wave and to divide the electron wave into upper and lower electron waves. The quantum phase interference transistor of claim 1, further comprising a blocker electrode (87; C1) formed between the emitter (81; 101) and the collector (82; 102). The quantum phase interference transistor of claim 1 or claim 3, characterized in that the collector (82) is formed of a thin film. The quantum phase interference transistor of claim 1 or claim 3 or claim 4, characterized in that the potential of the collector is lower than the potential of the gate electrode. The quantum phase interference transistor of claim 1 or claim 2 or claim 3, characterized in that the gate electrode (103, 104) comprises a plurality of parallel flat capacitors (C1 to C7).

Inventors: ISHIBASHI AKIRA, UGAJIN RYUICHI, ISHIBASHI, AKIRA, UGAJIN, RYUICHI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H01L29
IPC codes: H01J3, H03K17, H01J21, H01L29