Source-coupled oscillator

Abstract: An oscillator, comprising a first (1) and a second (2) transistor of which the sources are interconnected through a capacitor (20) and of which each gate is connected to the drain of the other transistor, whereas each drain is connected to a load circuit, for example, in the form of a resistor, presents a non-linear transfer. By arranging each load circuit in the form of a parallel combination of two transistors (3,4,5,6) of which a first gate is connected to the drain of the first transistor and of which a second gate is connected to the drain of the second transistor, an oscillator presenting a more linear transfer is obtained. With different frequency adjusting circuits this transfer can be realised in a first-order approximation or even totally independent of the threshold voltage of the transistors used.

Description: The invention relates to an oscillator, comprising a first and a second transistor including each a first main electrode, which first main electrodes are mutually coupled through a capacitor, and including each a second main electrode coupled to a gate electrode of the other transistor, the second main electrode of the first transistor being coupled to a first load circuit and the second main electrode of the second transistor being coupled to a second load circuit, the first load circuit comprises a parallel combination of a third and a fourth transistor, the second load circuit comprises a parallel combination of a fifth and a sixth transistor, gate electrodes of the third and fifth transistors both being coupled to the second main electrode of the first transistor and gate electrodes of the fourth and sixth transistors both being coupled to the second main electrode of the second transistor. An oscillator of this type is known from European Patent Application No. 361,529. If each load circuit is constituted by a resistor R and each first main electrode is connected to a current source that produces a current of the magnitude I, the oscillator will generate a square-wave output voltage between the two second main electrodes with a frequency f OSC = I/(2C * V C ), where C represents the value of the capacitor and V C is the voltage across this capacitor. The desired f OSC is obtained by selecting an appropriate value for the current I. Because the metallic conductance of a transistor is proportional to the square root of the main current through this transistor and because the metallic conductance of a resistor R is constant (= 1/R), the voltage V C (non-linear) becomes dependent on the current I. Consequently, the relation between the frequency f OSC and the current I assumes a non-linear feature. This is undesired, for example, in phase-locked loop applications in which an oscillator of this type is used. In forming each load circuit with the aid of transistors as is done in the above mentioned patent application, the metallic conductances of the load circuits are also proportional to the square root of the current. Thus, the relation between the frequency f OSC and the current I becomes more linear. Although the relation between the frequency f OSC and the current I becomes more linear, it remains strongly dependent on the threshold voltage V T of the transistors used. Since the V T of the transistors may vary considerably, and is strongly temperature dependent, this dependence is undesired. The object of the present invention is to provide an oscillator according to the preamble in which the dependence of the oscillator frequency on the threshold voltage V T has been reduced. Therefor the invention is characterised in that the oscillator comprises a frequency adjusting circuit which includes a seventh, an eighth and a ninth transistor, a gate electrode and a main electrode of this seventh transistor being mutually coupled and coupled to a first main electrode of the eighth transistor, a gate electrode and a second main electrode of this eighth transistor being mutually coupled and coupled to a gate electrode of the ninth transistor, whereas the second main electrode of the eighth transistor can be coupled to a current source and the ninth transistor is coupled to a connecting circuit coupled to the first main electrodes of the first and second transistors. The frequency of such an oscillator can be simply adjusted and varied. The connecting circuit may be realised in a manner known to those skilled in the art by serially combining a first connecting circuit transistor to the first transistor and a second connecting circuit transistor to the second transistor, and by connecting gate electrodes of the two above connecting circuit transistors to a gate electrode and to a main electrode of a third connecting circuit transistor which is to be combined in series with the ninth transistor. The value of the current generated by the current source then determines the main current flowing through the ninth transistor and through the third connecting circuit transistor combined in series therewith and, therefore, also determines the main currents flowing through the first and second connecting circuit transistors. This determines the maximum frequency of the oscillator, which maximum frequency can simply be reduced by connecting in series between the third connecting circuit transistor and a ninth transistor a fourth connecting circuit transistor, which fourth transistor can be shut off by means of a control voltage on its gate electrode, which operation likewise shuts off transistor 9 so that the main current through the third connecting circuit transistor and the associated frequency of the oscillator are reduced. It should be observed that it is widely known that a resistor can simply be realised by a single transistor in that the gate electrode of this transistor is connected to one of the main electrodes. A load circuit realised in this fashion does have the disadvantage, however, that its impedance is undefined during the period of time when no current flows through the transistor. This is undesired in the oscillator according to the invention. An embodiment of the oscillator according to the invention is characterized in that the W/L ratios of the first and second transistors are substantially equal, in that the W/L ratios of the third and sixth transistors are substantially equal and in that the W/L ratios of the fourth and fifth transistors are substantially equal, whereas the W/L ratios of the third and sixth transistors are larger than the W/L ratios of the fourth and fifth transistors. Thus, by arranging the oscillator in a substantially symmetrical fashion, the sensitivity of the oscillator for common mode noise voltages is strongly reduced. Because the W/L ratios of the third and sixth transistors are larger than the W/L ratios of the fourth and fifth transistors it is avoided that the load circuits by themselves start to oscillate. A further embodiment of the oscillator according to the invention is characterized in that the frequency adjusting circuit further includes a tenth, an eleventh and a twelfth transistor as well as a converter, a main electrode and a gate electrode of this tenth transistor being mutually coupled and coupled to a main electrode of the ninth transistor and to a gate electrode of the eleventh transistor, a main electrode of this eleventh transistor being coupled to a gate electrode and a main electrode of the twelfth transistor, a first input terminal of the converter being coupled to the gate electrode of the twelfth transistor, a second input terminal of the converter being coupled to the gate electrode of the seventh transistor and an output of the converter being coupled to the connecting circuit. In an oscillator according to the invention comprising such a frequency adjusting circuit, the frequency f OSC is totally independent of V T of the transistors used. Consequently, this embodiment is highly advantageous. The invention will be further explained with reference to the exemplary embodiments represented in the drawing Figures, in which like sections are referenced by like reference characters, in which: Fig. 1 shows the oscillator according to the invention, comprising a simple frequency adjusting circuit, and Fig. 2 shows the oscillator according to the invention comprising a more complicated frequency adjusting circuit. The oscillator represented in Fig. 1 comprises a first transistor 1 and a second transistor 2 whose sources are mutually connected through a capacitor 20. The drain of transistor 1 is connected to the gate of transistor 2 and to a first load circuit 21. The drain of transistor 2 is connected to the gate of transistor 1 and to a second load circuit 22. Load circuit 21 comprises a parallel combination of a third transistor 3 and a fourth transistor 4, whose sources are connected to ground and whose drains are connected to the drain of transistor 1. The gate of transistor 3 is also connected to the drain of transistor 1, whilst the gate of transistor 4 is connected to the drain of transistor 2. Load circuit 22 comprises a parallel combination of a fifth transistor 5 and a sixth transistor 6, whose sources are connected to ground and whose drains are connected to the drain of transistor 2. The gate of transistor 6 is also connected to the drain of transistor 2, whilst the gate of transistor 5 is connected to the drain of transistor 1. If a current I is applied to the two sources of the transistors 1 and 2, there will be a triangle voltage having a peak amplitude equal to 2 V C across the capacitor 20. Between the two drains of the transistors 1 and 2 there will then be a square-wave voltage having a frequency f OSC = I/(C * 2V C ). This current I is applied to the two sources through a connecting circuit 25 connected to a frequency adjusting circuit 23. With this adjusting circuit the current I may be varied as a result of which the frequency f OSC can be adjusted. The connecting circuit 25 comprises a first connecting transistor 32 whose source is connected to a positive voltage source and whose drain is connected to the source of transistor 1, a second connecting transistor 33 whose source is connected to the voltage source and whose drain is connected to the source of transistor 2, a third connecting transistor 31 whose source is connected to the voltage source and whose gate and drain are interconnected and also connected to the gates of connecting transistors 32 and 33, and a fourth connecting transistor 30 whose drain is connected to the drain of connecting transistor 31 and whose source is connected to the frequency adjusting circuit 23. The gate of connecting circuit 30 is connected to an adjustable source for obtaining a control voltage with which the degree of conductance of this connecting transistor 30 and of transistor 9 can be adjusted. The frequency adjusting circuit 23 comprises a seventh transistor 7, an eighth transistor 8 and a ninth transistor 9. The source of transistor 7 is connected to ground and the gate and drain are interconnected and connected to the source of transistor 8, whose gate and drain are interconnected and connected to the gate of transistor 9. The drain of transistor 8 is further connected to current source 24 for generating a current I bias through the main current paths of transistors 7 and 8. The source of transistor 9 is connected to ground and the drain is connected to the source of connecting transistor 30, through which connection the connecting circuit 25 and the frequency adjusting circuit 23 are interconnected. The functioning of the circuit described hereinbefore is as follows. Current source 24 produces a current I bias which flows to ground through the main current paths of the transistors 8 and 7. Consequently, there will be a voltage on the gates of transistors 8 and 9 that renders transistor 9 conductive. The magnitude of the current I which flows to ground through the main current paths of the respective transistors 31, 30 and 9 may be varied in a simple fashion by varying the control voltage on the gate of transistor 30, so that transistors 30 and 9 are shut off to a smaller or greater extent. Due to the current mirror arrangement this current I also flows through the main current paths of transistors 32 and 33 and the current I is thus applied to the sources of transistors 1 and 2 of the actual oscillator circuit. As a result, there will be a triangle voltage having a peak amplitude of 2V c across capacitor 20 and there will be a square-wave voltage having a frequency f osc = I/(C * 2V c ) between the drains of transistors 1 and 2. Since the current I is variable as a result of the control voltage on the gate of transistor 30, the frequency f osc is also variable (proportional to the current I). By means of measurements as well as a complicated calculation it can be demonstrated that the peak to peak amplitude 2V c of the triangle voltage across the capacitor 20 is proportional to +V T (threshold voltage of the transistors used). A simple calculation shows that for the main current through transistor 9 of the frequency adjusting circuit in a first-order approximation it also holds that this main current is proportional to +V T . Because f osc = I/(C * 2V c ) and both V c and I in a first-order approximation are proportional to +V T , f osc in a first approximation is independent of V T . However, if a conventional frequency-adjusting circuit were used, in the form of a single transistor switched as a current source, whose main current were proportional to -V T , an x% variation of V T would have caused a variation of over x% of f osc , which is highly detrimental. The oscillator represented in Fig. 2 differs from the oscillator represented in Fig. 1 only as regards the frequency adjusting circuit used. For the rest the two oscillators are identical. Frequency adjusting circuit 19 comprises, as does frequency adjusting circuit 23, the transistors 7, 8 and 9 and the current source 24, which are all interconnected in the same fashion. The drain of transistor 9 is connected to the drain and gate of a tenth transistor 10 and to the gate of an eleventh transistor 11, the sources of the two transistors 10 and 11 being connected to the voltage source. The drain of transistor 11 is connected to the gate and drain of a twelfth transistor 12 whose source is connected to ground. Furthermore, the gate of this transistor 12 is connected to a first input terminal 27 of a converter 26 converting an input voltage into a current. A second input terminal 28 of this converter is connected to the drain and gate of transistor 7. Output terminal 29 of converter 26 is connected to the source of connecting transistor 30. The operation of the oscillator represented in Fig. 2 is identical with the one represented in Fig. 1, with the exception of the operation of the more complicated frequency adjusting circuit 19 and its consequences to the remaining part of the oscillator. The operation of the frequency adjusting circuit 19 and the consequences of this circuit to the oscillator are as follows. Current source 24 produces a current I bias , which flows to ground through the main current paths of the transistors 7 and 8. This causes a voltage to occur on the gates of transistors 7, 8 and 9 so that transistor 9 is rendered conductive. The current flowing through transistor 9 also flows through transistor 10 and, as a result of the current mirror function, a current of about the same magnitude also flows through transistor 11. This current causes a voltage to occur across the transistor 12 switched as a diode, which voltage is also found on the input 27 of converter 26. The voltage difference between the drain of transistor 12 and that of transistor 7 is converted by converter 26 into a current which flows through the main current paths of the connecting transistors 31 and 30. As a result of the current mirror structure in the connecting circuit 25, currents of the same magnitude will flow through the main current paths of the transistors 32 and 33, and so on. By simply choosing the ratios of the transistors 7-12 in such a way that the voltage difference between the input terminals 27 and 28 is proportional to V T , and having the converter 26 operate according to I out = U in /R , where R is a constant, there is achieved that the oscillator represented in Fig. 2 has an oscillation frequency f osc which is independent of V T . For example, if the W/L ratios of the transistors 7 and 8 are substantially equal, if the W/L ratios of the transistors 10 and 11 are substantially equal and if the W/L ratio of transistor 12 is about 4 x as large as the W/L ratio of transistor 9, there will be a voltage difference of V T /2 between the input terminals 27 and 28. The maximum value of the current I from the equation f osc = I/(C * 2V c ) will then be equal to V T /2R and thus have a linear proportion to V T with a constant R. For example, if the W/L ratios of the transistors 1, 2 correspond to β p , if the W/L ratios of the transistors 3,6 correspond to β y and if the W/L ratios of the transistors 4, 5 correspond to β x , and, furthermore, it holds that: α - 1 β p = α 2 β y - 1 β x with α = Ir Il Λ A = β x β y 2 β y and that α - 1 β p = α 2 β y - 1 β x with α = Ir Il Λ A = β x β y 2 β y where Ir is the main current through transistor 2 and Il is the main current through transistor 1 if one of the transistors 4, 5 has a triode function and the other one is blocking or vice versa, in that case V c = V T . In this situation it then holds that I = V T /2R and V c = V T through which for f osc it is found that: f osc = I/(C * 2V c ) = 1/4RC. The frequency f osc is then totally independent of V T and has a maximum value of 1/4RC, this frequency f osc being decreased in a linear fashion when a lower control voltage is applied to the gate of transistor 30.

Claims: Oscillator comprising a first (1) and a second (2) transistor including each a first main electrode, which first main electrodes are mutually coupled through a capacitor (20), and including each a second main electrode coupled to a gate electrode of the other transistor, the second main electrode of the first transistor (1) being coupled to a first load circuit and the second main electrode of the second transistor (2) being coupled to a second load circuit, the first load circuit comprises a parallel combination of a third (3) and a fourth (4) transistor, the second load circuit comprises a parallel combination of a fifth (5) and a sixth (6) transistor, gate electrodes of the third (3) and fifth (5) transistors both being coupled to the second main electrode of the first transistor (1) and gate electrodes of the fourth (4) and sixth (6) transistors both being coupled to the second main electrode of the second transistor (2), characterized in that the oscillator comprises a frequency adjusting circuit which includes a seventh (7), eighth (8) and a ninth (9) transistor, a gate electrode and a main electrode of this seventh transistor (7) being mutually coupled and coupled to a first main electrode of the eighth transistor (8) a gate electrode and a second main electrode of this eighth transistor (8) being mutually coupled and coupled to a gate electrode of the ninth (9) transistor, whereas the second main electrode of the eighth transistor (8) can be coupled to a current source and the ninth transistor (9) is coupled to a connecting circuit (30, 31, 32, 33) coupled to the first main electrodes of the first (1) and second (2) transistors. Oscillator as claimed in Claim 1, characterized in that the W/L ratios of the first (1) and second (2) transistors are substantially equal, in that the W/L ratios of the third (3) and sixth (6) transistors are substantially equal and in that the W/L ratios of the fourth (4) and fifth (5) transistors are substantially equal, whereas the W/L ratios of the third (3) and sixth (6) transistors are larger than the W/L ratios of the fourth (4) and fifth (5) transistors. Oscillator as claimed in Claim 1 or 2, characterized in that the frequency adjusting circuit further includes a tenth (10), an eleventh (11) and a twelfth (12) transistor as well as a converter, a main electrode and a gate electrode of this tenth transistor (10) being mutually coupled and coupled to a main electrode of the ninth transistor (9) and to a gate electrode of the eleventh transistor (11), a main electrode of this eleventh transistor (11) being coupled to a gate electrode and a main electrode of the twelfth transistor (12), a first input terminal of the converter being coupled to the gate electrode of the twelfth transistor (12) a second input terminal of the converter being coupled to the gate electrode of the seventh transistor (7) and an output of the converter being coupled to the connecting circuit (30, 31, 32, 33).

Inventors: BOEKE WOUTER MARIA, ERFTEMEIJER FRANCISCUS G, BOEKE, WOUTER MARIA, ERFTEMEIJER, FRANCISCUS GEORGIUS
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: H03K3
IPC codes: H03B5, H03K3