Process for forming an electrical contact through an insulation layer to a silicon semiconductor wafer thereunder

Abstract: A process is described for forming planar tungsten-filled contacts to a silicon substrate (10) in contact openings (24) through an insulating layer (20) which provides for the formation of titanium silicide (32) in and on the silicon surface at the bottom of the contact openings (24) to provide low resistance silicide interconnections between the silicon substrate (10) and the tungsten (40). A titanium nitride layer (34,36,38) is formed over the titanium silicide (34) and on the surfaces of the insulation layer, including the top surface of the insulation layer (20) and the sidewall surfaces of the contact openings (24) through the insulating layer (20). This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO₂), resulting in the formation of low resistance and low defect density contacts.

Description: This invention relates to a method for forming electrical contacts on a silicon semiconductor wafer. In the formation of integrated circuit structures, it is necessary to provide electrical contact to portions of the silicon semiconductor substrate surface through openings in an insulator formed over the substrate, e.g., to provide electrical contact to one of the electrodes of an MOS or a bipolar device. Conventionally, this is carried out by filling the contact opening with a conductive material such as aluminum. However, the use of a metal such as aluminum for filling contact openings has become unsatisfactory in some instances, particularly where the aspect ratios (height/width) of such contact openings has increased to ratios greater than one 1. It has, therefore, been proposed to fill such contact openings with tungsten, due to its low resistance and ability to deposit conformally in contact openings, even when the opening has an aspect ratio of 1 or higher. However, tungsten does not make a good (low resistance) electrical contact with the surface of an insulator through which the contact opening is made, nor does the tungsten adhere very well to the sidewall surfaces of the contact opening through the insulator. Several prior art approaches toward solutions to the problems which have arisen with the use of tungsten to fill the contact opening have been proposed. These prior art approaches include, first of all, the preliminary physical vapor deposition (PVD) of an intermediate titanium nitride layer on the walls of the opening through reactive sputtering of titanium nitride material from a titanium or titanium nitride target prior to filling the opening with tungsten. This formation of a titanium nitride layer over the insulator provides a chemical barrier which inhibits the subsequent tungsten CVD process from interacting with the underlying silicon substrate which interaction could result in tungsten encroachment into the contact causing large leakage current and non-functional devices. This first approach requires a first or preliminary step of forming a silicide over and in the exposed silicon surface of the substrate before the titanium nitride deposition, since the titanium nitride does not form a good low resistance contact to silicon. The use of this type of process is particularly objectionable, however, because of the generation of high levels of titanium nitride particles, resulting in a high density of defects in the integrated circuit structures on the wafer, which, in turn, leads to low yields. It has also been proposed to physically deposit a titanium/tungsten (TiW) alloy or compound by reactive sputtering or other PVD methods, prior to filling the opening with tungsten. But this type of process has also been found to result in undesirable particle formation and deposition during the PVD formation of the titanium/tungsten alloy coating. A third method has also been proposed wherein a layer of titanium is first deposited on the exposed silicon substrate and the insulator sidewalls by a PVD method such as sputtering followed by sputter deposition of a layer of titanium nitride. The structure is then annealed to cause the deposited titanium over the silicon to react with the silicon to form a silicide in and on the silicon surface, prior to filling the opening with tungsten. However, when an annealing temperature of less than about 500°C is used, the type of silicide formed is not the desired low resistance type; while when a higher annealing temperature is used, silicon is found to migrate from the substrate to form titanium silicide along the walls of the contact opening, resulting in depletion of the silicon in the substrate adjacent the contact and, therefore, a nonfunctional device. It would, therefore, be desirable to provide a process for the filling of a high aspect ratio contact opening in an insulator with tungsten, wherein a good electrical contact could be formed between the tungsten and the silicon substrate at the bottom of the contact opening, while providing good adherence of the tungsten to the surfaces of the insulator, without the formation of undesirable particles which characterizes prior art processes for filling such a contact opening with tungsten, and without the prior art migration of the silicon from the substrate to form titanium silicide along the walls of the contact opening which, in such prior art processes, resulted in depletion of the silicon in the substrate adjacent the contact. This object is met by the process for forming an electrical contact through an insulation layer to a semiconductor wafer thereunder according to independent claim 1, 18 or 25. Further advantageous features, aspects and details of the process of this invention are evident from the dependent claims, the description and the drawings. The claims are intended to be understood as a first non-limiting approach of defining the invention in general terms. The produced contacts are low resistance and low defect density electrical contacts. The invention allows forming a low resistance contact between a silicon semiconductor wafer and a first metallization layer through a high aspect ratio contact opening in an insulating layer. The process of the invention provides for the formation of a tungsten-filled contact opening through an insulator, such as SiO 2 , to a silicon substrate according to claim 1. US patent 4,926,237 [Shih W. Sun et al.] discloses a process for forming an electrical contact through an insulation layer to a silicon wafer where a layer of titanium is deposited, followed by the deposition of a layer of tungsten without exposing the newly formed titanium layer at room ambient. The process is continued by heating the structure in a nitrogen ambient to cause both the formation of titanium silicide at the titanium-silicon interface and the formation of titanium nitride at the titanium-tungsten interface. In a further step a thick blanket layer of tungsten is deposited to fill the contact opening with tungsten. The document DE 37 43 591 [Mitsubishi Denki KK] shows a process where a first titanium layer is deposited. By heating the structure in nitrogen atmosphere titanium nitride is formed on the insulation layer and titanium silicide is formed on the silicon surface. In a further step a second layer of titanium is deposited that is transformed into titanium nitride in a second anneal step in nitrogen atmosphere. In the paper "Formation of TiSi 2 and TiN during nitrogen annealing of magnetron sputtered Ti films" by E.D. Adams, Journal of Vacuum Science and Technology A, vol. 3, no. 6 Nov/Dec 1985 the properties of titanium silicide and titanium nitride are studied. Figure 1 is a fragmentary vertical side-section view of a silicon semiconductor wafer having an insulator layer thereon with a contact opening formed through the insulator layer to the silicon substrate and a titanium layer deposited over the sidewalls of the contact opening, as well as over the exposed silicon surface at the bottom of the contact opening. Figure 2 is a fragmentary side-section view of the structure of Figure 1 after annealing of the structure to form the bilayer of titanium nitride and titanium silicide over the silicon substrate at the bottom of the contact opening and titanium nitride on the surfaces of the insulator. Figure 3 is a fragmentary side-section view of the structure of Figure 2 after a planarized layer of tungsten has been deposited on the entire wafer, including the contact opening. Figure 4 is a fragmentary side-section view of the structure of Figure 3 after the deposited tungsten has optionally been removed from the top surface of the insulator layer, leaving tungsten in only the contact opening in the insulator layer. The invention comprises an improved process for forming a tungsten-filled contact to a silicon substrate in a contact opening through an insulating layer which provides for the deposition of a titanium layer by sputtering, the formation of a bilayer of titanium nitride and titanium silicide in and on the silicon surface at the bottom of the contact opening to provide a low resistance silicide contact between the silicon substrate and the tungsten, and the formation of a titanium nitride layer on the surfaces of the insulating layer to provide a nucleation layer which permits a good bond to form between the tungsten in the contact opening and the insulator material such as silicon oxide, resulting in a low density of defects on the wafer. The process is particularly useful for filling high aspect ratio contact openings. By use of the term "low resistance silicide inter-connection" between the silicon substrate and the tungsten metal is meant a silicide with a sheet resistivity of less than 3 ohms/square, as compared to prior art silicides having a sheet resistance of from 3 to 30 ohms/square when annealed at a temperature less than 500°C. By use of the term "high aspect ratio" is meant a contact opening having a height to width ratio of at least 1. Turning now to Figure 1, a portion of an integrated circuit structure is shown comprising a fragmentary portion of a silicon wafer or substrate 10, having an insulating layer 20 formed thereon. Insulating layer 20 may comprise a silicon dioxide (SiO 2 ) insulation material, a boron glass, phosphorus glass, or boron/phosphorus glass, or any other material which is an insulator. A previously formed contact opening 24 is shown in insulating layer 20 which exposes a portion 12 of the silicon surface of substrate 10 which overlies a region or area 14 in substrate 10 to which it is desired to provide electrical communication. Region 14, for example, might comprise a source or drain region of an MOS transistor, or a collector region of a bipolar transistor, formed in substrate 10. A layer of titanium 30 is shown already deposited over the structure, including top surface 22 of insulator layer 20, the sidewall surfaces 26 of contact opening 24, and over exposed top surface 12 of silicon substrate 10. The thickness of titanium layer 30 will vary, depending upon the particular location of the titanium. For example, the thickness of the deposited titanium layer may vary from about 50 to about 500 NM (500 to about 5000 Angstroms) over top surface 22 of insulator layer 20; while the titanium thickness over surface 12 of silicon substrate 10 at the bottom of contact opening 24 may vary from about 5 to about 100 NM (50 to about 1000 Angstroms). Titanium layer 30 may be deposited over insulating layer 20, including sidewall surfaces 26 as well as top surface 22, and over exposed portion 12 of silicon substrate 10 using the process described in EP-A-0 452 889 and EP-A-0 452 891 assigned to the assignee of this invention, cross-reference to which is hereby made. These documents fall under Article 54(3) EPC and are not relevant to the question of inventive step. Such a titanium deposition comprises first the optional initial cleaning of the structure, for example, by a reaction process, using one or more fluorine-bearing gases and an inert gas such as argon. Following the cleaning of the structure, the titanium is deposited over the structure using a conventional PVD sputtering process, or any other suitable titanium deposition process. As described in the aforementioned documents EP-A-0 452 889 and EP-A-0 452 891, preferably the cleaned structure is transferred from the cleaning chamber to the titanium deposition chamber under vacuum to avoid exposing the cleaned surfaces to air or other oxygen-containing gases. The titanium-coated structure shown in Figure 1 is then transferred to an annealing chamber, without exposing the titanium surface to air or other oxygen-containing gases, and annealed in the presence of a nitrogen-bearing gas to form the titanium silicide and titanium nitride. The annealing is preferably carried out in accordance with the annealing process described in the above mentioned documents EP-A-0 452 889 and EP-A-0 452 891, crossreference to which is hereby made. As described in said documents EP-A-0 452 889 and EP-A-0 452 891, the anneal is carried out at an initial temperature ranging from about 500°C to about 695°C, preferably from about 600°C to about 675°C, to form the titanium nitride and titanium silicide, after which the temperature is raised to from about 800°C to about 900°C to convert to a more stable phase the titanium suicide initially formed at the lower temperature range. The pressure in the annealing chamber during the anneal is maintained within a range of from about 1.3 * 10 -4 bar to about 1064 mb (100 milliTorr to about 800 Torr). The anneal is usually carried out under rapid thermal anneal conditions where the wafer temperature is rapidly ramped up to the annealing temperature at a rate of from about 5°C/second to about 150°C/second, typically about 80°C/second, and the portion of the annealing step conducted at the temperature range of from about 500°C to about 695°C is carried out for a period of from about 10 to about 60 seconds. The second temperature range portion of the anneal at from about 800°C to about 900°C is then carried out for an additional time period of from about 10 to about 60 seconds. Oxygen-containing gases are excluded from the surfaces during the anneal, and a source of nitrogen is provided by flowing one or more nitrogen-bearing gases into the chamber at a rate ranging from about 500 to about 10,000 standard cubic centimeters minute (sccm), depending upon the volume of the annealing chamber and the capacity of the vacuum pump. As shown in Figure 2, titanium silicide 32 is formed at the bottom of contact opening 24, in and on previously exposed silicon surface portion 12 over region 14 in silicon substrate 10, by reaction of the titanium with the exposed silicon. Titanium nitride 34 is shown formed over silicide 32, titanium nitride 36 is shown formed over the exposed sidewall surfaces 26 of insulating layer 20 in contact opening 24, and titanium nitride 38 is shown formed over top surface 22 of insulating layer 20. Titanium nitride 34, 36, and 38 is formed by reaction of the titanium with the nitrogen gas present in the annealing chamber during the anneal. It should be noted here, that the exclusion of oxygen-containing gases from the titanium surface prior to the annealing step prevents or mitigates formation of titanium oxides on the titanium surfaces. The presence of titanium oxides on or in the titanium layer have been found to inhibit the penetration of the nitrogen atoms into the titanium, which could result in formation of titanium silicide on sidewall surfaces 26 of contact opening 24. Such titanium silicide formation would be undesirable, as discussed with respect to the prior art processes, because silicon migration from silicon substrate 10 to form such titanium silicide would result in a depletion of silicon in region 14 of silicon substrate 10 adjacent contact opening 24. After the formation of titanium nitride 34, 36, and 38, a controlled oxygen-bearing heat treatment could be included to allow for different types of tungsten CVD nucleations, as is well known to those skilled in the art. For example, such an oxygen-bearing heat treatment may be carried out in the same chamber used for the nitrogen-bearing anneal to form the titanium silicide and titanium nitride layers and within the same pressure range, i.e., from about 1.3 * 10 -4 bar to about 1064mb (100 milliTorr to about 800 Torr), while maintaining the water temperature within a range of from about 300°C to about 900°C. The anneal in the oxygen-bearing gaseous atmosphere may be carried out for a period of from about 10 to about 60 seconds by flowing an oxygen-bearing gas, such as oxygen or nitrous oxide (N 2 0), through the annealing chamber. In accordance with the invention, following the anneal in the nitrogen-bearing gas, and the optional subsequent anneal in the oxygen-bearing gas, a layer 40 of tungsten is then deposited over the structure to fill the remainder of contact opening 24 with tungsten, as well as to provide a planar coating of tungsten over top surface 22 of insulating layer 20 and titanium nitride coating 38 formed thereon. Deposition of a layer of tungsten over the structure at this point may be carried out using any conventional tungsten deposition method. For example, by way of illustration, and not of limitation, the tungsten deposition may be carried out in accordance with the tungsten deposition process described in EP-A-414267, assigned to the assignee of this invention, crossreference to which is hereby made. As disclosed in the aforementioned EP-A- 0414267, tungsten may be deposited over the structure and into contact opening 24 to form the structure of Figure 2 by first mounting the wafer on a susceptor in a CVD chamber, and then flowing a mixture of gases into the chamber which include a tungsten-containing gas, such as WF 6 . During the CVD process, a pressure is maintained in the chamber within a range of from about 6.5 * 10 -4 bar to about 1010.8 .10 -3 bar (1bar = 10 5 Pa) (500 milliTorr to about 760 Torr), and preferably from about 26.6 .10 -3 bar (1bar = 10 5 Pa) to about 1010.8 .10 -3 bar (1bar = 10 5 Pa) (20 Torr to about 760 Torr). The higher pressure range is preferred to provide a faster deposition rate. During the deposition, the temperature of the susceptor on which the wafer is mounted is maintained within a range of from about 350°C to about 525°C, preferably within a range of from about 400°C to about 475°C. The tungsten may be deposited while flowing a mixture of WF 6 , N 2 , and H 2 gases and an inert carrier gas such as helium, neon, argon, krypton, or xenon through the deposition chamber at a rate of from about 10 to about 200 sccm of WF 6 , preferably from about 20 to about 100 sccm; from about 100 to about 5000 sccm of an inert carrier gas such as argon, preferably from about 1000 to about 3000 sccm; from about 10 to about 300 sccm of nitrogen; and from about 300 to about 3000 sccm of hydrogen, preferably from about 500 to about 2000 sccm. The deposited tungsten forms a good electrical contact with the bilayer of titanium nitride 34 and titanium silicide 32 at the bottom of contact opening 24. Titanium nitride 36 and 38 on the remaining surfaces of insulation layer 20 form a nucleation layer which facilitates adherence of the deposited tungsten, respectively, to sidewall surfaces 26 and top surface 22 of insulating layer 20. It should be noted that while the use of nitrogen gas during the tungsten deposition, in combination with the other gases, is preferred, nitrogen can be eliminated from the gaseous mixture if the deposited tungsten will be later removed from the top surface of insulation layer 20. The nitrogen gas may optionally be omitted in such a case because one of the main purposes of the use of nitrogen gas, in combination with the other gases, is to provide a smooth tungsten surface to facilitate further photolithography. Using the above described tungsten deposition parameters, the tungsten deposition rate, on either top surface 22 of insulation layer 20 or within contact opening 24, will range from about 50 NM to about 700 NM (500 to about 7000 Angstroms) per minute. Therefore, for example, to ensure adequate filling of contact opening 24, when its width is about 1 µm, and the deposition rate is 50 NM (500 Angstroms) per minute, the tungsten deposition process should be carried out for at least about 1 minute, (since the tungsten deposits simultaneously on opposite sides of the contact opening) resulting in the structure shown in Figure 3. If it is desired to use deposited tungsten layer 40 on top surface 22 of insulating layer 20 as a wiring or interconnect layer, tungsten layer 40 may be masked and patterned at this point. Alternatively, the structure may be planarized at this point, as shown in Figure 4, to remove all tungsten (and titanium nitride) on top surface 22 of insulating layer 20, leaving only tungsten 40' (and titanium nitride 34 and 36) in contact opening 24. This may be desirable, for example, if a different conductive material is to be used over insulating layer 20 as the conductive layer or wiring harness. Such planarizing may comprise any conventional planarization such as an anisotropic dry etch, a wet etch, or a combined chemical/mechanical wet etch. It should be noted that while the steps of depositing titanium, annealing the titanium to form titanium silicide and titanium nitride, and tungsten deposition have all been described as being carried out in separate chambers, it will be understood that all of these steps may be carried out in separate vacuum apparatus, providing sufficient care is exercised during transfer of the wafer from one apparatus to another to not expose the coated wafer to contamination. For example, it is of particular importance that the titanium-coated wafer not be exposed to oxygen-bearing gases during the transfer from the titanium deposition chamber to the annealing chamber. On the other hand, all of the described titanium deposition, annealing, and tungsten deposition steps may be carried out in different stations in the same central vacuum chamber. Preferably, however, each of the steps will be carried out in a separate chamber in the same vacuum apparatus so that each chamber may be designed to optimize the particular process to be performed therein and to avoid cross chamber contamination. The wafer is then transferred from one chamber to another in the same vacuum apparatus while maintaining the wafer under vacuum throughout the process. Thus, the process of the invention provides an improved method of filling a high aspect ratio contact opening with tungsten wherein a silicide is formed between the exposed portion of the silicon substrate at the bottom of the contact opening and the tungsten filler material; a titanium nucleation layer is provided on the silicon oxide sidewall surfaces of the contact opening to facilitate formation of a good bond between the oxide sidewall surfaces and the tungsten filler material; and the formation of undesirable particles, while preparing the structure for the tungsten deposition is inhibited, in contrast to the prior art preparation steps.

Claims: A process for forming an electrical contact through an insulation layer to a silicon semiconductor wafer thereunder which comprises: a) depositing, in a deposition station, a layer of titanium over: i) exposed surfaces of said insulation layer, including sidewall insulation surfaces of a contact opening previously formed through said insulation layer to said silicon wafer; and ii) a surface of said silicon wafer exposed by said contact opening; b) transferring said titanium-coated, wafer from said deposition station to an annealing station in a vacuum apparatus without exposing said titanium to oxygen-containing gases; c) annealing said deposited titanium in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-containing gas, to form titanium silicide over the exposed silicon wafer surface at the bottom of said contact opening, and titanium nitride on said titanium silicide and on the surfaces of said insulation layer; d) transferring said wafer from said annealing station to a CVD station in a vacuum apparatus; and e) depositing a layer of tungsten by a CVD process over: i) said titanium nitride surfaces on said SiO 2 insulating layer; and ii) said titanium nitride on said titanium silicide formed over said silicon substrate; to thereby form a good electrical contact between said tungsten in said contact opening and said silicon wafer through said silicide, and a good bond between said tungsten and said titanium nitride formed on said insulating layer surfaces. The process of claim 1 wherein said insulating layer comprises a layer of SiO 2 . The process of claim 1 or 2 wherein said contact opening in said insulating layer has an aspect ratio of at least 1, and said step of depositing said titanium layer further comprises forming a layer of titanium over said exposed silicon surface at the bottom of said contact opening ranging in thickness from about 5 to about 100 nm (50 to about 1000 Angstroms). The process of one of the preceding claims including the further step of transferring said titanium coated wafer from a deposition station to an annealing station without exposing said titanium deposited thereon to any oxygen-containing gases prior to said step of annealing in the presence of a nitrogen-bearing gas. The process of one of the preceding claims wherein in step a), the layer of titanium is sputter deposited in a PVD station in a vacuum apparatus. The process of one of the preceding claims wherein said annealing step in said presence of said nitrogen-bearing gas further comprises initially annealing said titanium coated wafer at a temperature ranging from 500°C to 695°C to form said titanium. The process of claim 6 wherein said annealing step in said presence of said nitrogen-bearing gas further comprises raising said annealing temperature to a range of from 800°C to 900°C after said initial annealing to convert to a more stable phase said titanium silicide initially formed within said temperature range of from 500°C to 695°C. The process of claim 6 or 7 wherein said annealing step in said presence of said nitrogen-bearing gas further comprises initially annealing said titanium coated wafer at a temperature ranging from 650°C to 675°C to form said titanium silicide and titanium nitride. The process of one of claims 6 to 8 wherein said annealing step in said presence of said nitrogen-bearing gas further comprises maintaining the pressure within a range of from about 1.3 * 10 -4 bar to about 1066 mb (100 milliTorr to about 800 Torr) during said annealing to form said titanium silicide and titanium nitride. The process of one of the preceding claims wherein an optional annealing step in the presence of an oxygen-bearing gas is carried out after said step of annealing in the presence of a nitrogen-bearing gas. The process of one of the preceding claims wherein said annealing step in said presence of said nitrogen-bearing gas further comprises: a) heating said titanium-coated wafer to an initial annealing temperature ranging from 500°C to 695°C at a rate of from 5°C/second to 150°C/second; b) annealing said titanium coated wafer at a temperature ranging from 500°C to 695°C for a period of from 10 to 60 seconds to form said titanium silicide and titanium nitride; and c) then raising said annealing temperature to a second annealing temperature range of from 800°C to 900°C and maintaining said wafer within said second annealing temperature range for a period of from 10 to 60 seconds to convert to a more stable phase, said titanium silicide initially formed within said temperature range of from 500°C to 695°C. The process of one of the preceding claims wherein said step of depositing said titanium in said contact opening on said wafer further comprises PVD sputtering said titanium. The process of one of the preceding claims wherein said step of depositing said tungsten is to fill said contact opening with tungsten and to form a planarized layer of tungsten over said titanium nitride-coated insulation layer. The process of one of the preceding claims wherein said step of depositing said tungsten further comprises depositing said tungsten in said contact opening by a CVD process. The process of one of the preceding claims wherein said step of depositing said tungsten further comprises depositing said tungsten in said contact opening by flowing a mixture of gases which include a tungsten-containing gas into a CVD station in a vacuum apparatus while maintaining a pressure ranging from 66.6 Pa (500 mTorr) to 101 kPa (760 Torr). The process of one of the preceding claims wherein said step of depositing said tungsten in said contact opening further comprises flowing a gaseous mixture comprising WF 6 and H 2 gases and an inert carrier gas through the deposition station. The process of claim 16 wherein said step of flowing WF 6 and H 2 gases and an inert carrier gas through the deposition station is effected at a rate of from 20 to 200 sccm of WF 6 ; from 100 to 5000 sccm of said inert carrier gas; and from 300 to 3000 sccm of hydrogen. The process of one of the preceding claims wherein said step of depositing said tungsten in said contact opening further comprises mounting said wafer on a susceptor in a CVD station and maintaining the temperature of said susceptor within a range of from 350°C to 525°C during said deposition. The process of one of the preceding claims wherein said station for deposition of said titanium over said surfaces of said insulating layer and on said exposed portion of said silicon wafer; and/or said annealing station for annealing said titanium to form said titanium silicide and titanium nitride; and/or said station for depositing a layer of tungsten over insulating layer to fill said contact opening with tungsten are all located in separate chambers of the same vacuum apparatus whereby said wafer may be transported from one chamber to another without exposing said wafer to contamination. The process of one of claims 5 to 19 wherein said PVD titanium sputtering step, said annealing step, and said tungsten CVD step are all carried out in the same chamber in said vacuum apparatus. The process according to any of the preceding claims wherein the electrical contact is low resistance, low defect density and planar.

Inventors: CHANG MEI, NULMAN JAIM, SOMEKH SASSON, CHANG, MEI, NULMAN, JAIM, SOMEKH, SASSON
Applicants: APPLIED MATERIALS INC, APPLIED MATERIALS, INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L23