Image forming apparatus

Abstract: The apparatus, such as a laser printer, ink jet printer and a thermal transfer printer, uses a smoothing circuit (10) which according to the invention, comprises a neural network firstly to improve image quality by reducing a zigzag included e.g. in input image data, secondly to reduce circuit size by reducing the number of small-weight bits for an input combination, and, thirdly to correct the size of center, left and right picture elements in a predetermined window. The neural network outputs, for the first aim, correction data for the size and position of the center dot in a window in response to an input of dot image data in a window or subdot pattern exposure data for the center dot. The neural network uses for the second aim any of the three 3] values, +1, -1 and 0 for the coefficient of input combination for an hidden layer neuron e.g. after a teacher pattern is learned. The neural network provides for the third aim a correction data outputter (e.g. a neural network) for outputting correction data for 3xN subblocks of picture elements obtained by dividing blocks of picture elements in the center, left and right of a window.

Description: Background of the Invention The present invention relates to an image forming apparatus used for printers such as laser printers, ink jet printers, thermal transfer printers, etc., and more specifically to an image forming apparatus capable of improving the quality of inputted images by reducing jaggy forms and smoothing the density variation in gray scale images. Since a large part of image forming printers are designed for 300dpi, most electronic computers output signals in accordance with 300dpi. However, 300dpi printers have a disadvantage of forming jaggy images. To eliminate it, the density of picture elements must be made higher. Nevertheless, high-density picture elements increase page buffers and printer costs associated with enhanced precision in an engine. Additionally, widely distributed bit map font and popular input units (scanners, etc.) for 300dpi units cannot be used at all. With laser printers, high-density picture elements can be obtained in the vertical scanning. That is, it is very difficult to increase the pitch of form feed and drum feed. If it could, it would cost very high. If high-density picture elements is designed in the horizontal scanning direction, the improvement can be realized more easily with a low cost. Therefore, it is proposed that the quality of images should be improved by tripling the picture element positioning precision in the horizontal direction and setting the size of a picture element in 12 variations (USP4,847,641). With this method, inputted image picture elements are segmented by a sampling window of a predetermined form, compared with a plurality of template patterns written in a PLA (programmable logic array), and modified to the correct position and size of corresponding picture elements if they match any of the predetermined patterns. Figure 1 shows how to correct the position and size of picture elements. Inputted data 1 are segmented by a sampling window 2, compared with templates 3 shown to the right in Figure 1, and corrected to the position and size of corresponding picture elements if inputted data match any of the template patterns. Figure 2 shows before-correction and after-correction pattern samples stored in templates 3. In Figure 2, the patterns above each arrow shows data in a template to be corrected, and the patterns below each arrow show patterns corrected according to the data. Each of the upper patterns shows a vertical oblique line to be corrected to an appropriate vertical oblique line. For example, the left most pattern shows that the picture element at the center is moved by 1/3 element to left. In these patterns, thin black dots indicate picture elements not to be corrected in the present process. In Figure 2, middle patterns shows a jag reducing process on a horizontal oblique line where the size of a dot to be corrected is reduced to 60% in normal dot diameter. The two patterns in the lower right corner show a jag reducing process on a horizontal oblique line where the size of a dot to be corrected is reduced to 30% in normal dot diameter. Then, a white dot right to the corrected dot is assigned a black dot of 60% in normal dot diameter, thus reducing jags in horizontal oblique lines. However, since the methods described by referring to Figures 1 and 2 require a number of template patterns, they cause problems of a low process speed, a large memory requirements for storing a large number of template patterns, and correction being performed only on picture elements at the coincident positions in template patterns. An additional problem is that an appropriate correction cannot be performed for a pattern of, for example, a black-white-black arrangement because the correction is made only in picture element units and such arrangement cannot be made within one picture element. In addition to the jag reducing method, there is a density variation smoothing method as another method for improving the quality of images. However, this method is not practical because a great number of picture element patterns exist in the same gray scale. Furthermore, in the method shown in Figure 1, the quality of images is improved by correcting the position and size of a target picture element, that is, a picture element at the center of a template. Therefore, picture elements are undesirably corrected depending on the types of patterns as shown in Figure 3, thereby resulting in worse image quality. Besides, a picture element comes in 12 variations and the input position can be shifted for 3 positions, that is, the original, forward, and backward positions. This generates 36 selections of lighting timing, thereby causing a large scale circuit for light modulation. There is known from document US-A-5 029 108 an edge enhancement procedure for a dot matrix device in which the presence of edges is detected. Based on the finding, the edge is modified either by repositioning related dots or by altering the dot size. A neural architecture for the enhancement of noisy images is disclosed in Proceedings of the 2 nd International IEEE Conference on Tools for Artificial Intelligence, Nov. 6, 1990, Herndon, VA, USA, pp. 699-705, Shih F. et al.. The neural processing is in this concerned primarily with the elimination of noise in the region of organised patterns, without recourse to a pre-knowledge of these patterns. SUMMARY OF THE INVENTION An object of the present invention is to improve the quality of images by reducing jags in images inputted through a neural network and smoothing the density variations in gray-scale images. Another object is to reduce the capacity of a buffer for storing a coefficient and minimize the scale of a circuit by using a network capable of representing by a small number of bits the coefficient of input connection to each neuron in the hidden layer after the learning of a correction pattern. The third object of the present invention is to reduce image jags and improve the quality of images by comparing the data of a target picture element and those surrounding it with a predetermined pattern and simultaneously correcting the target and the right and left adjacent picture elements. A feature of the present invention resides in an image forming apparatus comprising the features of appended claim 1. Brief Description of the Drawings Figure 1 shows the prior art technology of improving the quality of images represented by inputted image data; Figure 2 shows an example of a correction pattern; Figure 3 shows the prior art technology of correcting images; Figure 4 is a block diagram for explaining the first principle of the present invention; Figure 5 is a block diagram for explaining the second principle of the present invention; Figure 6 shows the relationship between an angle and an jaggy effect; Figure 7 shows a subdot pattern required for reducing jags in images; Figure 8 is a view for explaining the evaluation levels for mean opinion values; Figure 9 shows an example of a pattern to be corrected according to the present invention; Figure 10 is a view for explaining the operation of a neuron; Figure 11 shows a model of a neural network; Figure 12 shows a Sigmoid function; Figure 13 shows a step function; Figure 14 shows an embodiment of assigning a picture element to the input layer unit (1); Figure 15 shows an embodiment of assigning a picture element to the input layer unit (2); Figure 16 shows an embodiment of the size of a picture element; Figure 17 shows an embodiment of the position of a picture element as conversion data; Figure 18 shows an embodiment of the correspondence between an output value from the output layer unit and the position and size of a picture element; Figure 19 is a block diagram for explaining the system configuration of the first embodiment of the image forming apparatus according to the first principle; Figure 20 is a timing chart of the operation of the system shown in Figure 19 ; Figure 21 shows an embodiment of a correction pattern (teaching pattern) 1; Figure 22 shows an embodiment of a correction pattern (teaching pattern) 2; Figure 23 is a flowchart of the embodiment of a learning process; Figure 24 shows an example of an erroneous correction during a learning process; Figure 25 shows an example of correcting an unlearned pattern; Figure 26 shows an example of correcting a character and a straight line; Figure 27 shows an embodiment of a coefficient for a neuron in the hidden layer after a learning process; Figure 28 shows an embodiment of a coefficient for a neuron in the output layer after a learning process; Figure 29 shows an embodiment of a flow of image data; Figure 30 shows an embodiment of the size of a 5-value picture element; Figure 31 is a block diagram for explaining the system configuration of the second embodiment of the image forming apparatus according to the first principle of the present invention; Figure 32 shows an embodiment of a coefficient for a neuron in the hidden layer after a learning process; Figure 33 is a block diagram for explaining the configuration of a neuron in the hidden layer of the third embodiment of the image forming apparatus according to the first principle of the present invention; Figure 34 is a block diagram for explaining the configuration of the neuron in the hidden layer of the fourth embodiment of the image forming apparatus according to the first principle of the present invention; Figure 35 shows an embodiment of the content of the coefficient buffer and the selection control signal shown in Figure ; Figure 36 is a block diagram for explaining the configuration of the selection controller. Figure 37 is a block diagram for explaining the general configuration of the printer as an image forming apparatus; Figure 38 is a block diagram for explaining the detailed configuration of the image quality correcting circuit; Figure 39 illustrates the input of 1-line image data; Figure 40 shows the connection between the latch on the input side of the image data and the RAM; Figure 41 illustrates the data input to the shift register; Figure 42 shows the connection between the RAM on the input side of the image data and the shift register; Figure 43 is a block diagram for explaining the configuration of the pulse width correcting circuit; Figure 44 shows an example of a exposure pulse correction signal specified by the dot size and shift; Figure 45 shows an example of a exposure pulse correction signal by combining the remaining data of the dots in the preceding window and the dot data in the present window Figure 46 is a timing chart of the operation of the image quality correcting circuit; Figure 47 is a block diagram for explaining the system configuration of the first embodiment of the image forming apparatus according to the second principle of the present invention; Figure 48 shows the embodiment of correction patterns (teacher patterns) 1; Figure 49 shows the embodiment of correction patterns (teacher patterns) 2; Figure 50 shows the embodiment of correction patterns (teacher patterns) 3; Figure 51 shows the embodiment of correction patterns (teacher patterns) 4; Figure 52 shows an example of correcting a character and a straight line; Figure 53 is a block diagram of the hidden and the output layers of the second embodiment of the image forming apparatus according to the second principle of the present invention; Figure 54 is a timing chart for explaining the operation of the second embodiment according to the second principle of the present invention. Figure 55 is a block diagram for explaining the configuration of an adder in a neuron shown in Figure 53 . Figure 56 shows the coefficient of input connection (1); Figure 57 shows the coefficient of input connection (2); Figure 58 shows an example of a pattern to be corrected; Figure 59 is a block diagram for explaining the configuration of a neuron in the input and the hidden layers of the third embodiment of the image forming apparatus according to the second principle of the present invention; Figure 60 is a block diagram for explaining- the configuration of a neuron in the hidden layer of the fourth embodiment of the image forming apparatus according to the second principle of the present invention; Figure 61 shows a conversion result of a corrected pattern; Figure 62 is an enlarged view of the subdot pattern shown at the lower left corner in Figure 61 . Figure 63 is a block diagram for explaining the configuration of and after the output layer of the fifth embodiment of the image forming apparatus according to the second principle of the present invention; Figure 64 is a block diagram for explaining the configuration of the neuro output-unit of the sixth embodiment of the image forming apparatus according to the second principle of the present invention; Figure 65 is a descriptive view of generating a subdot; Figure 66 is a block diagram for explaining the detailed configuration of the image quality correcting circuit according to the second principle of the present invention; Figure 67 is a timing chart 1 of the operation of the image quality correcting circuit shown in Figure 66 ; Figure 68 is a timing chart 2 of the operation of the image quality correcting circuit shown in Figure 66 ; Description of the Preferred Embodiment Figure 4 is a block diagram for explaining the first principle of the present invention. It shows the principle of the image forming apparatus for reducing jags in images and smoothing density variations in gray-scale images to obtain a high quality of inputted dot images by controlling the correction of inputted dot image data according to the array of the data. In Figure 4, a neural network forming a smoother 10 outputs conversion data of the position and size of a central picture element (dot) in a window of a predetermined form, for example, a rectangular window comprising three lines each comprising 5 picture elements, according to picture element data inputted therein. For example, the size of a dot as a picture element can be specified by 4 values including 100% at maximum, 60%, 30%, and 0% (no dot), or by 5 values including 100%, 75%, 50%, 25%, and 0%. The position of an image, that is, a dot, can be specified by 3 positions including the original position and its right and left adjacent positions. In an output layer of neural network, a plurality of neurons (units) output size conversion data of picture elements, and another plurality of units output position conversion data of picture elements. The size and position data of picture elements are outputted separately from respective units. Thus, compared with the conventional method in which a unit in the output layer generates an output code containing size and position data together, the present invention reduces the number of units in the hidden layer, thus stepping up the process in the neural network. Since the first principle is based on a neural network for instructing a correction of a dot according to the array of inputted dot image data, it does not require many template patterns, performs a process at a high speed, requires a small memory capacity, and gives the optimum correction instruction in response to an unlearned pattern. Figure 5 is a block diagram for explaining the second principle of the present invention. The neural network forming a part of the smoother 10 outputs exposure pattern data using a plurality of subdots corresponding to the dots for representing inputted image data which are processed in a rectangular window units. A window comprises, for example, 7 lines each comprising 9 picture elements. The exposure pattern data are outputted to correct a central picture element in a window according to the array of picture element data in each window. For example, if one picture element is represented by an 8-subdot exposure pattern, data conversion is performed for 2,400dpi when the resolution in the horizontal scanning direction is set for 300dpi. To further improve the quality of images, a pattern consists of 8-segment patterns to remove jags from picture elements and smooth density variations. A line is displayed in a jaggy form more than any other drawing elements. Besides, a line is displayed in different jaggy effects depending on its obliquity. Figure 6 shows the relationship between an angle and a jaggy effect. The mean opinion score (described later) of a vertical axis corresponds to the jaggy effect, i.e., a deteoration of an image caused by the jaggy. "Mark 5" indicates that jags are not recognized. Marks lower than 5 indicate a growing jaggy effect in the descending order. Figure 6 indicates that a line offers the most outstanding jaggy effect at a little bit off 0°, 45°, and 90°. When a corrected pattern is made at these angles using 8 subdots, it can be displayed with little jaggy effects if it is formed using 28 patterns in combination. Actually, the 8 subdots can form 256 patterns, only 28 patterns (shown in Figure 7) of which are enough to remove jags from images. That is, the size of a dot can be specified by the number of consecutive subdots (black). One inputted dot is not corrected by two or more consecutive subdots, and a dot image can be affected by the correction in its right and left dots. Therefore, a subdot pattern representing a dot has only 6 arrays: black, black-white, black-white-black, white-black-white, white-black, and white. All these patterns are shown in Figure 7. The size and position of a dot can be controlled by combining some of these patterns. The black-white-black pattern shown in Figure 7 in the third row is not a separated dot, but generated by the right-left shift of adjacent subdots. The mean opinion score shown in Figure 6 shows how to obtain an average value of marks of determination results according to the evaluation levels shown in Figure 8 after showing ten observers variations of sample images in which a line is displayed at different obliquities. Next, the second object of the present invention, to minimize the scale of a circuit by representing using a small number of bits the coefficient of an input connection to a neuron in the hidden layer. To achieve this, as indicated by the first and second principles shown in Figures 4 and 5, the smoother 10 is operated through a neural network comprising 3 layers: an input layer, an hidden layer, and an output layer, and outputting, after learning, one of three values +n, -n, and 0 (n indicates a constant), e.g. +1, -1, and 0 as a coefficient of an input connection to each neuron in the hidden layer. Then, it outputs correction data for a dot in inputted image data according to the array of inputted dot image data. It is also possible to configure the smoother 10 operated through a neural network for outputting, after learning, two values (+1 and 0) as coefficients of an input connection to each neuron in the hidden layer, and, to permit it to apply to the network both a normal signal and an inverted signal of picture element data. A sample of a pattern to be corrected is referred to in order to describe how to achieve the second object of the present invention as follows. In the present invention, the dot size and position of the central picture element in a window are corrected such that jags are removed from images and then outputted. Generally, all dots in a window are not involved in correcting a jaggy image, but they are limited to the central dot and some dots surrounding it. In Figure 9, after the correction, the central dot is moved to left by 1/3 dot in the normal size. The necessary data are the second black dot and the third and fourth white dots in the first row, the third black dot and the fourth white dot in the second row, and the third black dot and the fourth white dot in the third row. The other dots can be black or white, that is, they are "don't care" dots. A coefficient of an input connection to a neuron in the hidden layer is converged to one of three values +1, -1, or 0 when teaching is repeated by providing 0 or 1 as don't care data for the neural network in the smoother 10 shown in Figures 4 and 5, and proceeding the teaching with increased number of patterns. In the present invention, jags are removed from images through the neural network in which a coefficient of an input connection to a neuron in the hidden layer converges to 1, -1, or 0 after learning. Figure 10 shows the operation of a neuron forming the neural network. A neuron is also referred to as a unit. It multiplies a plurality of inputs by respective coefficients, adds the products together, converts the sum using an appropriate function, and then outputs the result. The output y n of the n-th neuron is obtained by the following expression. y n =f(k 0 n +k 1 n x 1 n +...+k m n x m n ) where x i n indicates the i-th input to the n-th neuron; k i n indicates a coefficient of the input; and k o n indicates a constant term. Figure 11 shows a model of the neural network. A circle indicates a neuron. Input layer units (for receiving an input to the network) are omitted in this figure because they only transmit an input to the units in the hidden layer. There are 3 units in the hidden layer, and 2 neuron units in the output layer. In Figure 10 , Sigmoid function and step function are used in converting a result of an addition. Figure 12 shows a Sigmoid function; and Figure 13 shows a step function. However, conversion function are not limited to these functions. Generally, the larger number of picture elements inputted to a neural network, the better image correction and the larger number of correction patterns. For example, if the number of inputted picture elements is 5x5, the combination using all the picture elements is diversified to 2 5x5 , that is, 33554432 variations. If it is 7x9, the combination comes in 2 7x9 , that is, 9.22x10 18 variations. Thus, it is impossible to teach all image patterns to the neural network. Therefore, among all patterns, some patterns should be selected as those to be corrected and others as those not to be corrected before teaching the network. Picture elements are corrected by the network using a coefficient obtained through the teaching. If the network is going to perform an undesirable conversion, it must learn again. In this way, picture elements can be corrected without operating for all patterns, and can also appropriately convert picture elements for an unlearned pattern to the network. Figures 14 and 15 show examples of assigning picture elements to each unit in the input layer of the neural network. In Figure 14 , the picture elements in 3 lines each comprising 5 picture elements are outputted in a window. In Figure 15 , the picture elements in 7 lines each comprising 9 picture elements are outputted in a window. A window is formed of a predetermined figure. In each of 15 units (63 units in Figure 15 ) in the input layer, picture element data are set to 1 if the picture element is assigned as "black", and set to 0 if it is assigned as "white". "1" and "0" can be set inversely. Figure 16 shows an example of the size of a picture element after the conversion. The size can be specified by 4 levels as 100% (the maximum dot diameter), 60%, 30%, and 0% (no dot). Figure 17 shows an example of the position of picture element, that is, a dot, specified by conversion data. The dot position can be specified for the central position, that is, its original input position, the position 1/3 dot to the left of the original input position, and the position 1/3 dot to the right of the original input position. A dot is represented by 900dpi if the original resolution is 300dpi. Figure 18 shows an example of the correspondence between an output value from the output layer of the network and the corresponding position and size of a picture element. In 5-bit data indicating an output value from 5 output units in the neural network, the higher 3 bits indicate the size of a dot (000 for 0%, 001 for 30%, 010 for 60%, and 100 for 100% by referring to Figure 16 ). The lower 2 bits indicate the position of a dot (00 for the central position, 01 the position 1/3 dot to the right of the central position, and 10 for the position 1/3 dot to the left of the central position). Thus, in the present invention, 3 units in the 5 units in the output layer specify the size of a dot, and 2 unit specify its position. Therefore, the output code is represented by 5 bits. The size and position of a dot can be specified by 10 values. Although each value can be represented by 4 bits, this causes the problems that the size and position of a dot cannot be independently assigned to outputs of the units in the output layer, the number of the units in the hidden layer must be increased to 30 units, and the neural network is operated at a lower speed. Figure 19 shows the configuration of the system of the embodiment 1 of the image forming apparatus according to the first principle of the present invention. Neurons forming the neural network are configured by hardware. Figure 20 is a timing chart for explaining the operation of the system shown in Figure 19 . The process of inputted dot image data in 3x5 window units is described below by referring to Figures 19 and 20 . In Figure 19 , input data from a bit map memory are provided for a data segmenter 20. One-line data in the bit map memory are given to either of the three line buffers 21a - 21c. If the present process line is given to line buffer 21b, the data in the lines above and below the present line are given to line buffers 21a and 21c respectively when the picture elements in the present line are processed. Thus, the picture elements in the necessary 3 lines are successfully given to line buffers 21a - 21c. The data stored in line buffers 21a - 21c are loaded in 5-bit units to shift registers (SR) 22a - 22c respectively. These 3 shift registers are serially connected, and the loaded data are serially processed bit by bit by the data segmenter 20. Thus, a piece of dot matrix data in a 3x5 window are outputted by the data segmenter 20 to the input layer (not shown in Figure 19 ) of the neural network. The outputs from these shift registers can be processed sequentially. Dot image data outputted from the data segmenter 20 are simultaneously provided bit by bit for 16 neurons 24a - 24p forming the hidden layer of the neural network. The neurons 24a - 24p in the hidden layer have the same configuration except that each neuron is assigned a different coefficient value, and are operated concurrently. A coefficient assigned to each neuron forming the intermediate and output layers of the neural network is determined according to the result of predetermined learning. The value of a coefficient is set in coefficient buffers 25 and 33 in the intermediate and output layers before a series of jag reducing processes performed by the neural network. The constant term in expression (1) is also preset in these registers at the initialization of resisters 28 and 36. Next, the hidden layer is explained below. Arithmetic operations performed by the hidden layer are similar to expression (1). However, since it is given an input "0" or "1", a sum of products can be obtained without performing multiplications by only incrementing the coefficient if "1" and not incrementing it if "0". That is, an inputted value determines whether or not the value stored in the coefficient buffer 25 is added. Therefore, an AND gate 26 is used as a circuit for obtaining a sum-of-products. Dot data in shift registers 22a - 22c are inputted bit by bit to one of the input terminals of the AND gate. Each bit of the coefficient assigned corresponding to each dot position in a 3x5 window is inputted to the other input terminal of the AND gate 26 in synchronous with each bit outputted from shift registers 22a - 22c. The AND gate 26 outputs "0" or a coefficient according to a value in each bit outputted by shift registers 22a - 22c. The content of the coefficient buffer 25 is explained later. An adder 27 and a register 28 in the next step are used in adding an output from the AND gate 26. After multiplying 15 pieces of dot data by a coefficient and obtaining the sum of those multiplications, the addition result is loaded to a register 29. The content of the register 29 is set in a three-state register 31 after the conversion by a sigmoid function stored in ROM 30 in the next step. A value set in the three-state register 31 in each neuron is scanned by sequentially setting an output ennoble (OE) as shown in Figure 20 , and sequentially inputted to the output layer. Each neuron in the output layer multiplies an output from the hidden layer by a coefficient set in each neuron in the output layer, and sets the result in the register 36 through the adder 35. A value in the register 36 is provided for the register 37 after obtaining the sum of products obtained by multiplying each output in the hidden layer by a coefficient. Since the output from the output layer as well as the input to the hidden layer is represented in binary, that is, by "1" or "0", the output from the output layer having a positive value is "1", and the output having a negative value is "0" if the slice level of the output from the output layer is set to "0". Therefore, the highest order bit (sign bit) can be outputted from the register 37 although the value set in the register 37 should be processed with a Sigmoid function. An output obtained by combining 5 output values finally corresponds to one of ten 5-bit strings shown in Figure 18 according to the dot image data array inputted to the neural network. Accordingly, a controller of a printer drives an exposure element in an optical unit through an image quality correcting circuit such that a dot can be formed at the position of the central picture element in the window according to the combination of above described 5 output values. This process is performed on each picture element in the present process line. On finishing the process for one line, the data of the next line and the adjacent lines are provided for line buffers 21a - 21c to continue the similar process. Thus, picture elements of 1-page dot data stored in the bit map memory and outputted on the printer can be corrected by sequentially repeating the above described operation. In Figure 19 , the contents of the coefficient buffer 25 in an hidden layer neuron and of a coefficient buffer 33 in an output layer neuron are determined by a simulation, that is, a learning by the back propagation method. Figure 21 shows an example of a correction pattern for a 3x5 dot window, that is, teaching data. In Figure 21 , an arrangement above an arrow indicates inputted data, and that below an arrow indicates a correction pattern, that is, a teaching pattern for the inputted pattern. In Figure 21 , the upper teaching patterns are for a vertical oblique line. For example, the leftmost teaching pattern indicates that the dot for the central picture element should be moved to left by 1/3 dot. In this teaching pattern, a pale black circle indicates a picture element which is not to be corrected in this process. The middle teaching patterns in Figure 21 indicate a process of reducing jags in a horizontal oblique line. The size of a corrected dot is 60% of the original size shown in Figure 16 . The two teaching patterns at the lower right corner indicate that a corrected dot is 30% of the original size shown in Figure 16 in reducing the jags in a horizontal oblique line. After this correction, the jags in the horizontal oblique line can be successfully reduced by forming a 60%-size dot for the circle right to the central circle as shown in the middle teaching patterns. Figure 22 as well as Figure 21 shows correction patterns, that is, teaching patterns, for reducing jags in images. In Figure 22 , the second teaching pattern in the upper group, for example, indicates a 60%-diameter dot at the intersection of the vertical and horizontal black lines in order to prevent an excessive toner thereon. Figure 23 is a flowchart for explaining an embodiment of learning by the back propagation method. In step S1, a combination of an inputted pattern and its teaching pattern is determined. In step S2, a coefficient of a neural network, that is, an initial coefficient is appropriately determined using a random number. Next, in step S3, an inputted pattern is applied to the neural network. In step S4, determination is made as to whether or not the output of the network coincides with an anticipated output, that is, its teaching pattern. If not, the predetermined coefficient is corrected according to a predetermined expression in step S5, and the processes from the process in step S3 are repeated until a coincident result is detected in step S4. This learning process is performed to obtain a coefficient which is used in the actual operation shown in Figure 19 , for example. Figure 24 shows an example of an erroneous correction during learning. The central picture element in the window being processed should have been assigned a 60%-size dot. Figure 25 shows an example of a correction to an inputted pattern not exactly corresponding to its learning pattern. After learning, the inputted pattern shown in Figure 24 is given a 60%-size dot formed at the center of the window as shown in Figure 24 . The same correction can be made by the neural network to an inputted pattern as shown in Figure 25 in which a black dot in the third line is shifted to left by one dot. Figure 26 shows an example of a correction of a character and a slanted straight line. A pale black dot indicates a dot having a position different from its original position, that is, having different exposure timing. Figure 27 shows a table containing coefficients for neurons in the hidden layer, that is, coefficients after learning. In Figure 27 , the leftmost numbers from 1 through 16 indicate 16 neurons in the hidden layer. The uppermost numbers 1 through 15 indicate 15 coefficients stored in the coefficient buffer 25. Each number corresponds to a picture element number shown in Figure 14 . Figure 28 , like Figure 27 , shows a table of coefficients for neurons in the output layer after learning. The number of neurons in the output layer is 5, and 16 coefficients corresponding to the 16 neurons in the hidden layer are stored in the coefficient buffer 33. Figure 29 shows an embodiment of an image data flow. In Figure 29A , image data are applied from a computer 200 to a bit map memory 201, and the data are applied to a neural network 202. If the neural network 202 has enough throughput, its output data are applied directly to a print head 203 of a laser printer, and image data can be corrected on real time. In Figure 29B , since a neural network 204 does not have such high throughput, its output data are temporarily stored in a bit map memory 205, and then outputted to a print head 206. If the bit map memory 201 before the neural network 204 is designed for 300dpi, the bit map memory 205 corresponds to 900dpi. P16 Figure 30 shows an example of a picture element represented by 5 sizes. It is specified by 100% indicating the maximum dot diameter, 75%, 50%, 25%, and 0%. As described above, the position of a dot is shifted by a neural network to right or left by 1/3 dot, that is, converted from 300dpi down to 900dpi. However, the conversion is not limited to this application, but it can be made by combining different density of picture elements. Therefore, the position of a picture element can be shifted in the vertical scanning direction as well as horizontal scanning direction. That is, if the dot position is physically fixed in the horizontal direction like in a thermal head, the form feed pitch can be made higher in the vertical scanning direction. Figure 31 shows the second embodiment of the image forming apparatus of the first principle of the present invention. Different points between the embodiment shown in Figures 19 and Figure 20 are described below. Since the operational timing chart of the embodiment is similar to that shown in Figure 20 , the explanation about it is omitted here. Similar operations in Figures 31 and 19 are assigned the same number. In Figure 31 , the operation of the data segmenter 20 is the same as that shown in Figure 19 , and dot image data in a window are simultaneously applied bit by bit to 24 neurons 24a - 24x in the hidden layer. The second embodiment corresponds to the second object of the present invention in which a coefficient of input connection to a neuron in the hidden layer is represented by a small number of bits. The operation of a neuron in the hidden layer is explained below. The arithmetic operation performed in the hidden layer is shown by expression (1). This operation is performed by 24 neurons in the hidden layer separately and concurrently. One-bit data of either "1" (black) or "0" (white) are applied as a picture element to each of the neurons in the hidden layer from the data segmenter. The inputted data and a coefficient stored in the coefficient buffer 25, that is, a coefficient, are applied to two AND gates 26a and 26b provided instead of the AND gate 26 shown in Figure 19 . The content of the coefficient buffer 25 is one of the values +1, -1, and 0. They are represented by 2 bits: +1 by "01", -1 by "11", and 0 by "00". The 2-bit representation of a coefficient requires the two AND gates 26a and 26b. The coefficient for a black dot (for example, the second dot in the first line shown in Figure 9) is +1, that is, "01", and the coefficient for a white dot is 11, and the coefficient for a don't care data is 00. Since an output from the AND gate 26a is a sign bit, it is applied to the adder 27 as 4 higher order bits. The content of the adder 27 is incremented when "black" is inputted to the dot corresponding to the coefficient 01 indicating "black", and the content of the adder 27 is decremented when "black" is inputted to the dot corresponding to the coefficient 11 indicating "white". In response to 15 inputs, the output from the adder 27 comes in the range of -15 through +15, and the number of bits outputted from the adder 27 can be 5 bits including a sign bit. The adder 27 performs an addition each time 1-bit data are inputted from the data segmenter 20, and outputs the result to the register 28. When the next data are inputted, the content in the register 28 is added to the content in the adder 27 together with the outputs from the AND gates 26a and 26b, and the result is stored in the register 28 again. After repeating this operation for each of the 15 input data, the final result as a sum of products is stored in the register 28. The value is then stored in the register 29, and the function stored in the ROM 30 in the next step, e.g. a step function, performs a transformation, that is, a scaling, and the transformation result is stored in the three-state register 31. The above described process is a cycle of the operation performed by the neurons in the hidden layer in response to inputted data in a window. Since the 24 neurons in the hidden layer perform their operations concurrently, the contents in the three-state registers 31 are simultaneously determined. The output of data from the hidden layer to the output layer and the operation of the neurons in the output layer are the same as those shown in Figure 19 . Therefore, the explanation about them are omitted here. Figure 32 shows an embodiment of a coefficient of input connection, that is, a coefficient, to a neuron in the hidden layer. The leftmost numbers 1 through 24 indicate the numbers of 24 neurons in the hidden layer, and the uppermost numbers 1 through 15 indicate the numbers of 15 inputs, that is, the input numbers for each dot shown in Figure 9 (the same numbers shown in Figure 14 ). The constant term indicates the constant term k 0 n in expression (1). In the present invention, each of the 24 neurons in the hidden layer detects a specific correction pattern. For example, in Figure 32 , the second neuron detects the pattern shown in Figure 9 where the second neuron indicates coefficient 1 for the input "black", -1 for the input "white", and 0 for the input "don't care". When the pattern shown in Figure 9 is inputted, the sum of products obtained by the second neuron equals the number of dots indicating black, resulting in +3. This is added to the constant term -3, resulting in 0. By detecting the resultant 0 using a comparator, for example, instead of a scaling by the ROM 30, the output of the second neuron is 1. Since the pattern shown in Figure 9 contains 8 don't care dots, 256 patterns can be corrected by a neuron in the hidden layer, that is, the second neuron therein. It is not required that all the 256 corrections are learned during the learning by the neural network. Even an unlearned pattern can be corrected only by the learning of 9 patterns comprising combinations, for example, 8 white dots, only one black dot in the combination, etc. However, all dots other than don't care dots are specified to either black or white dots in a correction pattern. Figure 33 is a configurational block diagram of the neurons in the hidden layer of the third embodiment of the image forming apparatus of the first principle. In the third embodiment, the data segmenter 20 and the neurons 32a - 32e in the output layer are the same in configuration as those shown in Figure 31 . In the third embodiment shown in Figure 33 , an up-down counter 43, instead of the adder 27, calculates a sum of products. The content in a coefficient buffer 40 is the same as that in the coefficient buffer 25 of the second embodiment. The up-down counter 43 is controlled by a decoder 42. The decoder 42 controls the up-down counter 43 such that it counts up when the output from AND gates 41a and 41b is "01", counts down when it is "11", and holds the present count when it is "00". As shown in the second embodiment, when "black" is inputted to a black dot having coefficient 01, the content in the up-down counter 43 is counted up, and it is counted down when "black" is inputted to a white dot having coefficient 11. After the up-down counter 43 counts in response to 15 inputs, the content is stored in a register 44, a scaling is performed by a ROM 45, and the transformation result is outputted to the neurons in the output layer through the three-state register 46. Figure 34 is a configurational block diagram of the neurons in the hidden layer of the fourth embodiment of the first principle. In this embodiment, the data segmenter and the neurons in the output layer are the same in configuration as those of the second embodiment. However, unlike the above described embodiments, two inputs A and A are applied in response to the input from the data segmenter in the fourth embodiment. The input A indicates a non-interted input which is an input as is, and the input A indicates an inverted input obtained through an inverted 49. The two inputs A and A are applied to a selector 50, either of which is selected according to a control signal from a selection controller 51. The selection result is applied to an AND gate 53 together with the content of a coefficient buffer 52, and the output from the AND gate is applied to an adder 54. An input to the adder 54 is, like in the first embodiment, added to the content in a register 55, and the result is stored in a register 55. This operation is repeated for each of the 15 inputs, and the final sum of products are stored in a register 56. Then, a ROM 57 performs a scaling, and the transformation result is applied to a neuron in the output layer through a three-state register 58. Figure 35 shows an embodiment of a selection control signal applied to the selector 50 and a coefficient stored in the coefficient buffer 52 as shown in Figure 34 . The selection controller 51 outputs a selection control signal value "0" to select a non-interted input A for the position of a black dot, and "1" to select an inverted input A for the position of a white dot. In the coefficient buffer 52, the coefficient is set to 1 for the non-interted input A indicating a black dot position and for the inverted input A indicating a white dot position. Otherwise, the coefficient is set to 0, that is, for a don't care dot position. The coefficient and the value of a selection control signal shown in Figure 35 are applied to the correction pattern shown in Figure 9. A dot number indicates an input number, and the coefficient is set to 0, that is, the value of the selection control signal for a don't care dot is 0 to select a right signal. Figure 37 is a block diagram for explaining the configuration of the selection controller 51 shown in Figure 34 . The selection controller comprises a counter 59a and a read only memory (ROM) 59b. The counter 59a is reset when image data are loaded from the line buffer 21 to the shift register 22. Its value is stepped up each time 1-bit data are applied from the shift register 22 to a neuron in the hidden layer shown in Figure 34 through the input layer. The output value of the counter 59a is applied as an address signal to the ROM 59b. According to this address, the ROM 59b outputs a selection control signal described above by referring to Figure 35 . That is, an address in the ROM 59b corresponds to the dot number shown in Figure 35 . As described above, a neuron in the hidden layer corresponds to a pattern to be detected, and the dot position of white/black/don't care is predetermined. A selection control signal is outputted according to this position. The fourth embodiment shown in Figure 34 is different from the third embodiment shown in Figure 33 in an addition result performed by the adder 54 when inputted data coincide with a pattern to be detected. In the third embodiment, the maximum value of the addition result indicates the number of dots to generate a black picture element. In the fourth embodiment, it indicates the number to generate black and white picture elements. For example, when the pattern shown in Figure 9 is detected, the addition result obtained by the up-down counter in a neuron in the hidden layer indicates "3" in the third embodiment. By contrast, in the fourth embodiment, the result indicates "7". In the fourth embodiment shown in Figure 34 , since the coefficient in the coefficient buffer 52 occupies only 1 bit, this embodiment reduces the scale of the sum-of-products operating circuit more effectively than the second embodiment shown in Figure 31 and the third embodiment shown in Figure 33 each having a 2-bit coefficient. The general configuration of an image forming apparatus, or a printer, is described below. In this connection, the explanation is given about the generation of an actual exposure pulse from the correction data, outputted from the above described neural network, of the size and position of the central dot in a window. Figure 37 is a general configurational block diagram of the printer. The printer comprises a controller 60, an image quality correcting circuit 61, and a printing mechanism 62. Among them, the image quality correcting circuit 61 is described later. The controller 60 comprises a processor MPU 63 for controlling the whole mechanism, a ROM 64 for storing a program, a character font ROM 65, a working RAM 66, a bit map expanded page memory RAM 67, a host computer interface 68 for receiving printing data, etc. from a host computer, a first-in-first-out (FIFO) memory 69 for storing printing data, etc., a shift register 70, a control panel 71, and an input interface circuit 72. The printing mechanism 62 comprises a power source 74 for supplying electric power, a mechanical controller 75, an optical unit 76, a process unit 77, a motor 78, etc. The mechanical controller 75 comprises a motor driving circuit 79, a sensor interface circuit 80, etc. The optical unit 76 comprises a laser diode for emitting a laser light, a polygon mirror for deflecting and scanning the laser light, an f-  lens for performing a scanning operation along the surface of a photoconductive object by the laser light at a constant speed, a photosensor for detecting the arrival of the scanning light at the end of the starting side of the area scanned by the scanning light through the polygon mirror, etc. The process unit 77 also contains a photoconductive drum on which a scanning light emitted from the optical unit 76 is irradiated to form a electrostatic latent image, a developer for generating a toner image from the electrostatic latent image, a transfer charger unit for transferring the toner image to a print form, a cleaner for removing the residual toner on the photoconductive drum, a fuser stabilizing roller for stabilizing the toner image on the print form, etc. The motor 78 revolves the photoconductive drum and the thermal stabilizing roller. A detection output of the photosensor in the optical unit 76 is outputted as a beam detect (BD) signal to the controller 60 and the image quality correcting circuit 61. The exposure pulse signal whose pulse width is corrected is outputted by the image quality correcting circuit 61 and applied to the laser diode in the optical unit 76. A bit map memory 201 to a RAM 67 for bit map expansion; a neural network 202 to a neuro 84; and a head 203 to a laser diode in the optical unit 76. Figure 38 is a detailed configurational block diagram of the image quality correcting circuit shown in Figure 37 . The image quality correcting circuit comprises a latch circuit 81 for receiving a video signal, that is, an input image signal from the controller 60, a two-port random access memory (RAM) 82 positioned after the latch circuit 81, shift registers 83a - 83n for performing a serial/parallel conversion on data outputted from the RAM 82 to produce window data, a neural network (neuro) 84 for receiving by a unit in the input layer an output from the shift registers and outputting correction data for the central picture element in a window, a two-port RAM 85 for storing an output from the neural network 84, a latch 86 for receiving an output from the two-port RAM 85, a pulse width correcting circuit 87 for outputting an exposure pulse correction signal to the optical unit 76 in the printing mechanism 62 according to the output from the two-port RAM 85 and the latch 86, a counter 88 for controlling the read/write address of the two-port RAM 82 on the side of the latch 81 and of the RAM 85 on the side of the latch 86, a counter 89 for controlling the write/read address of the RAM 82 on the side of the shift register and of the RAM 85 on the side of the neural network, and a general controller 90. Figure 39 is a block diagram for explaining the 1-line data input from the controller 60 to the RAM 82. The data input is described by referring to the connection chart indicating the connection between the latch 81 and the two-port RAM 82. In the following explanation, the size of a window for outputting correction data for the central picture element is 5x4. In Figure 39 , the content of the above described RAM 82 indicates the current value. For example, bits 0 - 4 at addresses n - 1 store data "a,b,c,d,e". Each of bits 0 - 4 corresponds to 1-line data in an image. The data in bit 0 are stored last in the RAM 82. After a predetermined time passes from BD (beam detection), the contents of the RAM 82 are sequentially read from address 0 and inputted to the latch 81. At this time, the RAM 82 and the latch 81 are connected such that data are shifted bit by bit as shown in Figure 40 . For example, "e" are overflown from the data at address n-1, and thus the data "a,b,c,d" are stored. At this time, the data "v" at address n-1 are inputted from the side of the controller 60 to the input Do to the latch 81. These data are stored in the RAM 82 again through the latch 81. The 1-line data inputted by repeating this operation for 1 line are stored in the RAM 82 at the position of bit 0. The data stored at bits 1 - 4 indicate the data stored in a line newly stored according to the order of bit numbers. Data are stored from left to right starting with the data closest to the start-of-print position in each line according to the addresses of the RAM 82. The data in the RAM 82 are cleared by continuously writing "0" while scanning the out-of-area space prior to printing. As shown in Figure 38 , the neural network 84 processes the data in a window comprising 5 lines each comprising 4 picture elements, for example, preceded by the data input from the RAM 82 to the shift registers 83a - 83n. Figure 41 is a block diagram for explaining the data input to the shift register. Assuming that a window to be processed starts with address n-1 in the RAM 82, the data "A,B,C,D,E" at bits 0 - 4 at the address are inputted to 5 shift registers respectively. Next, the data at address n are inputted to 5 shift registers. At this time, the data positioned at address n-1 are shifted in the shift registers. Figure 42 shows the connection between the RAM 82 and the shift registers 83a - 83n. The data are sequentially outputted from the RAM 82 in serial in bit units in the order of address, applied to the shift registers corresponding to the bit positions, and stored after sequentially shifted downwards in Figure 42 . When data in a window are stored in the shift registers, the shift registers 83a - 83n output data to the neural network as shown in Figure 38 . Since the data are outputted in parallel, each of the shift registers converts data in serial/parallel. The input/output of data to the shift registers is performed at the process speed of the neural network. In Figure 38 , it is controlled by a count value generated by the counter 89. Since common neural networks do not process data at a very high speed generally, data are applied to the neural network 84 at the timing regardless of, for example, the image data input to the RAM82, that is, the data input performed at the timing specified by a count value generated by the counter 88. The data in the shift registers 83a - 83n are cleared at the beginning of each line. The process result of the neural network 84, that is, the correction data of the size and position (shift) of a dot for the central picture element, is outputted to the latch 86 and the pulse width correcting circuit 87 through the RAM 85. The RAM 85 is used, like its input side, to adjust the timing between the neural network 84 and the exposure pulse correction signal output. In this embodiment, the correction data for the central picture element outputted by the neuro 84 comprise a total of 6 bits: 4 sizing bits and 2 position (shift) bits. Figure 43 is a configurational block diagram of the pulse width correcting circuit 87 shown in Figure 38 . The pulse width correcting circuit 87 comprises the read only memory (ROM) 88 and the shift register 89. The ROM 88 receives as an address a total of 12 bits (6-bit output from the latch 86 and 6-bit output directly from the RAM 85 without the latch 86). The shift register 89 receives the output from the ROM 88 and outputs an exposure pulse correction signal after performing a parallel/serial conversion on the inputted data. The output from the RAM 88 comes in 16 bits when a subdot pattern comprises 16 subdots. Figure 44 shows an example of a exposure pulse according to the specified size and shift of dots. Figure 44A shows an exposure pulse for a dot of 8/8 in size and positioned in the center, that is, a dot of the maximum size at the original position. At this time, the exposure signal indicates "1" in its 8 bits. When a dot is 2/8 in size and positioned in the center as shown in Figure 44B , the exposure pulse correction signal indicates "1" in its 4th and 5th bits in center and "0" in the other bits. Figure 44C shows a right-shifted dot of 8/8 in size, and its correction signal indicates "0" in its 1st - 3rd bits, and "1" in its 4th - 8th bits. Since this signal is issued for the present window, and the values are all "1" in its 8 bits as shown in Figure 44A when the original dot size is specified as 8/8, the value of 1 for the remaining 3 bits must be outputted when an exposure pulse correction signal is outputted for the next window. For a right-shifted dot of 4/8 in size as shown in Figure 44D , a rightmost overflowing bit must be outputted when a correction signal for the next window is outputted. Figure 45 shows an example of an exposure pulse correction signal after combining the present dot data and the remaining data for the preceding window dots. As shown in Figure 43 , a read address of the ROM 88 comprises size and shift specification data for the central dot in the preceding window stored in the latch 86 and size and shift specification data for the central dot in the present window applied directly from the RAM 85. The ROM 87a stores an exposure pulse correction signal outputted after combining the data according to the address, and the data are outputted as a serial signal to the optical unit 76 through the shift register 87b. Figure 46 is an operational timing chart for the image correcting circuit. When a beam detection signal (BD) indicating that the start of printing paper is detected is inputted, the counters 88 and 89 shown in Figure 38 are reset, and data are inputted from the controller 60 shown in Figure 37 to the RAM 82 shown in Figure 38 according to a video data clock (VDCLK). At this time, a line address is specified by the counter 88. When 1-line data are written, any writing operation is disabled until the next BD signal is inputted to prevent out-of-area data from being written. Addresses 0 through 2047 indicate write addresses for one line. Data are outputted from the RAM 82 to the neuro 84 when a BD signal is inputted. The input is performed at the timing later than that of the data input to the RAM 82. Size-and-shift data of a dot are outputted to the RAM 85 each time a process for a window is completed by the neuro 84. They are outputted according to a count value provided by the counter 89. At this time, the RAM 85 stores size-and-shift data of a dot as correction data for one line, and the data are outputted to the latch 86 and the pulse width correcting circuit 87 at the timing of the data input from the controller to the RAM 82, that is, according to a count value outputted by the counter 88. Next, explanation is given below about the second principle of the present invention, that is, an embodiment in which a subdot pattern is outputted as correction data for the central dot in a window. The subdot pattern described by referring to Figure 7 corresponds to an exposure pulse correction signal described by referring to Figure 44 , that is, an exposure pattern. The black portion in the subdot pattern indicates the position where a exposure pulse is ON. Figure 47 shows a system configuration of the first embodiment of the image forming apparatus according to the second principle of the present invention. A neuron forming a neural network is realized by hardware like in the first principle of the present invention. Since the system shown in Figure 47 is similar to the embodiment of the first principle shown in Figure 19 in configuration, the explanation is given by emphasizing different points between them. In this embodiment, a window comprises 7 lines each comprising 9 picture elements, and 63 dots of image data are provided bit by bit from connected 9-bit shift registers 91a - 91g, a part of the data segmenter, for all neurons in the hidden layer through the neurons (not shown) in the input layer. A presetting to a neuron of a constant term in expression (1) is omitted in the drawing. In the hidden layer, the system shown in Figure 47 differs from the embodiment shown in Figure 19 in that the number of neurons is 22 and the number of coefficients in the coefficient buffer 25 is 63 in the hidden layer, and in that the number of neurons is 8 and the number of coefficients in the coefficient buffer 33 is 22 in the output layer. The operational timing chart for the system is similar to that shown in Figure 20 , and thus the explanation is omitted here. In the above described configuration, a neural network comprising input, intermediate, and output layers performs an arithmetic operation using each picture element and coefficient data each time 7x9 dots in which the central picture element is set as a picture element to be corrected, that is, a total of 63-picture-element data, are inputted. Then, a neuron in the output layer performs an arithmetic operation using output data from a neuron in the hidden layer and coefficient data stored in the coefficient buffer 33. Eight neurons in the output layer outputs the optimum subdot pattern corresponding to a pattern of the array of picture elements in dot image data inputted to the neural network. The pattern is outputted to the print head controller (not shown in the figure) as the data indicating the central picture element in a 7x9 window. The optimum subdot pattern is one of the 28 pattern shown in Figure 7. Figures 50 - 58 show the relationship between a pattern applied to the neural network in the embodiment shown in Figure 49 and a teaching pattern for the inputted pattern. Patterns above each arrow are inputted patterns and those below it are teaching patterns and enlarged subdot patterns. As shown in Figure 48A ., the central picture element in a 7x9 window of a teaching pattern is converted to black at its 3 rightmost subdots out of 8 subdots although the central picture element in the inputted pattern is white. As shown in Figure 48B , an inputted pattern made by shifting bit by bit the inputted pattern shown in Figure 48A to left by 1 dot indicates "black" in the central picture element in the inputted pattern. However, the rightmost 3/8 subdots of the central picture element are converted to white. Accordingly, the jags shown in Figures 48A and 48B can be removed from the inputted pattern by having the teaching pattern shown in Figures 48A and 48B successfully learned. Figure 49A shows an example in which a central picture element to be displayed as black is converted to white at its leftmost 3/8 subdots. Figure 49B shows an example in which a central picture element to be displayed as black is outputted as is. Figure 50A shows an example in which a central picture element to be displayed as white is converted to black at its 4 central subdots. Figure 50B shows an example in which a central picture element to be displayed as black is converted to white at its subdots at both ends. In the example shown in Figure 50B , when a picture element one element to the right of the central picture element is determined to be the central picture element, 2 subdots each on both ends, that is, a total of 4 subdots, out of 8 subdots are converted to white. The next picture element to the right is white, but converted to black at its 2 central subdots, and each dot is corrected such that its size is gradually varied. Figures 51A and 51B show an example in which a central picture element to be displayed as white is converted to black at some of its central subdots out of 8 subdots. Figures 51A and 51B shows an example similar to that shown in Figure 50B in which picture elements adjacent to the central picture element are converted such that they are displayed as small dots. Figure 52 shows a pattern obtained by performing a correction shown in Figures 48 - 51 on a character and a straight line. Pale black dots indicate that the position and size, that is, the exposure timing, of a dot is corrected. Figure 53 shows a system configuration of the second embodiment of the image forming apparatus according to the second principle of the present invention. The number of coefficients in the hidden layer in the neural network is 2 bits, different from that of the embodiment shown in Figure 47 . This configuration can be realized by that the coefficient of the input connection to a neuron in the hidden layer in the neural network can be converged to one of the three values: +1, -1, or 0 as described above by referring to Figure 31 showing the second embodiment according to the first principle of the present invention. That is, the coefficients can be represented by a 2-bit number: 01 for +1, 11 for -1, and 00 for 0 with a higher bit set as a sign bit. Among these coefficients, a black picture element, a white picture element, and a don't care picture element are set to 01, 11, and 00 respectively. The number of neurons in the hidden layer is set to 60 and correction can be made to 60 inputted pattern. The number of neurons in the output layer is set to 8 such that 8 subdots can be outputted as in the embodiment shown in Figure 47 . The operation with the system configuration of the second embodiment is described below. First, data (1 for black and 0 for white) of each picture element in a 7x9-dot window, that is, 63-bit picture element data, are stored from the data segmenter (not shown in Figure 53 ) to the shift register before the hidden layer. Then, the 63-bit picture element data in the shift register are simultaneously applied to each of the neurons 95-1 - 95-60 in the hidden layer of the neural network through the neurons in the input layer not shown in the figure. Two AND gates 96a and 96b are provided in each of neurons 95-1 - 95-60 for one picture element. Accordingly, each of neurons 95-1 - 95-60 comprises a total of 126 AND gates 96a-1 - 96b-63. A 2-bit coefficient obtained by a learning for each picture element position is inputted to AND gates 96a - 96b, each bit being inputted to each terminal. Therefore, AND gates 96a and 96b multiply picture element data by a coefficient. As shown in Figure 31 , the neurons in the hidden layer are provided for detecting a specific pattern. Since a coefficient is set to 00 for a don't-care picture element in the pattern, the output from AND gates 96a and 96b is always 0, thereby never affecting the result of an addition. Accordingly, AND gate circuits for don't care picture elements can be omitted from neurons 95-1 - 95-60 including their connection lines. This means that the number of bits applied to an adder 97 is 126 bits at maximum, but it can be reduced depending on the number of omitted AND gates. The content in the adder 97 is incremented if image data to be displayed as black, that is, "1" is applied to an AND gate in which "01" is set as its coefficient. The adder 97 is decremented if "black", that is, data "1" is applied to an AND gate in which "11" is set as its coefficient. The adder 97 comprises a plurality of adders for adding outputs from adjacent AND gates and those for adding outputs from adjacent adders, all these adders being configured in the form of a pyramid. It is determined after checking the correction patterns that about 20 bits out of 63 bits of picture elements should be either white or black. Therefore, an output from the adder 97 is within the range -20 - +20, and the number of bits outputted from the adder 97 can be only 6 bits including a sign bit. The sum of products for the 63-bit inputted data is provided for a register 99, and processed by a Sigmoid function or a step function, that is, a scaling. The transformation result is stored in a register 101. An output from each neuron in the hidden layer can be represented by 1 or 0, that is, by 1 bit to output the existence of a specific pattern. The above described process corresponds to one cycle of the operation of neurons in the hidden layer performed on 1-window data. Since 60 neurons 95-1 - 95-60 in the hidden layer are operated concurrently, the content in the register 101 is determined simultaneously for all neurons in the hidden layer. The operation of neurons 102-1 - 102-8 in the output layer is almost the same as that of neurons in the hidden layer. That is, outputs of a total of 60 bits from 60 neurons 95-1 - 95-60 in the hidden layer are simultaneously inputted to 8 neurons 102-1 - 102-8 in the output layer. Each of neurons 102-1 - 102-8 in the output layer is provided with 60 AND gate circuits 103-1 - 103-60. A coefficient of 1 or 0 is inputted to one of the input terminals of each AND gate circuit 103. Each AND gate circuit 103 multiplies an output received from a neuron in the hidden layer by this coefficient. The result is added by an adder 104. The addition result of each of the neurons 102-1 - 102-8 in the output layer is stored in registers 105 and 106 in neurons 102-1 - 102-8, and synchronously outputted in 8-bit units to a print head controller. A coefficient inputted to one input terminal of the AND gate 103 in a neuron in the output layer occupies 1 bit because a neuron in the hidden layer corresponds to a pattern to be detected. That is, if an inputted image pattern is set in a neuron in the hidden layer, a value anticipated as an output from a neuron in the output layer is used "as is" as a coefficient value. This can be realized by a 1-bit output from a neuron in the output layer and by an exclusive pattern assigned to a neuron in the hidden layer. Figure 54 is an operational timing chart for explaining the second embodiment shown in Figure 53 . If 63 bits of window image data are applied simultaneously to neurons 95 in the hidden layer as shown in Figure 54 , the adder 97 obtains an addition result from these input data, the result is stored in the register 99 at the timing A, the scaling result obtained by the ROM 100 is stored in the register 101 at the timing B, and thus the output from the neuron in the hidden layer is determined. Each of the neurons 102 in the output layer performs an arithmetic operation using the determined output from the neurons in the hidden layer, the result is stored in the register 105 at the timing C, and the determined output from the neurons in the output layer is transmitted to the print head controller at the timing D. Figure 55 is a block diagram for explaining the configuration of the adder 97 in a neuron in the hidden layer and the adder 104 in a neuron in the output layer shown in Figure 53 . As shown in Figure 55 , a plurality of adders (for obtaining a sum of A and B) are connected in the form of a pyramid in which a constant term in expression (1) and, for example, an output from sixty AND gates 103-1 - 103-60 in a neuron when the adders are in a neuron in the output layer are applied to the adder in the first stage. The addition results are converged through a plurality of adders, and the final result is outputted from the adder in the top stage. Figures 56 and 57 shows the coefficient of input connection to neurons 95-1 - 95-60 in the hidden layer, that is, a coefficient, after learning. The leftmost numbers 1 - 60 indicate a number of a neuron in the hidden layer; the numbers 1 - 63 in the uppermost line indicate a total of 63 inputs, that is, a number of input to each dot shown in Figure 15 and a constant term k o n in expression (1). For readability, signs + and - are not used except in the constant term. Thus, 2 indicates a coefficient 0; 0 indicates a coefficient -1; and 1 indicates a coefficient +1. The pattern shown in Figure 58 indicates a pattern detected by one of the 60 neurons in the hidden layer, for example, the 25th neuron shown in Figures 56 and 57 . Since this pattern contains 56 don't care dots, the 25th neuron can perform a correction on 7x10 16 patterns. The learning process is not required for all the above described patterns in the learning process in the neural network. For example, an unlearned pattern can be corrected by repeating a learning process for 57 patterns containing all 56 don't care dots indicating "white" or containing any one dot indicating "black". In this case, the similarity of an inputted picture element pattern to its teaching pattern can be restricted optionally according to the transformation characteristic of a Sigmoid function or a step function. Figure 59 shows the system configuration of the third embodiment of the image forming apparatus according to the second principle of the present invention. In this embodiment, the configuration of and after the output layer is the same as that of the second embodiment shown in Figure 53 . Therefore, the explanation and figures involved are omitted here. The embodiment shown in Figure 59 is different from that shown in Figure 53 in that in response to 63-bit inputted dot image data from the data segmenter (not shown in Figure 59 ), a total of 126 bits comprising a non-interted input A which is an inputted dot image data value as is, that is, an output from a register 111, and an inverted image *A which is obtained by inverting the inputted dot image data value by, for example, an inverter 112 are applied in parallel to neurons 115-1 - 115-60 in the hidden layer, and in that a binary number 1 or 0 occupying 1 bit is applied as a coefficient to 126 AND gates 116-1 - 116-126 in 60 neurons 115-1 - 115-60 in the hidden layer. Therefore, 126-bit data are outputted from the input layer 110 and 126-bit data are determined simultaneously and outputted to neurons 115-1 - 115-60 in the hidden layer. A constant used in this embodiment of a picture element to be displayed as black is "1" for a non-interted input A, and that of a picture element to be displayed as white and don't-care is "0" for an inverted input * A. That is, since each bit for a non-interted input A and an inverted input *A is simultaneously and independently inputted in parallel to each neuron, the above described settings are effective, causing no problems at all. Defining a coefficient as described above enables the coefficient for each of the 60 neurons in the hidden layer to be represented by 1 bit. An output from an AND gate for a coefficient 0 and a non-interted input A or an inverted input *A always results in "0", never affecting the result of an addition at all. Therefore, an AND gate including its connection line can be omitted for inputted data having a coefficient of 0. Since the coefficient occupies 1 bit without a sign, an output from an adder 117 is within the range of 0 - 20, and the number of output bits of the adder 117 is 5. Figure 60 shows the system configuration of the fourth embodiment of the image forming apparatus according to the second principle of the present invention. The input layer shown in Figure 60 is the same as the input layer 110 shown in Figure 59 . The input layer applies to each of the neurons in the hidden layer of the neural network a total of 126 bits of the non-interted input A and the inverted input *A of 63-bit inputted dot image data provided by the data segmenter (not shown in Figure 60 ). The neural network is provided with 15 neurons 121-1 - 121-15 in the hidden layer. Each of the neurons 121-1 - 121-15 is provided with 4 AND gate groups 126a - 126d as shown in Figure 60 . A coefficient corresponding to the above described 126-dot pattern is applied to AND gate group 126a. A coefficient corresponding to a pattern obtained by inverting this pattern up to down is applied to AND gate group 126b. A coefficient corresponding to a pattern obtained by inverting this pattern right to left is applied to AND gate group 126c. A coefficient corresponding to a pattern obtained by inverting this pattern up to down and right to left is applied to AND gate group 126d. Like in the hidden layer shown in Figure 59 , the coefficients are applied to each of the AND gate groups 126a-1 - 126d-126 in 1 bit. AND gates can be omitted here including their connection lines for inputted data whose coefficient is 0. For example, as in the third embodiment shown in Figure 59 , the addition of a constant term in expression (1) can be omitted in the fourth embodiment shown in Figure 60 . This can be realized by absorbing the value of the constant value by modifying the threshold of a step function when it is used in a scaling operation by the ROM 130. Figure 61 shows dot patterns processed by each of AND gate groups 126a - 126d and their correction results (teaching patterns) by referring to the patterns shown in Figure 58 . As indicated in Figure 61 , the correction result for each pattern is similar to the others, thereby requiring the standardization of circuits. That is, in Figure 60 , the circuits after the adder 127 can be used in a time divisional manner. Four patterns shown in Figure 61 are the same in dot size after correction and differ in shift direction only. Therefore, they can be easily referred to when processed separately. That is, in the subdot pattern for the central dot in a window in Figure 61 , the size of a dot is not changed, but its position is shifted only. Figure 62 shows an enlarged view of the subdot pattern shown at the lower left corner in Figure 61 . The enlarged views for the other 3 patterns can be obtained only by inverting it respectively. In Figure 62 , the subdot pattern corresponding to the inputted data for the central picture element in a window indicates all black for 8 subdots each being shifted to right by 3/8 dot. In Figure 61 , two subdot patterns are indicated because actual printing position for one dot covers 2-dot areas due to the shift to right or left. In Figure 60 , first, a selector 136 applies only an output from AND gate group 126a to an adder 127. The sum is stored in a shift register 137 after scaled by a via register 129, and a ROM or a comparator 130 using a step function. The scaling results for the 4 patterns can be stored in the shift register 137 by selectively outputting the outputs from AND gate groups 126a - 126d after the operation performed by the selector 136. Thus, in the embodiment shown in Figure 60 , since 4-bit outputs can be obtained through each of 15 neurons 121-1 - 121-15 in the hidden layer, a total of 60 bits are applied from units 121-1 - 121-15 in the hidden layer of the neural network to its output layer (not shown in Figure 60 ). In this embodiment, the configuration of and after the output layer is the same as that of the second embodiment shown in Figure 53 . Figure 63 shows the configuration of and after the output layer of the fifth embodiment of the image forming apparatus according to the second principle of the present invention. It is different from other embodiments in that it has an output layer in which the number of neurons, that is, 6 neurons 141a - 141f, is smaller than that of subdot divisions while, in the other embodiments, the number of neurons in the output layer is equal to that of subdot divisions (8) forming one dot of an inputted dot image. In this embodiment, neurons 141a - 141f are used for learning, and a table 143 is referred to through the output from the output layer to obtain a subdot pattern shown in Figure 7. Since much learning time is required for generating a subdot pattern directly by the neural network, this embodiment uses an output from the neural network as a kind of code associated with a correction operation, resulting in the same output as that of the first principle. That is, when the number of neurons in the output layers is 6 as shown in Figure 63 , 2 neurons out of 6 represent the positions of dots, and the remaining 4 neurons represent the dot size. The combination of the output from these 6 neurons refers to the table 143 so that 8 subdot signals can be generated and outputted. The detailed configuration of each of neurons 141a - 141f in the output layer can be the same as that of the neurons in the output layer shown in Figure 53 if the configuration of the input and intermediate layers are those shown in Figure 53 , 59 , or 60 . The table 143 stores the correspondence data between the outputs and the corresponding subdot patterns shown in Figure 7 and the patterns. Therefore, the print head controller generates a pulse signal which indicates "ON" for the value of "1" in 8 subdots in the time width forming a picture element. A static latent image can be formed on a photoconductive drum. Figure 64 shows the configuration of the neuro output processor in the sixth embodiment of the image forming apparatus according to the second principle of the present invention. It is different from the embodiment shown in Figure 63 in that a 14-bit correction signal is generated by applying an output from 6 neurons in the output layer to a conversion table 145. That is, a conversion result can be effective covering 2 dot areas in inputted dot image data when a conversion is performed from 1 dot to a plurality of subdots for a pattern other than some teaching patterns shown in Figures 48 - 51 . In the embodiment shown in Figure 48 , each pattern is learned separately. However, there can be only one teaching pattern if the neural network shown in Figure 64 outputs a code associated with a correcting operation. That is, patterns must be made for the number of necessary pattern forms such that the number of bits covering the adjacent dot areas is added to the right and left of the bit configuration. In this embodiment, a conversion table 145 is configured such that the number of subdots covering its right and left subdots is 3, thereby generating a 14-bit pattern. An output of the table 145 is sequentially applied to registers 148 - 150. Since the scanning direction in a segmented window is the same as that of a laser light of an electronic photograph printer, that is, an output unit, a content of a register 150 indicates the subdot information of the preceding, that is, the left, picture element assuming that the content of the register 149 indicate data of the central picture element. Thus, the content in register 148 indicates the subdot information of the following, that is the right, picture element. Accordingly, the subdot information covering the preceding and the right picture elements and the subdot information covering the following and the left picture elements are ANDed by OR circuits 151a - 151f as the subdot information at a predetermined position. Figure 66 shows this as a descriptive pattern. Figure 65 shows how the inputted dots "black, white, black" in this order are shifted. The leftmost black dot is shifted to right by 3/8 dot, and the rightmost black dot is shifted to left by 3/8 dot. Figure 65 shows how the subdot pattern for the originally white dot in the center is outputted to a print head controller. The output pattern to be outputted to the print head controller is indicated, in the center at the bottom in Figure 65 , as a portion segmented by a dashed line. The register 150 shown in Figure 64 outputs 3 rightmost subdot patterns in the subdot patterns at the top (all black) in Figure 65 ; the register 149 outputs the central 8 subdot patterns in the second row (all white); the register 148 outputs 3 leftmost subdot patterns in the third row (all black). The logical sum of these data is obtained by OR gates 151a - 151f, and the result is outputted to a print head controller. In the above described example, 1 dot is divided into 8 subdots. However, the dot can be divided into a different number of subdots. Additionally, it can be divided in the vertical scanning direction as well as the horizontal scanning direction. Figure 66 shows the embodiment of the image quality correcting circuit in a printer shown in Figure 37 according to the second principle of the present invention. The configuration of this circuit is similar to that shown in Figure 38 except that 7x9 dot data are inputted to the neuro 84 and that the subdot pattern data outputted from the RAM 85 are converted in serial/parallel by a shift register 160 and transmitted as an exposure pulse correction signal to the printing mechanism as is. Figure 66 shows two oscillators 161 and 162 for generating a clock signal. Figures 67 and 68 are timing charts for explaining the operation of the image quality correcting circuit. When an optical sensor provided at the end of the laser light scanning area inputs a beam detection signal (BD) for indicating the detection of a laser light, the counters 88 and 89 shown in Figure 66 are reset and data are applied according to the video data clock (VDCLK=CK1) from the controller 60 shown in Figure 37 to the RAM 82 through the latch 81. The write of data to the RAM 82 from the latch 81 is controlled according to an address ADR1 from the counter 88, an output enable signal OE1, and a write enable signal WE1. The read of data from the RAM 82 to the latch 81 is controlled according to an output enable signal OE2 and a video data clock CK1 while data are not being written to the RAM 82 (while a write enable signal WE1 is OFF). When 1-line data at addresses 0 - N are inputted, the write of data is disabled to prevent the write of invalid out-of-area data from being written until the next BD signal is inputted. If a 8x11-inch printing form is fed in the longer side direction with the resolution of 300 dots/inch, N=2560 approximately. Data are outputted from the RAM 82 according to an address ADR2 outputted from the counter 89. The outputted data are applied to shift registers 83a - 83g in synchronous with clock CK2. The data inputted to shift registers 83a - 83g are converted in serial/parallel, and the 63-bit data are simultaneously applied to the neural network 84 in synchronous with input strove signal ST1. In the neural network 84, an arithmetic operation is performed in synchronous with clock CK3 using the circuit configuration of the input layer 110 shown in Figure 59 , the hidden layer 121 shown in Figure 60 , the output layer 141 shown in Figure 63 , and the neuro output unit shown in Figure 64 . After a process is completed by the neural network 84, an 8-bit image correction signal (comprising correction subdots 0 - 7) outputted from the circuit shown in Figure 64 is outputted in synchronous with output strove signal ST2. This image correction signal is stored in the RAM 85 according to address ADR2 from the counter 89 and write enable signal WE2. The data stored in the RAM 85 are sequentially read starting from address 0 according to address ADR1 outputted from the counter 88. The data read from the RAM 85 are loaded to a shift register 160 according to load signal LD1 to the shift register 160. The loaded data are outputted sequentially, starting from subdot 0, from the shift register 160 to the optical unit 76 in synchronous with clock CK4. Thus, the optical unit 76 applies to a laser diode a drive pulse signal having the pulse width according to a pattern comprising 8 sequentially inputted subdots. The present invention can be used in an ink jet printer and a thermal transfer printer as well as an electrophotographic printer such as laser printers, etc. Furthermore, it can be used in a display unit, not limited to a printer. When it is used in a display unit, the present invention can be applicable by applying print data to a video D/A converter, not to a print head.

Claims: An image forming apparatus comprising : an input means for receiving an image comprising a plurality of input dots, each dot having a corresponding dot position in a window of predetermined shape, said window having a centre dot; and a jagged edge reducing means (10) for reducing jagged edges in the image data and for receiving said image data and its window, wherein said jagged edge reducing means generates subdivided dots of each input dot subject to jagged edge reduction in response to said image data input in said window and thereby outputs a subdot exposure pattern exposure data comprised of subdivided dots having selected size values and positions for said window as correction data for replacement of the input dot subject to jagged edge reduction; characterized in that said jagged edge reducing means comprises a neural network (10) having a first plurality of neurons (units) for outputting size conversion data of said subdivided dots and a second plurality of neurons for outputting position conversion data of said subdivided dots, said size and position data of said subdivided dots being output separately from respective neurons. An image forming apparatus according to claim 1, wherein said neural network of said jagged edge reducing means (10) is composed of plural connected neurons, wherein a coefficient of the input connection to each neuron in the hidden layer of said neural network is +n, indicating n a constant, -n, or 0. An image forming apparatus according to claim 1 or 2, further comprising : exposure pattern data outputting means for obtaining a logical sum using an output from said jagged edge reducing means subdot information about left to right dots and right to left dots containing said central dot and subdot information about said central dot, and outputting said logical sum as exposure pattern data for said central dot in said window. The image forming apparatus according to claim 1, 2, or 3, wherein said input means further comprises : a data segmenter means (20) having a plurality of line buffer means (21), provided at the stage preceding to an input layer of said neural network, for storing one [1] line of image data among a plurality of horizontal lines in said window, and a plurality of shift register means (22) being connected for receiving respective contents stored in said plurality of line buffer means (21), and for serially outputting via an input layer to all neurons in hidden layers in bit units said image data in said window; and said neuron network comprises: a plurality of hidden layer neuron means (24) for forming said hidden layers of said neural network each comprising; a coefficient buffer means (25) for storing the coefficient corresponding to the number of image data within said window, an AND gate means (26) for receiving an output from said coefficient buffer means (25) and an output from said data segmenter means (20), a first adder means (27) receiving at one of its input terminals an output from said AND gate means (26) for performing a sum-of-product operations as one of a plurality of hidden layer neuron (24), a first register means (28) for storing an output from said first adder means (27) and for outputting a stored content to said first adder means (27) at the other one of its input terminals, a second register means (29) for storing an output from said first register means (28) when said first register means (28) stores the sum obtained by said first adder means (27) from coefficients and image data in all windows inputted to said AND gate means (26), a read only memory (ROM) means (30) for outputting as a scaling result a conversion function value of a neuron for an output from said second register means (29), and a three-state register means (31) for holding an output from said ROM means (30); and a plurality of output layer neuron means (32) forming an output layer of said neural network comprising; a coefficient buffer means (33) for storing a coefficient in correspondence with the number of said plurality of hidden layer neuron means (24), a multiplier means (34) for receiving an output from said coefficient buffer means (33) and an output from said plurality of hidden layer neurons (24), a second adder means (35) for receiving an output from said multiplier means (34) at one of its input terminals and for performing a sum-of-product operation as an output layer neuron, a third register means (36) for storing an output from said second adder means (35), and for outputting the stored content to said second adder means (35) at its other one of input terminals, a fourth register means (37) for storing an output from said third register means (36) when said third register means (36) stores the sum obtained by said second adder means (35) from inputted coefficients and outputs from all of said plurality of hidden layer neuron means (24) to said multiplier means (34). The image forming apparatus according to claim 4 , wherein: said neural network receives said window image data from said line buffer means (21) in said data segmenter means (20) in the stage preceding to said input layer, said line buffer means (21) loads said window image data on to said shift register means (22), said window image data shifted in said shift register means (22) causes said window image data to be outputted serially in bit units to said AND gate means (26) in all of said plurality of hidden layer neuron means (24), said three-state register means (31) in the corresponding one among said plurality of hidden layer neuron means (24) holds the result of scaling the sum total of the products between all of said window image data and said coefficient in said plurality of hidden layer neuron means (24), output-enables for said three-state register means (31) in the corresponding one among said plurality of hidden layer neuron means (24) are sequentially established for said plurality of hidden layer neuron means (24), said three-state register means (31) in the corresponding one of said plurality of hidden layer neuron means (24) sequentially outputs its stored contents to said multiplier means (34) in said plurality of output layer neuron means (32), and said plurality of output layer neuron means (32) output the most significant bit of the sum total of the products between said coefficient and all outputs from said plurality of intermediated layer neuron means (24) is said plurality of output layer neuron means (32), thereby ending the process. The image forming apparatus according to claim 5 , wherein: more than one [1] among said plurality of output layer neuron means (32) output correction data for the size of said center dot in said window: and more than one [1], being different, among said plurality of output layer neuron means (32) output correction data for the position of said center dot in said window. The image forming apparatus according to any preceding claim, for use in a printer wherein: said input means comprises a first latch circuit means (81) for receiving image data from a controller means (60) for said printer; a first two-port random access memory (2P RAM) means (82) for storing an output from said first latch circuit means (81); and a plurality of shift register means (83) for converting a serial output from said first 2P RAM means (82) to a parallel output; said neural network comprises a neural network means (84) for receiving an output from said plurality of shift register means (83) and for outputting correction data for the size and position of the center dot in said window; and further comprising a second 2P RAM means (85) for storing an output from said neural network means (84); a second latch circuit means (86) for storing an output from said second 2P RAM means (85); a pulse width correcting circuit means (87) for outputting an exposure pulse correction signal to a printing mechanism means (62) of said printer in accordance with an output from said second 2P RAM means (85) and said second latch circuit means (86); a first counter means (88) for controlling read/write addresses on the side of said first latch circuit means (81) of said first 2P RAM means (82) and on the side of said second latch circuit means (86) for said second 2P RAM means (85); and a second counter means (89) for controlling read/write addresses on the side of shift register means (83) of said first 2P RAM means (82) on the side of said neural network means (84) for said 2P RAM means (85). The image forming apparatus according to claim 7 , wherein: said first latch circuit means (81) comprises: n input terminals, including one [1] for receiving said image data; and n output terminals provided in a one-to-one correspondence with said n input terminals and connected to respective terminals of one port side of said first 2P RAM means (82): and n-1, including one [1] corresponding to said one [1] (of input terminals) receiving terminal for receiving said image data, of said n output terminals are connected to n-1 of said n input terminals, excluding one [1] for receiving said image data, in a form shifted by one from said one-to-one correspondence. The image forming apparatus according to claim 7 , wherein: respective terminals on the side of said shift register means (83) of said first two-port RAM means (82) are connected to respective input terminals of said shift register means (83); and said shift register means (83) store, by shifting one [1] bit, said window image data of respective horizontal lines stored in said first 2P RAM means (82). The image forming apparatus according to any one of claims 7 to 9, wherein said pulse width correcting circuit means (87) comprises : a read only memory (ROM) means (87a) for outputting actual graphic data for the center dot in a current window, according to the address specified by correction data for the position and dot size for said center dot in said current window inputted from said second 2P RAM means (85) and by correction data left behind by a shift in dot positions of the correction data for the position and dot size for the preceding graphic dots inputted from said second latch circuit means (86); and a shift register means (87b) for outputting to said printing mechanism means (62), as said exposure pulse correction signal, serial data converted from parallel data supplied from said ROM means (87a). The image forming apparatus according to claim 10 , wherein: said read only memory (ROM) means (87a) output, in accordance with said specified address, a logical sum between said correction data for said center dot in said window and said correction data left behind by said shift in dot positions. The image forming apparatus according to claim 7, further comprising an : image quality correcting circuit means (61) operative to reset said first counter means (88) and said second counter means (89) by a beam detect signal inputted from said printing mechanism means (62) from said printer; sequentially store in said first 2P RAM means (82) image data from said controller means (60) of said printer according to the value counted by said first counter means (88); wherein : said first 2P RAM means (82) sequentially outputs data to said neural network means (84) according to the value counted by said second counter means (89) at the same time; said neural network means (84) sequentially outputs data delayed by the operating cycle of said neural network means (84) to said second 2P RAM means (85) according to the value counted by said second counter means (89); and said second 2P RAM means (85) starts outputting data to said pulse width correcting circuit means (87) and processing image data for the next line according to the next beam direct signal from said printing mechanism means (62) . The image forming apparatus according to any preceding claim, wherein : said neural network has any of three [3] values comprised of +n, -n, where n is a constant, and zero [0] as a coefficient for input combination to the corresponding one of a plurality of hidden layer neuron means (24). The image forming apparatus according to claim 13, wherein the value of said n is one [1]. The image forming apparatus according to claim 4, wherein said AND gate means comprises : two [2] AND gates (26a and 26b) for receiving said output from said coefficient buffer means (25) and an output from said data segmenter means (20), said first adder means (27) receiving at one of its input terminals an output from said two [2] AND gates (26a and 26b) for performing the sum-of-product operations as one of a plurality of hidden layer neuron means (24). The image forming apparatus according to claim 4 , wherein: said plurality of hidden layer neuron means (24) further comprise, in lieu of said first adder means (27) and said first register means (28); a decoder means (42) for instructing an "up", "down" and "hold", respectively when outputs from said two [2] AND gate means (26a and 26b) are a combination of zero [0] and one [1], a combination of one [1] and one [1], and a combination of zero [0] and zero [0]; and an up/down counter means (43) counting up or down as instructed by said decoder means (43). The image forming apparatus according to any one of claims 2 to 16, wherein : said neural network has any of two [2] values comprised of plus one [+1] and zero [0] as a coefficient for the corresponding one of said input combination to hidden layer neuron means (24); and said plurality of hidden layer neuron means (24) receive a normal signal and an inverted signal of said dot image data. The image forming apparatus according to claim 17 , wherein said hidden layer neuron means comprises: an inverter means (49) for inverting data inputted from a data segmenter means (20); a selector means (50) for receiving as a normal input an output from said data segmenter means (20) and as an inverted input an output from said inverter means (49); a selector controller means (51) for controlling a selection between said normal input and said inverted input by said selector means (50); a coefficient buffer means (52) for storing a coefficient for said dot image data inputted from said data segmenter means (20); an AND gate means (53) for receiving an output from said coefficient buffer means (52) and an output from said selector means (50); an adder means (54) for receiving an output from said AND gate means (53) at one of its input terminals and for performing a sum-of-product operations as one of said plurality of hidden layer neuron means (24); a first register means (55) for storing the sum obtained by said adder means (54) and for outputting the stored sum to the other of said input terminals of said adder means (54); a second register means (56) for storing an output from said first register means (55) when said first register means (55) stores the sum of inputs to said AND gate means (53) of all image data in said window and said coefficient in said coefficient buffer means (52); a read only memory (ROM) means (57) for outputting as a scaling result a neuron's conversion function value for an output from said second register means (56); and a three-state register means (58) for holding an output from said ROM means (57). The image forming apparatus according to claim 18 , wherein: said selection controller means (51) outputs a selection control signal for instructing a selection of a normal input when a dot corresponding to a datum inputted from said data segmenter means (20) must be black and for instructing a selection of an inverted input when a dot corresponding to a datum inputted from said data segmenter means (20) must be white; said coefficient buffer means (52) stores one [1] as a coefficient to be multiplied to dot input data expressing black or white and zero [0] as a coefficient to be multiplied to dot input data that do not matter. The image forming apparatus according to claim 19, wherein said selector controller means (51) comprises : a counter means being reset immediately before a data input from said data segmenter means (20) and being incremented every one bit of said data input; and a read only memory (ROM) (59b) means for outputting to said selector means (50) a selection control signal stored at an address specified by an output from said counter (59a). The image forming apparatus according to any preceding claim, wherein said input means comprises : a plurality of shift register means (91), provided at the stage preceding to an input layer of said neural network, and being connected for serially outputting via an input layer to all neurons in hidden layers in bit units said image data in said window, said plurality of shift register means (91) respectively for receiving one [1] line of image data among a plurality of horizontal lines in said window. The image forming apparatus according to claim 21, wherein said neural network comprises : a hidden layer of said neural network comprises a plurality of hidden layer neuron means (95) each having pairs of first and second AND gate means (96a and 96b), provided in the number of image data in said window, for receiving at one of their input terminals one [1] bit each of dot image data in said window inputted simultaneously from said input layer of said neural network and for receiving at the other of their input terminals a combination of coefficients zero [0] and one [1] when said one [1] bit of image data is black, a combination of coefficients one [1] and one [1] when said one [1] bit of image data is white, a combination of coefficients zero [0] and zero [0] when said one [1] bit of image data does not matter, a first adder means (97) for receiving all outputs from said first and second AND gate means (96a and 96b), a first register means (99) for storing an output from said first adder means (97), a read only memory (ROM) means (100) for outputting a neuron's conversion function value for an output from said first register means (99) as a scaling result, and a second register means (101) for storing an output from said ROM means (100); and an output layer of said neural network comprises output layer neuron means (102), provided in the number of subdots in said subdot pattern, said output layer neuron means (102) each having third AND gate means (103), provided in the number of said plurality of hidden layer neuron means (95), for receiving at one of their input terminals one [1] bit each of plural bits simultaneously outputted from said plurality of hidden layer neuron means (95) and receiving at the other of their input terminal a coefficient being either zero [0] or one [1], a second adder means (104) for receiving all outputs from said third AND gate means (103), a third register means (105) for storing a sum outputted from said second adder means (104), and a fourth register means (106) for outputting the most significant bit in response to an input of a content stored in said third register means (105). The image forming apparatus according to claim 21 , wherein: said first adder means (97) in said hidden layer neuron means (95) and said second adder means (104) in said output layer neuron means (102) comprise a plurality of adders in a pyramid structure formed by an adder for adding a constant term used for an intraneuron operation to all outputs from said first, second and third AND gate means (96a, 96b and 103) thereby adding outputs from neighboring AND gate means and by an adder for adding outputs from neighboring adders. The image forming apparatus according to claim 21, wherein: an input layer of said neural network comprises a fifth register means (111) for storing all dot image data in said window and an inverter means (112) for inverting all dot image data in said window stored in said fifth register means (111), outputs all dot image data in said window as a content stored in said fifth register means (111) and inversions of all dot image data in said window as an output from said inverter means (112) to all of said plurality of hidden layer neuron means (95); and AND gate means (116), provided in the number double the number of dot image data in said window in lieu of said pairs of AND gate means (96a and 96b) in said plurality of hidden layer neuron means (95), for receiving at one of their input terminals one [1] bit of parallel data outputted from said input layer, and for receiving at the other of their input terminals one [1] if said one [1] dot must be black, and zero [0] otherwise, when said one [1] bit is a normal input outputted from said fifth register means (111), as well as one [1] if said one [1] dot must be white, and zero [0] otherwise, when said one [1] bit is an inverted input outputted from said inverter means (112). The image forming apparatus according to claim 21, wherein said hidden layers of said neural network comprises a plurality of neuron means (121) each having: a first class of AND gate means (126a), provided in the number double the number of dot image data in said window, for receiving at one of their input terminals one [1] bit of all dot image data in said window and the inversions of all dot image data in said window and for receiving at the other of their input terminals a coefficient in accordance with said normal input or said inverted input; a second class of AND gate means (126b), provided in the number double the number of dot image data in said window, for receiving at one of their input terminals one [1] bit of all dot image data in said window and the upside-down inversions of all dot image data in said window and for receiving at the other of their input terminals a coefficient of corresponding to a pattern obtained by inverting dot patters to be detected in said window basing said coefficient for said first class of AND gate means (126a); a third class of AND gate means (126c), provided in the number double the number of dot image data in said window, for receiving at one of their input terminals one [1] bit of input data from said input layer and at the other of their input terminals the mirror images of dot pattern corresponding to said first class of AND gate means (126a); a fourth class of AND gate means (126d), provided in the number double the number of dot image data in said window, for receiving at one of their input terminals one [1] bit of input data from said input layer and at the other of their input terminals the upside-down inversions of the mirror images of dot pattern corresponding to said first class of AND gate means (126a); a selector means (136) for selecting an output from any of said first through fourth classes of AND gate means (126a through 126d); an adder means (127) for adding an output from said selector means (136); a register means (129) for storing an output from said adder means (127); a read only memory (ROM) means (130) for outputting as a scaling result a neuron's conversion function value for an output from said register means (129); a shift register means (137) for shifting the scaling result obtained by said ROM means (130) corresponding to outputs from said first through fourth AND gate means (126a through 126d) according to the sequence of selection by said selector means (136) and for storing the shifted scaling result. The image forming apparatus according to claim 21, wherein: said output layer comprises said output layer neurons provided in a number less than the number of subdots forming said subdot pattern; and a conversion table means (143), provided in the succeeding stage of said output layer, for converting an output from said output layer neuron means (102) to said subdot pattern. The image forming apparatus according to claim 21, wherein: said output layer has said output layer neuron means (102) in a number less than the number of subdots forming said subdot patterns; and the succeeding stage of said output layer comprises a table means (145) for outputting a bit pattern including all of subdot patterns for the center dot of said window and a part each of the left side and the right side of said center dot, a first register means (149) for storing subdot data for the center dot in said window, a second register means (150) for storing subdot data for the dots on the left side of said center dot, a third register means (148) for storing subdot data for the dots on the right side of said center dot, and a plurality of OR circuit means (151) for producing a logical sum among subdot data across said center dot from a left side dot to a right side dot, subdot data across said center dot from a right side dot to a left side dot and subdot data for said center dot. The image forming apparatus according to any preceding claim, wherein said input means comprises: a first latch circuit means (81) for receiving image data from a controller means (60) for said printer; a first two-port random access memory (2P RAM) means (82) for storing an output from said first latch circuit means (81); a plurality of shift register means (83) for converting a serial output from said first 2P RAM means (82) to a parallel output; a neural network means (84) for receiving an output from said plurality of shift register means (83) and for outputting correction data for the size and position of the center dot in said window; a second 2P RAM means (85) for storing an output from said neural network means (84); a shift register means (160) for outputting an exposure pulse correction signal to said printing mechanism means (62) of said printer by serializing a parallel output from said second 2P RAM means (85); a first counter means (88) for controlling read/write addresses on the side of said first latch circuit means (81) of said first 2P RAM means (82) and on the side of said second latch circuit means (86) for said second 2P RAM means (85); and a second counter means (89) for controlling read/write addresses on the side of shift register means (83) of said first 2P RAM means (82) on the side of said neural network means (84) for said 2P RAM means (85).

Inventors: CHIBA HIROTAKA, KONAKA TOSHIO, MIKAMI TOMOHISA, MORI MASAHIRO, MOROO JUN, NAGATA SHIGEMI, NAKAMURA SHIGEYOSHI, SATO KAZUHIKO, CHIBA, HIROTAKA, KONAKA, TOSHIO, MIKAMI, TOMOHISA, MORI, MASAHIRO, MOROO, JUN, NAGATA, SHIGEMI, NAKAMURA, SHIGEYOSHI, SATO, KAZUHIKO, Chiba, Hirotaka, c/o Fujitsu Limited, Konaka, Toshio, c/o Fujitsu Limited, Mikami, Tomohisa, c/o Fujitsu Limited, Mori, Masahiro, c/o Fujitsu Limited, Moroo, Jun, c/o Fujitsu Limited, NAGATA, SHIGEMI, C/O FUJITSU LIMITED, Nakamura, Shigeyoshi, c/o Fujitsu Limited, Sato, Kazuhiko, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G06T5
IPC codes: G06K9, G06T1, G06N3, G06T5