SOI CMOS DEVICE HAVING BODY EXTENSION FOR PROVIDING SIDEWALL CHANNEL STOP AND BODY TIE

Abstract: An SOI/SOS thin film MOS mesa architecture has its body/channel region (14) extended beyond the source and drain regions (16, 18) and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region (31, 32), so as to provide both a body tie access location which enables the body/channel region (14) to be terminated to a prescribed bias voltage (e.g. Vss), and a channel stop region (41, 42) that is effective to functionally interrupt a current leakage path or 'parasitic' N-channel that may be induced along sidewall surface of the P-type material of the body/channel region (14). In another embodiment, ionizing radiation-induced inversion of the sidewalls (83, 84) of the P-type body/channel region (14) is prevented by an asymmetric sidewall channel stop structure (71, 72) formed in opposite end portions of the source region (16).

Description: SOI CMOS DEVICE HAVING BODY EXTENSION FOR PROVIDING SIDEWALL CHANNEL STOP AND BODYTIE FIELD OF THE INVENTION The present invention relates in general to semiconductor devices and is particularly directed to an SOS/SOI architecture, the 'Λ channel/body portion of which is extended beyond the source and drain 5 regions so as to provide a body tie access location and, being more heavily doped than the body/channel portion, serves as a channel stop against 'sidewall 7 parasitic transistor action between the source and drain regions. The present invention further provides an asymmetric sidewall channel stop structure in opposite end portions of the 10 source region, thereby preventing ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region. BACKGROUND OF THE INVENTION Thin film, co-planar integrated circuits employing silicon-on- insulator (SOI) or silicon-on-sapphire (SOS) CMOS architectures are 15 typically characterized by the use of either air or (oxide) dielectric to provide lateral isolation between adjacent 'mesa' transistors which are formed atop an insulating dielectric (e.g. silicon oxide or sapphire) . More particularly, as diagrammatically illustrated in the top view of Figure 1 and the side view of Figure 20 2, a conventional N-channel SOI/SOS thin film MOS transistor structure is typically comprised of a semiconductor (silicon) mesa layer 11, which is disposed atop a substrate-supported dielectric (silicon dioxide) layer 12 and the sidewall perimeter of which is bounded by air or an oxide dielectric layer, shown at 13. This 25 semiconductor mesa structure contains a P-type body/channel region 14 disposed between and immediately contiguous with respective N+ source and drain regions 16 and 18. Overlying the (P-type) channel/body region 14 and extending onto the surrounding support substrate, either co-planar with the top of the mesa as shown in Figure 2 in the ^30 case where the mesa is bounded by an oxide dielectric layer 13, or stepped down to the surface of dielectric layer 12 in the case where the mesa is bounded by air isolation, is a doped polysilicon gate layer 21, insulated from the semiconductor material of the mesa by thin dielectric layer (e.g. oxide) 22. Because the surface of P-doped material (here the P-typ channel/body region 14) is susceptible to inversion in the presenc of ionizing radiation, there is the danger of a leakage path o 'parasitic' channel being induced along the body/channel sidewall 23, 24 between the source and drain regions 16, 18. Moreover, regardless of the potential for exposure to ionizing radiation, th inability of some manufacturing processes to accurately control th channel doping along the edges of the device (beneath the polysilico gate overlay 21) , and the lack of control of electrostatic charg build-up along surface portions 25, 27 of dielectric layer 13 that is immediately adjacent to P-type silicon body 14, may cause the device to suffer extraordinary current leakage in its OFF state. Another problem associated with this type of architecture is the fact that the body/channel region 14 of the transistor, being situated atop a dielectric layer, is not readily accessible to be terminated to either a Vdd node or, in the case of an N-channel device, a Vss node, so that the potential of the body/channel region effectively r floats', which can severely degrade the performance of the transistor (e.g. subject the saturation region of the device to the 'kink' effect and additionally by permitting parasitic NPN devices to be turned on) . SUMMARY OF THE INVENTION In accordance with the present invention the above drawbacks of conventional SOI/SOS thin film MOS mesa architectures are effectively obviated by extending the body/channel region beyond the source and drain regions and also increasing the impurity concentration at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the body/channel region to be terminated to a prescribed bias voltage (e.g. Vss) , and a channel stop region that is effective to functionally interrupt a current leakage path or 'parasitic 7 N- channel that may be induced along sidewall surface of the P-type material of the body/channel region. Pursuant to a first embodiment of the present invention, the problem of the inducement of a parasitic sidewall channel within an SOI/SOS field effect transistor architecture is successfully addressed by extending the body/channel region beyond endwall 5 terminations of source and drain regions that are contiguous with the body/channel region, so as to form a pair of body/channel extension regions at opposite ends of the device. The thin film, field effect transistor, being an SOI/SOS mesa structure, includes a semiconductor mesa having a body/channel region of a first conductivity type (e.g. 10 P-type for an N-channel device) formed on a first surface portion of an underlying dielectric layer (e.g. silicon dioxide, sapphire), with its source region of a second conductivity type (e.g. N-type for an N-channel device) , formed in the mesa on a second surface portion of the substrate immediately contiguous with the first surface portion 15 and forming a source/body junction with (P-type) body/channel region. A drain region of the second conductivity type (N-type) is formed in the mesa on a third surface portion of the substrate, spaced apart from the second surface portion by the first surface portion therebetween, and being immediately contiguous with the first surface 20 portion and forming a drain/body junction with the body/channel region. A dielectrically insulated (polysilicon) gate layer overlies the body/channel region of the mesa. Extending the opposite end portions of the P-type mesa body/channel region extend beyond the terminations of the source and 25 drain regions, serves to increase the effective channel length to a value greater than the case where the (P-type) body/channel region terminates 'flush' with the (N+) source and drain regions. Thus, respective body extensions at both ends of the body/channel region beneath the polysilicon gate, by increasing the 'net edge length 7 , 30 will result in a significantly reduced OFF state leakage due to the attenuation of parasitic transistor short channel effects. In accordance with a second embodiment of the invention, the * impurity concentration of end portions of the (P-type) extension regions is increased relative to the impurity concentration of that "35 portion of the body/channel region disposed between the source and drain regions, thereby forming a pair of P+ channel stops. This relatively high impurity concentration of the end portions of th extension regions insures that the parasitic sidewall threshold i higher than any possible negative threshold shift which might b induced by ionizing radiation. These more heavily doped (P+) en portions of the extension regions are spaced apart from th intermediate portion of the (P-type) body/channel region b respective portions of the extension region of the same dopin concentration as the body/channel region itself, so that the mor heavily doped (P+) channel stop regions do not form (very lo breakdown voltage) P+/N+ junctions with the source and drain regions Pursuant to a third embodiment of the invention, the channe stops of the extension regions are configured to provide additiona functionality, specifically to provide body tie contact regions, s that the body/channel region may be terminated at a prescribed bia voltage (e.g. Vss, which will substantially reduce parasitic curren leakage during the transistor 7 s OFF state). For this purpose, th heavily doped portions of the extension regions protrude to the sid of or transverse to the lengthwise direction of the body/channel region and its polysilicon gate overlay, so that a pair of heavil doped (P+) bodytabs project outwardly from beneath and to the side of the gate layer, thereby forming a symmetrical, bidirectional transistor geometry and facilitating the electrical connection of a bias rail to the body/channel region through one or both ends of the device. In accordance with a fourth embodiment of the invention, the problem of ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is addressed by means of an asymmetric sidewall channel stop structure formed in opposite end portions of one of the source and drain regions. Specifically, first and second end portions of one (e.g. the N+ source region) of (N+) source and drain mesa regions, which are contiguous with the (P) body/channel mesa region and extend to sidewall edges of the selected one of the source and drain mesa regions, are heavily overdoped with impurities (e.g. P+) of the same conductivity type as the body/channel region, thereby forming a demiurgic channel stop structure having first and second mesa sidewall channel stops immediately adjacent to the ends of the (P) body/channel region and which extend throughout the thickness of the selected source or drain region. The heavy (P+) overdoping ensures that the parasitic sidewall threshold is higher than any possible negative threshold shift that might occur as a result of the incidence of ionizing radiation. Even in the case of a very thick dielectrically filled trench isolation structure where the potential charge generation volume is relatively large, the sidewall remains adequately enhancement mode. Since the P+ channel stops are disposed in the same N+ region, they are physically and electronically separated from the N+ drain/source region on the opposite side of the body/channel region over which the polysilicon gate is formed. Thus, both P+/N+ junctions formed between the high impurity concentration (P+) channel stops and the (N+) material in which they are introduced are into the source region and are always at the same potential, so that the value of reverse bias breakdown voltage is not of concern. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 and 2 are respective diagrammatic top and side views of a conventional N-channel SOI/SOS thin film MOS transistor structure; Figures 3 and 4 are respective diagrammatic top and side views of an MOS transistor structure having body/channel extension regions in accordance with a first embodiment of the present invention; Figures 5 and 6 are respective diagrammatic top and side views of an MOS transistor structure having body/channel extension regions in accordance with a second embodiment of the present invention; Figures 7 and 8 are respective diagrammatic top and side views of an MOS transistor structure having body/channel extension regions in accordance with a third embodiment of the present invention; Figures 9 and 10 are respective diagrammatic isometric and side views of an asymmetric sidewall channel stop structure in accordance with a fourth embodiment of the present invention; and Figures 11 - 16 show conventional MOS channel stop architectures. DETAILED DESCRIPTION Referring now to Figures 3 and 4, respective top and side view of a first embodiment of the present invention show how th conventional thin mesa transistor structure of Figures 1 and 2 i modified such that the body/channel region 14 extends beyond it interfaces with each of the source and drain regions, as shown b body/channel extension regions or segments 31, 32. Regions 31, 3 have a prescribed length x and a width y within the dimensions of th gate layer 21 and serve to increase the effective channel length o body/channel region 14 to a value greater than the case where th body/channel region terminates 'flush 7 with source and drain region 16, 18 (as shown in Figure 1) . The respective channel/body extension 31, 32 at both ends of the body/channel region beneath th polysilicon gate, by increasing the net edge length 7 (2x + y) , wil result in a significantly reduced OFF state leakage due to th attenuation of parasitic transistor short channel effects. Figures 5 and 6 diagra matically show respective top and sid view of a second embodiment of the invention, in which respective high impurity concentration 'tab 7 regions 41, 42 are introduced to overlap end portions 43, 44 of (P-type) body/channel extension regions 31, 32 so that the impurity concentration of these end portions of the extension regions is increased relative to the impurity concentration of that portion 17 of the body/channel region 14 disposed between the source and drain regions, thereby forming a pair of P+- channel stops. This relatively high impurity concentration of the channel stop tab regions 41, 42 insures that the parasitic sidewall threshold is higher than any possible negative threshold shift which might be induced by ionizing radiation. These more heavily doped (P+) tab regions 41, 42 of the extension regions 31, 32 are spaced apart from the endwall edges of source and drain regions 16, 18 by respective portions 51, 52 of the extension regions 31, 32 of the same doping concentration as the body/channel region 14 itself, so that the more heavily doped (P+) channel stop tab regions 41, 42 do not form (very low breakdown voltage) P+/N+ junctions with the source and drain regions 16, 18. The source and drain regions may be formed by an N+ implant using an implant mask the geometry of which overlaps polysilicon gate layer 21, as shown at 55 in Figure 6. Pursuant to a third embodiment of the invention, the channel stops of the extension regions are configured to provide additional functionality, specifically to provide body tie contact regions, so that the body/channel region may be terminated at a prescribed bias voltage (e.g. Vss, which will substantially reduce parasitic sidewall originating current leakage during the transistor 7 s OFF state) . For this purpose, as shown in the diagrammatic top and side views of Figures 7 and 8, heavily doped 'bodytab' portions 61, 63 of P-type body/channel extension regions 31, 32 protrude to the side of or transverse to the lengthwise direction of the body/channel region 14 and its polysilicon gate overlay 21, so that the pair of heavily doped (P+) bodytabs 61, 63 project outwardly from beneath and to the side of the gate layer 21, thereby forming a symmetrical, bidirectional transistor geometry and facilitating the electrical connection of a bias voltage rail to the body/channel region from either end of the device. As in the second embodiment heavily doped bodytab regions 61, 63 are spaced apart from the end sidewalls of N+ source and drain regions 16, 18 by extension portions 51, 52, so that the more heavily doped (P+) channel stop tab regions 61, 62 do not form (low reverse breakdown voltage) P+/N+ junctions with the source and drain regions 16, 18. In accordance with a fourth embodiment of the invention, the problem of ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is addressed by means of an asymmetric sidewall channel stop structure formed in opposite end portions of one of the source and drain regions. Specifically, as diagrammatically illustrated in the isometric sectional view of Figure 9 and the top view of Figure 10, first and second end portions 71, 72 of one of N+ source and drain mesa regions are heavily overdoped with impurities of the same conductivity type as the body/channel region. In particular, these P+ end portions 71 and 72 are located such that they are contiguous with the (P) body/channel mesa region 14 and extend to sidewall edges 75, 76 of the source mesa region 16, thereby forming a demiurgic channel stop structure havin first and second mesa sidewall channel stops 81, 82 immediatel adjacent to ends 83, 84 of the (P) body/channel region 14 and whic extend throughout the thickness of the selected region (source regio 16) . The P+ implant photomask used to define the geometry of channel stop regions 81, 82 is sized and located such that it partiall overlaps (e.g. terminates along the centerline 90 of) polysilicon gate 21 and also extends beyond the side edge of the gate onto the source region, so as create a partially self-aligned P+ channel stop structure that is contiguous with the P-type body/channel region. Terminating the P+ channel stop implant masking photoresist pattern over polysilicon gate layer 21 guarantees that the P+ implant will not fall off the gate onto either the source or drain region side under statistically controlled misalignment conditions. Channel stop regions 71, 72 are doped with a P-type impurity during both a lightly doped P source/drain region implant and P+ surface source/drain implant operations, such that the composite doping profile of these regions is sufficient to inhibit sidewall inversion well into the megarad total dose range. The magnitude of P+ implant energy is predetermined to be sufficient to cause a pair of P source and drain regions of an associated complementary P-channel device to bottom out against insulator support layer 12. As a consequence, the P+ implant is similarly effective across the entire sidewall interface surface in the formation of the channel stops 81, 82. The shape and position of this heavy (P+) overdoping ensures that the sidewalls 83, 84 of the mesa adjacent to the location where gate electrode 21 exits the mesa are P-doped to the magnitude necessary to prevent sidewall inversion. The heavy overdoping also ensures that the parasitic sidewall threshold is higher in magnitude than any possible threshold shift that might occur as a result of the incidence of ionizing radiation. Even in the case of a very thick dielectrically filled trench isolation structure where the potential charge generation volume is relatively large, the sidewall remains adequately enhancement mode. Since P+ channel stops 81, 82 are disposed in the same N+ source region 16, they are physically and electronically separated from the N+ drain region 18 on the opposite side of body/channel region 14 over which polysilicon gate 21 is formed. Conductive material such as a layer of low resistance silicide 95 is formed atop each of gate layer and source and drain regions, as shown in Figure 9. Silicide layer 95 conductively bridges channel stop regions 81, 82 and source region 16, so that the body region 14 is inherently shunted to source region 16. Thus, P+/N+ junctions 91, 92 formed between the high impurity concentration P+ channel stops 81, 82 and the N+ material of source region 16 in which they are introduced are at the same potential, so that the reverse bias voltage characteristics of the diode are of no consequence. The amount of semiconductor real estate necessary to prevent sidewall inversion using the asymmetric channel stop configuration of Figures 9 and 10 is considerably reduced compared with other MOS channel stop architectures, shown in Figures 11-16, that have been conventionally used for this purpose. Specifically, in the course of carrying out a full self-alignment with the polysilicon gate in a T- gate structure, such as shown in Figure 11 and an H-gate structure shown in Figures 12 and 13, contacts must be added to the channel stop regions in order for the P+ regions to provide body tie capability. On the other hand, as described above, the asymmetric channel stop configuration of the embodiment of Figures 9 and 10 is inherently shunted to source region 16 by means of low resistance silicide 95. This bridging silicide layer 95 also eliminates the need for additional contacts and metalization, such as those shown in the structure of Figure 14, which employs N+ diffusions spaced inwardly away from the mesa edge. In fact, for small transistors, a single, minimum sized source contact to silicide layer 95 will serve to maintain the necessary bias on both sidewall channel stops 81, 82, while also providing bias to the body/channel region 14 and the source region 16. It will also be appreciated that conventional configuration employing full or partial guardrings (Figure 15) and circular gat structures (Figure 16) require significantly larger chip area t implement than do the asymmetric device of Figures 9 and 10, and mak high density memories and other digital circuits more difficult t design and manufacture. Indeed for guardring structures, at least on additional lithographic and ion implantation step is required prio to- the deposition of the gate electrode. On the other hand, i asymmetric device of the present invention no additional fabricatio operations, photomasking, or ion implantation steps are required. While we have shown and described several embodiments i accordance with the present invention, it is to be understood tha the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein . but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

Claims: WHAT IS CLAIMED 1 1. A semiconductor device comprising: 2 a substrate; * _ 3 a first semiconductor region of a first conductivity type formed 4 on a first surface portion of said substrate; 5 a second semiconductor region of a second conductivity type 6 formed on a second surface portion of said substrate contiguous with 7 said first surface portion so as to form a first junction with said 8 first semiconductor region, said first junction having a first length 9 along said first semiconductor region; 10 a third semiconductor region of said second conductivity type 11 formed on a third surface portion of said substrate, spaced apart 12 from said second surface portion by said first surface portion 13 therebetween, and being contiguous with said first portion so as to 14 form a second junction with said first semiconductor region, said 15 second junction having a second length along said first semiconductor 16 region; and wherein 17 said first semiconductor region extends as at least one 18 extension region beyond terminations of said second and third 19 semiconductor regions. 1 2. A semiconductor device according to claim 1, further 2 including a layer of conductive material overlying said first 3 semiconductor region, and wherein said layer of conductive material 4 is insulated from said first semiconductor region by a layer of 5 insulating material therebetween. 1 3. A semiconductor device according to claim 2, wherein said 2 at least one extension region extends outward from beneath said layer 3 of conductive material overlying said first semiconductor region. 1 4. A semiconductor device according to claim 1, wherein a 2 first portion of said at least one extension region has an impurity 3 concentration greater than the impurity concentration of another * 4 portion thereof adjacent to said first semiconductor region. 5. A semiconductor device according to claim 4, wherein sai first portion of said at least one extension region is arranged to b coupled to a prescribed voltage. 6. A field effect transistor device comprising: a dielectric substrate; a field effect transistor structure disposed on said dielectri substrate, said field effect transistor structure including a bod region of a first conductivity type formed on a first surface portion of said dielectric substrate, a source region of a second conductivity type formed on a second surface portion of said dielectric substrate contiguous with said first surface portion and forming a source/body junction with said body region, said source/body junction having a first length along said body region, a drain region of said second conductivity type formed on a third surface portion of said dielectric substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body junction with said body region, said drain/body junction having a second length along said body region, and a gate layer insulated from and overlying said body region for inducing therein a channel region between said source and drain regions, and wherein said body region extends beyond terminations of said source and drain regions as at least one body extension region. 7. A field effect transistor device according to claim 6, wherein a first portion of said at least one extension region has an impurity concentration greater than the impurity concentration of a second portion thereof adjacent to that portion of said body region between said source and drain regions. 8. A field effect transistor device according to claim 7, wherein said first portion of said at least one extension region is arranged to be coupled to a prescribed voltage, so that said body region may be biased at said prescribed voltage. 9. A field effect transistor device according to claim 8, wherein said first portion of said at least one extension region is arranged to be coupled to receive a voltage applied to said source region, so that said body region may be biased at said source region voltage. 10. A field effect transistor device according to claim 6, wherein said at least one extension region comprises first and second extension regions at opposite ends of said body region. 11. A field effect transistor device according to claim 10, wherein a first portion of said first extension region has an impurity concentration greater than that of a second portion thereof adjacent to a first end of said body region, and wherein a first portion of said second extension region has an impurity concentration greater than that of a second portion thereof adjacent to a second end of said body region. 12. A field effect transistor device according to claim 6, wherein said at least one extension region extends outwardly from beneath said gate layer overlying said body region. 13. A method of inhibiting edge current while providing a body tie path for an N-channel field effect transistor that is provided on a dielectric substrate, said N-channel field effect transistor including a P-type body region disposed on a first surface portion of said dielectric substrate, an N-type source region disposed on a second surface portion of said dielectric substrate contiguous with said first surface portion and forming a source/body PN junction with said P-type body region, said PN source/body junction having a first length along said P-type body region, an N-type drain region formed on a third surface portion of said dielectric substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body PN junction with said P-type body region, said drain/body junction having a second length along said body semiconductor region, and a gate layer insulated from and overlyi said P-type body region for inducing therein an N-channel regio between said source and drain regions, comprising the steps of: (a) extending said P-type body region beyond terminations o said source and drain regions as at least one P-type extensio region; and (b) coupling a prescribed voltage to said at least on P-typ extension region. 14. A method according to claim 13, wherein step (b) comprise coupling to said at least one P-type extension region a voltage tha is applied to said source region, so that said P-type body region i biased at the source region voltage. 15. A method according to claim 13, wherein step (a) comprise extending said P-type body region at opposite ends thereof so as t form first and second P-type extension regions at opposite ends o said P-type body region. 16. A method according to claim 13, wherein step (a) comprise controlling the impurity concentration of a first portion of said a least one P-type extension region spaced apart from said portion o said P-type body region disposed between said source and drai regions to be greater than the impurity concentration of a secon portion of said at least one P-type extension region contiguous with said portion of said P-type body region disposed between said source and drain regions. 17. A method according to claim 13, wherein step (a) comprises extending said P-type body region outward from beneath said gate layer overlying said P-type body region. 18. A mesa field effect transistor architecture comprising: a dielectric support substrate; a mesa field effect transistor structure disposed on said dielectric support substrate, said mesa field effect transistor structure including a body mesa region of a first conductivity type formed on a first surface portion of said dielectric support substrate, a source mesa region of a second conductivity type formed on a second surface portion of said dielectric support substrate contiguous with said first surface portion and forming a source/body junction with a first sidewall of said mesa body region, a drain mesa region of said second conductivity type formed on a third surface portion of said dielectric support substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body junction with a second sidewall of said body region, and a gate layer overlying said mesa body region for inducing therein a channel region between said source and drain mesa regions, said body mesa region extending beyond terminations of said source and drain mesa regions as at least one extension mesa region, and wherein a first end portion of said at least one extension mesa region has an impurity concentration greater than the impurity concentration of a portion of said body mesa region disposed between said source and drain mesa regions, so as to form a mesa sidewall channel stop. 19. A mesa field effect transistor architecture according to claim 18, wherein said first end portion of said at least one extension mesa region is spaced apart from said portion of said body mesa region disposed between said source and drain mesa regions by a second portion of said at least one extension mesa region, said second portion of said at least one extension mesa region having an impurity concentration less than that of said first end portion of said at least one extension mesa region. 20. A mesa field effect transistor architecture according t claim 18, wherein said at least one extension mesa region comprise first and second mesa extension regions at opposite ends of said bod mesa region, and wherein end portions of said first and second mes extension region have an impurity concentration greater than th impurity concentration of a portion of said body mesa region dispose between said source and drain mesa regions, so as to form first an second mesa sidewall channel stops. 21. A mesa field effect transistor architecture according to claim 20, wherein an end portion of said first extension mesa region is spaced apart from said portion of said body mesa region disposed between said source and drain regions by a second portion of said first extension mesa region, said second portion of said first extension mesa region having an impurity concentration less than that of said end portion of said first extension mesa region, and wherein an end portion of said second extension mesa region is spaced apart from said portion of said body mesa region disposed between said source and drain mesa regions by a second portion of said second extension mesa region, said second portion of said second extension mesa region having an impurity concentration less than that of said end portion of said second extension mesa region, whereby said first and second mesa sidewall channel stops are spaced apart from said source and drain mesa regions. 22. A mesa field effect transistor architecture according to claim 21, wherein said gate layer overlies said first and second mesa sidewall channel stops. 23. A mesa field effect transistor architecture comprising: a dielectric support substrate; a mesa field effect transistor structure disposed on said dielectric support substrate, said mesa field effect transistor structure including a body mesa region of a first conductivity type formed on a first surface portion of said dielectric support substrate, a source mesa region of a second conductivity type formed on a second surface portion of said dielectric support substrate contiguous with said first surface portion and forming a source/body junction with a first sidewall of said mesa body region, a drain mesa region of said second conductivity type formed on a third surface portion of said dielectric support substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body junction with a second sidewall of, said body region, and a gate electrode overlying said mesa body region for inducing therein a channel region between said source and drain mesa regions, said body mesa region extending beyond terminations of said source and drain mesa regions as at least one body mesa extension tab region, and wherein said gate electrode overlies said at least one body mesa extension tab region. 24. A mesa field effect transistor architecture according to claim 23, wherein said at least one body mesa extension tab region comprises first and second body mesa extension tab regions at opposite ends of said body mesa region. 25. A mesa field effect transistor architecture according to claim 24, wherein portions of said first and second body mesa extension tab regions have an impurity concentration greater than the impurity concentration of a portion of said body mesa region disposed between said source and drain mesa regions. 26 . A mesa field effect transistor architecture according t claim 2 5, wherein said gate electrode extends along and is insulate from end walls of said first and second extension tab regions a opposite ends of said body mesa region. 27. A mesa field effect transistor architecture comprising: a dielectric support substrate; and a mesa field effect transistor structure disposed on sai dielectric support substrate, said mesa field effect transistor structure including a body mesa region of a first conductivity type formed on a first surface portion of said dielectric support substrate, a source mesa region of a second conductivity type formed on a second surface portion of said dielectric support substrate contiguous with said first surface portion and forming a source/body junction with a first sidewall of said mesa body region, a drain mesa region of said second conductivity type formed on a third surface portion of said dielectric support substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body junction with a second sidewall of said body region, and a gate electrode overlying said mesa body region for inducing therein a channel region between said source and drain mesa regions, and first and second end portions of one of said source and drain mesa regions contiguous with said body mesa region and extending . to sidewalls of said one of said source and drain mesa regions are doped with impurities of said first conductivity type, forming first and second mesa sidewall channel stops in said first and second end portions of said one of said source and drain mesa regions respectively. 28. A mesa field effect transistor architecture according to claim 27, further including conductive material formed atop said one of said source and drain mesa regions, conductively bridging said first and second portions of said one of said source and drain regions with said one of said source and drain regions. 29. A mesa field effect transistor architecture according to claim 28, wherein said first conductivity type is P-type, said second conductivity type is N-type, said one of said source and drain regions corresponds to said source region, and said first and second portions of said source region have an impurity concentration greater than the impurity concentration of said body mesa region. 30. A mesa field effect transistor architecture according to claim 29, wherein the conductive material formed atop said source region is coupled to receive a prescribed bias voltage which is coupled to said first and second portions of said source region and thereby to said mesa body region.

Inventors: CHERNE RICHARD D, CLARK JACK E II, DEJONG GLENN A, LICHTEL RICHARD L, MORRIS WESLEY H, SPEECE WILLIAM H, CHERNE, RICHARD, D., CLARK, JACK, E., II, DEJONG, GLENN, A., LICHTEL, RICHARD, L., MORRIS, WESLEY, H., SPEECE, WILLIAM, H.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1992
Main classification: H01L27
IPC codes: H01L27, H01L29