Method of manufacturing polysilicon film

Abstract: A method of fabricating a polysilicon film whose crystal grain size can be controlled in a wide range and which has a large surface area, and an application thereof to a DRAM are disclosed. An amorphous silicon film (103) is formed on a silicon oxide film (102) on a silicon substrate (101). In polycrystallizing the amorphous silicon film having a substantially clean surface, nucleation and crystal growth are performed under different conditions; e.g. by lowering the temperature. Then a dielectric film (106) is formed on the polysilicon film, and a conductive film (107) is formed on the dielectric film to form a capacitance electrode. With this method, crystal grains (105) are formed with a crystal grain density and crystal grain size which can be controlled easily, causing a polysilicon film having finer grains to be formed, and permitting reduction of capacitor area due to increase of integration density of DRAM.

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device and, particularly, to a method of manufacturing a polysilicon film suitable for use as a capacitor electrode. With the recent increase of integration density of DRAMS, cell size and the area occupied by a capacitor of the DRAM cell tend to reduce, respectively. In order to keep a capacitance of such capacitor at an acceptable value, a stacked capacitor or a trench stacked capacitor has been used since it can provide a large capacitor area therein, has anti-alpha ray characteristics and is capable of reducing interference between DRAM cells. For a DRAM of 64 Mbits, a cell area is estimated as 2 µm² or less. When such capacitor as. mentioned above is incorporated in such DRAM, a silicon oxide film as thin as 50 Å is required as a dielectric film of the capacitor. It is very difficult to form such thin silicon oxide film on a whole chip uniformly without defects. Therefore, it has been proposed to increase the above-mentioned area of the capacitor portion while keeping the thickness of the capacitor insulating film as it is. By way of background a discussion of certain other proposals will now be given. Published patent application No. GB 2130009A teaches a method for annealing amorphous silicon films deposited by chemical vapour deposition to provide polycrystalline layers of very low surface roughness and low strain. The layers are deposited between 560°C and 580°C and annealed between 850°C and 1000°C. A paper entitled "Selective Area Crystallisation of Amorphous Silicon Films by Low-Temperature Rapid Thermal Annealing" by Gang Liu et al in Applied Physics Letters, vol. 55, no. 7, 14th August 1989, New York, USA, pages 660-662, reports that in areas of an amorphous silicon film on which an ultrathin palladium layer was deposited prior to annealing, the annealing temperature required to induce crystallisation was reduced compared with uncoated areas from, for example, 700°C to 500°C for an annealing time of 4 minutes. A paper entitled "A New Stacked Capacitor Structure using Hemispherical-Grain, Poly-Silicon Electrodes" by H. Watanabe et al. in the Japanese Journal of Applied Physics Extended Abstracts, 22nd Conference on Solid State Devices and Materials, 1990, Tokyo, Japan, pages 873-876, report that the capacitance of a storage capacitor in a DRAM cell can be increased by providing a crystalline silicon film having a rough surface as a capacitor electrode. The so-called hemispherical-grain, poly-silicon film was prepared by low-pressure, chemical-vapour deposition at 550°C. European patent application No. EP 91302414.7, published as EP 0448374A, claims three earlier priority dates than this application but was published after the priority dates of this application. EP 0448374A describes a process in which, by lowering the temperature in forming a polysilicon film by LPCVD from 600°C which has been used conventionally to about 550°C, dense crystal grains each having hemispherical shape grow on a surface of a substrate in a boundary region thereof in which amorphous silicon is transferred to polysilicon, resulting in a surface area of the polysilicon film twice that grown at 600°C. In Watanabe et al., a sufficient capacitance value and low leak current value are obtained with a silicon oxide film 100 Å thick by applying such polysilicon film to a charge storage electrode of a stacked capacitor. However, according to the method of EP 0448374A, the temperature at which such hemispherical crystal grains grow on the surface is limited to a very narrow range from 545°C to 555°C. Therefore, it is very difficult to control growing temperature within such a small range as 10°C for mass production. Further, when, in order to isolate between adjacent capacitors, dry-etching is performed after such polysilicon film formation, a side wall portion of the storage electrode is flattened by etching, which is a problem in realizing a large capacitance value. EP 0448374A also states that a polysilicon film containing hemispherical or mushroom-shaped crystal grains is obtained by forming an amorphous silicon film and heating it in vacuum condition. A sufficient capacitance value and low leak current value are obtained with a silicon oxide film 100 Å thick by applying such polysilicon film to an electrode of a stacked capacitor. That is, crystal nucleation is performed on a surface of an amorphous silicon film and nuclei thus.produced grow when it is heated at a constant temperature in a range from 550°C to 700°C. Since the surface diffusion rate of silicon on a clean amorphous silicon film surface is very high compared with the growing rate of solid phase epitaxy, silicon is concentrated to the nuclei by surface diffusion and thus mushroom-shaped crystal grains are obtained. An upper limit of grain size is determined at a time when grains grow to the extent that adjacent grains contact each other. Thus, average grain size depends upon density of crystal nuclei produced by nucleation in unit time, that is, nucleation rate. In other words, the average grain size is determined by substrate temperature in an initial stage of substrate heating. The higher the substrate temperature, the higher the nucleation rate and thus the smaller the average grain size. However, since the activation energy of crystal nucleation of amorphous silicon film is larger than the activation energy of surface diffusion of silicon atoms, crystals may grow rapidly before crystal nuclei density becomes enough even if the substrate temperature is increased for the purpose of reducing average grain size. Therefore, it is difficult to obtain a polysilicon film having small enough grain size. Further, variation of grain size is also increased. In addition, since atom migration becomes large with increase of temperature, grain shape becomes relatively smooth and flat compared with the hemispherical shape. As an example, it is possible to obtain a polysilicon film having average grain size of about 1500 Å at a substrate temperature of 650°C. When a capacitor electrode area is reduced to 2 µm², the number of crystal grains formed on the capacitor electrode may vary. A capacitance value is twice at most compared with that of a flat electrode surface and about 1.5 times in average. As described, since, according to the conventional technique, the generation and growth of crystal nuclei are performed at a constant temperature, it is very difficult to form a polysilicon film having small enough grain size and large enough surface area with acceptable reproducibility. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a manufacturing method of a semiconductor device having a polysilicon film whose surface area is large and whose crystal nuclei density and crystal grain size are controllable over wide ranges, respectively. The invention provides methods of fabricating semiconductor devices as defined in the appendent independent claims, to which reference should now be made. Preferred features of the invention are defined in dependent-sub-claims. In a preferred embodiment, the invention includes the steps of depositing an amorphous silicon film on a desired interlayer insulating film of a semiconductor chip, nucleating a clean surface of the amorphous silicon film under predetermined conditions and allowing nuclei thus produced to grow under other conditions. The term "clean surface" means a state of surface such as as-grown surface of a film formed by MBE, surface of a film which is exposed only to an inert gas such as nitrogen or argon after formation of the film, surface whose natural oxide film formed after film formation is removed by fluoric acid solution to terminate the surface with hydrogen atoms or fluorine atoms and which is then heated to a temperature lower than the crystallization temperature of amorphous silicon film in vacuum or inert gas to separate the hydrogen atoms or fluorine atoms, or surface after natural oxide film is removed by irradiation with rare gas ions such as argon. In a first embodiment of the present invention, crystal nuclei are produced on an amorphous silicon film by heating the latter and then the crystal nuclei are allowed to grow by decreasing the temperature. Average grain size of a polysilicon film depends upon nucleation rate which corresponds to the density of crystal nuclei generated in unit time and crystal growing rate. The higher heating temperature results in a higher nucleation rate as well as crystal growing rate. Density of crystal nuclei increases with time at a nucleation rate which depends upon the substrate temperature. However, when the crystal growing rate exceeds the crystal nucleation rate, generation of new crystal nuclei is blocked by already grown crystal nuclei. Therefore, control of crystal grain size is facilitated by making the heating temperature for crystal nucleation high, heating time short and the temperature for crystal growth low. In a second embodiment of the present invention, crystal nucleation is performed by exposing an amorphous silicon film to silicon compound gas for a predetermined constant time while keeping it at a predetermined temperature, and crystal nuclei produced are allowed to grow by continuously heating the film without exposing it to the silicon compound gas. Since silicon compound is decomposed at dangling bonds in the amorphous silicon film surface to produce crystal nuclei, nucleation rate becomes higher than that obtained only by heating, facilitating control of crystal grain size and enabling finer crystal grains to be formed. In a third embodiment of the present invention, nucleation is performed by irradiating an amorphous silicon film with a silicon molecular beam for a predetermined time while keeping the film at a predetermined temperature and crystal nuclei thus produced are allowed to grow by continuously heating the film without irradiation by the silicon molecular beam. Since there is no chemical reaction used, it is possible to perform nucleation at a lower temperature. Since it is possible to realize a capacitor having large capacitance per unit area with high reproducibility by forming a dielectric film on a polysilicon film having large surface area and forming a conductive film thereon, it is possible to further increase the integration density of DRAM. BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other objects, features and advantages of the present invention will become more apparent by reference to the following detailed description of the present invention taken in conjunction with the accompanying drawings, wherein: Fig. 1(a) is a cross section of a semiconductor chip for explanatory purposes of a first embodiment of the present invention; Fig. 1(b) is a cross section of a semiconductor chip for explaining a step subsequent to the step corresponding to Fig. 1(a); Fig. 1(c) is a cross section of a semiconductor chip for explaining a step subsequent to the step corresponding to Fig. 1(b); Fig. 1(d) is a cross section of a semiconductor chip for explaining a step subsequent to the step corresponding to Fig. 1(c); Fig. 1(e) is a cross section of a semiconductor chip for explaining a step subsequent to the step corresponding to Fig. 1(d); Fig. 2 is a graph showing a relation between average grain size and the ratio of heating time for nucleation to total heating time in the first embodiment of the present invention; Fig. 3 is a graph showing a relation between capacitance value of a capacitor and the ratio of heating time for nucleation to total heating time in the first embodiment of the present invention; Fig. 4 is a cross section of a semiconductor chip for explaining nucleation in a second embodiment of the present invention; Fig. 5 is a graph showing a relation between nucleation time and heating temperature in the second embodiment of the present invention; Fig. 6 is a graph showing a relation between average crystal grain size and irradiation time with Si₂H₆ gas in the second embodiment of the present invention; Fig. 7 is a graph showing a relation between crystal grain density and flow rate of Si₂H₆ gas in the second embodiment of the present invention; Fig. 8 is a graph showing a distribution of crystal grain size in the second embodiment of the present invention; Fig. 9 is a graph showing a relation between capacitance value of a capacitor and heating temperature in the second embodiment of the present invention; Fig. 10(a) is a cross section of a semiconductor chip for explaining a third embodiment of the present invention; Fig. 10(b) is a cross section of a semiconductor chip for explaining a manufacturing step subsequent to that corresponding to Fig. 10(a); Fig. 11 is a graph showing a relation between crystal grain density and substrate temperature in the third embodiment of the present invention; Fig. 12 is a graph showing a relation between capacitance value of a capacitor and substrate temperature in the third embodiment of the present invention; Fig. 13 is a graph showing a relation between crystal grain density and irradiation rate of molecular beam in the third embodiment of the present invention; Fig. 14 is a graph showing a relation between capacitance value of a capacitor and irradiation rate of molecular beam in the third embodiment of the present invention; Fig. 15 is a graph showing a distribution of crystal grain size in the third embodiment of the present invention; and Fig. 16 is a cross section of a semiconductor chip showing a main portion of a DRAM formed according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to Figs. 1(a) to 1(e). As shown in Fig. 1(a), a silicon oxide film 102 having thickness of 2000 Å is formed on a surface of a silicon substrate 101 having diameter of 4 inches (100mm) by thermal oxidation. Then the substrate is inserted into a molecular beam epitaxy (MBE) apparatus and irradiated with a silicon molecular beam from an electron gun type silicon evaporator at irradiation rate of 7 Å/sec, the substrate being at room temperature, to form an amorphous silicon film 103 having thickness of 4000 Å. Thereafter, phosphor ions are implanted there into at density of 5 x 10¹⁵ cm⁻² with acceleration voltage of 50 keV. With lamp heating thereafter, crystal nuclei 104 are produced as shown in Fig. 1(b). The nucleation process was performed at heating temperatures Tn of 600°C, 650°C and 700°C, respectively. Heating at each temperature was performed over heating times tn of 0 min, 5 min, 10 min and 20 min, respectively. With heating at 550°C for time tv after the nucleation process, mushroom shaped or hemisphere shaped crystal grains 105 were obtained as shown in Fig. 1(c). Fig. 2 shows a relation between average grain size and ratio of nucleation time tn to the total heating time (tn/(tn + tv)) when the total heating time (tn + tv) is set to 20 min. The leftmost data correspond to a case where polycrystallization is performed at a constant temperature of 550°C and the rightmost data correspond to a case where polycrystallization is performed at constant temperatures of 600°C, 650°C and 700°C, respectively. It is clear from Fig. 2 that average crystal grain size can be made smaller when nucleation and growth are performed at different temperatures and/or when heating temperature is higher. Average grain size of crystals formed by poly-crystallization of an amorphous silicon film depends upon the density of nuclei produced in unit time, that is, nucleation rate, and the growing rate of the nuclei. The higher the heating temperature, the higher the nucleation rate. In that case, however, the growing rate of nuclei also increases. Density of nuclei increases with increase of nucleation rate which depends upon substrate temperature. When nuclei growing rate exceeds nucleation rate, existing nuclei grow prior to new nucleation, so that nucleation cannot occur any more. Therefore, in order to form fine crystal grains, it may be enough to raise the heating temperature Tn for nucleation, reduce heating time tn and lower heating temperature Tv for crystal nuclear growth to a value lower than Tn at which nucleation rate is small enough. Further, preferably, temperature control therefor should be sharp to heat/cool rapidly. Although, in Fig. 1(c), polysilicon grains 105 are shown as having uniform mushroom shape, they may be not uniform in shape and in size in practice. Then, as shown in Fig. 1(d), a silicon nitride film was formed by Low Pressure CVD (LPCVD) and a surface thereof was oxidized to form a capacitor insulating film 106. Thickness of this capacitor insulating film 106 is selected to be any suitable value in a range from 30 Å to 100 Å in SiO₂ film equivalent. Thereafter, as shown in Fig. 1(e), a polysilicon film 107 was deposited thereon and doped with phosphorus. Then, the polysilicon film was patterned to form an electrode, and a capacitor 1 mm x 1 mm wide was formed, whose capacitance was measured. The result is shown in Fig. 3. In this case, the thickness of the capacitor insulating film 106 was 100 Å in SiO₂ film equivalent. It is clear from Fig. 3 that capacitance of the capacitor generally increases with decrease of average grain size. Although, this embodiment was described with a silicon wafer as the substrate, the present invention is, of course, equally applicable to an SOS (Silicon-on-Sapphire) substrate in which silicon exists in only a surface region thereof or even generally to an SOI (Silicon-on-Insulator) substrate, etc. Further, although the amorphous silicon film is formed in the MBE apparatus using electron gun type silicon deposition equipment, it can be formed by LPCVD or sputtering. It has been confirmed that an effect similar to that obtained by the described embodiment is obtained for an amorphous silicon film formed by these other methods after removal of a natural oxide film on a surface thereof. Pressure in the forming apparatus is not always ultra high vacuum pressure. The important thing is to heat the amorphous silicon film while a surface thereof is kept clean. It has been confirmed that similar phenomena to those which occured in the described embodiment occur when the treatment is done in an atmosphere of gas which is non-reactive to the amorphous silicon surface, such as nitrogen gas or helium gas. Heating is not limited to lamp heating so long as heating and cooling can be done rapidly. A second embodiment of the present invention will be described. As in the first embodiment, an amorphous silicon film having thickness of 4000 Å is formed by MBE or LPCVD and ion-implanted with phosphorus. After contamination on a surface of the amorphous silicon film is removed by dipping it in washing liquid (60°C) which is a mixture of NH₄OH, H₂O₂ and H₂O in a ratio of 1 : 6 : 20, the film is dipped in 5 % fluoric acid solution for 30 seconds to remove a natural oxide film. The wafer is dried by a centrifugal separator or dried nitrogen gas and then inserted into a forming chamber of an ultra high vacuum CVD equipment having a Si₂H₆ supply nozzle. The forming chamber is kept at 10⁻⁹ Torr and has a substrate heating equipment such as graphite heater. First, the substrate is heated to a certain constant temperature, preferably a temperature as low as 500°C to 620°C at which nucleation does not occur rapidly, and then, by supplying Si₂H₆ to the forming chamber at flow-rate of 13 sccm, nuclei 104A such as shown in Fig. 4 are generated. Nucleation can be confirmed by in-situ observation using reflection HEED (RHEED). Si₂H₆ gas is decomposed at dangling bonds existing in the clean surface of the amorphous silicon film, resulting in polysilicon nuclei on the surface at higher density than that obtained conventionally. Fig. 5 shows a relation between time before nucleation is confirmed (nucleation time) and heating temperature. From Fig. 5, it is clear that nucleation time is very long at a temperature below 500°C while crystal nuclei are produced rapidly at a temperature above 650°C. After the substrate is exposed to the gas for a constant time, heat treatment is continued under high vacuum pressure to grow the nuclei. When heating temperature is changed from 540°C to 800°C, unevenness of the substrate surface due to crystal grains of hemisphere shape or mushroom shape is still confirmed although nucleation time is changed, as shown in Fig. 5. That is, nucleation is observed over a large temperature range. At a temperature above 650°C, both nucleation and subsequent crystal growth of small grains having large surface area occur very rapidly. However, when heating continues, the surface unevenness of polysilicon film becomes small. Therefore, it is preferred to use equipment capable of heating and cooling rapidly in order to control the surface configuration of the substrate. Even at low temperatures at which nucleation does not occur rapidly, surface diffusion rate of silicon atoms at a clean surface of amorphous silicon film is very high compared with solid phase growing rate. Silicon atoms are concentrated to crystal nuclei formed on its surface by surface diffusion, resulting in fine, mushroom shaped crystal grains. When the reaction is continued further, grown crystal grains come into contact with each other. Since there is no feed of silicon atoms from the amorphous silicon due to surface diffusion at boundaries between adjacent grains, growth of crystal grains is terminated, resulting in hemisphere shaped grains on the substrate surface. Since grain size of the grown crystal is smaller than that when grains are formed only by heating, because its original nuclei density is high and growth is performed at low temperature, resultant grain shape becomes close to real hemisphere. Fig. 6 shows a relation between Si₂H₆ gas supply time and average grain size of hemispherical crystal grains when heating is performed at 600°C for a constant time of 45 seconds. From Fig. 6, it is clear that grain size is in inverse proportion to Si₂H₆ gas supply time. This is because a number of nuclei are produced on a surface as crystal seeds, the number being in proportion to Si₂H₆ gas supply time, and grow to mushroom or hemisphere shape. However, supply of Si₂H₆ gas beyond 45 seconds makes adjacent crystal grains too close to each other, resulting in insufficient surface unevenness. For gas supply for 45 seconds, it is possible to make grain size smaller down to 300 Å. Crystal grain density also has a dependency on flow rate of Si₂H₆ gas. Fig. 7 shows a relation between flow rate of Si₂H₆ gas and crystal grain density when gas supply time is 5 seconds and heating time is 45 seconds. When flow rate of Si₂H₆ gas exceeds a certain constant value, crystal grain density becomes substantially constant. This phenomenon can be explained in that a predominant portion of hydrogen atoms bonded to an amorphous silicon film surface due to washing with an aqueous solution of fluoric acid becomes free therefrom by heating. Such reaction rate determining region should be utilized in view of control of crystal grain density and grain size. Fig. 8 shows a distribution of crystal grain size when Si₂H₆ gas at 600°C is supplied at flowrate of 2 sccm for 80 seconds. Heating time was 80 seconds. From Fig. 8, it can be said that distribution range is relatively narrow. Thereafter, a capacitor insulating film is formed in a similar manner to that used in the first embodiment. In this case, it is preferable that there is enough distance between adjacent crystal grains 105 so that they do not contact each other by the capacitor insulating film. This can be achieved by controlling heating time. Fig. 9 shows a relation between capacitance of the capacitor and heating temperature. Thickness of the capacitor insulating film is 100 Å in SiO₂ equivalent and area thereof is 1 mm x 1 mm. Data shown in Fig. 9 is the best one among those obtained by experiments performed by varying flow rate of Si₂H₆ gas and gas supply time at respective heating times. Data obtained under the same conditions without Si₂H₆ gas supply is shown for comparison purposes. From Fig. 9, it is clear that, when Si₂H₆ gas is supplied, an increase of capacitance value of the capacitor starts at a lower temperature than that for the case where no Si₂H₆ gas is supplied. This is because, when Si₂H₆ gas is supplied, nucleation occurs at low temperature. The increase of capacitance value is 2.5 times at a temperature from 540°C to 650°C and is smaller outside this range. This is so, although, as mentioned previously, heating must be terminated within a short time when high temperature heating is used, and the substrate heating equipment used in this embodiment had no facility of doing so and thus the substrate surface was smoothened. On the other hand, when only heating is performed, capacitance peaks at 650°C, the value being very small compared with the present invention. This is due to the fact that surface configuration becomes smooth by high temperature heating as in the case of the nucleation with gas. Such smoothing of surface configuration at high temperature in both cases may be prevented by using heating equipment such as a lamp heater which can heat/cool rapidly and by reducing heating time. According to this embodiment, it is possible to form a polysilicon film of finer grain size than that obtained by the first embodiment and thus to realize capacitance increase in the wide temperature range of heating. Although this embodiment has been described using silicon wafer as the substrate, the present invention is also applicable to an SOS substrate in which silicon exists in only a surface region and even to an SOI substrate, generally. Further, although, in this embodiment, the amorphous silicon film is nucleated by using Si₂H₆ gas in the ultra high vacuum equipment, Si₂H₆ gas may be substituted by other gases such as SiH₄, SiCl₂H₂, etc., containing silicon with similar effect. Pressure in the forming apparatus is not always ultra high vacuum pressure. The important thing is to heat the amorphous silicon film while a surface thereof is kept clean. It has been confirmed that similar phenomena to those which occurred in the described embodiment occur when the treatment is done in an atmosphere of a gas which is non-reactive to the amorphous silicon surface, such as nitrogen gas or helium gas. Heating is not limited to lamp heating so long as heating and cooling can be done rapidly. Further, although the natural oxide film of the amorphous silicon film formed by LPCVD is removed by washing it with aqueous solution of fluoric acid, the amorphous silicon film may be formed by MBE. Further, washing of the amorphous silicon film surface with other material than aqueous solution of fluoric acid may be used. It is essential that a clean surface of the amorphous silicon film is subjected to gas containing silicon. A third embodiment of the present invention will be described. As in the first embodiment or the second embodiment, a silicon oxide film 102 is formed on a surface of a silicon substrate 101 by thermal oxidation and then the substrate is inserted into a molecular beam epitaxy (MBE) apparatus and irradiated with a silicon molecular beam from an electron gun type silicon evaporator at irradiation rate of 7 Å/sec and at room temperature to form an amorphous silicon film 4000 Å thick. Silicon molecular beam irradiation is stopped and the substrate is lamp-heated to a certain constant temperature in a range from 400°C to about 500°C, at which thermal nucleation does not occur, and irradiated with a silicon molecular beam at irradiation rate of 1 Å/sec. As illustrated in Fig. 10(a), there are a surface atom layer 203A and an adsorbed atom layer 203B in the amorphous silicon film 203 during this irradiation by the silicon molecular beam. Although there is no nucleation, atoms in the surface atom. layer 203A of the amorphous silicon film 203 diffuse in the surface with a certain activation energy E1. On the other hand, atoms in the adsorbed atom layer 203B also diffuse with activation energy E2 which is considerably smaller than E1. Therefore, adsorbed atoms nucleate in that surface regardless of low substrate temperature, resulting in fine crystal grains 204 as shown in Fig. 10(b). When the irradiation with the silicon molecular beam is stopped while continuing heating, diffusing surface atoms are trapped by these crystal grains to grow the latter grains into a polysilicon film containing mushroom shaped crystal grains 105 as shown in Fig. 1(c). Thus, a polysilicon film having large surface area is formed. Then, a capacitor is formed in a similar manner to that described with reference to the second embodiment. Fig. 11 is a graph showing a relation between substrate temperature and crystal grain density immediately after irradiation with a silicon molecular beam with irradiation rate of 1 Å/sec for 50 seconds. From Fig. 11, it is clear that, with increase of the substrate temperature crystal grain density is increased and crystal grain size is decreased. Average grain size in Fig. 11 is measured when grains contact each other and there is no further grain size increase. Fig. 12 is a graph showing a relation of capacitance value of the capacitor and temperature of the substrate when it is irradiated at a rate 1 Å/sec. From this graph it is clear that the higher the substrate temperature, that is, the higher the crystal grain density, the larger the capacitance value. The capacitance value itself is larger than that for the polysilicon film formed by the conventional substrate heating method (cf. Fig. 3). Fig. 13 is a graph showing a relation of grain density immediately after irradiation of a substrate maintained at 450°C with a silicon molecular beam for 50 seconds to irradiation rate. This clearly shows that crystal grain size also depends upon irradiation density and can be sufficiently controlled by varying irradiation rate. Fig. 14 shows a graph showing a relation between capacitance value of capacitor and irradiation rate. It is clear from this figure that the higher the irradiation rate, that is, the higher the crystal grain density, the larger the capacitance value. The capacitance value itself is larger than that for the polysilicon film formed by the conventional substrate heating method. Grain size distribution is shown in Fig. 15. Data in Fig. 15 is obtained when a substrate maintained at 460°C is irradiated with a silicon molecular beam at 1 Å/sec for 30 seconds and then further heated for 60 minutes. For comparison purpose, data obtained when an amorphous silicon film is heated for 1 minute in vacuum is also shown. According to this embodiment, variation of crystal grain size is substantially reduced. This embodiment makes a formation of polysilicon film at lower temperature than in the second embodiment possible. Although this embodiment has been described with reference to a silicon wafer, the present invention is also applicable to an SOS substrate in which silicon exists in only a surface region and even to an SOI substrate, generally. Further, although in this embodiment the amorphous silicon film is formed by using an electron gun type silicon evaporator in an MBE apparatus, similar effect was obtained for an amorphous silicon film prepared by LPCVD or sputtering method and having a surface whose natural oxide film is removed. Pressure in the forming apparatus is not always ultra high vacuum pressure. The important thing is to heat the amorphous silicon film while a surface thereof is kept clean. It has been confirmed that similar phenomena to those which occured in the described embodiment occur when the treatment is done in an atmosphere of a gas which is non-reactive to the amorphous silicon surface, such as nitrogen gas or helium gas. Now, a semiconductor DRAM formed by applying the present invention will be described with reference to Fig. 16 showing a main portion of the DRAM cell. A field oxide film 308 is formed on a surface of a P type silicon substrate 301 to isolate transistor forming regions from each other. A gate oxide film 309 is formed in a transistor forming region and gate electrodes 310 which also function as wordlines are formed across the transistor forming region.. Then, ion implantation is performed to the forming region through the gate electrodes 310 and the field oxide film 308 as a mask to form N⁺ type diffusion layers 311s and 311d. Then an interlayer insulating film 302 of silicon oxide is deposited; through which a contact hole C is formed on the region 311s. On the wafer, an amorphous silicon film is deposited by LPCVD, etc., and, after patterning thereof, the wafer is washed with a mixture solution of NH₃OH, H₂O₂ and H₂O and then a natural oxide- film on the amorphous silicon film is removed by using fluoric acid solution. Then, the amorphous silicon film is converted into polysilicon film in a similar manner to that used in the second embodiment to form a capacitance storage electrode 305. In this conversion process, the amorphous silicon film starts to be polycrystallized at a contact portion with the region 311s by solid phase epitaxy. However, since polycrystallization rate is low compared with poly-crystallization by Si₂H₆ irradiation, there is no adverse effect on surface configuration of the capacitance storage electrode 305. Further, since the surface of the amorphous silicon film is exposed uniformly to Si₂H₆ gas, a desired, substantially uniform unevenness is obtained on the surface of the capacitance storage electrode 305 including its side wall. Then, a capacitor insulating film 306 is formed and a facing electrode 307 is formed using the polysilicon film, etc. Thus, a capacitor connected to the region 311s of a MOS transistor can be formed, resulting in a high integration density DRAM. When the third embodiment is to be applied to a formation of such a DRAM, it is preferred that the storage electrode is formed by patterning following the polycrystallization immediately after the formation of the amorphous silicon film. The reason for this is that, although it may be possible to form the polycrystallization after patterning, it is difficult to obtain a satisfactory unevenness of the side wall of the electrode in view of the directional nature of the molecular beam and, therefore, it is better to omit the step of removing the natural oxide film.

Claims: A method of fabricating a semiconductor device, comprising the steps of; forming a capacitance electrode by depositing an amorphous silicon film over an insulating film on a semiconductor chip, nucleating crystal nuclei at a surface of the amorphous silicon film which is substantially clean and devoid of a native oxide layer by holding the semiconductor chip at a temperature in the range 600°C to 700°C in a vacuum or in a gas with which the amorphous silicon film is substantially non-reactive; growing the crystal nuclei at a temperature of 550°C to form a polysilicon film; forming a dielectric film on the polysilicon film; and forming a second capacitance electrode by forming a conductive film on the dielectric film. A method of fabricating a semiconductor device, comprising the steps of; forming a capacitance electrode by depositing an amorphous silicon film over an insulating film on a semiconductor chip, nucleating crystal nuclei at a surface of the amorphous silicon film which is substantially clean and devoid of a native oxide layer by heating the semiconductor chip to a temperature in the range 540°C to 800°C while supplying gaseous silane, disilane or chlorosilane; growing the crystal nuclei by terminating supply of the gas and continuing the heating; forming a dielectric film on the polysilicon film; and forming a second capacitance electrode by forming a conductive film on the dielectric film. The method claimed in claim 2, in which the nucleation is performed by patterning the amorphous silicon film in an atmospheric environment, washing the patterned film with fluoric acid solution, drying it and supplying disilane (Si₂H₆) gas at a predetermined pressure. A method of fabricating a semiconductor device, comprising the steps of; forming a capacitance electrode by depositing an amorphous silicon film over an insulating film on a semiconductor chip, nucleating crystal nuclei at a surface of the amorphous silicon film which is substantially clean and devoid of a native oxide layer by heating the semiconductor chip in a vacuum and irradiating it with a silicon molecular beam; growing the crystal nuclei by terminating the irradiation with the silicon molecular beam and holding the semiconductor chip at a temperature in the range 400°C to 500°C; forming a dielectric film on the polysilicon film; and forming a second capacitance electrode by forming a conductive film on the dielectric film.

Inventors: SAKAI AKIRA C O NEC CORPORATIO, TATSUMI TORU C O NEC CORPORATI, SAKAI, AKIRA, C/O NEC CORPORATION, TATSUMI, TORU, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L27