Overflow detection system and its circuit for use in addition and subtraction

Abstract: In an overflow detection circuit for A+B operation, an inverter outputs a value V B ' of inverteed bits of a numeric part of addend B. A comparator inputs a numeric part V A of an augend A and an output V B ' of the inverter and outputs a signal C indicating whether or not V g > V B ' is given. Sign parts S A and S B of A and B and the output C of the comparator are inputted into the decoder and an overflow signal O is outputted. The decoder is a circuit which outputs 1 when S A and S B are 0 and V g is large and when S A and S B are 1 and V A is small and 0 in other cases. If the comparator is a circuit for determining V g ≧V B ', the overflow of A+B+1 can be detected. Thus, the overflow of the result of operation can be detected earlier than an adder and a substracter output the results.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overflow detection system and its circuit for use in addition and subtraction by a digital operating unit. 2. Description of the Prior Art Conventionally, an overflow signal as to the results of addition and subtraction of two digital values has been detected using a carry signal obtained as a result of addition and subtraction or during operation. Fig. 1 shows an adder for adding digital values expressed as n-bit 2's complements according to the ripple carrying system. a i is the ith value of augend A, b i is the (i)th value of addend B, c i is the (i)th carry output signal, and s i is the (i)th sum output. a n-1 and b n-1 are respectively a sign part of augend A and addend B and the following bits form a numeric part. The adder body is formed by connecting n sets of full adders 100 each of which enters the (i)th bit values of the augend and addend and the (i-1)th bit carry signal output and outputs the (i)th bit sum and the carry signal. The overflow signal is obtained by the exclusive OR circuit 101 which uses the carry signal c n-1 from the sign part and the carry signal c n-2 from the MSD of the numeric part as inputs. Also in case the expression method of negative numerals other than the 2's complement is adopted, the overflow of the result of addition is detected from the carry signal from the sign part and the carry signal from the MSD of the numeric part. However, the conventional overflow detection method is disadvantageous in that the overflow has been determined at the same time or after the result of sum was obtained since the overflow has been detected from the result of addition and the carry signal. The European Patent publication EP-A-0 142 912 discloses an apparatus for predicting condition code like overflow by comparing operands in a comparator made of half adder. The comparator determines the carries out from the two highest bit positions without performing full addition and supplies the carries to a selection logic in which they are logically combined. Detection of the overflow for algebraic addition is based on the operands in their true form whereas for algebraic substraction, the second operand is inverted for overflow detection. SUMMARY OF THE INVENTION An object of the present invention is to provide an overflow detection system and its circuit which detects an overflow signal independent of an adder. The overflow detection method and circuit of the invention are defined in independent claims 1 or 2 and 3 or 4, respectively. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the detection of overflow of the conventional adder; Fig. 2 is a block diagram showing an embodiment of the overflow detection circuit according to the present invention; Fig. 3 is a diagram showing the overflow range when A+B operation of 4-bit digit values is carried out; Fig. 4 is a diagram showing the image of the overflow range when the numeric part of addend B is inverted; Fig. 5 is a diagram showing the overflow range when A+B+1 operation with 4-bit digit values is carried out; Fig. 6 is a diagram showing the image of the overflow range when the numeric part of addend B is inverted; Fig. 7 is a block diagram showing another embodiment oft he overflow detection circuit according to the present invention; and Fig. 8 is a block diagram showing another further embodiment of the overflow detection circuit according to the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The following description explains the overflow detection method according to the present invention, referring to Figs. 3 to 6. In this case, an example of 4-bit digit values is shown and the generality is not lost and the case of n-bit digit values can be similarly considered. Fig.3 is a diagram prepared by entering "x" in the coordinates when the result of A+B causes an overflow where augend A is plotted on the abscissa and addend B is plotted on the ordinate. The range where an overflow occurs exists in the upper right part of the line connecting the point of A=7 and B=1 (hereafter denoted as (7, 1)) and (1, 7) and the lower left part of the line connecting (-8, -1) and (-1, -8). Therefore, it is attempted to invert the bits of only the numeric part while the sign of addend B is kept as is. For example, since 7 is 0111 2 in the binary value, it becomes 0000 2 , that is, 0 as a result of bit inversion except the MSD bit showing the sign and therefore (1, 7) is shifted to (1, 0). Similarly, -7 that is 1001 2 is inverted to 1110 2 , that is, -2 and therefore (-2, -7) is shifted to (-2, -2). Fig. 4 shows a diagram when the above operation is performed for all Bs and the range where the overflow occurs is image-displayed. In this diagram, the broken line shows the point of A=B. From this diagram, it is known that, the bits of the numeric part of B are inverted, the range of A>B is a combination of A and B which causes the overflow when A and B are positive, thatis, in the first quadrant shown in Fig. 4 and the range of A≦B is a combination of A and B which causes the overflow when A and B are negative, that is, in the third quadrant shown in Fig. 4. The overflow does not occur when one of A and B is a positive value and the other is a negative value. A combination of A and B which causes the overflow can be determined from the result of comparison of the value obtained by inverting the numeric part of B and the numeric part of A, using the inverter and the sign parts of two digit values. Figs. 5 and 6 show the similar operation to Figs. 3 and 4 as to A+B+1. In this case, as shown in Fig. 5, the upper right part of the line connecting (7, 0) and (0, 7) and the lower left part of the line connecting (-8, -2) and (-2, -8) are the range of the combination of A and B where the overflow is caused. The image of the range where the overflow is caused by an operation for inverting the bits of the numeric part of B is shown in Fig. 6. The broken line shows A=B. As known from Fig. 6, A≧B in the first quadrant is the range where the overflow is caused and the range of A<B in the third quadrant is the combination of A and B by which the overflow is caused. Thus, also in case of A+B+1, the overflow can be detected from the result of comparison of the inverted value of bits of the numeric part of B and the numeric part of A and the values of the sign parts of two digit values. As described above, the overflow can be detected by using the inverter, the comparator and the decoder which uses the sign parts of two digit values and the result of comparison without addition. Fig. 2 shows an embodiment of the overflow detection circuit which implements the system according to the present invention. The inverter 1 outputs the value V B ' of the inverted bits of the value V B of addend B. The comparator 2 inputs the numeric part V A of augend A and the output V B ' of the inverter and outputs the signal C indicating whether or not V A >V B '. The sign parts S A and S B of A and B and the output C of the comparator are inputted into the decoder, which determines a combination of A and B which permits x in Fig. 4 and outputs the overflow signal C. The decoder is a circuit which outputs 1 when S A and S B are 0 with V A >V B ' and S A and S B are 1 with V A ≦V B ', that is, when V A >V B ' is not permitted and 0 in other cases. In this case, the overflow of A+B can be detected. If the output of the comparator 2 is assumed as a signal indicating V A ≧V B ' or not, the overflow in case of A+B+1 can be detected. In this case, the decoder is a circuit which outputs 1 when S A and S B are 0 with V A >V B ' and S A and S B are 1 with V A <V B ', that is, when V A ≧V B ' is not permitted and 0 in other cases. Thus, the decoder can have the same circuit as in case of A+B except that the meaning of the output of the comparator is different. Fig. 7 shows another embodiment of the overflow detection circuit in which the overflow detection system according to the present invention is embodied. If the comparator 2 shown in Fig.2 is changed over to the comparator 10 capable of detecting V A >V B ' and V A ≧V B ' by the selector 11, the overflow detection circuit capable of detecting the overflow in two kinds of additions of A+B and A+B+1 is obtained. In subtraction, the bits of addend B are inverted and A-B is obtained by calculating A+B+1. In case of detecting an overflow in subtraction, the inverted bits of the value of B can be inputted in B shown in Fig. 2 and an overflow of A+B+1 can be detected. Fig. 8 shows an embodiment of the carry detection circuit for subtraction in which the overflow detection system according to the present invention is embodied. An overflow in subtraction of A-B can be detected by inverting the sign part, not the numeric part, of B by the inverter 20 and V A ≧V B ' by the comparator 2 to detect the overflow of A+B+1 even though the inverted bits of B are not inputted. As described above, the overflow detection system and its circuit according to the present invention allow to detect the overflow of the results of addition and subtraction by using an independent circuit, not from the result of addition or substraction or the carry signal obtained during addition or subtraction. This circuit is a simpler circuit than the adder and the subtracter and can earlier detect whether or not the result of addition or subtraction overflows than the output of the result by the adder and the subtracter.

Claims: An overflow detection method for detecting an overflow in an addition of two digital values, independently from said addition, each of said values having a sign part and a numeric part, said overflow detection method comprising: an inverting step (1; 20) for inverting each bit of a numeric part of an addend; a comparing step (2; 10) for comparing an output of said inverting step (1; 20) with a numeric part of the augend and for outputting only a result of said comparison; and a decoding step (3) for outputting an overflow signal in response to both a sign part of the addend and a sign part of the augend being positive and the numeric part of the augend being larger than the output of said inverting step (1; 20) and for outputting an overflow signal in response to both the sign part of the addend and the sign part of the augend being negative and the numeric part of the augend being equal to or smaller than the output of said inverter means (1; 20). An overflow detection method for detecting an overflow in a subtraction of two digital values, independently from said substraction, each of said values having a sign part and a numeric part, said overflow detection method comprising: an inverting step (1; 20) for inverting each bit of a sign part of a subtrahend; a comparing step (2; 10) for comparing a numeric part of the subtrahend with a numeric part of a minuend and for outputting only a result of the comparison; and a decoding step (3) for outputting an overflow signal in response to both an output of said inverting step (1; 20) and a sign part of the minuend being positive and the numeric part of the minuend being larger than a numeric part of said subtrahend and in response to both the output of said inverting step (1; 20) and the sign part of the minuend being negative and the numeric part of the minuend being smaller than the numeric part of said subtrahend. An overflow detection circuit for detecting an overflow in an addition of two digital values, independently from said addition, each of said values having a sign part and a numeric part, said overflow detection circuit comprising: inverter means (1; 20) for inverting each bit of a numeric part of an addend; comparator means (2; 10) for comparing an output of said inverter means (1; 20) with a numeric part of the augend and for outputting only a result of said comparison; and decoder means (3) for outputting an overflow signal in response to both a sign part of the addend and a sign part of the augend being positive and the numeric part of the augend being larger than the output of said inverter means (1; 20) and for outputting an overflow signal in response to both the sign part of the addend and the sign part of the augend being negative and the numeric part of the augend being equal to or smaller than the output of said inverter means (1; 20). An overflow detection circuit for detecting an overflow in a subtraction of two digital values, independently from said substraction, each of said values having a sign part and a numeric part, said overflow detection circuit comprising: inverter means (1; 20) for inverting each bit of a sign part of a subtrahend; comparator means (2; 10) for comparing a numeric part of the subtrahend with a numeric part of a minuend and for outputting only a result of the comparison in terms of large or small; and decoder means (3) for outputting an overflow signal in response to both an output of said inverter means (1; 20) and a sign part of the minuend being positive and the numeric part of the minuend being larger than a numeric part of said subtrahend and in response to both the output of said inverter means (1; 20) and the sign part of the minuend being negative and the numeric part of the minuend being smaller than the numeric part of said subtrahend.

Inventors: SUZUKI KAZUMASA, SUZUKI, KAZUMASA, SUZUKI, KAZUMASA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G06F7
IPC codes: G06F7