Semiconductor integrated circuit device having wells biased with different voltage levels

Abstract: A semiconductor integrated circuit device is fabricated on a lightly doped n-type silicon substrate (11), and p-type wells (13/ 14) are formed in the silicon substrate, wherein a heavily doped n-type channel stopper (21) is formed in a surface portion (20) between the p-type wells for restricting a parasitic channel between the p-type wells, and the surface portion is doped at a predetermined impurity concentration larger than a remaining portion of the silicon substrate and smaller than the channel stopper so that a p-n junction hardly takes place between the inverted surface portion and the channel stopper.

Description: FIELD OF THE INVENTION This invention relates to a semiconductor device and, more particularly, to electrical isolation between wells of the semiconductor device. DESCRIPTION OF THE RELATED ART Referring first to Fig. 1 of the drawings, a semiconductor integrated circuit device such as a solid-state image pick-up device is fabricated on a lightly doped n-type silicon substrate 1, and variable voltage level is applied from a variable voltage source 2 to the lightly doped n-type silicon substrate 1. P-type wells 3 and 4 are formed in surface portions of the lightly doped n-type silicon substrate 1, and a biasing unit 5 biases the p-type wells 3 and 4 to the ground voltage level and -10 volts, respectively. Though not shown in Fig. 1, photo-electric converting regions, a shift register for charge packets and an output circuit coupled with the shift register are formed in the p-type well 3, and an input protection circuit is formed in the p-type well 4 negatively biased. The p-type wells 3 and 4 are spaced apart from each other, and a thick field oxide film 6 is selectively grown on the surfaces of the p-type wells 3 and 4 for providing appropriate electrical isolation. The surface of the lightly doped p-type silicon substrate 1 is covered with thin oxide film 7, and a first inter-level oxide film 8 extends over the thick field oxide film 6 as well as the thin oxide film 7. A metal wiring strip 9 is formed on the first inter-level oxide film 8, and is brought into contact with the p-type well 4 through a contact hole 8a formed in the first inter-level oxide film 8. The metal wiring strip 9 is coupled with the biasing unit 5, and supplies negative voltage level of -10 volts to the p-type well 4. The first inter-level oxide film 8 extends over the photo-electric converting regions in the p-type well 3, and the metal wiring strip 9 is patterned in formation stage for a metallic shield plates ( not shown ) over the photo-electric converting regions. A heavily doped n-type channel stopper 10 is formed in surface portion between the p-type wells 3 and 4, and is spaced apart from each of the p-type wells 3 and 4 by 10 to 20 microns. The heavily doped n-type channel stopper 10 prevents the surface portion between the p-type wells 3 and 4 from a conductive channel, and is, accordingly, opposed to a parasitic MOS transistor. Namely, the metal wiring strip 9 negatively biased is faced to the surface portion between the p-type wells 3 and 4 through the oxide films 7 and 8, and holes tend to be induced in the surface portion beneath the thin oxide film 7. However, holes are hardly induced in the heavily doped n-type channel stopper 10, and any conductive channel can not bridge the surface portion between the p-type wells 3 and 4. However, a problem is encountered in the prior art semiconductor integrated circuit device in that breakdown is liable to take place at a junction between the p-type well 4 and the lightly doped n-type silicon substrate 1. In detail, depletion layer extends from the p-type well 3 applied with - 10 volts into the doped n-type silicon substrate 1 with relatively low impurity concentration of about 1 x 10 14 to 5 x 10 14 cm -3 , and the electric field tends to be concentrated at the edge of the heavily doped n-type channel stopper 10 identical in conductivity type with the lightly doped n-type silicon substrate 1. Moreover, the metal wiring strip 9 applied with - 10 volts extends over the junction, and the inter-level oxide film 8 is relatively thin rather than the width of the depletion layer. For this reason, the electric field at the edge of the heavily doped n-type channel stopper 10 is dominated by surface effects of the parasitic MOS structure thereover, and is, accordingly, promoted. This results in deterioration of the breakdown characteristics at the junction between the p-type well 3 and the lightly doped silicon substrate 1. WO-A-8 503 807 discloses a semiconductor device comprising an n-type substrate, first and second p-type wells formed spaced away from each other in a respective first and second surface portion of the substrate. Each p-type well contains a plurality of circuit components. The two p-type wells are biased at different voltage levels. A third surface portion of the substrate separating the p-type wells from each other is higher doped than the remaining portion of the substrate. IEEE Journal of Solid-State Circuits, vol. SC-16, pages 212-226 (1981) discribes a CMOS power device where the transistors are formed in different n-wells separated by p + -channel stoppers. The substrate has an impurity concentration of 3 x 10 14 cm -3 . SUMMARY OF THE INVENTION It is therefore an important object of the present invention provide s semiconductor integrated circuit device which is free from the problem inherent in the prior art semiconductor integrated circuit device. This object is solved by the features of the independent claim. Further advantages are reached by the features of the sub-claims. BRIEF DESCRIPTION OF THE DRAWINGS The feature and advantages of the semiconductor integrated circuit device according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a cross sectional view showing the structure of the prior art semiconductor integrated circuit device; Fig. 2 is a cross sectional view showing the structure of a semiconductor integrated circuit device according to the present invention: Fig. 3 is a plan view showing the arrangement in a well incorporated in the semiconductor integrated circuit device shown in Fig. 2; Fig. 4 is a graph showing improvement in breakdown voltage in terms of a surface portion around a channel stopper; and Fig. 5 is a cross sectional view showing the structure of another semiconductor integrated circuit device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring to Fig. 2 of the drawings, a solid-state image pick-up device is fabricated on a single lightly doped n-type silicon substrate 11, and variable voltage level is applied from a variable voltage source 12 to the lightly doped n-type silicon substrate 11. P-type wells 13 and 14 are formed in surface portions of the lightly doped n-type silicon substrate 11, and a biasing unit 15 biases the p-type wells 13 and 14 to the ground voltage level and negative voltage level of -10 volts, respectively. In this instance, the p-type wells 13 and 14 are doped at about 5 x 10 18 cm -3 . In this instance, photo-electric converting elements, a transfer gate, a vertical shift register for charge packets and an output circuit coupled with the vertical shift register are formed in the p-type well 13, and an input protection circuit is formed in the p-type well 14 negatively biased. Namely, Fig. 3 shows the layout in the p-type well 13 of the lightly doped n-type semiconductor substrate 11, and a channel stopper 13a provides an electrical isolation between adjacent photo electric converting elements 13b and a vertical shift register 13d. Only one of the photo electric converting elements is shown i Fig. 3. The channel stopper 13a is indicated by hatch lines for better understanding. Each of the photo-electric converting elements 13b is implemented by a p-n junction type photo diode. In a surface portion of the semiconductor substrate 11 is further formed an n-type impurity region 13e which forms the shift register 13d together with transfer gate electrodes 13f, 13g, 13h and 13i embedded in an insulating film 13j in a partially overlapping manner. The transfer gate electrodes 13f and 13g are supplied with a first phase clock pulse CL1, and a second phase clock pulse CL2 is fed to the transfer gate electrodes 13h and 13i. The vertical shift register 13d thus arranged transfers a data signal in the form of charge packet in synchronization with the two phase clock signal in the left direction of Fig. 3. Photo shield plates 13k and 13m are provided on the insulating film 13j, and are spaced from each other for exposing a part of photo electric converting elements 13b and 13c to an optical radiation carrying photo images. Parts of the optical radiation are converted into electric charges the amounts of which are dependent upon the respective intensities of the parts of the optical radiation. Although the photo electric converting element 13b is spaced apart form the vertical shift register 13d, a transfer gate electrode 13n allows the electric charges to flow into the vertical shift register 13d. The transfer gate electrode 13n is partially overlapped with the photo-electric converting element 13b, and the edge of the transfer gate electrode 13f extends below the transfer gate electrode 13n. Then, the electric charges accumulated in the photo-electric converting element 13b are read out to the shift register 13d in the presence of a transfer pulse Pt of a high voltage level fed to the transfer gate electrode 13n, and the vertical shift register 13d transfers the electric charges as one of the charge packets in synchronization with the two phase shift clock signal as described above. Turning back to Fig. 2, the p-type wells 13 and 14 are spaced apart from each other, and a thick field oxide film 16 is selectively grown on the surfaces of the p-type wells 13 and 14 for providing appropriate electrical isolation. The surface of the lightly doped p-type silicon substrate 11 is covered with thin oxide film 17, and an inter-level oxide film 18 extends over the thick field oxide film 16 as well as the thin oxide film 17. A metal wiring strip 19 is formed on the inter-level oxide film 18, and is brought into contact with the p-type well 14 through a contact hole 18a formed in the inter-level oxide film 18. The metal wiring strip 19 is coupled with the biasing unit 15, and supplies negative voltage level of -10 volts to the p-type well 14. The inter-level oxide film 18 extends over the photo-electric converting elements in the p-type well 13, and the metal wiring strip 19 is patterned in formation stage for the metallic shield plates 13k and 13m. The lightly doped n-type silicon substrate 11 is doped at about 2 x 10 14 cm -3 ; however, the impurity concentration of the lightly doped n-type silicon substrate 11 may range from 1 x 10 14 cm -3 to 5 x 10 14 cm -3 . A surface portion 20 between the p-type wells 13 and 14 is larger in impurity concentration than the above impurity range of the silicon substrate 11, and the impurity concentration of the surface portion 20 ranges from 1 x 10 17 to 2 x 10 17 cm -3 in this instance. In the surface portion 20 is formed a heavily doped n-type channel stopper 21 which is larger in impurity concentration than the surface portion 20, and the heavily doped n-type channel stopper 21 is doped at about 1 x 10 22 cm -3 in this instance. The heavily doped n-type channel stopper 21 prevents the p-type wells 13 and 14 from a parasitic MOS transistor as similar to that of the prior art. Even if extremely high voltage level ranging from 30 volts to 50 volts are applied to the lightly doped silicon substrate 11, any parasitic MOS structure never turns on, and the p-n junction between the p-type well 14 and the lightly doped silicon substrate 11 is free from any breakdown, because the surface portion 20 restricts depletion layer extending from the p-type well 14 into the lightly doped silicon substrate 11. Fig. 4 shows improvement in the breakdown voltage level at the p-n junction in terms of the impurity concentration of the surface portion 20. A small bubble A stands for the breakdown voltage of the prior art semiconductor integrated circuit device, and dots is indicative of the breakdown voltage in terms of the impurity concentration of the surface portion 20. If the impurity concentration is adjusted to 1 x 10 17 cm -3 , the breakdown voltage is about 1.8 times higher than that of the prior art. Second Embodiment Turning to Fig. 5 of the drawings, another semiconductor integrated circuit device is illustrated. The semiconductor integrated circuit device shown in Fig. 5 is similar to the solid-state image pick-up device except for an n-type surface portion 30, and, for this reason, regions and films thereof are labeled with the same references designating the corresponding regions and films of the first embodiment without detailed description for the sake of simplicity. The n-type surface portion 30 is larger in impurity concentration than a remaining portion of the semiconductor substrate 11 and is smaller in impurity concentration than the n-type channel stopper 21. However, the surface portion 30 is not contiguous to the p-type wells 13 and 14. By virtue of the spaced n-type surface portion 30, even if the impurity concentration of the n-type surface portion 30 is higher than the n-type surface portion 20, the similar advantage is achieved by the n-type surface portion 30. As will be understood from the foregoing description, the surface portion between the wells suppresses the depletion layer extending from the p-type well 14 into the silicon substrate 11, and the p-n junction between the p-type well 14 and the silicon substrate 11 is hardly broken down.

Claims: A semiconductor integrated circuit device fabricated on a semiconductor substrate (11) of a first conductivity type (n) for serving as a solid-state image pickup device, comprising: a first well (13) having a second conductivity type (p) opposite to said first conductivity type, and formed in a first surface portion of said semiconductor substrate, said first well being biased to a first voltage level; a plurality of first circuit components forming at least a photo-electric converting unit, a charge transfer circuit and a transfer gate provided between said photo-electric converting unit and said charge transfer circuit in said first well; a second well (14) of said second conductivity type formed in a second surface portion of said semiconductor substrate spaced from said first surface portion, and biased to a second voltage level different from said first voltage level; a plurality of second circuit components forming at least an input protection circuit in said second well; a third surface portion (20; 30) of said semiconductor substrate provided between said first and second wells and having said first conductivity type; a channel stopper (21) formed in said third surface portion, and doped with impurity atoms of said first conductivity type higher than a remaining portion of said third surface portion; an insulating film (17) covering at least said first, second and third surface portions; and a wiring strip (19) extending over said insulating film, and biased in such a manner as to induce carriers of said second conductivity type in said third surface portion, wherein said remaining portion of said third surface portion is doped with impurity atoms of said first conductivity type ranging between 1 x 10 17 cm -3 and 2 x 10 17 cm -3 , and the impurity concentration of a remaining portion of said semiconductor substrate ranges between 1 x 10 14 cm -3 and 5 x 10 14 cm -3 . A semiconductor integrated circuit device as set forth in claim 1, in which said third surface portion (20) is contiguous to said first and second surface portions (13/ 14). A semiconductor integrated circuit device as set forth in claim 1, in which the impurity concentration of said third surface portion (20) is adjusted to about 2 x10 14 cm -3 . A semiconductor integrated circuit device as set forth in claim 3, in which the impurity concentration of said channel stopper (21) is adjusted to about 1 x 10 22 cm -3 . A semiconductor integrated circuit device as set forth in claim 1, in which said wiring strip (19) is held in contact with said second well (14) through a contact hole (18a) formed in said insulating film (18). A semiconductor integrated circuit device as set forth in claim 1, in which said third surface portion (30) is spaced from both of said first and second surface portions (13/ 14).

Inventors: NAKASHIBA YASUTAKA, NAKASHIBA, YASUTAKA, NAKASHIBA, YASUTAKA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01L29
IPC codes: H01L27, H01L21, H01L29