Transmitter input stage with adaptive frequency deviation control

Abstract: Input stage of a transmitter, comprising a combining circuit having a plurality of inputs for receiving various input signals having various highest frequencies with significant amplitudes, the combining circuit combining the input signals into a modulation signal which is supplied to an output of the combining circuit which is intended to be connected to a frequency modulation stage of the transmitter in order to arrange for the generation and transmission of a transmission signal having a bandwidth which is essentially smaller than, or equal to, a maximum permitted bandwidth, and in which the combining circuit amplifies each of the input signals and/or a combined group of input signals, depending on their highest frequency, in such a way that the bandwidth of the transmission signal is increased towards the maximum permitted bandwidth.

Description: The invention relates to an input stage of a transmitter, comprising a combining circuit having a plurality of inputs for receiving various input signals having various highest frequencies with significant amplitudes, the combining circuit combining the input signals into a modulation signal which is supplied to an output of the combining circuit which is intended to be connected to a frequency modulation stage of the transmitter in order to arrange for the generation and transmission of a transmission signal having a bandwidth which is essentially smaller than, or equal to, a maximum permitted bandwidth. The bandwidth of the transmitter signal depends, in the case of frequency modulation, on the highest frequency of the modulation signal and on a frequency deviation which depends on the amplitude of the modulation signal. The bandwidth of the transmitter signal is approximately equal to twice the sum of the highest frequency of the modulation signal plus the frequency deviation. A transmitter input stage of the abovementioned type is known from transmitter CW 8032, manufactured by applicant from 1984. With this prior art input stage two input signals are combined. One input signal has a low frequency range to 400 Hz and the second input signal has a high frequency range from 800 Hz. Both input signals are amplified (or attenuated) individually by fixed factors and then summed and low pass frequency limited to 2600 Hz to eventually provide a modulation signal for a modulator. The waveform of the modulation signal and amplitudes of high frequencies components thereof and therefore the bandwidth will differ for the three possible cases in which both input signals are present or just one input signal is present. As explained below, eventually this requires limitation of the fixed gain factor of an output stage and therefore limits the receiving sensitivity and/or the reception range for the transmission signal. A transmitter input stage of the above mentioned type is known also from "IEEE Transactions On Vehicular Technology", VOL. VT 29, NO.2, May 1980, pages 260, 265, 266, Chapter V "Experimental Simulation Test System" (fig. 7 and 8) by Takeshi Hattori and Shigeaki Ogose. This article discloses a transmitter input stage as experimental test system. This test system comprises two adders, each receiving a rectangular input signal and a sinusoidal input signal, the sinusoidal input signal having a higher frequency and different phases for both adders, wherein each adder provides a different modulation signal by addition of the associated input signals. Each modulation signal is supplied to its associated transmitter. The amplitude of the sinusoidal input signal is a parameter of the experiment, while by variation of said amplitude there is no adaptation of gain factors of the system. Therefore this prior art system, if used to transmit in practice after all, operates with fixed amplification factors and therefore, as explained below, makes no optimum use of the available bandwidth and therefore limits the receiving sensitivity and/or the reception range for the transmission signal. In the case of the known transmitter input stage the combining circuit consists simply of a junction point or of an amplifier which has a plurality of inputs for the various input signals and a fixed gain factor. In this way the maximum occurring bandwidth of the transmitter signal is determined by the input signal or the group of input signals having the highest frequency with significant amplitude and/or the largest amplitude. In the case of individual input signals or groups of input signals whose highest frequencies and/or amplitudes are lower and/or smaller, the associated bandwidths of the transmitter signal will then be smaller. The smaller bandwidth and, consequently, a non-optimum distribution of the transmitter energy over the frequency spectrum, given the same gain of a main stage of the transmitter, limits the receiving sensitivity and/or the reception range for the transmission signal. The object of the invention is to overcome the drawback of the known transmitter input stage. This object with regard to the transmitter input stage of the type described in the preamble is achieved according to the invention in that the combining circuit amplifies each of the input signals and/or a combined group of input signals, depending on their presence and on their highest frequency, in such a way that the bandwidth of the transmission signal is increased towards the maximum permitted bandwidth. Suitable choice of the amplification of each received individual input signal and/or each group of received input signals thus enables the modulation signal to be adapted in such a way that it is always possible to achieve and to use the maximum permitted bandwidth of the transmitter signal. In this way the receiving sensitivity and/or the reception range for the transmitter signal is increased. Because the frequencies of the various input signals in the modulation signal do not change in this case, adaptive control of the frequency deviation of the transmitter signal is essentially achieved. For each individual input signal received, or for each group of input signals received, a separate amplifier having a gain factor can be used, or a common amplifier having an adjustable gain factor can be used, which gain factor is determined by which of the input signals or which of the group of input signals is being received. It should be noted that where the claims and the description refer to amplification, this term may be replaced within the scope of the invention by attenuation. These and other properties and advantages of the invention will become apparent upon reading the following explanation of embodiments of the transmitter input stage according to the invention with reference to the appended drawings, in which: Figure 1 shows a block diagram of a transmitter having an input stage according to the invention; Figure 2 shows another embodiment of an input stage according to the invention; and Figure 3 shows a block diagram of another embodiment of an input stage according to the invention for use in a paging system. Figure 1 shows a block diagram of a transmitter comprising, in series, an input stage 1, a modulation stage 2 and a main/transmitter stage 3. The input stage 1 has a plurality of amplifiers 4.1 to 4.M inclusive, each of which receives one or more input signals i 1 to i N inclusive and supplies an output signal to a summator 5. One output of the summator 5 supplies a modulation signal m and is connected to a modulation input of a frequency modulator 6 of the modulation stage 2. Another input of the modulator 6 receives a carrier wave signal from an oscillator 7. The output signal of the modulator 6 is amplified by an amplifier 8 of the main/transmitter stage 3 and after amplification is emitted by an antenna 9. In the modulation stage 2, as shown in Figure 1, the frequency modulator comprises, for example, a phase modulator and an integrator. The modulation stage may however, more commonly, also comprise a directly modulatable oscillator, for example a voltage controlled oscillator (VCO). Depending on the construction of the amplifiers 4.1 to 4.M inclusive and of the modulator 6, the summator 5 may comprise a summing amplifier or, in the simplest embodiment, a junction point. The bandwidth of the transmission signal emitted by the antenna 9 is approximately equal to twice the sum of the highest frequency of the modulation signal plus the frequency deviation (or frequency swing). The greater the frequency deviation is, the greater the amplitude of the modulation signal is. The amplifiers 4.1 to 4.M inclusive are set with gain factors (which, once set, are intended to remain unchanged) in such a way that the greater the amplitude of an output signal of an amplifier 4.i is, the lower a highest frequency with significant amplitude of the output signal of the amplifier 4.i is. In this way, the frequency deviation of the transmission signal will be greater for signals i having lower highest frequencies. Consequently, adaptive control of the frequency deviation is achieved for the purpose of increasing the bandwidth of the transmission signal within a maximum permitted bandwidth. Thus the receiving sensitivity and/or the reception range for the transmitter signal is increased. Figure 2 shows a block diagram of another embodiment of an input stage 1' according to the invention, which can be used instead of the input stage of Figure 1. The input stage 1' of Figure 2 comprises a summator 10 which receives, continuously or alternating in random sequence, a single input signal or a group of input signals combined from the input signals i 1 to i N inclusive, and which, depending on the circuits supplying these input signals, may comprise a summing amplifier or even a simple junction point. An output of the summator 10 supplies an input signal i x to an input of an amplifier 11 having an adjustable gain factor. Control inputs of the adjustable amplifier 11 receive, from a memory 12, a data signal DAT for the purpose of adjusting the gain factor of the amplifier 11. An output of the adjustable amplifier 11 supplies the modulation signal m. The memory 12 is addressed by an address ADR which is supplied by a coder 13 which receives selection signals S 1 to S N inclusive, each of which indicates whether the input signals, or groups thereof, i 1 to i N inclusive are supplied to the summator 10. If the signals S 1 to S N inclusive are not available in the transmitter, they may easily be generated by using a detector, such as the detector 14 of the input signal i 1 , which receives the input signal in question, or the group of input signals in question, and which detects whether the amplitude of the signal(s) is or is not above a certain value. In the memory 12, at locations indicated by the address ADR, values of gain factors are stored associated with each individual received input signal, or each group of received input signals, i 1 to i N inclusive. Consequently, apart from a possible amplifier of the summator 10, the input stage 1' of Figure 2 need only comprise a single amplifier, namely the adjustable amplifier 11. The gain factors stored in the memory 12 are easily changed (although this is not shown), for example by replacing the memory by another memory if it is a read-only memory, or by a user from a workstation if the memory 12 is connected to a control system (not shown) of the transmitter. Figure 3 shows a block diagram of an input stage 1" for a transmitter of a paging system. Three of the abovementioned input signals i 1 to i N inclusive received by the input stage 1" are a speech signal SP, a binary code signal CD and a binary frequency offset modulation signal FOM. The code signal CD may contain an identification number assigned to a portable receiver unit of the system. The signal FOM is used in systems having more than one transmitter and comprises a signal whose frequency is approximately twice the bit frequency of the code signal CD, which for different transmitters is differently shifted in phase and is superimposed on the code signal CD. The signal FOM therefore does not exist without a signal CD being supplied to the input stage 1". Two selection signals of the abovementioned selection signals S 1 to S N inclusive received by the input stage 1" are a speech enabling signal SE and an FOM detection signal FD. If the signal SE is high, this indicates that a speech signal SP is being received. If both SE and FD are low, this indicates that only a code signal CD is being received. If the signal FD is high, this indicates that a code signal CD is being received onto which the signal FOM must be superimposed. The signals SP, CD, FOM, SE and FD are available in systems which can be obtained from the applicant. The speech signal SP is first fed through a circuit 20 which amplifies higher frequencies more strongly than lower frequencies, or which attenuates lower frequencies more strongly than higher frequencies ("emphasise circuit"). The output signal of the circuit 20 is fed through a limiting circuit 21 in order to limit its amplitude. The output signal of the limiting circuit 21 is supplied to an input of the adjustable amplifier 11. The adjustable amplifier 11 at the same time receives, via a low-pass filter 22, the code signal CD. The signal FOM is supplied, via a low-pass filter 23 and an amplifier 24, to an input of a summator 25 which receives, at another input, the output signal of the adjustable amplifier 11. The output signal of the summator 25 is supplied to a low-pass filter 26 which, at one output, supplies the modulation signal m for the modulator 6 of Figure 1. If the selection signal SE is high, that is to say if a speech signal SP is being received, the address supplied to the memory 12 points to a memory location having a first value for the gain factor of an adjustable amplifier 11. If the selection signal SE is low and the selection signal FD is low, that is to say if only a code signal CD is being received, the address supplied to the memory 12 points to a location having a second value for the gain factor. If the selection signal SE is low and the signal FD is high, that is to say if a code signal CD is being received onto which an FOM signal must be superimposed, the address supplied to the memory 12 points to a location having a third value for the gain factor. The memory 12 therefore need contain only three locations having three values for the gain factor. The memory need therefore comprise only three registers, each having an enabling input for the purpose of receiving an enabling signal which, for example by means of a combinatorial circuit, is obtained from the signals SE and FD. For the same bit time of the code signal CD the second value will be greater than the third value. The low-pass filter 26 is preferably a 4th order Chebyshev filter having a cut-off frequency of 3 kHz. The low-pass filters 22 and 23 are preferably 10th order Bessel filters, which are almost optimally suited for the code signal CD and the FOM signal, respectively, and which have a smaller bandwidth than that of the filter 26. The cut-off frequency of the filter 22 is equal to the bit time of a code signal CD having the shortest bit time, and the cut-off frequency of the filter 23 is equal to twice the cut-off frequency of the filter 22. A filter of this type, in response to pulses having the bit time of the code signal CD or the FOM signal, produces as the output signal a signal having the shape of a raised cosine pulse. To the extent that more successive bits are high or low, the peak or the trough, respectively, becomes wider. By shaping pulses in this way, frequency components of a bit which are not of essential importance to information transfer are removed. Consequently, higher harmonics of the fundamental bit frequency disappear, which means that, if angle modulation is used, it is possible to operate with a greater frequency deviation than if the pulses were not shaped in the way described. In practice within a paging system different receivers may be used or messages may be sent with code signals CD having different bit frequencies. Bit frequencies of 480 bit/s - 4800 bit/s may be used, corresponding to a sine wave fundamental frequency of 240 Hz - 2400 Hz in the case of alternate reception of logical ones and zeros. It is then expedient for the memory 12 to have more than three storage locations and a correspondingly larger address range, which makes it possible to choose code signals CD having different bit frequencies from different gain factors of the amplifier 11, and thus to choose different frequency deviations of the transmitter signal to be emitted by the antenna 9, for the purpose of increasing the receiving sensitivity and/or the reception range for the transmitter signal. If the frequency of the FOM signal then changes, an adjustable amplifier can be used as the amplifier 24, which adjustable amplifier may be of the same type as the amplifier 11 and whose gain factor is controlled in the same way from a memory. It should be noted that the definition of "bandwidth" has not been established unambiguously, that it has changed with time, and that it will probably continue to change. According to the current PTT definition, the power of the emitted transmitter signal in a neighbouring channel must be attenuated by a particular number of dB's with regard to the power in the channel itself, with in addition an upper limit applying to the power in the neighbouring channel. It should again be noted that where the claims and the description refer to amplification, this may also be understood as attenuation within the scope of the invention. Furthermore, the transmitter input stage according to the invention is not restricted to the embodiments shown. As explained, for example, with reference to Figure 2 and, at the end of the explanation, with reference to Figure 3, the memory 12 may, after all, contain a large number of values for the gain factor of the adjustable amplifier 11 for each individual input signal or for each group of received input signals having various highest (permitted) frequencies.

Claims: Input stage of a transmitter, comprising a combining circuit (1,1',1") having a plurality of inputs for receiving various input signals (i 1 ,...,i N ) having various maximum frequencies with significant amplitudes, the combining circuit (1,1',1") combining the input signals into a modulation signal (m) which is supplied to an output of the combining circuit which is intended to be connected to a frequency modulation stage (2) of the transmitter in order to arrange for the generation and transmission of a transmission signal having a bandwidth which is essentially smaller than, or equal to, a maximum permitted bandwidth, characterised in that the combining circuit (1,1',1") amplifies each of the input signals (i 1 ,...i N ) and/or a combined group of input signals (i 2 ,i 3 ), depending on their presence and on their highest frequency, in such a way that the bandwidth of the transmission signal is increased towards the maximum permitted bandwidth. Input stage of a transmitter according to Claim 1, characterised in that the combining circuit (1') has an amplifier (11), with an adjustable gain factor, having inputs for receiving a single input signal (i x ) or a combined group of input signals of said input signals (i 1 ,...,i N ), the combining circuit (1') has a memory (12) in which for each single input signal or group of input signals, respectively, to be amplified by the amplifier (11) a gain factor assigned thereto is stored which is read out and supplied to the amplifier (11) for the purpose of adjusting the gain factor upon reception by the amplifier (11) of the associated single input signal (i x ) or the associated group of input signals, respectively. Input stage of a transmitter according to Claim 1, characterised in that the combining circuit (1") has an amplifier (11), with an adjustable gain factor, having inputs for receiving a single input signal or a combined group of input signals of said input signals, the combining circuit (1") has a memory (12) in which for each single input signal (Sp,CD) or group of input signals, respectively, to be amplified by the amplifier (11) a gain factor assigned thereto is stored which is read out and supplied to the amplifier (11) for the purpose of adjusting the gain factor upon reception by the amplifier (11) of the associated single input signal or the associated group of input signals, respectively, and in which the input signals of the combining circuit (1") may comprise a code signal (CD), a frequency offset modulation signal (FOM), and a speech signal (Sp). Input stage of a transmitter according to Claim 3, characterised in that different gain factors are assigned to code signals (CD) having different bit durations. Input stage of a transmitter according to Claim 3, characterised in that different gain factors are assigned to different groups each comprising a code signal and a frequency offset modulation signal (FOM) in which said groups having different bit durations. Input stage of a transmitter according to Claim 3, 4 or 5, characterised in that the frequency offset modulation signal (FOM) is amplified along a separate path with fixed gain, and in that the combining circuit (1") has a summator (25) which, at its inputs, receives an output signal of the amplifier (11) with adjustable gain factor and the amplified frequency offset modulation signal (FOM) and which, at one output, supplies the modulation signal. Input stage of a transmitter according to one of Claims 3 to 6 inclusive, in which the system is suitable for supplying an indication (SE) which indicates that an input signal is a speech signal (Sp) and an indication (FD) which indicates that an input signal is a frequency offset modulation signal (FOM), whereby each of the gain factors is stored in a register assigned to the factor and the combining circuit (1") has a logical combinatorial circuit which receives the two indications (SE,FD) and, depending on the indications received, enables one of the registers for the purpose of supplying to the amplifier (11) with an adjustable gain factor the gain factor stored in the enabled register. Input stage of a transmitter according to one of Claims 3 to 7 inclusive, characterised by one or more filters (22,23,26) between the inputs and the output of the combining circuit (1") for the purpose of limiting the frequencies of the input signals (Sp,CD,FOM) in the modulation signal (m) to essentially a highest frequency thereof. Input stage of a transmitter according to Claim 8, characterised in that the highest frequency of the modulation signal (m) is essentially the highest permitted frequency of the speech signal (Sp).

Inventors: EIKENBROEK JOHANNES WILHELMUS, VRIJKORTE MARCEL JOHANNES GERH, EIKENBROEK, JOHANNES WILHELMUS THEODORUS, VRIJKORTE, MARCEL JOHANNES GERHARDUS
Applicants: ERICSSON RADIO SYSTEMS BV, ERICSSON RADIO SYSTEMS B.V.
Application year: 1992
Main classification: H04B1
IPC codes: H04B1