Opto-electronic integrated circuit

Abstract: There is disclosed an optoelectronic integrated circuit comprising a plurality of channels each including an optical receiving device (PD₁; ... PD n ) for converting a received optical signal to an electric signal, and an amplifier (AMP₁; ... AMP n ) for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, electric power source nodes of at least two of the amplifiers of the respective channels being connected to a common electric power source node (11), and the common electric power source node (11) being connected through a resistor element (R) to an electric source power supply terminal (12) for supplying an electric source power to the channels.

Description: Background of the Invention This invention relates to an optoelectronic integrated circuit device for use in optical receiving units or others of receivers for the optical fiber communication. A conventional optoelectronic integrated circuit device (hereinafter called OEIC array) for use in optical receiving units or others for the optical fiber communication is disclosed in "High-speed eight-channel optoelectronic integrated receiver arrays comprising GaInAs PIN PDs and AlInAs/GaInAs HEMTs ", Optical Fiber Communication Conference, Tuesday, February 19, 1991, Lecture No. Tub2. Its schematic circuit diagram is shown in FIG. 1. This OEIC array 40 is provided by monolithically integrated eight channels of an optical receiving circuit. Each channel includes photodiodes PD (PD 1 ∼ PD 8 ), and AMPs provided by resistors, high electron mobility transistors or others for converting a received optical signal to an electric signal. In such conventional OEIC array 40, the electric power source nodes (contacts) 41 of the respective preamplifiers AMP are connected to one another and have the same potential. Because of such circuitry, it is a problem that crosstalks, i.e., leakage of a signal inputted to one channel to other channels, has a level as high as about -30 dB. A cause for such crosstalks is considered to be as follows. That is, condensers C 1 and C 2 are inserted in circuits inside and outside the OEIC array 40 for the reduction of an impedance of the AC current component, and all the electric power source circuits are grounded through the condensers C 1 , C 2 . On the other hand, an electric source power supply terminal 42 is usually supplied with a current from an electric power source 43 through a limited length of an electric power source wiring 44. This electric power source wiring 44 has an inductance L as a distributed constant. This inductance L and the condenser C 2 resonate at a specific frequency, and at this frequency an impedance between the electric source power supply terminal 42 and the ground becomes infinite. When a signal is inputted to one channel, an output voltage corresponding to the signal is generated at the output terminal 45, and a signal current is supplied to a load 46. This signal current is supplied by the electric power source 43. At the time of the supply of the signal current from the electric power source 43, a voltage equal to a product of the impedance between the electric source power supply terminal 42 and the ground, and a value of a current flowing there is generated in the electric source power supply terminal 42. Accordingly, at the above-described resonance frequency the impedance between the electric power source supply terminal 42 and the ground is infinite, and a very large voltage deflection corresponding to the inputted signal current occurs. Generally the preamplifier AMP has a deflected output voltage corresponding to a deflection of an electric power source voltage. Consequently at this resonance frequency, an electric signal inputted to one channel causes a large source voltage deflection and causes deflections of output voltages of all the other channels through the common electric power source wiring. This is a cause for the occurrence of crosstalks. A circuit corresponding to the OEIC array 40 in FIG. 1 is shown in FIG. 2. In this OEIC array, eight channels are monolithically integrated. The first channel of the eight channels includes a PIN photodiode PD 1 , resistors R 11 ∼ R 14 , and high electron mobility transistors (HEMTs) Q 11 ∼ Q 15 , The transistor Q 11 and the resistor R 12 constitute an amplification stage. The transistors Q 12 ∼ Q 15 , and the resistors R 13 , R 14 constitute a two-stage source follower. In FIG. 2 the third to the sixth channels have the same structure as the first channel, and they are not shown. Another example of the conventional OEIC arrays of this kind is disclosed in "Monolithic Integration of an InP/InGaAs Four-Channel Transimpedance Optical Receiver Array", Electronics Letters, vol. 26, pp. 1833 - 1834, October 1990. FIG. 3 schematically shows its circuit diagram. In this OEIC array, four channels constituting the optical receiver are monolithically integrated. A first one of the four channels comprises a PIN photodiode PD 1 , and an input resistor R f1 , junction transistors Q 11 ∼ Q 19 , and a level shift diode LSD 1 . The transistors Q 11 ∼ Q 13 constitute an amplifying stage for amplifying an electric signal photo-electrically converted by the photodiode PD 1 . The transistors Q 14 , Q 15 , and the diode LSD 1 constitute a level shifting stage for shifting a d.c. voltage of an amplified signal outputted by the amplifying stage. The transistors Q 16 ∼ Q 19 constitute a source follower stage for securing a fan out of an optical receiver output O/P 1 . The second, the third and the fourth channels have the same circuitry as the first channel, and the second and the third channels are not shown. In a conventional OEIC array of FIG. 3, the amplification stages and the level shift stages of the respective preamplifiers are supplied with an electric source power V DD1 through an electric power source wiring which is common to the respective channels. The source follower stages are supplied with an electric power source V DD2 through a different electric power source wiring which is common to the respective channels. In a conventional OEIC array of FIG. 2, all the stages of the respective preamplifiers are supplied with an electric source power V DD through an electric power source wiring which is common to the respective channels. In the conventional OEIC arrays of these structures, large modulated currents are caused by input signals in the level shift stages and the source follower stages as will be described below. Consequently in the electric power sources for these stages large source voltage deflections are caused by the modulated currents. Such source voltage deflections affect the common electric power sources of the respective channels connected to these stages. That is, a source voltage deflection caused by an input signal in one channel affects the power sources of the other channels, and causes voltage deflections in the output terminals of the other channels. Consequently crosstalks take place among the channels. As a result, the problem that the crosstalks deteriorate minimum sensitivities of the optical receiving circuits of the respective channels occurs. Major causes for such crosstalks are as follows. With respect to the OEIC array of FIG. 2 using HEMTs, explanation will be made as follows with reference to FIG. 4. Here it is assumed, for example, that an optical signal inputted to the first channel is converted to an electrical signal by a photodiode PD 1 , and a modulated current ΔI ml is caused by an input signal when the electric signal is amplified by the preamplifier consisting of an amplification stage and a follower stage. 90% of a modulated current ΔI ml is generated in the source follower state. This modulated current ΔI ml flows through the wiring of a resistor R p to thereby generate a voltage deflection Δv D . This wiring resistor R p is equivalently shown at the electric power source terminal V DD for supplying an electric source power commonly to the respective preamplifiers. The above-described modulated current ΔI ml flows through this wiring resistor and generates a voltage deflection Δv D (=ΔI ml xR p ) This voltage deflection Δv D is source voltage deflections of the preamplifiers of the other channels as it is. Generally when a source voltage is deflected, an output voltage of the preamplifier is deflected. Accordingly, when an optical signal is inputted to one channel, source voltages of the preamplifiers of the other channels are deflected, and the deflected source voltages deflect output voltage of the other channels with a result of occurrences of crosstalks. In the OEIC array of FIG. 3 using junction transistors, modulated currents are generated due to input signals. 90% of a modulated current is generated in the level shift stage or the source follower stage. The amplification stage and the level shift stage of each preamplifier are supplied with a source voltage V DD1 through the common electric power source wiring. Consequently, when a modulated current occurs in the level shift stage of one preamplifier, a voltage deflection Δv D is generated in the common electric power source wiring as described above. This voltage deflection Δv D deflects source voltages of the preamplifiers of the other channels through the common power source wiring, and deflects output voltages. That is, an optical signal inputted to one channel deflects output voltages of the other channels, and crosstalks take place. The reason for output voltages being deflected when source voltages of the preamplifiers are deflected is as follows. That is, as shown in FIG. 4, each preamplifier includes an amplification stage, a level shift stage, a source follower stage. Output voltages of the level shift stage and of the source follower stage are not substantially deflected. But an output voltage of the amplification stage is deflected in a range from 50% to 100% and is sensitive to the voltage deflections. Accordingly, when a voltage deflection due to a source voltage deflection takes place in an output of the amplifier of one channel, this voltage deflection directly affects the source follower stages and the level shift stages. That is, when a source voltage of a preamplifier is deflected, output voltages are adversely deflected. Because of crosstalks due to this cause, as described above, a minimum receiver sensitivity of the optical receiving circuit of each channel is deteriorated. The above-described modulated current ΔI ml is bypassed to the ground by a condenser monolithically integrated on the same semiconductor chip. But the bypass condenser integrated on the semiconductor chip can only have a limited capacity, and it is impossible to give the condenser a sufficiently large capacity. Accordingly all of a generated modulated current cannot be bypassed, and only a part of the current can be bypassed. Consequently a residual modulated current which has not been able to be removed is a cause for the occurrence of the above-described crosstalks. On the other hand, it makes a size of the semiconductor chip impractically extremely large to increase a capacity of the condenser so as to remove all of a modulated current. Summary of the Invention An object of this invention is to provide an optoelectronic integrated circuit device which can decrease such crosstalks among channels, or can eliminate such crosstalks among channels. This invention is an optoelectronic integrated circuit comprising a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an amplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, electric power source nodes of at least two of the amplifiers of the respective channels being connected to a common electric power source node, and the common electric power source node being connected through a resistor device to an electric source power supply terminal for supplying an electric source power to the channels. According to this invention, an inductance L and a condenser C in an external electric source circuit resonance at a specific frequency. Generally, when an inductance and a condenser resonate, in the presence of a resistance component, an impedance at the resonance is lowered. In view of this, the OEIC array according to this invention has a resistor device inserted between the electric power source terminal and the common electric power source contact to thereby lower an impedance at the resonance. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention will become apparent to those skilled in the art form this detailed description. Brief Description of the Drawings FIG. 1 is a general circuit diagram of the conventional optoelectronic integrated circuit array; FIG. 2 is a schematic circuit diagram of a first conventional OEIC array; FIG. 3 is a schematic circuit diagram of a second conventional OEIC array; FIG. 4 is a circuit diagram explaining a principle of the occurrence of crosstalks in the second conventional OEIC array; FIG. 5 is a schematic circuit diagram of the OEIC array according to this invention; FIG. 6 is a graph of frequency characteristics of crosstalks with a resistance value of the connected resistor device as a parameter; FIG. 7 is a circuit diagram of an example of the OEIC array ; FIG. 8 is a circuit diagram of a modification of the example of FIG. 7; Description of the Preferred Embodiments Embodiments of this invention will be explained with reference to the drawings attached hereto. FIG. 5 shows a schematic circuit diagram of the OEIC array according to a first embodiment of this invention. This OEIC array is not limited specifically in a number of channels but generally has 4 ∼ 12 channels depending on applications. FIG. 5 shows the first channel and the final n (4 ∼ 12)th channel and does not show the second to the (n-1)th channel. These channels are monolithically integrated on the same semiconductor substrate. Each channel includes photodiodes PD (PD 1 ∼ PD n ) for converting a received optical signal to an electric signal, and amplifiers AMP (AMP 1 ∼ AMP n ) including a resistor, high electron mobility transistors, and so on for amplifying the electric signal. The amplifiers AMP 1 ∼ AMP n and the photodiodes PD 1 ∼ PD n of the respective channels are connected to one another by common electric source power supply contacts where they have the same potential. The common electric power source contacts 11 and an electric source power supply terminal 12 are connected to each other through a resistor device R. The resistor device R is formed by depositing a metal thin film on the semiconductor substrate, but may be a resistor attached to the semiconductor substrate. This electric source power terminal 12 is a metal electrode pad provided on the semiconductor substrate and is connected to an external electric power source circuit by an Au (gold) wire. The terminal 12 is an input terminal for supplying an electric source power to the OEIC array 10. Condensers C 1 , C 2 are provided in an internal electric power source circuit and an external electric power source circuit for decreasing an impedance. The electric power source circuits are grounded through the condensers C 1 , C 2 . In each channel, an output signal of the photodiode PD is amplified by the amplifier AMP, and the amplified output is supplied to the output terminal 15 1 ∼ 15 n . Next, the function of the resistor device R will be explained. The electric source power supply terminal 12 is supplied with a current from an electric power source 14 through a limited length of an electric source power supply wiring 13, e.g., Au wire. This electric power source wiring 13 has an inductance L as a distributed constant. When an optical signal is inputted to at least one of the photodiodes PD, an electric source power is supplied to the channel which has received the input signal, at the electric power source supply terminal 12 connected to the electric power source 14. At this time, as described above, an inductance L of the electric power source wiring 13, and the condenser C2 resonate at a specific frequency. But in this embodiment, a resistor device R is inserted between the electric source power supply terminal 12 and the common electric power source contact 11. It is general that when an inductance and a condenser resonate, an impedance at the resonance is lowered in the presence of a resistor component. Then, a voltage deflection at the common electric power source contact 11 is proportional to an impedance between the respective electric power source contacts and the ground. Accordingly an impedance at the resonance can be suppressed low by inserting the resistor device R between the electric source power supply terminal 12 and the common electric power source contact 11. Consequently a voltage deflection of the common electric power source contact 11, i.e., a source voltage deflection at the amplifier AMP, is decreased, and the other channels are little affected by the voltage deflection. Consequently crosstalks are decreased. A capacity of the condenser C 1 is generally 100 pF and can be monolithically formed on the semiconductor substrate, but may be provided by a condenser chip externally provided on the semiconductor substrate. Because of this condenser C 1 , the common electric power source contact 11 has an a.c. earth potential. In many cases a capacity of the condenser C 2 is more than 10 times that of the condenser C 1 . Generally the condenser C 2 is externally provided on a semiconductor chip. Then, resistance values of the resistor device R will be discussed below. The insertion of the resistor device R between the electric source power supply terminal 12 and the common electric power source contact 11 lowers an impedance at the resonance. But an impedance between the common power source contact 11 and the ground is increased when a value of the resistor device R is increased above a set value. Resultantly crosstalks are increased. Accordingly there is an optimum range of the resistance value of the resistor device R. FIG. 6 shows frequency characteristics of crosstalks with resistance values of the resistor device R as a parameter. It is seen from FIG. 6 that when values of the resistor device R are 1 [Ω] ∼ 10 [Ω], crosstalks are decreased at a frequency below 100 [MHz], and when a resistance value is above 30 [Ω], crosstalks reach -30 [dB] near at 2 [MHz]. It is seen from these results that a resistance value of the resistor device R is optimumly 1 [Ω] ∼ 10 [Ω]. FIG. 7 shows one example of the circuit of the OEIC array according to this embodiment. In FIG. 7, the first channel and the final (n-1)-th channel are shown. The second to the (n-1)-th channels are not shown. These channels are monolithically integrated on the same semiconductor substrate, and all the channels have the same structure as the first channel. The first channel includes a photodiode PD 1 , resistor devices R 11 , R 12 , transistors Q 11 - Q 15 , and level shift diodes D 11 ∼ D 16 . The photodiode PD1 is provided by a PIN photodiode having a GaInAs layer as a photoabsorptive layer formed on an InP layer. The transistors Q 11 ∼ Q 15 are provided by HEMTs having an N-AlInAs layer and a GaInAs layer, junction transistors, hetero bipolar transistors of InP/GaInAs hetero junction or others. The resistor devices R, R 11 , R 12 are metal thin film resistors or others formed by sputtering or others. The photodiode PD 1 , and the resistor device R 11 constitute an optical detection stage, and the transistor Q 11 and the resistor device R 12 constitute an amplification stage for amplifying an input signal detected by the optical detection stage. The transistors Q 12 , Q 13 , and the level shift diodes D 11 ∼ D 13 constitute a level shift stage, and the level shift diodes D 14 ∼ D 18 , and the transistors Q 14 , Q 15 constitute a source follower stage. In the OEIC array 30 of such structure as well, the electric source power supply terminal 32, and the common electric power source contact 31 of the respective channels are connected to one another through the resistor device R. This resistor device R functions to decrease crosstalks as in the circuit of FIG. 5. As described above, the optoelectronic integrated circuit device according to this embodiment includes a common electric power source contact where at least two of the amplifiers of the respective channels are connected to each other to have the same potential. This common electric power source contact, and the electric source power supply terminal for supplying an electric source power to the optoelectronic integrated circuit device are connected to each other through the resistor device. When an external electric power source circuit connected to the electric source power supply terminal resonates at a specific frequency, the resistor device can decrease an impedance at the resonance. Consequently source voltage deflections supplied to the amplifiers of the other channels are decreased, whereby outputs of the other channels are less affected, and crosstalks can be decreased. FIG. 8 shows a modification of the circuit of FIG. 7 and includes the amplifiers provided by hetero junction bipolar transistors. A photodiode PD 1 and a resistor R 11 constitute an optical detection stage; and a transistor Q 11 and a resistor R 12 constitute a amplification stage; a transistor Q 12 and a resistor R 13 constitute a level shift stage; and a transistor Q 14 and a resistor R 14 constitute an emitter follower stage. This circuit can produce the same effect as that of FIG. 7. From the invention thus described, it will be obvious that the invention may be varied in many ways. Such variations are not to be regarded as a departure from the scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims: An optoelectronic integrated circuit comprising: a plurality of channels each including an optical receiving device (PD 1 ; ...PDn) for converting a received optical signal to an electric signal, and an amplifier (AMP 1 ; ...AMPn) for amplifying an output signal of the optical receiving device; the channels being integrated on the same semiconductor substrate; electric power source nodes of at least two of the amplifiers of the respective channels being connected to a common electric power source node (11); characterized in that the common electric power source node (11) is connected through a resistor element (R) to an electric source power supply terminal (12) for supplying an electric source power to the channels; and in that the resistor element (R) is formed on the semiconductor substrate. An optoelectronic integrated circuit according to claim 1, wherein the respective amplifiers (AMP) include high electron mobility transistors. An optoelectronic integrated circuit according to claim 1, wherein the respective amplifiers (AMP) include bipolar transistors. An optoelectronic integrated circuit according to claim 1, wherein the electric power source supply terminal (12) is formed on the semiconductor substrate; and the resistor element (R) is formed by depositing a metal thin film on the semiconductor substrate. An optoelectronic integrated circuit according to claim 1, wherein the resistor element (R) is 1 to 10 ohms. An optoelectronic integrated circuit according to claim 1, wherein the electronic source power supply terminal (12) is connected to a terminal of the electronic power source (14) by a wire (13). An optoelectronic integrated circuit according to claim 1, wherein the semiconductor substrate is an InP substrate; the optical receiving device is PIN photodiodes; and the amplifier includes hetero junction bipolar transistors or high electron mobility transistors.

Inventors: SASAKI GORO, SASAKI, GORO, Sasaki, Goro, c/o Yokohama Works of Sumitomo
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES, LIMITED
Application year: 1992
Main classification: H04B10
IPC codes: H04B10