Artificial random-number pattern generating circuit

Abstract: An artificial random-number pattern generating circuit has a plurality of flip-flops (11-14; 11-15) each having a set signal input terminal and a clock signal input terminal; a plurality of selectors (21-23,25,27; 21-24,26,28) each of which forwards its output to the corresponding flip-flop and receives a first operation mode signal (C1) and/or a second operation mode signal (C2); and an exclusive logical OR gate (30). The artificial random-number pattern generating circuit functions in three different ways, that is, as an artificial random-number pattern generator, a boundary scanning buffer or an input buffer, in accordance with the combinations of the first and second operation mode signals. The circuit can make not only a diagnosis of failure in the internal circuit of the LSI but also overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings for the LSI.

Description: The present invention relates to an artificial random-number pattern (or parallel pattern) generator which is used for testing LSI circuits and, more particularly, to an artificial random-number pattern generator which is also capable of operating not only as an input or output buffer but also as a boundary scanning buffer only by means of the switching of operation mode signals. Previously, in order to realize in an LSI chip a built-in self testing (BIST) which has a testing function for making diagnosis of failure in or malfunction of the LSI by utilizing the artificial random-number patterns, there has been added an artificial random-number pattern generator in the LSI chip. Such artificial random-number pattern generator is formed, for example, as shown in Figs. 1 and 2, by a plurality of flip-flops 11 - 14 each having a clock signal input terminal, and an exclusive OR gate 30 for receiving outputs from at least two flip-flops out of the plurality of flop-flops. Such artificial random-number pattern generator is disclosed in "Logic Design Principles", 1986, Prentice-Hall, Pages 458 and 469, U.S.A. The conventional random-number pattern generators as described above only have a function of generating artificial random-number patterns and can make a diagnosis of failure only in the internal circuit of the LSI. A disadvantage in such conventional generators is that it is not possible to conduct overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings of the LSI. US-A-4 860 236 discloses a multiple bit artificial random-number pattern generator comprising N flip-flops, where N is greater than or equal to two, each of the first to N-th flip-flops having an input terminal, a set signal input terminal and a clock signal input terminal; (N-1) selectors, each of which receives an output from the (1+i)th (1 ≤ i ≤ (N-1)) flip-flop and an i-th input data and selectively forwards its output to the input terminal of the i-th flip-flop; an artificial random-number producing means which receives outputs from at least two of said N flip-flops, conducts a predetermined logical operation on said outputs, and outputs an artificial random-number data of 1 bit; and an N-th selector which receives the output data from said artificial random-number producing means, and an external output data, and which selectively forwards its output to the input terminal of said N-th flip-flop; each of said plurality of (N-1) selectors being supplied with a first operation mode signal and said N-th selector is supplied with a second operation mode signal. It is therefore, an object of the invention to overcome the problems existing in the known random-number generators and to provide an improved artificial random-number pattern generator. It is another object of the invention to provide an artificial random-number pattern generator which is also capable of operating both as a boundary scanning buffer and an input or output buffer and which is realized by a simple repetition of the same basic circuits. The present invention provides a multiple bit artificial random-number pattern generator as defined in independent claims 1 and/or 3 to which reference should now be made. Preferred features of embodiments of the invention are listed in the dependent claims. According to some embodiments of the invention, in order to generate artificial random-number patterns of N-bits, the artificial random-number pattern generator is provided with flip-flops and selectors constituted by N+1 number of the basic circuits which are repetition of substantially the same circuit. To the particular one (1) added selector are inputted an output of the exclusive OR gate and an external output data so that, by causing one of them to be outputted therefrom according to the operation mode signal, it is possible to arrange the artificial random-number generator by simple repetition by the number N+1 of the same flip-flops and the same two-input selectors. In this way, according to these embodiments, it is possible to avoid such problems that three-input type selector having a complex circuit configuration is required for the particular one of the selectors and that the overall circuit is constituted by a number of circuit stages thereby resulting in low speed operation. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a known artificial random-number pattern generator; Fig. 2 is a block diagram of another known artificial random-number pattern generator; Fig. 3 is a block diagram of an artificial random-number pattern generator not falling within the present invention as claimed; Fig. 4 is a block diagram of an artificial random-number pattern generator embodying the invention; Fig. 5 is a detailed circuit diagram of a 3-input selector 27 used in the generator shown in Fig. 4; Fig. 6 is a block diagram of an artificial random-number pattern generator not falling within the scope of the invention as claimed. Fig. 7 is a detailed circuit diagram of a selector 26 used in the generator shown in Fig. 6; Fig. 8 is a detailed circuit diagram of a selector 23 used in the generator shown in Fig. 6; and Fig. 9 is a block diagram of an artificial random-number pattern generator embodying the invention. Now, some preferred embodiments of the invention will be explained with reference to the appended drawings. It should be noted that the same or like elements of the conventional generators shown in Figs. 1 and 2 are indicated with the same reference numerals or symbols in Figs. 3 to 9. Fig.3 is a circuit diagram showing an artificial random-number pattern generator capable of operating as a random-number generator, a boundary scanning buffer and an input buffer. The circuit of Fig.3 shows a 4-bit artificial random-number pattern generator which comprises: four flip-flops 11 - 14 each of which has an input terminal, a set signal input terminal, a clock signal input terminal and an output terminal for outputting a corresponding one output of output data 35 - 38; selectors k (k = 21, 22, 23) each of which receives the output data j+1 (j = 35, 36, 37) of the flip-flop f+1 (f = 11, 12, 13) and an input data i (i = 1, 2, 3) and which selectively forwards to the flip-flop f either one of such output data and such input data as it is or an exclusive logical OR thereof in accordance with a first operation mode signal C1 and a second operation mode signal C2; an exclusive OR gate 30 which receives and takes an exclusive logical OR of the output data 35, 36 of the flip-flops 11, 12 out of the four flip-flops 11 - 14 and outputs an artificial random-number output data 40; and a 3-input selector 25 which receives the output data 40 from the exclusive OR gate 30, an external output 10 of other adjacent flip-flop (not shown) and an input data 4 and which forwards selectively to the flip-flop 14 either one of the external output 10 and the input data 4 or an exclusive logical OR of the output data 40 and the input data 4 in accordance with the combinations of the first and second operation mode signals Cl and C2. The adjacent flip-flop issuing the external output 10 mentioned herein refers to such flip-flop which immediately precedes and is connected to this artificial random-number pattern generator where it is incorporated in a portion of a boundary scanning path. A table 1 shows the operation of the artificial random-number pattern generator shown in Fig. 3. C1 C2 OUTPUTS OF FLIP-FLOPS f (f=11, 12, 13) OUTPUT OF FLIP-FLOP 14 OPERATION MODE 0 0/1 INPUT DATA i (i=1,2,3) INPUT DATA 4 INPUT BUFFER 1 1 OUTPUT OF FLIP-FLOP f+1 EXTERNALLY INPUT DATA 10 BOUNDARY SCANNING BUFFER 1 0 EXCLUSIVE LOGICAL OR OF OUTPUT FROM F/F f+1 AND INPUT DATA i EXCLUSIVE LOGICAL OR OF OUTPUT DATA 40 FROM EX-OR 30 AND INPUT DATA 4 ARTIFICIAL RANDOM-NUMBER PATTERN GENERATOR As shown in the above table 1, the artificial random-number pattern generator shown in Fig. 3 operates in three different ways in accordance with the combinations of the first operation mode signal C1 and the second operation mode signal C2 which are commonly supplied to the selectors 21 - 23 and 25. When the signal C1 = "0" irrespective of the signal C2 = "0" or "1", the selectors 21 - 23 forward to the corresponding flip-flops 11 - 13 the corresponding input data 1 - 3, respectively. The selector 25 forwards to the flip-flop 14 the input data 4. Each of the flip-flops 11 - 14 outputs the input data 1 - 4 as it is with a delay of one clock signal. Thus, the artificial random-number pattern generator operates as an input or output buffer. When the first operation mode signal C1 = "1" and the second operation mode signal C2 = "1", each of the selectors 21 - 23 selectively forwards an output 36 - 38 of the corresponding following flip-flop 12 - 14 to each of the flip-flops 11 - 13. The selector 25 forwards to the flip-flop 14 the external output 10 supplied from the external flip-flop. Each of the flip-flops 11 - 14 outputs the supplied data as it is with a delay of one clock signal, so that the overall circuit of this invention operates as a boundary scanning buffer. When the first operation mode signal C1 = "1" but the second operation mode signal C2 = "0", each of the selectors 21 - 23 selectively forwards to each of the flip-flops 11 - 13 a corresponding exclusive logical OR of the output data 36, 37, 38 and the input data 1 - 3. The selector 25 forwards to the flip-flop 14 an exclusive logical OR of the output data 40 of the exclusive OR gate 30 and the input data 4. Each of the flip-flops 11 - 14 accordingly outputs the supplied data as it is with a delay of one clock signal, so that the overall circuit of this invention operates as an artificial random-number pattern generator. Fig. 4 is a circuit diagram showing an artificial random-number pattern generator of an embodiment according to the present invention. This embodiment also shows a 4-bit artificial random-number pattern generator which comprises: four flip-flops 11 - 14 each of which has an input terminal, a set signal input terminal, a clock signal input terminal and an output terminal for outputting a corresponding one output of output data 35 - 38; selectors k (k = 21, 22, 23) which receive the outputs j+1 (j = 35, 36, 37) of the flip-flops f+1 (f = 11, 12, 13) and input data i (i = 1, 2, 3) and which forward to the flip-flops f either such outputs or such input data selectively in accordance with a first operation mode signal C1; an exclusive OR gate 30 which receives the output data 35, 36 of the two flip-flops 11, 12 out of the four flip-flops 11 - 14; and a 3-input selector 27 which receives an output data 40 of the exclusive OR gate 30, an external output 10 of other adjacent flip-flop (not shown) and an input data 4 and which forwards to the flip-flop 14 one of such output 40, output 10 and input data 4 selectively in accordance with the combinations of the first and second operation mode signals C1 and C2. In this embodiment, it should be noted that the first operation mode signal C1 is commonly supplied to the respective selectors 21 - 23, 27 but the second operation mode signal C2 is supplied only to the selector 27. Here, Fig. 5 shows a detailed circuit diagram of the 3-input selector 27 shown in Fig. 4. The selector 27 includes two 3-input AND gates 271, 272, a 2-input AND gate 273, a 3-input OR gate 274 and two inverters 275, 276. The selector 27 selectively outputs one of the external output 10, the output 40 of the exclusive OR gate 30 and the input data 4 in accordance with the combinations of the first and second operation mode signals C1 and C2. Specifically, when the signal C1 = "1" and the signal C2 = "1", the selector 27 selectively outputs the output 40 of the exclusive OR gate 30, when C1 = "1" and C2 = "0", it outputs the output 10 of the other adjacent flip-flop and, when C1 = "0" irrespective of the value of C2, it outputs the input data 4. The table 2 shows the operation of the artificial random-number pattern generator shown in Fig. 4. C 1 C 2 OUTPUTS OF FLIP-FLOPS f (f=11, 12, 13) OUTPUT OF FLIP-FLOP 14 OPERATION MODE 0 0 INPUT DATA i (i=1,2,3) INPUT DATA 4 INPUT BUFFER 0 1 INPUT DATA i (i=1,2,3) INPUT DATA 4 INPUT BUFFER 1 0 OUTPUT OF FLIP-FLOP f+1 EXTERNALLY INPUT DATA 10 BOUNDARY SCANNING BUFFER 1 1 OUTPUT OF FLIP-FLOP f+1 OUTPUT DATA 40 FROM EX-OR 30 ARTIFICIAL RANDOM-NUMBER PATTERN GENERATOR As shown in the above table 2, the artificial random-number pattern generator shown in Fig. 4 operates in three different ways in accordance with the combinations of the first operation mode signal C1 and the second operation mode signal C2. When the signal C1 = "1" and the signal C2 = "1", each of the flip-flops 11 - 13 receives an output of the corresponding preceding flip-flop 12 - 14 and outputs it as it is with a delay of one clock signal, whereas the flip-flop 14 outputs a signal in the value of the output 40 of the exclusive OR gate 30, so that the overall circuit operates as an artificial random-number pattern generator. When the signal C1 = "1" but the signal C2 = "0", each of the flip-flops 11 - 13 receives an output of the corresponding preceding flip-flop 12 - 14 and outputs it as it is with a delay of one clock signal, whereas the flip-flop 14 outputs a signal in the value of the output 10 of the adjacent flip-flop, so that the overall circuit operates as a boundary scanning buffer which forms a part of the boundary scanning path. When the signal C1 = "0" irrespective of the signal C2 = "1" or "0", each of the flip-flops 11 - 14 outputs the input data 1 - 4 as it is, so that the overall circuit operates as an input buffer. Fig. 6 is a circuit diagram showing an artificial random-number pattern generator not falling within the scope of the present invention as claimed. This embodiment shows also a 4-bits artificial random-number pattern generator which comprises: five flip-flops 11 - 15 each of which has an input terminal, a set signal input terminal, a clock signal input terminal and an output terminal for outputting a corresponding one output of output data 35 - 39; selectors k (k = 21, 22, 23, 24) each of which receives the output data j+1 (j = 35, 36, 37, 38) of the flip-flop f+1 (f = 11, 12, 13, 14) and an input data i (i = 1, 2, 3, 4) and which selectively forwards to the flip-flop f either one of such output data and such input data as it is or an exclusive logical OR thereof in accordance with the combinations of a first operation mode signal C1 and a second operation mode signal C2; an exclusive OR gate 30 which receives and takes an exclusive logical OR of the output data 35, 36 of the flip-flops 11, 12 out of the five flip-flops 11 - 15 and outputs an artificial random-number output data 40; and a selector 26 which receives the output data 40 from the exclusive OR gate 30 and an external output 10 of other external flip-flop (not shown) and which forwards selectively to the flip-flop 15 either one of the output data 40 and the output 10 in accordance with second operation mode signal C2. In this embodiment, it should be noted as the differences from the circuits shown in Figs. 3 and 4 that all the selectors 21 - 24, 26 are of the 2-input type. Here, Fig. 7 shows a detailed circuit diagram of the selector 26 in Fig. 6. The selector 26 is formed by, for example, four 2-input AND gates 261 - 264, two 2-input OR gates 265, 266, a 2-input exclusive OR gate 267 and two inverters 268, 269. The selector 26 selects and outputs the output data 40 from the exclusive OR gate 30 when the second operation mode signal C2 = "0", whereas it selects and outputs the external output data 10 when the signal C2 = "1". Fig. 8 shows a detailed circuit diagram of the selector 23 in Fig. 6. The selector 23 has a NAND gate 231 which receives both the first and second operation mode signals C1, C2, in addition to the same circuit as the selector 26 shown in Fig. 7. The selector 23 selects and outputs the input data 3 when the first operation mode signal C1 = "0", irrespective of the value of the second operation mode signal C2. It selects and outputs the output data 38 of the preceding flip-flop 14 when both the first and second operation mode signals Cl, C2 = "1". It selects and outputs an exclusive logical OR of the output data 38 of the preceding flip-flop 14 and the input data 3 when the first operation mode signal C1 = "1" but the second operation mode signal C2 = "0". Each of the remaining selectors 21, 22 and 24 has the same circuit configuration as that of the selector 23 explained above. A table 3 shows the operation of the artificial random-number pattern generator shown in Fig. 6. C 1 C 2 OUTPUTS OF FLIP-FLOPS f (f=11,12,13,14) OUTPUT OF FLIP-FLOP 15 OPERATION MODE 0 0 INPUT DATA i (i=1,2,3,4) OUTPUT DATA 40 FROM EX-OR 30 INPUT BUFFER 0 1 INPUT DATA i (i=1,2,3,4) EXTERNALLY INPUT DATA 10 INPUT BUFFER 1 1 OUTPUT OF FLIP-FLOP f+1 EXTERNALLY INPUT DATA 10 BOUNDARY SCANNING BUFFER 1 0 EXCLUSIVE LOGICAL OR OF OUTPUT FROM F/F f+1 AND INPUT DATA i OUTPUT DATA 40 FROM EX-OR 30 ARTIFICIAL RANDOM-NUMBER PATTERN GENERATOR As shown in the above table 3, the artificial random-number pattern generator shown in Fig. 6 operates in three different ways in accordance with the combinations of the first operation mode signal C1 and the second operation mode signal C2. When the signal C1 = "0" irrespective of the signal C2 = "0" or "1", the selectors 21 - 24 forward to the corresponding flip-flops 11 - 14 the corresponding input data 1 - 4, respectively. Each of the flip-flops 11 - 14 thus outputs the input data 1 - 4 as it is. Thus, the artificial random-number pattern generator as a whole operates as an input or output buffer. When the first operation mode signal C1 = "1" and the second operation mode signal C2 = "1", each of the selectors 21 - 24 selectively forwards an output 36 - 39 of the corresponding preceding flip-flop 12 - 15 to each of the flip-flops 11 - 14. The selector 26 forwards to the flip-flop 15 the output 10 supplied from the external flip-flop. Each of the flip-flops 11 - 14 outputs the supplied data as it is with a delay of one clock signal, so that the overall circuit of this invention operates as a boundary scanning buffer. When the first operation mode signal C1 = "1" but the second operation mode signal C2 = "0", each of the selectors 21 - 24 selectively forwards to each of the flip-flops 11 - 14 a corresponding exclusive logical OR of the output data 36, 37, 38, 39 and the input data 1, 2, 3, 4. The selector 26 forwards to the flip-flop 15 the output data 40 of the exclusive OR gate 30. Each of the flip-flops 11 - 14 accordingly outputs the supplied data at it is with a delay of one clock signal, so that the overall circuit of this invention operates as the same artificial random-number pattern generator as the conventional one. Fig. 9 is a circuit diagram showing an artificial random-number pattern generator of another embodiment according to the present invention. The embodiment also shows a 4-bits artificial random-number pattern generator which comprises: five flip-flops 11 - 15 each of which has an input terminal, a set signal input terminal, a clock signal input terminal and an output terminal for outputting a corresponding one of output data 35 - 39; selectors k (k = 21, 22, 23, 24) which receive outputs j+1 (j = 35, 36, 37, 38) of the flip-flops f+1 (f = 11, 12, 13, 14) and input data i (i = 1, 2, 3, 4) and which forward to the flip-flops f either such outputs or such input data selectively in accordance with the first operation mode signal C1; an exclusive OR gate 30 which receives outputs 35, 36 of the two flip-flops 11, 12 out of the five flip-flops 11 - 15; and a selector 28 which receives an output 40 of the exclusive OR gate 30 and an external output 10 of other adjacent flip-flop (not shown) and which forwards to the flip-flop 15 either such output 40 or such output 10 selectively in accordance with the second operation mode signal C2. In this embodiment, it should be noted as the differences from previously described embodiments that all the selectors 21 - 24, 28 are of the 2-input type, that the first operation mode signal C1 is commonly supplied to the selectors 21 - 24 excluding the selector 28, and that the second operation mode signal C2 is supplied to the selector 28 only but is not supplied to the remaining selectors 21 - 24. The table 4 shows the operation of the artificial random-number pattern generator shown in Fig. 9. C 1 C 2 OUTPUTS OF FLIP-FLOPS f (f=11,12,13,14) OUTPUT OF FLIP-FLOP 15 OPERATION MODE 0 0 INPUT DATA i (i=1,2,3,4) EXTERNALLY INPUT DATA 10 INPUT BUFFER 0 1 INPUT DATA i (i=1,2,3,4) OUTPUT DATA 40 FROM EX-OR 30 INPUT BUFFER 1 0 OUTPUT OF FLIP-FLOP f+1 EXTERNALLY INPUT DATA 10 BOUNDARY SCANNING BUFFER 1 1 OUTPUT OF FLIP-FLOP f+1 OUTPUT DATA 40 FROM EX-OR 30 ARTIFICIAL RANDOM-NUMBER PATTERN GENERATOR As shown in the above table 4, the artificial random-number pattern generator of the embodiment shown in Fig. 9 operates in three different ways in accordance with the combinations of the first operation mode signal C1 and the second operation mode signal C2. When the first operation mode signal C1 = "0" irrespective of the value of the second operation mode signal C2, each of the flip-flops 11 - 14 outputs the corresponding input data 1 - 4 as it is with a delay of one clock signal and, when C1 = "1", each of the flip-flops 11 - 14 outputs the output data 36 - 39 of the corresponding immediately preceding flip-flop 12 - 15 with a delay of one clock signal. When the second operation mode signal C2 = "0", the flip-flop 15 outputs the external output 10 of the other adjacent flip-flop with a delay of one clock signal and, when the same signal C2 = "1", it outputs the output 40 of the exclusive OR gate 30 with a delay of one clock signal. Thus, when the first operation mode signal C1 = "0", the input data 1 - 4 are outputted as they are irrespective of the value of the output of the flip-flop 15, that is, irrespective of the value of the second operation mode signal C2, so that the pattern generator operates as an input buffer. When both the first and second operation mode signals C1 and C2 = "1", there is formed a shift register to which is applied a feedback through the exclusive OR gate 30, so that the pattern generator operates as an ordinary artificial random-number pattern generator. When the first signal C1 = "1" but the second signal C2 = "0", since there is formed a shift register to which is inputted the output 10 of the flip-flop adjacently located in the boundary scanning path, the pattern generator operates as a boundary scanning buffer. In particular, according to this embodiment of the invention, with the mere repetition of the same basic circuits formed by the flip-flops and the selectors of the same type respectively, it is made possible to achieve the same object and function as achieved by any preceding embodiments.

Claims: An N-bit artificial random-number pattern generator comprising : a plurality of N flip-flops (11-14), a first to N-th, N ≥ 2, each of which has an input terminal, a set signal input terminal and a clock signal input terminal; a plurality of (N-1) selectors (21-23), a first to (N-1)th, each of which receives an output of said (1+i)th, 1 ≤ i ≤ N-1, flip-flop and an i-th input data (1,2,3) and selectively forwards its output to said input terminal of said i-th flip-flops; an artificial random-number producing means (30) which receives outputs (35,36) from at least two (11,12) of said N flip-flops, conducts a predetermined logical operation on said outputs, and outputs an artificial random-number data (40) of 1 bit; and an N-th selector (25;27) which receives the output data (40) from said artificial random-number producing means, an external output data (10), and an N-th input data (4), and which selectively forwards its output to the input terminal of said N-th flip-flop (14); in which: each of said plurality of (N-1) selectors (21-23) is supplied with a first operation mode signal (C1), and selectively forwards to said input terminal of said i-th flip-flop either one of said output of said (1+i)th flip-flop and said i-th input data (1,2,3) in accordance with said first operation mode signal (C1); and said N-th selector (27) is supplied with said first operation mode signal (C1) and a second operation mode signal (C2) and selectively forwards to the input terminal of said N-th flip-flop (14) either one of said output data (40) from said artificial random-number producing means (30), said external output data (10) and said N-th input data (4) in accordance with said first and second operation mode signals (C1, C2), whereby said artificial random-number pattern generator operates as either one of an artificial random-number pattern generator, a boundary scanning buffer and an input buffer in accordance with the combinations of said first and second operation mode signals. An N-bit artificial random-number pattern generator according to claim 1, in which said artificial random-number producing means is an exclusive OR gate (30) which conducts an exclusive logical OR of at least two outputs (35,36) from said plurality of N flip-flops (11-14). An N-bit artificial random-number pattern generator comprising: a plurality of (N+1) flip-flops (11-15), a first to (N+1)th, N ≥ 2, each of which has an input terminal, a set signal input terminal and a clock signal input terminal; a plurality of N selectors (21-24), a first to N-th, each of which receives an output of said (1+i)th, 1≤ i ≤ N, flip-flops and an i-th input data (1,2,3,4) and selectively forwards its output to said input terminal of said i-th flip-flop; an artificial random-number producing means (30) which receives outputs (35,36) from at least two (11,12) of said (N+1) flip-flops (11-15), conducts a predetermined logical operation on said outputs, and outputs an artificial random-number data (40) of 1 bit; and an (N+1)th selector (26,28) which receives the output data (40) from said artificial random-number producing means (30) and an external output data (10), and which selectively forwards to the input terminal of said (N+1)th flip-flop either one of said output data (40) from said artificial random-number producing means (30) and said external output data (10); in which: each of said plurality of N selectors (21-24) is supplied with a first operation mode signal (C1), and selectively forwards to said input terminal of said i-th flip-flop either one of said output (36,37,38,39) of said (1+i)th flip-flop (12,13,14,15) and said i-th input data (1,2,3,4) in accordance with said first operation mode signal (C1); and said (N+1)th selector (28) is supplied with a second operation mode signal (C2) and selectively forwards to the input terminal of said (N+1)th flip-flop (15) either one of said output data (40) from said artificial random-number producing means (30) and said external output data (10) in accordance with said second operation mode signal (C2), whereby said artificial random-number pattern generator operates as either one of an artificial random-number pattern generator, a boundary scanning buffer and an input buffer in accordance with the combinations of said first and second operation mode signals. An N-bit artificial random-number pattern generator according to claim 3, in which said artificial random-number producing means is an exclusive OR gate (30) which conducts an exclusive logical OR of at least two outputs (35,36) from said plurality of (N+1) flip-flops (11-15).

Inventors: HAGIHARA YASUHIKO, OHKUBO CHIE, HAGIHARA, YASUHIKO, OHKUBO, CHIE, HAGIHARA, YASUHIKO, C/O NEC CORPORATION, Ohkubo, Chie, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G06F7
IPC codes: G06F11, G06F7, G01R31