METHOD FOR INCREASING THE SPEED OF DATA PROCESSING IN A COMPUTER SYSTEM

Abstract: Method for increasing data-processing speed in computer systems containing at least one microprocessor (1), a memory device (3), and a so-called cache (2, 4) connected to the processor, in which the cache (2, 4) is arranged to fetch data from the addresses in the memory device (3) requested by the processor (1) and then also fetches data from one or several addresses in the memory device (3) not requested by the processor (1). This invention is distinguished by: a circuit called the stream-detection circuit (5), connected to interact with a cache (2, 4) such that the stream-detection circuit (5) detects the addresses which the processor (1) requests in the cache (2, 4) and registers whether the addresses requested already existed in cache (2, 4) or not; a stream-detection circuit (5) arranged such that it is made to detect one or several sequential series of addresses requested by the processor (1) in the cache (2, 4); and, the stream-detection circuit, upon detection of such a series, being structured to command the cache (2, 4) to fetch data from the memory device (3) corresponding to the next address in the series and insert the address in the cache (2, 4).

Description: Method for increasing the speed of data processing in a computer system. This invention relates to a method for increasing the speed of processing data in a computer system. In latter years, progress in VLSI (Very Large Scale Integrated) circuits has widened the gap in access times between microprocessors and memory devices. The memory devices are relatively slow compared with the rapid microprocessors. In order to narrow this gap in speed, so-called caches have been introduced. These caches are installed between microprocessor and memory device. Caches are relatively small and quick memory devices in the form of chips. In one cache, for example, data that is often used by the microprocessor is stored. The cache fetches its data from a larger memory device, which is slow compared to the cache and the microprocessor. Sometimes, two or several caches are arranged hierarchically between a microprocessor and a large memory device. Caches can also be found in multiprocessor systems, e.g., where each microprocessor is connected to a cache and where information can be stored into and retrieved from a large memory device by each cache. An example of the use of this technique is a multiprocessor system in which different processors work to execute separate sections of a program and in which they therefore must fetch different data from the memory device. When a processor has completed one execution and is about to start a new one, it only needs a fraction of the data stored in the memory device. A processor in this situation first requests the cache for the first piece of data. If the cache does not have this piece of data, it fetches the data from the memory device and stores it in cache. As the processor requests data that is not stored in cache, the data contents of the cache increase. Since the processor is only executing a specific section of the program, the data sought by the processor will be found in cache more often as the execution advances, since the cache has already fetched these data upon previous requests from the processor. The access time for fetching a piece of data from the cache falls considerably short of the access time for the processor to fetch a piece of data straight from the large memory device. The speed of data between memory and processor is thus increased, decreasing the gap between memory-device speed and processor speed, which in turn increases data-processing speed. Attempts have been made to further increase memory speed with a cache that, when fetching data at an address in the memory device, would simultaneously fetch data at a nearby address in anticipati of the latter being requested by the processor, in which case tha piece of data would already be in cache. Another possibility woul be to fetch an entire block of data when a single piece is requested. This is advantageous if the data is stored in blocks allowing one to assume that, if the processor requests one address in a block, it will probably request several addresses in the same block. This means that large amounts of unusable data are fetched however, which is why required caches increase in terms of necessary memory capacity, thus decreasing memory speed. The present invention provides a method in which the cache fetches data before the microprocessor requests it, but in which the cache is nonetheless small and thus very quick because the probability i considerably greater that prefetched data will be requested by the processor than it is in other known systems that prefetch data. The present invention thus relates to a method to increase data-processing speed in computer systems containing at least one microprocessor and a memory device plus a so-called cache connecte to the processor, in which the cache is structured to fetch data from the addresses in the memory device that the processor request and thus also fetch data from one or several addresses in the memory device that the processor has not requested, and is characterized by : a circuit called the stream-detection circuit connected to interact with a cache such that the stream-detectio circuit monitors the addresses the processor requests in the cac and registers whether those addresses were already in cache or n the stream-detection circuit is structured such that it is made detect one or several sequential series of addresses requested b the processor in the cache; and, the stream-detection circuit, u detecting such a series, is structured to command the cache to fetch the data from the memory device corresponding to the next address in the series and insert the address in the cache. The invention submitted in the application can be generally used connection with different computer systems and in systems with b individual caches and hierarchically arranged caches. The invention is described in greater detail below, in part in reference to the attached drawings of an embodiment of the invention, of which - figure 1 shows a cache added to a computer and a memory device - figure 2 shows a so-called stream-object circuit; - figure 3 shows a so-called checker-object circuit; - figure 4 shows a stream-detection circuit; and, - figure 5 is an informal specification of a simplified stream-detection circuit in a software implementation. Figure 1 shows computer 1, to which cache2 may be attached. Between the computer and memory device 3, another cache4 exists, called cache2. According to the invention, a stream-detection circuit 5 exists, connected between the computer and cache2. It labeled Istream, which stands for Intelligent Stream. The stream-detection circuit contains so-called stream-object circuits and so-called checker-object circuits. The task of the checker-object circuit is to detect whether ther is a pattern or a sequential series of addresses in the traffic from the processor. It achieves this by guessing which addresse will be requested based on current addresses and a list of the mo commonly occurring intervals between requested addresses, e.g., a list such as (+1, -1, +17). Such a list stimulates the checker-object circuit to, given a request for address A, guess that addresses A+l, A-l, and A+17 will be requested in the future If a guess at a predetermined pattern turns out to be correct a predetermined number of times, a so-called stream object will be initiated and started. The checker-object circuit contains information about an address that is to be checked (Caddr), the previously mentioned Step, and counter (Ctr) . Caddr contains one address to be checked or guarded, but generates no prefetching. When the address in Caddr appears between the processor and Cache2, it is checked if Ctr counted to a numerical value equal to the threshold value for whether a stream of addresses shall be considered as having been identified or not. If Ctr does not exceed the threshold value, Caddr is increased by the interval in Step, and Ctr is increased a numerical value of one. The stream-object circuit contains information about the oldest prefetched address (Oaddr), the most recently fetched address (Naddr), and a function to calculate the next address. An exampl of such a function is a constant difference between the prefetche addresses (Step), e.g., +1 or -1. The stream-object circuit is arranged so that each request for Oaddr from the processor indicates that the prefetched addresses are usable, stimulating additional prefetching. If a request for Oaddr from the processo results in Oaddr not being in cache—a so-called cache miss—the prefetching has not been done quickly enough, causing more than o address to be prefetched. In those cases in which a request results in the address being in the cache, the prefetching was do in time, so only one additional address was prefetched. Thus, the stream-object circuit generates fetching of a stream of data or addresses according to a certain pattern, e.g., nearby addresses such as A+l and A-l. The pattern can be made simple or complicated depending upon the application. It is, however, the checker-object circuit that detects whether a stream of data or addresses exists or not. The way the circuit accomplishes this is that when the processor has requested an address in cache that was not in cache, it selects one or several addresses, i.e., the so-called checker objects, which the checker-object circuit shall guard or watch. This selection take place according to a specific pattern, such as adding a 1 to or subtracting a 1 from the most recently requested address,i.e. select and A-l. When the checker-object circuit has succeeded in guessi the correct address a certain number of times, a stream of data o addresses is considered to be detected. The number of times is counted and compared with a previously determined numerical value herein threshold value. In a presently preferred embodiment, the series can be made up of two or several addresses. In a special embodiment, the stream-detection circuit can be arranged such that, when the processor requests an address in cache, the stream-detection circuit fetches data from the memory device that corresponds to both the higher and lower order in an assumed series of addresses until the stream-detection circuit ha detected whether the series is increasing or decreasing. In yet another preferred embodiment, the above-named series which is detectable can be additive, arithmetic, or geometric, or otherwise logically constructed. In yet another preferred embodiment, new and interesting patterns can be detected upon execution, and thus be added to the list of functions that the checker-object circuit uses to guess addresses for upcoming requested addresses. One example of this is when a new constant interval between the requested addresses starts bein used. It must be noted here that the stream-detection circuit can be constructed, i.e., implemented in hardware, in a relatively simpl manner as in the example given below; however, the stream-detecti circuit can also be entirely composed of software, processed by a processor of a suitable known type. Thus, there is no specific hardware implementation here. In the latter case, there are clearly great opportunities for programming the stream-detection circuit, which thereby is a piece of software for detecting vario more or less complicated streams of data. One is thereby not limited to e.g., constant steps between addresses; rather, different series can be detected. For example, a series A+l, A+2 A+4, A+8 . . . A+n or a series A+l, A+2, A+3, A+ll, A+12, A+l3, A+21, A+22 . . . can be detected. The present invention is thus not at all limited to the detection of a special configuration of a series that must be detected to b able, by using the detected series, to predict which data in cach will be requested by the processor with a high degree of probability and thus prefetch these data. In order to prefetch addresses at the appropriate time, which mea that prefetched addresses shall have just arrived in cache when they are requested by the processor, the amount of prefetched dat is made to increase, in yet another preferred embodiment, until t microprocessor requests an address in the cache where the data ha just arrived from the memory device. A description follows of how a cache functions in this invention a simple example illustrating an algorithm for the stream-detecti circuit's function together with a cache. This is exemplified in figure 1, to the right of which a table is shown displaying: the traffic between the processor and Cache2, whether a so-called cac hit occurs, and the activity of prefetching addresses. The simple stream-detection circuit in the example below includes two checker-object-circuits and four stream-object circuits. The inter¬ val Step is set at +1 and -1. In the example, the so-called threshold value br the discovery of a stream is set at the numerical value of one, i.e. , a stream is created immediately when a checker objget agrees with an address in Cache2 requested by the processor. These activities are described line-by-line below according to t column headed "Studied traffic." In the column headed "Studied traffic" and the column headed "Prefetch Activity," "read" and "write" appear. This means that the prefetched data to the cache are prefetched in "read" or "write" mode. This has great significance when the invention is implemented with a multiprocessor. read A - The request from the processor for address A in the cac results in a miss in cache2, i.e., the address was not in cache2 Cache2 then fetches A from memory device 3. Address A is compar with all Oaddr, which currently contains no addresses, resulting no agreement. So-called checker objects C(A-l) and C(A+1) are t formed. write B - This results in a so-called cache hit, given that addr B already exists in cache2. Address B is compared with all Oadd which currently contains no addresses. read A+l - A miss in cache2 causes cache2 to fetch A+l. Address A+l is compared with the two checker objects C(A-l) and C(A+1), which results in an agreement with A+l. A stream is created wit Naddr=A+2 and Oaddr A+2 and Step=l. Stream-detection circuit 5 forces cache2 to prefetch A+2. read A+2 - a miss in cache2 causes cache2 to fetch A+2. However exactly this fetch was initiated in the previous step, read A+l, but A+2 has not yet had time to arrive in cache2. A+2 is compar with all Oaddr, which results in an agreement. This causes the stream-detection circuit to force cache2 to prefetch two address i.e., A+3 and A+4 to increase prefetching preparedness. Oaddr i changed to A+3 and Naddr is changed to A+4. write C - The request results in a miss in cache2. The stream-detection circuit forces cache2 to fetch C. Address C is compared with all Oaddr (A+3), which does not lead to any agreement. Address C is compared also with the two checker obje (A+l and A+2), but they do not agree either. Two new checker objects are then created, i.e., C(C+1) and C(C-l). read D - This results in a hit in cache2, given that address D already existed in cache2. Address D is compared with all Oaddr (A+3), which does not result in any agreement. read A+3 - This results in a hit in cache2. The address is compared with all Oaddr (A+3), which results in an agreement. Oaddr is then changed to A+4, Naddr to A+5. Furthermore, the stream-detection circuit forces cache2 to prefetch A+5 with a rea instruction (A+5). read A+l - This results in a hit in cache2. The A+l address is compared with all Oaddr (A+4), which does not result in any agreement. Nothing more happens. write C-l - This results in a miss in cache2. Address C-l is compared with all Oaddr (A+ ) , which does not result in any agreement. C-l is compared with all checker objects (A+l, A-l, C+l, and C-l), which results in a hit. A stream with Naddr=C-2, Oaddr=C-2, and Step=-1 is then initiated. Furthermore, address C is prefetched with a write instruction (C-2). read A+4 - This results in a hit in cache2. Address A+4 is compared with all Oaddr, i.e. (A+4) and (C-2), which results in a agreement on C-2. Oaddr is changed to A+5, Naddr is changed to A+6, and address A+6 is prefetched with the read instruction (A+6 write C-2 - This results in a hit in cache2. Address C-2 is compared with all Oaddr (A+5 and C-2), which results in an agreement. Oaddr is then changed to C-3 and Naddr to C-3. Addre C-3 is prefetched with the write instruction (C-3). The algorithm described above is specially suited for implementation in hardware. It is furthermore especially suited for prefetching addresses to a so-called second-level cache. Mos requests from a processor result in a cache hit. When a cache h occurs, only one comparison per stream object is necessary. When cache miss occurs, i.e., when that which was requested is not in cache, comparisons per stream object and per checker object are required. Figure 5 shows an informal specification of a simple stream-detection circuit implemented in software. Shown in figu 5 is the structure that the software would take in a simple case. One skilled in the art may nonetheless wish to use this structure with a more complicated stream-detection circuit implemented in software. Figure 5 is named "Informal Specification of a Simplified I-stream." The following description is an example of an implementation of stream-detection circuit in hardware according to the invention. The implementation is described in connection with three figures, figure 2 showing a stream-object circuit, figure 3 showing a checker-object circuit, and figure 4 showing a stream-detection circuit including checker-object and stream-object circuits. In figures 3 and 4, the "Control" symbol represents the logic th directs the flow of data and data paths in execution. Figure 4 shows the high-level structure for the data paths of a stream-detection circuit. The input signal, "Address," contains the address requested by a processor from the cache, while the input signal "miss" indicates whether that which was requested is in cache or not. The "checker-array" block is assumed to contain several checker objects. The purpose of the block is to discover new patterns in the requests from the processor, and is activated with the "enabl signal when a miss in cache has been detected in combination with request not being included in an already active stream. When new requests according to any pattern are detected, an "s.create" signal is sent to an LRU-BOX block. The LRU box has t task of selecting the stream object that has been inactive the longest. To determine this, each stream object sends a signal ea time it is active (hitO, hitl, hit2, and hit3). The LRU box initiates a selected stream object by sending the signal to the selected stream object (createO, createl, create2 and,create3). The initial address value (init.addr) of the selected stream obje activated with its "create" signal is calculated as the sum of th present request's address and the steps of the detected pattern. This address is also sent for prefetching to the "output buffer." The steps of the pattern are also sent to initialize a stream object (ini .step). The input signals "address" and "miss" are sent to all stream objects, which use them to check active streams. The stream obje sends new addresses to be prefetched to the "output buffer." In figure 2, a stream-object circuit is shown. The circuit contains three registers, i.e., step, naddr, and oaddr. The registers are initiated when an input signal labeled create is active, which causes the signals "init step" (initial step), "ini naddr" (initial new address), and "init oaddr" (initial old address) to be written to each register. When the input signal s-create is not active, the content of oaddr will be compared wit the "address" signal, which is the address that is momentarily being requested by the processor. If agreement is detected, an output signal "stream-hit" is produced, which indicates that a previously prefetched address is now being requested. The outpu signal "prefetch-addr" is created by adding naddr and step. If stream-hit is active, a data path, which calculates the prefetch address (prefetch-addr) by adding step and oaddr, will be activated. The Naddr register will also be updated with prefetch-addr. If the "miss" input signal is active, the data p that adds step and naddr in order to produce a new naddr will be activated twice, and an additional prefetching address (prefetch addr) will be created. In figure 3, a checker-object circuit, which contains an array of checker-object circuits, is shown. The input signals are the address that shall be checked (address), an activation signal (enable), and the above-named create signal. The output signals are step, a signal to create a stream (s.create), and the "hit" signal, which states that a prefetched address has been detected. Figure 3 shows an array of checker-object circuits, each of whic contain three registers, i.e., caddr (address to be checked), ct (which contains a numerical value to check whether the threshold value mentioned earlier has been reached or not), and step. Oneobject is selected by means of either the "forall.ctr" or the "fifo.repl" register. If the "enable" input signal is active, a check is carried out. The counter forall.ctr steps through the entire array each time address is to be checked. The content of the caddr register of selected object is compared with the incoming address. The cont of ctr in the selected object is compared with the constant numerical value c-threshold, i.e., the threshold value. The content of the step register of the selected object is output as "step" output signal. The combination of the selected caddr bei the same as the incoming address and the content of the selected ctr being greater than the threshold value in the c-threshold generates the s.create output signal. The combination of the selected caddr being the same as the incoming address and the not being greater than the threshold value in the c-threshold generates the output signal int.inc (internal increment). The int.inc signal activates a data path, which increases the numerical value in the selected ctr and enters the new numerica value into the ctr register. The int.inc signal also activates data path, which adds the selected step to the incoming address writes the result into the caddr register. The "hit" output signal reports that it has detected an agreeme regarding the addresses between a caddr (address being checked) an incoming address. When the input signal create is active, the contents of fifo.re will select the object. The caddr of the register thus selecte will be set at the incoming address plus the first value on a l of values labeled c-interval; its ctr will be set at 1 and its set at the first value in the c-interval list. Then the fifo.r register will be incremented and used to carry out the same wor for the second value on the c-interval list. This procedure wi be repeated until such time as all the values on the c-interval list have been used. In figure 4, a stream-detection circuit is shown that includes array of checker-object circuits and several stream-object circuits. The incoming address is sent to a stream-object circ and to the array of checker-object circuits. The incoming addr reports whether the address generated a miss in cache. The add for the data that shall be prefetched is reported as an output signal in an output register labeled "output buffer." If there is no hit—i.e., no agreement—in the stream-object circuit in combination with a miss in cache, the checker array be activated. If the activated checker array does not create a hit, new checker objects—i.e., addresses to be checked—will b created by the signal "s.create" sent to the checker array. A hit in the checker array—i.e., the address was expected—is shown with the "hit" output signal. The "s.create" output signal reports that there was a hit and that the threshold value to crea a stream was also exceeded. The s.create signal is sent to a so-called LRU (least recently used) box, which sends a create signal to the next stream-object circuit to be initiated. The LR box selects the stream-object circuit that was inactive longest. The selected stream-object circuit receives its init.step signal from the checker array, its init.addr and init.oaddr from the sum of step plus the address currently being requested by the processor. Simultaneously with the initiation of a stream-object circuit, th first piece of data is being prefetched. When a stream is detected, the address of the data that is to be prefetched is sen to the register output buffer. More than one address can be prefetched when a stream is detected. The Implementation depends on the numbercf addresses and transfer speed between processor and cache. The stream-detection circuit can be implemented as a separate functional unit connected to the bus that runs between the processor and cache, or alternatively as an tnteqratjed oartofthe cache. The difference depends on the destination of stream-detection circuit commands issued to prefetch addresses. In a separate unit, the stream-detection circuit issues commands the bus as any other arrangement connected to the bus. Examples suitable buses are Motorola Mbus and Futurebus+. Integrating the stream-detection circuit into a cache has the advantage of not generating extra traffic on the bus to the cache. An embodiment of the cache described above is well suited to several areas of application. One area is when the requests are strictly sequential, such as searching arrays or files. Another is loops requesting large arrays, in which each element comes up several times and then i never used again. Another area is scientific computing, such a matrix calculations. In, for example, matrix multiplication, t streams are generated. Reading from the first matrix and then writing to the result matrix generates streams of one step with numerical value of one, whereas reading the other operand resul in a step with a numerical value equal to the number of columns Another area is the creation of so-called stacks which grow slo The greatest use for stream-detection circuits should be in the startup stage, i.e., a so-called cold start, or immediately aft processors have been joined or reconnected to other processors. A number of applications have been described above. This inven can be modified, however, to differ from the embodi- m e n s without straying from the basic idea behind the invent i.e., to detect a stream of data or addresses and utilize the detected stream to predict coming requests for data or addresses and then prefetch them. This invention shall therefore not be considered as limited to t exemplary embodiments described above; rather, it may be modifie within the spirit and scope of the appended claims.

Claims: Claims 1. Method for increasing the data-processing speed in computer systems with at least one microprocessor (1), a memory device (3) and a so-called cache (2,4) connected to said processor, in which the cache (2,4) is arranged to fetch data from the addresses in t memory device (3) , which the processor (1) requests and thereby also fetches data from one or several addresses in the memory device (3) that the processor (1) does not request, characterized by a circuit, called the stream-detection circuit (5) connected t interact with a cache (2,4) such that the stream-detection circui (5) senses the addresses that the processor (1) requests in the cache (2,4) and registers whether the addresses requested existe in the cache(2, ) or not; a stream-detection circuit (5) being arranged such that it is forced to detect one or several sequent series of addresses that are requested by the processor (1) in t cache (2,4); and, the stream-detection circuit, upon detection o such a series, being arranged to command the cache (Z,4) to fetch da from the memory device (3) corresponding to the next address in the series and insert the address in the cache (Z , k) . 2. A method set forth in claim 1, characterized by said series being made up of two or more addresses. 3. Method set forth in claim 1 or 2, characterized by said serie being additive, arithmetic, or geometric or otherwise logically constructed. 4. Method set forth in claim 1, 2, or 3, characterized by the a m o u n t of said prefetched data increasing until such time a the microprocessor (1) requests an address in the cache (2,4) tha has just received data from the memory device (3) . 5. Method set forth in any of claims 1- 4, characterized by a stream-detection circuit (5) being arranged such that, when the processor (1) requests an address in the cache (2,4), the stream-detection circuit (5) commands the cache (2,4) to fetch d from the memory device (3) that corresponds to both the higher a lower order of an accepted series of addresses until such time a the stream-detection circuit (5) detects whether the series is increasing or decreasing.

Inventors: HAGERSTEN ERIK, HAGERSTEN, ERIK
Applicants: SWEDISH INST OF COMPUTER SCIEN, SWEDISH INSTITUTE OF COMPUTER SCIENCE
Application year: 1992
Main classification: G06F12
IPC codes: G06F12