Idle channel tone and periodic noise suppression for sigma delta modulators using high level dither

Abstract: A dither signal (18) is applied to a sigma-delta modulator (9) to remove low level tones and periodic noise in the desired passband of the modulator when no, or a very low, signal is present (idle). The dither signal is a high-level signal added to the input of a quantizer (16) in the modulator, the normalized in the AC component thereof being at least about 2 -2(N-1) 12 of the square of the quantizer step, where N is the order of the modulator. No significant reduction in the dynamic range of the modulator results. The technique may also be applied to multiple order sigma-delta modulators as well as to multiple stage sigma-delta modulators. Further, the dither may be added at any point in the modulator with suitable filtering of the dither. The transfer function of the filter (11₁ ... 11 N+1 ) is proportional to the noise shaping transfer function of the modulator between the point of addition of the dither and the input to the quantizer.

Description: Description of the Prior Art Sigma-delta (Σ - Δ) techniques (as part of the digital-to-analog or analog-to-digital conversion function) are finding wide acceptance in many applications, such as telephone codecs, compact disc (CD) players and the like. Σ - Δ converters are not without drawbacks, however. They may suffer from periodic noise and spurious tone generation (in-band and out-of-band) due to the feedback required to implement the converter. Although the periodic noise and spurious tones typically occur at very low levels (for example, at about 90 dB below full scale), they may be very objectionable to a human listener while having virtually no impact on a data acquisition system using the same converter. The noise and tones are typically noticeable to a human listener when no, or a very low, desired signal is present. The periodic noise and tones are generally referred to as idle channel noise. US-AA 968 987 discloses a delta-sigma modulation analog to digital converter for converting an analog input signal to a digital output signal. The converter includes a clock generator for generating a very high frequency clock signal, a dither signal generator responsive to the clock signal generator for generating a dither signal which is synchronized with the clock signal, an adder coupled to the dither signal generator for combining the analog input signal and the dither signal, a delta-sigma modulation type quantizer coupled to the adder for quantizing the analog input signal and the dither signal in response to the clock signal, and a data decimation circuit responsive to the clock signal and coupled to the delta-sigma modulation type quantizer for decimating prescribed quantization data from the quantized signal and producing a digital signal corresponding to the analog input signal. EP-A-308982 discloses an embodiment of a sigma-delta modulator according to the preamble of claim 1. According to this invention there is provided a sigma-delta modulator as claimed in claim 1. In one embodiment of the invention, a sigma-delta (Σ - Δ) modulator, with substantially suppressed idle channel periodic noise and tones, has at least one integrator and a quantizer. The quantizer has a predetermined step size, the input thereof coupled to the output of the integrator. The modulator is characterized by means for adding a dither signal to the output of the integrator, the dither signal having a predetermined normalized power in the AC component thereof (related to the variance of the probability density function of the dither signal). The normalized AC power of the dither signal is at least: approximately 2 -2(N-1) / 12 for N ≥ 2; or 1/12 for N = 1; of the square of the predetermined step size of the quantizer, where N is the number of integrators in the modulator. The advantages derived from the invention include the substantial suppression of idle channel periodic noise and spurious tones without significantly increasing the noise floor of the modulator or substantially impacting the dynamic range thereof. Brief Description of the Drawing The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description of the drawings, in which: FIG. 1 is a simplified block diagram of an encoder/decoder (codec) using sigma-delta modulation techniques; FIG. 2 is a simplified diagram of a sigma-delta modulator embodying the invention; FIG. 3 is a simplified diagram of an alternative form of a sigma-delta modulator embodying the invention; and, FIG. 4 is a simplified diagram of another approach to sigma-delta modulation utilizing multiple stages of sigma-delta modulators, similar to those shown in FIGs. 2 and 3. Detailed Description For purposes here, a sigma-delta (Σ - Δ) modulator is a modulator having at least one integrator between the input of the modulator and the quantizer therein. Such a modulator is also known either as delta-sigma (Δ - Σ) modulator, or an interpolative noise-shaping modulator or coder. The number of integrators in the modulator is generally referred to as the order of the modulator. Dither is added to the Σ - Δ modulators discussed herein to substantially suppress spurious tones and periodic noise in such modulators. For purposes here, the dither signal is a random noise signal having a predetermined probability density function, or PDF. Preferably, the average, or mean, of the PDF (or of the noise signal itself) is substantially zero, i.e., there is no significant DC energy in the noise signal. As is well known, the normalized power in the AC (the time-varying) component of the noise signal is substantially equal to the variance of the noise signal's PDF and is, therefore, dependent on the shape of the noise signal's PDF. As will be discussed below, the PDF of the noise signal may be rectangular, triangular, n th order, Gaussian, etc. The amount of power the noise (dither) signal has substantially determines the effectiveness of the spurious tones and periodic noise suppression. Because the discussion of the invention involves normalized power, the amount of power is related to the square of the quantizer step size, as will be discussed below. An alternative approach is to recognize that the standard deviation of the noise (dither) signal (equal to the square root of the variance, or normalized power, of the noise signal) and the quantizer step size are directly related. For convenience, however, the normalized power of the noise signal and squared step size of the quantizer is used herein to describe the invention. Of the Σ - Δ modulators presented here, the transfer function of a modulator is dependent on the number of integrators therein, among other factors. Quantizers, being non-linear devices, contribute noise to the modulator. The effect of the modulator on that noise is referred to here as the noise shaping transfer function of the modulator. As will be discussed in more detail below, the noise shaping transfer function is dependent upon where the noise is measured within the modulator. The invention may be understood generally from the Σ - Δ modulator 9 diagramed in FIG. 2. As will be discussed in more detail below and in accordance with one embodiment of the invention, the output of an integrator 13 N is coupled to the input of a quantizer 16 via a summer 17. The quantizer 16 has at least one predetermined quantization step size. Added to the signal from the output of the integrator 13 N is a noise signal from a dither generator 18. The noise signal (also referred to here as a dither signal) has an average value of about zero (substantially no DC energy). Preferably, the normalized power in the AC component of the noise signal is at least about 2 -2(N-1) / 12 times the square of the predetermined step size of the quantizer 16, where N is the number of integrators (order) of the Σ - Δ modulator 9 for two or more integrators. For one integrator in the Σ - Δ modulator 9 (N=1), the normalized power in the AC component of the noise signal is at least about 1/12 the square of the predetermined step size of the quantizer 16. In addition to the embodiment of the modulator 9 shown in FIG. 2, the dither signal may be injected at any point within the modulator 9, the dither being filtered by filters 11 1 - 11 N before being added to the modulator 9. The transfer function of the filters 11 1 - 11 N is substantially equal to the noise shaping transfer function of the modulator between the point of adding the dither and the input to the quantizer, 16. The foregoing is also applicable to the modulator 9 embodiment shown in FIG. 3. An alternative exemplary embodiment of a modulator is shown in FIG. 4, a multi-stage Σ - Δ modulator 9. As will be discussed in more detail below, the modulator 9 has a plurality of stages 31 1 - 31 M arranged from most significant stage, 31 1 , to least significant stage, 31 M . Each of the stages 31 1 - 31 M has at least one integrator 13 1 - 13 M and a quantizer 16 1 - 16 M . Dither from the dither generator 33 is added to the stages 31 1 - 31 M via filters 34 1 - 34 M . The transfer function of the filters 34 1 - 34 M is proportional to the noise shaping transfer function of the modulator between the dither addition point and the input to the quantizer. Preferably, the quantizer used for determining the transfer function of the modulator 9 is the quantizer of the least significant stage, 33 M . Referring to FIG. 1, an exemplary encoder 1 and decoder 2, usually referred to as a codec in combination, is shown for converting an analog signal to a sixteen bits per sample, linear, 128 kilobit per second (KB/s) digital data output stream and vice-versa. The encoder 1 converts the analog input signal to a digital data stream by first bandlimiting the analog signal to less than the Nyquist frequency by a well known anti-aliasing filter 3. The analog Σ - Δ modulator 4 then converts the bandlimited analog signal into a one-bit-per-sample, one megabit per second (MB/s), data stream, as will be discussed in more detail below. A decimation filter then converts the one-bit-per-sample digital stream into a sixteen bits per sample, 128 MB/s, data stream. The sixteen bits per sample stream is then filtered by high-pass filter 6 to remove substantially all DC energy. Conversely, the decoder 2 receives the sixteen bits per sample digital data stream, again removing any DC component therein with high-pass filter 7, and converting the 128 KB/s digital input into a sixteen bits per sample, 16 MB/s data stream in interpolation filter 8. A digital Σ, - Δ modulator 9 converts the 16 MB/s stream into a one-bit-per-sample, one MB/s stream for the analog Σ, - Δ demodulator 10 to convert into an analog signal. Operation of the decimation filter 5 and interpolation filter 8 are well known in the art and will not be discussed here. In the exemplary embodiment of the invention, the analog Σ - Δ modulator 4 and the digital Σ - Δ modulator 9 are substantially similar in operation (ignoring, for the sake of convenience, obvious differences between analog and digital circuitry). For simplicity, however, only the digital Σ - Δ modulator will be discussed in detail. It is understood that a duality exists between the digital domain and analog domain; the invention described herein also applies to the analog Σ - Δ modulator 4. In FIG. 2, the preferred embodiment of an exemplary digital Σ - Δ modulator 9 is shown. The modulator 9 has at least one integrator 13 1 - 13 N , subtracter 14 1 - 14 N , and gain stage 15 1 - 15 N . Each gain stage 15 1 - 15 N has a corresponding gain A 1 - A N . Output from the final integrator 13 N is coupled to a quantizer 16 via a summer 17. The output of the quantizer 16 is the output of the modulator 9 as well as the feedback to the integrators 13 1 - 13 N . The quantizer 16 has predetermined step sizes or levels, determined by the thresholds in the quantizer 16. In the preferred embodiment, the number of levels is two (one threshold, preferably at zero for bipolar input signals), and the step size is between the maximum signal amplitude (positive or negative) and zero. Added to the output from the final integrator 13 N is a noise signal from dither generator 18, which will be described in more detail below. For purposes here, generator 18 preferably creates a dither (noise) signal having an average amplitude of approximately zero while the normalized power in the AC component of the dither signal is between approximately 2 -2(N-1) / 12 times and one times the square of the step size of the quantizer 16, where N is the order (the number of integrators) of the modulator. By setting the normalized power in the AC component of the dither signal to approximately withing the range given above, the dither signal substantially suppresses the idle channel periodic noise and spurious tones, discussed above, without substantially increasing the idle noise (noise floor) level of the decoder 2 (FIG. 1). For example, if the order of the modulator 9 is two (there are two integrators, 13 1 , 13 2 , where N=2), then the normalized power in the AC component of the dither signal should be between 1/48 times and one times the square of the step size of the quantizer 16. An exception to the above is with first order (single integrator) modulators 9. In this case, the preferable normalized power in the AC component of the dither signal is between 1/12 times and one times the the square of the step size of the quantizer 16. In addition to adding the dither signal to the output of the last integrator 13 N , the dither may be added anywhere within the modulator 9 with suitable filtering. Filters 11 1 - 11 N filter the dither signal from the dither generator 18 prior to adding the dither to the inputs of the corresponding integrators 13 1 - 13 N . The transfer function of the filters 11 1 - 11 N+1 is proportional to the noise shaping transfer function of the modulator 9 between the point where the dither is injected and the input to the quantizer 16. For an N th order modulator 9 shown in FIG. 2, the noise shaping transfer function of the modulator 9 is generally proportional to (1 - Z -1 ) N , referred to the input X of the modulator 9. Hence, injecting a dither signal to the input to the first integrator, 13 1 , has the dither signal filtered by filter 11 1 having a transfer function proportional to an N th order differentiator. More pragmatically, the filters 11 1 - 11 n+1 has a differentiator of the order equal to the number of integrators 13 1 - 13 N between the point of dither signal injection (where the corresponding filter 11 1 - 11 N+1 couples to the modulator 9) and the input to the quantizer 16. Hence, filter 11 n+1 has no differentiation (zero order differentiation) since the noise shaping transfer function of the modulator 9 at the input to the quantizer 16 is not significantly shaped by the integrators 13 1 - 13 N . Similarly, injecting dither into the input of the integrator 13 N infers that the transfer function of the filter 11 N is a first derivative, 1 - z -1 , since the noise shaping transfer function is significantly shaped by the integrator 13 N . It is noted that while N integrators 13 1 - 13 N are shown, as a practical matter, one to five integrators may be all that can be used depending on the application of the codec (1,2 FIG. 1). As noted above, the Σ - Δ modulator may be in analog form, such as modulator 4 in FIG. 1. In such a case, the modulator 9 shown in FIG. 2 may require a digital-to-analog converter (not shown) to convert the digital output of the quantizer 16 back into analog form for presentation to the integrators 13 1 - 13 N . In addition, another digital-to-analog converter (not shown) may be needed to convert the dither signal (if in digital form) from the generator 28 into analog form. It is understood that as few as two or three bits of digital dither signal may be used in this approach. An alternative embodiment of the modulator 9 is shown in FIG. 3. The Σ - Δ structure shown here allows for the optimization of the zeros in the transfer characteristics of the modulator 9. As with the modulator 9 in FIG. 2, there are series coupled integrators 20 1 - 20 N . Unlike the modulator 9 in FIG. 2, the modulator 9 of FIG. 3 has the outputs of one (or more) integrators 20 1 - 20 N coupled to the input of the quantizer 21 via corresponding weighted gain stages 22 and adder 23. In addition, outputs from the integrators 20 1 - 20 N are also coupled to the input of the first integrator 20 1 via corresponding weighted gain stages 24 and adder 25 to form a feedback path. Feedback from the quantizer 21 only goes to the input of the modulator 9 through subtracter 26. Adder 27 adds to the output of adder 23 the dither signal from dither generator 28 for coupling to the input of the quantizer 21. Adders 23 and 27 may be combined into a common adder (not shown). The dither generator 28 is similar to the dither generator 18 in FIG. 2 and the noise signal therefrom has the same normalized AC power limitations as described above. Further, the dither may be added to the input via adders 25 or 26, or at any intermediate point within the modulator 9, with suitable filtering, as described above. Another approach to forming a Σ - Δ modulator 9 is a multiple stage Σ - Δ modulator, commonly referred to as an MSM or MASH, shown in FIG. 4. In general, this technique relies on a subsequent Σ - Δ modulator stage 31 i+1 (1 ≦ i ≦M - 1 to convert quantization errors of the previous Σ - Δ modulator stage 31 i to increase the number of bits of resolution of the modulator 9. Similar to the modulator 9 of FIG. 2, each Σ - Δ modulator stage 31 i (not shown, 1 ≦ i ≦M - 1 has a subtracter 19 i (not shown) with the output of integrator 13 i (not shown) as one input and the output of the quantizer 16 i (not shown) as the other input. The output of subtracter 19 i (not shown) is then the quantization error (ERROR) for the stage 13 i (not shown) plus the dither signal from generator 33. Similarly, subtracter 29 in FIG. 3 generates the quantization error for that modulator. Returning to FIG. 4, the quantization error (ERROR) of the first (highest order) Σ - Δ modulator 31 1 is then converted by a subsequent modulator 31 2 (not shown), up to the last (least significant) Σ - Δ modulator 31 M . The digital output of the modulators 31 1 - 31 M are combined and equalized in a combining network 32. A dither generator 33 generates the dither signals for each of the modulators 31 1 - 31 M for the purpose discussed above. It is preferable that each of the dither signals to the Σ - Δ modulators 31 1 - 31 M be uncorrelated. It is understood that not all of the modulators need to have a dither signal coupled thereto; it may be sufficient to have the dither signal coupled to only the first one or two of the modulators 31 1 - 31 M . Also as discussed above, the addition of dither should be filtered prior to adding it to the modulator 9. The transfer function of the filters 34 1 - 34 M+1 is preferably proportional to the noise shaping transfer function of the modulator 9 between the point dither addition and the input of the quantizer 16 M in the least significant stage 31 M . For example, if dither was to be added to the input of the first integrator, 13 1 , of the first stage, 31 1 , then the dither from generator 33 is filtered by a filter 34 M having a transfer function including an M th order derivative, (1 - z -1 ) M . As discussed in connection with FIG. 2, the filter 34 M+1 has a transfer function of "1", i.e., no significant shaping (except for amplitude scaling, if any) of the dither signal occurs. As discussed above, a more pragmatic approach to determine the order of the differentiator in each transfer function of the filters 34 1 - 34 M+1 is to count the number of integrators 13 1 - 13 M between the point of dither signal injection (where the corresponding filter 34 1 - 34 M+1 couples into the modulator 9) and the input of the quantizer 16 M in the least significant stage 31 M . The number of integrators is then the order of the differentiator within the corresponding filter 34 1 - 34 M+1 . The dither generators 18 (FIG. 2), 28 (FIG. 2), and 33 (FIG. 4) are preferably formed using one or more maximal length, linear feedback, shift registers (not shown), commonly called a MLSR, to generate a pseudorandom binary sequence as the dither signal. In the preferred embodiment, there are 25 taps on the shift register, with feedback from taps 1 and 23. Sixteen taps (bits) on the shift register are used as the dither signal (sign extended) added to the outputs of the stages 12 N (FIG. 2) or integrators 20 1 - 20 N (FIG. 3). Other methods for generating the dither signal and other shift register lengths may be used. It is preferable, however, to have the period of the pseudorandom sequence much longer than the period of the lowest frequency signal to be processed by the modulator. In the preferred embodiment, the data paths in the modulator 9 (FIGs. 2,3) are at least 21 bits wide. It is understood that a single MLSR generates a noise (dither) signal with a nearly uniform PDF. It may be preferable, however, to use multiple MLSRs with uncorrelated noise signals and combine (e.g., add) the noise signals together to achieve a non-uniform PDF, such as a triangular (first order), or higher order, PDF. Further, the PDF of the noise signal may be weighted or skewed to achieve a desired level of spurious tone suppression. While the average (DC) value of the noise (dither) signal is preferably near zero, having a DC value may be advantageous in certain circumstances where, for example, the modulator 9 reacts to DC signals with a certain output (digital) pattern which may be easier to suppress with dither. In the foregoing embodiments, the invention is discussed as a discrete time implementation using digital or switched-capacitor circuitry, for example. However, the invention may be utilized in a continuous time form.

Claims: A sigma-delta modulator (9) having: at least one integrator (13 1 - 13 N , 20 1 - 20 N ) having an input and an output; a quantizer (16,21) having a predetermined step size, the input thereof coupling to the output of the integrator; and means (7,27) for adding a noise dither signal to the modulator, the dither signal having a predetermined normalized power in the AC component thereof; characterised in that the minimum normalized AC power of the dither signal is approximately: 2 -2 N-1 12 for N ≥ 2; or 1/12 for N = 1; of the square of the predetermined step size of the quantizer; where N is the number of integrators in the modulator. A multi-stage sigma-delta modulator (9) having a plurality of stages (31 1 - 31 M ), each stage having a modulator as claimed in claim 1. A modulator as claimed in claim 1 or 2 wherein the means for adding (17,27) is disposed between the output of the integrator and the input of the quantizer. A modulator as claimed in claim 1, 2 or 3 wherein the average value of the dither signal is approximately zero. A modulator as claimed in claim 1, 2, 3 or 4 wherein the maximum normalized AC power of the dither signal is equal to or less than one times the square of the predetermined step size of the quantizer. A modulator as claimed in claim 1, 2, 3, 4 or 5, wherein the dither signal is generated by a pseudo-random sequencer.

Inventors: NORSWORTHY STEVEN ROBERT, NORSWORTHY, STEVEN ROBERT
Applicants: AT & T CORP, AT&T CORP.
Application year: 1992
Main classification: H03M3
IPC codes: H03M3, H03M7, H03M1, H04B14