Information processing apparatus

Abstract: An information processing apparatus for accumulating image information consisting of n pixels and effecting the processing of output of the information is provided with a plurality of memory devices, a distributing device and an output control device. The information is stored in the plurality of memory devices. By the distributing device, the image information consisting of the n pixels are divided into m pixel unit basis (n > m), and the information consisting of the m pixels into a p (m > p) pixel unit basis, and the plurality of information each consisting of the p pixels are distributed to the plurality of memory devices. Upon the output of the image information, the information stored in the plurality of memory devices are selectively outputted by the output control device.

Description: BACKGROUND OF THE INVENTION Field of the Invention The invention relates to an information processing apparatus using a technique of a scanning tunnel microscope or the like. Related Background Art In recent years, memory materials are mainly used in the electronics industries such as computer, its peripheral apparatuses, video disc, digital audio disc, and the like. The development of the memory materials are also extremely actively being progressed. Although the performances which are required for such memory materials are different depending on the application, it is indispensable that a response speed for recording and reproducing is high. Hitherto, a semiconductor memory or a magnetic memory which is made of a material such as magnetic material or semiconductor is a main stream. However, in association with the development of the recent laser technique, a cheap recording medium of a high density by an optical memory using an organic thin film such as organic pigment, photo polymer, or the like has been put into practical use. On the other hand, in recent years, a scanning tunnel microscope (hereinafter, abbreviated to STM) which can directly observe an electron structure of a surface atom of a conductor has been developed (G. Binnig, et al., Phys. Rev. Lett, 49, 57, 1982). A real spatial image can be measured at a high resolution irrespective of a difference between a monocrystal and an amorphous. Moreover, there is also an advantage such that the image can be measured with a low electric power without damaging a sample by a current. Further, the STM can operate even in the atmosphere and can be used for various materials. Therefore, applications to a wide range are expected. The STM uses a principle such that when a voltage is applied between a metal probe (probe electrode) and a conductive material and the probe is allowed to approach up to a distance of about 1 nm, a tunnel current flows. The tunnel current is very sensitive because it exponentially responds to a change in distance between the probe and the conductive material. By scanning the probe so as to keep the tunnel current constant, various information regarding the whole electron cloud in the real space can be also read. In this instance, a resolution in the in-plane direction is equal to about 0.1 nm. Therefore, by applying the principle of the STM, the high density recording and reproduction can be sufficiently executed on the order of atom (subnanometer). For instance, according to an information processing apparatus disclosed in JP-A-61-80536, atomic particles adsorbed on the medium surface are removed by an electron beam or the like and data is written and the written data is reproduced by the STM. There has also been proposed a method of performing the recording and reproduction by the STM by using a thin film as a recording layer which is made of a material having a memory effect to switching characteristics of a voltage current, for instance, an organic compound or chalcogen compound class having a conjugate π electron system (JP-A-63-161552, JP-A-63-161553). According to the above method, by setting a pit size for recording to 10 nm, the recording and reproduction of a large capacity of 10 12 bits/cm 2 can be performed. As a scanning mechanism of the probe electrode, there is a cantilever type (JP-A-62-281138). It is possible to form several tens of cantilever type mechanisms each of which is made of SiO 2 and has dimensions such that a length is equal to 100 µm, a width lies within a range from 10 to 20 µm, and a thickness is equal to 0.5 µm onto an Si substrate. A writing/reading circuit is also integrated on the same substrate. Generally, in the case of recording and reproducing image information at a high quality, a searching operation such as to pick up arbitrary one of a plurality of images is required. In case of information such as a still image file in which there is no correlation among the images, such a searching operation is particularly required. Actually, operations such that a plurality of images are simultaneously generated to a display such as a monitor or the like and the operator selects a desired image or the like are executed as such a searching operation. In this case, since an information amount per picture plane is very large, all of the pixels are not generated but they are thinned out and displayed in accordance with the resolution of the monitor. In case of generating the pixels to an apparatus such as monitor, printer, or the like having different display resolutions, the operations such that the pixels are also thinned out and the like are executed and the resultant image data is generated. Hitherto, however, an image of a low resolution is formed from an original image by software processes. Consequently, it takes some time to form an image of a necessary resolution, and the output time increases. An information processing apparatus of the kind defined by the precharacterizing features of claim 1 is known from the EP-A-O 439 144. In accordance with this document distributed information is recorded sequentially by this apparatus on tape by a single head. Therefore, reduced image of each frame is read out only sequentially. That means, when a simultaneous indication of two frames is made on a display, the reduced image of the first frame is read out, and thereafter, the reduced image of the second frame is read out. There is no possibility to simultaneously indicate a plurality of images at high speed. The GB-A-2 231 453 discloses a video tape recorder with a divider for dividing the video data in subpicture blocks, each block comprising N data elements, wherein N is an integer equal to or larger than 2 and preferably 16. Moreover, this known apparatus comprises a data reproducing circuit for reproducing the first through M-th of the recorded subpicture data elements, where M is an integer such that 1 ≤ M < N. Thereby, during a quick turnover operation, data retrieval speed is increased. The GB-A-2 199 982 discloses a data reduction system for a similar video tape system as discussed above, that system comprising dividing means for dividing video data information into a plurality of segments, each segment being assigned to record full raster information at a partial of fractional pixel resolution. Moreover, each of these segments is further divided into Y, I and Q components of a television signal. SUMMARY OF THE INVENTION It is an object of the invention to provide an information processing apparatus of the kind defined by the precharacterizing features of claim 1 which can accomplish reduction (high processing speed) of a processing time upon generation of image information. This object is attained by the characterizing features of claim 1. Advantageous developments of the invention are defined in the subclaims. According to such an apparatus, the image information supplied is distributed by the distributing means so as to obtain the image in which the original image is thinned out into l/(the number of memory blocks) when it is seen on a memory block unit basis. When the image information is outputted, only the memory blocks according to the necessary resultion among the outputs of the memory blocks are accessed and the signals of the accessed memory blocks are outputted. The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a whole constructional diagram of an embodiment according to the invention; Fig. 2 is a constructional diagram of a memory block shown in Fig. 1; Fig. 3 is a diagram showing pixels of an original image according to the embodiment; Fig. 4 is a diagram showing the pixels of the image of 1/4 of the original image according to the embodiment; Fig. 5 is a diagram showing the pixels of the image of 1/2 in the vertical direction of the original image according to the embodiment; Fig. 6 is a diagram showing the pixels of 1/2 in the lateral direction of the original image according to the embodiment; Fig. 7 shows a waveform of a pulse for writing in the recording mode in the embodiment; Fig. 8 shows a waveform of a pulse for erasing in the recording mode in the embodiment; Fig. 9 is a block diagram showing a control circuit of the distance between a probe electrode and a recording medium in the embodiment; and Fig. 10 is a whole constructional diagram of an example useful for understanding the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention will be practically explained hereinbelow with respect to an embodiment. (preferred embodiment) There is shown an embodiment in the case where an information processing apparatus of the invention is applied to a still video camera. Fig. 1 is a constructional diagram of the embodiment. In Fig. 1, reference numeral 101 denotes a lens; 102 a CCD; 103 an A/D converter; 104 an information distributing mechanism (distributing means); 105 a clock generator; 106 a CPU; 107 an information recovery mechanism (output control means); 108, 109, 110, and 111 memory blocks; 112 a frame memory; 113 a D/A converter; and 114 an image display device. According to the above construction, image information (the total number of pixels of the image information is determined by the effective pixels of the CCD) whose image has been formed onto the CCD (pixels of the effective pixels) 102 by the lens 101 is converted into a digital signal by the A/D converter 103. An output of the A/D converter 103 is divided by the information distributing mechanism 104 on an m (n > m) pixel unit basis, for instance, a pixel unit basis of 2 x 2 pixels. Further, the m pixels are divided on a p (m > p) pixel unit basis, for instance, one pixel unit basis. Each of the p pixels among the m pixels is distributed to m/p memory blocks 108 to 111, respectively. Inputs of the memory blocks are controlled synchronously with the clocks obtained by frequency dividing an output frequency of the A/D converter 103 that is controlled by the clock generator 105 into 1/4. It is now assumed that m = 2 x 2 = 4 and p = 1 for simplicity of explanation. That is, the elements a xx , b xx , c xx , and d xx of (2 x 2) pixels of the original image in Fig. 3 are recorded into the respective memory blocks as image information in a format similar to that of the image consisting of only the element a xx shown in Fig. 4 which has been distributed. It is now assumed that an element a xx has been recorded into the memory block 108, an element b xx has been recorded in the memory block 109, an element c xx has been recorded in the memory block 110, and an element d xx has been recorded in the memory block 111. When the image is reproduced, although outputs of the memory blocks are controlled by similar clock, an input channel of the information recovery mechanism 107 is selectively controlled by the CPU 106 in accordance with an image with a required resolution. Therefore, the image of 1/2 in the vertical direction as shown in Fig. 5 can be easily formed from the output image information of the memory blocks 108 and 109. The image of 1/2 in the lateral direction as shown in Fig. 6 can be easily formed from the output image information of the memory blocks 108 and 110. Since one memory block solely has the image information as shown in Fig. 4, in the case where addresses which are designated in the memory blocks are deviated by a few frames and the image information of different frames are respectively generated from the memory blocks, by writing the image information into the addresses in the frame memory 112 by the information recovery mechanism 107 in Fig. 1 in a manner such that four images are displayed like a matrix onto the image display device 114, four images can be simultaneously displayed. The image information that is finally generated is accumulated into the frame memory 112 and is converted into the analog information by the D/A converter 113 and outputted in accordance with a sync frequency of the image display device 114. The recording and reproducing operations in the memory block will now be described with reference to Fig. 2 showing a constructional diagram of the memory block. In Fig. 2, reference numeral 201 denotes an encoding circuit; 202 a modulation circuit; 203 a substrate; 204 a cantilever type scanning mechanism; 205 a probe electrode; 206 a recording medium; 207 an XY scanning mechanism; 208 a demodulation circuit; 209 a decoding circuit; 210 a reading/writing circuit; and 211 an address generator. Four reading/writing circuits 210 and the cantilever type scanning mechanism are formed on the same substrate 203. In the embodiment, since the operation of the information and the control of the mechanism are executed in the same manner for each memory block, one memory block will be explained. First, the input information is BCH encoded by the encoding circuit 201 for error correction. Subsequently, an RZ modulation is executed by the modulation circuit 202. The modulated data is recorded onto the recording medium 206 by the probe electrode 205 which has been moved to the position according to an output write address of the address generator 211 by the XY scanning mechanism 207. In the reproducing mode, the recorded information is read out by the probe electrode which has been moved by the XY scanning mechanism 207 to the position according to the output read address of the address generator 211 (In this instance, the information is read out by detecting a change in tunnel current flowing in the probe electrode). The readout data is demodulated by the demodulation circuit 208 and is decoded by the decoding circuit 209 and is outputted. Actually, the recording medium 206 is manufactured as follows. That is, Au is epitaxially grown on a smooth substrate obtained by cleaving mica. Eight layers of squalillium-bis-6-octylazulene (hereinafter, abbreviated to SOAZ) having an electric memory effect are laminated on the Au substrate by a Langmuir-Blodgett (LB) method, thereby forming a recording layer as a recording medium 206. The recording medium 206 is constructed by the substrate and an underelectrode layer (not shown). Since the recording layer is made of a material having the memory effect for the switching characteristics of a voltage current, in the recording mode, it is sufficient to apply a pulse voltage of a waveform as shown in Fig. 7 between the probe electrode and the recording medium. In the erasing mode, it is sufficient to apply a pulse voltage of a waveform as shown in Fig. 8. In the reproducing mode, a voltage of about 100 mV such that the memory state of the recording layer doesn't change is applied and "1" or "0" is judged by a difference of a conductivity of the recording layer at that time. The distance between the recording medium and the probe electrode is controlled as follows by using a control circuit of Fig. 9. Generally, a bias voltage of about 100 mV is applied between the recording medium and the probe electrode. The probe electrode is allowed to approach the recording medium by the cantilever type scanning mechanism 204 until a state in which a current of about 2 nA flows. The current detected by the probe electrode 205 is converted into the voltage signal by an I/V converting circuit 901. The signal passes through an LPF 902 whose cut-off frequency is set to about a scanning frequency so that the probe electrode can trace only the component of frequencies which are equal to or lower than the frequency upon scanning of the detection current signal due to an inclination on the substrate or the like. The signal is transmitted through a phase compensation circuit 903 and a difference between an output voltage of the phase compensation circuit 903 and an offset voltage is calculated by a differential amplifier 904 so that the distance between the probe electrode and the recording medium is set to a constant value as an average. The signal which has been transmitted through the above circuit is used to control the cantilever type scanning mechanism 204, thereby performing a feedback control. In the recording mode, the distance between the probe electrode and the recording medium is set to a constant value. A sample and hold circuit 905 is set into a holding state by the feedback control so as not to cause a collision between them. Although the BCH encoding and the RZ modulating method have been used in the embodiment, the invention is not limited to them but other various methods which are generally used can be used. There is shown an example being useful for understanding the invention in which the information processing apparatus is applied to a still video camera and an outputting speed to a printer is raised. Fig. 10 is a constructional diagram of the example. In Fig. 10, reference numeral 101 denotes the lens; 102 the CCD; 103 the A/D converter; 104 the information distributing mechanism; 105 the clock generator; 106 the CPU; 107 the information recovery mechanism; 1001 a group of memory blocks consisting of 25 memory blocks; and 1002 a printer. According to the above construction, image information consisting of (2000 x 1125) pixels whose image has been formed on the CCD 102 by the lens 101 is converted into the digital signal by the A/D converter 103. An output of the A/D converter 103 is supplied to the information distributing mechanism 104, by which one information in (5 x 5) pixels is distributed into 25 memory blocks, respectively. The inputs of the memory blocks are controlled synchronously with clocks obtained by frequency dividing the output frequency of the A/D converter 103 that is controlled by the clock generator 105 into 1/5. In the printing mode, although the outputs of the memory blocks are controlled by similar clocks, in the information recovery mechanism 107, the input of one of the input channels is permitted by the CPU 106 in case of a single print. From the data of the permitted input channel, the information recovery mechanism 107 outputs the image information and can print at a high speed. By making the output images of the memory blocks different, a plurality of images can be continuously outputted at a high speed. In the exemple, since the original image is distributed into 1/5 in each of the vertical and lateral directions, it is optimum to a printer having a resolution of about 400 d.p.i.. If the outputs of all of the channels are set to the outputs of the same frame, they can be outputted to a printer of a high precision or a conventional method whereby a resolution is reduced by executing processes in a software manner can be also used. The operations in the memory block are similar to those in the preferred embodiment.

Claims: An information processing apparatus for storing and outputting image information consisting of n pixels, comprising: a plurality of memory means adapted to store the information and output the stored information (108-111); distributing means (104) for dividing each image information consisting of the n pixels into an m pixel unit wherein m is an integer and n > m, for further dividing the information consisting of the m pixels into a p pixel unit wherein p is an integer and m > p, and for distributing the plurality of divided information consisting of the p pixels to said plurality of memory means, wherein each of said plurality of memory means is adapted to store image information each of which consists of the distributed p pixels and the resolution of which is lower than that of the image information consisting of the n pixels; and collecting, demodulating and decoding means (106, 107) for selectively collecting the information stored in said plurality of memory means and for outputting the collected information, characterized in that each of said plurality of memory means (108, 111) is capable of independently outputting the stored information, said apparatus further comprises: an address generator (211) for outputting an address in the memory where the information is to be stored upon storing of the information and an address in the memory where the information is to be output upon output of the stored information, and each of said plurality of memory means stores and outputs the information on the basis of said address, and image display or printing means for simultaneously displaying or printing plural different image information respectively output from said plurality of memory means. An apparatus according to claim 1, wherein each of said plurality of memory means includes a probe and a recording medium disposed so as to be opposed to said probe.

Inventors: HATANAKA KATSUNORI, OGUCHI TAKAHIRO, SAKAI KUNIHIRO, SHIDO SHUNICHI, YAMANO AKIHIKO, HATANAKA, KATSUNORI, OGUCHI, TAKAHIRO, SAKAI, KUNIHIRO, SHIDO, SHUNICHI, YAMANO, AKIHIKO, HATANAKA, KATSUNORI, C/O CANON KABUSHIKI KAISHA, OGUCHI, TAKAHIRO, C/O CANON KABUSHIKI KAISHA, SAKAI, KUNIHIRO, C/O CANON KABUSHIKI KAISHA, Shido, Shunichi, c/o Canon Kabushiki Kaisha, YAMANO, AKIHIKO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: G09G1
IPC codes: G11B7, G11C7, H04N5, G11B20, G11B9, G09G5