Solid state imager

Abstract: The horizontal transfer section of a solid state imager comprises a well-region (12) of a second conductivity type formed on the surface of a semiconductor substrate (11) of a first conductivity type and a signal charge transfer region (14b) formed on the surface of the well-region (11) of the second conductivity type. The well-region (12) is formed completely in depletion state by implantation of impurities into this well-region (12), thereby improving the horizontal transfer efficiency without substantially affecting other element sections.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method of fabricating a solid state imager including a charge transfer section and, more particularly, to the fabrication of a horizontal transfer section of a solid state imager in which charge transfer efficiency of its horizontal transfer section is improved. Description of the Prior Art FIG. 1 of the accompanying drawings shows an arrangement of a CCD (charge-coupled device) solid state imager of, for example, an interline transfer type as an example of conventional solid state imagers. As shown in FIG. 1, an image pickup section 3 is comprised of a plurality of sensitive units (pixels) 1 arrayed in the horizontal and vertical directions at the unit of pixel in a two-dimensional manner so as to store signal charges corresponding to the amount of an incident light and a vertical shift register (vertical transfer sections) 2 for transferring signal charges read-out from these sensitive sections 1 at every vertical column to the vertical direction. In the image pickup section 3, the sensitive section 1 is made of, for example, a photodiode and the vertical shift register 2 is made of a CCD. Signal charges transferred to the vertical shift register 2 are sequentially transferred to a horizontal shift register (i.e., horizontal transfer section) 4 by an amount corresponding to one scanning line during a part of the horizontal blanking period. Signal charges corresponding to the amount of one scanning line are sequentially transferred by the horizontal shift register 4 to the horizontal direction. An output circuit section 5 is provided at the end of the horizontal shift register 4. This output circuit section 5 is formed of a floating diffusion amplifier (i.e., FDA) to convert a signal charge transferred thereto into an electrical signal. Of this kind of CCD solid state imager, particularly in a device utilizing a semiconductor substrate of a first conductivity type, e.g., N type, respective elements are provided on a P-well region and this P-well region is formed in depletion state so as to function as an overflow barrier in order to remove a so-called blooming in the image sensor section. As to the horizontal shift register 4, in order to match the drive condition of a transfer clock for driving the horizontal transfer section, i.e., in order to match the voltage level (e.g., voltages of 5V and OV) of a horizontal transfer clock, the potential of the P well-region is decreased by the implantation of boron (B) therein. In this case, however, since the potential of the P well-region is lowered or made shallow by the implantation of boron (B) to the P well-region, it is to be understood that, when the horizontal transfer clock is "L" (low) in level, the P well-region is not formed in depletion state. As a result, the potential of the P well-region becomes neutral, thus resulting in the charge transfer efficiency of the horizontal transfer section being deteriorated. EP-A-0 278 565 discloses a charge-coupled device for an image sensor, said device comprising a semiconductor body having a vertical npn configuration, in which the upper n-type layer constitutes a buried channel of the CCD, the p-type layer constitutes an overflow barrier for excess charge carriers and the lower n-type layer constitutes a drain of the excess charge carriers. Both the p-type layer and the lower n-type layer are each provided with an electrical connection for applying a voltage with which a potential barrier between the p-type layer and the lower n-type layer can be controlled for "anti-blooming" purposes. OBJECTS AND SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an improved method of fabricating a solid state imager in which the aforesaid shortcomings and disadvantages of the prior art can be eliminated. It is another object of the present invention to provide a method of fabricating solid state imager in which a charge transfer efficiency in the horizontal transfer section can be improved without substantially exerting a bad influence on other elements. In order to achieve the aforesaid objects, a method is provided so that in a solid state imager having a horizontal transfer section comprised of a well-region of a P type formed on the surface of a semiconductor substrate of an N type and a signal charge transfer region formed on the surface of the well-region of the P type, this well-region of the P type is formed completely in depletion state by the implantation of impurities onto the above well-region. In the horizontal transfer section of the solid state imager fabricated according to the present invention, in order to match the driving condition of the transfer clock, the potential is made shallow by the implantation of boron onto the well-region of the P type and then the well-region is formed completely in depletion state by the implantation of donors onto this well-region. Energy of the ion implantation is selected to be high so as not to affect the signal charge transfer region substantially. Since the well-region is formed completely in depletion state, the charge transfer efficiency in the horizontal transfer section can be increased. Further, since the mask for the implantation of impurities is used commonly when the implantation of donor is carried out, the improvement of the charge transfer efficiency can be realized only by adding the ion implantation process. The invention is defined in claim 1. The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description of an illustrative embodiment thereof to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a structure of a conventional CCD solid state imager of an interline transfer type; FIG. 2 is a cross-sectional view of a horizontal transfer section of a solid state imager fabricated according to the method of the present invention; FIG. 3 is a diagram of potentials in respective regions before the implantation of boron; FIG. 4 is a diagram of potentials in respective regions after the implantation of boron; and FIG. 5 is a diagram of potentials in respective regions after the implantation of donor. DETAILED DESCRIPTION OF PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a cross-sectional view of a structure of a horizontal transfer section in a solid state imager fabricated according to the present invention. Referring to FIG. 2, on the surface of a semiconductor substrate 11 of a first conductivity type, i.e., N type, there is formed a well-region of a second conductivity type, i.e., P type (hereinafter simply referred to as a P well-region) 12, and an N type region 13 is formed on the surface of the P well-region 12. A horizontal shift register 4 (see FIG. 1) is comprised of a signal charge storage region 14a of an N type, a signal charge transfer region 14b of an N- type, both being formed on the surface of the N type region 13, a storage gate electrode 16 and a transfer gate electrode 17, which are formed on the regions 14a and 14b through an insulating layer 15 made of a silicon oxide layer (SiO 2 layer) 15. In the horizontal shift register 4, the adjacent storage gate electrode 16 and transfer gate electrode 17 form a pair and supplied with two-phase transfer clocks  H1 and  H2 to thereby transfer the signal charges in the horizontal direction. In order to match the driving condition by the two-phase clocks  H1 and  H2 , that is, in order to enable the transfer driving by the transfer clocks  H1 and  H2 of two values in which the "L" level is 0V and the "H" level is 5V, the potential is lowered or made shallow by the implantation of boron (B) to the P well-region 12. FIG. 3 shows a diagram of potentials of respective regions before the implantation of boron and FIG. 4 shows a diagram of potentials of respective regions after the implantation of boron, respectively. A broken line in FIG. 4 shows the potential before the implantation of boron in FIG. 3. As is clear from FIG. 4, by the implantation of boron to the P well-region 12, the potential becomes shallow over the whole regions and particularly the potential of the P well-region 12 becomes neutral (neutral region). After the implantation of boron, the P well-region 12 is further implanted with donor (donor impurity) of energy which is selected substantially so as not to exert a bad influence on other element sections such as the transfer region or the like. When the donor is implanted, a mask through which the boron is already implanted is used commonly. By implanting the high-energy donor into the P well-region 12, as shown in FIG. 5, the P well-region 12 can be formed completely in depletion state while substantially maintaining the potential of the N type region 13 at the potential shown by the solid line in FIG. 4. In that case, in order to prevent the potential of the transfer regions and so on formed on the surface of the N type region 13 from being made deep, the dose amount of donor impurity must be optimized. Incidentally, a broken line in FIG. 5 shows a potential after the implantation of boron in FIG. 4. As described above, according to the present invention, since the P well-region is made completely in depletion state by the implantation of donor whose energy is selected high so as not to exert a bad influence upon other element sections substantially, the charge transfer efficiency in the horizontal transfer can be improved while other element sections are prevented from being affected substantially. Further, since the mask used for the implantation of boron is used commonly upon implantation of donor impurity, the improvement of the charge transfer efficiency can be realized only by adding the ion implantation process.

Claims: A method of fabricating a solid state imager including a horizontal shift register (4), said method comprising the steps of a) providing an n-type semiconductor substrate (11) and forming a p-type well-region (12) on the surface of said substrate (11); b) forming an n-type region (13) on the surface of said well-region (12); c) implanting boron to the well-region (12) by using a mask, wherein the energy of the ion implantation is selected high so as not to affect essentially the n-type region (13), in particular the region corresponding to the horizontal shift register (4), wherein the implantation effects that the potential becomes shallow over the whole regions and the potential of the well region (12) becomes neutral; d) implanting donor impurities to the well-region (12) by using the same mask as in step c) to form the well-region (12) completely in depletion state, wherein the energy of the ion implantation is selected high so that the potential of the n-type region (13), in particular the region corresponding to the horizontal shift register (4), is substantially maintained; e) forming the horizontal shift register (4) in said n-type region (13), said horizontal shift register (4) comprising an n-type signal charge storage region (14a) and an n-type signal charge transfer region (14b), both being formed on the surface of the n-type region (13), and a storage gate electrode (16) and a transfer gate electrode (17) which are formed on the storage region (14a) and the transfer region (14b) through an insulating layer (15), respectively.

Inventors: HOJO JUNICHI, WAKAYAMA TOSHIAKI, HOJO, JUNICHI, WAKAYAMA, TOSHIAKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H01L27
IPC codes: H01L27, H04N5