Encoding apparatus for digital signal with improved block channel coding

Abstract: An encoder (3) separates an input digital signal including m bits into the first group and the second group, and encodes each piece of data in the first group to a single code word including n bits in one-to-one correspondence and encodes each piece of data in the second group to two code words each including n bits in one-to-two correspondence. A CDS calculator (4) calculates a CDS value for each of the words output from the encoder (3). A DSV calculator (7) calculates the accumulated DSV value of the individual words output from the encoder (3). When the two-n-bit code words are output from the encoder (3), a code selector (5) selects that one of the code words which decreases the next accumulated DSV value to be calculated by the DSV calculator (7), according to the CDS value from the CDS calculator (4) and the accumulated DSV value from the DSV calculator (7). A margin bit generator (6) generates a predetermined margin bit which decreases the next accumulated DSV value to be calculated by the DSV calculator (7), according to the CDS value from the CDS calculator (4) and the accumulated DSV value from the DSV calculator (7), and inserts the margin bit in the single n-bit code word output from the encoder (3) and the one code word selected by the code selector (5). A transfer section (8-10) transfers an encoded code word including a total of n+1 bits resulting from the insertion by the margin bit generator (6).

Description: The present invention relates to an encoding apparatus, and, more particularly, to an encoding apparatus with improved block channel coding, which is used to convert a digital signal, such as a video signal, into a code word, and record or reproduce the code word. There have been developed apparatuses which sample a signal having an approximation correlation, such as a color video signal of a high definition television (HDTV) system, to covert it to digital data of m bits per sample, e.g., 8 bits (one word), and then record that data on a video tape recorder (VTR) for later reproduction. If 8-bit data is recorded as it is by such an apparatus, "1" and "0", binary levels of the record signal at that time, do not appear evenly, so that the record signal is likely to include a DC component. Because the magnetic head of an ordinary recording/reproducing apparatus cannot reproduce the DC component before the reproduction, the record signal is subjected to an encoding process including block channel coding so as not to include the DC component. The block channel coding included in the encoding process at the time of such recording should be carried out so as to make the DSV (Digital Sum Variation) value of the record signal as small as possible. The "DSV" is a value acquired by integrating a binary level "1" or "0" in association with "+1" or "-1" respectively, and has a value at an arbitrary point of time or in an arbitrary period of time. In the case where a DSV for successive binary signals is acquired from the beginning, the record signal has a DC component if the DSV increases or decreases infinitely, while the record signal has no DC component if the DSV is finite. Fig. 12 is a block diagram showing a conventional magnetic recording/reproducing apparatus which digitalizes a color video signal as explained above, and records the digital signal on a VTR or reproduces the recorded signal therefrom, as disclosed in Published Unexamined Japanese Application No. 58-75950. A video signal input from an input terminal 1 is converted into an 8-bit parallel digital signal by an A/D converter 2, and this digital signal is then sent to a DSV control encoding circuit 103. The encoding circuit 103 replaces the input digital signal with an associated one of 8-bit words prepared by rearranging the aforementioned individual 8-bit data words according to a predetermined rule. In this case the words to be replaced with are stored in, for example, a read only memory (ROM), so that the target word to replace the input data is read out from the ROM by specifying the address with the corresponding natural binary code, resulting in replacement of the input data with the read-out word. The words replaced in the D/A converter 103 are input to an inversion processing circuit 104, which in turn changes the input words to complementary words, for example, word by word. In the inversion processing circuit 104, a certain word is directly output, and one word following that word is changed to a word with inverted "1" and "0". For instance, if data word (DSVCC), "00110001," having a CDS (Code word Digital Sum) value of -2 is inverted, it is converted into "11001110." The CDS value of this data word is +2. In other words, a complementary word to the word input from the encoding circuit 103 is such that the positive or negative polarity of its CDS value is opposite to that of the original word. In this manner the word as input and the inverted word are alternately output from the inversion processing circuit 104. As an input color video signal has a high correlation, it is easily understood that the DSV values of output data words of the inversion processing circuit 104, if computed, will converge to "0." The words from the inversion processing circuit 104 are supplied to a parallel/serial converter 105 to be converted into serial data. That is, the 8-bit parallel data is converted into serial data which is then supplied to a VTR section 11. In this VTR section 11 one-field data of the color video signal is recorded on a tape as a plurality of tracks. It is to be noted that the "CDS value" mentioned above is the value of the sum of code data of one word, considering that "1" and "0" of the code data are "+1" and "-1," respectively, and is called a weight of a code. The DSV value is therefore an accumulated value of the CDS values. Thereafter, the tape having data recorded by the VTR section 11 in the above manner is played, and the reproduced data is converted into 8-bit parallel data by a serial/parallel converter 107. This parallel data is then input, word by word, to a reverse inversion processing circuit 108. The reverse inversion processing circuit 108 subjects the input word to the opposite process to the one executed in the inversion processing circuit 104 at the recording time, to restore the complementary word at the recording time to the original word. The restored original word from the reverse inversion processing circuit 108 is input to a DSV control decoding circuit 109. This decoding circuit 109 subjects the input word to the completely opposite processing as done by the encoding circuit 103 of the recording system, thereby restoring the input word to the original digital data. In this respect the DSV control decoding circuit 109 has a RAM, and the word acquired by this circuit 109 becomes the original natural binary code. This natural binary code is input to a D/A converter 50. The D/A converter 50 converts the input digital data to an analog color video signal which is sent to an output terminal 60. Problems inherent to the above conventional signal processing system will be discussed below referring to Figs. 11A to 11D. In general magnetic signal recording/reproduction, a reproduced signal has a frequency response as shown in Fig. 11A. This characteristic shows the output amplitude characteristic of a reproduced signal with a flat noise distribution. The feature of this characteristic will be discussed below. Referring to the diagram, the low frequency component indicated by the arrow A has a low C/N (carrier to noise) ratio due to the differential characteristic of the magnetic head. The intermediate frequency component indicated by the arrow B has a good C/N ratio; of this component, the component having a low frequency has a higher C/N ratio than the one having a higher frequency. The high frequency component indicated by the arrow C has a low C/N ratio due to losses of a magnetic tape and the magnetic head. The error rate for a signal having a spectrum shown in Fig. 11B is sent onto a transfer path including the above-described magnetic recording and reproduction, has a relation a ○, d ○ > c ○, b ○. Therefore, concentrating the spectrum on the portion having a good C/N ratio can reduce the error rate to ensure high density recording. In the conventional magnetic recording/reproducing apparatus as shown in Fig. 12, however, the signal that is recorded and reproduced has many spectrum components around a ○ and d ○ or concentrated more on c ○ than on b ○. This means that the best use of the capacity of the transfer path (specifically, the magnetic tape, magnetic head, etc.) is not always made. When the signal to be recorded is image data having a correlation, the conventional magnetic recording/reproducing apparatus as shown in Fig. 12 can suppress the low frequency component of the record signal or the reproduced signal. The spectrum of the record signal does not however match the characteristic of the transfer path, which means that the portion of the transfer path with a good C/N ratio is not effectively used, thus degrading the image quality accordingly. In other words, the conventional magnetic recording/reproducing apparatus, which converts an analog video signal into a digital signal and encodes the digital signal before recording it on a VTR or reproducing it therefrom, has the first shortcoming such that because the spectrum of the record signal does not match the characteristic of the transfer path, the portion of the transfer path with a good C/N ratio cannot effectively be used, thus degrading the image quality at the recording/reproducing time accordingly. The above conventional signal processing system has the following shortcoming. The band of codes which are electrically transferred in the above-described signal processing system is broad, ranging from a low frequency range to a high frequency range. Given that the minimum magnetism inversion time is denoted by Tmin and the data clock period by T, Tmin/T is defined as a density ratio DR. In the above prior art, this DR is 1 and the record signal often includes a high frequency component, necessitating the use of that portion where the magnetic head does not have a good characteristic. This increases the error rate at the recording/reproducing time, degrading the quality of the image signal at the recording/ reproducing time. That is, the conventional magnetic recording/reproducing apparatus, which converts an analog video signal into a digital signal and encodes the digital signal before recording it on a VTR or reproducing it therefrom, has the second shortcoming such that because of the density ratio DR being "1," the record signal tends to include many high frequency components, broadening the band on the high frequency side of the signal that is to be recorded on or reproduced from a VTR. This increases the error rate at the recording/reproducing time, degrading the quality of the image signal at the recording/reproducing time. The above conventional signal processing system also has the following shortcoming. Since the band of codes which are electrically transferred in the above-described signal processing system is broad, ranging from a low frequency range to a high frequency range, when a video signal has a successive variation, the DSV value diverges so that the record signal contains a considerable amount of DC components and low-frequency energy. This requires the use of that portion where the magnetic head does not have a good characteristic, thus increasing the error rate at the recording/reproducing time. In addition, even when the video signal has no variation and has the same level, inversion is carried out word by word, thus increasing the maximum magnetism inversion time Tmax. This increases the amount of DC components of the record signal and the low-frequency energy, also increasing the error rate at the recording/reproducing time. Further, since the minimum magnetism inversion time Tmin is the same as the data clock period T as mentioned above, the density ratio DR becomes "1," the record signal often contains a DC component and it becomes necessary to use that portion where the magnetic head does not have a good characteristic. The error rate at the recording/reproducing time will also increase in this respect. In short, the conventional magnetic recording/reproducing apparatus has the third shortcoming such that because the signal to be recorded on the VRT 11 has a broad band, the quality of the image signal at the recording/reproducing time is deteriorated. The conventional magnetic recording/reproducing apparatus, which converts an analog video signal into a digital signal and encodes the digital signal before recording it on a VTR or reproducing it therefrom, therefore has the fourth shortcoming such that the DSV value diverges or the maximum magnetism inversion time Tmax is large, so that the record signal contains a considerable amount of DC components and low-frequency energy. This increases the error rate at the reproducing time, deteriorating the image quality. Further, because the density ratio DR is "1," the record signal tends to include many high frequency components, increasing the error rate at the recording/reproducing time. This further degrades the image quality. Prior art document EP-A-0 178 813 discloses a method and apparatus for encoding binary data. In this method, data words each containing n data bits are converted into channel words each containing m data bits, and NRZI code data are produced from the channel words. In the converting step, a data word is not converted in real time when the data word has a specific data bit pattern or when the data word is in a specific relation to adjacent data words. This unconverted data word is converted to an established channel word which is determined as to reduce DSV at a time when the predetermined number of data words which are convertible in real time have been inputted or when another data word which should be maintained unconverted has been inputted again. It is an object of the present invention to provide a new and advanced encoding apparatus for a digital signal with improved block channel coding in which the DSV value is finite and made small, so that, when used particularly in a magnetic recording/ reproducing apparatus, this apparatus can contribute to improving the image quality at the recording/reproducing time by setting the maximum magnetism inversion time small and increasing the density ratio. It is another object of the present invention to provide an encoding apparatus which can suppress the high frequency component of a record signal/reproduce signal by increasing the density ratio, so that when used particularly in a magnetic recording/reproducing apparatus, it can contribute to improving the image quality at the recording/reproducing time. It is a further object of the present invention to provide an encoding apparatus which can permit the spectrum of an encoded image signal to concentrate on that portion of a transfer path having a good C/N ratio, so that when used particularly in a magnetic recording/ reproducing apparatus, it can significantly improve the error rate at the recording/reproducing time, thus contributing to improvement of the image quality at the recording/reproducing time. According to the present invention, there is provided an encoding apparatus which converts an input digital signal into a predetermined code word, in the code word, the minimum number of "Os" between the codes "1" which indicate change points based on an NRZI rate and correspond to magnetism inversion, is one, said code word having a "1"-bit state and a "0"-bit state corresponding to normal and reverse states of the digital modulation signal, said encoding apparatus comprising: encoding means (3) for separating the input digital signal including m bits (m: a positive integer) into a first group and a second group predetermined with respect to 2 m pieces of data allowable for said input digital signal, and encoding each piece of data in said first group to a single code word including n bits (n being a positive integer and larger than m) in one-to-one correspondence and encoding each piece of data in said second group to two code words each including n bits in one-to-two correspondence; code word digital sum (CDS) calculating means (4) for calculating a CDS value for each of said words output from said encoding means (3); digital sum variation (DSV) calculating means (7) for calculating an accumulated DSV value of said individual words output from said encoding means (3); code selecting means (5) for, when said two n-bit code words are output from said encoding means (3), selecting that one of said code words which decreases a next accumulated DSV value to be calculated by said DSV calculating means (7), in accordance with said CDS value from said CDS calculating means (4) and said accumulated DSV value from said DSV calculating means (7); margin bit inserting means (6) for generating a predetermined margin bit which decreases a next accumulated DSV value to be calculated by said DSV calculating means (7), in accordance with said CDS value from said CDS calculating means (4) and said accumulated DSV value from said DSV calculating means (7), and inserting said margin bit in said single n-bit code word output from said encoding means and said one code word selected by said code selecting means (5); and transfer means (8-10) for transferring an encoded DSV code word including a total of n+1 bits resulting from the insertion of said predetermined margin bit by said margin bit inserting means (6), whereby said encoding means (3) includes: means for assigning "0" to both first and last bit positions of the single n-bit code word when encoding is executed in one-to-one correspondence; and means for assigning "1" and "0", "0" and "1" to first and last bit positions of each of the two n-bit code words when encoding is executed in one-to-two correspondence. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram illustrating an embodiment of an encoding apparatus according to the present invention; Figs. 2A to 2D are diagrams exemplifying the structures of signals processed in the encoding apparatus shown in Fig. 1; Fig. 3 is an encoding diagram showing the correlation between input data and a code word in a mapping converter shown in Fig. 1; Fig. 4 is a diagram showing the CDS value and the number of change points of a code word produced in the encoding apparatus shown in Fig. 1; Fig. 5 is a diagram illustrating the patterns of combining two pairs of code words used in the encoding apparatus in Fig. 1; Fig. 6 is a diagram for explaining how a margin bit is used after produced by a margin bit generator shown in Fig. 1; Figs. 7A and 7B are diagrams for explaining an operation for controlling the DSV value by the encoding apparatus in Fig. 1; Fig. 8 is a diagram for explaining another operation for controlling the DSV value by the encoding apparatus in Fig. 1; Fig. 9 is a diagram for explaining further operation for controlling the DSV value by the encoding apparatus in Fig. 1; Figs. 10A and 10B are diagrams showing the frequency bands of a record signal and reproduced signal in the encoding apparatus in Fig. 1 in comparison with the conventional bands; Figs. 11A to 11D are graphs for explaining the meaning of the product of the spectrum of the code and C/N; Fig. 12 is a block diagram exemplifying a conventional digital magnetic recording/reproducing apparatus. Reference will now be made in detail to the presently preferred embodiments of the invention as illustrated in the accompanying drawings, in which like reference characters designate like or corresponding parts throughout the several drawings. The first embodiment of the present invention will now be explained referring to the accompanying drawings. Fig. 1 is a block diagram illustrating the embodiment of the present invention as applied to a magnetic recording/reproducing apparatus. Reference numeral "1" denotes an input terminal from which an analog record signal such as a video signal of an HDTV system is input. An A/D converter 2 converts the input analog video signal into an 8-bit digital signal. A mapping converter 3 assigns the input digital signal to two groups of 12-bit code words, one group in one-to-one correspondence and the other in one-to-two correspondence, before encoding. A CDS calculator 4 calculates CDS values of all the words coded by the mapping converter 3. A code selector 5 selects a code word to be output after being coded by the mapping converter 3 at the one-to-two relation. A margin bit generator 6 generates a margin bit in a direction to reduce DSV value of the code word sent from the mapping converter 3 or a fixed margin bit. A DSV calculator 7 calculates the accumulated DSV values of code words sent from the mapping converter 3. A parallel/serial converter 8 performs parallel/serial conversion in such a way that the code word from the mapping converter 3 is converted into a serial signal and a margin bit output from the margin bit generator 6 is inserted into the input code word to perform a parallel/serial conversion. A sync signal generator 9 generates a sync signal by which the parallel/serial converter 8 is activated. An NRZI (Non-Return to Zero Inversion) modulator 10 performs NRZI modulation on the serial signal sent from the parallel/serial modulator 7. A VTR section 11 records a record signal input from the NRZI modulator 10 on a magnetic tape T. A NRZI demodulator 12 performs NRZI demodulation on a signal reproduced by the VTR section 11. A sync signal detector 13 detects a sync signal from the demodulated reproduced signal and supplies the sync signal to a serial/parallel converter 14. The serial/parallel converter 14 converts the input serial signal into a parallel signal based on the sync signal. A reverse mapping converter 15 performs reverse mapping on the code word output from the serial/parallel converter 14, and converts that word into a normal digital signal. A D/A converter 16 converts a digital signal into an analog signal. Reference numeral "17" denotes an output terminal where a reproduced analog video signal is output. The mapping converter 3 and the reverse mapping converter 15 perform their conversions in the totally opposite processes. The operation of this embodiment will now be described. The A/D converter 2 converts a color video signal from the input terminal 1 into a digital signal of 8 bits per pixel. The mapping converter 3 encodes an input digital signal to a 12-bit word. The minimum number of "0s" between the codes "1," which indicate change points based on an NRZI rule and correspond to magnetism inversion, is one. 12-bit code data coded by the mapping converter 3 is regarded as one word. The color video signal input from the input terminal 1 is converted into an 8-bit digital signal by the A/D converter 2 as shown in Figs. 2A and 2B, and is sent to the mapping converter 3. By means of, for example, a ROM (table) to be described later, the mapping converter 3 assigns the received 8-bit digital signal to two groups of 12-bit code words in one-to-one correspondence and one-to-two correspondence as shown in Fig. 2C before encoding. The CDS calculator 4 calculates the CDS values of all the code words coded by the mapping converter 3 by, for example, the ROM (table), and sends the calculation result to the code selector 5 and the margin bit generator 6. The DSV calculator 7 calculates the DSV values of all code words from the mapping converter 3 by means of, for example, an adder, and supplies the calculation result to the code selector 5 and the margin bit generator 6. It is supposed that the DSV calculator 7 internally performs NRZI modulation on the input code word, and calculate the modulated DSV value. The mapping converter 3 produces one code word in one-to-one correspondence and two code words in one-to-two correspondence with respect to the input digital signal. For a single code word, the mapping converter 3 sends that code word to the parallel/serial converter 8 and the DSV calculator 7. The margin bit generator 6 determines a margin bit ("1" or "0") to be inserted into the code word output from the mapping converter 3. To describe more specifically, the margin bit generator 6 receives the CDS value of the code word, sent from the mapping converter 3, from the CDS calculator 4 and the accumulated DSV value from the DSV calculator 7. The margin bit generator 6 then generates a margin bit and sends it to the parallel/serial converter 8 so that a margin bit in the direction of reducing the DSV value calculated by the DSV calculator 7 is inserted after the rear end of the code word output from the mapping converter 3. The parallel/serial converter 8 converts the code word received from the mapping converter 3 into a serial signal, and inserts the margin bit produced from the margin bit generator 6 to the serial signal as shown in Fig. 2C, sending the acquired signal of 13 bits in total to the NRZI modulator 10. Given that one bit unit shown in Fig. 2C is a detect window width Tw, the minimum magnetism inversion time Tmin is 2Tw (< 2 data clocks (T)). The maximum magnetism inversion time Tmax is 8 data clocks (8T) or shorter. When the mapping converter 3 produces two code words from the input digital signal, the code selector 5 receives the CDS values of the two code words from the CDS calculator 4 and the DSV values up to now from the DSV calculator 7. The code selector 5 determines which code word is output when the following DSV value calculated by the DSV calculator 7 is reduced, and selects a code word whose DSV value becomes smaller and sends it to the parallel/serial converter 8. The parallel/serial converter 8 converts the received code word into a serial signal, and sends that signal to the NRZI modulator 10. The VTR section 11 records a modulation signal (same as the record signal), sent from the NRZI modulator 10, on the magnetic tape T. In this case, one margin bit, which is generated from the margin bit generator 6, is inserted into the serial signal in the parallel/serial converter 8. The record signal therefore has 13 bits. Although not explained above, an error correction signal, etc. are of course added by a circuit (not shown) to the record signal recorded on the magnetic tape T in the VTR section 11. A signal reproduced by the VTR section 11, after being demodulated by the NRZI demodulator 12, is sent to the serial/parallel converter 14 and the sync signal detector 13. The sync signal detector 13 detects a sync signal from an input signal, and supplies the sync signal to the serial/parallel converter 14. Upon reception of the sync signal, the serial/parallel converter 14 specifies the position of the code, and converts the input reproduced serial signal into a parallel signal. The word reproduced in this manner is input to the reverse mapping converter 15. The reverse mapping converter 15 performs reverse conversion on the received code word into a normal 8-bit digital data, and outputs this data to the D/A converter 16. The D/A converter 16 converts the received digital signal into an analog video signal, and sends this video signal to the output terminal 17. The specific operations of the individual components in this embodiment shown in Fig. 1 will now be described in order. First, the coding system of the mapping converter 3 will be explained referring to Fig. 3. In Fig. 3, the first column on the left side shows the number of codes to be used for coding input data, and the second column shows input data. The third column presents code words corresponding to the input data. In this embodiment, 8-bit input data "0" to "140" out of those "0" to "255" are coded in one-to-one correspondence and the code words have P1=P12=0. Input data "141" to "228" correspond to two code words; one code word has P1=1 and P2=P12=0, and the other has P1=P11=0, and P12=1. The remaining input data "229" to "255" correspond to two code word; one code word has P1=P12=1, and P2=P11=0, and the other also has P1=P12=1, and P2=P11=0. As shown in Fig. 3, P1=P12=0 is assigned to the code word in one-to-one correspondence with input data. Accordingly, 144 pieces of code data can be obtained at the maximum as shown in the corresponding portion in Fig. 4. Considering the maximum number of continuations of the same bit in a code, however, 141 pieces of code data are used instead of 144 pieces in parentheses in Fig. 4. The table in Fig. 4 will be now explained. The first column on the left side shows types of code data and total number of codes, and the second column shows the number of change points in code data. The third column shows how many pieces of code data corresponding to the CDS values of the code data are present, and the fourth column shows the number of codes for each case. For example, it is indicated that there are two code words each of which has P1=P12=0 and has two change points with the CDS value of "-4." In Fig. 3, P1=1 and P2=P12=0, P1=P11=0 and P12=1, or P1=P12=1 and P2=P11=0 is assigned to the code words in two-to-one correspondence with input data. The code words in this case are also acquired as shown in the corresponding portions in Fig. 4. As described above, data input to the mapping converter 3 is assigned to two groups of code words in one-to-one correspondence and in one-to-two correspondence as shown in Fig. 3 before being coded, and the values of the individual code words are determined in advance. The mapping converter 3 can therefore be designed by storing the correspondence between the data and the code words as shown in Fig. 3 in the ROM (table). The reason for assigning data to two groups of code words in one-to-one correspondence and in one-to-two correspondence before coding is to control the DSV value to be described later by the optimal number of bits. A supplemental description will be given of input data encoded to two code words by the mapping converter 3. The absolute values of the two code words are expressed by a and @, respectively. The positive CDS values are indicated as +a, and the negative ones are as -a. Further, the CDS values of the code words with the even number of change points are represented as a+, and those with the odd number of change points are as a-. In this embodiment, therefore, the combinations of two code words corresponding to one piece of input data is determined as (1) +a-, -@+ (2) +a+, -@-. These combinations are optimal for controlling the DSV value, but other combinations are also available. Fig. 4 shows the examples of combinations (1) and (2). "+a-" in (1) corresponds to the code word, in the case of P1=P11=0 and P12=1, which has the CDS value of "+6" and the three change points. "-@+" in (1) corresponds to the code word, in the case of P1=1 and P2=P12=0, which has the CDS value of "-4" and four change points. "+a+" in (2) corresponds to the code word, in the case of P1=P11=0 and P12=1, which has the CDS value of "+4" and four change points. "-@-" in (2) corresponds to the code word having P1=1 and P2=P12=0, which has the CDS value of "-6" and three change points. In this embodiment, only code word with P1=P12=0 has one-to-one correspondence with input data. It is however possible that code words with P1=1 and P2=P12=0, or P1=P11=0 and P12=1 can have one-to-one correspondence with the input data. The margin bit will be "1" or "0" for code word with P1=P12=0. Fig. 5 is a diagram for explaining a method for determining a margin bit by the margin bit generator 6 in the case where two code words output from the mapping converter 3 continue. The lowest portion in the diagram shows a Y 1 word, and the left side portion indicates a Y 2 word. The Y 1 and Y 2 words, classified by coding types, define matrix regions. The margin bit can be "1" or "0," in a shaded region A. By selecting the margin bit "1" or "0," the DSV value calculated by the DSV calculator 7 can be controlled in the direction of reduction. The margin bit is fixed to "0" in shaded regions D, G and J. By the code selector 5 selecting the even number or odd number of change points of the code word in the individual region, it is possible to control the DSV value of the DSV calculator 7 in the reduction direction. Further, in double-shaded regions, B and C, E and F, and H and I, if one of the two code words and a margin bit is selected, the DSV value can be controlled in the reduction direction. The actual control operation in each region in Fig. 5 will be described in more details referring to Figs. 6 through 8. Before going into the description, it is to be noted that parameters are to be set as follows. "a" and "b" indicate absolute values of the CDS values of a code of a Y1 word and a Y2 word shown in Fig. 5; a ≥ 0 and b ≥ 0. The positive and negative signs that come before those "a" and "b" indicate the polarities of the CDS values, "+" indicating the direction to increase the CDS value and "-" the direction to decrease it. Further, the signs "+" and "-" are determined on the premise that the direction before the initial bit of a code is in the "+" direction. The positive sign that comes after "a" and "b" indicates that the number of change points in a code word, or the number of "1" of an NRZI rule is an even number, and the negative sign indicates the number of change points in the code word is an odd number. In this case, the direction is the opposite to the one before the initial bit of the code word. The code selector 5 in Fig. 1 selects a code word whose DSV value calculated next by the DSV calculator 7 becomes small with respect to the result of conversion done by the mapping converter 3, and the margin bit generator 6 also in Fig. 1 generates a margin bit to reduce the DSV value and inserts it into an output code word. The principle of the operations of those circuits 5 and 6 will be explained referring to Figs. 5, 6, 7A, 7B and 8. Fig. 5 illustrates patterns which two code words, Y1 and Y2, can take. The DSV control operations of the code selector 5 and margin bit generator 6 are executed based on the patterns. The pattern (A) in Fig. 5 is for the case where the Y1 word has P1=P12=0, and the Y2 word has P1=P12=1 and P2=P11=0. In this case the margin bit is fixed to "0" as shown in (D) in Fig. 6. In this case the absolute value of the DSV value can also be reduced using the difference in CDS value of the Y2 word by the same operation as shown in Fig. 7B. The patterns (E) and (F) in Fig. 5 are for the case where the Y1 word has P1=P11=0 and P12=1 or P1=1 and P2=P12=0, and the Y2 word has P1=P12=0. In this case, the absolute value of the DSV value can also be reduced using the margin bit by the same operation as shown in Fig. 7A when P1=1 and P2=P12=0 are selected as shown in (E) in Fig. 6. When "0" is selected for the margin bit and P1=P11=1 and P2=1 or P1=1 and P2=P12=0 are selected for the Y1 word as shown in (F) in Fig. 6, the DSV value varies as shown in Fig. 8 depending on the difference in the CDS value of the Y1 word and the number of change points of a code, so that the code word to reduce the DSV value is selected using this change. If code words of the same classification, such as +a+ and +@+, which have the same CDS polarity and the same odd number and even number of change points are combined as a combination of two code words of the Y1 word, there may be a pattern in which the DSV value diverges. If code words of different classifications, such as +a+ and -@-, or +a- and -@+, are combined, however, the DSV values of the two words differ from each other. Selecting one of the words can therefore reduce the DSV value. In this example, since +a+ and -@- or +a- and -@+ are combined, either a+b or -(a+b) is selected as the DSV value, or a-b or -(a-b) is selected, making it possible to always reduce the DSV value. The pattern (G) in Fig. 5 is for the case where the Y1 word has two types of code words having P1=P12=1 and P2=P11=0, and the Y2 word has P1=P12=0. This case is shown in (G) in Fig. 6; the same as can be said to (F) in Fig. 6 is true of this case which has the same operation as shown in Fig. 8. The pattern (H) in Fig. 5 is for the case where the Y1 word has P1=P11=0 and P12=1 or P1=1 and P2=P12=0, and the Y2 word has P1=P11=0 and P12=1 or P1=1 and P2=P12=0. In this case, since "1" or "0" is selectable for the margin bit when P1=1 and P2=P12=0 are selected for the Y1 word and P1=P11=0 and P12=1 are selected for the y2 word, the absolute value of the DSV value can also be reduced by the same operation as shown in Fig. 7B. The pattern (I) in Fig. 5 is for the case where the Y1 word has P1=P11=0 and P12=1 or P1=1 and P2=P12=0, and the Y2 word has P1=P11=0 and P12=1 or P1=1 and P2=0. With the margin bit set to "0," the pattern becomes as shown in (I) in Fig. 6, and the possible operation then is as shown in Fig. 9. In this example, there are four possible DSV values of the Y1 and Y2 words, a+b, a-b, -a+b and -a-b, from which the word that sets the absolute value of the DSV small is to be selected. The pattern (J) in Fig. 5 is for the case where the Y1 word can have P1=P11=0 and P12=1 or P1=1 and P2=P12=0, and the Y2 word can have two types of code words with P1=P12=1 and P2=P11=0, or the case where the Y1 word has P1=P12=1 and P2=P11=0, and the Y2 word can have P1=P11=1 and P12=1, or P1=1 and P2=P12=0, or the case where the Y1 word has P1=P12=1 and P12=P11=0, and the Y2 word can have P1=P12=1 and P2=P11=0. All of those cases are the same as shown in (I) in Fig. 5, and the operation for the cases is the same as shown in Fig. 7B, making it possible to suppress down the absolute value of the DSV value. The structure shown in Fig. 1 can cope with the case where DSV value can be controlled by selecting one of code words converted by the mapping converter 3, and the DSV value can be controlled by inserting the margin bit of "1" or "0" into the selected and output code word. According to this embodiment, input data is assigned to two groups of code words in one-to-one correspondence and one-to-two correspondence by the mapping converter 3 before encoding and one of the code words converted in one-to-two correspondence is selected as a record signal, or a margin bit of "0" or "1" is inserted into the code word output from the mapping converter 3 to reduce the DSV value, thereby preventing the DSV value of the record code word from diverging and making it finite, and reducing its absolute value. Further, since the input data is converted into a 12-bit code word as shown in Fig. 2C by the mapping converter 3, the maximum magnetism inversion time Tmax and minimum magnetism inversion time Tmin become as shown in Fig. 2D; in particular, Tmin = 2Tw (> T). It is also possible to set the maximum magnetism inversion time Tmax to be equal to or smaller than 6.77T (= l1*Tw=11*S/13*T) or equal to or smaller than 8T at maximum, thus narrowing the low-frequency side band as shown Fig. 10A. Most of the DC component of the record signal and the low frequency component therearound can therefore eliminated to reduce the error rate at the reproducing time, thus improving the image quality. Further, since code words are acquired in the above manner, the density ratio DR (Tmin/T) can be increased by 23% as compared with the prior art. It is therefore possible to reduce the high frequency component of the record signal by that amount as shown in Fig. 10A, narrowing the high-frequency side band of the record signal. Since in general, the characteristic of the recording/reproducing magnetic heads of the VTR section 11 rapidly attenuates in the high frequency range and high frequency component has a large loss, the reduction in the high frequency component of the record signal decreases the error rate, likewise improving the image quality. The required band in this embodiment therefore becomes 11 MHz to 60.9 MHz as shown in Fig. 10A, narrower than that of the conventional system, 0 to 75 MHz, shown in Fig. 10B, thus permitting the recording/reproducing magnetic heads to be used efficiently and in the favorable part of the characteristic to improve the image quality at the recording/ reproducing time. As described above, the encoding apparatus according to the embodiment can suppress the DSV value down to be finite, so that when used particularly in a magnetic recording/reproducing apparatus, it can contribute to improving the image quality at the recording/reproducing time by reducing the maximum magnetism inversion time and increasing the density ratio. According to the present invention, a magnetic recording/reproducing apparatus encodes an m-bit digital signal to a code word which is recorded on/reproduced from a magnetic tape. The magnetic recording/reproducing apparatus comprises encoding means for encoding the m-bit digital signal to an n-bit code word in one-to-one correspondence or in one-to-two correspondence, DSV calculating means for calculating the DSV value of the code words output from the encoding means, CDS calculating means for calculating the CDS values for all the code words encoded by the encoding means, code selecting means for selecting one of the two code words corresponding to one piece of input data so that the next accumulated DSV value to be calculated by the DSV calculating means will be decreased based on the DSV value calculated by the DSV calculating means and the CDS value calculated by the CDS calculating means, and margin bit inserting means for generating a margin bit and inserting it into the code word output from the encoding means so that the next DSV value to be calculated by the DSV calculating means will be decreased based on the DSV value from the DSV calculating means and the CDS value from the CDS calculating means, whereby the code word output from the encoding means is recorded on a magnetic tape. In the magnetic recording/reproducing apparatus according to the present invention, the encoding means encodes the m-bit digital signal to an n-bit code word in one-to-one correspondence or in one-to-two correspondence. The DSV calculating means calculates the DSV value of the code word output from the encoding means. The CDS calculating means calculates the CDS values for all the code words encoded by the encoding means. The code selecting means selects one of the two code words corresponding to one piece of input data so that the next DSV value to be calculated by the DSV calculating means will be decreased based on the DSV value calculated by the DSV calculating means and the CDS value calculated by the CDS calculating means. The margin bit inserting means generates a margin bit and inserting it into the code word output from the encoding means so that the next DSV value to be calculated by the DSV calculating means will be decreased based on the DSV value from the DSV calculating means and the CDS value from the CDS calculating means. The code word output from the encoding means is recorded on a magnetic tape.

Claims: An encoding apparatus which converts an input digital signal into a predetermined code word, in the code word, the minimum number of "Os" between the codes "1" which indicate change points based on an NRZI rate and correspond to magnetism inversion, is one, said code word having a "1"-bit state and a "0"-bit state corresponding to normal and reverse states of the digital modulation signal, said encoding apparatus comprising: encoding means (3) for separating he input digital signal including m bits, m being a positive integer into a first group and a second group predetermined with respect to 2 m pieces of data allowable for said input digital signal, and encoding each piece of data in said first group to a single code word including n bits, n being a positive integer and larger than m in one-to-one correspondence and encoding each piece of data in said second group to two code words each including n bits in one-to-two correspondence; code word digital sum (CDS) calculating means (4) for calculating a CDS value for each of said words output from said encoding means (3); digital sum variation (DSV) calculating means (7) for calculating an accumulated DSV value of said individual words output from said encoding means (3) ; code selecting means (5) for, when said two n-bit code words are output from said encoding means (3), selecting that one of said code words which decreases a next accumulated DSV value to be calculated by said DSV calculating means (7), in accordance with said CDS value from said CDS calculating means (4) and said accumulated DSV value from said DSV calculating means (7); margin bit inserting means (6) for generating a predetermined margin bit which decreases a next accumulated DSV value to be calculated by said DSV calculating means (7), in accordance with said CDS value from said CDS calculating means (4) and said accumulated DSV value from said DSV calculating means (7), and inserting said margin bit in said single n-bit code word output from said encoding means and said one code word selected by said code selecting means (5) ; and transfer means (8-10) for transferring an encoded DSV code word including a total of n+1 bits resulting from the insertion of said predetermined margin bit by said margin bit inserting means (6), characterized in that said encoding means (3) includes: means for assigning "0" to both first and last bit positions of the single n-bit code word when encoding is executed in one-to-one correspondence; and means for assigning "1" and "0", "0" and "1" to first and last bit positions of each of the two n-bit code words when encoding is executed in one-to-two correspondence. An encoding apparatus according to claim 1, characterized in that said positive integer m is 8 and said positive integer n is 12. An encoding apparatus according to claim 2, characterized in that said encoding means (3) includes means for encoding data "0" to "140" as said first group, out of "0" to "255" which said input digital signal can have, and encoding data "141" to "255" as said second group.

Inventors: NIIMURA KAZUHARU, NIIMURA, KAZUHARU, Niimura, Kazuharu, c/o Intellectual Prop. Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: H03M5
IPC codes: H03M5, H04N9, G11B20