PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS

Abstract: A precursor comprising a metal 2-ethylhexanoate in a xylenes solvent is applied (P7) to an integrated circuit wafer (1, 20, 50). The wafer is baked (P9) to dry the precursor, annealed (P11) to form a layered superlattice material (12, 30, 60) on the wafer, then the integrated circuit (70) is completed. If the metal is titanium, the precursor comprises titanium 2-methoxyethoxide having at least a portion of its 2-methoxyethoxide ligands replaced by 2-ethylhexanoate. If the metal is a highly electropositive element, the solvent comprises 2-methoxyethanol. If the metal is lead, bismuth, thallium, or antinomy, 1 % to 75 % excess metal is included in the precursor to account for evaporation of the oxide during baking and annealing. The process provides ferroelectric devices having extremely low fatigue and high dielectric constant devices that do not degrade easily.

Description: PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS BACKGROUND OF THE INVENTION 1. Field of the Invention The invention in general relates to the fabrication of layered superlattic materials, and more particularly to fabrication processes that provide low fatigu ferroelectric and reliable high dielectric constant integrated circuit devices that ar unusually resistant to degradation. 2. Statement of the Problem In 1959 G.A. Smolenskii, V.A. Isupov, and A.I. Agranovskaya discovered new class of ferroelectric materials which they recognized had a layered perovskit structure. See Chapter 15 of the book. Ferroelectrics and Related Materials, ISS 0275-9608, (V.3 of the series Ferroelectrics and Related Phenomena, 1984) edite by G. A. Smolenskii, especially sections 15.3 -15.7. These and other relate materials have recently been recognized as "layered superlattice" materials by th present inventors. See copending PCT application Serial No. , which is incorporated herein by reference. Up to now, these layered superlattice materials have not been considered as being suitable use in integrated circuits or ferroelectric memories, nor have they been recognized as useful high dielectric constant materials. An attempt has been made to use two of the layered ferroelectric materials, bismuth titaπate (Bi Ti 3 0 12 ) and barium magnesium fiuoride in a switching memory application as a gate on a transistor. See "A New Ferroelectric Memory Device, Metal-Ferroelectric- Semiconductor Transistor", by Shu-Yau Wu, IEEE Transactions On Electron Devices. August 1974, pp. 499 - 504, which relates to the Bi 4 Ti 3 0 12 device, and the article "Integrated Ferroelectrics" by J.F. Scott, C.A. Paz De Araujo, and L.D. McMillian in Condensed Matter News. Vol. 1 , No. 3, 1992, pp. 16 - 20, which article is not prior art to this disclosure; However, Section IIB of the article discusses experiments with ferroelectric field effect transistors (FEFETs), the exact date of which experiments is not presently known to the inventors. Both these attempts failed: In the case of the Bi 4 Ti 3 0 12 device, the ON state decayed logarithmically after only two hours, and in the case of the BaMgF 4 device, both states decayed exponentially after a few minutes. See "Memory Retention And Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistors", by S. Y. Wu, Ferroelectrics. 1976 Vol. 11 , pp. 379 -383. It is believed that a key reason why none of the layered superlattice materials have been successfully used in a ferroelectric, high dielectric constant, or other practical application is that the processes of preparing the materials and fabricating devices from the materials that have been employed up to now have not been capable of producing high quality specimens of the materials. Prior to about 1988, the vast majority of ferroelectric thin films were made by either RF sputtering or chemical vapor deposition (CVD). See "Metalorganic Chemical Vapor Deposition of PbTiO 3 Thin Films", by B.S. Kwak, E.P. Boyd, and A. Erbil, Applied Physics Letters, Vol. 53, No. 18, October 31, 1988, pp. 1702 -1704. About 1988, several other approaches began to be developed. The Kwak paper just cited discloses one such development, namely metalorganic chemical vapor deposition, or MOCVD. A recent paper discloses the fabrication of a thin film of Bi 4 Ti 3 O 12 , a layered superlattice material, by spin coating sol-gel onto a substrate and annealing. Joshi, P.C. et al., "Structural and Optical Properties of Ferroelectric Thin Films By Sol-gel Technique," Appl. Phys. Lett., Vol 59, No. 10, Nov. 91. The process of applying precursor solutions comprising organic compounds of the elements of the desired thin film in solution to substrates, and then heating the precursor on the substrate to form the film, has been used for many years in manufacturing and is known to be a simple process. However, until recently, all the manufactured products the process has been applied to have been large objects, such as windshields, in which the microscopic properties of the films have not been critical. It was generally thought that since an inherent part of the process is that significant quantities of organic materials must be disassociated from the elements of the future thin film and evaporated from the film as it dries, therefore the resulting film must have a relatively porous structure. About the same time as the MOCVD research mentioned above, the use of the precursor application/heating process was being developed as a process was to produce inks, such as for ink jet or screen printing, for forming conductors, resistors, and dielectric films on circuit boards or other substrates such as metal foil or glass. In this process, films of metal oxides were fabricated by dissolving a carboxylate of the metal in a solvent, such as xylene, spinning, dipping the a stoichiometric mixture of the solution on a substrate to form a thin film of liquid, and drying and firing the film to remove the solvents and organics and form the metal oxide thin film. See "Synthesis of Metallo- organic Compounds for MOD Powers and Films", G. M. Vest and S. Singaram, Materials Research Society Symposium Proceedings. Vol. 60, 1986 pp. 35 -42. Specifically, this paper discloses the reaction of a metal compound, such as barium, bismuth, calcium, lead, strontium, zirconium, ruthenium, and tin compounds with either neodecanoic acid or 2-ethylhexanoic acid to form a metal carboxylate, such as bismuth 2-ethylhexanoate, which is dissolved in xylene to produce a precursor solution from which a thin film of a simple metal oxide, such as Bi 2 0 3 , is produced. In one instance these processes were used to produce thin ferroelectric thin films of PbTiO 3 (not a layered superlattice material), and since the processing conditions for making the films is compatible with silicon technology, it was postulated that it would be possible to use the process to make capacitors, detectors, and sensors on chips. See "PbTiO 3 Thin Films From Metalloorganic Precursors", Robert W. Vest and Jiejie Xu, IEEE Transactions On Ultrasonics, Ferroelectrics, and Frequency Control, Vol 35, No. 6, November 1988, pp. 711 - 717. It is also known that these processes can be used to form thin films of other ceramics and superconductors. W. W. Davidson, S. G. Shyu, R. D. Roseman, and R. C. Buchanan, "Metal Oxide Films from Carboxylate Precursors", Materials Research Society Symposium Proceedin g s. Vol. 121, pp. 797-802 (1988). Concurrently with the development of the MOCVD and metal carboxylate processes for printing purpose summarized above, experiments were performed to explore the use of the same or similar precursors as used in the above process to produce ferroelectric thin films by spinning the precursor onto a substrate and drying it. The experiments showed the preferred precursors to be the metal alkoxides and acetates. See United States Patent No. 5,028,455 issued to William D. Miller et al. and the article "Process Optimization and Characterization of Device Worthy Sol-Gel Based PZT for Ferroelectric Memories", in Ferroelectrics. Vol 109, pp. 1-23 (1990). While the Miller patent mentions one metal carboxylate, lead tetra-ethylhexanoate, as a possible precursor, it was rejected as less desirable since the large organic group was thought to result in more defects in the final film. Further, the fact that the metal carboxylate processes were developed to produce inks such as for ink jet or screen printing, while the metal alkoxide and acetate processes were developed specifically for ferroelectric materials, also argued against the use of the metal carboxylates in ferroelectric integrated circuit applications. In spite of the considerable research outlined above, none of the thin films made by the above processes, including the thin films of PbTiO 3 made by Vest or the thin films of PZT made by Miller, produced reliable, low fatigue ferroelectrics, and in particular, none produced reliable, low fatigue layered superlattice thin films. 3. Solution to the Problem The invention solves the above problems by providing a standardized process for making high quality thin films of a layered superlattice material. The microscopic quality of the film provides excellent properties in integrated circuits. The process is simple and compatible with conventional integrated circuit materials and processes. The process starts with preparing a precursor solution containing each of the metals in the desired thin film compound. For most metals, a metal carboxylate with medium-length ligands is the preferred precursor compound. A metal 2- ethylhexanoate works for most metals. If the metal is titanium, the precursor may comprise titanium 2-methoxyethoxide having at least a portion of its 2- methoxyethoxide ligands replaced by 2-ethylhexanoate. The precursor is dissolved in a solvent having a boiling point greater than 10°C. A xylenes solvent works for most metals. For highly electropositive elements, the solvent includes 2-methoxyethanol or n-butyl acetate. The precursor is preferably applied to the integrated circuit wafer by spin coating or using a mist deposition process. Optionally, the coated wafer is dried by heating it at about 150°C for a few minutes- It is then baked at about 250°C for from 30 seconds to a few minutes. The wafer is then annealed in an oxygen furnace at about 700°C for about an hour. Sev¬ eral, coating, drying, baking and annealing steps may be repeated for thicker films. Alternatively, a sputtering target may be prepared in the above manner and the material deposited by sputtering it onto the integrated circuit. If the metal is lead or bismuth, 1% to 75% excess metal is included in the precursor to account for evaporation of the oxide during baking and annealing. The best results were obtained for 50% excess bismuth. If sputtering is used, even higher excess amounts may be required for best results. Extremely high quality thin films have been made by the above process. For example, strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ) has been made in thin films suitable for use in integrated circuits and having a polarizability, 2Pr, of 24 microcoulombs/cm 2 and showing less than 5% fatigue after 10 10 cycles, which is equivalent to 10 years use in a typical integrated circuit switching device. As another example, barium bismuth tantalate (BaBi 2 Ta 2 O 9 ) having a dielectric constant of 166, measured at 1 Megahertz with a V osc of 15 millivolts, and a leakage current of 7.84 X 10 '8 amps/cm 2 at a field of 200 KV/cm has been made in thin films of less than 2000 A, which are suitable for use in integrated circuits. The development of a process that consistently produces high quality thin films has lead to the discovery that a class of materials, called layered superlattice materials herein, have remarkable properties. Layered superlattice materials having high polarizabilities, extremely low fatigue when switched over long periods in integrated circuits, high dielectric constants, and many other previously unknown electrical properties have been fabricated. Now that process of making high quality layered superlattice materials and reliable integrated circuits utilizing the layered superlattice materials has been discovered, this process can be applied to creating numerous other integrated circuits and other devices utilizing these materials and many other related materials. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a flow chart showing the preferred embodiment of a process for preparing a thin film of a layered superlattice material according to the invention; Fig. 1 B is a flow chart showing an alternative preferred embodiment of the precursor solution formation portion of the process of Fig. 1A; Fig. 1C is a flow chart showing an another alternative preferred embodiment of the precursor solution formation portion of the process of Fig. 1A; Fig. 2A is a top view of a silicon wafer on which thin film capacitors according to the invention are shown greatly enlarged; Fig. 2B is a portion of the cross-section of Fig. 2A taken through the lines 2B - 2B, illustrating a thin film capacitor device having buffer layers according to the invention; Fig. 2C is a cross-sectional illustration of a portion of a thin film capacitor according to the invention; Fig. 2D is a cross-sectional illustration of a portion of an integrated circuit fabricated utilizing the process of the invention; Fig. 3 illustrates the process of sputtering a thin film of a layered superlattice material according to the invention; Fig. 4C shows a graph of P r ' and P* versus number of hysteresis cycles for a hysteresis curve of a device as shown in Fig. 2B having a layer of Bi 4 Ti 3 O 12 between buffer layers of SrTiO 3 , illustrating the low fatigue of the material; Fig. 6E shows hysteresis curves at 2, 4, 6, 8, and 10 volts for a ferroelectric capacitor as shown in Fig. 2C utilizing SrBi 2 Ta 2 O 9 as the ferroelectric material; Fig. 16 shows a hysteresis curve for a sample of SrBi 2 Ta 2 O 9 after 10 12 cycles superimposed on an initial hysteresis curve for the same sample; and Fig. 9 is a graph of the logarithm of the DC leakage current versus applied field for a capacitor as shown in Fig. 2C utilizing BaBi 2 Ta 2 O 9 as the high dielectric constant material. DESCRIPTION OF THE PREFERRED EMBODIMENT The processes of the invention is simple and relatively inexpensive, and thus lends itself to large scale manufacturing. The end product, the thin films, are of high quality. Further, the process is standardizable and produces a high yield. The process is compatible with conventional integrated circuit technology, such as silicon technology. An important factor in making the process standardizable is the fact that the precursor solutions have a relatively long shelf life. This has three aspects: first the precursors for the individual metals, such as strontium, tantalum, etc. have a long shelf life so that one can readily select and mix solutions to produce any desired layered superlattice material; second, there is a common solvent for all the precursors, so that they can be readily combined; third, the mixed precursor for a given layered superlattice material, such as strontium bismuth tantalate, has a relatively long shelf life so that it can be made ahead of time in volume and used as needed. The above factors conflict, and thus the discovery of such a process was inherently difficult. The standardized process according to the invention is one by which high quality thin films of any layered superlattice material can be easily made from precursors having a long shelf life. The basic preferred process for fabricating layered superlattice thin films as may be incorporated into a integrated circuit is illustrated in Figs. 1A, 1B, and 1C. Electrical devices that have been fabricated utilizing the process of the invention are shown in Figs. 2A through 2D. We shall first describe the electrical devices briefly, and then describe the process of the invention, relating it to the devices. An exemplary wafer 1 on which test samples of capacitor devices according to the invention have been fabricated is shown in Fig. 2A. It should be understood that the Figs. 2A, 2B, and 2C depicting capacitor devices and Fig. 2D depicting an integrated circuit device are not meant to be actual plan or cross-sectional views of any particular portion of an actual capacitor or integrated circuit device, but are merely idealized representations which are employed to more clearly and fully depict the structure and process of the invention than would otherwise be possible. Fig. 2B shows a cross-section of the wafer 1 of Fig. 2A taken through the line 2B - 2B. Fig. 2C depicts a similar cross-section taken through a wafer similar to that of Fig. 2A but having a different layered structure. Referring to Figs. 2A and 2B, the wafer 1 preferably comprises a P-type silicon substrate 2 on which an approximately 5000 A silicon dioxide insulating layer 4 has been wet grown. A thin layer 6 of titanium metal has been deposited on the silicon dioxide 4, preferably by sputtering in situ, and a 2000 A thick electrode of platinum has been deposited on the titanium 6, preferably by sputtering in situ. By "in situ" is meant that both the titanium and the platinum are sputtered without breaking vacuum. The titanium diffuses into the silicon dioxide and platinum and assists the platinum 8 in adhering to the silicon dioxide 4, and is optional. A buffer layer 10, is deposited on the platinum electrode 8, followed by a layer 12 of a layered superlattice material according to the invention, followed by another buffer layer 14, via processes that will be described in detail below. Another 2000 A layer of platinum is deposited on the buffer layer 14. The wafer 1 is annealed, patterned with a photo-mask process, and etched down to the electrode layer 8 to produce rectangular capacitor devices 17A.17B, etc. (Fig. 2A) of various sizes separated by large areas of the electrode 8. The size of the devices 17A, 17B, etc. is greatly exaggerated in Fig. 2A. Each device 17A, 17B, etc. may be tested by connecting one lead of the test device to the platinum electrode layer 8 and contacting the other electrode layer 16 of the particular device 17A, 17B, etc. with a fine probe connected to the other lead of the test device- Devices having the cross-sectional structure of Fig. 2C are similarly fabricated except that the two buffer layers 10, 12 are not deposited. That is, the wafer of Fig. 2C includes a silicon substrate 22, a silicon dioxide layer 24, an optional titanium layer 26, a first platinum electrode 28, a layered superlattice material layer 30, and a second platinum electrode 32. The wafer 20 is similarly patterned to form capacitor devices of various sizes having the cross-section shown in Fig. 2C. The fabrication of exemplary devices of the types shown in both Figs. 2B and 2C will be described in detail in the examples below. A portion of an integrated circuit wafer 50, i.e. a ferroelectric capacitor-based memory cell 70, that may be formed utilizing the process of the invention is shown in Fig. 2D. The wafer 50 includes a silicon substrate 51, field oxide areas 54, and two electrically interconnected electrical devices, a transistor 71 and a ferroelectric switching capacitor 72. Transistor 71 includes a gate 73, a source 74, and a drain 75. Capacitor 72 includes first electrode 58, ferroelectric layered superlattice material 60, and second electrode 77. Insulators, such as 56, separate the devices 71 , 72, except where drain 75 of transistor 71 is connected to first electrode 58 of capacitor 72. Electrical contacts, such as 47A and 78 make electrical connection to the devices 71, 72 to other parts of the integrated circuit 70. A detailed example of the complete fabrication process for an integrated circuit memory cell as shown in Fig. 2D is given in United States Patent Application Serial No. 919,186, which is incorporated herein by reference. The detailed process for fabricating the layered superlattice ferroelectric layer 60 is given below. The preferred process for fabricating a layered superlattice material in which there are three metallic elements is shown in Fig. 1A. The process begins by the formation of a liquid precursor. In each of steps P1 through P3 a metal compound is reacted with a carboxylic acid to form a metal carboxylate, which is dissolved in a solvent. The preferred carboxylic acid is one having a medium-length ligand, such as 2-ethylhexanoic acid, though others may be used. Preferably the solvent's boiling point should be within the range 110°C - 170°C. The preferred solvents are alcohols, such as 2-methoxyethanol, aromatic hydrocarbons, such as the xylenes, and esters, such as n-butyl acetate, though any of the solvents in Table A may be used. TABLE A Solvent Boiling Point n-Butyl acetate (bp = 126.5°C) N, N-dimethylformamide (bp = 153°C) 2-Methoxyethyl acetate (bp = 145°C) Methyl isobutyl ketone (bp = 116°C) Methyl isoamyl ketone (bp = 144°C) Isoamyl alcohol (bp = 132°C) Cyclohexanone (bp = 156°C) 2-Ethoxyethanol (bp = 135°C) 2-Methoxyethyl ether (bp = 162°C) Methyl butyl ketone (bp = 127°C) Hexyl alcohol (bp = 157°C) 2-Pentanol (bp = 119°C) Ethyl butyrate (bp = 121°C) Nitroethane (bp = 114°C) Pyrimidine (bp = 123°C) 1, 3, 5 Trioxane (bp = 115°C) Isobutyl isobutyrate (bp = 147°C) Isobutyl propionate (bp = 137°C) Propyl propionate (bp = 122°C) Ethyl Lactate (bp = 154°C) n-Butanol (bp = 117°C) n-Pentanol (bp = 138°C) 3-Pentanol (bp = 116°C) The amounts of the metals used are usually proportioned to an equivalent weight of each metal equal to the molecular weight of the metal in the stoichiometric formula for the desired layered superlattice material. An exception is lead. Generally an excess of lead of between 1% and 100%, preferably between 3% and 10%, of the equivalent stoichiometric amount is included because lead oxide has a higher vapor pressure than the other metals and a significant amount of lead evaporates as lead oxide during baking and annealing. Similarly, excess amounts of other materials, such as bismuth, thallium, and antimony, that evaporate or otherwise are lost in the process may be used. For bismuth the best results were obtained with 50% excess. In Example 1 below, an excess of titanium is noted in the Bi 4 Ti 3 O 12 material, however this was an accidental excess and is believed to be too small of an excess to make a significant difference, but is noted for completeness. The steps P1, P2, and P3 are preferably performed by mixing the metal or other metal compound, such as a metal alkoxide, with the carboxylic acid and the solvent and stirring. Low heat of between about 70°C and 90°C may be added to assist the reaction and dissolving, but this is generally not necessary. The solid arrows indicate that generally, the chemist will perform all the steps P1, P2 and P3 in the same container; that is the first metal or metal compound, the first measure of carboxylic acid, and a first solvent are placed in a container, the metal or metal compound and carboxylic acid are reacted, and the reactant dissolved, the second metal or metal compound is then placed in the same container and additional carboxylic acid and solvent are added and stirred to react the second metal or metal alkoxide and dissolve the reactant, then the third metal or metal compound, third carboxylic acid, and third solvent are added, the metal or metal compound is reacted, and the reactant dissolved. In this process the most reactive metal or metal compound is preferably added first, the second most reactive metal or metal compound added second, and the least reactive metal/metal compound added last. It also may be desirable to perform the distillation step after each or some of the metal/metal compounds are reacted and dissolved. Or, each metal and/ or metal compound may be combined with a carboxylic acid and solvent, reacted, and dissolved in a separate container, the result distilled if desirable, and then the three separate solutions mixed in step P4. Variations and combinations of preparing the individual metal precursors separately or in the same container with or without distil¬ lation^) may be used depending on the solvents used and the form in which metal element is readily available. In addition it should be understood that if the desired superiattice material includes only two metallic elements, then only two metals or metal compounds will be reacted and dissolved, and if the desired superlattice material includes four or more metallic elements, then four or more metals or metal compounds will be reacted and dissolved. Further, it is understood that any of the steps P1, P2, and P3 may be replaced by using a preprepared metal carboxylate. When the solution of reacted and dissolved metal carboxylates has been prepared, the mixed precursor solution is then distilled in step P5 by heating and stirring the solution to reduce the solution to the desired volume and viscosity, which may depend on whether the solution is to be stored or used immediately, and/or to remove certain liquids. Generally, if it is desirable to remove certain liquids, the solution is heated to a temperature above the boiling point of the liquids to be removed and below the boiling point of the liquids that are desired to be retained. The solution is distilled until all the solvents that are desired to be removed have evaporated and a desired volume and viscosity are reached. It may be necessary to add the desired solvent several times in the distilling process to remove all undesired solvents and obtain the desired volume and viscosity. Optionally, either separately or in combination with the steps P1 through P5, a xylene exchange step P6 is performed. In this step xylene is added and the other solvents are distilled away. This xylene exchange step P6 would generally be performed when the coating process P7 is one in which a xylene-based precursor is preferable. This may also depend on the personal preferences and experience of the person who performs the coating process P7. Although the xylene exchange is shown as a separate step P6, if it is known that the xylene-based precursor will be preferable, the xylene may be added with the other solvents in steps P1, P2, and/or P3 and the other solvents distilled away in the distillation step P5. Or, as shown by the dotted lines in Fig. 1A, the precursor may be stored after the distilla¬ tion step P5, and the xylene exchange performed just prior to use. If it is not known at the time of preparing the precursor solution whether or not a xylene-based solution will be preferable, then the xylene exchange should not be done since the xylene generally has a higher boiling point than the other solvents used in steps P1 , P2, and P3 and therefore removing it in favor of the other solvents is difficult. As described in example 2 below, it has recently been found that the addition of n-butyl acetate as a co-solvent just prior to the coating step P7 often results in superior films. In step P7 the precursor solution is then applied to a wafer, such as the wafer 1 in Fig. 2b, the wafer 20 in Fig. 2C, or the wafer 50 in Fig. 2D. In the case of wafer 20, the substrate 2 and the layers 4, 6, and 8 will be already formed at the time of coating in step P7 to form layer 10. Then the process of Fig. 1A may be used to form layers 12 and 14. Similarly, in the case of wafer 20, the substrate 22, and the layers 24, 26, and 28 will be formed, and in the case of wafer 50, the substrate 51 , the doped areas 52, and the layers 54, 56, and 58 will be formed prior to the coating step P7 in which the layers 30 and 60, respectively, are deposited. Preferably the coating step P7 may be either a mist deposition at ambient temperature in a vacuum as described in the first embodiment in United States Patent Application Serial No.660,428, which is incorporated herein by reference, or it may be a spin deposition, which is a well-known form of deposition in which the precursor is placed on a wafer and the wafer is spun to evenly distribute the precursor over the wafer. Preferably the wafer is spun at a spin rate of between 750 RPM and 6000 RPM for a period of 5 seconds to a minute, with these parameters depending on the concentration and viscosity of the solution being applied and the desired thickness of the resulting layer. In general the xylene exchange P6 is performed in preparing the precursor solution if the spin coating method is used, and the xylene exchange P6 is not performed if the mist deposition is used. After the coating process, the wafer 1, 20, 50 Is transferred to a hot plate in which it is baked as indicated at P9. Alternatively, an oven may be used in the baking if it is desirable to control ambients. Preferably, the baking is at a temperature in the range of 200°C and 400°C for a time period between 30 seconds and 15 minutes. Optionally, a drying step P8 may be preformed between the coating and bake steps. The drying will generally comprise a heating on a hot plate or in an oven for from about 30 seconds to a few minutes at a lower temperature than the bake step. Preferably, the drying is performed at about 150°C. If the initial coating and bake steps do not result in a layer, such as 30 in Fig. 2C, that is as thick as desired, then the coating P7, optionally the drying step P8, and the baking step P9 are repeated until the desired thickness is obtained. After the last layer is coated and baked, the wafer is placed in a diffusion furnace and the layered superlattice material is annealed at step P11. Preferably, the annealing is performed in an oxygen atmosphere at ambient pressure with a flow rate of about 3 liters to 6 liters per minute, and at a temperature of between 600°C and 850°C for a time period of between 5 minutes and three hours. The temperature is preferably ramped upward in steps over this period. Optionally, the wafer may be annealed in a rapid thermal process (RTP) step P10 prior to the diffusion furnace anneal step P11. The RTP step utilizes a halogen light source to raise the wafer rapidly to a high temperature in the range from 500°C to 850°C for an anneal time of between 15 seconds and 3 minutes. After the annealing P11, the rest of the wafer 1, 20, or 50 is completed. For those metals for which the metal carboxylates do not yield a good thin film, a variation of the above process is utilized. This variation preferably employs a metal alkoxide rather than a metal carboxylate precursor. Preferably an alkoxide is chosen that has a medium-length ligand, so that the precursor has a long shelf life and does not produce precipitates. Preferably, the alkoxide is one that is an effective solvent for the fabricating process, and if desired, can easily be replaced by xylenes via the addition of xylene and distillation. As mentioned above, 2- methyethanol is such an ideal alkoxide. When the precursor is a metal alkoxide it is also important that all the water be distilled out of the solution before it is stored. An example of the above variation of the process of Fig. 1A to produce a bismuth titanate (Bi 4 Ti 3 O 12 ) thin film is shown in Fig. 1 B. This variation is the same as the precursor solution formation portion of the process of Fig. 1A, except that the reaction and dissolving of the titanium in step P14 does not involve a carboxylic acid. In step P14 titanium isopropoxide is reacted with 2-methoxyethanol to produce titanium 2-methoxyethoxide, isopropanol and water, and the isopropanol and water are distilled off. In step P12 the bismuth metal, bismuth carbonate, or bismuth oxide has already been reacted with a carboxylic acid, i.e. 2-ethylhexanoic acid, to form bismuth 2-ethylhexanoate, a metal carboxylate. Bismuth is readily available commercially in this form. The process of Fig. 1 B is the process used to produce the bismuth titanate to produce the samples described below in the discussion of example 1. However, some combination of the processes of Fig. 1A and 1B by using various amounts of 2-ethylhexanoic acid and 2-methoxyethanol in step P14 may also be used to produce bismuth titanate and other such compounds. The 2- methoxyethoxide ligands are more heat sensitive than 2-ethylhexanoate ligands, and the deposition and film shrinkage process may proceed so rapidly that cracking and other defects may occur. Therefore, small amounts of 2-ethylhexanoic acid are added to replace some or all of the 2-methoxyethoxide ligands by 2-ethylhexanoate ligands in the titanium solution just prior to coating. The 2-ethylhexanoate ligands are less thermally sensitive and slow down the deposition and thermal decomposition process, usually producing better results. Fig. 1C shows another variation of the precursor solution formation process portion of Fig. 1A. In the process of Fig. 1C, the step P20 is the same as the step P14 of Fig. 1B, and the step P22 is the same as one of the steps P1 through P3 in Fig. 1A: that is, a metal, strontium, a carboxylic acid, 2-ethylhexanoic acid, and a solvent, 2-methoxyethanol, are combined to produce a metal carboxylate, strontium 2-ethylhexanoate, dissolved in a solvent, 2-methoxyethanol. In Fig. 1C optional steps of hydrolysis P26 and xylene exchange P28 are shown after the step of distilling P24. The xylene exchange step was discussed above in connection with step P6 of Fig. 1A. The hydrolysis step involves adding water to the solution to react with the metal alkoxide, i.e. titanium 2-methoxyethoxide. to partially polymerize the metal oxides into chains. This is sometimes useful to prevent the film from cracking after deposition. The acetic acid is optional and slows the rate of hydrolysis to prevent solids from forming and precipitating during hydrolysis. A distillation process is usually done as the final step of the hydrolysis P26. The process of Fig. 1C including the xylene exchange step P28, but not the hydrolysis step P26, was the process used in preparing the strontium titanate (SrTiO 3 ) solution to form the layers 10, 14 of the device of Fig. 2B as described below in example 1. While the preferred process is to apply the precursor directly to the integrated circuit wafer or other substrate on which the end device is fabricated, this is not necessary. The precursor may instead be applied to first substrate in accordance with the above process, and then sputtered onto a second substrate. This process is illustrated in Fig. 3. The precursor is applied to a first substrate 36 in the above-described process to form a film 38 of the desired material. Since the first substrate 36 is not the final substrate on which the material will be deposited, problems of cracking, porosity, shrinking etc. are not as significant, and a wider variety of precursors may be used following the guidelines discussed in the Overview section above. Generally the coat through bake steps, P7 through P9 (Fig. 1A), will be repeated a number of times to form a relatively thick film 38. The first substrate is preferably a conductive support 36. The second substrate 39 is preferably a silicon or other integrated circuit wafer as described in connection with Figs. 2A through 2D. The film 38 on its support 36 becomes the target electrode 40 in the sputtering process which takes place in sputtering chamber 41. The second substrate 39 is placed on the deposition electrode 42. A voltage source 44 is applied between the electrodes 40 and 42, and an inert gas plasma 46 is struck. Positive ions from the plasma 46 strike the target material 38 with sufficient energy to strip off atoms or molecules of the target material 38. Vacuum pumps are used to reduce the pressure in the sputtering chamber 41 so that the atoms or molecules make no or only a few collisions with each other before striking a surface, to which they stick. Most will follow the line of sight from the target electrode 40 to the wafer 39. Wafer 39 is generally heated to a temperature of between 200°C and 750°C. Because of the nature of the sputtering process, significant excess amounts of elements which tend to form low vapor pressure compounds must be used even beyond the excess amounts used in the direct spin coating and misted deposition processes. For example, for bismuth, lead, thallium, and antimony, as much as 100% excess may be necessary to provide the best results. The amount of the excess will depend on the particular sputtering process and sputtering system used. Sputtering is a well-known process, that can be applied to almost any material, and thus we shall not describe it further here. In the above discussion "sputtering" is understood to mean any one of a spectrum of related processes, including DC sputtering, RF sputtering, magnetron sputtering, reactive sputtering, bias sputtering, and ion beam deposition. The high-quality thin films produced by the above-described processes have led to the discovery that a class of materials that have never before been successfully utilized in non-volatile ferroelectric switching memories, in ferroelectric switching capacitors, or as high dielectric constant materials in volatile memories, are considerably superior to all previous materials used in such applications. In particular these materials exhibit low fatigue in switching applications, little or no imprinting, little change in the polarizability with film thickness, long retention of polarization charge even under high stress conditions, a high dielectric constant with low leakage current, and are compatible with, or can be designed to be compatible with, the other materials commonly used in integrated circuits, such as silicon and gallium arsenide. The class of materials include those disclosed by Smolenskii as having a layered perovskite-like structure, as discussed in the Background of the Invention. It has been realized that these materials are more than a substance which spontaneously forms in layers. This is seen most easily by an example. Strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ) can be considered to be a combination of a material having the formula Bi 2 O 3 and a material having the formula SrTa 2 O 6 . SrTa 2 O 6 has a tungsten bronze structure by itself, but within the layered material 92 has a perovskite structure. Thus the layered structure is in reality a superlattice in which the structures of the individual sublattices of the perovskite layers 94 and the non- perovskite layers 96 are interdependent. Hence we refer to these materials herein as "layered superlattice" materials. The layered superlattice materials of the invention which are ferroelectric can be defined as: (A) a material having a localized structure, within a grain or other larger or smaller unit, which localized structure contains predominately repeatable units containing one or more ferroelectric layers and one or more intermediate non ferroelectric layers spontaneously linked in an interdependent manner. The invention also includes materials that are not ferroelectric, and these can be included in the following definition: (B) a material having a localized structure, within a grain or other larger or smaller unit, which localized structure contains predominately repeatable units containing one or more perovskite-like layers and one or more intermediate non-perovskite-like layers spontaneously linked in an interdependent manner. The layered superlattice materials may be summarized under the formula: a) A N f ... Aj ; sι rs2 ?...sk f BI ;; ι B2 + y f ...BI^'Q 2 , where A1, A2...AJ represent A-site elements in the perovskite-like structure, which may be elements such as strontium, calcium, barium, bismuth, lead, and others S1 , S2...Sk represent super-lattice generator elements, which usually is bismuth, but can also be materials such as yttrium, scandium, lanthanum, antimony, chromium, thallium, and other elements with a valence of +3, B1, B2...BI represent B-site elements in the perovskite-like structure, which may be elements such as titanium, tantalum, hafnium, tungsten, niobium, zirconium, and other elements, and Q represents an anion, which generally is oxygen but may also be other elements, such as fluorine, chlorine and hybrids of these elements, such as the oxyfluorides, the oxychlorides, etc. The superscripts in formula (1) indicate the valences of the respective elements, and the subscripts indicate the number of moles of the material in a mole of the compound, or in terms of the unit cell, the number of atoms of the element, on the average, in the unit cell. The subscripts can be integer or fractional. That is, formula (1) includes the cases where the unit cell may vary throughout the material, e.g. in Sr 75 Ba 25 Bi 2 Ta 2 O 9 , on the average, 75% of the time Sr is the A-site atom and 25% of the time Ba is the A-site atom. If there is only one A-site element in the compound then it is represented by the "A1" element and w2...wj all equal zero. If there is only one B-site element in the compound, then it is represented by the "B1" element, and y2...yl all equal zero, and similarly for the superlattice generator elements. The usual case is that there is one A-site element, one superlattice generator element, and one or two B-site elements, although formula (1) is written in the more general form since the invention is intended to include the cases where either or the sites and the superlattice generator can have multiple elements. The value of z is found from the equation: (2) (a1w1 + a2W2... + ajwj) + (s1x1 + s2x2...+skxk) + (b1y1 +b2y2...+ bjyj) = 2z. The layered superlattice materials include all the materials as described by the definitions (A) and (B) above, and the formula (1), plus solid solutions of all the foregoing materials. As mentioned above, a detailed example of the fabrication process for an integrated circuit memory cell as in Fig. 2D is given in United States Patent Application Serial No. 919,186. Several examples of the process of fabricating a layered superlattice material and capacitor devices as shown in Figs. 2A through 2C are given below. Each is preceded by a table listing the reactive components utilized in the fabrication process and each is followed by a description of the ferroelctric and/or the dielectric properties as appropriate. The solvents used are described in a description of the process following each table. In the tables, "FW" indicates formula weight, "g" indicates grams, "mmoles" indicates millimoles, and "Equiv." indicates the equivalent number of moles in solution. "Xylenes" indicates a commercially available xylene solution which includes three different fractionations of xylene. Bismuth 2-ethylhexanoate indicates a commercially available bismuth solution of bismuth 2-ethylhexanoate in 74% naphtha; the formula weight in this case is placed in parenthesis to indicate that it is an equivalent formula weight of bismuth in the solution as a whole, rather than the formula weight of the just the bismuth 2-ethylhexanoate, in order to take into account the presence of the naphtha. AH processes were performed at the atmospheric pressure in Colorado Springs, Colorado, except where otherwise noted. In the examples below, all the initial wafer substrates on which the materials described were layered substrates as illustrated by layers 2, 4, 6, and 8 in Fig. 2B or layers 22, 24, 26, and 28 in Fig. 2C, with the silicon substrates 2, 22 being made of P-type silicon of between 5 Ohms/cm and 25 Ohms/cm resistivity, having a field oxide layer 4, 24 that was wet grown to about 500θA, a 200 A thick layer 6, 26 of sputtered titanium, and a 2000 A layer 8, 28 of sputtered platinum. After the layers 10, 12, 14 and 16, for the samples that had buffer layers, or the layers 30 and 32 for the samples that did not have buffer layers, were deposited as described in the examples, the wafer was patterned as illustrated in Fig. 2A using either a positive or negative photo resist in combination with a photo mask step. When a positive photo resist is indicated in an example, the resist is spun on at 5000 RPM, soft-baked on a hot plate at 95°C for 2 minutes, followed by a standard photo mask process having a 7 second UV exposure, a 1 minute development and 1 minute water rinse, and a 5 minute hard bake at 140°C. When a negative photo resist is indicated in an example, the negative resist is spun on at 5000 RPM, soft-baked on a hot plate at 90°C for 5 minutes, followed by a standard photo mask process utilizing a 4 second UV exposure, a 1 minute development and 1 minute water rinse, and a 5 minute hard bake at 140°C. When an IPC strip is indicated, this is an oxygen plasma strip using an Ion Plasma Corporation "barrel etcher" at 500 mTorr oxygen and 350 watts. When an rapid thermal process (RTP) is indicated, the process was done with an AG Associates model 410 Heat Pulser, the ramp rate given is for the period of increasing the temperature to the working temperature, and the time period given is the time for which the temperature was held at the working temperature. In all cases an oxygen flow of 3 liters/minute is used in the RTP anneals. In each figure, the material of the sample, the thickness of the sample, and other relevant parameters are given. The thickness is usually approximate since, as in all layering type processes, the thickness can vary, and it was not measured for each portion of the wafer. For some samples, the given thickness is based on the known thickness that results from the processing parameters; the measurements of thickness that were done confirmed that the thicknesses did not vary sufficiently from that determined from the process parameters to alter the results significantly. The hysteresis measurements were made on an uncompensated Sawyer-Tower circuit. The endurance or "fatigue" curve (Fig. 4) gives the polarization, P), P ~ , measured in a hysteresis measurement, in microcoulombs per square centimeter versus the number of cycles. The leakage current curve (Fig.7) is given in terms of the applied electric field as the abscissa versus the log of the current in amps per square centimeter. It is necessary to use the log of current because the curves are measured over an extremely wide range of currents. A leakage current of 10 "6 amps per square centimeter or less is considered excellent for dielectric applications. However, it should be kept in mind that for a given material the leakage current can be decreased simply by making the material thicker, and will be increased if the material is made thinner. Thus the thickness of the material on which the measurement is made must be considered. In state-of-the-art high-density CMOS integrated circuits, the dielectric layers range from about 100 A for the capacitor dielectric in DRAM capacitors to about 15,000 A for passivation layers. EXAMPLE 1 - Bismuth Titanate Between Buffer Layers of Strontium Titanate The compounds shown in Table I were measured. The bismuth TABLE I 2-ethylhexanoate was placed in 90 ml xylenes. The solution was stirred and heated to a maximum temperature of 117°C to distill out all light hydrocarbon fractions and water. The first measure of titanium isopropoxide was combined with 60 ml of 2- methoxyethanol, and was stirred and heated to a maximum temperature of 116°C to distill out all water and isopropanol. The bismuth solution and the titanium solution were combined, then heated to a maximum temperature of 136°C to distill out all 2-methoxyethanol and some xylenes until 60 ml of solution remained. The concentration was 0.1206 moles of Bi 4 Ti 3 O 12 per liter with .002% excess titanium. The strontium was placed in the 2-ethylhexanoic acid together with 50 ml 2- methoxyethanol. The solution was stirred and heated to a maximum temperature of 115°C to distill off all light hydrocarbon fractions and water. The second measure of titanium isopropoxide was dissolved in 50 ml methoxyethanol and stirred and heated to a maximum of 115°C to distill off the isopropanol and water. The strontium and titanium solutions were combined and stirred and heated to a maximum temperature of 125°C to distill down to a volume of 60.0 ml. The concentration was 0.533 moles of SrTiO 3 per liter. Just prior to use, a xylene exchange was performed by adding 25 ml of xylenes to 5 ml of the above SrTiO 3 solution and stirred and heated to a maximum temperature of 128°C to distill out 7 ml to produce a final solution of 23 ml volume and a concentration of .116 moles of SrTiO 3 per liter. The wafer was baked at 140°C in air for 30 minutes to dehydrate it. An eyedropper was used to place 1 ml of the SrTi0 3 solution on a wafer as in Fig. 2B with the layers deposited up to and including the platinum bottom electrode 8. The wafer was spun at 1500 RPM for 20 seconds. The wafer was then placed on a hot plate and baked at 250°C in air for four minutes. An eyedropper was used to place 1 ml of the Bi 4 Ti 3 0 12 solution on the wafer and the wafer was spun at 1500 RPM for 20 seconds. The wafer was placed on a hot plate and baked at 250°C for 4 minutes. The steps from using an eyedropper to deposit 1 ml of SrTiO 3 solution on the wafer through baking on the hot plate were repeated for another SrTi0 3 layer 14. The wafer was then transferred to a diffusion furnace and annealed at 700°C in A process, an ion mill etch, an IPC strip and a final contact anneal at 700°C in an oxygen flow of 5 l/m for 50 minutes. The resulting sample was tested with the results shown in Fig. 4, which shows the polarizabilities, P|! and P*, as a function of hysteresis cycles, thereby illustrating the fatigue of the material. The polarizabilities were measured from hysteresis curves for the capacitor device 1 (Fig. 2B) with Bi 4 Ti 3 O 12 deposited in a layer 12 with SrTiO 3 buffer layers 10, 14. The total thickness of the three layers was about 2500 A. Fig. 4 shows that p and P* remain almost unchanged all the way out past 10 9 cycles. In the best prior art devices, the polarizabilities decay by more than 50% under the same conditions. Thus, whatever is exhibiting the hysteresis is a very low-fatigue material. It was believed that the material exhibiting the low fatigue is strontium bismuth titanate (SrBi 4 Ti 4 0 15 ) formed by the diffusion of elements at the SrTiO 3 /Bi 4 Ti 3 O 12 interfaces. Subsequent tests of a buffered capacitor device 1 as in Fig. 2B with a layer 12 of SrBi 4 Ti 4 O 15 showed similarly low fatigue. EXAMPLE 2 - Strontium Bismuth Tantalate - SrBi 2 Ta 2 O 9 The compounds shown in Table II were measured. The strontium was TABLE II combined with the first measure of 2-ethylhex-anoic acid and 80 ml 2- had cooled to approximately room temperature, the tantalum ethoxide followed by the second measure of 2-ethylhexanoic acid were added. The mixture was stirred and heated to a maximum temperature of 115°C to distill out ethanol and water. Then 75 ml xylenes followed by the bismuth 2-ethylhexanoate were added. The solution was stirred and heated with a maximum temperature of about 125°C until only 60.0 ml of solution remained. The concentration was 0.102 moles of SrBi 2 Ta 2 O 9 per liter. The wafer was baked at 140°C in air for 30 minutes to dehydrate it. An eyedropper was used to place 1 ml of the SrBi 2 Ta 2 0 9 solution on a wafer as in Fig. 2C with the layers deposited up to and including the platinum bottom electrode 28. The wafer was spun at 1500 RPM for 20 seconds. The wafer was then placed on a hot plate and baked at above 250°C in air for three minutes. The steps from using an eyedropper to deposit solution on the wafer through baking on the hot plate were repeated for another layer. The wafer was then transferred to a diffusion furnace and annealed at750°C in an oxygen flow of 5 l/m for 2 hours. The top layer 32 of 2000 A platinum was sputtered, a resist was applied, followed by a standard photo mask process, an ion mill etch, an IPC strip and a final contact anneal at 750°C in an oxygen flow of 5 l/m for 30 minutes. The resulting sample was tested and showed even lower fatigue than the device of example 1. For more recent samples a precursor solution in xylenes as described above with a concentration of 0.2 moles SrB^T^O g was diluted to 0.13 moles with n-butyl acetate and then spun onto the wafer and processed as described above. The resulting film was smoother and more uniform than previous films of the same material. Fig. 5 shows hysteresis curves at 2, 4, 6, 8, and 10 volts for a more recent sample of a capacitor of the type shown in Fig. 2C utilizing strontium bismuth tantalate (SrBi 2 Ta 2 0 9 ) as the ferroelectric material. This capacitor was made in a process as described in Example 2 above, except that 10% excess bismuth was used in the precursor solution and other process parameters were more carefully controlled to ensure better stoichiometry. The hysteresis curves are boxy and vertical, indicating much better ferroelectric switching performance than any prior art material. Moreover, the hysteresis curves for the five different voltages all nearly integrated circuit devices, since it means that even if the voltage changes substantially from specifications, as often happens in the real world, the device performance will not change significantly. The value of 2PR was 25.06, the best obtained to date for this material. This value of 2Pr is more than 4 times the value of Ps for strontium bismuth tantalate given in the prior art! Fig. 6 shows a hysteresis curve for a sample of SrBi 2 Ta 2 O 9 after 10 12 cycles superimposed on an initial hysteresis curve for the same sample is shown. 10 12 cycles is roughly equivalent to device switching 1000 times a second for 25 years. This is far more switching than can be expected for a non-volatile memory cell. The two curves change so little that for about half the loop the curve for 10 12 cycles retraces the initial curve. The above are not isolated, especially good samples. Fatigue curves such as shown in Fig. 4 for numerous samples of strontium bismuth tantalate (SrBi 2 Ta 2 0 9 ) have been run, and when placed on the same sheet of graph paper, they were nearly superimposed. It is expected that as experience grows with the fabrication processes, the difference from one sample to the next will become even less. For the best of the prior art materials, PZT, 2Pr decreased more than 50% over only 10 9 cycles, and varied widely from sample to sample. Because of the "shock absorber" feature of the layered superlattice materials, they also can perform under stressful conditions. PUND switching measurements performed on a sample of SrBi 2 Ta 2 0 9 over approximately 10 10 switching cycles at a temperature of 100°C were so consistent that the line of the curve merely grew thicker, without disturbing any of the features of the curve. PUND measurements for a sample of SrBi 2 Ta 2 O 9 taken after the sample had retained a polarization charge for 80 days at 100°C were superimposed on the initial PUND measurements for the same sample. The percentage change was relatively constant over the entire curves so that the shape of the curves stayed the same and the switching current still remained well within the range sufficient to operate a switching device. In another test samples of SrBi 2 Ta 2 O 9 held a programming charge for eighty days at 100°C, with sufficient charge remaining after 80 days to operate a memory function. Other tests on SrBi 2 Ta 2 0 9 shown little change in PUND curves after pulsing the with negative pulses at 1 MHZ for one hour at 84°C. These tests show that the layered superlattice material fabricated by the process of the invention shows little or no evidence of imprinting. Similar good results have been shown for samples of strontium bismuth niobate (SrBi 2 Nb 2 O 9 ) and strontium bismuth tantalum niobate (SrBi 2 TaNbO 9 ) fabricated using the process of the invention. EXAMPLE 3 - Barium Bismuth Tantalate - BaBi 2 Ta 2 0 9 The compounds shown in Table III were measured. The barium was placed TABLE III in 40ml of 2-methoxyethanol and 20 ml of toluene, to slow the reaction, and the first measure of 2-ethylhexanoic acid were added and allowed to react completely. Then the bismuth 2-ethylhexanoate was added followed by 40ml xylenes. The solution was stirred and heated to a maximum temperature of about 123°C to distill out water, the toluene and the 2-methoxyethanol. The solution was allowed to cool to room temperature, then the tantalum butoxide was added, followed by the second portion of the 2-ethylhexanoic acid and 40 ml additional xylenes. The mixture was heated to a temperature of about 123°C while stirring to distill out the butanol until eyedropper was used to place 1 ml of the BaBi 2 Ta 2 O 9 solution on a wafer as in Fig. 2C with the layers deposited up to and including the platinum bottom electrode 28. The wafer was spun at 1000 RPM for 20 seconds. The wafer was then placed on a hot plate and baked at 250°C in air for five minutes. The wafer was placed in a rapid thermal processor and annealed for 30 seconds in an oxygen flow of 3 l/m at a temperature of 700°C with a 125°/sec ramp rate. The steps from using an eyedropper to place BaBi 2 Ta 2 O g solution on the spinner to the RTP were repeated for another layer. The wafer was then transferred to a diffusion furnace and annealed at 750°C in an oxygen flow of 5 l/m for 2hours. A top layer 32 of 2000 A platinum was sputtered, a positive resist was applied, followed by a standard photo mask process, an ion mill etch, an IPC strip and a final contact anneal at 750°C in an oxygen flow of 5 l/m for 30 minutes. The resulting sample was tested with the results shown in Fig. 7. The BaBi 2 Ta 2 O 9 was not a switching ferroelectric, but was a paraelectric with a dielectric constant of 166 at 1 megahertz. This is a very high dielectric constant as compared to the dielectric constant of 3.9 for silicon dioxide, the most commonly used dielectric in integrated circuits. Fig. 7 shows the leakage current curve for BaBi 2 Ta 2 0 9 . At low voltages, the leakage current is negligible, of the order of 10 "10 amps/cm2. Over the range of voltages uses in conventional integrated circuits, i.e. 1-10 volts, the leakage current across the 2400 A sample remains below about 10 '8 amps/cm 2 , which is still very small. The thickness of this sample is about the same thickness generally used for dielectrics in conventional integrated circuits. These results show that this material will be an excellent high dielectric material in integrated circuits. Moreover, none of the elements of which the material is composed create compatibility problems with conventional integrated circuit materials. In addition BaBi 2 Ta 2 O 9 should be much more resistant to radiation damage than conventional dielectrics because, except for the oxygen, the elements out of which is compounded are heavier than the elements such as silicon and nitrogen out of which conventional integrated circuit dielectrics are composed. Similar results, close to but not quite as good as for BaBi 2 Ta 2 0 9 , were obtained for The above-described data shows that the materials fabricated according to the process of the invention are vastly superior to the materials fabricated according to prior art processes. There has been described a novel process for fabrication of thin films, and in particular layered superlattice thin films for integrated circuits that results in reliable, low fatigue devices which have many advantages. It should be understood that the particular embodiments shown in the drawings and described within this specification are for purposes of example and should not be construed to limit the invention which will be described in the claims below. Further, it is evident that those skilled in the art may now make numerous uses and modifications of the specific embodiments described, without departing from the inventive concepts. For example, now that it is seen that layered superlattice materials generally have much better ferroelectric and dielectric properties when fabricated according to the process of the invention, the process can now be applied to fabrication many other materials for integrated circuits. These materials may be incorporated into many different devices other than capacitors, many different integrated circuits other than memories. The process may also be applied in other switching applications requiring low fatigue, such as pyroelectrics, electro-optics, etc. It is also evident that the steps recited in the fabrication processes may in some instances be performed in a different order. Or equivalent materials, structures, and processes may be substituted for the various materials, structures, and processes described. Different dimensions will certainly be used in other applications. Additional materials, structures, and process steps may be added. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in and/or possessed by the processes, materials, and structures described.

Claims: CLAIMS What is claimed is: 1. A method of fabricating a material (12), (30), (60), (38) comprising the steps of providing a first substrate (1), (20), (50), (36) and a precursor liquid containing a metal, applying (P7) said precursor liquid to said first substrate, and heating (P9) said precursor on said first substrate to form said material (12), (30), (60), (38) on said first substrate, characterized in that said precursor comprises a metal carboxylate in a solvent and said material is a layered superlattice material (12), (30), (60), (38). 2. A method as in claim 1 , wherein said first substrate is an integrated circuit wafer (50), and characterized by: applying (P7) said precursor to said integrated circuit wafer (50); heating (P9) said integrated circuit wafer (50) to form a layer (60) of a layered superlattice material on said integrated circuit wafer; and completing the fabrication of an integrated circuit (70) on said integrated circuit wafer (50) to include at least a portion (60) of said layer of layered superlattice material in a circuit component (72). 3. A method as in claim 1 wherein said first substrate comprises a support (36) and characterized by the step of sputtering the said layered superlattice material (38) from said support onto a second substrate (39). 4. A method as in either claims 1 , 2, or 3 characterized in that said metal carboxylate is a metal carboxylate having medium-length ligands. 5. A method as in claim 4 characterized in that said metal carboxylate is a metal 2-ethylhexanoate. 6. A method as in either claims 1 , 2, or 3 characterized in that said solvent is selected from the group comprising alcohols, aromatic hydrocarbons, and esters. 7. A method as in claim 6 characterized in that said solvent is selected from the group comprising xylenes, 2-methoxyethanol, and n-butyl acetate. 8. A method as in either claims 1 , 2, or 3 characterized in that said metal is a highly electropositive element and said precursor comprises a solvent selected comprises one or more of the elements from the group comprising strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, and thallium. 10. A method as in either claims 1, 2, or 3 characterized in that said precursor comprises 1% - 75% excess quantity of an element in said layered superlattice material (12), (30), (60), (38). AMENDED CLAIMS [received by the International Bureau on 28 May 1993 (28.05.93); original claim 10 deleted; original claims 7 and 8 amended; new claim 11 added; remaining claims unchanged (2 pages)] What is claimed is: 1. A method of fabricating a material (12), (30), (60), (38) comprising the steps of providing a first substrate (1), (20), (50), (36) and a precursor liquid containing a metal, applying (P7) said precursor liquid to said first substrate, and heating (P9) said precursor on said first substrate to form said material (12), (30), (60), (38) on said first substrate, characterized in that said precursor comprises a metal carboxylate in a solvent and said material is a layered superlattice material (12), (30), (60), (38). 2. A method as in claim 1 , wherein said first substrate is an integrated circuit wafer (50), and characterized by: applying (P7) said precursor to said integrated circuit wafer (50); heating (P9) said integrated circuit wafer (50) to form a layer (60) of a layered superlattice material on said integrated circuit wafer; and completing the fabrication of an integrated circuit (70) on said integrated circuit wafer (50) to include at least a portion (60) of said layer of layered superlattice material in a circuit component (72). 3. A method as in claim 1 wherein said first substrate comprises a support (36) and characterized by the step of sputtering the said layered superlattice material (38) from said support onto a second substrate (39). 4. A method as in either claims 1 , 2, or 3 characterized in that said metal carboxylate is a metal carboxylate having medium-length ligands. 5. A method as in claim 4 characterized in that said metal carboxylate is a metal 2-ethylhexanoate. 6. A method as in either claims 1 , 2, or 3 characterized in that said solvent is selected from the group comprising alcohols, aromatic hydrocarbons, and esters. 7. A method as in claim 6 characterized in that said solvent is selected from the group comprising xylenes and 2-methoxyethanol. 8. A method as in either claims 1 , 2, or 3 characterized in that said metal is a highly electropositive element and said precursor comprises 2-methoxyethanol. 9. A method as in either claims 1 , 2, or 3 characterized in that said metal comprises one or more of the elements from the group comprising strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, and thallium. 11. A method of fabricating a material (12), (30), (60), (38) comprising the steps of providing a substrate (1), (20), (50), (36) and a precursor liquid containing a metal, applying (P7) said precursor liquid to said substrate, and heating (P9) said precursor on said substrate to form said material (12), (30), (60), (38) on said substrate, characterized in that said precursor liquid comprises xylene and said material is a layered superlattice material (12), (30), (60), (38). STATEMENT UNDER ARTICLE 19 Claims 7 and 8 have been amended and claim 10 has been canceled to delete matter to which joint inventors in addition to those named in the application may have contributed. A new claim 11 had been added to cover a further aspect of the invention and to keep the total number of claims at 10.

Inventors: CUCHIARO JOSEPH D, MCMILLAN LARRY D, PAZ DE ARAUJO CARLOS A, SCOTT MICHAEL C, CUCHIARO, JOSEPH, D., MCMILLAN, LARRY, D., PAZ DE ARAUJO, CARLOS, A., SCOTT, MICHAEL, C.
Applicants: SYMETRIX CORP, SYMETRIX CORPORATION
Application year: 1992
Main classification: H01L21
IPC codes: C01G35, C23C18, C30B7, H01C7, H01L21, H01L27, H01L29