Preprocessor of a division device employing a high radix division system

Abstract: A preprocessor of a division device employing a high radix division system includes a first zero counter, a first shifter, a second counter, a latch, and a second shifter. From among continued "0" bits at the heads of a divisor and a dividend, the number of units of continued "0" bits are counted by the first zero counter using "n" bits as a unit. The divisor and the dividend are shifted by "the unit number" × "n bits" by the first shifter using "n" bits as a unit. Concurrently, the divisor shifted by the first shifter is counted for the remaining number of head expression " 0" bits by the second zero counter, and the divisor is normalized by the second shifter for obtaining the head bit "1". The dividend is shifted by the second shifter by the number of the head expression "0" bits of the divisor of the second zero counter stored by a latch, namely, by the shift number of the divisor. Thus, the difference between the shift numbers of the divisor and the dividend is always equal to an integer multiple of "n". The digit number of a quotient is also equal to an integer multiple of "n", the division can terminate at a predetermined digit, and a required remainder can be obtained simultaneously with the quotient.

Description: The present invention relates to a preprocessor of a division device, and in particular, to a preprocessor of a division device employing a high radix division system capable of producing a partial quotient "n" bits (n≧ 2) at a time. A division operation is largely classified into three processes, namely; preprocess, main process, and postprocess. The preprocess is used to modify operand data into a form such that the main processor accepts the operand data, and the main process actually produces the quotient and a remainder. The postprocess modifies the output of the main processor to obtain a specified form suitable for a result. The preprocess of the division device has various forms, depending on the systems of the main processes. The most widely known system of the main processes is a means such that one bit of partial quotient is obtained by subtracting a divisor from a partial remainder, the result of such subtraction of the original partial remainder is shifted by one bit, and the resultant value is made a new partial remainder (hereinafter referred to as one-bit system). The high radix division system is used to produce an n-bit partial quotient by a one time processing, in comparison with the one-bit system. The one-bit system performs a normalization shift as a preprocess to produce a significant bit of "1" both for a divisor and a dividend. Such a processing is carried out by a preprocessor. In the preprocessor of the division device as hereinbefore described, a drawback often arises when a high radix division requires both a quotient and a remainder at the same time. This is because an enumeration for obtaining a quotient must be stopped at the predetermined digit to leave a remainder, but such a predetermined digit is often not the last digit of group "n" digits. Such a problem arises in the high radix division, and therefore, conventionally a dividend shift is performed after amending a micro program to make the bit number of the quotient to be obtained an integer multiple of "n". However, such an amendment by the micro-program requires multiple machine cycles for the processing, and therefore, results in the deterioration of a division performance. Such an algorithm is disclosed in IBM technical disclosure bulletin, Volume 23 No. 1 of June 1980, pages 249 to 251, in an article by K.K. Maass entitled "Alignment of operands before and after 2-bit binary divide loop". The divisor is first digit normalised, and then bit normalised. The dividend is then left shifted by the number of leading digits of the divisor, right shifted 4-bits, and then left shifted by the number of leading zero bits of the divisor. After division, a number of steps are taken to obtain the remainder from the result. In "Radix-16 Signed-digit division", by T M Carter and J E Robertson, IEEE transactions on computers, Volume 39 No. 12 of December 1990, New York, US, another division algorithm is described, for use with digits having a maximum value of ± 10 and a radix of 16. Some numbers have redundant representations. Normalisation takes place to a particular value range, not to a particular digit in the leading position. SUMMARY OF THE INVENTION An object of the present invention is to provide a preprocessor of a division device capable of preprocessing a high radix division at a high speed. According to the present invention there is provided a division device preprocessor as defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below with reference to the accompanyinq drawinqs wherein: Fig. 1 is a schematic block diagram explaining a conventional preprocessor of the division device; Fig. 2 shows an operation of the conventional preprocessor of the division device; Fig. 3 shows an operation of the conventional preprocessor of the division device; Fig. 4 shows an operation of the conventional preprocessor of the division device; Fig. 5 is a clock diagram showing an embodiment of a preprocessor of a division device according to the present invention; Fig. 6 is a block diagram showing a division device using a preprocessor of Fig. 5 according to the present invention; Fig. 7 shows an operation of a preprocessor of a division device according to the present invention; and Fig. 8 shows an operation of a preprocessor of a division device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the preferred embodiments, an explanation will be given of the conventional preprocessor of a division device, with reference to Fig. 1. Figure 1 is a schematic block diagram explaining a conventional preprocessor of the division device of a one bit system. The one-bit system performs a normalization shift as a preprocess to produce a most significant bit of "1" both for a divisor and a dividend. Such a processing is carried out by a preprocessor as shown in Figure 1. The preprocessor is comprised of a selector 11 for selecting a divisor or a dividend to be input, a zero counter 12 for counting the number of binary digits on which "0s" at the heads of a divisor and dividend are written, and a shifter 13 for shifting zero bits obtained by such counting to produce the most significant bit of "1". Producing the most significant bit of "1" is called normalization. The preprocessor outputs the number of "0" expression bits measured by a zero counter 12 and shifted by a shifter 13, and the normalized divisor and dividend, and sends the same to the main processor 10. In such a process, "0111" + "0011" can be computed, for example, by the following procedure. A divisor Y=0011 is normalized to produce "1100" and a dividend X=0111 is normalized to produce "1110". At this time, assume that the shift amount (=sa) of Y and X are saY and saX, and saY=2 and saX=1 is produced, since the divisor Y=0011 is shifted two bits to "1100" and the dividend X=0111 is shifted one bit to "1110". In the main processor, in Fig. 2, if a division is performed as a binary digit integer and a left bit of a dividend X is the 0th bit, then a quotient is produced only from the third bit (saY-saX+1), in this example producing only 2 bits. Further (3-saY+saX) pieces of "0s", in this example two "0s" are inserted to the left of the third bit, thus leaving a quotient " 0010". A remainder starts at the (-saX)-th bit, and in this example "0001" corresponding to as much as 4 bits from the (-1)-th bit is left. In the preprocessor of the division device as hereinbefore described, a drawback often arises when a high radix division requires both a quotient and a remainder at the same time, because an enumeration for obtaining a quotient must be rounded up at a predetermined digit to leave a remainder, but such a predetermined digit is often not the last digit of group "n" digits. An example of such a drawback is shown in Fig. 3, where 1011 ÷ 0011 is computed, by using the high radix system capable of obtaining two quotient bits producing basis at a time. If producing quotient bits is started at the third bit, (saY-sax+1)= 2 - 0 + 1 = 3 is the number of bits to be produced and it is desired to attain only the fifth bit after obtaining the third and fourth bits at the same time by the high radix system. If simultaneously attaining the fifth and sixth bits, the quotient of the sixth bit is established. To obtain only a quotient, a rounding down of the sixth bit is preferred, but, to obtain a remainder, an amendment is required because of an excessing high minus of as much as the quotient of the sixth bit thereafter. This example is satisfactorily processed when a quotient is attained from the second bit, but upon computing 1011÷ 0110, as shown in Fig. 4, the enumerating for a quotient is processed up to the fifth bit when the enumeration is intended to stop at the fourth bit. Such a problem arises in the high radix division, and therefore, conventionally a dividend shift is performed after amending a micro program to attain "n" as the bit number of the quotient to be obtained However, such an amendment by the micro-program requires multiple machine cycles for the processing, and therefore, results in the deterioration of a division characteristic. An embodiment of a preprocessor of a division device in accordance with the present invention is described with reference to the drawings. Figures 5 to 8 show an embodiment of a preprocessor of a division device in accordance with the invention. In the present embodiment, a preprocessor of a division device is comprised of, as shown in Figure 5, a first selector 6 for selecting either a divisor or a dividend respectively to be input; a first zero counter 1 for counting the unit number of continued "0" bits when using "n" bits as a unit from among the continued "0" bits at the heads of the divisor and the dividend respectively input; a first shifter 2 for shifting the divisor and the dividend by a "n" bit unit based on the above counted value, a second zero counter 3 for counting the number of head expression "0" bits of the divisor having completed the first normalization (hereinafter referred to as "bsaY", standing for bit shift amount of Y); a latch 4 for storing the value of the zero counter, a second selector 7 for selectively outputting an output of the second zero counter 3 or an output of the latch 4, and a second shifter 5 for receiving the output of the second selector and executing a shift of the divisor by less than "n" bits and another shift of the dividend by the number stored by the latch 4. The preprocessor of the division device is used to output the normalized dividend X and divisor Y and the respective shift numbers. Therefore, according to the embodiment, for example, when computing the high radix division with a radix 3 for 000 010 111 010÷ 000 000 001 001, the first selector 6 selects a divisor 000 000 001 001 and feeds it to the first zero counter 1. The first zero counter 1 counts the unit number of "0" bits existing from the head by using n=3 as a unit (hereinafter referred to as "nsaY", standing for n-bit shift amount of Y), and obtains the shift unit value nsaY=2 to be fed to the first shifter 2. Similarly, the number of continued three "0s" bits "000" is counted when inputting 000 000 001 111, and leaves nsaY=2. The first shifter 2 shifts the divisor by (nx nsaY) bits, i.e., by 3× 2=6 bits, and leaves 001 001 000 000 to send out to the second zero counter 3. The second zero counter counts expression "0" bit of the divisor shifted by the first shifter, obtains the shift number 2, and outputs the same to the latch 4 and the second shifter 5. The second shifter 5 performs a 2-bit shift, and outputs 100 100 000 000 and the shift unit number nsaY=2 of the first time and the shift number bsaY=2 of the second time. To normalize the dividend, the first selector 6 selects dividend 000 010 111 010, which is input to the first zero counter 1. The first zero counter 1 counts the shift unit number using n=3 as a unit to obtain the shift unir number nsaX=1, and feeds it to the first shifter 2. Then, the first shifter 2 shifts the dividend by 3 bits to obtain 010 111 010 000, and feeds it to the second zero counter 3. At this time, the second selector 7 selects the latch 4 to obtain the shift number 2, and feeds it to the latch 4 and the second shifter 5. The second shifter 5 performs a 2-bit shift to output the dividend 01 011 101 000 000 and the shift unit number nsaX=1 of the first time. As hereinbefore described, according to the present embodiment, the difference between the shift numbers of the divisor and the dividend is 8-5=3, which is a multiple of 3. This relationship is always established, the bit number of a quotient operated is a multiple of 3, and the division is stopped at the predetermined digit to thus obtain an exact remainder. In more detail, the divisor is shifted by (3 × nsaY + bsaY) bits, the dividend is shifted by (3 × nsax + bsaY) bits, and thus, the difference between the shift numbers is (3 × nsaY + bsaY) - (3 × nsaX + bsaY) = 3(nsaY - nsaX), thereby resulting in a multiple of radix n=3 of the present example. An example of the division device using the preprocessor according to the present embodiment will be described. The preprocessor is the same as described above, and the explanation thereof is hereinafter omitted. Figure 6 shows a division device using the preprocessor according to the invention. In the drawing, reference numeral 21 depicts a latch for storing a first shift amount nsaX of the dividend counted by the first zero counter 1; 22 depicts another latch for storing the first shift amount nsaY of the divisor; 23 depicts still another latch for storing the second shift number bsaY of the dividend and the divisor; 24 depicts a Y register for storing the normalized divisor; 25 depicts an X register for storing the normalized dividend; 26 depicts a subtracter for computing nsaX-nsaY; 27 depicts a main processor for enumerating a quotient and a remainder; 28 depicts a quotient register for storing a quotient enumerated from the main processor 27; 29 depicts a right shifter for right-shifting a quotient stored in the quotient register based on the value of the subtracter; 30 depicts another right shifter for right-shifting a remainder stored in the X register based on value of nsaX and bsaY, and 31 depicts a third selector for storing a remainder from the main processor to the X register. The change of the normalized divisor in the process of division is explained in detail in USP 4,722. 069. When the latches 21, 22, 23 and the registers 24, 25 store nsaX, nsaY, bsaY, X, and Y, the number of repeating times nsaX-nsaY+1 for a quotient enumeration is determined by computing nsaY-nsaX by the subtracter 26. According to this process, the main processor computes to obtain a quotient and an intermediate remainder on processing basis. The quotient and remainder are respectively stored in the quotient register 28 and the X register 25, and after the processes are completed a predetermined number of times. the quotient is stored in the quotient register 28 and the remainder is stored in the X register 25. Since the quotient and remainder correspond to the normalized dividend and divisor, then by the respective right shifters 29 and 30, the quotient and the remainder are obtained respectively by right-shifting the quotient by [n× (nsaX-nsaY)+p] bits and by right-shifting the remainder by (n× nsaX+nsaY+q) bits, where "p" and "q" are constants determined depending on a scaling of the divisor and the dividend and other conditions. A practical computation is described assuming n=2. Producing quotient bits starts at the second bit. In Fig. 7, when computing 1011 + 0011, because the divisor's first shift number nsaY=1 and the dividend's first shift number nsaX=0 and the divisor's second shift number bsaY=0, then the number of the operational times nSaY-nsaX+1 is equal to 2, the quotient is 0011, and the remainder is 0010. Similarly, in Figure 8, when computing 1011÷ 0110. because the divisor's first shift number nsaY=0 and the dividend's first shift number nsaX=0 and the dividend's second shift number bsaY, then the number of the operational times nsaY-nsaX+1 is equal to 1, the quotient is 0001, and the remainder is 0101. According to the embodiment, the difference between the shift numbers of the divisor and the dividend is always an integer multiple of "n"; a digit number of a quotient is also an integer multiple of " n"; a division may be stopped at the predetermined digit. and a desired remainder obtained simultaneously with a quotient. Note that the shift value may be different if a bit position of a shift register, to which a dividend is stored, is different, but the substantial shift amount is the same when the bit position of the shift register is fixed, for example, when a left bit of a dividend X is the 0th bit. As hereinbefore described, in accordance with the present invention, a divisor and a dividend measures the bit number of head expression "0" bits by the first zero counter using "n" bits as a unit, and is shifted by the first shifter by a unit of "n" bits. Concurrently, for the divisor shifted by the first shifter, the number of remaining head expression "0" bits thereof is measured by the second zero counter, and its head bits are normalized by the second shifter to express "1", and the dividend is shifted by the second shifter by the number of the head expression "0" bits of the divisor of the second zero counter stored by the latch, namely, by the shift number of the divisor. Thus, the difference between the shift numbers of the divisor and the dividend is always equal to an integer multiple of "n", a digit number of a quotient is also equal to an integer multiple of "n"; the division can be terminated at a predetermined digit, and a required remainder can be obtained simultaneously with the quotient. Since the preprocessor of the division device is realized by hardware, the division process can be executed at high speed with an improvement of the characteristic of a computer.

Claims: A division device preprocessor for use with a high radix division system capable of producing a partial quotient "n" bits (n ≥ 2) at a time, said preprocessor comprising; a first zero counter (1) connected to the operand inputs for counting the unit number of "n" bit units of continued "0" bits at the heads of a divisor and a dividend that have been input, and which outputs the respective input divisor unit number and input dividend unit number; a first shifter (2) whose data input is connected to the operand inputs and whose shift input is connected to the output of the first zero counter, for shifting the input divisor and the input dividend by the unit number counted by the first zero counter multiplied by "n" bits obtained from the divisor and the dividend; said preprocessor being characterised by further comprising: a second counter (3) connected to the output of the first shifter for counting the number of the continued "0" bits at the head of the shifted divisor output by the first shifter (2); a second shifter (5) whose data input is connected to the output of the first shifter and whose shift input is connected to the output of the second counter, for shifting sequentially the divisor and the dividend shifted by the first shifter (2) by the number of bits output from the second counter (3), whereby the preprocessor outputs a normalised divisor and dividend in which the difference between the shift numbers of the divisor and the dividend is always an integer multiple of "n", and a digit number of a quotient is also made an integer multiple of "n", so that a division may be stopped at the predetermined digit, and a remainder can be obtained simultaneously with a quotient. A preprocessor as set forth in claim 1, further comprising; a latch (4) for storing the value output by the second counter; a first selector (6) having the divisor and dividend as inputs for outputting one of the divisor and dividend to the first zero counter and to the first shifter; and a second selector (7) having the latch and the second zero counter as inputs, for outputting one of the value being output by the second zero counter and the value stored by the latch to the second shifter.

Inventors: ITO EIKI, ITO, EIKI, Ito, Eiki, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G06F7
IPC codes: G06F7