Electronic device interconnection technique

Abstract: External connections are made in an electronic device (11) having on an upper surface an array of contact pads (12) by providing successively over the electronic device a first anisotropic member (13), a first flat insulator member (14) having on an upper surface a first conductor pattern (29), a second flat anisotropic conductor member (15), and a second flat insulator member (17) having on an upper surface a second conductor pattern (30). The two flat insulator members contain an array of conductive vias (25, 26) extending between opposite surfaces. The first anisotropic conductor member (13) and a first array of conductive vias (25) extending through the first insulative member (14) interconnect a first plurality of contact pads (12) on the electronic device (11) to the first conductor pattern (29) which includes a peripheral array of contact pads (32) to which external connections are made. Means for interconnecting a second plurality of the contact pads on the electronic device to the second conductor pattern (30) comprise the second flat anisotropic conductor member (15) and a second array of conductive vias (26) extending through the second insulator member (17), the first array of conductive vias (25) and the first anisotropic conductor member (13).

Description: Technical Field This invention relates to techniques for connecting an electronic device to external circuitry and, more particularly, to packages for making contact to each contact pad of a high density array of contact pads of an integrated circuit chip. Background of the Invention As the density of devices formed in integrated circuit chips has increased, the problem of making reliable connections to the chip has become more complicated. Most integrated circuit chips include contact pads arranged around the periphery of the device so that electrical connections can conveniently be made by any of a number of bonding techniques. Some integrated circuits, however, have so many separate contact pads that it is not possible to locate them all around the chip periphery. For example, known photonics systems may require an array of thousands of photodetectors, each requiring a separate connection, defined on a single integrated circuit chip having an area of only about one square centimeter. There are other integrated circuit devices in which the number of contact pads has become so numerous that one cannot make the required connections of the chip to external circuitry without difficult and painstaking effort. The U.S. patent of Thomas, No. 4,843,191, provides one approach to the problem comprising the use of several rows of contact pads on the periphery of the chip to be contacted by tape automated (TAB) bonding to conductors carried on different insulator layers. It is difficult to use this technique with a matrix array, such as photoconductor arrays. There has therefore developed a long-felt need for techniques to make contact to a high density of contact pads of an integrated circuit chip, particularly a dense matrix array of pads, in a manner that is reasonably inexpensive, reliable, and which is consistent with the mass production of such devices. The invention makes use of a material known as an anisotropic conductor material, that is, a material that will conduct electricity in only one direction. Such material may comprise an insulative sheet containing spaced conductors extending across the thickness of the sheet as described, for example, in the U.S. patent of Kashiro et al., No. 4,209,481, granted June 24, 1980. As another example, it may comprise a sheet of polymer material containing conductive ferromagnetic particles which have been aligned during cure of the polymer by a magnet to form conductor columns connecting opposite surfaces of the polymer sheet, as described generally in the U.S. patent of Hechtman et al., No. 4,778,635, granted October 18, 1988 and in the paper, "Applications and Reliability of the AT&T Elastomeric Conductive Polymer Interconnection (ECPI) System," J. A. Fulton et al., IEPS , September 1990, pp. 930-943, both of which are hereby incorporated herein by reference. According to the present invention, there is provided a package as defined in claim 1. In accordance with an illustrative embodiment of the invention, external connections are made to an electronic device having on an upper surface an array of contact pads by providing successively over the electronic device a first flat anisotropic conductive member, a first flat insulative member having on an upper surface a first conductor pattern, a second flat anisotropic conductive member, and a second flat insulative member having on an upper surface a second conductor pattern. The two flat insulative members contain an array of conductive vias extending between opposite surfaces. The first anisotropic conductive member and a first array of conductor vias extending through the first insulative member interconnect a first plurality of the contact pads on the electronic device to the first conductor pattern which includes a peripheral array of contact pads to which external connections can be made. Means for interconnecting a second plurality of the contact pads on the electronic device to the second conductor pattern comprise the second flat anisotropic conductive member and a second array of conductor vias extending through the second insulative member, the first array of conductor vias extending through the first insulative member and the first anisotropic conductive member. The conductor pattern on the second insulative member contains another peripheral array of contact pads to which external connection can be made. The foregoing embodiment divides the contacts of the electronic device into two arrays of peripheral contact pads on two overlying flat insulative members. Thus, if the electronic device contained one hundred contact pads, one could form fifty peripheral contact pads on each of the two flat insulative members for making external connections to the device. It may be possible to arrange the fifty contact pads around a periphery of each of the two insulative members much more conveniently than to form one hundred contact pads around the periphery of the electronic device; and so the invention permits external connection by a plurality of peripheral contact pad arrays to the single dense contact pad array of an electronic device. From the foregoing, it is apparent that a larger plurality of flat insulative members can be used to divide further the number of contact pads that can be used for making contact to the contact pads of the electronic device. That is, three, four, five or even more flat insulative members can be used with intervening anisotropic conductive members to provide a multiplicity of layers to which external contacts can be made. Each of the flat insulative members contains conductor vias for interconnecting electronic device contact pads to peripheral contact pads on the insulative member or for making a connection to another anisotropic conductive member, and thence to a conductor via of another flat insulative member. In a specific embodiment to be described in detail, three flat insulative members are used for providing interconnections to an array of thirty-six contacts of an electronic device. The first flat insulative layer includes four peripheral bonding pads for making external connections to four of the electronic device contact pads, the second insulative member provides twelve peripheral bonding pads, and the third insulative member provides twenty contact pads. This embodiment demonstrates that there is no need to divide the number of external bonding pads equally among the various flat insulative members that are used. A fewer number of peripheral bonding pads may be desirable on flat insulative members in which longer conductor paths to the peripheral conductor pads are required. Various other objects, features, advantages, and various other embodiments of the invention will be better understood from a consideration of the following detailed description taken in conjunction with the accompany drawing. Brief Description of the Drawing FIG. 1 is a schematic exploded view of part of an electronic device package in accordance with an illustrative embodiment of the invention; FIG. 2 is a top view of an integrated circuit chip of FIG. 1; FIG. 3 is a sectional view of part of an anisotropic conductive member of FIG. 1; and FIGs. 4, 5 and 6 are top views of flat insulative members of the embodiment of FIG. 1. Detailed Description It is to be understood that the drawings are schematic and not to scale, and have been distorted to reveal more clearly certain important features of the invention. Referring now to FIG. 1, which is an exploded view of part of an electronic device package in accordance with an illustrative embodiment of the invention, there is shown an integrated circuit chip 11 containing on one surface an array of contact pads 12. Successively bonded to the upper surface of device 11 is a first flat anisotropic conductive member 13, a first flat insulative member 14, a second flat anisotropic conductive member 15, a second flat insulative member 17, a third flat anisotropic conductive member 18, and a third flat insulative member 19. Referring to FIG. 2, the integrated circuit device 11 illustratively comprises a matrix array of semiconductor photoconductor devices 20, each of which has a contact pad 12; as is known, photodetector arrays are useful in conjunction with various lightwave communications systems. A common practice in integrated circuit fabrication and packaging is to make external connections to the device by way of conductor pads or bonding pads arranged on the periphery of the integrated circuit chip. The purpose of the assembly of FIG. 1 is to provide contacts on the peripheries of the three insulative members 14, 17, and 19, rather than all being included on the periphery of just one element. The anisotropic conductive members 13, 15, and 18 are all made so as to conduct electrical current only in the vertical direction and not in the horizontal direction (hence, the term "anisotropic"). FIG. 3 shows a portion of anisotropic member 13 as an illustration of one of many forms such members can take. The major portion of the member 13 comprises an insulative material 22 with conductive elements 23 interconnecting upper and lower surfaces of the member. The conductors 23 may constitute solid conductor members as is described in the aforementioned Kashiro et al. patent, for example, or they may be magnetically aligned columns of conductive ferromagnetic particles, as described, for example, in the aforementioned Fulton et al. paper. In either case, the conductors 23 are not interconnected and do not touch each other so that there can be no conduction in the horizontal direction, but each conductor interconnects the opposite vertically displaced surfaces of the flat member 13. Further, the conductors 23 are sufficiently close together that they are separated by a maximum distance P in both the length and width directions. The separation distance may be regular or it may be arbitrary, but the distance P , known as the pitch, is a measure of the size of elements that can be interconnected by member 13. That is, the pitch P of the anisotropic conductive member 13 should be smaller than the length or width dimension of each conductor pad 12 of FIG. 2 to insure that at least one conductor 23 makes contact with each conductor pad 12. Referring again to FIG. 1, the first insulative member 14 includes therein a plurality of conductor vias 25, the second insulative member 17 contains an array of conductor vias 26, and the third insulative member 19 contains an array of conductor vias 27. Each of the conductor vias interconnects the lower surface of its respective insulative member with the upper surface. Referring to FIGs. 4-6, which are top views of the insulative members 14, 17 and 19 of FIG. 1, the first insulative member 14 includes on an upper surface a first conductor pattern 29, the second insulative member 17 includes on an upper surface a second conductor pattern 30, and the third insulative member 19 contains on an upper surface a third conductor pattern 31. The first conductor pattern 29 interconnects certain of the vias 25 with peripheral contact pads 32, the second contact pattern 30 connects certain other vias 26 with peripheral contact pads 33, and the third conductor pattern 31 interconnects vias 27 with peripheral contact pads 34. Referring to FIG. 4, it can be seen that the first insulative member 14 has conductor vias 25 at locations that match the locations of the contact pads 12 of FIG. 2. Thus, each of the contact pads 12 of FIG. 2 is connected to the upper surface of insulative member 14 by way of the anisotropic conductive member 13 and the conductor vias 25. Four of the conductor vias 25 are connected to peripheral contact pads 32 by way of the conductor pattern 29. As illustrated in FIG. 1, each of the peripheral contact pads 32 is connected in a conventional manner to a contact pad 36 of an external circuit that is illustratively supported by a substrate 37. Referring to FIG. 5, the second insulative member 17 includes conductor vias 26 corresponding to the array of FIG. 2, except at locations corresponding to those to which external contact was made by the conductor pattern 29 of FIG. 4. That is, there are no conductor vias 26 at locations matching the four central contact pads of FIG. 2. Vias 26 are therefore connected to all but four of the pads 12 of FIG. 2 by way of second anisotropic conductive member 15, conductor vias 25, and first anisotropic conductive member 13. Twelve of the conductor vias 26 are connected to peripheral contact pads 33, each of which are connected to the external circuitry by way of connections to external contact pads 38, as shown in FIG. 1. External contact to the outer contact pads 12 of the device 11 is provided by the circuit pattern 31 of insulative member 19 shown in FIG. 6. The insulative member contains conductor vias 27 only at locations corresponding to the outer contact pads 12 of the array of FIG. 2 to which connection to the external circuitry has not been previously made. Thus, electrical connection is made between the peripheral contact pads 34 and corresponding contact pads 12 of FIG. 2 by way of circuit pattern 31, conductor vias 27, anisotropic conductive member 18 of FIG. 1, the conductor vias 26, the anisotropic conductive member 15, the conductor vias 25, and the anisotropic conductive 13. As shown in FIG. 1 contact pads 34 are connected to external circuitry by means of connections to contact pads 40. From the foregoing, it can be seen that the apparatus of FIG. 1 essentially divides the array of contact pads 12 of FIG. 2 into three groups. Peripheral contacts on the insulative members 14, 17, and 19, are made to each of the three groups, and such contacts can be made on the insulative members more conveniently because the number of peripheral contacts on each insulative member is smaller than would be the case if all of the peripheral contacts were made around the periphery of the integrated circuit chip 11. In the example shown, the innermost four contacts 12 of FIG. 2 are connected to the external circuitry by way of the anisotropic conductive 23, the conductor vias 25, and the circuit pattern 29 of insulative member 14. The pitch P of each of the anisotropic conductive members 13, 15, and 18 should be smaller than the horizontal dimensions of any of the conductor vias 25, 26 and 27 to assure that dependable contact is made with all of the conductor vias. Notice that progressively more contact pads are included in FIGs. 5 and 6 than in FIG. 4. In general, it is desirable to minimize the number of connections to the innermost conductor vias as in FIG. 4, because of the relative complexity of such connections, while a relatively large number of connections can be made to the outermost vias as in FIG. 6. Nevertheless, the number of peripheral contact pads on each insulative member is a matter of design preference and clearly one could increase the number of peripheral contact pads on the upper surface of insulative member 14 of FIG. 4, if desired. For example, one could have twelve peripheral contacts for each of the insulative members 14, 17, and 19 to provide reliable external contact for the thirty-six contact pads 12 of FIG. 2. The embodiment described in detail above has been presented primarily to illustrate the principles of the invention, rather than as being the most practical embodiment of the invention. It is expected, for example, that the invention will be used for making contact to an array of 64 x 64 photodetectors, or 4,096 photodetectors. It is calculated that for such use the pitch P of the anisotropic conductive member of FIG. 3 should preferably be less than three mils. Anisotropic conductive members with such a fine pitch can be made by the techniques described in the aforementioned Hechtman et al. patent and the Fulton et al. paper. It is expected that future refinements in the production of anisotropic conductive members will make possible connections to matrix arrays of 128 x 128 photodetectors (16,384 separate devices). It can be seen that the invention offers a large degree of flexibility, and the designer is free to use any number of conductor levels that is most appropriate for the production system involved. Connection to the peripheral contact pads can be made by using any of a number of known techniques such as wire bonding and tape automated (TAB) bonding. The different insulative members can have different dimensions to expedite bonding to the peripherally located contact pads of such layers. The conductor patterns supported by the various insulative members can be used for interconnecting chips or chip elements as well as simply making external connection to a chip. For example, modem multichip modules (MCMs) typically comprise a planar silicon surface supporting a number of interconnected integrated circuit chips. The conductor patterns on the various insulative members of the invention could bridge two or more chips and provide interconnection between them; that is, specific contact pads of one chip could be connected by way of anisotropic conductive, members conductor vias and conductor patterns to specific contact pads of another chip. In wafer scale integration, redundancy is built into a circuit covering an entire wafer surface to prevent loss of the entire wafer by the failure of a single component. The invention could be used to provide tailored or customized interconnections between elements of a wafer to reduce the amount of required redundancy; that is, after fabrication, the invention could be used to provide auxiliary interconnections on the wafer surface which could be used to connect supplemental or substitute elements to a system to replace local regions of failure. The various layers of the apparatus of FIG. 1 are preferably permanently bonded together, although they could be held together by clamping apparatus. The various anisotropic conductive members may be made of adhesive materials known as "Adcon" which may aid in the bonding of the package. An advantage of a clamped unbonded apparatus is that, if desired, layers can thereafter be selectively removed, for example, for repair or replacement.

Claims: An electronic device package comprising: an electronic device (11) having on an upper surface thereof a first array of first contact pads (12) characterized by; a first flat anisotropic conductive member (13) overlying the first array of first contact pads (12); a first flat insulative member (14) overlying the first anisotropic conductive member (13) and having on an upper surface thereof a first conductor pattern (29) connected to a second array of contact pads (32); a second flat anisotropic conductive member (15) overlying the first flat insulative member (14); a second flat insulative member (17) overlying the second anisotropic conductive member (15) and having on an upper surface a second conductor pattern (30) connected to a third array of contact pads (33); means for interconnecting a first plurality of the first array of contact pads (12) to the first conductor pattern (29), said means comprising the first anisotropic conductive member (13) and a first array of conductor vias (25) extending through the first insulative member (14); means for interconnecting a second plurality of the first array of contact pads (12) to the second conductor pattern (30), said means comprising the second anisotropic conductive member (15), a second array of conductor vias (26) extending through the second insulative member (17), the first array of conductor vias (25) extending through the first insulative member (14), and the first anisotropic conductive member (13); and means (36, 38) for interconnecting at least part of the first array of contact pads (12) of the electronic device with external circuitry, said means being connected to the second and third arrays of contact pads (32, 33). The electronic device package of claim 1 further comprising: a third flat anisotropic conductive member (18) overlying the second flat insulative member (17); a third flat insulative member (19) overlying the third anisotropic conductive member (18) and having on an upper surface thereof a third conductive pattern (31) connected to a fourth array of contact pads (34); means for interconnecting a third plurality of the first array of contact pads (12) to the third conductor pattern (31), said means comprising a third array of conductor vias (27) extending through the third insulative member (19), the third anisotropic conductive member (18), the second anisotropic conductive member (15), the second array of conductor vias (26) extending through the second insulative number (17), the first anisotropic conductive member (13) and the first array of conductor vias (25) extending through the first insulative member (14); and said means for connecting the first array of contact pads (12) of the electronic device with external circuitry includes means connected to the fourth array of conductor pads (34). The electronic device package of claim 1 wherein: the flat anisotropic members each comprise an insulator sheet (22) having conductors (23) that extend through the sheet thickness, but which do not conduct electric current for significant distances in either the length or width directions of the sheet. The electronic device package of claim 3 wherein: each conductor comprises a column of ferromagnetic conductive particles (23); and the columns are formed by magnetic alignment. The electronic device package of claim 1 wherein: the electronic device comprises an integrated circuit chip (11). The electronic device package of claim 1 wherein: the electronic device comprises a matrix array of semiconductor photodetectors (20).

Inventors: NGUYEN HUNG NGOC, NGUYEN, HUNG NGOC
Applicants: AT & T CORP, AT&T CORP.
Application year: 1992
Main classification: H05K1
IPC codes: H01L23, H01L21, H01R13