A display apparatus, a drive circuit for a display apparatus, and a method of driving a display apparatus

Abstract: A method of driving a display apparatus includes the steps of receiving output requests at a interval and outputting an oscillating voltage to a source line connected to a display section, the oscillating voltage including a component which oscillates during one output period of time defined by the output requests.

Description: 1. Field of the Invention: The present invention relates to a drive circuit and a drive method for use in a plane display apparatus, particularly of the type that indicates gray-scale in accordance with digital video data. 2. Description of the Prior Art: When a liquid crystal display apparatus (hereinafter referred to as "LCD apparatus") is driven, the speed of response of the liquid crystal is slower than a luminescent material used in a CRT (cathode ray tube) display apparatus. To compensate for the slow response speed, special drive circuits are often used. One such liquid crystal drive circuit does not supply video data in succession to pixels but holds the data as signal voltages for a period of time after the data has been sampled up to the horizontal period of time (the horizontal period of time is the time that is required for a video signal to be sampled for all pixels on a horizontal scanning line). The video signal voltages are then output to all of the pixels on one scanning line at the same time, which may be at the initial moment of the horizontal period of time or at an appropriate point of time within the horizontal period of time. The video signal voltages delivered to the corresponding pixels are held for a period of time exceeding the response speed of the liquid crystal, thereby allowing the liquid crystal fully to assume the desired orientation. One known drive circuit uses capacitors to hold video signal voltage. Figure 47 shows a signal voltage output circuit (a source driver) for supplying drive voltages V S to N pixels on a selected scanning line. The signal voltage output circuit for each pixel is composed of a first analog switch SW 1 , a sampling capacitor C SMP , a second analog switch S W2 , a holding capacitor C H , and an output buffer amplifier A . This known signal output circuit will be described below with reference to the circuit diagram of Figures 47 and 48 and to the timing chart of Figure 49 . An analog video data V S input to the first analog switch SW 1 is sequentially sampled by the switch in accordance with a corresponding sampling clock signal T SMP1 to T SMPN which correspond to the N pixels on one scanning line selected by a horizontal synchronizing signal H syn . By this sampling, the sequential instantaneous voltages V SMP1 to voltages V SMPN of the video data signal V s are applied to the corresponding sampling capacitors C SMP . For example, the nth sampling capacitor C SMP will be charged to the voltage V SMPn of the video signal V S when the analog switch SW 1 corresponding to the nth pixel, receives a signal T SMPN and will hold this value. The signal voltages V SMP1 to V SMPN which are sequentially sampled and held in one horizontal period of time are transferred from the sampling capacitors C SMP to the holding capacitors C H , when an output pulse OE is supplied to all of the analog switches SW 2 at the same time. Then the signal voltages V SMP1 to V SMPN are output to source lines 0 1 to O N connected to the respective pixels through the buffer amplifiers A. The drive circuit described above, which is supplied with analog video data, suffers from the following problems when the size and resolution of the liquid crystal panel are increased: (1) When the charges in the sampling capacitors C SMP are transferred to the holding capacitors C H , the relationship between the voltage V H of the holding capacitor C H and the sampled voltage V SMP is represented by the following equation: V H = 1 1 + C H C SMP · V SMP Accordingly, in order to ensure that voltage V H held by the holding capacitor C H becomes equal to the sampled voltage V SMP , a condition of C SMP >> C H must be satisfied, i.e., the capacitance of the capacitor C SMP must be much greater than the capacitance of capacitor C H . To this end, it is necessary to use a sampling capacitor C SMP of a relatively large capacitance. However, if the capacitance of the sampling capacitor C SMP is too large, the period of time required for charging (i.e. a sampling period of time) is prolonged. However, as the size of the LCD apparatus becomes larger or the resolution is improved, the number of pixels corresponding to one horizontal period of time increases, thereby necessitating the shortening of the sampling time. Consequently, there is a limit to the increase in size or the improvement in resolution of the LCD apparatus. (2) Analog video data are supplied to the source driver via bus lines. As the size and resolution of a display apparatus are increased, the frequency band of the video signal becomes wider and the distribution capacity of the bus lines increases. This requires a wideband amplifier in the circuit for supplying video data, thereby increasing the cost of production. (3) A color display apparatus using RGB video data has bus lines for supplying multiple analog color video data. As the size and resolution of the display panel of such an apparatus are increased, the wideband amplifiers must have an extremely high signal quality so that no phase difference occurs from data to data and no dispersion occurs in the amplitude and frequency characteristics. (4) In the drive circuit for a matrix type display apparatus, unlike the display in a CRT, analog video data is sampled in accordance with a clock signal and displayed in pixels arranged in a matrix. At this time, since the bus lines unavoidably cause delays of clock signals in the drive circuit, it is difficult to locate the sampling position exactly for the analog video data. Particularly, when a computer graphic image is displayed in which the video data and pixel addresses must exactly correspond to each other, any displacement in the image display position, blurring of the image, or any other faults caused by the signal delay in the drive system and deterioration of the frequency characteristics are fatal problems. These problems which occur when using analog video data can be solved by digitizing the video signals. To supply digital data, the drive circuit shown in Figures 50 and 51 can be used. For simplicity, two bits ( D 1 , D 0 ) of data are illustrated. The video data thus has one of four values 0 to 3, and a signal voltage applied to each pixel is one of the four levels V 0 to V 3 . Figure 50 shows a digital source driver circuit equivalent to the analog source driver circuit shown in Figure 47 . The circuit diagram of Figure 50 shows the entire source driver for supplying a driving voltage to N pixels. Figure 51 shows a portion of the circuit for the nth pixel. This portion of the circuit comprises a D-type flip-flop (sampling flip-flop) M SMP at a first stage and a flip-flop (holding flip-flop) M H at a second stage which are provided with the respective bits ( D 1 , D 0 ) of the video data, a decoder DEC , and analog switches ASW 0 to ASW 3 corresponding to four external voltage sources V 0 to V 3 and a source line 0 n . For the sampling of digital video data, various circuit components other than a D-type flip-flop can be used. The digital source driver operates as follows: The sampling flip-flop M SMP samples the video data ( D 1 , D 0 ) at the rising edge of a sampling pulse T SMPn corresponding to the nth pixel. When the sampling for one horizontal period of time is completed, an output pulse OE is fed to the holding flip-flop M H . All the video data ( D 1 , D 0 ) held in the holding flip-flops M H are then simultaneously output to the respective decoders DEC . Each of the decoders DEC decodes the 2-bit video data ( D 1 , D 0 ). In accordance with the values 0 to 3, one of the analog switches ASW 0 to ASW 3 closes, and the corresponding one of the four external voltages V 0 to V 3 is output to the source line O n . The source driver using video data for sampling has solved problems 1 to 4 occurring in the use of analog video data for sampling, but nevertheless the following other problems arise: (1) With an increase in the number of bits of video data, the size of the memory cells, decoders, etc. constituting a drive circuit becomes large. (2) When voltage sources V 0 to V 3 supplied from outside in Figures 50 and 51 are selected by analog switches, the selected voltage source is directly connected to a source line of the liquid crystal panel and drives it. Accordingly, the circuit must drive a large load like the liquid crystal panel. However, it is difficult to obtain such a high power within the LSI which must be supplied with power from outside. This increases the production cost. As the number of bits increases, the number of the voltage sources increases by 2 n . As a result, an increase in the number of bits raises production cost. For example, when four-bit data ( D 0 to D 3 ) is used and a 16 gray-scale is indicated, the source driver is constructed as shown in Figure 52 which requires a signal voltage ( V 0 to V 15 ) with 2 4 (i.e. 16) levels. This requires sixteen voltage sources. (3) In proportion to the increase in the number of voltage sources by 2 2 , the number of input terminals constituting the driver circuit increases. For example, if the data is extended from 5-bits to 6-bits, the number of voltage sources (the number of input terminals) will increase from 2 5 (32) up to 2 6 (64). This makes it difficult to fabricate LSIs . In addition, the mounting and production of such LSIs become difficult. As a result, mass production becomes difficult. As the video data is composed of a greater number of bits, the number of analog switches increases by 2 2 . In addition, an ON resister is required to be inserted between the voltage source and the source line. It is desirable to minimize the resistance of the ON resister but there is a limit to the reduction of the size. As a result, the size of the chip cannot be reduced beyond a certain extent. As the number of components is increased, the power compsumption of the circuit correspondingly increases. "IBM Technical Disclosures Bulletin", Vol. 33, No 6B, November 1990, pp 384-385, on which the preambles of claims 1 and 3 are based, discloses a method of driving a display apparatus having a display section including a pixel and a switching element connected to said pixel, and a source line connected to said switching element, said method comprising the steps of: receiving output requests in a drive circuit at predetermined intervals; and outputting a voltage from said drive circuit to said source line. The document also discloses a corresponding drive circuit. In any gate-on period, the voltage output to a source line remains constant or changes only once. EP-A-0 391 655 discloses a driving circuit for a display apparatus. The intensity of the display is varied by changing the time-averaged voltage applied to a pixel. This done by changing the output voltage from one horizontal scanning period to another; the applied voltage remains constant over any individual horizontal scanning period (a "horizontal scanning period" in this document corresponds to an "output period" of the present invention). EP-A-0 387 550 discloses a driving circuit for a display apparatus. The intensity of the display is varied by changing the time-averaged voltage applied to a pixel. This done by changing the output voltage from one frame to another; the applied voltage remains constant over any individual frame (a "frame" in this document corresponds to an "output period" of the present invention). A first aspect of the present invention provides a method of driving a display apparatus having a display section including a pixel and a switching element connected to said pixel, and a source line connected to said switching element, said method comprising the steps of: receiving output requests in a drive circuit at predetermined intervals; and outputting a voltage from said drive circuit to said source line; characterised in that said voltage is an oscillating voltage including a component which repeatedly oscillates during one output period, an output period being a period from receiving one of said output requests to receiving a next one of said output requests; wherein during said one output period said source line is connected to said pixel by said switching element for charging said pixel based on said oscillating voltage. A second aspect of the present invention provides a drive circuit for a display apparatus having a display section including a pixel and a switching element connected to said pixel, and a source line connected to said switching element, said drive circuit comprising: receiving means for receiving output requests at predetermined intervals; and outputting means for outputting a voltage to said source line; characterised in that said voltage is an oscillating voltage including a component which repeatedly oscillates during one output period, an output period being a period from receiving one of said output requests to receiving a next one of said output requests through said receiving means; wherein during said one output period said source line is connected to said pixel by said switching element for charging said pixel based on said oscillating voltage. A third aspect of the present invention provides a display apparatus having a display section including: a pixel; a switching element connected to said pixel; and a source line connected to said switching element, the display apparatus comprising: a drive circuit as specified above; and reducing means for reducing the amplitude of said component of said oscillating voltage, said oscillating voltage being applied to said pixel after the amplitude of said component is reduced by said reducing means. Preferred features of the invention are set out in claims 2, 4 to 15, and 17 to 19. Thus, the invention described herein makes possible the objectives of (1) providing a drive circuit capable of low cost production, (2) providing a drive circuit suitable for a display apparatus which has numerous pixels and numerous gray-scale levels, (3) providing a drive circuit with low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1 is a schematic diagram showing a configuration of a display apparatus. Figures 2 , 3 and 4 are timing charts showing a relationship between input data, sampling pulses, output pulses, and output voltages. Figure 5 shows a waveform of a voltage output from the source driver during one output period of time. Figure 6 shows a circuit for one output of the source driver in Example 1. Figures 7A , 7B and 7C show waveforms of clock signals applied to the drive circuit in Example 1. Figures 8A , 8B , 8C and 8D show the relationships between data input to the source driver and voltages from the source driver in Example 1. Figure 9 shows an example of a periodical function. Figure 10 shows an equivalent circuit of the display apparatus. Figure 11 shows an amplitude characteristic depending on an normalized frequency. Figures 12 and 13 show equivalent circuits of the display apparatus. Figure 14 shows a circuit for one output of the source driver in Example 2. Figure 15 shows a circuit for one output of the source driver in Example 3. Figure 16 shows a relationship between a clock signal applied to the source driver and an voltage output from the source driver in Example 3. Figure 17 shows a logic circuit for the selective control circuit in Example 3. Figure 18 shows a circuit for one output of the source driver in Example 4. Figure 19 shows a logic circuit for the selective control circuit in Example 4. Figure 20 shows a circuit for one output of the source driver in Example 5. Figure 21 shows a circuit for one output of the source driver in Example 6. Figure 22 shows waveforms of clock signals applied to the source driver in Example 6. Figure 23 shows waveforms of voltages output from the source driver in Example 6. Figure 24 shows a circuit for one output of the source driver in Example 7. Figure 25 shows waveforms of clock signals applied to the source driver in Example 7. Figure 26 shows a circuit for one output of the source driver in Example 8. Figure 27 shows a logic circuit for the selective control circuit in Example 8. Figure 28 shows an equivalent circuit of the source driver. Figure 29 shows waveforms of voltages output from the source driver in Example 8. Figure 30 shows an equivalent circuit of the display apparatus. Figure 31 shows a circuit for one output of the source driver in Example 9. Figure 32 shows a logic circuit for the selective control circuit in Example 9. Figure 33 shows waveforms of clock signals applied to the source driver in Example 9. Figures 34A , 34B and 34C show waveforms of voltages output from the source driver in Example 9. Figure 35 shows a voltage characteristic for a display with multiple gradation levels. Figure 36 shows a circuit for one output of the source driver in Example 10. Figures 37A and 37B show a relationship between a clock signal applied to the source driver and a voltage output from the source driver in Example 10. Figure 38 shows a logic circuit for the selective control circuit in Example 10. Figure 39 shows a circuit for one output of the source driver in Example 11. Figures 40A and 40B show a relationship between a clock signal applied to the source driver and an voltage output from the source driver in Example 11. Figure 41 shows a logic circuit for the selective control circuit in Example 11. Figure 42 shows a circuit for one output of the source driver in Example 12. Figures 43A , 43B and 44 show waveforms of clock signals applied to the source driver in Example 12. Figures 45A , 45B , 45C and 45D show a relationship between data input to the source driver and voltages output from the source driver in Example 12. Figure 46 shows a circuit for one output of the source driver in Example 13. Figure 47 shows a circuit for an analog source driver in the prior art. Figure 48 shows a circuit for one output of an analog source driver in the prior art. Figure 49 is a timing chart of as analog source driver in the prior art. Figure 50 shows a circuit for a digital source driver in the prior art. Figure 51 shows a circuit for one output of a digital source driver in the prior art. Figure 52 shows a circuit for one output of a digital source driver in the prior art. Figure 53 shows a waveform of a voltage output from a source driver during one output period of time in the prior art. Figure 54 shows an equivalent circuit in Example 3. Figure 55 shows an equivalent circuit replaced with a concentrated constant in Example 3. Figure 56 shows a simplified equivalent circuit in Example 3. Figure 57 shows a waveform of the voltage V in input to the equivalent circuit in Example 3. Figures 58A , 58B and 58C show a process of the low-pass filter reducing the oscillating voltage. Figures 59A and 59B show a relationship between the oscillating voltage and the gate signal. Figure 60 shows a circuit for one output of a digital source driver in the prior art. DESCRIPTION OF THE PREFERRED EMBODIMENTS Example 1 In Figure 1 , the exemplary display apparatus includes a display section 100 with ( M x N ) pixels P (j=1, 2, ··· M ; i = 1, 2, ··· N) each connected to a corresponding switching element T (j= 1, 2, ··· M, i = 1, 2, ··· N) such as thin film transistors (TFTs), a source driver 101 and a gate driver 102 both for driving the display section 100 . N source lines Oi (i = 1, 2, ··· N) connect the output terminals S ( i ) (i = 1, 2, ··· N) of the source driver 101 to the switching elements T (j, i). Gate lines Lj (j = 1, 2, ··· M) connect the output terminals G (j) (j = 1, 2, ··· M) of the gate driver 102 to the switching elements T (j, i). A voltage of a high level is successively output to the gate lines Lj through the output terminals G (j) of the gate driver 102 in predetermined cycles over a period of time. Hereinafter, this period of time will be referred to as "one horizontal period of time jH " (j=1, 2, ··· M). The total sum of all the horizontal periods of time jH constitutes one "vertical" period of time. When the voltage applied to the gate line Lj from the output terminals G ( j ) has a high level, the switching element T ( j , i ) is turned on. When the respective switching element T ( j , i ) is on, the respective pixel P ( j , i ) is charged in accordance with the voltage applied to the source line Oi from the output terminals S ( i ) of the source driver 101 . The voltage is maintained at a constant level and applied to the pixel throughout the vertical period of time. Figure 2 shows the relationship among digital video data DA for the jth horizontal period of time jH , a sampling pulse T SMPi , and a output pulse signal OE . The sampling pulses T SMP1 , T SMP2 , ··· T SMPi ··· T SMPN are applied to the source driver 101 , causing the digital video data DA 1 , DA 2 , ··· DA i , ··· DA N to be latched and held by the source driver 101 . When the source driver 101 receives the jth pulse signal OEj (j=1, 2, ··· M) controlled by the output pulse signal OE , the output terminal S ( i ) outputs a voltage. Figure 3 shows the relationship among a horizontal synchronizing signal H syn for a vertical period of time controlled by a vertical synchronizing signal V syn , digital video data DA , an output pulse signal OE , the output timing of the source driver, and the output timing of the gate driver. In Figure 3 , the source ( j ) are indicated by hatching, so as to totally show the levels of the voltages from N output terminals of the source driver 101 at the intervals shown in Figure 2 . While voltages represented by the source ( j ) are applied to the source lines Oj , the voltage through the jth output terminal G ( j ) has a high level, and all of the N switching elements T ( j , i ) (i=1, 2, ··· N) connected to the jth gate line Lj become on. As a result, the pixels P ( j , i ) are charged in accordance with the voltages applied to the source lines Oj . The same procedure is repeated M times for the sources ( j ) being 1, 2,··· M, and an image for one vertical period of time (in the case of non-interlace, this image covers the whole screen) is displayed. Hereinafter, the period of time from the supply of the jth pulse signal to the supply of the next pulse signal OEj+1 is called "one output period of time". One output Period corresponds to each period of time indicated by the source ( j ) (j=1, 2, ··· M) in Figure 3. Figure 4 shows the levels of voltages applied to the pixels P ( j , i ) (j=1, 2, ··· M). Figure 5 shows a voltage signal waveform applied to the source line Oi for one output period of time. The voltage signals applied to the source line Oi are at a constant level for one output period of time under the conventional system (see, Figure 53 ). According to the present invention, the voltage signals have oscillating components during one output period of time. The operation of the drive circuit for outputting a voltage signal having oscillating components during one output period of time will be described: Figure 6 shows a portion of the driver circuit allocated for one output of the source driver 101 . For simplicity, the data input to the drive circuit ( DA i (i=1, 2, ···, N) as shown in Figure 2 ) consists of two bits. As shown in Figure 6 , the operation of the sampling flip-flop M SMP , the holding flip-flop M H , and the decoder DEC , and the generation of sampling pulses T SMPn , output pulse OE , and the outputs Y 0 to Y 3 of the decoder DEC are conducted in the same manner as in the known circuit shown in Figure 51 . AND circuits 602 and 603 , and an OR circuit 604 are disposed toward the output of the decoder DEC . The outputs Y 1 and Y 2 of the decoder DEC are connected to inputs of the AND circuits 602 and 603 respectively. The outputs of the AND circuits 602 and 603 are connected to the inputs of the OR circuit 604 . The output Y 3 is directly connected to the OR circuit 604 . If either input of the OR circuit 604 is a binary "1", then the OR circuit outputs a voltage of a value V D over the source line O n . If all inputs of the OR circuit 604 are binary "0", then the OR circuit outputs a voltage of a value V GND over the source line O n . The OR circuit 604 is designed to drive the source line O n regardless of any load thereof. The other inputs of the AND circuits 602 and 603 receive signals TM 1 and TM 2 , respectively. Figures 7A and 7B show waveforms of the signals TM 1 and TM 2 , and Figure 7C shows a portion of the signal TM 1 . The signals TM 1 and TM 2 are a rectangular-shape pulse signal having the duration of "1", and "0" which alternately appear. A signal has a ratio ( n : m ) of duration "1" to "0", called a duty ratio. The signal TM 1 has a duty ratio as being 1:2, and the signal TM 2 has a duty ratio as being 2:1. When digital data ( D 1 , D 0 ) {(0, 0)} is input to the source driver, the output Y 0 of the decoder DEC becomes "1", and the other outputs Y 1 , Y 2 and Y 3 become "0". Since all the inputs of the OR circuit 604 become "0", and the output of the OR circuit has a constant value V GND as shown in Figure 8A . When the digital video data ( D 1 , D 0 ){(0, 1)} is input, the output Y 1 of the decoder DEC becomes "1", and the other outputs Y 0 , Y 2 and Y 3 become "0". As a result, one of inputs of the OR circuit 604 becomes "1" in the same cycle as the signal TM 1 . The output of the OR circuit 604 thus becomes an oscillating voltage having a waveform which oscillates between voltages V D and V GND at the same duty ratio as that of the signal TM 1 (n:m=1:2) as shown in Figure 8B . When the digital video data ( D 1 , D 0 ){(1, 0)} is input, the output Y 2 of the decoder DEC becomes "1", and the other outputs Y 0 , Y 1 and Y 3 become "0". As a result, one of the inputs of the OR circuit 604 becomes "1" in the same cycle as the signal TM 2 . The output of the OR circuit 604 thus becomes an oscillating voltage having a waveform which oscillates between voltages V D and V GND at the same duty ratio as that of the signal TM 2 (n:m = 2:1) as shown in Figure 8C . When the digital video data ( D 1 , D 0 ){(1, 1)) is input, the output Y 3 of the decoder DEC becomes "1", and the other outputs Y 0 , Y 1 and Y 2 become "0". As a result, the output of the OR circuit 604 becomes a voltage having a constant value V D as shown in Figure 8D . When the digital video data ( D 1 , D 0 ) is (0,1) or (1,0), a mean value of the output of the OR circuit 604 , that is, a mean value of the voltage applied to the source line O n is expressed by: n · V D + m · V GND n + m When the ground voltage level V GND is O V in the above expression, a mean value of the voltage applied to the source line O n is expressed by: n n + m V D Since the duty ratio (n:m) of the signal TM 1 is set to 1:2 as described above, if the digital video data ( D 1 , D 0 ) is (0, 1), then the mean value of oscillating voltages output from the OR circuit 604 becomes, is (1/3) V D . Since the duty ratio (n:m) of the signal TM 2 is set to 2:1, if the digital video data ( D 1 , D 0 ) is (1,0), then the mean value of the oscillating voltage output from the OR circuit 604 becomes (2/3) V D . When the signals TM 1 and TM 2 have a frequency higher than a cut-off frequency of a low-pass filter inherent in the source line, and the OR circuits 604 has power enough to drive the source line, the voltage applied to the pixels exhibit various values as follows: If the digital video data ( D 1 , D 0 ) = (0, 0), then the voltage value is 0. If ( D 1 , D 0 ) = (0, 1), then it is (1/3) V D . If ( D 1 , D 0 ) = (1, 0), then it is (2/3) V D , and if ( D 1 , D 0 ) = (1, 1), then it is V D . Thus, voltages apply to the pixels according to the digital video data. This will be described in greater detail below: Figure 9 shows a voltage v (t) which oscillates with a cycle of 2π. The oscillating voltage shown in Figure 9 is only an example, and oscillating voltages having a given waveform are applicable if they can be a periodic function as a voltage applied to the source line from the driving circuit. The function f having a cycle 2π is expressed by the following Fourier series: It is evident that actual voltage waveform can be integrated and therefore the periodic voltage v (t) can be expressed by: In the equation above, a 0 /2 is constant. Accordingly, the equation shows that the voltage v (t) is formed by infinitely adding a d.c. component a 0 /2, a basic periodic component having a cycle 2π, a second harmonic component, a third harmonic component and etc. When the voltage v (t) is passed through a low-pass filter having a cut-off frequency of greater length than 2π, the second term in the equation will be removed. As a result, a d.c. component a 0 /2 can be obtained. The d.c. component a 0 /2 is expressed by: The equation above shows that the d.c. component of the voltage v (t) has a mean value of the voltages v (t). Thus, it is understood a mean value of the voltage v (t) is obtained as an output from the low-pass filter, when the voltage v (t) is passed through the low-pass filter. Figure 10 shows an equivalent circuit extended from the drive circuit to the pixels according to the present invention. There are provided a resistance R S of the source line, a capacitance C s thereof, and a voltage V COM of a counter electrode. Actual capacitance C LC of the pixels (including an auxiliary capacitance inherent in the pixels) is connected in parallel to the capacitance C S but since the capacitance C S is greater than the capacitance C LC , the latter is negligible as an equivalent circuit, in that the voltage applied to the pixels is equivalent to the voltage at a point A of the resistance R S and capacitance C S . It is understood that the equivalent circuit shown in Figure 10 functions as a primary low-pass filter, which includes the resistance R S and the capacitance C S . When the periodic oscillating voltage v (t) is applied to the input of this primary low-pass filter, the voltage applied to the pixels becomes almost equal to a mean value of the voltage v (t) at the point A under the condition that the cycle of the voltage v (t) is adequately shorter than that of the cut-off frequency of the low-pass filter. A transmission function T (j ω) of the equivalent circuit in Figure 10 is represented by: T(jω) = V out V in = 1 1 + jω CR Herein, with 1/C S R S = ω 0 , the function T(j ω) is represented by: T(jω) = ω 0 ω 0 + jω Both the denominator and the numerator are divided by ω 0 to normalize the function, the function T(j ω) is represented by: T(jω) = 1 1 + j ω ω 0 Where, ω/ω 0 represents a normalized frequency. An amplitude characteristic function |T| of the function T(jω) is represented by: |T| = 1 1 + ( ω ω 0 ) 2 Figure 11 shows an amplitude value of the function |T| according to a normalized frequency (ω/ω 0 ). Figure 11 teaches that if a normalized frequency ω / ω 0 is 100, the amplitude of the oscillating voltage at the point A in Figure 10 amounts to 1/100 of that of the oscillating voltage output from the drive circuit. The value of ω / ω 0 is appropriately determined depending upon the differences Δ V (= V n - V n-1 ) between the adjacent voltage levels and the required display quality. For example, when Δ V is 5 V, and the tolerance of the required display quality is within 0.05 V, the value ω/ω 0 must be 100 or more. If C S R S is 10 x 10 -6 , the frequency of the oscillating voltage must be 1.6 MHz or more. Refer to the following equations. ω ω 0 = 100 ω 0 = 2π f 0 , ω = 2π f 2π f 2π f 0 = 100 ∴ f = 100 · f 0 f 0 = ω 0 2π ω 0 = 1 C S R S = 1 10 x 10 -6 = 10 5 f 0 = 10 5 2π = 1.6 x 10 4 f 0 = 16 KHz ∴ f = 1.6 MHz In the illustrated embodiment the low-pass filter is achieved by making use of the resistance and capacitance of the source line. Furthermore, as shown in Figure 12 it is possible to obtain the low-pass filter by use of the capacitance C LC of the pixels and the resistance Rt of a switching element connecting the pixels to the source line. In the latter case, it is presupposed that the capacitance and resistance of the source line are zero. On the other hand, in the former case, the capacitance of the pixels and the resistance of the switching elements are ignored. In actual liquid crystal panels, it is considered that neither state can singly occur but they occur in combination. Actually the low-pass filter functions as a secondary low-pass filter as shown in Figure 13 . In the illustrated embodiment, the low-pass filter is achieved by utilizing components inherent to the construction of a liquid crystal display apparatus. Furthermore, it is possible to modify a design of a display apparatus so as to adapt the characteristic of the display apparatus to the drive mechanism of the present invention, and/or to add a special filtering circuit or elements to the display apparatus (especially the source line) so as to secure an optimum cut-off frequency and/or to impart the characteristic of a secondary low-pass filter to the display apparatus. Figures 58A , 58B and 58C illustrate a process of the low-pass filter reducing the amplitude of the oscillating voltage. The oscillating voltage shown in Figure 58A is changed to the voltage shown in Figure 58B , and finally changed to the voltage shown in Figure 58C through the low-pass filter. Figures 59A and 59B show a relationship between the oscillating voltage and a gate signal. When the gate signal is in on-state shown in Figure 59B , the oscillating voltage oscillates as shown in Figure 59A . Example 2 Figure 14 shows a circuit for one output of the source driver 101 in the drive circuit. For simplicity, a digital video data input to the drive circuit consists of two bits ( D 1 , D 0 ). Outputs Y 0 to Y 3 of the decoder DEC are input to one terminal of the AND circuits 1401 to 1404 respectively, and signals TM 0 are input to the other terminals thereof respectively. The output of the OR circuit 1405 are applied to the source line O n . The duty ratios of the signals TM 0 to TM 3 are appropriately set so as to apply a desired voltage between a first voltage V D and a second voltage (ground level voltage) V GND to the pixels. When mean voltage values depending upon the duty ratios of the signals TM 0 to TM 3 are V 0 to V 3 respectively, the relationship between the digital video data ( D 1 , D 0 ) and the voltages applied to the pixels is shown in Table 1: D 1 D 0 Voltages 0 0 V 0 0 1 V 1 1 0 V 2 1 1 V 3 In this way, according to Example 2, four arbitary voltages can be applied to the pixels. The drive circuit of Example 2 is the same as that of prior art shown in Figure 51 in terms of the voltages which are applied to the pixels. However, the drive circuit of Example 2 requires neither the analog switches nor the external sources required by the prior art for supplying voltages V 0 to V 3 . Instead, the drive circuit of Example 2 requires four AND circuits 1401 to 1404 and one OR circuit 1405 . All of these circuits are basic logic circuits. The drive circuit of Example 2 also requires a signal generator circuit (not shown) for generating signals TM 0 to TM 3 . As the signal generator circuit is known to be easily realized within an LSI , the description of the circuit is omitted herewith. Example 3 Figure 15 shows a circuit for one output of the source driver 101 . In the drive circuit. Digital video data input to the drive circuit consists of three bits ( D 2 , D 1 , D 0 ). Hereinafter, numerals enclosed by [ ] indicate decimal numbers, and those enclosed by " " indicate binary numbers. The sampling memory M SMP and the holding memory M H are operated in the same manner as shown in Figure 51 . The digital video data ( D 2 , D 1 , D 0 ) are latched by the sampling memory M SMP at the rising edge of the sampling pulse T SMPn , and latched by the holding memory M H at the rising edge of the output pulse OE . In Example 3, each output of the holding memory M H is connected to the inputs d 0 , d 1 and d 2 of the selective control circuit SCOL to which a signal t is also applied as a clock pulse. From five output terminals S 0 , S 2 , S 4 , S 6 and S 8 of the selective control circuit SCOL , control signals for controlling the "on" or "off" state of the corresponding analog switches ASW 0 , ASW 2 , ASW 4 , ASW 6 and ASW 8 are output. Five distinct voltages V 0 , V 2 , V 4 , V 6 and V 8 ( V 0 < V 2 < V 4 < V 6 < V 8 or V 8 < V 6 < 4 < V 2 < V 0 ) are supplied to the input terminals of corresponding analog switches. As a device for supplying a plurality of voltages is known, the description thereof is omitted for simplicity. Table 2 shows the relationship between the inputs and outputs of the selective control circuit SCOL . The blank spaces indicate "0", t indicates that if the signal t is "1", then the output is "1", else the output is "0", t indicates that if the signal t is "1", then the output is "0", else the output is "1". Decimal Numbers d 2 d 1 d 0 S 0 S 2 S 4 S 6 S 8 O n 0 0 0 0 1 V 0 1 0 0 1 t t V 0 + V 2 / 2 2 0 1 0 1 V 2 3 0 1 1 t t V 2 + V 4 / 2 4 1 0 0 1 V 4 5 1 0 1 t t V 4 + V 6 / 2 6 1 1 0 1 V 6 7 1 1 1 t t V 6 + V 8 / 2 Referring to Table 2, the operation of the selective control circuit SCOL will be described: When digital video data is [0], the analog switch ASW 0 is "on" in response to a signal output from the output terminal S 0 of the selective control circuit SCOL . As a result, the voltage V 0 is applied to the source line O n . When the digital video data is [2], the analog switch ASW 2 is "on" in response to a signal output from the output terminal S 2 . As a result, the voltage V 2 is applied to the source line O n . When the digital video data is [4], the analog switch ASW 4 is "on" in response to a signal output from the output terminal S 4 . As a result, the voltage V 4 is applied to the source line O n . When the digital video data is [6], the analog switch ASW 6 is "on" in response to a signal output from the output terminal S 6 . As a result, the voltage V 6 is applied to the source line O n . When the digital video data is [1], the signal t is output from the output terminal S 0 of the selective control circuit SCOL , and the signal t (i.e. the inverted signal t ) is output from the output terminal S 2 thereof. In this way, when the signal t is "1", the analog switch ASW 0 becomes "on", thereby applying the voltage V 0 to the source line O n . When the signal t is "0", the analog switch ASW 2 is also "on" since the signal t is "1", thereby applying the voltage V 2 to the source line O n . Since the signal t is a clock pulse signal, the voltage applied to the source line is an voltage oscillating in the same cycles as those of the clock pulse signal t . In Figure 16 , since the duty ratio of the signal t is 50%, the mean value of the voltages applied to the source line O n becomes ( V 0 + V 2 )/2. Likewise, when the video data is [3], the analog switches ASW 2 and ASW 4 alternately are "on", thereby outputting a voltage oscillating between the voltages V 2 and V 4 . When the video data is [ 5], the analog switches ASW 4 and ASW 6 alternately are "on", thereby outputting a voltage oscillating between the voltages V 4 and V 6 . When the video data is [ 7], the analog switches ASW 6 and ASW 8 alternately are "on", thereby outputting a voltage oscillating between the voltages V 6 and V 8 . When the video data is [3], [5] and [7], the mean values of the voltages applied to the source line O n are respectively ( V 2 + V 4 )/2, ( V 4 + V 6 )/2, ( V 6 + V 8 )/2. Figure 54 shows an equivalent circuit from the drive circuit to a TFT (thin film transistor) liquid crystal panel. In Figure 54 , R ASW represents a resistance which occurs when an analog switch is in on-state, r CONCT represents a resistance which occurs because of the connection between the drive circuit and a source line of the liquid crystal panel, and r and c represent a resistance and a capacitance which exist as a distributed constant in the source line of the liquid crystal panel. V COM represents a counter voltage applied to the counter electrode (not shown) of the liquid crystal panel. In view of the load of the output terminal at the point A shown in Figure 54 , the distributed constant r and c can be replaced with a concentrated constant r ST and C . Figure 55 shows such a replaced equivalent circuit. A time constant which usually appears in a source line of the liquid crystal panel is equal to the concentrated constant. If R ASW + r CONCT + r ST in Figure 55 is replaced with one resistance R , Figure 56 is obtained. The equivalent circuit shown in Figure 56 is regarded as an equivalent circuit for one output of the drive circuit. As shown in Figure 56 , since the capacitance of the capacitor C is much greater than that of the capacitor C LC of the pixel, the capacitance of the capacitor C LC is negligible regarding the operation of the drive circuit. It is also presupposed that a resistance which occurs when a switching element TFT (not shown) is in on-state is negligible. Accordingly, it can be understood that the pixel is charged in accordance with the voltage at the point B in Figure 56 . Figure 57 shows a waveform of the voltage V in which is input to the equivalent circuit shown in Figure 56 (in other words, the oscillating voltage output from the output terminal of the drive circuit to the source line) when the digital video data is [1]. In Figure 57 , the oscillating voltage is normalized so that the period of the oscillating voltage is equal to 2π on the axis τ. As described in Example 1, the oscillating voltages are applied to the pixels through the low-pass filter wherein a signal t having a frequency greater than a frequency inherent to the low-pass filter is selected and applied to the selective control circuit SCOL , thereby applying a voltage which value is substantially equal to ( V 0 + V 2 )/2 for practical use to the pixels. The same procedure takes place when the digital video data is [3], [5] and [7], which will be described in greater detail below: Referring to Figure 11 , it is understood that when a normalized frequency ω /ω 0 is 10, the amplitude of the oscillating voltage at the point B in Figure 56 amounts to 1/10 of that of the oscillating voltage output from the drive circuit. The value of ω /ω 0 is appropriately determined depending upon the difference Δ V (= V n - V n-1 ) between the adjacent voltage levels and the required display quality. For example, when Δ V is 1 V, and the tolerance of the required display quality is within 0.1 V, it is enough that the value of ω/ω 0 is 10. If CR is 5 x 10 -6 , the frequency of the oscillating voltage must be 320 kHz or more. In actual liquid crystal panels, the value of CR is approximately 5 x 10 -6 to 10 x 10 -6 . One output period of time is about 30 µsec. If a liquid crystal panel is used as a display for a computer. At a result, when an oscillating voltage whose frequency is 320 kHz is applied, one output period of time includes 10 periods of the oscillating voltage. There is no theoretical upper limit on the frequency of the signal t . However, the frequency of the signal t is actually limited because of the characteristics of analog switches ASW 0 to ASW 8 . According to an experiment of driving an actual liquid crystal panel by the use of the signal t which has the frequency of 100 kHz - 25 MHz, there is no difference in the display quality, compared to the case in which a voltage having a value ( V n + V n+1 )/2 is supplied directly to the source line O n . For above-mentioned reasons, it is apparent that the tolerance for the frequency of the oscillating voltage is very broad. The resistance R and the capacitance C as shown in Figure 56 vary among the pixels of a liquid crystal panel. Actually some pixels are arranged close to the output terminals of the source driver 101 , and others are arranged far from the output terminals of the source driver 101 . As a result, it is considered that it is necessary to adjust the resistance R and the capacitance C depending upon the distances from the output terminals of the source driver 101 in some cases. However, since the tolerance for the frequency of the oscillating voltage is very broad as mentioned above, the smallest value of the resistance R and the capacitance C makes it possible to absorb the unevenness which depends upon liquid crystal panels and the distances from the output terminals of the source driver. In addition, there provided a function as a low-pass filter in actual liquid crystal panels. The low-pass filter is caused by a resistance which occurs when a switching element TFT is in on-state and a capacitance of the pixel. This is an advantageous condition especially for the pixels arranged close to the output terminals of the source driver. Figure 17 shows a logic circuit for the selective control circuit SCOL as shown in Figure 15 . The logic circuit is provided from the following logic expressions which are derived from Table 2. S 0 =(0)+(1)t S 2 =(1) t +(2)+(3)t S 4 =(3) t +(4)+(5)t S 6 =(5) t +(6)+(7)t S 8 =(7) t (0)= d 2 d 1 d 0 (1)= d 2 d 1 d 0 (2)= d 2 d 1 d 0 (3)= d 2 d 1 d 0 (4)=d 2 d 1 d 0 (5)=d 2 d 1 d 0 (6)=d 2 d 1 d 0 (7)=d 2 d 1 d 0 Example 4 Figure 18 shows a circuit for one output of the source driver 101 in the drive circuit. Figure 19 shows a logic circuit for the selective control circuit SCOL for the source driver. In Figure 18 , the circuit is modified to change the supplied voltage V 8 as shown in Figure 15 to a voltage V 7 , and to change the analog switch ASW 8 as shown in Figure 15 to a analog switch ASW 7 . In this circuit, when digital video data is [7], the voltage V 7 is applied to the source line On. Table 3 is a logic table which defines an operation of the selective control circuit SCOL in the source driver. In Figure 15, the voltage V 8 is not applied to the source line. On the other hand, in Figure 18 , the voltage V 7 is applied to the source line. Thus, the circuit in Figure 18 is more reasonable than that in Figure 15 for the practical use. Decimal Numbers d 2 d 1 d 0 S 0 S 2 S 4 S 6 S 7 O n 0 0 0 0 1 V 0 1 0 0 1 t t V 0 + V 2 / 2 2 0 1 0 1 V 2 3 0 1 1 t t V 2 + V 4 / 2 4 1 0 0 1 V 4 5 1 0 1 t t V 4 + V 6 / 2 6 1 1 0 1 V 6 7 1 1 1 t t V 7 Example 5 Figure 20 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of four bits. Table 4 is a logic table which defines an operation of the selective control circuit SCOL in the source driver. Decimal Numbers d 3 d 2 d 1 d 0 S 0 S 2 S 4 S 6 S 8 S 10 S 12 S 14 S 15 0 0 0 0 0 1 1 0 0 0 1 t t 2 0 0 1 0 1 3 0 0 1 1 t t 4 0 1 0 0 1 5 0 1 0 1 t t 6 0 1 1 0 1 7 0 1 1 1 t t 8 1 0 0 0 1 9 1 0 0 1 t t 10 1 0 1 0 1 11 1 0 1 1 t t 12 1 1 0 0 1 13 1 1 0 1 t t 14 1 1 1 0 1 15 1 1 1 1 1 Table 5 teaches that seven complement voltages can be obtained from nine given voltages, thereby a source driver capable of driving a display apparatus with 16 gradation levels is realized. Decimal Numbers d 3 d 2 d 1 d 0 O n 0 0 0 0 0 V 0 1 0 0 0 1 1 / 2 (V 0 + V 2 ) 2 0 0 1 0 V 2 3 0 0 1 1 1 / 2 (V 2 + V 4 ) 4 0 1 0 0 V 4 5 0 1 0 1 1 / 2 (V 4 + V 6 ) 6 0 1 1 0 V 6 7 0 1 1 1 1 / 2 (V 6 + V 8 ) 8 1 0 0 0 V 8 9 1 0 0 1 1 / 2 (V 8 + V 10 ) 10 1 0 1 0 V 10 11 1 0 1 1 1 / 2 (V 10 + V 12 ) 12 1 1 0 0 V 12 13 1 1 0 1 1 / 2 (V 12 + V 14 ) 14 1 1 1 0 V 14 15 1 1 1 1 V 15 Example 6 Figure 21 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of six bits. As shown in Figure 21 , four distinct signals t 1 , t 2 , t 3 and t 4 are applied to the selective control circuit in the source driver. Figure 22 shows waveforms of these signals. In this example, duty ratios of the signals t 1 , t 2 , t 3 and t 4 are set to 7:1, 6:2, 5:3 and 4:4, respectively. Table 6 is a logic table which defines an operation of the selective control circuit SCOL in the source driver. Figure 23 shows oscillating voltages output to the source line according to Table 6 when the value of the digital video data is not a multiple of eight. Thus, 56 complement voltages can be obtained from nine given voltages, thereby the source driver capable of driving a display apparatus displaying with 64 gradation levels is realized. Example 7 Figure 24 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of eight bits. As shown in Figure 24 , sixteen distinct signals t 1 to t 16 are applied to the selective control circuit in the source driver. Figure 25 shows waveforms of these signals. In this example, duty ratios of the signals t 1 to t 16 are set to 31:1, 30:2, 29:3, 28:4, 27:5, 26:6, 25:7, 24:8, 23:9, 22:10, 21:11, 20:12, 19:13, 18:14, 17:15 and 16:16, respectively. According to a logic table like Table 6, a plurality of complement voltages can be obtained. Table 7 teaches that 248 complement voltages can be obtained from nine given voltages, thereby the source driver capable of driving a display apparatus with 256 gradation levels is realized. Value of lower five bits (Decimal numbers) Complement voltages Value of lower five bits (Decimal numbers) Complement voltages 1 31V 32n + V 32(n+1) / 32 17 15V 32n + 17V 32(n+1) / 32 2 30V 32n + 2V 32(n+1) / 32 18 14V 32n + 18V 32(n+1) / 32 3 29V 32n + 3V 32(n+1) / 32 19 13V 32n + 19V 32(n+1) / 32 4 28V 32n + 4V 32(n+1) / 32 20 12V 32n + 20V 32(n+1) / 32 5 27V 32n + 5V 32(n+1) / 32 21 11V 32n + 21V 32(n+1) / 32 6 26V 32n + 6V 32(n+1) / 32 22 10V 32n + 22V 32(n+1) / 32 7 25V 32n + 7V 32(n+1) / 32 23 9V 32n + 23V 32(n+1) / 32 8 24V 32n + 8V 32(n+1) / 32 24 8V 32n + 24V 32(n+1) / 32 9 23V 32n + 9V 32(n+1) / 32 25 7V 32n + 25V 32(n+1) / 32 10 22V 32n + 10V 32(n+1) / 32 26 6V 32n + 26V 32(n+1) / 32 11 21V 32n + 11V 32(n+1) / 32 27 5V 32n + 27V 32(n+1) / 32 12 20V 32n + 12V 32(n+1) / 32 28 4V 32n + 28V 32(n+1) / 32 13 19V 32n + 13V 32(n+1) / 32 29 3V 32n + 29V 32(n+1) / 32 14 18V 32n + 14V 32(n+1) / 32 30 2V 32n + 30V 32(n+1) / 32 15 17V 32n + 15V 32(n+1) / 32 31 V 32n + 31V 32(n+1) / 32 16 16V 32n + 16V 32(n+1) / 32 wherein n = 0, 1, ... 7 Example 8 Figure 26 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of three bits ( D 2 , D 1 , D 0 ). As shown in Figure 26 , one signal t 1 is applied to the selective control circuit SCOL in the source driver. In this example, a duty ratio of the signal is set to 1:1. Figure 27 shows a logic circuit for the selective control circuit SCOL . Table 8 is a logic table which defines an operation of the selective control circuit SCOL . Decimal Numbers d 3 d 2 d 1 d 0 S 0 S 4 S 8 S 12 S 16 0 0 0 0 0 1 1 0 0 0 1 1 t 1 2 0 0 1 0 1 1 3 0 0 1 1 t 1 1 4 0 1 0 0 1 5 0 1 0 1 1 t 1 6 0 1 1 0 1 1 7 0 1 1 1 t 1 1 8 1 0 0 0 1 9 1 0 0 1 1 t 1 10 1 0 1 0 1 1 11 1 0 1 1 t 1 1 12 1 1 0 0 1 13 1 1 0 1 1 t 1 14 1 1 1 0 1 1 15 1 1 1 1 t 1 1 As shown in Table 8, the left column shows the value of digital video data input to the source driver in decimal notation. The center column shows data ( d 3 , d 2 , d 1 , d 0 ) input to the selective control circuit SCOL in binary notation. The right column shows control signals output from output terminals of the selective control circuit SCOL . In the table, t 1 represents that if the signal t 1 is "1", then the control signal is "1", else the control signals is "0". In Figure 26 , analog switches ASW 0 to ASW 16 are "on" when the corresponding control signals are "1". Figure 27 shows a logic circuit for the selective control circuit SCOL . The logic circuit is provided from the following logic expressions which are derived from Table 8. S 0 = [0] A S 4 = [0] B + [4] A S 8 = [4] B + [8] A S 12 = [8] B + [12] A S 16 = [12] B [0] = d 3 · d 2 [4] = d 3 · d 2 [8] = d 3 · d 2 [12] = d 3 · d 2 A = (0) + (1) + (2) + (3)t B = (1)t + (2) + (3) (0) = d 1 · d 0 (1) = d 1 · d 0 (2) = d 1 · d 0 (3) = d 1 · d 0 A minimization is not considered regarding the logic circuit as shown in Figure 27 . However, since a plurality of selective control circuits SCOLs are required, the number being equal to the number of outputs of the source driver, it is required to minimize the logic circuit as possible. As shown in Table 8, when the digital video data is 0 (d 0 = d 1 = d 2 =d 3 = "0"), the corresponding analog switch ASW 0 is "on" according to a control signal output from the output terminal S 0 of the selective control circuit SCOL , thereby the voltage V 0 which is supplied to the analog switch ASW 0 is output to the source line. In the same way, when the digital video data is 4 (d 0 = d 1 = d 3 = "0", d 2 = "1"), 8 (d 0 = d 1 = d 2 = "1", d 3 = "0"), and 12 (d 0 = d 1 = "0", d 2 = d 3 = "1"), the voltages V 4 , V 8 , and V 12 respectively are output. When the digital video data is 6 (d 0 = d 3 = "0", d 1 = d 2 = "1"), the corresponding analog switches ASW 4 and ASW 8 are "on" at the same time according to control signals output from the output terminals S 4 and S 8 . Figure 28 shows an equivalent circuit from the output terminals S 4 and S 8 to the output terminal of the drive circuit under the condition that each resistance of the analog switches ASW 4 and ASW 8 is equal to r. Referring to Figure 28 , it is understood that the voltage applied to the source line O n is ( V 4 + V 8 )/2. In the same way, when the digital video data are 2(d 1 ="1", d 0 =d 2 =d 3 ="0"), 10(d 0 =d 2 ="0", d 1 =d 3 ="1"), and 14(d 0 ="0", d 1 =d 2 =d 3 ="0"), the voltages (V 0 +V 4 )/2, (V 8 +V 12 )/2 and (V 12 +V 16 )/2 respectively are output. When the digital video data is 5(d 0 =d 2 ="1", d 1 =d 3 ="0"), the corresponding analog switch ASW 4 is "on" according to a control signal output from the output terminal S 4 , and the corresponding analog switch ASW 8 is "on" according to a control signal which is changed based on the signal t 7 output from the output terminal S 8 . Thus, in this case, there exists some time when both of the analog switches ASW 4 and ASW 8 are "on", thereby the voltage ( V 4 + V 8 )/2 is output, and other time when the only analog switch ASW 4 is "on",thereby the voltage V 4 is output. The control signal may be changed at least once during one output period of time. Figure 29 shows an oscillating voltage output to the source line when the digital video data is 5(d 0 =d 2 ="1", d 1 =d 3 ="0"). The oscillating voltage oscillates between the voltage V 4 and ( V 4 + V 8 )/2 and a mean value of the oscillating voltage is { V 4 +( V 4 + V 8 )/2}/2=(3 V 4 + V 8 )/4. Since the oscillating voltage is passed through the low-pass filter discussed above, the mean value of the oscillating voltage is obtained at the point B in Figure 30 . In the same way, when the digital video data are 1(d 0 ="1", d 1 =d 2 =d 3 ="0"), 9(d 0 =d 3 ="1", d 1 =d 2 ="0"), and 13(d 1 ="0", d 0 =d 2 =d 3 ="1"), mean values of the oscillating voltages output to the source line are ( 3V 0 + V 4 )/4, ( 3V 8 + V 12 )/4, and ( 3V 12 + V 16 )/4 respectively. When the digital video data is 7(d 0 =d 1 =d 2 ="1", d 3 ="0"), the corresponding analog switch ASW 4 is "on" according to a control signal which is changed based on the signal t 1 output from the output terminal S 4 , and the corresponding analog switch ASW 8 is "on" according to a control signal output from the output terminal S 8 . Thus, in this case, there exists some time when both of the analog switches ASW 4 and ASW 8 are "on", thereby the voltage ( V 4 + V 8 )/2 is output, and the other time when the only analog switch ASW 8 is "on", thereby the voltage V 8 is output. The control signal may be changed at least once during one output period of time. An oscillating voltage output to the source line oscillates between the voltages ( V 4 + V 8 )/2 and V8 , and a mean value of the oscillating voltage is {( V 4 + V 8 )/2+ V 8 }/2=( V 4 + 3V 8 )/4 . Since the oscillating voltage is passed through the low-pass filter discussed above, the mean value of the oscillating voltage is obtained at the point B in Figure 30 . In the same way, when the digital video data are 3(d 0 =d 1 ="1", d 2 =d 3 ="0") , 11(d 0 =d 1 =d 3 ="1", d 2 ="0"), and 15(d 0 =d 1 =d 2 =d 3 ="1"), mean values of the oscillating voltages output to the source line are ( V 0 + 3V 4 )/4, ( V 8 + 3V 12 )/4, and ( V 12 + 3V 16 )/4 respectively. Table 9 shows a relationship between digital video data and obtained voltages. Decimal Numbers d 3 d 2 d 1 d 0 Voltages (Figure 26) Voltages (Figure 52) 0 0 0 0 0 V 0 V 0 1 0 0 0 1 3V 1 + V 4 / 4 V 1 2 0 0 1 0 V 0 + V 4 / 2 V 2 3 0 0 1 1 V 0 + 3V 4 / 4 V 3 4 0 1 0 0 V 4 V 4 5 0 1 0 1 3V 4 + V 8 / 4 V 5 6 0 1 1 0 V 4 + V 8 / 2 V 6 7 0 1 1 1 V 4 + 3V 8 / 4 V 7 8 1 0 0 0 V 8 V 8 9 1 0 0 1 3V 8 + V 12 / 4 V 9 10 1 0 1 0 V 8 + V 12 / 2 V 10 11 1 0 1 1 V 8 + 3V 12 / 4 V 11 12 1 1 0 0 V 12 V 12 13 1 1 0 1 3V 12 + V 16 / 4 V 13 14 1 1 1 0 V 12 + V 16 / 2 V 14 15 1 1 1 1 V 12 + 3V 16 / 4 V 15 Table 9 teaches that twelve complement voltages can be obtained from four given voltages, compared to the prior art as shown in Figure 52 , which requires sixteen voltages. Thus, according to this invention, it is possible to reduce the number of external sources for supplying voltages. For example, when the digital video data consists of four bits, the prior art as shown in Figure 52 requires sixteen external sources for supplying voltages. On the other hand, according to this invention, the circuit requires only five external sources for supplying voltages. Thus, the number of external sources for supplying voltages can be reduced from 16 in the prior art to 5 in this invention. When the digital video data consists of five bits, the number of external sources for supplying voltages can be reduced from 32 in the prior art to 9 in this invention. When the digital video data consists of six bits, the number of external sources for supplying voltages can be reduced from 64 in the prior art to 17 in this invention. In the illustrated embodiment, the duty ratio of the signal t 1 is set to 1:1, however, any duty ratio is available. It is possible to adjust the value of complement voltages by changing the duty ratio. Example 9 Figure 31 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of four bits. As shown in Figure 31 , two distinct signals t 1 and t 2 are applied to selective control circuit SCOL in the source driver. Figure 33 shows waveforms of the signals t 1 and t 2 . In this Example, duty ratios of the signals t 1 and t 2 are set to 3:1 and 1:1 respectively. Table 10 shows a logic table which defines an operation of the selective control circuit SCOL in the drive circuit. decimal numbers d 3 d 2 d 1 d 0 S 0 S 4 S 8 S 12 S 16 0 0 0 0 0 1 1 0 0 0 1 t1 t1 2 0 0 1 0 t2 t2 3 0 0 1 1 t1 t1 4 0 1 0 0 1 5 0 1 0 1 t1 t1 6 0 1 1 0 t2 t2 7 0 1 1 1 t1 t1 8 1 0 0 0 1 9 1 0 0 1 t1 t1 10 1 0 1 0 t2 t2 11 1 0 1 1 t1 t1 12 1 1 0 0 1 13 1 1 0 1 t1 t1 14 1 1 1 0 t2 t2 15 1 1 1 1 t1 1 As shown in Table 10, the left column shows the value of digital video data input to the source driver in decimal notation. The center column shows data ( d 3 , d 2 , d 1 , d 0 ) input to the selective control circuit SCOL in binary notaton. The right column shows control signals output from output terminals of the selective control circuit SCOL . In the table, t 1 represents that if the signal t 1 is "1", then the control signal is "1", else the control signal is "0". Similarly, t 2 represents that if the signal t 2 is "1", then the control signal is "1", else the control signal is "0". The blanks represent that the control signal is "0". In Figure 31 , analog switches ASW 0 to ASW 16 are "on" when the corresponding control signals are "1". Figure 32 shows a logic circuit for the selective control circuit SCOL . The logic circuit is provided from the following logic expressions which are derived from table 10. S 0 = [0] · B S 4 = [0] · A + [4] · B S 8 = [4] · A + [8] · B S 12 = [8] · A + [12] · B S 16 = [12] · A A = (1) t 1 + (2) t 2 + (3)t 1 B = (0) + (1)t 1 + (2)t 2 + (3) t 1 (0) = d 1 d 0 (1) = d 1 d 0 (2) = d 1 d 0 (3) = d 1 d 0 [0] = d 3 d 2 [4] = d 3 d 2 [8] = d 3 d 2 [12] = d 3 d 2 A minimization is not considered regarding the logic circuit as shown in Figure 31 . However, since a plurality of selective control circuits SCOLs are required, the number being equal to the number of outputs of the source driver, it is required to minimize the logical circuit as possible. As shown in Table 10, when the digital video data is 0, the analog switch ASW 0 is "on" according to a control signal output from the output terminal S 0 of the selective control circuit SCOL , thereby the voltage V 0 which is supplied to the analong switch ASW 0 is output to the source line. In the same way, when the digital video data are 4, 8 and 12, the voltages V 4 , V 8 and V 12 reppectively are output. When the digital video data is 2, the analog switch ASW 0 is controlled to be "on" or "off" based on the signal t 2 and the analog switch ASW 4 is controlled to be "on" or "off" based on the signal t 2 (i.e., the inverted signal t 2 ). As a result, the analog switches ASW 0 and ASW 4 are controlled so that when one of the analog switches ASW 0 and ASW 4 are controlled so that when one of the analog switches ASW 0 and ASW 4 is "on", the other is "off". In this Example, since the duty ratio of the signal t 2 is set to 1:1, a first period and a second period is repeated alternatively. The first period is a period when the analog switch ASW 0 is "on" and the analog switch ASW 4 is "off", and the second period is a period when the analog switch ASW 0 is "off" and the analog switch ASW 4 is "on", the duration of the first period being equal to that of the second period. Thus, an oscillating voltage between the voltages V 0 and V 4 is output to the source line as shown in Figure 34A . Since the cscillating voltage is passed through the low-pass filter discussed above, a mean value of the oscillating voltage ( V 0 +V 4 )/2 is applied to the pixel of the display apparatus. In the same way, when the digital video data are 6, 10 and 14, mean values of the voltages output to the source line are ( V 4 +V 8 )/2, ( V 8 +V 12 )/2, and ( V 12 +V 16 )/2, respectively. As a result, the voltage ( V 4n +V 4n+4 )/2 is applied to the pixel of the display apparatus when the digital video data is 4n+2, wherein n = 0, 1, 2 and 3. When the digital data is 1, the analog switch ASW 0 is controlled to be "on" or "off" based on the signal t 1 , and the analog switch ASW 4 is controlled to be "on" or "off" based on the signal t 1 (i.e., the inverted signal t 1 ). As a result, the analog switches ASW 0 and ASW 4 are controlled so that when one of the analog switches ASW 0 and ASW 4 is "on", the other is "off". In this Example, since the duty ratio of the signal t 1 is set to 3:1, the first period and the second period mentioned above are repeated alternatingly, the length of the first period being three times that of the second period. Thus, a voltage oscillating between the voltages V 0 and V 4 is output to the source line as shown in Figure 34B . Since the oscillating voltage is passed through the low-pass filter discussed above, a mean value of the oscillating voltage ( 3V 0 + V 4 )/4 is applied to the pixel of the display apparatus. In the same way, when the digital video data are 5, 9 and 13, mean values of the voltages output to the source line are ( 3V 4 + V 8 )/4, ( 3V 8 + V 12 )/4 and ( 3V 12 + V 16 )/4 respectively. As a result, the voltage ( 3V 4n + V 4n+4 )/4 is applied to the pixel of the display apparatus when the digital data is 4n+1, wherein n = 1, 2 and 3. When the digital data is 3, the analog switch ASW 0 is controlled to be "on" or "off" based on the signal t 1 (i.e., the inverted signal t 1 ), and the analog switch ASW 4 is controlled to be "on" or "off" based on the signal t 1 . As a result, the analog switches ASW 0 and ASW 4 are controlled so that when one of the analog switches ASW 0 and ASW 4 is "on", the other is "off" . In this Example, since the duty ratio of the signal t 1 is set to 3:1, the first period and the second period mentioned above are repeated alternatinely, the length of the first period being one-third as that of the second period. Thus, a voltage oscillating between the voltages V 0 and V 4 is output to the source line as shown in Figure 34C . Since the oscillating voltage is passed through the low-pass filter discussed above, a mean value of the oscillating voltage ( V 0 + 3V 4 )/4 is applied to the pixel of the display apparatus. In the same way, when the digital video data are 7, 11 and 15, mean values of the voltages output to the source line are ( V 4 + 3V 8 )/4, ( V 8 + 3V 12 )/4, and ( V 12 + 3V 16 )/4 respectively. As a result, the voltage ( V 4n + 3V 4n+4 )/4 is applied to the pixel of the display apparatus when the digital data is 4n+3, wherein n = 0, 1, 2 and 3. Table 11 shows a relationship between digital video data and obtained voltages. Decimal numbers d 3 d 2 d 1 d 0 Voltages (Figure 31) Voltages (Figure 52) 0 0 0 0 0 V 0 V 0 1 0 0 0 1 3V 0 + V 4 / 4 V 1 2 0 0 1 0 V 0 + V 4 / 2 V 2 3 0 0 1 1 V 0 + 3V 4 / 4 V 3 4 0 1 0 0 V 4 V 4 5 0 1 0 1 3V 4 + V 8 / 4 V 5 6 0 1 1 0 V 4 + V 8 / 2 V 6 7 0 1 1 1 V 4 + 3V 8 / 4 V 7 8 1 0 0 0 V 8 V 8 9 1 0 0 1 3V 8 + V 12 / 4 V 9 10 1 0 1 0 V 8 + V 12 / 2 V 10 11 1 0 1 1 V 8 + 3V 12 / 4 V 11 12 1 1 0 0 V 12 V 12 13 1 1 0 1 3V 12 + V 16 / 4 V 13 14 1 1 1 0 V 12 + V 16 / 2 V 14 15 1 1 1 1 V 12 + 3V 16 / 4 V 15 Table 11 teaches that twelve complement voltages can be obtained from four given voltages. When the digital video data consists of four bits, the prior art as shown in Figure 52 requires sixteen external sources for supplying voltages. On the other hand, the circuit acording to this invention, requires only five external source for supplying voltages as shown in Figure 31 . Thus, the number of external sources for supplying voltages can be reduced from 16 in the prior art to 5 in this invention. In the illustrated embodiment, the signals applied to the selective control circuit are described as being generated outside the selective control circuit. Of course, the signals can be generated in any circuits. However, since the source driver requires a plurality of selective control circuits SCOLs , it is not a good choice to generate the signals in each of the selective control circuits. It is desired that the signals are generated in one common circuit of the LSI by which the drive circuit is composed, and applied to each of the selective control circuits. The clocks signals can be generated from sampling clocks input to the drive circuit and can alternatively be supplied from external sources. When the clock singnals are supplied from the external sources, It is possible to adjust the period of an osclllating voltage as desired with the demerit that the LSI requires one more input terminal to receive the clock signals. Example 10 Figure 35 shows an example of the voltages V 0 to V 7 used to make a liquid crystal panel with eight gradation levels. Figure 35 teaches the voltages have a linear characteristic from V 1 to V 6 . According to the drive circuit described in Example 4, the voltages V 3 and V 5 shown in Figure 35 can be obtained. The voltage V 7 shown in Figure 35 can also obtained by adjusting the voltage V 7 shown in Table 3 (Example 4). However, there remains a problem regarding the voltage V 1 shown in Figure 35 . Figure 35 teaches that the voltages have an non-linear characteristic from V 0 to V 1 . If the voltages V 0 and V 2 are adjusted as shown in Figure 35 , the difference Δ V 1 occurs between the obtained voltage and the desired voltage. If the voltages V 2 and V 1 are adjusted as shown in Figure 35 , the difference Δ V 0 occurs between the obtained voltage and the desired voltage. The drive circuit capable of providing an appropriate voltage regarding the portion of the non-linear characteristic shown in Figure 35 is described in detail below: Figure 36 shows a circuit for one output of the source driver 101 an the drive circuit. Digital video data input to the drive circuit consists of three bits. As shown in Figure 36 , two distinct signals t 1 and t 2 are applied to the selective control circuit in the source driver. In this Example, the duty ratio of the signal t 1 is set to 1:1, and the duty ratio of the signal t 2 is set to 1:2. The signal t 2 is used to provide a voltage V 1 . Figure 37A shows a waveform of the signal t 2 , and Figure 37B shows a waveform of a voltage V 1 provided from the signal t 2 . As shown in Figure 37B , the ratio of the voltages V 0 and V 2 is 1:2 corresponding to the duty ratio of the signal t 2 . As a result, a mean value of the voltage V 1 is ( V 0 + 2V 2 )/3, which satisfies the condition of the voltage V 1 shown in Figure 35 . Thus, the drive circuit mentioned above can provide an appropriate voltage regarding the portion of the non-linear characteristic shown in Figure 35 . Table 12 shows a logic table which defines the operation of the selective control circuit. d 2 d 1 d 0 S 0 S 2 S 4 S 6 S 7 0 0 0 1 0 0 1 t2 t2 0 1 0 1 0 1 1 t1 t1 1 0 0 1 1 0 1 t1 t1 1 1 0 1 1 1 1 1 In Table 12, the left column shows data ( d 2 , d 1 , d 0 ) input to the selective control circuit, and the right column shows control signals output from the output terminals S 0 to S 7 to the corresponding analog switches ASW 0 to ASW 7 . In Table 12, t 1 represents that if the signal t 1 is "0", then the control signal is "0", else the control signal is "1". t 1 represents that if the signal t 1 is "0", then the control signal is "1", else the control signal is "0". t 2 and t 2 are defined similarly as t 1 and t 1 . In Figure 36 , analog switches ASW 0 to ASW 7 are "on" when the corresponding control signals are "1". Figure 38 shows a logic circuit for the selective control circuit SCOL . The logic circuit is provided from the following logic expressions which are derived from Table 12. S 0 = (0) + (1)t 2 S 2 = (1) t 2 + (2) + (3)t 1 S 4 = (3) t 1 S 6 = (5) t 1 + (6) S 7 = (7) (0) = d 1 d 1 d 0 (1) = d 2 d 1 d 0 (2) = d 2 d 1 d 0 (3) = d 2 d 1 d 0 (4) = d 2 d 1 d 0 (5) = d 2 d 1 d 0 (6) = d 2 d 1 d 0 (7) = d 2 d 1 d 0 In this example, the duty ratio of the signal t 2 is set to 1:2. However, any duty ratio except 1:1 is available for adjusting the voltages. Example 11 Figure 39 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of three bits. As shown in Figure 39 , one signal t 3 is applied to the selective control circuit SCOL in the source driver. The duty ratio of the signal t 3 is set to 1:2. Figure 40A shows a waveform of the signal t 3 , and Figure 40B shows a waveform of a voltage provided from the signal t 3 . Table 13 shows a logic table which defines an operation of the selective control circuit SCOL in the drive circuit. d 2 d 1 d 0 S 0 S 2 S 5 S 7 0 0 0 1 0 0 1 t 3 t 3 0 1 0 1 0 1 1 t t 3 1 0 0 t 3 t 3 1 0 1 1 1 1 0 t 3 t 3 1 1 1 1 As shown in Table 13, when the digital video data is 0, the analog switch ASW 0 is "on" according to a control signal output from the output terminals S 0 of the selective control circuit, thereby the voltage V 0 which is supplied to the analog switch ASW 0 is output to the source line. In the same way, when the digital video data are 2, 5 and 7, the voltages V 2 , V 5 and V 7 respectively are output. When the digital data is 1, the analog switch ASW 0 is controlled to be "on" or "off" based on the signal t 3 (i.e. the inverted signal t 3 ), and the analog switch ASW 2 is controlled to be "on" and "off" based on the signal t 3 . As a result, the analog switches ASW 0 and ASW 2 are controlled so that when one of the analog switches ASW 0 and ASW 2 is "on", the other is "off", thereby an voltage oscillating between the voltages V 0 and V 2 is output to the source line. A mean value of the oscillating voltage is ( V 0 + 2V 2 )/3. In the same way, when the digital video data are 3, 4 and 6, mean values of the voltages output to the source line are ( 2V 2 + V 5 )/3, ( V 2 + 2V 5 )/3, and ( 2V 5 + V 7 )/3. Table 14 shows the voltages output to the source line in the right column, compared with the voltages in the prior art shown in Figure 60 in the center column. d 2 d 1 d 0 Voltages (Figure 60) Voltages (Figure 39) 0 0 0 V 0 V 0 0 0 1 V 1 V 0 + 2V 2 / 3 0 1 0 V 2 V 2 0 1 1 V 3 2V 2 + V 5 / 3 1 0 0 V 4 V 2 + 2V 5 / 3 1 0 1 V 5 V 5 1 1 0 V 6 2V 5 + V 7 / 3 1 1 1 V 7 V 7 Figure 41 shows a logic circuit for the selective control circuit. The logic circuit is provided from the following logic expressions which are derived from Table 13. S 0 = (0) + (1) t 3 S 2 = (1)t 3 + (3)t 3 + (4) t 3 + (2) S 5 = (3) t 3 + (4)t 3 + (5) + (6)t 3 S 7 = (6) t 3 + (7) (0) = d 2 d 1 d 0 (1) = d 2 d 1 d 0 (2) = d 2 d 1 d 0 (3) = d 2 d 1 d 0 (4) = d 2 d 1 d 0 (5) = d 2 d 1 d 0 (6) = d 2 d 1 d 0 (7) = d 2 d 1 d 0 As a result, if the V 0 , V 2 , V 5 and V 7 are adjusted as shown in Figure 35 , the voltages ( V 0 + 2V 2 )/3, ( 2V 2 + V 5 )/3, ( V 2 + 2V 5 )/3, and ( 2V 5 + V 7 )/3 satisfy the condition of the desired voltages V 1 , V 3 , V 4 and V 6 , respectively. It is understood that the drive circuit shown in Figure 39 causes the same effect as the drive circuit in the prior art shown in Figure 60 . Thus, the drive circuit mentioned above can provide appropriate voltages regarding the portion of the non-linear characteristic shown in Figure 35 . Furthermore, the number of external sources for supplying voltages can be reduced. In this example, the duty ratio of the signal t 3 is set to 1:2. However, the duty ratio 2:1 is also available for adjusting the voltages. Example 12 Figure 42 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of two bits. As shown in Figure 42 , two distinct signals t 4 and t 5 are applied to the selective control circuit in the source driver. Figures 43A and 43B show waveforms of the signals t 4 and t 5 . Figure 44 shows a magnification of the signal t 4 . The duty ratios of the signals t 4 and t 5 are set to 1:2 and 2:1 respectively. When the digital video data ( D 1 , D 0 ){(0, 0)} is input to the source driver, the output S 0 of the decoder DEC becomes "1", and the other outputs S 1 , S 2 and S 3 become "0". Since all the inputs of the OR circuit 4204 become "0", the output of the OR circuit becomes a constant voltage V gnd as shown in Figure 45A . When the digital video data ( D 1 , D 0 ){(0, 1)} is input, the output S 1 of the decoder DEC becomes "1", and the other outputs S 0 , S 2 and S 3 become "0". As a result, one of inputs of the OR circuit 4204 becomes "1" in the same cycle as the signal t 4 . The output of the OR circuit 4204 becomes an voltage oscillating between the voltages V D and V gnd at the same duty ratio as that of the signal t 4 (n:m = 1:2) as shown in Figure 45B . When the digital video data ( D 1 , D 0 ){(1, 0)} is input, the output S 2 of the decoder DEC becomes "1", and the other outputs S 0 , S 1 and S 3 become "0". As a result, one of the inputs of the OR circuit 4204 becomes "1" in the same cycle as the signal t 5 . The output of the OR circuit 4204 becomes a voltage oscillating between the voltages V D and V gnd at the same duty ratio as that of the signal t 5 (n:m = 2:1) as shown in Figure 45C . When the digital video data ( D 1 , D 0 ){(1, 1)} is input, the output S 3 of the decoder DEC becomes "1", and the other outputs S 0 , S 1 and S 2 become "0". As a result, the output of the OR circuit 4204 becomes a constant voltage V D as shown in Figure 45D . When the ground video data ( D 1 , D 0 ) is (0, 1) or (1, 0), a mean value of the output of the OR circuit 4204 , that is, a mean value of the voltage applied to the source line is expressed by: n · V D + m · V gnd n + m When the ground level V gnd is 0 V in the above expression, a mean value of the voltage applied to the source line is expressed by: n n + m V D Accordingly, if the digital video data ( D 1 , D 0 ) = (0, 0), then a mean value of the voltage output to the source line is 0. If ( D 1 , D 0 ) = (0, 1) then it is (1/3) V D . If ( D 1 , D 0 ) = (1, 0), then it is (2/3) V D . If ( D 1 , D 0 ) = (1, 1), then it is V D . Thus, two complement voltages can be obtained from two given voltages V D and V gnd . The two complement voltages can be adjusted appropriately by changing the duty ratios of the signals t 4 and t 5 . Therefore, the drive circuit mentioned above can provide appropriate voltages regarding the portion of the non-linear characteristic shown in Figure 35 . In this example, the duty ratio of the signals t 1 and t 5 are set to 1:2 and 2:1 respectively. However, any duty ratio is also available for adjusting the voltages. Example 13 Figure 46 shows a circuit for one output of the source driver 101 in the drive circuit. Digital video data input to the drive circuit consists of two bits. The outputs S 0 to S 3 of the decoder DEC are input to one input of the AND circuits 4601 to 4604 respectively. The signals t 6 to t 9 are input to the other inputs thereof, respectively. The outputs of the AND circuits 4601 to 4604 are input to the OR circuit 4605 . The output of the OR circuit 4605 is applied to the source line O n . In this Example, any voltages between the voltages V D and V gnd can be obtained from the given voltages V D and V gnd by changing the duty ratios of the signals t 6 to t 9 appropriately, and can be applied to the source line. When mean values of the voltages generated based on the signals t 6 to t 9 are represented by V 0 to V 3 respectively, the relationship between the the pixels are shown in Table 15. D 1 D 0 Voltages 0 0 V 0 0 1 V 1 1 0 V 2 1 1 V 3 Four voltages can be obtained from two given voltages V D and V gnd . The four voltages can be adjusted appropriately by changing the duty ratios of the signals t 6 to t 9 . Therefore, the drive circuit mentioned above can provide appropriate voltages regarding the portion of the non-linear characteristic shown in Figure 35 . According to this invention, at least one complement voltage can be obtained from the given voltages, thereby the number of external sources for supplying voltages can be reduced drastically and the number of input terminals of the drive circuit can be decreased. Accordingly it possible (1) to reduce the cost of the display apparatus and the device circuit for the display apparatus, (2) to produce easily the drive circuit suitable for the display apparatus which has multiple gradation levels, which cannot be produced in the prior art devices because of problems on an implementation of a LSI , and (3) to reduce the power consumption of the display apparatus. When the drive circuits described in Example 1 and Example 2 are used, additional advantages are obtained as follows: (1) Any voltage can be applied to the pixel by changing the duty ratios of signals appropriately. (2) A size of the drive circuit can become smaller than that of the prior art as no analog switch is used in the drive circuit. When the drive circuits described in Example 10 to Example 13 are used, the drive circuit can provide voltages adjusted to the non-linear displaying characteristic. Various modifications will be apparent to and can be readily made by those skilled in the art. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein.

Claims: A method of driving a display apparatus having a display section (100) including a pixel (P ij ) and a switching element (T ij ) connected to said pixel (P ij ), and a source line (O i ) connected to said switching element (T ij ), said method comprising the steps of: receiving output requests in a drive circuit (101) at predetermined intervals; and outputting a voltage from said drive circuit (101) to said source line (O i ); characterised in that said voltage is an oscillating voltage including a component which repeatedly oscillates during one output period (jH), an output period (jH) being a period from receiving one of said output requests to receiving a next one of said output requests; wherein during said one output period (jH) said source line is connected to said pixel by said switching element for charging said pixel based on said oscillating voltage. A method of driving a display apparatus as claimed in claim 1 wherein said oscillating voltage oscillates between a first voltage and a second voltage during said one output period. A drive circuit for a display apparatus having a display section (100) including a pixel (P ij ) and a switching element (T ij ) connected to said pixel (P ij ), and a source line (O i ) connected to said switching element (T ij ), said drive circuit comprising: receiving means for receiving output requests at predetermined intervals; and outputting means for outputting a voltage to said source line; characterised in that said voltage is an oscillating voltage including a component which repeatedly oscillates during one output period (jH), an output period (jH) being a period from receiving one of said output requests to receiving a next one of said output requests through said receiving means; wherein during said one output period said source line (O i ) is connected to said pixel (P ij ) by said switching element (T ij ) for charging said pixel (P ij ) based on said oscillating voltage. A drive circuit for a display apparatus as claimed in claim 3 wherein said oscillating voltage oscillates between a first voltage and a second voltage during said one output period. A drive circuit for a display apparatus according to claim 3 or 4, wherein said outputting means comprises:- a logic circuit which receives a digital video input and plurality of oscillating signals for selecting one of said oscillating signals as a function of said digital video data input; and a voltage outputting circuit for outputting an oscillating voltage to said source line according to said oscillating signal, said oscillating voltage including at least a component which oscillates during said one output period. A drive circuit for a display apparatus according to claim 5, and further comprising:- a voltage outputting circuit for outputting a constant voltage as a function of a digital video data input. A drive circuit for a display apparatus according to claim 3, wherein said outputting means comprises: a plurality of switching elements (602, 603; ASW 0 , ASW 2 , ASW 4 , ASW 6 , ASW 8 ; ASW 0 , ASW 2 , ASW 4 , ASW 6 , ASW 7 ; ASW 0 , ASW 4 , ASW 8 , ASW 12 , ASW 16 ), distinct voltages being supplied to said plurality of switching elements respectively, and said supplied voltages being outputted to said source line when said corresponding switching elements are in an ON states; and a selective control circuit for controlling to change the ON state and OFF state of at least one pair of said plurality of switching elements during said one output period of time. A drive circuit for a display apparatus according to claim 7, wherein said selective control circuit controls to change ON state and OFF state of at least one pair of said plurality of switching elements at least once during said one output period of time, to that one of said pairs of said plurality of switching elements is in an ON state when the other of said pairs of said plurality of switching elements is in an OFF state. A drive circuit for a display apparatus according to claim 8, wherein said selective control circuit controls to change the ON state and OFF state of at least one pair of said plurality of switching elements base-on a clock signal having a duty ratio of 1:1. A drive circuit for a display apparatus according to claim 8, wherein said selective control circuit controls to change the ON state and OFF state of at least one pair of said plurality of switching elements based on a plurality of clock signals having duty ratios set to 3:1 and 1:1. A drive circuit for a display apparatus according to claim 8, wherein said selective control circuit controls to change the ON state and OFF state of at least one pairs of said plurality of switching elements based on a plurality of clock signals having duty ratios set to 7:1, 6:2, 5:3 and 4:4. A drive circuit for a display apparatus according to claim 8, wherein said selective control circuit controls to change the ON state and OFF state of at least one pair of said plurality of switching elements based on a plurality clock signals duty ratios set to 31:1, 30:2, 29:3, 28:4, 27:5, 26:6, 25:7, 24:8, 23:9, 22:10, 21:11, 20:12, 19:13, 18:14, 17:15 and 16:16. A drive circuit for a display apparatus according to claim 7, wherein said selective control circuit controls to change the ON state and OFF state of at least one pair of said plurality of switching elements, so that one of said pairs of said plurality of switching elements is in an ON state and the other of said pairs of said plurality of switching elements is controlled to change to an ON state and OFF state at least once during said one output period of time. A drive circuit for a display apparatus according to claim 13, wherein said selective control circuit controls to change the ON state and OFF state of at least one pair of said plurality of switching elements based on a clock signal having a duty ratio is set to 1:1. A drive circuit for a display apparatus according to claim 7, wherein said selective control circuit controls to change the ON state and OFF state of at least one pair of said plurality of switching elements, so that one of said pairs of said plurality of switching elements is in the OFF state and the other of said pairs of said plurality of switching elements is in the ON state during said one output period of time. A display apparatus having a display section including: a pixel; a switching element connected to said pixel; and a source line connected to said switching element, said display apparatus comprising: a drive circuit as specified in any of claims 4 to 15; and reducing means for reducing the amplitude of said component of said oscillating voltage, said oscillating voltage being applied to said pixel after the amplitude of said component is reduced by said reducing means. A display apparatus as claimed in claim 16 wherein a part of said reducing means is formed by said source line. A display apparatus as claimed in claim 16 wherein a part of said reducing means is formed by said pixel. A display apparatus as claimed in claim 16 wherein a part of said reducing means is formed by said switching element.

Inventors: FUKUOKA HIROFUMI, KANATANI YOSHIHARU, NISITANI TADATSUGU, OKADA HISAO, TAKARADA TAKESHI, TANAKA KUNIAKI, YANAGI TOSHIHIRO, FUKUOKA, HIROFUMI, KANATANI, YOSHIHARU, NISITANI, TADATSUGU, OKADA, HISAO, TAKARADA, TAKESHI, TANAKA, KUNIAKI, YANAGI, TOSHIHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: G09G3
IPC codes: G09G3