Selection response circuit according to small computer system interface

Abstract: The present invention relates to a selection response circuit according to an SCSI (small computer system interface), where a selection response device is designed with digital logic having simple structure. The present circuit comprises bus checking means for checking the status of an SCSI bus, ID bit checking means for checking whether a bit corresponding to ID of itself is active on bus, and bus free checking means for checking the status of a BSY signal and an SEL signal on the SCSI bus to determine whether all SCSI units are using the bus.

Description: The present invention relates to a target selection response circuit for a small computer system interface (hereinafter referred to as SCSI). More particularly the invention relates to a selection response circuit according to SCSI which realizes a selection response function by digital hardware. It is known to add SCSI to a small computer (BYTE - June 1986 (USA) pages 107 - 114 - CIARCIA, S' ADDING SCSI TO THE SB 180 COMPUTER, II. BUS PHASES. Generally, SCSI is the regulations affecting the interface for connecting a small computer, i.e., a personal computer, and external peripheral units. Currently, the regulations are standardized with respect to a magnetic disc unit such as a floppy disc driver and a hard disc driver, and an optical disc unit such as a compact disc ROM, and a printer. FIGs.1A to 1C show systems connected according to SCSI, where one computer 1A can be coupled to one controller 2A by mutual SCSI bus (as shown in FIG.1A), or one computer 1B can be coupled to two controllers 2B and 2C by an SCSI bus (as shown in FIG.1B). Also, two or more computers 1C to 1E can be coupled to a plurality of controllers 2D to 2H by an SCSI bus. That is, one or a plurality of computers 1A to 1E control one or a plurality of controllers 2A to 2H as target. FIG.2 is a functional diagram with respect to phase conversion in SCSI. A bus free phase P1 used in FIG.2 is the phase in which all SCSI units do not use a bus. An arbitration phase P2 is for an SCSI unit to obtain the use of a bus, and a selection phase P3 or a reselection phase P4 is for an initiator (computer) to select an SCSI unit operated as a target and winning in arbitration. An information transmission phase P5 (message out, comment, data in, data out, status, message in) is to transmit/receive actually needed information between initiator and target. Meanwhile, FIG.3 shows a SCSI bus intermediating data transmission between a computer 1F and a controller 2I, in which the SCSI bus has data bits, parity bit, and control signal bits. The selection phase among the respective bus phases is for an initiator (computer) to select an SCSI unit operated as a target, and winning in arbitration. The response sequence in the selection phase of SCSI is as follows. That is, when a bus is not used by any SCSI units and data on the bus is equal to identification (hereinafter referred to as ID) of the SCSI unit itself, and IDs of three or more SCSI units are not active over a predetermined time, it is automatically indicated that the target is selected with respect to the initiator. Conventionally, such a selection response function of SCSI units is performed using the software of a computer. That is, after it is identified that there is a selection phase, it is identified that the ID of the SCSI unit itself is active by reading data on data bus and the active bit is one bit (i.e., ID of the itself) or 2 bits (i.e., IDs of SCSI unit itself and its host computer), using a switch or a switching device, and then the response with respect to this is performed. Also, there is a system using an SCSI controller IC to obtain a selection response, but the internal constitution of such an SCSI controller IC and the selection response type have not been known. It is an object of the present invention to provide a selection response circuit according to SCSI where a selection response function according to SCSI is performed by a digital logic circuit having a simplified construction. To achieve the object, the invention teaches a target selection response circuit according to claim 1. Furthermore the invention teaches a target selection response circuit according to the claims 2-6. The above object and other advantages of the present invention will become more apparent by describing the preferred embodiment of the present invention with reference to the attached drawings, in which: FIGs1A to 1C show connection states of systems coupled according to SCSI; FIG.2 is a block diagram explaining phase conversion function in SCSI; FIG.3 is a connection state diagram of SCSI bus; FIG.4 is an embodiment of a present selection response circuit according to SCSI; FIG.5 is a circuit diagram of a preferred embodiment of slice adder within FIG.4; FIG.6 is a truth table explaining the operational state of slice adder within FIG.4; FIG.7 is a circuit diagram of a preferred embodiment of decoder within FIG.4; FIG.8 is a circuit diagram of a preferred embodiment of a bus signal check portion within FIG.4; FIG.9 is a circuit diagram of a preferred embodiment of a bus free check portion within FIG.9; and FIGs.10A and 10B are timing diagrams of selection signals according to the used state of arbitration. FIG.4 shows an embodiment of a selection response circuit according to the present invention. A bus check portion 100 comprises a slice adder 10 for checking whether bits below three (two bits or one bit) are active on an SCSI bus, and a signal output check portion 11 for checking whether an output of the slice adder 10 is 1 or 2. An ID bit check portion 200 comprises a decoder 12 for decoding ID bit of the SCSI unit itself to check whether a bit corresponding to ID of SCSI unit itself is active on the SCSI bus, and a bus signal check portion 13 for checking whether a decoded output from the decoder is equal to a signal on the SCSI bus. Meanwhile, the selection response circuit of the present invention comprises a bus free check portion 300 which checks whether BSY and SEL signals on SCSI bus are at "high" level, thereby determining whether any of the SCSI units use bus. First of all, the slice adder 10 functions to check whether bits below three among the data bus eight bits, i.e., one bit or two bits, are active, and as shown in FIG.5, is constituted by coupling full-adders FA1 to FA4 and half-adders HA1 to HA3. That is, lower six bits of eight-bit data are inputted to the full-adders FA1 and FA2, respectively, and upper two bits are inputted to the half-adder HA1. Sum outputs S and carry outputs C of the respective adders FA1, FA2 and HA1 are inputted to the full-adders FA3 and FA4, respectively. A first output OUTO is drawn out from the sum output terminal S of the full-adder FA3 and the carry output C of the full-adder FA3 and the sum output S of the full-adder FA4 are inputted to the half-adder HA2. A second output OUT1 is drawn out from one output of the half-adder HA2. Also, the other output of the half-adder HA2 is inputted to the half-adder HA3 to be summed with the carry output C of the full-adder FA4, and a sum output S and a carry output C of the half-adder HA3 are drawn out as outputs OUT2 and OUT3. Such operation of a slice adder 10 shows the characteristics of the truth table shown in FIG.6, and accordingly, when only one or two bits are activated, a signal of 'high' level is outputted. Meanwhile, FIG.7 is a circuit diagram of a decoder 12 for decoding an ID bit of the SCSI unit itself to check whether the bit corresponding to ID of the SCSI unit itself on the SCSI bus is activated in FIG.4, where a 3*8 decoder is used. The decoder 12 performs the basic operation of a general decoder where bits corresponding to previous values of input signals ID0 to ID2 are activated to be 1 and the other remaining bits are activated to be zero level. FIG.8 shows an embodiment of a bus signal check portion 13 for checking whether an output decoded from the decoder 12 is the same as the signal on the SCSI bus. Outputs of decoder 12 and corresponding bits of compared data are inputted to the respective AND gates AD10 to AD17, whose outputs are OR-gated by an OR gate OR10, so that even if one specific output bit of decoder 12 is equal to a corresponding bit of compared data, its output becomes 'high' level to be outputted as a selection identification signal. Meanwhile, FIG.9 shows an embodiment of a bus free check portion 300 for checking how many periods the same value is maintained with respect to successive clocks of specific signal (here, Sig 1). In the embodiment of FIG.4, the durability of input signal Sig 1 is checked for three periods of clock signal CLX using three flip-flops FF1 to FF3. However, if the state of input signal Sig 1 is checked with respect to a period longer than the above period, a plurality of flip-flops FF1 to FFn and AND gates AD2 to ADn+1 are used by being successively coupled in parallel in the same structure. Accordingly, if an input signal Sig 1 is 'high' level, in the next clock CLX, a 'high' level signal is transferred to the next flip-flop. But, if an input signal Sig 1 becomes 'low' level, the outputs of AND gates AD2 to ADn+1 become directly 'low' level, so that in the next clock CLX, all outputs of flip-flops FF1 to FFn become 'low' level. Accordingly, if it is checked when the flop-flop FFn of final stage becomes 'high' level and the number of flip-flops coupled in parallel is known, it can be obtained how long the input signal maintains a constant value. Meanwhile, the operation of generating a selection signal by the selection response device of FIG.4 is as follows. The selection process for selecting an SCSI device operated as a target by an initiator is different in an arbitration-used system and an arbitration unused system. First of all, as shown in the timing diagram of FIG.10A, in a system which does not use arbitration, the initiator detects a bus free status, waits for 800nsec, activates ID bits of target and initiator itself, waits for 90nsec, and then activates a SEL signal. However, in a system using arbitration, an initiator activates a selection SEL signal in an arbitration phase, and activates ID bits of target and initiator, itself on data bus after a time longer than about 1.2µsec, i.e., after the sum of bus clear delay and bus stability delay time, elapses. Then, after a time over 90nsec elapses, a BSY signal is inactivated, the initiator again waits for over 90nsec, and then waits a response from the target. Meanwhile, in a response sequence with respect to the selection, the SCSI unit (target) detects that SEL signal and data bus bits corresponding to ID of SCSI unit itself are activated and the BSY signal and input/output (I/O) signal are inactivated for about 400nsec, i.e., an interval longer than bus settling delay, thereby recognizing that it itself is selected in selection phase. The target should respond with respect to the initiator by activating a BSY signal within about 400nsec from its selection detecting time, i.e., within a selection failure time. At this time, the selected target checks every bit on data bus to identify SCSI ID of initiator. When three SCSI IDs or more are detected on the data bus, the target does not respond to the selection phase. And, after the initiator detects a response of BSY signal from the target, it inactivates the SEL signal after 90nsec elapses, thereby ending the selection phase. As described above, according to the present invention, the selection response device between a computer and peripheral units, according to the international standard interface, i.e., SCSI, has the advantages of being designed with digital logic of a simple structure, and being included in the conventional SCSI protocol IC.

Claims: A target selection response circuit for a small computer system interface, hereinafter referred to as SCSI, where the selection response function is performed by a digital logic circuit, comprising: bus checking means (100) for checking a status of a SCSI bus, said bus checking means (100) comprising a slice adder (10) for checking active bits below a predetermined number among data bits received through said SCSI bus and providing output signals in response thereto; and a signal output checking means (11) for determining whether only a target or both the target and a host computer are in an active state in response to said output signals of said slice adder (10); identification bit checking means (200) for checking whether the bit corresponding to the identification of the target is active on said SCSI bus in order for the target to use said SCSI bus; and bus free checking means (300) for checking whether said SCSI bus is in bus free state by checking a status of a busy signal and a selection signal on said SCSI bus to determine whether any of SCSI units are using the bus. A target selection response circuit according to claim 1, wherein said slice adder (10) comprises: first and second full-adders (FA1, FA2) for receiving bits 0 to 5 of input data and outputting sum outputs (S) and carry outputs (C); a first half-adder (HA1) for receiving bits 6 and 7 of said input data and outputting a sum output (S) and a carry output (C); third and fourth full-adder (FA3, FA4) for summing said sum outputs (S) and carry outputs (C) of said first and second full-adders (FA1, FA2) and said first half-adder (HA1), a first output (OUT0) being obtained from a sum terminal of said third full-adder (FA3); a second half-adder (HA2) for summing a carry output of said third full-adder (FA3) and a sum output of said fourth full-adder (FA4), a second output (OUT1) being obtained from a sum output terminal of said second half-adder (HA2); and a third half-adder (HA3) for adding a carry output of said second half-adder (HA2) and a carry output of said fourth full-adder (FA4), third and fourth outputs (OUT2, OUT3) being obtained from said third half-adder (HA3). A target selection response circuit according to claim 1, wherein said signal output checking means (11) comprises: first and second inverters for inverting two different output signals of said slice adder (10); an exclusive-OR gate for exclusive-OR gating two different output signals from outputs of said slice adder (10); and an AND gate for AND-gating outputs of said first and second inverters and said exclusive-OR gate. A target selection response circuit according to claim 1, wherein said target identification bit checking means (200) comprises: a decoder (12) for decoding a target identification bit in order to check whether said target identification bit is active on said SCSI bus; and a bus signal checking portion (13) for checking whether an output signal of said decoder (12) identifies a corresponding bit signal active on said SCSI bus. A target selection response circuit according to claim 4, wherein said decoder (12) is a 3x8 decoder. A target selection response circuit according to claim 4, Wherein said bus signal checking portion (13) comprises: eight AND gates for AND-gating output signals of said decoder (12) and corresponding data bits on said SCSI bus; and an OR gate for OR-gating output signals of said AND gates.

Inventors: SEUNG JONG CHOI, SEUNG JONG CHOI,C/O GOLDSTAR CO. LTD.
Applicants: GOLD STAR CO, GOLDSTAR CO. LTD.
Application year: 1992
Main classification: G06F13
IPC codes: G06F13