Field of electric transistor of metal-oxide-semiconductor (MOSFET)

Abstract: A MOSFET wherein a gate of it, a source of it is grounded through high resistance, a source is connected to a drain, furthermore, an output capacitance is connected to the source.

Description: -FIELD OF THE INVENTION- The present invention relates to a field of electric transistor of metal-oxide-semiconductor (MOS), especially to a field of electric transistor of MOS effective in integrating signal of IC. -BACKGROUND OF THE INVENTION- Conventionally, it has been necessary a device comprising plural number of inputs in order to perform signal integration, and also necessary different devices as the same number of inputs. When the same circuit is realized in IC, many libraries of the IC has been necessary. Such library is inefficient. -SUMMARY OF THE INVENTION- The present invention is invented so as to solve the above problems and has an object to provide a MOSFET to easily realize the integration of plural inputs. An electrical summation circuit according to the present invention is defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a MOSFET circuit. Figure 2 shows the block diagram of the structure of a circuit for signal integration using the embodiment in Figure 1. Figure 3 shows a block diagram of the structure of a circuit for hierarchical signal integration using the embodiment in Figure 1. "T" shows a MOSFET, dd, ddl, dd2 and ddn show input voltage, Vcc shows a power source, "D" shows a drain, "G" shows a gate, "S" shows a source, "R" shows a high resistance, "C" shows a capacitance, "DD" shows an output of a capacitance, T1, T2, Tn and To show transistors, DD, DD2 and DDn show output of transistors, DD COM shows a common output, dd in shows an input of transistor To, and dd out shows and output of transistor To. -PREFERRED EMBODIMENT OF THE INVENTION- An embodiment of MOSFET according to the present invention is described with reference to the attached drawings. In Figure 1 with respect to MOSFET "T", gate "G" of it is connected to input voltage "dd", drain "D" is connected to power source "Vcc" and source "S" is grounded through high resistance "R". Output capacitance "C" is connected to source "S", and the output "DD" of capacitance "C" is the output of MOSFET "T". Figure 2 shows the structure of the circuit for integrating signals. The outputs of plural number of transistors from T1 to Tn are connected to the common output (the voltage of it is "DD COM ). Representing the volume of output capacitance for transistors from T1 to Tn by C1 to Cn, respectively, and the volume of electricity of the capacitances by Q1 to Qn, respectively, the equations in (1) are formulated. The total summations of both members are expressed as in (2). In formula (2), as Σ C k and Σ Q i are constants, formula (2) is varied into (3) of the equation for DD COM , representing them by "Ct" and "Qt", respectively. As it is clear from the formula in (3), DD COM is a linear function of weighted summation (weight is "Ci") of input voltage dd i . When the electrical charge of each condenser "Qi" is 0, "Qt" is also 0. In such a condition, the offset in (3) can be deleted and the formula in (4) can be obtained. As shown, it is a simple summation of electrical change. The signal integration can be easily realized without using plural inputs device and a circuit module. Figure 3 shows a structure for inputting such integration to the similar transistor To. The common output of transistor from T1 to Tn is connected to "dd in " of the input of transistor To. It is possible not only to drive the transistor by the output integrated by it but also to integrate the output of to with the output of the transistor. That is, hierarchical integration of information is possible. As mentioned, it is possible to realize easily the integration of plural inputs by the MOSFET according to the present invention because output capacitance is connected to the source.

Claims: An electrical summation circuit for summing a plurality of input voltages applied at respective input voltage terminals, said circuit comprising a plurality of MOSFET-circuits, each MOSFET-circuit including a MOSFET having a drain terminal electrically connected to a source voltage terminal, a gate terminal electrically connected to one of said input voltage terminals and a source terminal electrically connected through a high resistance to a ground terminal and electrically connected through a capacitance to an output terminal, wherein all output terminals of said plurality of MOSFETcircuits are electrically connected together to form a combined output terminal to provide an output voltage (DD com ) which represents a weighted summation of the plurality of input voltages (dd 1 , dd 2 , ...dd n ), and wherein the weight of each MOSFET-circuit is determined by the respective capacitance.

Inventors: SHU GUOLIANG, TAKATORI SUNAO, WONGWARAWIPAT WIWAT, YAMAMOTO MAKOTO, YANG WEIKANG, SHU, GUOLIANG, TAKATORI, SUNAO, WONGWARAWIPAT, WIWAT, YAMAMOTO, MAKOTO, YANG, WEIKANG
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1992
Main classification: H01L27
IPC codes: H03F3, H01L27, H01L21