Power-on reset circuit having a low static consumption

Abstract: A power-on reset circuit employs a supply voltage sensing line (M1,R1,R2,M2) for triggering a first inverter (M3,M4) of a pair of cascaded inverters (M3,M4;J). The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator (G1,G2,R3), which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing line (M1,R1,R2,M2) into a subthreshold operating condition.

Description: In integrated circuits, and particularly in micro-logic circuits, there is often the necessity of integrating therewith specific circuits capable of ensuring the resetting of all the functional elements of the integrated circuit to a certain state whenever power is switched on. This resetting must occur independently of the manner in which the supply voltage is raised from ground potential to the nominal supply voltage level, in order to prevent the occurrence of undesired and uncontemplated configurations of the integrated circuit, which may cause malfunctioning and possibly latching of the whole integrated circuit device. Such circuits are called power-on reset circuits, and are commonly referred to by the acronym POR. POR circuits perform the afore-mentioned function. These circuits are capable of generating a resetting pulse of predetermined characteristics upon the switching on of the integrated circuit. Generally, these POR circuits have an architecture which includes power dissipative, static current paths between the supply voltage nodes and, although these static current paths normally have a relatively high impedance, the persistence of a non-negligible static power consumption is not, in many cases, compatible with design specifications of CMOS integrated circuit devices, which typically have a null-static consumption. This problem is felt even more in special CMOS circuit devices which are destined to function for very short periods of time while being powered solely by the electrical charge stored in an electrolytic capacitor of several (µF) , wherein the static consumption caused by the power-on reset circuit assumes great relevance. These power-on reset circuits may in turn be themselves a cause of malfunctioning if they are likely to be accidentally triggered by internal or external transients, i.e. noise. Commonly, the power-on reset circuits have a structure such as the one which is shown in Fig. 1, which comprises two inverters, the first of which is formed by the complementary pair of transistors M5 and M4 and the second is indicated by the block I, connected in cascade. The output of the second inverter I coincides with the output node of the circuit. A voltage monitoring line (voltage driver) for the voltage which is actually present on the supply node is connected between the supply node and ground and substantially may comprise at least two directly biased junctions connected in series to each other, and which are realized with two diode-configured, transistors M1 and M2, and a resistance R1. The intermediate node Vx of this voltage sensing line drives the first inverter through the gate electrode of the M4 transistor. The capacitance C1 represents the capacitive coupling of the node Vx toward ground potential. The M3 transistor is driven by the voltage which is present on the intermediate connection node A between the two inverters and determines the dropping to zero of the reset signal produced by the POR circuit when the voltage Vx reaches the triggering threshold of the first inverter, that is when the voltage on the supply node has reached a safety level which is sufficiently high in its rise toward the nominal value VDD. In fact, at that point, the voltage on the A node becomes low, thus switching-off the M3 transistor, while the M1 and M2 junctions are kept conducting by R1. The drawback of such a circuit is current consumption. In fact, when the supply voltage has reached the nominal working level, R1 continue to draw a non-negligible current which, for a value of R1 of 300KΩ and a supply voltage (VDD) of 5V, may be of about 6.6µA. In many instances, such a current static absorption may be outside the specifications of the particular integrated circuit. Object of the present invention is to provide a power-on reset circuit (POR) having a low-static consumption and is particularly immune to spurious stimuli. This object and other related advantages are obtained by the circuit of the present invention which is characterized by having a reduced static consumption as compared with the known circuits and an enhanced immunity to noise. Basically, the method herein proposed for reducing the current absorption under static condition of a power-on reset circuit comprises biasing with an extremely low current a pair of transistors functionally utilised in the supply voltage monitoring line, until the supply voltage remains relatively low. This has the purpose and effect of bringing said transistors in a condition normally referred to as "sub-threshold" operation. This is a peculiar condition of operation proper of field effect (MOS) transistors which occurs for gate-to-source voltages close to the transistor's threshold voltage. Under these bias conditions, the MOS transistor conducts an extremely low current and the input-to-output transfer characteristic becomes exponential instead of being quadratic. Such an operation condition is amply described in the article entitled "CMOS Analog Integrated Circuits Based on Weak Inversion Operation" by Eric Vittoz and Jean Fellrath, IEEE Journal of Solid-State Circuits, vol. SC-12, No. 3, June 1977. According to the invention, such an objective is achieved in practice by employing a reference current generator having a characteristic defined by the ratio δVbe/R, by the use of which a first bias current is delivered to a pull-up element of the first inverter of the circuit according to a certain current-mirror ratio, and a second bias current is delivered to a first element of said supply voltage monitoring line which is functionally connected to the supply node, in order to force a certain current through this sensing line. The intermediate node of connection in cascade between two inverters of the circuit drives a second element capable of being biased and functionally connected to ground of the supply voltage sensing line, as well as a control terminal of the current generator, through which the current delivered by the generator may be modified in order to reduce it during the periods of operation of the integrated circuit. The different aspects and related advantages of a POR circuit made in accordance with the present invention will be better illustrated through the following description of several embodiments thereof and by referring to the annexed drawings, wherein: Fig. 1 , is a circuit diagram of a power-on reset circuit of the prior art, as already described before; Fig. 2 , shows a power-on reset circuit made in accordance with the present invention; Fig. 3 , shows how the pull-down element of the first inverter of the power-on reset circuit may be made so as to introduce a certain hysteresis in the triggering performance of the inverter. With reference to Fig. 2 , the main aspect of the circuit of the invention is represented by the use of a current generator having an operating characteristic of a δVbe/R type and which preferably may be implemented by the use of a pair of transistors, Q1 and Q2, and a current mirror made with a pair of MOS transistors, M5 and M6. In the embodiment shown, an unbalance between the emitter voltages of the transistors Q1 and Q2, which is transformed in a current signal by the resistance R3 (emitter degeneration of Q1), is determined by making transistor Q1 and Q2 of different size, e.g. the Q1 transistor of a size double the size of the Q2 transistor. Viceversa, the pair of MOS transistors which form the current mirror may have, in the context of the example shown, identical dimensions (indicated by their "aspect ratio" 80/8, where the first number indicates the channel width and the second number the channel length in arbitrary units). The current mirror formed by the transistors M5 and M6 has only the scope of forcing the same current through the transistors Q1 and Q2. This type of current generator is well known in literature and the current which flows through Q1 and Q2 is given by I Q1 = I Q2 = (V T ln A 1 /A 2 )R3, where V T is the so-called "thermal voltage" (V T ≈ 26mV at 300K 0 ) and A 1 /A 2 is the area ratio between Q1 and Q2. Therefore, such a current will have a value given by I Q1 = I Q2 = 0.6µA. This current is utilised for biasing the pull-up element of the first inverter which is formed by the pair of complementary transistors M3 and M4, which may be appropriately dimensioned, as indicated by the relative values shown in Fig. 2. Actually the M3 transistor is biased by mirroring the generator current according to a certain current mirror ratio which, for the example shown in Fig. 2 is given by M 5 /M 3 = 80/8/20/8 = 4. Therefore, the bias current of M3 is: 0.6µA/4 = 0.15µA. Moreover, the generator's current is also delivered through transistor Q3 as a biasing current to an element of the voltage sensing line capable of being biased and which may be represented by MOS transistor M1, having dimensions as indicated in the figure. In practice, the M1 transistor may be biased with the same current which flows through the transistors Q1 and Q2 (0.6µA), through the transistor Q3, the base of which is connected to the bases of the transistors Q1 and Q2 of the current generator. After having so examined the biasing arrangements, the operation of the whole circuit may be described as follows. At the instant the voltage on the supply node starts to rise (i.e. upon switching-on the device) the intermediate driving node Vx of the sensing or biasing line, between the two limiting resistances R1 and R2, because of its capacitive coupling with the ground potential, which is depicted by the capacitance C1, remains for a certain period of time to a relatively low level and permits a persistence of a high logic level on the drain of the pull-down element M4 of the first inverter. As a consequence, the output (OUT) remains low and the transistors M2 and M7 conducting. The conduction of M2 practically ties to ground potential one terminal of the resistance R2, while the conduction of M7 practically connects to ground a terminal of the resistance R4. This purposely modifies the working conditions of the current generator which, as long as the resistance R4 remains substantially connected to ground (thus constituting a by-pass path of the current which is forced through the circuit of the current generator), determines altered operation conditions of the current generator. In these conditions, the generator delivers a relatively high current as compared to the current which would be delivered under normal operation conditions of the generator without being subject to the influence of the resistive connection to ground through R4 (i.e. during a stand-by period of the circuit). Under these conditions, and by supposing that the voltage on the supply node has reached a level of 3V, the current delivered by the generator would be given by (VDD - V gsM5)/R4 = 1.7 V/200kΩ = 8,5µA. Therefore, the current through the pull-up transistor M3 of the first inverter will be equal to about 2µA. The triggering of the circuit will take place when the voltage on the supply node reaches a value so that: I M4 = I M3 ≈ 2µA. The equation describing the operation of the circuit may then be written as: I M3 = I M4 = Kn (W/L) M4 (W gsM4 - V THn ) 2 by considering that V gsM4 = VDD - V gsM1 R2/(R2 + R1) and V gsM1 = V Tp + 1/I M1 1/Kp L/W M1 wherein Kn and Kp are technological constants (i.e. characteristic of a particular fabrication process of the device), W/L is the aspect ratio, i.e the ratio between the channel width and the channel length and T THn,p is the threshold value of either n-channel (n) or of p-channel (p) transistors. The current which flows through the transistor M1 of the sensing (biasing) line depends on the value of the two limiting resistances R1 and R2. The relatively complicated equation may be resolved through a process of re-normalization with the aid of a computer and leads to a triggering voltage of about 3.6V. When this triggering voltage is reached by the node Vx, the circuit triggers. The output OUT becomes high, M2 and M7 are switched-off and the current generator returns to generate its characteristic current thus modifying the bias of the pull-up transistor M3 of the first inverter which will conduct a current given by: I M3 = 0.15µA and also the transistor M1 of the supply voltage monitoring line will return to conduct a current given by: I M1 = 0.6µA, under the control of the current generator (Q1, Q2) which is free of functioning without being forced by the ground connection line through the resistance R4. The total consumption of the circuit, as described in Fig. 2, is 2µA, which is made up of the following contributions: I M5 , 0.6µA; I M6 , 0.6µA; I M3 , 0.15µA; I M1 , 0.6µA; and such a condition of power consumption remains unaltered by a variation of the supply voltage within a certain design range during the normal operation of the integrated circuit. When the supply voltage drops (e.g. upon the switching-off of the integrated circuit), the circuit will trigger again when the voltage on the control node Vx of the supply voltage monitoring line drops below the triggering voltage of the M4 transistor, i.e.: VDD - V gsM1 = V gsM4" Because of the relatively low current levels of the circuit, it may be supposed that, V gsM1 = V TH,p and V gsM4 = V TH,n thus: VDD - V TH,p ≈ V TH,n" The triggering of the circuit will occur when VDD = V TH,n, + V TH,p ≈ 2V. This is an extremely advantageous characteristic of operation because, by considering that normally logic circuits are still functioning when VDD = V TH,n + V TH,p , the action of the power-on reset circuit of the invention positively occurs when the value of the voltage on the supply node has reached a level at which the integrated circuit is still functioning correctly. According to a particularly preferred embodiment of the circuit, the pull-down transistor M4 of the first inverter of the circuit may be advantageously replaced by an appropriate, equivalent structure, as the one depicted in Fig. 3, formed by three n-channel MOS transistors, M4A, M4B and M4C. The use of this equivalent pull-down structure, is particularly preferred because it introduces a small hysteresis in the triggering response of the first inverter of the circuit, thus increasing the noise immunity characteristics of the POR circuit of the invention.

Claims: A power-on reset circuit for generating a reset signal which, upon powering, follows the voltage present on the supply node until it reaches a preset level and thereafter stably switches to ground potential, substantially comprising a first and a second inverter connected in cascade, the output of the second inverter constituting the output of the circuit, a supply voltage sensing line connected between a supply node and ground and providing on an intermediate node thereof a driving signal (Vx) for said first inverter; means (M2), driven by a second signal present on a connection node (A) between said two inverters, capable of forcing a current through said supply voltage sensing line when said driving signal (Vx) is lower than a triggering threshold of said first inverter, and characterized by comprising further a current generator (Q1,Q2,Q3) having a control terminal and capable of being forced in a first operating condition and in a second operating condition whereat the current generated is lower than the current generated during said first condition, and which provides a first bias voltage to a pull-up element (M3) of said first inverter according to a certain current mirroring ratio and a second bias current to a first element (M1) of said voltage sensing line which is functionally connected to said supply node, so as to force a certain current therethrough; said connection node (A) between said two inverters being connected to said control terminal of the curent generator and to a control terminal of a second element (M2) of said voltage sensing line which is functionally connected to ground and which consitutes said means; the triggering of said first inverter determining the switching off of said second element (M2) of said voltage sensing line and forcing said current generator into said second operating condition. The circuit as defined in claim 1, wherein said intermediate node of the voltage sensing line is connected to the supply node through a series combination of a resistance and a diode-connected p-MOS transistor and to ground through a series combination of a second resistance and an n-MOS transistor; said transistors being biased with a gate-to-source voltage close to the threshold voltage in order to determine a subthreshold working condition of the transistors upon powering the circuit. A circuit as defined in claim 2, wherein said current generator has a characteristic of operation of a δVbe/R type and said control terminal is constituted by a gate electrode of an n-MOS transistor (M7) which establises a by-pass current path to ground in order to force said generator into said first condition of operation until the triggering of said first inverter occurs. A circuit as defined in claim 1, wherein first inverter is the said pull-down element of said an n-MOS transistor (M4). A circuit as defined in claim 1, wherein said first inverter pull-down element of said is made of a network functionally equivalent to an n-MOS transistor and capable of introducing a hysteresis in the triggering characteristic of the said first inverter.

Inventors: FUCILI GIONA, GOLA ALBERTO, FUCILI, GIONA, GOLA, ALBERTO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H03K17
IPC codes: H03K17, G06F1