Spiral resistor integrated on a semiconductor substrate

Abstract: A spiral resistor (1), being of a type formed on a semiconductor substrate (2) to withstand high voltages, comprises at least one thin field-plate layer (6) covering said substrate (2) between adjacent turns (5) of the resistor. This prevents the well-known phenomenon of the "phantom gate" from occurring which would result in the characteristics of spiral resistors deteriorating over time.

Description: This invention relates to a spiral resistor of a type comprising a semiconductor substrate having a first conductivity type and a spiral resistive region of the opposite conductivity type integrated within the substrate to withstand high voltages having a plurality of turns. In the specific field of application of this invention, it is common practice to provide high-voltage resistors with a horizontal geometry which is essentially spiral-shaped and formed on a semiconductor substrate having a predetermined, opposite polarity from that of the resistor. One such construction is known, for instance, from US Patent No. 4,792,840 and allows the resistor to so distribute the equipotential lines across the substrate surface as to hold the difference of potential at the junction points between the resistor and the substrate surface below the junction breakdown voltage. The potential difference varies linearly toward the spiral center, which allows the resistor to withstand high voltages of up to 400 Volts. While being beneficial from this point of view, said prior approach still has a serious drawback. When any two regions of the resistor are taken which lie close to each other, i.e. regions of two adjacent turns or convolutions, one of them is bound to be at a lower potential than the other. As a result, the positive charges present in the oxide layer that covers the spiral will be pulled toward the metallic contact associated with the lower potential region. The build-up of positive charges gradually forms a conductive layer proper, referred to in the art as "phantom layer", which extends toward the lower potential region. This phantom layer, being additionally connected to a negative potential present at the metallic contact, establishes conduction between the aforesaid two and underlying regions at different potentials. Briefly stated, the phantom layer functions as if it were the gate of a MOS transistor, with the two regions at different potentials corresponding to the source and drain of the transistor. This reflects in deep alteration of the spiral resistor characteristics, and deterioration of its reliability. A second solution proposed by the prior art is disclosed in the US patent No. 4,423,433 to Imaizumi. Imaizumi teaches the use of electrodes 161 and 162 over linear resistors 13 on a silicon n-type layer 12 covered by an isulating film. However, this document does relate to a spiral resistor and does not contemplate nor treat the 'phantom gate' phenomenon. Even the problem of breakdown between adjacent resistive regions of a spiral resistor is not considered. The underlying technical problem of this invention is to provide a spiral resistor of the kind outlined herein above, which has such constructional and performance characteristics as to overcome this serious drawback besetting the prior art. Accordingly, it is an object of this invention to provide a spiral resistor which can retain its characteristics unaltered over time. Another object of the invention is to provide a resistor which can be used as a high-voltage edge termination in an integrated power circuit. The solutive idea on which the invention stands is one of having the semiconductor layer covered between turns of the resistor with a field-plate layer. Consistent with this solutive idea, the technical problem is solved by a resistor as indicated and defined in Claim 1. The features and advantages of a spiral resistor according to this invention will become apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a top plan view showing schematically a spiral resistor according to the invention; Figure 2 is a schematic cross-sectional view taken through the resistor in Figure 1 along line II-II; Figure 3 is a schematic top plan view, drawn to an enlarged scale, of a detail of the spiral resistor according to the invention; and Figure 4 is a cross-sectional side view, taken along line IV-IV, of the detail shown in Figure 3. With reference to the drawing views, generally and schematically shown at 1 is a spiral resistor embodying this invention which is formed on a semiconductor silicon substrate 2 of an integrated circuit or chip. The substrate 2 comprises a first base region having predetermined conductivity, e.g. of the N+ type, and being covered with an epitaxial layer 3 of the N- type; the latter being conventionally covered and protected by an oxide layer 16. The resistor 1 is formed on a substrate surface to provide an essentially spiral-pattern region comprising a predetermined number of turns 5 and being doped oppositely from the epitaxial layer 3, e.g. of the P+ type. The spiral pattern may either be hyperbolic or "Archimedean"; it being in either case a region characterized by a reduced width with respect to its lenght effective to provide a desired resistance value. This region may be formed using conventional diffusion or implantation techniques so as to rise substantially to the surface of the epitaxial layer 3. For convenience of illustration, the drawings show but a few of the turns 5, but their number may be a large one in actual practice. The turns 5 are separated by portions of the epitaxial layer which ensure electric insulation thereof. Centrally on the spiral, there may be formed such electronic power devices as a control circuit 12 and a power transistor 13. Such circuits may be enclosed in insulating pockets 14 normally connected to ground in accordance with known techniques. The substrate 2 has an edge 10 to which one end 9 of the resistor 1 is connected. The connection is provided by a metallization contact 7. Advantageously, according to the invention, there are deposited over the epitaxial layer 3 of the semiconductor thin metallization layers 6 of the field-plate type which extend between adjacent turns 5 of the resistor 1. In essence, these field-plate layers 6 would cover the epitaxial N- regions between two P+ regions of adjacent turns 5. With reference in particular to Figure 3, it can be seen that, starting from the edge 10, whereto the end 9 of the resistor 1 is connected, contacts 11 are opened in the resistor turns 5 to which the metallic field plates 6 are connected. In order to have said field plates 6 correctly polarized, the connection is established on the higher potential one of two adjacent turns. Stated otherwise, when two adjacent P+ regions of two turns 5 are considered, the field plate 6 that covers part of the epitaxial N- region extending between said P+ regions is connected to the higher electric potential region via the contact 11. As previously mentioned, of two adjacent turns, the higher potential one would always be the outward turn, that is the larger radius one. The connection between a field-plate layer 6 and a P+ region of a turn 5, using the contact 11, can be accomplished by placing the contact at one end of the field plate, as shown in Figure 3. It would be equally possible, however, to position the contact at any other intermediate location on the thin layer 6. It can be appreciated from the foregoing that the metallization layer 6 functions as the gate electrode of a P-channel MOS transistor having the two turns 5 for its source and drain electrodes. However, this is a shut-down transistor because of its gate being connected to the higher electric potential. Thus, the phenomenon known as "phantom gate" is effectively prevented from occurring by the metallic shielding provided by the field plate 6. It matters to observe that the field-plate metallization should be partialized, in the sense that its continuous connection to the higher potential (which would be that of the substrate) is not to be recommended. In fact, a decrease in the radius of curvature and packing of the equipotential lines together at the surface would otherwise occur which result in the N-P junction breaking down at the lower potential turn in the spiral. The field-plate metallizations 6 should be partialized by so selecting the length of each individual metallic section as to prevent the potential difference between the field-plate and the P+ regions of the two turns 5 from bringing about concentration of the equipotential lines at the surface of the epitaxial layer 3, which would actually bring about the aforesaid breakdown phenomenon. Such dimensioning would obviously have to be tied to the number of the turns 5 in the spiral resistor 1, because the potential difference between one turn and its adjacent one decreases as the number of the turns increases. In view, therefore, of that a break, indicated at 15 in the drawings, has been suitably provided between a field plate 6 and the next, a small portion of the N- channel separating adjacent P+ regions will be left exposed by the metallization. Since this could represent a weakness in the construction, the invention uniquely provides for these portions 15 left uncovered by the metallization to lie offset from one another, substantially as shown in Figure 3. The inventive resistor solves the technical problem and affords a number of advantages, of which the most important one is that the occurrence of the phantom gate phenomenon can be effectively prevented. Thus, the resistor can retain its resistance characteristics unchanged over time.

Claims: A spiral resistor of a type comprising a semiconductor substrate of a first conductivity type and a spiral resistive region of the opposite conductivity type integrated within the substrate to withstand high voltages having a plurality of turns, characterized in that it comprises a plurality of thin field-plate layers (6) located above the semiconductor substrate (2) and separated from the substrate by an insulating layer (16) to cover portions of said substrate (2) between any two adjacent turns (5) of the resistor, an electrical contact (11) being provided between each field-plate layer and said resistive region on the turn having the larger radius. A resistor according to Claim 1, characterized in that said thin field-plate layers (6) cover an epitaxial region (3) of the substrate (2). A resistor according to Claim 1, characterized in that each field-plate layer (6) is connected electrically to only one of the two adjacent turns (5) of the resistor. A resistor according to Claim 3, characterized in that said one of the two turns (5) is an outward turn having higher electric potential. A resistor according to Claim 3, characterized in that the electrical connection is provided by a contact (11) placed at an edge of each thin field-plate layer (6). A resistor according to Claim 1, characterized in that each thin field-plate layer (6) has a predetermined length and only extends through a section of said spiral. A resistor according to Claim 1, characterized in that said plurality of thin field-plate layers (6) extend discontinuously over the spiral. A resistor according to Claim 7, characterized in that each thin field-plate layer (6) has an inversely proportional length to the electric potential difference between the two turn (5) sections covered by said layer (6). A resistor according to Claim 7, characterized in that, between two ends of two contiguous thin field-plate layers (6) , there extends an exposed portion (15) of the substrate, and that the exposed portions (15) of adjacent turns (5) are not radially aligned to each other.

Inventors: PALARA SERGIO, PALARA, SERGIO
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1992
Main classification: H01L29
IPC codes: H01L29