Method and apparatus for vertical interpolation

Abstract: In TV systems like SECAM, MAC, MUSE, etc. the chrominance signals are transmitted on alternate lines. Precautions have to be taken in account in order to avoid sampling artefacts, but these precautions are not made in each of these standards. According to the invention the chrominance signal can be prefiltered prior to alternate line omission and post-filtered for a full-line display. The inventive adaptive filter for improving the picture quality uses additional information from the other colour component or even from the luminance signal.

Description: The present invention relates to a method and to an apparatus for vertical interpolation. Background The reduction of the chrominance resolution in vertical direction with regard to the luminance resolution in TV systems is a valid point which corresponds to the behaviour of the human visual system. For that reason in TV systems like SECAM, MAC, MUSE, etc. the chrominance signals are transmitted on alternate lines. In doing this some precautions have to be taken in account in order to avoid sampling artefacts, but these precautions are not made in each of these standards. US-A-4796085 discloses an vertical colour signal interpolating apparatus using the arithmetic mean for interpolation. Invention It is one object of the invention to disclose a method for improved vertical chrominance interpolation. This object is reached by the inventive method disclosed in claim 1. It is a further object of the invention to disclose an apparatus which utilizes the inventive method. This object is reached by the inventive apparatus disclosed in claim 7. The most severe artefacts like mentioned above are exhibited in the SECAM standard because of the applied-four field sequence. It causes a 12.5Hz activity which is particularly disturbing. This is due to the fact that a great deal of the chrominance flickering will be converted into a luminance flickering by the display non-linearity. In todays analogue SECAM encoders there is no pre-filtering applied and also not foreseen in the next future. That means the problem of how to overcome the 12.5Hz edge flickering in SECAM decoders still exists. According to the invention the chrominance signal can be prefiltered prior to alternate line omission and post-filtered for a full-line display. In principle the inventive method consists in vertical interpolation of lines in alternate line transmission TV systems and/or recording systems, wherein the missing lines and pixel values of missing lines, respectively, are calculated according to the formula C(i) int = [Δ down *C(i-1)+Δ up *C(i+1)]/[Δ down +Δ up ], pixel difference Δ down = |C(i)-C(i+2)|, pixel difference Δ up = |C(i)-C(i-2)|, wherein C(i) is the respective value from the actual line and C(i-1) is the respective value from the line above and C(i-2) is the respective value from the preceding line and C(i+1) is the respective value from the line below and C(i+2) is the respective value from the following line. Advantageously said interpolation is adaptively changed to C(i) int = [C(i-1)+C(i+1)]/2, if the values of C(i-1) and C(i+1) are equal. The C(i) int , C(i-1) and C(i+1) values may correspond to lines with an U colour component and the C(i), C(i-2) and C(i+2) values may correspond to lines with a V colour component and viceversa, respectively. Advantageous additional embodiments of the inventive method are resulting from the respective dependent claims. In principle the inventive apparatus consists of a first line delay circuit 431 to which U and V input signals are fed and which input is connected to the inverting input of a first combination circuit 421, wherein the output of said first line delay circuit 431 is connected to a second line delay circuit 432, to the inverting inputs of a second combination circuit 420 and of a third combination circuit 441 and to the first input of a first adder 442, and wherein the output of said second line delay circuit 432 is connected to a third line delay circuit 433, to the non-inverting input of said first combination circuit 421, to the inverting input of a fourth combination circuit 422 and to the first input of a multiplexer 444 which outputs the U and V output signals and wherein the output of said third line delay circuit 433 is connected to a fourth line delay circuit 434 and to the non-inverting inputs of said second 420 and said third 441 combination circuits, and wherein the output of said fourth line delay circuit 434 is connected to the non-inverting input of said fourth combination circuit 422 and the output of said third combination circuit 441 is connected to the first input of a first multiplier 443 and the output of this multiplier is connected to the second input of said first adder 442 and the output of this adder is connected to the second input of said multiplexer 444 and the output of said first combination circuit 421 is connected via a first absolute value circuit 419 to the first input of a second adder 417, representing signal Δ up , and the output of said fourth combination circuit 422 is connected via a second absolute value circuit 420 to the first input of a third adder 418, representing signal Δ down , and the output of said second combination circuit 420 is connected via a third absolute value circuit 423 and via a modified reciprocal value circuit 424, which adds e.g. one LSB, to the second inputs of said second 417 and third 418 adders, representing signal Δ, and wherein the output of said second adder 417 is connected via a first horizontal lowpass filter 415 to the first input of a fourth adder 45 and to the first input of a second multiplier 47, representing signal Δ up , and the output of said second adder 417 is connected via a second horizontal lowpass filter 416 to the second input of said fourth adder 45, representing signal Δ down , and wherein the output of said fourth adder 45 is connected via a reciprocal value circuit 46 to the second input of said second multiplier 47 and the output signal Δ of this multiplier is connected to the second input of said first multiplier 443 and said multiplexer 444 is synchronized by the U/V alternation signal coming from a line identification signal 48. Advantageous additional embodiments of the inventive apparatus are resulting from the respective dependent claims. Drawings Preferred embodiments of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 shows the sampling grid and spectrum for U and V signals; Fig. 2 depicts 12.5Hz flickering at a vertical chrominance transition; Fig. 3 shows the inventive adaptive vertical chrominance interpolation; Fig. 4 depicts an apparatus for the inventive interpolation. Preferred embodiments Fig. 1a illustrates the y-t-scanning grid applied within the SECAM standard for the U and V component. The lines within a field have a distance of 2*d from each other. Fig. 1b shows the corresponding f y -f t -spectra. The first vertical repeat center is located at 576c/h (cycles per picture height) in case of a 625 line system. If the chrominance signal is scanned in such a way and displayed without post-filtering the spectral area 10 of the spectrum centered on 144c/h vertically and 12.5Hz temporally would be near completely visible. This does mean that the alternate-line structure would become visible. Todays state-of-the-art SECAM decoders utilize only a line delay for the reconstruction of the missing U and V lines. In terms of the frequency behaviour this corresponds to a vertical post-filtering consisting of a cosine function with a first zero crossing at 144c/h. Therefore, only the frequencies around the center of this alias spectrum can be suppressed and for plane colour areas only an acceptable reconstruction is possible. It fails at horizontal edges. In Fig. 2a an example for a horizontal edge at position 21 in the spatial domain is given. Fig. 2a-e show the corresponding sample values for a sequence of 4 fields. With respect to line i at position 21 the scanned edge appears after the line repetition only once within the 4-field sequence. This results mainly in said 12.5Hz edge flickering. In case of line repetition 20 the dashed sample values are generated. The inventive adaptive filter for improving the picture quality is based on the idea of using additional information from the other colour component or even from the luminance signal. This can be done because there is normally a significant correlation between these components. Fig. 3 will illustrate the principal processing for a vertical chrominance transition 30. In the drawing it is assumed that the missing U component for the line i is to be interpolated. Instead of a simple average value of the adjacent values U(i+1) and U(i-1) for value U(i) an adaptively weighted average value should be applied which is controlled by the vertical differences Δ down and Δ up of the V component. In Fig. 3 the difference Δ up becomes zero while Δ down represents the step size of the colour edge. According to the formula given by U(i) int = [Δ down *U(i-1)+Δ up *U(i+1)]/[Δ down +Δ up ] = U(i-1)+[Δ up /(Δ down +Δ up )]*[U(i+1)-U(i-1)] = U(i-1)+α*[U(i+1)-U(i-1)] and Δ down = V i -V i+2 Δ up = V i -V i-2 only line U(i-1) will be used for the vertical interpolation in this example. That means with respect to Fig. 3 that the transition is located at the correct position and the full step height of the edge is preserved, which supplies reconstructed pictures with a maximum vertical sharpness and without 12.5Hz edge flickering. Furthermore this adaptation should be enabled only if there is a difference of U between line i-1 and i+1, otherwise a simple line average should be carried out. The enabling signal advantageously behaves like an inverse function of the difference of U in accordance with Δ = 1/[|U(i-1)-U(i+1)|+ε 1 ]+ε 2 in which ε 1 , ε 2 are small figures, e.g. an LSB bit or a value '1', just to provide reasonable results. In order to achieve a uniform vertical interpolation along a colour edge for noisy pictures the weighting factors Δ up and Δ down advantageously are horizontally lowpass filtered. An average over 5 pixels (f s = 17.718MHz) will already be sufficient. Advantageously the luminance signal can be used for a further improvement of the adaptivity in case that the other colour component contains no transition. Then the resulting weighting factors become Δ down = { Δ down +Δ+Δ lum down } LP Δ up = { Δ up +Δ+Δ lum up } LP and Δ lum down = Y i -Y i+1 Δ lum up = Y i -Y i-1 The processing in Fig. 4 follows the mathematical formula given above except that in the next line to be interpolated the U and V signals in the formula have to be exchanged. The multiplexer 444 at the output of the interpolation filter which is synchronized by the U/V alternation signal coming from the line identification signal 48 takes this fact into account. The Y input signal is fed to a first line delay circuit 401 and to the inverting input of a combination circuit 403. The output of line delay circuit 401 is connected to a second line delay circuit 402, to the non-inverting input of combination circuit 403 and to the inverting input of a combination circuit 404. The output of line delay circuit 402 is connected to the non-inverting input of combination circuit 404 and to a delay circuit 400 which outputs the Y output signal. The delay time τ is matched to the U/V processing time. The signals Y(i-2), Y(i-1) and Y(i) are respectively present at the input of first line delay circuit 401, at the input and at the output of second line delay circuit 402. The output signal of combination circuit 403 is serially fed to an absolute value circuit 405, to a horizontal low pass filter 407, to a subsampling circuit 409, to a third line delay circuit 411 and to the first input of an adder 413. At the output of line delay circuit 411 the signal Δ lum up is available. The output signal of combination circuit 404 is serially fed to an absolute value circuit 406, to a horizontal low pass filter 408, to a subsampling circuit 410, to a third line delay circuit 412 and to the first input of an adder 414. At the output of line delay circuit 412 the signal Δ lum down is available. The U and V input signals are fed to a fifth line delay circuit 431 and to the inverting input of a combination circuit 421. The output of line delay circuit 431 is connected to a sixth line delay circuit 432, to the inverting inputs of combination circuits 420 and 441 and to the first input of an adder 442. The output of line delay circuit 432 is connected to a seventh line delay circuit 433, to the non-inverting input of combination circuit 421, to the inverting input of combination circuit 422 and to the first input of multiplexer 444 which outputs the U and V output signals. The output of line delay circuit 433 is connected to an eighth line delay circuit 434 and to the non-inverting inputs of combination circuits 420 and 441. The output of line delay circuit 434 is connected to the non-inverting input of combination circuit 422. The output of combination circuit 441 is connected to the first input of a multiplier 443. The output of this multiplier is connected to the second input of adder 442. The output of adder 442 is connected to the second input of multiplexer 444. For example the signals V(i-2), U(i-1), V(i), U(i+1), V(i+2) are respectively present at the input of line delay circuit 431, at the input of line delay circuit 432, at the input of line delay circuit 433 and at the input and at the output of line delay circuit 434 and the signals V(i) and U(i) int are present at the inputs of multiplexer 444. The output of combination circuit 421 is connected via an absolute value circuit 419 to the first input of an adder 417, representing signal Δ up , and the output of combination circuit 422 is connected via an absolute value circuit 420 to the first input of an adder 418, representing signal Δ down . The output of combination circuit 420 is connected via an absolute value circuit 423 and via a modified reciprocal value circuit 424 (adding of 1 LSB) to the second inputs of adders 417 and 418, representing signal Δ. The outputs of these adders are respective connected via horizontal lowpass filters 415 and 416 to the second inputs of adders 413 and 414. The output of adder 413 represents signal Δ up and is connected to the first input of adder 45 and to the first input of multiplier 47. The output of adder 414 represents signal Δ down and is connected to the second input of adder 45. The output of adder 45 is connected via a reciprocal value circuit 46 to the second input of multiplier 47. The output signal α of this multiplier is connected to the second input of multiplier 443. If the signals Δ lum up and Δ lum down are not used for the interpolation, all circuits of the luminance processing, except delay circuit 400, can be omitted. The adaptive filter has been tested within a digital SECAM decoder. The simulation has shown that the impact of the filter on the picture quality is very impressive and that this kind of interpolation gives always better results than the simple line repetition in the analogue decoder. The results indicate that the adaptive vertical interpolation filter offers a maximum sharpness at horizontal edges. In contrast to that the known linear pre- and post-filtering is not able to achieve this sharpness because this filtering has to cope with the vertical resolution, the flickering and the aliasing together in a linear way of processing. This can at best result in a compromise between these parameters. If the source signal contains extremely fine vertical details advantageously an approximate pre-filtering should be foreseen. However, in order to supply a better picture quality the adaptive vertical interpolation filter in the decoder should always be used. The inventive interpolation can be used for all TV systems or recording systems based on an alternate-line transmission.

Claims: Method for vertical chrominance interpolation of lines in alternate line transmission TV systems and/or recording systems, characterized in that pixel values C(i) int of missing pixels in alternate lines are calculated according to the formula C(i) int = [Δ down *C(i-1)+Δ up *C(i+1)]/[Δ down +Δ up ], pixel difference Δ down = |C(i)-C(i+2)|, pixel difference Δ up = |C(i)-C(i-2)|, wherein C(i) is the respective value from the actual line and C(i-1) is the respective value from the line above and C(i-2) is the respective value from the preceding line and C(i+1) is the respective value from the line below and C(i+2) is the respective value from the following line, and wherein the C(i) int , C(i-1) and C(i+1) values correspond to lines with an U colour component and the C(i), C(i-2) and C(i+2) values correspond to lines with a V colour component and viceversa, respectively. Method according to claim, wherein said interpolation is adaptively changed to C(i) int = [C(i-1) +C(i+1)] /2, if the values of C(i-1) and C(i+1) are equal. Method according to claim 1 or 2, wherein Δ = 1/[|C(i-1)-C(i+1)|+ε 1 ]+ε 2 is added to said pixel differences (Δ down , Δ up ), and wherein ε 1 and ε 2 are small figures, e.g. one LSB bit or a value '1'. Method according to any of claims 1 to 3, wherein respective luminance pixel differences (Δ lum down , Δ lum up ) are added to said pixel differences (Δ down , Δ up ) of said colour components. Method according to any of claims 1 to 4, wherein said pixel differences (Δ down , Δ up , Δ lum down , Δ lum up ) are respectively horizontally low pass filtered or are respectively averaged over five horizontal adjacent pixel positions. Method according to any of claims 1 to 5, wherein the transmitted and/or recorded source lines (C(i-2), C(i-1), C(i), C(i+1), C(i+2)) are vertically prefiltered prior to transmission and/or recording. Apparatus for a method according to any of claims 1 to 6, consisting of a first line delay circuit (431) to which U colour component and V colour component input signals are fed and which input is connected to the inverting input of a first combination circuit (421), wherein the output of said first line delay circuit (431) is connected to a second line delay circuit (432), to the inverting inputs of a second combination circuit (420) and of a third combination circuit (441) and to the first input of a first adder (442), and wherein the output of said second line delay circuit (432) is connected to a third line delay circuit (433), to the non-inverting input of said first combination circuit (421), to the inverting input of a fourth combination circuit (422) and to the first input of a multiplexer (444) which outputs the U colour component and V colour component output signals and wherein the output of said third line delay circuit (433) is connected to a fourth line delay circuit (434) and to the non-inverting inputs of said second (420) and said third (441) combination circuits, and wherein the output of said fourth line delay circuit (434) is connected to the non-inverting input of said fourth combination circuit (422) and the output of said third combination circuit (441) is connected to the first input of a first multiplier (443) and the output of this multiplier is connected to the second input of said first adder (442) and the output of this adder is connected to the second input of said multiplexer (444) and the output of said first combination circuit (421) is connected via a first absolute value circuit (419) to the first input of a second adder (417), representing signal Δ up , and the output of said fourth combination circuit (422) is connected via a second absolute value circuit (420) to the first input of a third adder (418), representing signal Δ down , and the output of said second combination circuit (420) is connected via a third absolute value circuit (423) and via a modified reciprocal value circuit (424), which adds e.g. one LSB, to the second inputs of said second (417) and third (418) adders, representing signal Δ, and wherein the output of said second adder (417) is connected via a first horizontal lowpass filter (415) to the first input of a fourth adder (45) and to the first input of a second multiplier (47), representing signal Δ up , and the output of said second adder (417) is connected via a second horizontal lowpass filter (416) to the second input of said fourth adder (45), representing signal Δ down , and wherein the output of said fourth adder (45) is connected via a reciprocal value circuit (46) to the second input of said second multiplier (47) and the output signal α of this multiplier is connected to the second input of said first multiplier (443) and said multiplexer (444) is synchronized by the U/V colour alternation signal coming from a line identification signal (48). Apparatus according to claim 7, additionally consisting of a fifth line delay circuit (401) to which the Y luminance input signal is fed and which input is connected to the inverting input of a fifth combination circuit (403) and wherein the output of said fifth line delay circuit (401) is connected to a sixth line delay circuit (402), to the non-inverting input of said fifth combination circuit (403) and to the inverting input of a sixth combination circuit (404) and the output of said sixth line delay circuit (402) is connected to the non-inverting input of said sixth combination circuit (404) and to a delay circuit (400) which outputs the Y luminance output signal which delay time T is matched to the U/V processing time, and wherein the output signal of said fifth combination circuit (403) is serially fed to a fourth absolute value circuit (405), to a third horizontal low pass filter (407), to a first subsampling circuit (409), to a seventh line delay circuit (411) and to the first input of a fifth adder (413) which adds the output signal of said seventh line delay circuit (411) to the input signals of said fourth adder (45) and said second multiplier (47), and wherein the output signal of said sixth combination circuit (404) is serially fed to a fifth absolute value circuit (406), to a fourth horizontal low pass filter (408), to a second subsampling circuit (410), to an eighth line delay circuit (412) and to the first input of a sixth adder (414) which adds the output signal of said eighth line delay circuit (412) to the input signal of said fourth adder (45).

Inventors: BOIE WERNER, WATRIN THIERRY, BOIE, WERNER, WATRIN, THIERRY
Applicants: THOMSON MULTIMEDIA SA, THOMSON MULTIMEDIA
Application year: 1992
Main classification: H04N9
IPC codes: H04N9