Method and apparatus for generating PAL video signal by digital processing

Abstract: Disclosed is a method and apparatus for highly stably and accurately generating a PAL video signal by digital processing. The method and apparatus comprise generating a basic clock having a frequency which is 11 x N times (N : an integer) as high as a horizontal synchronization frequency F H , producing digital data of orthogonal color subcarriers, color difference signals and a luminance signal respectively with the timing of the basic clock, multiplying the digital data D B-Y and D R-Y of the color difference signals by the digital data Dsin and Dcos of the color subcarriers respectively to obtain digital data of two kinds of modulation signals, adding the digital data D Y+S of the luminance signal to the digital data of the two modulation signals, and effecting digital/analog conversion of the result of addition to provide the PAL video signal.

Description: BACKGROUND OF THE INVENTION This invention relates to a method preferably used in a PAL video signal generator apparatus for generating a PAL video signal by digital processing. Many proposals for the purpose of technological developments in regard to the PAL system have been made hitherto in an effort to provide an improved PAL video signal generator apparatus capable of operation with high performance. A prior art PAL video signal generator apparatus will be first described before describing the present invention, so that the present invention can be clearly understood. In the case of a video signal of PAL system, as the relation between its color subcarrier frequency F SC and its horizontal synchronization frequency F H does not have simple integral relation between them unlike those in an NTSC system because an offset frequency is 25 Hz, and, because of such a frequency relation, it is difficult to realize a PAL video signal generator apparatus capable of generating a PAL video signal by digital processing. Therefore, it is common practice to generate such a PAL video signal by analog processing. In such a prior art PAL video signal generator apparatus relying on the analog processing, it has been inevitable that the apparatus becomes large in its size resulting in an undesirable increase in the number of points to be adjusted, and it has been difficult for the apparatus to highly stably and accurately generate the PAL video signal. US-A-4 349 833 describes apparatus for digital demodulation or modulation of television chrominance signals employing line-locked sampling. The subcarrier digital signals for digital demodulation are derived with the correct frequency from sampling rate clock pulses. Although the apparatus is described mainly in relation to NTSC signals, similar provisions for PAL are described. US-A-4 982 179 describes composite video signal generation in which a digital luminance signal and two digital chrominance signals combined from digital primary colour component signals are calculated. A subcarrier is balance-modulated by the two digital chrominance signals, and the balance-modulated signals and the luminance signals are combined. In the balance-modulation step, a series of phase information values by adding one by one a value of a sampling period of the digital primary colour component signal per subcarrier period is obtained, cosine function values and sine function values are operated in response to the phase information values, and the cosine function values and the sine function values are multiplied by the two digital chrominance signals respectively. FR-A-2 520 178 describes the use of a frequency llxN times the horizontal frequency of a PAL video signal as being specially suitable for the generation of PAL synchronisation signals. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and apparatus for highly stably and accurately generating such a PAL video signal by digital processing. According to the present invention, as defined by the claims, which attains the above object, a frequency which is 11 × N times as high as the horizontal synchronization frequency F H of the PAL video signal is used as a basic clock, and the PAL video signal is quantized on the basis of the clock having the frequency 11·N·F H so as to generate the PAL video signal in a digital mode. In the method and apparatus of the present invention, the frequency of the basic clock is selected to be 11·N·F H , so that the amount of quantized data required for generating color subcarriers in the form of a continuous sinusoidal wave can be compressed to be stored in a memory available on the market and having a capacity enough to store these quantized data. When, for example, the value of N is N ≦ 104, a single memory having a capacity of 64 kilobits can store these quantized data. The quantized data of the color subcarriers thus obtained change with the same timing as that of the data of the color difference signals quantized also on the basis of the clock described above. Therefore, these signals are multiplied and added in the form of the digital data so as to produce the digital data of the complete color signal. Then, the data of the luminance signal and those of the synchronizing signals are added to the data of the color signal to obtain the digital data of the PAL video signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a waveform diagram illustrating the basic principle of the present invention. Fig. 2 is a timing chart illustrating the basic principle of the present invention. Fig. 3 is a block diagram showing the structure of an embodiment of the PAL video signal generator apparatus according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the PAL video signal generator apparatus according to the present invention will now be described by reference to the drawings. In a PAL video signal to which the present invention is directed, its color subcarrier frequency F SC and its horizontal synchronization frequency F H have the relation expressed by the following equation (1): F SC = (1135/4+1/625) F H = (709379/2500) F H When a sinusoidal signal having the above frequency is expressed as F(t), the following equation (2) is obtained: F(t) = sin {2π F SC ·t} The sinusoidal signal F(t) is continuous relative to time t. When the sinusoidal signal F(t) is sampled at a sampling period T, and the result is expressed as F[n], F[n] can be expressed by the following equation (3): F[n] = sin {2π F SC ·nT} = sin {2π (709379/2500) F H ·nT} where n is the sampling number. Fig. 1 is a graph showing the relation between F(t) and F[n]. In Fig. 1, the sampled values F[n] relative to the sampling number n are indicated by round marks O. When now the sampling frequency for F(t) is selected to be M times (M : an integer) as high as the horizontal synchronization frequency F H , the sampling period T is expressed by the following equation (4): T = 1/(M F H ) = (1/M) T H where T H = 1/F H . From the equations (3) and (4), F[n] is expressed by the following equation (5): F[n] = sin {2π (709379/2500) (1/T H ) n (T H /M)} = sin {2π (709379/2500) n/M} The sampling frequency M F H is required to be a frequency higher by two or more times than the color subcarrier frequency F sc . When the value of M is selected to be an integer satisfying the above condition, the number of the sampled data F[n] required so that the sinusoidal signal F(t) having the frequency Fsc can be maintained continuous is 2500 × M according to the equation (5). Noting the fact that the greatest common divisor of the value 709379 in the equation (5) is 11, F[n] can now be expressed as follows: F[n] = sin {2π (64489 × 11/2500) n/M} Therefore, when the value of M is selected to be 11 x N (N: an integer), F[n] is now given by the following equation (7): F[n] = sin {2π (64489/2500) n/N} According to the present invention, all of the color signal,luminance signal and synchronizing signals constituting the PAL video signal are generated on the basis of the same clock having the frequency 11·N·F H . Thus, when the bandwidth occupied by the PAL video signal is 6 MHz, the value of the clock frequency 11·N·F H is required to be higher than 12 MHz which is two times as high as the bandwidth occupied by the PAL video signal. In view of the above condition, the required value of N is given by the following expression (8): 11·N·F H ≧ 12 MHz Therefore, the value of N is expressed as follows: N ≧ 70 The present invention will now be described by reference to Fig. 2 in which the value of N is set at 80. Thus, when N = 80, the value of the clock frequency is 880F H . In this case, the amount of the sampled data F[n] required to maintain continuous the sinusoidal signal F(t) is 2500 × N = 200000. When a clock having a frequency M F H , for example, a clock having a frequency 879F H which is close to the clock frequency 880F H but which is not equal to 11·N·F H is used in lieu of the clock frequency 880F H , the amount of the sampled data F[n] required to maintain continuous the sinusoidal signal F(t) is 2500 × 879 = 2197500. This amount corresponds to about 11 times as large as that required when the clock frequency 880F H is used. The above discussion teaches that, when the basic clock frequency is selected to be integer times as high as 11 F H where F H is the horizontal synchronization frequency, the amount of sampled data required to generate the sinusoidal signal F(t), that is, the color subcarrier can be compressed to about 1/11 of that required when the basic clock frequency has any other values. For the storage of the 200000 sampled data described above, a plurality of memories, for example, four memories each having a capacity of 64 kilobits are required. However, it will be apparent from Fig. 2 that, when the symmetry of the data is noted, the amount of data to be stored is only 50001 data corresponding to the relation 0 ≦ n ≦ 50000 where n is the sampling number. Such an amount can be sufficiently stored in a single memory having a capacity of 64 kilobits. A control pulse signal A as shown in Fig. 2 is used for reading out the 50001 data from the memory. The operation of a memory read counter is controlled so that the counter counts up in each low level period of the control pulse signal A, while the counter counts down in each high level period of the control pulse signal A. Further, the polarity of the data read out from the memory is inverted only when control pulse signals B and C are in their high level. By so controlling, continuous sine and cosine digital data can be generated. Thus, two color subcarriers orthogonal to each other can be generated. Fig. 3 is a block diagram showing the structure of an embodiment of the PAL video signal generator apparatus of the present invention using the color subcarrier generating method described above. Referring to Fig. 3, a clock 10, that is, the basic clock having the frequency 11·N·F H used for realizing the concept of the present invention is stably generated from an oscillator, for example, a crystal oscillator 27. Memories 11 and 12 store digital data obtained when the two color subcarriers orthogonal to each other are quantized with the timing of the clock 10. The digital data stored in the memories 11 and 12 are sequentially read out by an updown counter 13 with the timing of the clock 10. Memories 14 and 15 store digital data obtained by quantizing the color difference signals R-Y and B-Y with the timing of the clock 10 respectively. A memory 16 stores digital data obtained by quantizing the luminance signal (including the synchronizing signal) with the timing of the clock 10. A counter 17 is used to read out the data from the memories 14, 15 and 16 with the timing of the clock 10. Polarity inverter circuits 18 invert the polarity of the data outputted from the memories 11 and 12 in response to the application of the control pulses C and B respectively. In response to the application of a PAL pulse signal, a polarity inverter circuit 19 inverts the polarity of the data outputted from the memory 14. Digital multipliers 20 operate with the timing of the clock 10. The apparatus further includes adders 21, 22, a D/A converter 23, a low-pass filter 24, a buffer 25 and a video signal output terminal 26. The relation between the components of the apparatus and their operation will now be described. The updown counter 13 operating with the timing of the clock 10 orderly repeats its upcounting and downcounting operation under control of the first control pulse signal A shown in Fig. 2. The polarity of the data thus read out from the memories 11 and 12 is inverted by the respective polarity inverter circuits 18 in the high level period only of the second control pulse signals B and C shown in Fig. 2. As a result, data Dcos and Dsin of the two color subcarriers orthogonal to each other appear as outputs of the respective polarity inverter circuits 18. By the function of the counter 17 making its counting operation with the timing of the clock 10, color difference signal data each corresponding to one line are sequentially outputted from the memories 14 and 15. The polarity of the data read out from the memory 14 is inverted in alternate lines by the polarity inverter circuit 19 inverting the data polarity in response to the application of the PAL pulse to provide data D R-Y of the regular color difference signal R-Y. On the other hand, the data outputted from the memory 15 directly provide data D B-Y of the regular color difference signal B-Y. Then, with the timing of the clock 10, one of the digital multipliers 20 multiplies the color difference signal data D R-Y by the color subcarrier data Dcos, while the other digital multiplier 20 multiplies the color difference signal data D B-Y by the color subcarrier data Dsin, and the adder 21 adds these results of multiplication to provide its output given by D R-Y x Dcos + D B-Y x Dsin. Then, when the one-line luminance signal data D Y-S read out from the memory 16 by the counter 17 is added in the adder 22 to the output of the adder 21, the complete digital data of the PAL video signal appears at the output of the adder 22. Then, when the digital data output of the adder 22 is converted by the D/A converter 23 into the corresponding analog signal with the timing of the clock 10, and the analog signal is passed through the low-pass filter 24 and the buffer 25, the PAL video signal can be stably derived from the video signal output terminal 26. It is apparent that a plurality of video signals can be derived from the output terminal 26 of the illustrated embodiment when various data to be stored in the memories 14 to 16 are prepared. Therefore, according to the present invention, the color subcarrier signals having an entirely asynchronous relation between them with respect to the line period are sampled with the timing of a clock synchronous with the line period, so that such quantized data can be generated as fixed data. In this case, the value of the clock is selected to be 11·N·F H , that is, the frequency obtained by multiplying the horizontal synchronization frequency F H by a constant 11·N where N is an integer. By so selecting the value of the clock, the amount of the fixed data to be stored can be compressed to about 1/11, so that the data can be stored in a memory having a capacity preferable from both the aspect of cost and the aspect of circuit scale. Further, because the quantized data of the luminance signal, the synchronizing signal and the two color difference signals can be easily generated, the digital data of the PAL video signal can be completely produced, so that the PAL video signal can be generated with high stability and high accuracy. Also, because the value of N can be freely selected as desired, the frequency of the basic clock 11·N·F H can be selected to be suitable for each of a plurality of video signal generator apparatuses.

Claims: A method for generating a PAL video signal by digital processing comprising the steps of : selecting a basic clock frequency which is K times as high as the horizontal synchronisation frequency Fh corresponding to said PAL video signal, K being an integer; generating digital data D(B-Y), D(R-Y) and D(Y+S) of respective colour difference signals B-Y, R-Y and of luminance signal Y+S by quantization with the timing of said basic clock; generating digital data Dsin and Dcos representing orthogonal colour subcarriers by sequentially reading with the timing of said basic clock sine and cosine digital data out of memory means wherein the amount of quantized data required for generating colour subcarriers is stored; generating digital data of B-Y and R-Y modulation signals by multiplying respectively said digital data D(B-Y) and D(R-Y) of respective colour difference signals B-Y and R-Y by said digital data Dsin and Dcos representing orthogonal colour subcarriers; characterised in that K is a multiple of 11 and in that the method further includes the step of : generating the reading address of said memory means by incrementing or decrementing an updown counter with the timing of said basic clock frequency. An apparatus for generating a PAL video signal by digital processing comprising : means (27) adapted for generating a basic clock frequency which is K times as high as the horizontal synchronisation frequency Fh corresponding to said PAL video signal, K being an integer; means (29) for generating digital data D(B-Y) and D(R-Y) of respective colour difference signals B-Y and R-Y by quantization with the timing of said basic clock; memory means (11,12) for storing sine and cosine digital data signals corresponding to the amount of quantized data required for generating orthogonal colour subcarriers; address generation means (13) for sequentially reading digital data Dsin and Dcos representing orthogonal colour subcarriers from said memory means with the timing of said basic clock frequency; means (16) for generating digital data D(Y+S) of a luminance signal by quantization with the timing of said basic clock; multiplier means (20) for multiplying respectively said digital data D(B-Y) and D(R-Y) of respective colour difference signals B-Y and R-Y by said digital data Dsin and Dcos representing orthogonal colour subcarriers to obtain digital data of B-Y and R-Y modulation signals; first adder means (21) for adding said digital data of the B-Y modulation signal and said digital data of the R-Y modulation signal; second adder means (22) for adding said data D(Y+S) of the luminance signal to the result of addition by said first adder means; and digital/analog conversion means (23) for effecting digital/analog conversion of the result of addition by said second adder means; characterised in that K is a multiple of 11 and in that the said address generation means are an updown counter incremented or decremented with the timing of said basic clock.

Inventors: KOBAYASHI HIROAKI, KOBAYASHI, HIROAKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: H04N11
IPC codes: H04N9, H04N11