Nonvolatile semiconductor memory

Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11₀₀ to 11₂₂), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

Description: This invention relates to a nonvolatile semiconductor memory, particularly to an EPROM and an EEPROM including a nonvolatile memory circuit and, more particularly to a circuit construction of a nonvolatile semiconductor memory of the batch erasure type (hereinafter referred to as a flash memory). The invention further relates particularly to a circuit construction concerning a sense amplifying (S/A) circuit, supply of a supply voltage, improvement in the reliability of a writing operation, and a high speed reading operation in a nonvolatile semiconductor memory. Fig. 8 shows diagrammatically a structure of a cell used in a flash memory. In this figure, indicated at V G is a gate terminal, at V D a drain terminal, at V S a source terminal, at 27 a control gate CG connected to the gate terminal V G , and at 25 a floating gate FG which is controlled by the potential of the control gate CG. Further, indicated at 22 is a semiconductor substrate, e.g., a semiconductor substrate having P-type conductivity. On the semiconductor substrate 22 are mounted well portions 23, 24 made of semiconductor having N-type conductivity. The well portion 23 forms a drain while the well portion 24 forms a source. Indicated at 26, 28 are insulating films. When data is read from the cell, 0V is applied to the source terminal V S , a read voltage (normal supply voltage V CC ) of 5V is applied to the gate terminal V G , and a voltage of about 1V is applied to the drain terminal V D . Then, it is discriminated whether the read data is "1" or "0" depending upon whether a current flows through the cell. On the other hand, when data is written in the cell, 0V is applied to the source terminal V S , a write/erase voltage V PP of about 12V is applied to the gate terminal V G , and a write drain voltage V W (lower than V PP ) is applied to the drain terminal V D . Thereby, electrons are injected into the floating gate FG from a drain region (writing operation). Further, when the data is erased, the drain terminal V D is brought into an open state, and 0V and the write/erase voltage V PP are applied to the gate terminal V G and the source terminal V S respectively. Thereby, the electrons are taken from the floating gate FG to a source region (erasing operation). When the data is written, it is required to check whether the data is written sufficiently in the memory cell (write verification). Likewise, when the data is erased, it is required to check whether the data is erased sufficiently from the memory cell (erase verification). The write verification and erase verification are carried out so as to confirm whether the degree of writing and the degree of erasing have a sufficient margin for the read voltage, i.e., a variation range of the normal supply voltage V CC (5V ± 0.5V). Generally, these verifications are carried out to confirm that an operation margin of about 0.5V to 1.0V is available for a voltage range of V CC . In this case, the verify voltage including the operation margin is 6V to 6.5V in the write verification, and 3.5V to 4V in the erase verification. It is expected that the write verification and the erase verification can be accomplished easily if the verify voltage including the operation margin to be secured is applied to word lines (for example, word lines WL l to WL m of the flash memory shown in Fig. 1), so that the sensitivity of the S/A circuit is the same regardless of whether the voltage V CC or the verify voltage is applied as the supply voltage of the S/A circuit. US4875188 discloses a flash EPROM (nonvolatile semiconductor memory) in which such write and erase verification are accomplished by applying the appropriate verify voltage to the selected word lines. This nonvolatile semiconductor memory may be considered to have circuitry including a matrix of nonvolatile erasable memory cells formed at intersections of word lines and bit lines, a row decoder, a column decoder, and sense amplifiers connected to the bit lines, the nonvolatile semiconductor memory further including an internal source voltage generator for connection when the memory is in use to an external power source and operable selectively to produce predetermined internal source voltages in dependence upon the voltage of the external power source, such internal source voltages being applied to the said circuitry such that it carries out predetermined operations according to the internal source voltages, one of the said predetermined internal source voltages being a predetermined verify source voltage of a level suitable for performing a preselected verify operation on one of the said memory cells. In this memory, the internal source voltage generator is operable selectively to apply either a write verify source voltage or an erase verify source voltage to the selected word line during the write or erase verify operation, as the case may be, but is not capable of generating a normal source voltage of a level suitable for a normal reading operation. Fig. 9 shows a construction of a general S/A circuit used in the nonvolatile semiconductor memory such as an EPROM. In this figure, indicated at V CC is a line of a supply voltage 5V, and at V SS a line of a supply voltage 0V. Between the power supply lines V CC and V SS are connected a p-channel transistor 11 and an n-channel transistor 12 in series. A gate of the transistor 11 is connected to power supply line V SS , while a gate of the transistor 12 is connected to a data line (i.e., a bit line). Between the power supply line V CC and the data line is connected an n-channel transistor 13 whose gate is connected to drains of the respective transistors 11, 12. Likewise, between the power supply line V CC and the data line are connected a p-channel transistor 14 and an n-channel transistor 15 in series. A gate of the transistor 14 is connected to the power supply line V SS , while a gate of the transistor 15 is connected to the drains of the respective transistors 11, 12. An output (data output) of the S/A circuit is taken from drains of the respective transistors 14, 15. In this construction, when the data read from the memory cell is "1", i.e., when the level of the data line is "H", the transistor 12 is turned on and thereby a drain potential thereof is reduced to "L" level. Accordingly, the transistor 15 is cut off. Thus, the voltage of "H" level is output from the power supply line V CC through the transistor 14 (data output). In other words, the data having the same level as the read data is sensed. Conversely, when the data read from the memory cell is "0", the transistor 12 is cut off and the voltage of "H" level is fed from the power supply line V CC through the transistor 11 to the gate of the transistor 15 to turn the transistor 15 on. Thereupon, the level of a data output line is reduced to "L" (the data of "L" level is the same as the read data). In this way, the transistor 15 is provided with a function of transmitting the level of the bit line to the data output line (bit line level adjustment), and the transistor 14 is provided with a function of discriminating the data of the memory cell according to the state (on/off) of the transistor 15. In the construction of the conventional S/A circuit as described above, the sensitivity of the S/A circuit becomes dependent on the voltage V CC since the voltage V CC is used as a supply voltage, thus presenting the problem that an original object of the verification cannot be accomplished. On the other hand, the desired object can be accomplished if the voltage V CC is replaced by the verify voltage. However, since all the power to be consumed by the S/A circuit must be supplied by the verify voltage, the size, i.e., the current supplying performance of a power supply circuit for supplying the verify voltage is disadvantageously required to be increased. Moreover, in recent years, a high speed operation has been aimed at. However, there is a limit in carrying out the data writing, data reading, and erasing operations at a high speed in the conventional nonvolatile semiconductor memory in terms of its circuit construction and software, thus realization of higher operations are earnestly demanded. The present invention seeks to provide a nonvolatile semiconductor memory capable of solving the aforementioned various problems collectively and having high utility value and in particular an embodiment seeks to provide a nonvolatile semiconductor memory in which an S/A circuit is permitted to have the sensitivity compatible with any of a write verification and an erase verification even if a normal supply voltage is used, that is, a verification can be conducted sufficiently. Further, it is desirable to solve conventional problems residing in an internal supply voltage generating circuit used mainly in the nonvolatile semiconductor memory and to provide the internal supply voltage generating circuit capable of reducing a current consumption and supplying an external supply voltage after reducing the same stably. Moreover, it is desirable to provide a nonvolatile semiconductor memory in which a read voltage is reduced to a low voltage so as to consume less power so that the nonvolatile semiconductor memory is capable of carrying out verification satisfactorily and assuring a stable device operation even when it is operated at a voltage obtained by reducing a supply voltage internally. The prior art has also the problem that, when a read mode is executed in the nonvolatile semiconductor memory such as a flash type memory, the write data and the erase data in the read mode are erroneously determined, and thereby write and erase errors are liable to occur. It is desirable to overcome such defects residing in the prior art and to provide a power supply circuit used in a nonvolatile semiconductor memory such a flash type memory, the power supply circuit being provided with a supply voltage generating function with which a plurality of different supply voltages can be generated easily. According to the present invention, there is provided a nonvolatile semiconductor memory having circuitry including a matrix of nonvolatile erasable memory cells formed at intersections of word lines and bit lines, a row decoder, a column decoder, and sense amplifiers connected to the bit lines, the nonvolatile semiconductor memory further including an internal source voltage generator for connection when the memory is in use to an external power source and operable selectively to produce predetermined internal source voltages in dependence upon the voltage of the external power source, such internal source voltages being applied to the said circuitry such that it carries out predetermined operations according to the internal source voltages, one of the said predetermined internal source voltages being a predetermined verify source voltage of a level suitable for performing a preselected verify operation on one of the said memory cells; characterised in that another one of the said internal source voltages selectively producible by the internal source voltage generator is a normal source voltage of a level suitable for performing a normal reading operation on one of the said memory cells. Specifically, the nonvolatile semiconductor memory in one preferred embodiment comprises a cell matrix including erasable nonvolatile memory cells arranged at the intersections of the plurality of word lines and the plurality of bit lines, sense amplifying (S/A) circuits having two different kinds of source voltages supplied thereto and adapted to apply sense amplification to data of the selected line in the cell matrix, and a verify source voltage supply circuit for generating the two different kinds of source voltages in accordance with a control signal for instructing a write verification or erase verification, wherein a normal source voltage and a specific verify source voltage different from the normal source voltage are generated as the two different kinds of source voltage during the verification and the verify source voltage is applied to the selected word line. With the above construction, the specific verify source voltage different from the normal source voltage V CC is applied to the S/A circuit during the write verification or erase verification, and also to the selected word line. Accordingly, the sensitivity of the S/A circuit to the normal source voltage during a reading operation can be made equal to that of the S/A circuit to the verify source voltage during the verification. Further, margins during a data writing operation and an erasing operation can be checked sufficiently. The voltage supply circuit for supplying the verify source voltage V VER is used to reduce or boost the external source voltage of, e.g., 5V, to a specified level. However, the size of the voltage supply circuit is determined by the places to which the verify source voltage needs to be supplied. Accordingly, a preferred feature of the invention is to limit a place where the verify source voltage is supplied. In this way, the reading operation can be executed in the same state as in the prior art by supplying the verify source voltage to limited places. This enables a capacity of the verify source voltage supply circuit to be small, thereby permitting an area of the semiconductor memory itself to be reduced. Preferably, the internal source voltage generator comprises voltage reducing means for reducing an external supply voltage to a specified internal voltage, the voltage reducing means including a transistor connected between a line of the external supply voltage and a node where the internal voltage is generated, wherein a reference voltage of a predetermined level is applied to a gate of the transistor thereby to take out the reduced internal voltage from the internal voltage generating node. Alternatively, the nonvolatile semiconductor memory may comprise external voltage reducing means constructed similar to that mentioned above but adapted to receive a read external supply voltage and a write external supply voltage, and having means for reducing the read external supply voltage to a given value so as to operate a circuit for carrying out a reading operation in the nonvolatile semiconductor memory, and means for generating a word line potential at which verification is carried out after a writing operation by reducing the write external supply voltage. In one preferred embodiment of the invention, the nonvolatile semiconductor memory which includes a plurality of read modes and requires different supply voltages in the respective read modes, further comprises a supply voltage input portion, reference voltage generating means, boosting means including a capacity element, and charging means for charging the capacity element, the charging means including charge amount changing means for changing a charge amount of the capacity element to a plurality of values in response to the mutually different voltages required in the respective read modes. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is an overall construction diagram showing a flash memory as an embodiment of the invention; Fig. 2 is a circuit diagram showing an exemplary construction of an S/A circuit in Fig. 1; Fig. 3 is a graph showing a characteristic of the S/A circuit in Fig. 2; Fig. 4 is a construction diagram of a verify voltage supply circuit in Fig. 1; Fig. 5 is a circuit diagram showing another exemplary construction of the S/A circuit in Fig. 1; Fig. 6 is a graph showing an ideal sensing characteristic; Fig. 7 is a circuit diagram showing an exemplary construction of the S/A circuit in order to realize the characteristic shown in Fig. 6; Fig. 8 is a diagram showing a cell structure for explaining an operation of the flash memory; Fig. 9 is a circuit diagram showing a construction of the S/A circuit as an example of the prior art; Fig. 10 is a circuit diagram showing an exemplary voltage reducing circuit in a prior art semiconductor device; Fig. 11 is a diagram showing an operation characteristic of the circuit shown in Fig. 10; Fig. 12 is a circuit diagram showing an exemplary address input circuit in a prior art semiconductor device; Fig. 13 is a circuit diagram showing an exemplary data output circuit in a prior art semiconductor deice; Fig. 14 is a circuit diagram showing another exemplary data output circuit in a prior art semiconductor device; Fig. 15 is a circuit diagram showing an exemplary voltage reducing circuit for use in a semiconductor device embodying the invention; Fig. 16 is a circuit diagram showing another voltage reducing circuit for use in a semiconductor device embodying the invention; Fig. 17 is a circuit diagram showing an exemplary input circuit of the semiconductor device to which the circuit shown in Fig. 15 or 16 is applied; Fig. 18 is a circuit diagram showing an exemplary output circuit of the semiconductor device to which the circuit shown in Fig. 15 or 16 is applied; Fig. 19 is a block diagram showing a schematic construction of a semiconductor memory to which the circuit shown in Fig. 16 is applied; Fig. 20 is a circuit diagram showing an exemplary construction of a nonvolatile memory cell writing/erasing circuit in a voltage reducing circuit in Fig. 19; Fig. 21 is a circuit diagram of a first specific example of a supply voltage switching unit for use in a nonvolatile semiconductor memory embodying the invention; Figs. 22(A), 22(B), and 22(C) are circuit diagrams of a second specific example of a supply voltage switching unit for use in a nonvolatile semiconductor memory embodying the invention, Fig. 22(A) being a general circuit diagram, Fig. 22(B) being a circuit diagram specifically of a verify voltage generating circuit, and Fig. 22(C) being a voltage waveform chart; Fig. 23 is a circuit diagram of a third specific example of a supply voltage switching unit for use in a nonvolatile semiconductor memory embodying the invention; Fig. 24 is a circuit diagram showing a sense amplifier for use in nonvolatile semiconductor memory embodying the invention; Fig. 25 is a chart showing a characteristic of a memory cell; Fig. 26 is a block diagram of an EPROM; Fig. 27 is a circuit diagram of a prior art decoder; Fig. 28 is a block diagram showing a construction of a specific example of a supply voltage generating circuit for use in a semiconductor memory embodying the invention; Fig. 29 is a block diagram showing a detailed construction of the Figure 28 specific example of the supply voltage generating circuit; Fig. 30 is a timing chart relating to the supply voltage generating circuit shown in Fig. 29; Fig. 31 is a block diagram showing a detailed construction of another specific example of a supply voltage generating circuit for use in a semiconductor memory embodying the invention; Fig. 32 is a timing chart relating to the supply voltage generating circuit shown in Fig. 31; Fig. 33 is a block diagram showing a detailed construction of still another specific example of a supply voltage generating circuit for use in a semiconductor memory embodying the invention; Fig. 34 is a timing chart relating to the supply voltage generating circuit shown in Fig. 33; Fig. 35 is a block diagram showing a detailed construction of a further specific example of a supply voltage generating circuit for use in a semiconductor memory embodying the invention; Fig. 36 is a block diagram showing a schematic construction of the semiconductor memory using such a supply voltage generating circuit; Fig. 37 is a block diagram showing an example of construction of a prior art semiconductor memory; Fig. 38 is a block diagram showing a detailed construction of a semiconductor memory using the supply voltage generating circuit of one of the above specific examples of Figures 28 to 35; Fig. 39 is a diagram showing an example of the construction of a prior art charging circuit; Fig. 40 is a diagram showing another example of the construction of a prior art charging circuit; Fig. 41 is a diagram showing still another example of the construction of a prior art charging circuit; Fig. 42 is a diagram showing a further example of the construction of a prior art charging circuit; Fig. 43 is a block diagram showing an example of the construction of a reference voltage generating circuit which operates as a charging circuit in an embodiment of the invention; and Fig. 44 is a block diagram showing another example of the construction of a reference voltage generating circuit which operates as a charging circuit in an embodiment of the invention. Fig. 1, partially a block diagram, shows an overall construction of a flash type memory as a specific example of a nonvolatile semiconductor memory embodying the invention. In this figure, indicated at 1 is a cell array formed by arranging erasable nonvolatile memory cells M ij at intersections of a plurality of word lines WL l to WL m and a plurality of bit lines BL ll to BL lk , ..., BL nl to BL nk . In this embodiment, the cell array is divided into n blocks, in each of which (k × m) memory cells are arranged. Indicated at 2 is a row address buffer for buffering a row address RAD of an address signal fed externally thereto, at 3 a row decoder for decoding the row address and selecting any one of the word lines WL l to WL m , at 4 a column address buffer for buffering a column address CAD of the address signal, and at 5 a column decoder for decoding the column address and selecting any one of column lines CL l to CL k corresponding to the bit lines BLi l to BLi k for each of the aforementioned blocks. Indicated at 6 is a column gate circuit including transfer gate transistors Q l to Q k corresponding to the bit lines BL il , to BL ik for each of the aforementioned blocks. The respective transistors Q l to Q k are turned on when the corresponding column lines CL l to CL k are selected, to thereby connect the selected bit line BL ij to a data line D i . Indicated at 7 l to 7 n are respectively writing circuits and S/A circuits for applying amplification to a write data and sense amplification to a read data between corresponding internal data lines D l to D n and external input/output data lines I/O l to I/O n . Indicated at 8 is a verify source voltage generating circuit for generating a verify voltage V VER in accordance with a control signal C fed externally thereto. The generated verify source voltage V VER is supplied to the selected word lines WL l to WL m through the row decoder 3 as described later, and to the S/A circuit corresponding to the selected word line. Indicated at 9 is a source voltage supply circuit for supplying a source voltage in common to the respective sources of the nonvolatile memory cells M ij . Fig. 2 shows an exemplary construction of the S/A circuit used in an embodiment of the present invention. The circuit illustrated in Figure 2 corresponds to a part of one of the writing circuits and S/A circuits 7 l to 7 n and a construction thereof is basically the same as the one of the conventional S/A circuits shown in Fig. 9, and accordingly no description is given of the construction. However, the Figure 2 construction differs from the one shown in Fig. 9 in that the verify voltage V VER is supplied to a source of a transistor 14 illustrated as a load resistance element 14 for discriminating the data stored in the memory cell. As will be described later, this verify voltage V VER is a variable voltage set such that it is at the same level as a supply voltage V CC during a normal reading operation but is at the same level as the potential of the word line during a verifying operation. When obtained mathematically, a sense voltage curve of the S/A circuit in this embodiment is as shown in Fig. 3. In this figure, a curve (1) indicated by solid line represents a sense characteristic curve when V CC is changed in a state where the verify source voltage is set equal to the normal supply voltage (V VER = V CC ); and a curve (2) indicated by broken line represents a sense characteristic curve when the verify source voltage V VER is changed in a state when V CC is held at 5V. Further, a curve (3) represents a cell current characteristic curve after the data is written; and a curve (4) represents the cell current characteristic curve after the data is erased. Indicated at V W is a write verify source voltage, and at V E is an erase verify source voltage. The data is discriminated to be "1" when a larger amount of current flows through the cell, and is discriminated to be "0" when a smaller amount of current flows through the cell, compared to the current indicated by the sense characteristic curves (1), (2). It can be seen from the characteristic curves shown in Fig. 3 that the sensitivity of the S/A circuit is practically the same in both cases where only the verify voltage V VER is changed and where V CC is changed in the state where V VER = V CC . In view of this, one typical method for checking the verification has been carried out by applying the verify source voltage to the selected word line, while the verify source voltage is applied uniformly to all components provided in the circuitry (to which components the normal source voltage V CC is supplied at other times). On the other hand, the Figure 2 embodiment provides another method for checking the verification which is carried out by applying the verify source voltage to the selected word line and this voltage is also applied only to a transistor used for comparing with a voltage level of the sense amplifier used in the reading operation, while the normal source voltage V CC is applied to any other components provided in the circuitry as in the normal reading operation. As is apparent from Fig. 3, these two methods do not differ significantly from one another in terms of the discriminating level of the sensitivity of the sense amplifier. Accordingly, the verification can still be carried out at a specified operating power supply margin in a memory embodying the present invention. Since the verify voltage circuit 8 supplies the voltage only to the transistor 14, this embodiment is advantageous in terms of a supply ability of the verify voltage circuit. In other words, the size of a transistor contributing to supply the current, provided in the circuit, can be prevented from being increased by avoiding waste. Fig. 4 shows an exemplary construction of the verify voltage circuit 8. The circuit illustrated in Fig. 4 includes resistors 31 to 33 connected in series between a write/erase voltage line V PP and a power supply line V SS , an n-channel transistor 34 having a source thereof connected to a connection node between the resistors 31, 32 and responsive to a write verify signal WV, an n-channel transistor 35 having a source thereof connected to a connection node between the resistors 32, 33 and responsive to an erase verify signal EV, an n-channel transistor 36 whose source is connected to the respective drains of the transistors 34, 35 and whose gate is connected to its own drain, a p-channel transistor 37 whose source is connected to the respective drains of the transistors 34, 35 and whose gate is connected to its own drain, a current supply 38 connected between the voltage line V PP and the drain of the transistor 36, a current supply 39 connected between the drain of the transistor 37 and the power supply line V SS , an n-channel transistor 40 and a p-channel transistor 41 connected in series between the voltage line V PP and the power supply line V SS and having gates connected respectively to the gates of the transistors 36, 37. The verify voltage V VER is taken from the sources of the respective transistors 40, 41. In this construction, the resistors 31 to 33 divide the write/erase voltage V PP (12V). In this embodiment, resistance values of the respective resistors are set so that the potential at the connection node between the resistors 31, 32 is 6.5V (maximum voltage for the write verification) and the potential at the connection node between the resistors 32, 33 is 3.5V (minimum voltage for the erase verification). Further, the transistors 36, 37, 40, 41 and the current supplies 38, 39 constitute a form of current mirror circuit, which functions so that an output voltage (verify voltage V VER ) becomes equal to the potential at the connection node between the transistors 36, 37. It is desirable to set the erase verify source voltage V E lower than the normal source voltage (V CC ) and to set the write verify source voltage V W higher than the normal source voltage (V CC ). Preferably, the normal supply voltage (V CC ) is an intermediate value between a first verify voltage which is the erase verify voltage and a second verify voltage which is the write verify voltage. In this case, the desirable range of the write verify source voltage V W and the erase verify source voltage V E can be determined with reference to the graphs as shown in Fig. 3. Note that when the erase verify source voltage V E is selectively set at the voltage level close to or exactly at the crossing point formed by the characteristic curve of the sense amplifier ((1) or (2)) and the cell current characterisitic curve (after data is erased ) (4), and the write verify source voltage V W is selectively set at the voltage level close to or exactly at the crossing point formed by the characteristic curve of the sense amplifier ((1) or (2)) and the cell current characteristic curve (after data is written) (3), the accurate discrimination for the verification can be obtained. Accordingly, if the write verify signal WV is set at "H" level during the write verification, the transistor 34 is turned on. Thus, the potential at the node of the resistors 31, 32, i.e., the voltage of 6.5V, is applied to the connection node between the transistors 36, 37, and the verify voltage V VER of 6.5V can be obtained by a current mirror action. On the other hand, if the erase verify signal EV is set at "H" level during the erase verification, the transistor 35 is turned on. Thus, the potential at the node of the resistors 32, 33, i.e., the voltage of 3.5V, is applied to the connection node between the transistors 36, 37 and the verify voltage V VER of 3.5V can be obtained by the current mirror action. If the write verify signal WV and the erase verify signal EV are both set at "H" level during the normal reading operation, the transistors 34, 35 are cut off. As a result, only the current mirror circuit operates and an intermediate level (5V) between 6.5V and 3.5V is output as the output voltage V VER . This output voltage is at the same level as the normal supply voltage V CC . Since an output signal of the S/A circuit is normally a weak signal in terms of the amplitude and drive ability, it is preferable to provide a buffer circuit for the purpose of stabilizing the output signal. In the case of the flash type memory, in which the voltage is changed from the bit line potential (about 1V) to the verify voltage V VER during the verification, it is preferable to supply the verify voltage V VER as a source voltage of the buffer circuit. Fig. 5 shows an exemplary construction of the S/A circuit including a buffer circuit. The illustrated circuit is obtainable by adding the buffer circuit to the construction of Fig. 2. This buffer circuit includes a p-channel transistor 16 and n-channel transistors 17, 18 which are connected in series between the verify source voltage line V VER and the power supply line V SS and are responsive to the drain potentials of the respective transistors 14, 15, and a p-channel transistor 19 which is connected between the voltage line V VER and a connection node between the transistors 17, 18 and is responsive to the drain potentials of the respective transistors 14, 15. In this case, the output of the S/A circuit (data output) is taken from the drains of the respective transistors 16, 17. In consideration of the operation of the flash type memory, the sense characteristic curves shown in Fig. 3 are ideally required to be devised. For example, the inclination of the sense characteristic curve is preferably large in the neighborhood of the write verify source voltage V W so that a large power supply margin is taken for a change of a threshold voltage of the cell transistor. Conversely, the inclination of the sense characteristic curve is preferably small in the neighborhood of the erase verify source voltage V E so as to make it easier to adjust the voltage V E finely and in order to improve the stability of the characteristic in terms of differences among cell transistors. Fig. 6 shows ideal sense characteristic curves, and Fig. 7 shows an exemplary construction of a preferable S/A circuit for realizing this characteristic. The illustrated circuit is obtainable by adding two transistors 20 and 21 to the construction of the S/A circuit including the buffer circuit shown in Fig. 5. The transistor 20 is a p-channel transistor, and is connected between the verify source voltage V VER and the source of the transistor 14. A gate of the transistor 20 is connected to a drain thereof. Accordingly, this transistor 20 functions as a voltage reducing element. On the other hand, the transistor 21 is an n-channel transistor of the depletion type, and is connected between the voltage V VER and the commonly-connected drains of the transistors 14,15. A gate of the transistor 21 is connected to a source thereof. Accordingly, this transistor 21 functions as a constant current supplying element. In this construction, when the verify source voltage V VER is at low level, the drain potential of the voltage reducing transistor 20 is reduced accordingly. Thus, the transistor 14 is cut off and only the transistor 21 for the constant current load is turned on. In other words, there is realized a steeply inclined portion of the sense characteristic in the neighborhood of the erase verify source voltage V E shown in Fig. 6. On the contrary, when the verify source voltage V VER is at a relatively high level, the drain potential of the transistor 20 increases accordingly, and the transistor 14 is turned on. In other words, the transistors 21, 14 are both turned on, thereby realizing a gently inclined portion of the sense characteristic curve in the neighbourhood of the write verify voltage V W shown in Fig. 6. As described above, in a memory embodying the present invention, the portion of the overall memory circuit to which the verify source voltage should be applied, may be confined just to the selected word line and the transistor used for comparing with a voltage level provided in the sense amplifier. Note, that in accordance with the present invention, the number of the portions to which the verify source voltage should be applied in the verify operation can be significantly reduced as compared with the conventional method in which the source voltage V CC applied to each of the components provided in the memory circuit is simply and uniformly converted to the verify source voltage. Accordingly, in the present invention, the number of the circuit elements to which the source voltage should be applied is remarkably small, thereby making it possible to reduce the performance required of the verify source voltage generating circuit used for supplying the verify source voltage. Accordingly, this generating circuit can be made significantly smaller than the comparable generating circuit required by the conventional method and thus the area to be occupied by the verify source voltage generating circuit can be significantly reduced whilst still maintaining suitable sensitivity in the verifying operation. In the flash-type memory according to the present invention, a plurality of different power-supply voltages are used at different places, and many of them are supplied from external power supplies. A single external power supply should preferably be used to produce a plurality of different power-supply voltages within the flash-type memory embodying the present invention. Heretofore, however, there have been many problems with such internal power-supply voltage generation circuits, and it has been difficult to obtain an ideal internal power-supply voltage generation circuit. Recently, because of the larger-scale integration of semiconductor devices, down-sizing and lower power consumption are required. It is also required that the power-supply voltage be lower (for example, a voltage of 5V is currently prevailing, but a reduction to 3.0 or 3.3V is required). On the other hand, use of conventional semiconductor devices and other parts together with such recent semiconductor devices integrated in a larger scale is unavoidable. Therefore, it is required that the operation of an apparatus using both a low voltage and an ordinary power-supply voltage be ensured. In conventional technology, existing semiconductor devices are used with a low voltage without special consideration afforded them. Therefore, since transistors used to build a semiconductor device are not sufficiently adapted for use with a low voltage (for example, thinning of a gate oxide film, shortening of channel length, etc.), the characteristics of the transistors are degraded significantly when the semiconductor device is operated using a low voltage. Thus, in the conventional semiconductor device, an external power-supply voltage (normally, 5V) is dropped to a suitable low voltage within the device (namely, the power-supply voltage is simply dropped). Namely, the transistors are adapted to the reduced voltage so as to maintain characteristics thereof. However, conventional semiconductor devices in which an external reduced power-supply voltage is used incur the following problems (1) Problems with the voltage dropping circuit itself, (2) Problems with the input-stage circuit and (3) Problems with the output-stage circuit. (1) Problems with the voltage dropping circuit Fig. 10 shows an example voltage dropping circuit used in the conventional semiconductor device, and Fig. 11 shows its operational characteristic waveform. In Fig.10, Vcc indicates an external power-supply voltage (power line), Vss a reference power-supply voltage (power line) of the semiconductor device, and Vci an internally dropped voltage. The circuit illustrated in Fig. 10 comprises a constant-current source IS connected to the power line Vcc, n-channel transistors QT1 to QTn connected in series between the output terminal of the constant-current source IS and the power line Vss and each of which has a gate connected to the drain thereof, and an n-channel transistor Q30 connected between the power line Vcc and the internal-voltage (Vci) delivery node and which responds to a signal at the drain terminal of the transistor QT1. As shown in the operational characteristic waveform in Fig. 11, the internal voltage Vci is stabilized at the level of V2 when the external voltage Vcc is higher than the level of V1, thus advantageously, an ideal voltage drop is obtainable. On the other hand, however, since the gate potential (reference voltage) of the transistor Q30 for conversion of the external voltage Vcc to the dropped voltage Vci is determined based on the voltage drop (threshold level) of each of the transistors QT1 to QTn, a problem will occur when the ambient temperature changes, the power-supply voltage varies or the like. Namely, the voltage drop of each of the transistors QT1 to QTn varies and the gate potential of the transistor Q30 also varies correspondingly, so that the operation of the transistor Q30 loses stability, thereby resulting in unstable delivery of the lowered voltage Vci. Also since the constant-current source IS is used to generate a voltage drop in each of the transistors QT1 to QTn,some current is always consumed, which is a significant disadvantage. (2) Problems with the input-stage circuit Fig. 12 shows an example address input circuit used in the conventional semiconductor device. The circuit shown in Fig. 12 comprises a p-channel transistor Q31 driven by a dropped voltage Vci produced in, for example, the voltage dropping circuit shown in Fig. 10. The p-channel transistor Q31 is connected at the source thereof to the potential Vss. A CMOS inverter (composed of a p-channel transistor Q32 and n-channel transistor Q33) is connected between the drain of the transistor Q31 and the power line Vss and responds to the address input signal; an n-channel transistor Q34 is connected parallel to the transistor Q33 and receives at its gate the potential Vss; and a CMOS inverter (composed of a p-channel transistor Q35 and n-channel transistor Q36) is connected between the power lines Vci and Vss and responds to the output from the inverter (Q32 and Q33). Since the input threshold level of the input circuit is lower because this circuit is driven by the internally dropped voltage Vci, the circuit is susceptible to noise compared to the case when driven by an ordinary power-supply voltage Vcc higher than the voltage Vci. For example, the transistor will possibly malfunction as a result of an internally developed noise. Also, when the amplitude of the address input signal changes to the levels of the voltages Vcc to Vss, the noise component (coupling noise) caused by the capacitive coupling with the external signal line and will be larger. (3) Problems with the output-stage circuit Fig. 13 shows an example data output circuit used in the conventional semiconductor device. Similar to the circuit shown in Fig. 12, this circuit comprises a CMOS inverter (composed of a p-channel transistor Q37 and an n-channel transistor Q38) driven by the dropped voltage Vci produced in, for example, the voltage dropping circuit shown in Fig. 10. The inverter is connected between the dropped voltage line Vci and the power line Vss and responds to the data signal from the internal circuit. Since this circuit is driven by the internally dropped voltage Vci, when the data signal from the internal circuit changes in amplitude to the levels of the voltages Vci to Vss, the output signal also changes correspondingly with the amplitude at the levels of the voltages Vci to Vss. Thus, if a circuit connected to the output stage of this data output circuit is driven by an ordinary power-supply voltage (5V), matching with elements used in that circuit will be poor. A signal at a predetermined logical level may not be transmitted stably, as the case may be. Fig. 14 shows another example data output circuit in the conventional semiconductor device. This circuit comprises a CMOS inverter (composed of a p-channel transistor Q39 and an n-channel transistor Q40) driven by the external power-supply voltage Vcc . The inverter in this case is connected between the power lines vcc and Vss and which responds to the data signal from the internal circuit. Since it is driven with the power-supply voltage Vcc, this circuit has no problem in matching with external elements that are driven with the same voltage (5V). When the input is at the level of Vss in the case that the data signal from the internal circuit changes in amplitude to the levels of the voltages Vci to Vss, only the p-channel transistor Q39 is turned on while the n-channel transistor Q40 is cut off, thus causing no problem. But if the input is at the level of Vci, the p-channel transistor Q39 is turned on as well, depending on the difference in level between the power-supply voltage Vcc and the internally dropped voltage Vci. In this case, a problem will occur in that a through current flows from the power line Vcc to the power line Vss through the transistors Q39 and Q40. Accordingly, to solve the aforementioned problems of the internal power-supply voltage generation circuit used primarily in such a flash-type memory, it is preferable to provide an internal power-supply voltage generation circuit that consumes less power and can supply a low voltage by stably dropping an external power-supply voltage. Furthermore, it is preferable to provide an internal power-supply voltage generation circuit for use in a flash-type memory that can maintain a good matching with various elements including external elements even in the case that an external voltage and an internally dropped voltage are used together, and which contributes to the improvement of operational reliability by eliminating the influence of noise. Moreover, the internal power-supply voltage generation circuit should also have a simple configuration, should not develop therein such through currents as in the conventional voltage dropping circuit, and should be very suitable for building an internal power-supply voltage generation circuit in which the CMOS configuration is adopted. In a preferred embodiment of the present invention, the basic technical concept is to adjust the threshold of the main transistors composing the internal power-supply source voltage generation circuit while both the external power-supply voltage and reference voltage are kept at a stable fixed level to generate a dropped voltage at a predetermined level. Therefore, in this preferred embodiment the internal power-supply voltage generation circuit incorporates a circuit that drops an external power-supply voltage and the performance of which can be ensured with a wide range of power-supply voltages. The internal power-supply voltage generation circuit in the preferred embodiment of the present invention comprises, to solve the aforementioned problems, a means of dropping an external power-supply voltage to a predetermined internal voltage. This voltage dropping means is characterized in that a transistor is connected between the power-supply voltage line and the node at which the internal voltage is developed and that a reference voltage at a predetermined level is applied to the gate of the transistor so as to deliver the internally dropped voltage at the internal-voltage delivery node. Particularly, the flash-type memory according to a preferred embodiment of the present invention comprises a cell matrix circuit (1) having disposed therein reloadable nonvolatile memory cells (Mij) at the intersections of a plurality of word lines WL1 to WLm and a plurality of bit lines BLll to BLlk, ..., BLnl to BLnk, a row decoder circuit 3, a column decoder 5, sense amplifier circuits 71 to 7n connected to the bit lines BLll to BLlk, ..., BLnl to BLnk of the cell matrix circuit (1), and an internal power-source voltage generation circuit connected to at least an external power supply and in which an external power-supply voltage Vcc is used to produce different kinds of internal voltages. The internal power-supply voltage generation circuit comprises a means of dropping an external power-supply voltage Vcc to a predetermined internal voltage Vci. This voltage dropping means has a transistor Q connected between the external power-supply voltage line and the node N at which the internal voltage is delivered. A reference voltage at a predetermined level is applied to the gate of the transistor Q to deliver the internally dropped voltage at the internal-voltage delivery node. The transistor Q should preferably be a depletion-type n-channel transistor. Further, a smoothing capacitor C may be provided in the internal-voltage delivery node in the internal power-source voltage generation circuit, whereby the internal source voltage resulting from noise or the like can be prevented from fluctuating. Moreover in this embodiment, the voltage dropping level can be adjusted by changing the threshold of the aforementioned transistor Q. Also in this embodiment, the fixed reference voltage applied to the gate of the transistor Q should preferably be a single voltage supplied from the reference power line Vss of the semiconductor device. Furthermore, the reference voltage at the predetermined level applied to the gate of the transistor Q may be supplied to the reference power line of the semiconductor device, whereby only the dropped voltage is delivered at the internal-voltage delivery node. Otherwise, nonvolatile memory elements may be used and the reference voltage at the predetermined level applied to the gate of the transistor Q should be set to either the level of the external power-source voltage or that of the reference power-source voltage of the semiconductor device, whereby a dropped voltage or an ordinary power-source voltage is selectively delivered at the internal-voltage delivery node. In the aforementioned circuit configuration, since a transistor is used as the means of dropping an external power-supply voltage to a predetermined internal voltage and it is driven by applying the transistor at the gate thereof with a stable reference voltage at a predetermined level, power is not unnecessarily consumed as in the conventional circuit configuration, thereby providing a stable internally-dropped voltage. Also, a smoothing capacitor may be provided in the internal-voltage delivery node to further stabilize the level of the internally dropped voltage delivered at the node. Embodiments of the preferred internal power-supply voltage generation circuit will be described with reference to Figs. 15 to 20. Fig. 15 shows an example configuration of the voltage dropping circuit in the internal power-supply voltage generation circuit. In this embodiment, a depression-type n-channel transistor Q is used to convert an external power-supply voltage Vcc to an internal voltage dropped for the internal circuit. The transistor Q is connected at the gate thereof to the reference power line Vss (that is a stable reference voltage of 0 V (= ground potential) of the semiconductor device, at the drain thereof to a higher-potential power line (that is, external voltage Vcc), and at the source thereof to the internal-source voltage (Vci) delivery node N. The threshold level of this depletion-type transistor Q is selected to be Vth = -Vci. Also, a smoothing capacitor C is connected between the internal-voltage delivery node N and the lower-potential power line Vss. In the circuit configuration according to this embodiment, the transistor Q provided for converting a stable external power-source voltage Vcc to a dropped internal voltage Vci is connected at the gate thereof to the reference voltage line Vss, the potential of which is stable and does not fluctuate. Since there is no problem that a current is always supplied as in the circuit configuration shown in Fig. 10, a stable internally-dropped voltage Vci can be obtained. The threshold of the transistor used in the internal power-source voltage generation circuit embodying the present invention can be adjusted by changing, for example, the silicon oxide film thickness. Also, since a smoothing capacitor C is provided in the internal-voltage delivery node N, the level of the internally dropped voltage Vci delivered at the node N can be further stabilized. In this embodiment, only the internally dropped voltage Vci is delivered at the internal-voltage delivery node N. However, the ordinary power-supply source voltage Vcc can be easily delivered in place of the internal source voltage Vci. Fig. 16 shows an example of such a circuit. The circuit shown in Fig. 16 comprises a nonvolatile memory cell QM such as EPROM to determine whether the internally dropped voltage Vci or the external voltage Vcc is to be delivered. The nonvolatile memory cell QM is connected between the reference power line Vss and an internal-voltage delivery node P and has its control gate connected to the supply line of the external voltage Vcc. The nonvolatile memory cell QM supplies or does not supply a current according to its contents. Therefore, the potential at the internal-voltage delivery node P takes the L level when the memory cell QM supplies a current, and takes the H level when the memory cell does not supply a current. A p-channel transistor Q1 is connected between the power line Vcc having a high potential and the internal-voltage delivery node P. Also a CMOS inverter (composed of a p-channel transistor Q2 and an n-channel transistor Q3) is connected between the power line Vcc and the low voltage line Vss, and these transistors are connected at the respective gates thereof to the internal-voltage delivery node P and at the respective drains thereof to the gate of the p-channel transistor Q1. Similarly, there is connected between the power lines Vcc and Vss another CMOS inverter (composed of a p-channel transistor Q4 and an n-channel transistor Q5), the gates of which are connected to the output terminals of the inverter (Q2 and Q3) and the drains of which are connected to the gate of the transistor Q (Fig. 15). In particular, the gate of the transistor Q provided for conversion of the power-source voltage Vcc to an internal source voltage Vci (or Vcc) is so arranged as to receive a voltage determined in dependence upon the contents of the nonvolatile memory cell QM (namely, the H or L level developed at the internal-source voltage delivery node P) instead of receiving the fixed reference potential Vss as in the embodiment shown in Fig. 15. Therefore, when the nonvolatile memory cell QM supplies a current, the internal-source voltage delivery P takes the L level. Thus, the transistor Q is supplied at the gate thereof with an L-level signal through the two-stage inverter, and this transistor is cut off. A dropped internal source voltage vci is delivered at the internal-source voltage delivery node N. On the other hand, when the nonvolatile memory cell QM supplies no current, the internal-source voltage delivery node P takes the H level, so that the transistor Q is turned on and thus the external power-source voltage Vcc is delivered at the internal-source voltage delivery node N. Fig. 17 shows an example configuration of the input-stage circuit in a semiconductor device in which the aforementioned voltage dropping circuit is adopted. The input-stage circuit shown in Figure comprises circuitry driven by an external power-source voltage Vcc and circuitry driven by the dropped internal source voltage Vci, and it is so configured as to transmit an input signal Si (for example, an address signal in case of a semiconductor memory) to an internal circuit of which at least a part is driven by the internally dropped voltage Vci. The circuitry driven by the external power-source voltage Vcc comprises: a p-channel transistor Q11, connected at the source thereof to the power line Vcc, that responds to the potential Vss; a CMOS inverter (composed of a p-channel transistor Q12 and an n-channel transistor Q13), connected between the drain of the transistor Q11 and the power line Vss,that responds to the input signal Si; an n-channel transistor Q14, connected parallel to the transistor Q13,that responds to the potential Vss; and a CMOS inverter (composed of a p-channel transistor Q15 and an n-channel transistor Q16), connected between the power lines Vcc and Vss,that responds to the output from the inverter (Q12 and Q13). The transistors Q15 and Q16 function to stabilize the level of signals having amplitudes Vcc to Vss delivered from the circuit provided upstream thereof and transmit them to the circuit provided downstream thereof. On the other hand, the circuitry driven by the internally dropped voltage Vci comprises: a CMOS inverter (composed of a p-channel transistor Q17 and an n-channel transistor Q18),connected between the internally-dropped voltage line Vci and the power line Vss,that responds to the output from the inverter (Q15 and Q16); and a CMOS inverter (composed of a p-channel transistor Q19 and an n-channel transistor Q20), connected between the power lines Vci and Vss, that responds to the output from the inverter (Q17 and Q18). In the circuit configuration shown in Fig.17 , since the circuitry which directly receives the input signal Si is driven by the external power-supply voltage Vcc, the input threshold level can be set high compared to that in the conventional circuit configuration (shown in Fig. 12 ). Namely the circuitry is not susceptible to noise in an external input signal (that is, improvement in the noise margin of the circuit) and the possibility of a transistor malfunction can be eliminated. Note that in the first stage of the circuitry driven by internally dropped voltage Vci (consisting of the transistors Q17 and Q18), since the gate signals change between Vcc and Vss according to the logical level of the input signal Si,the gate withstand voltage of each transistor used in that circuitry is preferably selected so as to be relatively high. Also, in this connection, the drain or gate withstand voltage of each transistor used in the circuitry driven by the external power-supply voltage Vc should preferably be set high. Fig. 18 shows an example configuration of the output-stage circuit in a semiconductor device in which the aforementioned voltage dropping circuit is adopted. The output-stage circuit shown in the Figure comprises circuitry driven by the dropped internal voltage Vci and circuitry driven by the external power-supply voltage Vcc, and it is so configured as to deliver outside the circuit, as data output So, a data signal from an internal circuit (not shown) at least a part of which internal circuit is driven by the internally dropped voltage Vci. The circuitry driven by the internally dropped voltage Vci comprises a CMOS inverter (composed of a p-channel transistor Q21 and an n-channel transistor Q22), connected between the internally dropped voltage line Vci and the power line Vss, that responds to the above-mentioned data signal, and an n-channel transistor Q23 connected at the source thereof to the output terminal of the CMOS inverter and at the gate thereof to the internally dropped voltage line Vci. On the other hand, the circuitry driven by the external power-supply voltage Vcc comprises: a p-channel transistor Q24 connected between the drain of the transistor Q23 and the power line Vcc; a CMOS inverter (composed of a p-channel transistor Q25 and an n-channel transistor Q26), connected between the power lines Vcc and Vss, that responds to the signal at the drain terminal of the transistor Q24 and that provides an output signal applied to the gate of the p-channel transistor Q24; and a CMOS inverter (composed of a p-channel transistor Q27 and an n-channel transistor Q28), also connected between the power lines Vcc and Vss, that is operative in response to the output signal from the inverter (Q25 and Q26) to produce a data output So. In the circuit configuration shown in Fig. 18, the data signal from an internal circuit is converted to the level of the external power-supply voltage Vcc by means of the level converting means (transistors Q23 and Q24) and delivered outside the circuit as a data output So having amplitudes of the voltage Vcc to Vss. Therefore, in the case that the external circuit connected to this output-stage circuit is driven by an ordinary power-supply voltage (5V), matching with the elements used in this external circuit can be maintained. Namely, a stable predetermined logical-level signal can be transmitted. Also in the case that the data signal from the internal circuit changes with the amplitudes of the voltages Vci to Vss, the above-mentioned level converting means works in such a manner that the transistors Q25 and Q26 are supplied at the gates thereof with signals having amplitudes of the voltages Vcc to Vss. Thus both transistors are not turned on together, so that a through current will not flow from the power line Vcc to the power line vss through these transistors. Similar to the circuit configuration shown in Fig.17 , it should be noted here that the drain or gate withstand voltage of each transistor used in the circuitry driven by the external power-source voltage Vcc should preferably be relatively high. Fig. 19 shows the configuration of a semiconductor device in which the circuit shown in Fig.16 is adopted. In Figure, the reference numeral 410 denotes a voltage dropping circuit comprising a data write/erase circuit (see Fig.20 ) of the nonvolatile memory cell and the voltage dropping circuit shown in Fig.16. The voltage dropping circuit 410 works with the normal source voltage Vcc and a high voltage Vpp for data write/erase with respect to the nonvolatile memory cell. The reference numeral 420 denotes circuitry comprising an address buffer, a decoder, a memory cell and a sense amplifier, and this circuitry works with an internally dropped voltage developed at the output terminal (node N) of the voltage dropping circuit 410. In addition, the reference numeral 430 denotes a first-stage address buffer which, upon receiving the power-source voltage Vcc, buffers and address input, and 440 an output buffer which, also upon receiving the power-source voltage Vcc, delivers a data output. Fig. 20 shows an example configuration of the data write/erase circuit of the nonvolatile memory cell in the voltage dropping circuit 410. In the Figure, the circuit for controlling the write operation to the nonvolatile memory cell QM comprises a p-channel transistor Q41 connected at the source thereof to a pad P1 and at the gate to the drain thereof, a CMOS inverter (composed of a p-channel transistor Q42 and an n-channel transistor Q43) connected between the drain of the transistor Q41 and the power line Vss that responds to the power-supply voltage Vcc, and a CMOS inverter (composed of a p-channel transistor Q44 and an n-channel transistor Q45) connected between the power lines Vcc and Vss that is operative in response to the output from the inverter (Q42 and Q43) so as to generate a write signal WX. Similarly, the circuit for controlling the erase operation of the nonvolatile memory cell comprises a p-channel transistor Q46 connected at the source thereof to a pad P2 and at the gate to the drain thereof, a CMOS inverter (composed of a p-channel transistor Q47 and an n-channel transistor Q48) connected to the drain of the transistor Q46 and the power line Vss that responds to the power-supply voltage Vcc, and a CMOS inverter (composed of a p-channel transistor Q49 and an n-channel transistor Q50) connected between the power lines Vcc and Vss that is operative in response to the output from the inverter (Q47 and Q48) so as to produce an erase signal EX. The data write/erase circuitry of the nonvolatile memory cell QM comprises an n-channel transistor Q51 connected at the drain thereof to the power line Vcc that responds to the write signal WX, an n-channel transistor Q52 connected at the drain thereof to the high voltage power line Vpp that responds to the potential at a node 3, an n-channel transistor Q53 connected at the drain thereof to the source of each of the transistors Q51 and Q52 and at the gate to the source thereof node 1), an n-channel transistor Q54 connected between the node 1 and the power line Vss that responds to the potential at a node 4, an n-channel transistor Q55 connected between the output terminal of erase signal EX and node 5 that responds to the power-supply voltage Vcc, a p-channel transistor Q56 connected between the high voltage power line Vpp and the node 5 that responds to the potential at the node 4, an inverter IV1 connected in the forward direction between the nodes 5 and 4, a p-channel transistor Q57 connected between the high voltage power line Vpp and the node 2 that responds to the potential at the node 3, an inverter IV2 connected in the forward direction between the nodes 2 and 3, an n-channel transistor Q58 connected between the node 2 and the output terminal of write signal WX that responds to the power-source voltage Vcc, an n-channel transistor Q59 connected at the drain thereof to the high voltage power line Vpp that responds to the potential at the node 3, a nonvolatile memory cell QM connected between the source of the transistor Q59 and the node 4 that responds to the potential at the node 1, and an n-channel transistor Q60 connected between the source of the transistor Q59 and the internal-voltage delivery node P that responds to the power-source voltage Vcc. The data write/erase circuit shown in Fig. 20 functions as explained below: (1) When the write signal WX is at L level and the erase signal EX is at H level: Since the transistor Q51 is off while the transistor Q58 is on in this case, the node 2 takes the L level and the node 3 takes the H level through the inverter IV2 so that the transistor Q52 is on. Thus, the nonvolatile memory cell QM is applied at the control gate thereof with the potential (nearly at the level of Vpp) at the node 1. Also because the node 3 takes the H level, the transistor Q59 is turned on and the nonvolatile memory cell QM is applied at the drain thereof with a signal of nearly Vpp level. On the other hand, since the erase signal EX is at the H level, the node 5 takes the H level through the transistor Q55. Thus the node 4 takes the L level through the inverter IV1 so that the source of the nonvolatile memory cell transistor QM takes the L level. Thus, electrons are injected into the floating gate of the transistor QM and data is written into the memory cell transistor QM with the result that the transistor QM is turned off. The potential at the internal-voltage delivery node P takes the H level. In this case, the external power-supply voltage Vcc is delivered at the internal-voltage delivery node N as seen from Fig. 16. (2) When the write signal WX is at H level and the erase signal EX is at L level: Since the transistor Q51 is on while the transistor Q58 is off, the node 2 takes the H level, so that the node 3 takes the L level. Thus the transistor Q59 is off. On the other hand, the erase signal EX takes the L level, so the node 5 takes the L level. Therefore, the node 4 takes the H level and the transistor Q54 is turned on. Therefore, the node 1 takes the L level. The nonvolatile memory cell QM is applied at the control gate thereof with a signal at the L level (nearly at the level of Vss). Since the node 3 is at the L Level at this time, electrons are evacuated from the floating gate of the transistor QM, namely, data are erased with the result that the transistor QM is turned on. The potential at the internal-voltage delivery node P takes the L level. As seen from Fig. 16, a dropped internal voltage Vci is delivered at the internal-voltage delivery node N in this case. In the aforementioned circuit configuration, when the pads P1 and P2 are applied with a power-source voltage Vcc + Vth (where Vth is the threshold level of the p-channel transistors Q41 and Q46), both the write signal WX and the erase signal EX take the L level. As described in the foregoing, the Figures 15 to 20 embodiments of of the present invention can permit a reduction in power consumption and stably supply an internally dropped voltage in a semiconductor device in which a circuit to drop an external power-source voltage is incorporated. Even in the case that an external voltage and an internally dropped voltage are used together, matching with elements including external ones can be maintained, and the influence of noise can be eliminated thereby improving the operational reliability of the semiconductor device significantly. In the foregoing, the configurations of the internal power-supply voltage generation circuit used in a flash-type memory embodying the present invention have been described. During the operation of such a flash-type memory, it is necessary in some cases to simply drop an external power-supply voltage as well as raise a predetermined voltage to a predetermined level. However, since the conventional internal power-source voltage generation circuit has. no booster circuit, it was formerly necessary to provide a discrimination circuit. Fig. 26 is a block diagram of an EPROM used in the conventional flash-type memory. As seen, the EPROM comprises a memory cell array MCA disposed in a matrix, a column address buffer CAB, a column decoder CD, a row address buffer RAB, a row decoder RD, a write circuit WC, a sense amplifier SA and an input/output data buffer IOB. Based on an address input, the row decoder RD selects the word line WL, and the column decoder CD selects the bit line BL, thus selecting a single memory cell with respect to which write or read data is put through the input/output buffer IOB. Fig. 27 is a circuit diagram of the decoder. For a data write, the write control signal W# (# means that the signal in consideration is a negative-logic signal) takes the L level, and the power-supply voltage Vpp is applied to the word line WL. For a data read, the write control signal W# takes the H level and the power-supply voltage is applied to the word line WL. Further, for verification the write control signal W# remains at the H level and verification is completed with the power-supply voltage Vcc raised above the ordinary read voltage. These days, it is required that the ordinary read voltage be changed from 5V to 3V to reduce power consumption, which is also true for the EPROM. In this case, a shift to the lower voltage will necessarily lower the access speed. Therefore, the transistor must be optimally adapted for use with a voltage of 3V. A write operation to the EPROM is effected with a specially designed writer, and when a conventional writer is used for such a write, the power source-voltage Vcc will be 5 or 6V. Therefore, it is necessary to use the voltage dropping circuit shown in Figs. 10 and 11 in order to inhibit the power-source voltage Vcc (Vci) to the internal circuit from rising above a predetermined value. In this case, verification of the type referred to above is impossible since the power-source voltage Vci to the internal circuit is inhibited by the voltage dropping circuit from rising above the predetermined value. For the conventional flash-type memory, it is necessary to change the read voltage to a lower voltage in order to minimize power consumption as described in the foregoing. If the conventional write operation is used for a data write to the memory, the power-source voltage to the internal circuit should be prohibited by the voltage dropping circuit from rising above a predetermined value. However, verification in the conventional manner cannot be done in this case. Accordingly, preferred embodiments of the present invention seek to solve the above problems by providing a flash-type memory in which the read voltage is changed to a lower voltage to minimize power consumption and that can effect the verification and provide a stable device operation even when operated with a voltage produced by internally dropping the power-source voltage. For overcoming the drawbacks of the conventional technique, a first embodiment shown in Fig. 21 relates to an internal power-source voltage generation circuit adapted so as to receive an external power-source voltage vcc for a data read and an external power-source voltage vpp for a data write, and which comprises a means of operating the read circuit in the flash-type memory by dropping the read external power-source voltage Vcc to a predetermined value and a means of producing a word-line potential for post-write verification by dropping the write external power-source voltage Vpp. A second embodiment shown in Fig. 22 provides an internal power-source voltage generation circuit adapted to receive a read external power-source voltage Vcc and a write external power-source voltage Vpp that comprises a means of operating the read circuit inside the flash-type memory by dropping the read external power-source voltage Vcc to a predetermined value and a means of producing a word-line potential for post-write verification by internally generating a voltage higher than a voltage obtained by dropping the read external power-source voltage Vcc. Fig. 23 shows a third embodiment of the preferred internal power-supply voltage generation circuit, which is adapted to receive a read external power-source voltage Vcc and a write external power-source voltage Vpp, and comprises a means of operating the read circuit in the flash-type memory by dropping the read external power-source voltage Vcc to a predetermined value and a means of inhibiting the read external power-source voltage Vcc from being dropped at the time of post-write verification. In a fourth embodiment of the internal power-source voltage generation circuit, as shown in Fig. 24, the internal power-source voltage generation circuitis adapted to receive a read external power-source voltage Vcc and a write external power-source voltage Vpp, and comprises a means of operating the read circuit inside the flash-type memory by dropping the read external power-source voltage Vcc to a predetermined value and a means of normally making the sense current of a sense amplifier smaller than the read sense current. More particularly, the first embodiment has a power-source voltage selector comprising, as shown in Fig. 21, a Vpp detection circuit 501 that detects whether or not the write external power-source voltage Vpp is supplied, and a selection circuit 503 that supplies a word-line potential. This power-source voltage selector is so arranged that when the write external power-source voltage Vpp is supplied, the voltage Vci (power to the internal circuit) provided by dropping the read external power-source voltage Vcc to a predetermined value is disconnected and for verification, the write external power-source voltage Vpp is dropped to provide a word-line potential for post-write verification. Therefore, in the flash-type memory in which the read voltage is changed to a lower voltage for reduced power consumption, verification can be effected and a stable device operation can be ensured even when the semiconductor device is operated with a voltage obtained by internally dropping the power-source voltage. In the second embodiment, the power-source voltage selector comprises, as shown in Fig. 22, a Vpp detection circuit 501 that determines whether or not the write external power-source voltage Vpp is supplied, and a selection circuit 503' that supplies a word-line potential. It is so arranged that when the write external power-source voltage Vpp is supplied, the voltage Vci (power to the internal circuit) derived from dropping the read external power-source voltage Vcc to a predetermined value is supplied as a word-line potential, whereas for the post-write verification, a voltage obtained by raising the voltage produced by dropping the read external power-source voltage Vcc is supplied as the word-line potential. Thus, good verification can be implemented. The power-source voltage selector in the third embodiment comprises, as shown in Fig. 23, a voltage dropping circuit provided for the read circuit in the flash-type memory that drops the read external power-source voltage Vcc to a predetermined voltage, and a means of inhibiting the voltage supply produced by dropping the read external power-source voltage Vcc under control of the Vpp detection circuit 501, which detects whether or not the write external power-source voltage Vpp is supplied, whereby the read external power-source voltage Vcc is used as it is for the word-line potential for post-write verification. Thus, a good verification can be effected. In the fourth embodiment, the sense current of the sense amplifier is made smaller than that for the ordinary read for verification, as shown in Fig. 24, so that a stable operation on the power-source voltage Vci to the internal circuit can be ensured and a good verification can be effected. Next, each of the aforementioned embodiments will be described with reference to the drawings. Fig. 21 is a circuit diagram of the power-source voltage selector in the flash-type memory according to the first embodiment. The general configuration of the flash-type memory according to this embodiment is the same as that shown in the block diagram in Fig. 26 and additionally includes the power-supply voltage selector shown in Fig.21 and the voltage dropping circuit shown in Fig. 10. As shown in Fig. 21, the power-supply voltage selector in the flash-type memory according to this embodiment comprises a Vpp detection circuit 501 that determines whether or not the write external power-source voltage Vpp is supplied, and a selection circuit 503 that supplies the column decoder and the row decoder with the power-source voltage (word-line potential) after changing. The Vpp detection circuit 501 comprises p-channel MOS transistors Tpl, Tp2 and Tp3 and n-channel MOS transistors Tnl and Tn2, thereby changing the Vpp detection signal R to L level when the write external power-source voltage Vpp is supplied. For verification, the selection circuit 503 supplies, as a power-source voltage (word-line potential) to the column decoder and the row decoder, a voltage produced by dropping the write external power-source voltage Vpp. Namely, when the write external power-source voltage Vpp is supplied, the Vpp detection signal R takes the L level and the power-source voltage Vci (to the internal circuit) produced by dropping the reads external power-source voltage Vcc by the voltage dropping circuit shown in Fig. 10 is disconnected by the n-channel MOS transistor Tn7. Then, when the write control signal W# is at the L level (for write), the n-channel MOS transistor Tn6 is turned on and the write external power-supply voltage Vpp is supplied as a power-source voltage to the column decoder and the row decoder, respectively, or when the Vpp detection signal R is at the L level, the p-channel MOS transistor Tp5 is turned on so that if the write control signal W# is at the H level (for verification), a voltage Vpp' derived from voltage division of the write external power-source voltage Vpp by resistors R1 and R2 is supplied to the column decoder and the row decoder, respectively. Fig. 22(A) is a circuit diagram of the power-source voltage selector in the flash-type memory according to the second embodiment. The general configuration of the flash-type memory according to this embodiment is the same as that shown in the block diagram in Fig. 26 and additionally includes the power-source voltage selector shown in Fig. 22(A) and the voltage dropping circuit shown in Fig.10. The power-source voltage selector according to this embodiment comprises a Vpp detection circuit 501 that is identical to that shown in Fig. 21 and a selection circuit 503'. For the verification, the selection circuit 503' supplies a voltage produced by an internal verification source voltage generation circuit 513 as a power-source voltage to the column and row decoders. The verification source voltage generation circuit 513 comprises a booster circuit composed of n-channel MOS transistors Tnll, Tn12 and Tn13 and capacitors C1 and C2 as shown in Fig. 22(B). Namely, the power-source voltage Vci to the internal circuit, produced by the voltage dropping circuit shown in Fig. 10, is raised and used as a power-source voltage to the column and row decoders. Note that the capacitors C1 and C2 are supplied with voltages 1 and 2 having the waveforms shown in Fig. 22 (C). The selection circuit 503' is so arranged that when the write external power-source voltage Vpp is supplied (the Vpp detection signal R is at the L level), the power-source voltage Vci is disconnected by the n-channel MOS transistor Tn7. If the write control signal W# is at the L level (for write), the write external power-source voltage Vpp is supplied as the power-source voltage to the column and row columns, respectively. If the write control signal W# is at the H level (for verification), the internal voltage boosted by the verification source voltage generation circuit 513 is supplied as the power-source voltage to the column and the row decoders, respectively. Fig. 23 is a circuit diagram of the power-source voltage selector in the flash-type memory according to the third embodiment. Note that the general configuration of this flash-type memory is identical to that shown in the block diagram in Fig.26 and additionally includes the power-source voltage selector shown in Fig. 23. The power-source voltage selector in this embodiment includes a p-channel MOS transistor Tp21 added to the voltage dropping circuit shown in Fig. 10 that is controlled with the Vpp detection signal R from the Vpp detection circuit 501; the transistor Tp21 serving to inhibit the word-line drive component from being dropped for the verification. Namely, when a data write is completed by a writer, the write external power-source voltage Vpp is supplied and the Vpp detection signal R takes the L level and the p-channel MOS transistor Tp21 is turned on so that the read external power-source voltage Vcc is supplied as it is as the power-source voltage (word-line potential) to the column and row decoders, respectively. Thus, a good verification can be effected. Also, it is one of the effective methods to form the power-source voltage selector from a conventional decoder circuit (shown in Fig. 27) and always supply the read external power-source voltage Vcc as a word-line potential for other than the data write. Fig. 24 is a circuit diagram of the sense amplifier in the flash-type memory according to the fourth embodiment. It should be noted that the general configuration of the flash-type memory according to this fourth embodiment is identical to that shown in Fig. 26 and additionally includes the Vpp detection circuit shown in Fig. 21 and the voltage dropping circuit shown in Fig. 10. In the flash-type memory according to this embodiment, the sense current of the sense amplifier SA is made smaller than that for the ordinary read, thereby attaining a good verification. As seen from the circuit diagram in Fig. 24 , the sense amplifier SA has two p-channel transistors Tp41 and Tp42 which form together a load circuit. The Vpp detection signal R# from the Vpp detection circuit is supplied to the gate of one (Tp42) of these transistors to supply a sense current to the bit line BL of the memory cell. The Vpp detection signal R# takes the L level for data read, the p-channel MOS transistor Tp42 is turned on and the sense current has a larger value as shown in Fig. 5. As seen from Fig.25 , the characteristic of the memory cell changes as indicated with the curve A for the verification, but by changing it to the sense current value for the data read, it is possible to provide an operational voltage margin for Vw-Vci. Namely, for the verification, the sense current of the sense amplifier SA is made smaller than that for the ordinary read, whereby a stable operation with the power-supply voltage Vci to the internal circuit can be ensured. As has been described in the foregoing, the first embodiment (Figure 21) is so configured that when the write external power-source voltage-is supplied, the voltage produced by dropping the read external power-source voltage to a predetermined value for the verification, the voltage obtained by dropping the write external power-source voltage is supplied as the word-line potential for the post-write verification. Thus, for a flash-type memory in which the read voltage is changed to a low voltage to minimize power consumption, an internal power-source voltage generation circuit can be provided in which verification can be effected even when the memory is operated with a voltage produced by internally dropping the power-source voltage and a stable device operation can be ensured. The second embodiment (Figure 22) is so arranged that, when the write external power-source voltage is supplied, the voltage produced by dropping the read external power-source voltage V to a predetermined value is disconnected and a voltage produced by boosting a voltage derived from dropping of the read external power-source voltage is supplied as the word-line potential for the post-write verification. Thus, the second embodiment provides an internal power-source voltage generation circuit for a flash-type memory, which can provide a good verification. The third embodiment (Figure 23) provides an internal power-source voltage generation circuit for a flash-type memory, comprising a voltage dropping circuit provided for the read circuit in the flash-type memory that drops the read external power-source voltage Vcc to a predetermined value, and a means of inhibiting the supply of a voltage derived by dropping the read external power-source voltage under the control of the Vpp detection circuit, which detects whether or not the write external power-source voltage is supplied, whereby the read external power-source voltage Vcc is supplied as it is as the word-line potential for the post-write verification so that a good verification can be ensured. Furthermore, in the fourth embodiment (Figure 24), a read external power-source voltage Vcc and a write external power-source voltage Vpp are used and the read circuit in the flash-type memory is operated with a voltage produced by raising or boosting the read external power-source voltage Vcc to a predetermined voltage, and for the verification, the sense current of the sense amplifier SA is made smaller than that for the ordinary read, whereby a stable operation with the power-source voltage Vci to the internal circuit can be ensured and a good verification can be done. Incidentally, when the internal power supply of the non-volatile semiconductor memory device including the flash memory described above is examined, the data readout operation alone, for example, includes the readout modes of at least three different kinds of systems, that is, the normal readout mode, the erase verify mode at the time of erase and the write verify mode after writing. In other words, three different kinds of power supply voltages are necessary in at least the readout mode in the non-volatile semiconductor memory device such as the flash memory, as can be understood from the example given above. However, these voltages have in most cases a predetermined correlationship between them, and when this correlationship collapses, a predetermined logical operation is likely to fail. Therefore, the correlationship between a plurality of kinds of power supply voltages must be kept constant by all means. As shown in Fig. 37, however, it has been customary according to the prior art to suitably select one of a number of separate power supply voltage generation circuits such as a power supply voltage generation circuit 790 for the first readout mode, a power supply voltage generation circuit 791 for the second readout model; ... , a power supply voltage generation circuit 792 for the n th readout mode, by the use of a mode selection circuit 793, and to supply the selected voltages to a decoder through a suitable booster circuit. In this case, a variance necessarily occurs between these power supply voltages, and the correlationship described above is likely to collapse. Such a problem results from the fact that a predetermined power supply voltage is formed from different power supply voltages by individual booster circuits. In other words, among the three kinds of internal power supply voltages described above, the or each power supply voltage that cannot be supplied directly from an external power supply must be generated inside the semiconductor memory device to match each mode. Recently, in order to reduce the power supply voltage, to use a single power supply and to improve an operation speed, it has become necessary to generate the power supply voltages for all the readout modes inside the semiconductor memory device to match each of the readout modes. However, when a low voltage operation is taken into account, variance will occur if the predetermined different power supply voltages are generated by suitable individual booster circuits, and there remains the problem described above that the correlationship between the power supply voltages collapses. In other words, there is the possibility that the voltage value will deviate from a target voltage value in each of the booster circuits due to variance in the production process, and the synergistic effect of this variance of the respective booster circuits causes the correlationship of the power supply voltages necessary for the readout modes to greatly deviate from the initial design values. As a result, there occurs the problem that an error occurs in the judgement of the write data to the read mode and the judgement of the erase data, and write defects as well as erase defects are more likely to occur. Therefore, it is preferable to provide a power supply circuit for use in a semiconductor memory device such as a flash memory having a power supply voltage generation function, which can solve the problems with the prior art described above, and which can easily generate a plurality of kinds of different power supply voltages. To accomplish the object described above, the power supply circuit for a non-volatile semiconductor memory device embodying the present invention preferably employs the following technical construction. In other words, in a preferred embodiment of the present invention the semiconductor memory device has a plurality of kinds of readout modes and requires a different power supply voltage for each of these modes, and comprises power source voltage input unit, reference voltage generation means, boost means including a capacitance device, and charge means for charging the capacitance device, the charge means of the capacitance device including charge quantity change means for changing the charge quantity of the capacitance device into a plurality of kinds in response to mutually different voltages. Namely, such a power supply voltage circuit uses a single external reference power supply source and one booster circuit, and generates a plurality of kinds of power supply voltages. More definitely, the reference source voltage is used as the first power source voltage by the use of one capacitance device and at the same time, a voltage necessary for generating mutually different voltages necessary for the readout modes is charged in advance in the capacitance device constituting the boost means, and at a predetermined timing control signals each having a voltage amplitude necessary to generate respective voltage the level of which is different from each other from the capacitance device, are applied to the capacitance device so that a plurality of kinds of mutually different, necessary power supply voltages can be generated by adding and combining the output charged voltage with the reference voltage. In a semiconductor memory device including such a power supply voltage circuit the correlationship between the power supply voltages of the readout modes is determined only by the amplitude of the signal input to the capacitance device, or only by the voltage charged in advance in the capacitance device, or by both of them. Accordingly, the power supply voltage can be controlled by controlling only the input signal or the charge voltage, so that setting of the power supply voltages becomes easier and the correlationship between the power supply voltages of the readout modes can be set more correctly. Hereinafter, a definite embodiment of this preferred power supply circuit will be explained in detail with reference to the drawings. Fig. 28 is a block diagram showing an example of the construction of the power supply voltage generation circuit 710 used in the semiconductor memory device according to this definite example. Fig. 28 illustrates a semiconductor memory device 701 which includes a logical circuit unit 702 having a plurality of kinds of readout modes, and which requires different power supply voltages for these readout modes. In other words, the semiconductor memory device 701 includes a power supply voltage input unit 703 and a power supply voltage generation circuit 710, which, in turn, includes reference voltage generation means 704, boost means 706 including a capacitance device 705, and charge means 707 for charging the capacitance device 705, the charge means 707 being equipped with charge quantity change means 707 for changing a charge quantity of the capacitance device 705 into a plurality of kinds in response to mutually different voltages required by the readout modes, respectively. In other words, the power supply voltage generation circuit 710 in the semiconductor memory device 701 according to this definite example generates a plurality of kinds of power supply voltages required by the logical circuit unit 702 by boosting the reference voltage by the capacitance device 705 and at the same time, changes the amplitude of a clock pulse signal input to the capacitance device 705 for generating the power supply voltage required by each readout mode in response to each of a plurality of kinds of power supply voltages required by the logical circuit unit 702, or changes the charge voltage to be charged in the capacitance device 705. The clock pulse signal having a different amplitude or the charge voltage having a different voltage is charged in the capacitance device 705 in accordance with a predetermined clock signal, and is added to, or subtracted from, the reference voltage so as to obtain a predetermined power supply voltage, which is output to the power supply voltage input unit 703 of the logical circuit unit 702 as the predetermined power supply voltage. The reference voltage generation means 704 in this definite example functions also as charge means for charging the capacitance device 705 constituting the boost means 706. Though its construction is not limited in particular, it may be constituted by connecting a P-channel enhancement type field effect transistor TP5 and an N-channel depletion type field effect transistor TD2 in series, connecting the gate of the P-channel enhancement type field effect transistor to the gate of the N-channel type depletion type field effect transistor TD2 through an inverter INV2, and connecting their common terminal to a suitable control terminal S1, as shown in Fig. 29. In this case, the free end portion of the P-channel type enhancement type field effect transistor TP5 in the reference voltage generation means 704 may be connected to a predetermined external power supply, or may be connected to an internal power supply voltage Vcc. On the other hand, the free end portion of the N-channel type depletion field effect transistor TD2 is connected to one of the ends of the capacitance device 705 disposed in the boost means 706. The power supply voltage generation circuit 710 in the semiconductor memory device 701 according to this definite example includes a suitable charge circuit 709 and charge quantity selection means 708 for changing the charge voltage to be charged in the capacitance device 705 constituting the boost means 706 into a plurality of kinds in accordance with the mutually different voltages required by the readout modes, respectively. In other words, the charge quantity selection means 708 is provided in advance with a plurality of kinds of voltage generation circuits capable of outputting a plurality of predetermined voltage levels, selects these voltage generation circuits by suitable selection means, supplies the selected voltage to the capacitance device 705, and boosts the voltage charged to the capacitance device 705 from the reference voltage generation means 704. The boost voltage is input to the power supply voltage input unit 703 of the logical circuit unit from a node portion N1 shown in Fig. 28. In this definite example, a predetermined clock pulse can be used as the charge quantity selection means. In other words, the charge quantity selection means 708 in this definite example may even be controlled by the signal from the clock circuit 711. In the power supply voltage generation circuit 710 in this definite example, the charge quantity change means 707 includes a suitable charge circuit 709 and at the same time, may be equipped with amplitude change means 712 for changing the amplitude of the clock pulse into the capacitance device 705 into a plurality of kinds in response to the mutually different voltages required by the readout modes, respectively. In the definite example, the amplitude change means 712 generates a predetermined pulse width control signal for the clock circuit 711 and changes the amplitude of this clock pulse into a plurality of kinds, so that the charge voltage charged in the capacitance device 705 disposed in the boost means 706 is changed. This means that the mutually different voltages required by the readout modes in the semiconductor memory device 701 according to this definite example are obtained by the selective addition of the output voltage from the reference voltage generation means 704 and the amplitude of the input signal to the boost means 706, respectively. Furthermore, all of a plurality of kinds of readout modes in the semiconductor memory device according to this definite example may be connected to the power supply voltage circuit such as the one described above, or at least a part of the readout modes may be connected to such a power supply voltage circuit. In any case, the mutually different voltages required for a plurality of kinds of readout modes in this definite example are preferably generated from the same internal power supply voltage. Hereinafter, the definite construction of the power supply voltage generation circuit 710 of the semiconductor memory device 701 according to this definite example will be explained in further detail. Fig. 29 is a block diagram useful for explaining a definite example of the power supply voltage generation circuit 710 of the semiconductor memory device 701 of this definite example. As described already, the reference voltage generation means 704 in this definite example is constituted by connecting the P-channel enhancement field effect transistor TP5 in series with the N-channel depletion field effect transistor TD2, connecting the gate of the P-channel enhancement field effect transistor to the gate of the N-channel depletion field effect transistor TD2 through the inverter INV2, and further connecting their common terminal to a suitable first control terminal S1. In this case, the free end portion of the P-channel enhancement field effect transistor TP5 in the reference voltage generation means 704 may be connected to a predetermined external power supply or to the internal power supply voltage Vcc. On the other hand, the free end portion of the N-channel depletion field effect transistor TD2 is connected to one of the end portions of the capacitance device 705 disposed in the boost means 706 and to the power supply voltage input unit 703 in the logical circuit unit 702 of the semiconductor memory device. The charge quantity change means 707 in the power supply voltage generation circuit 710 includes a first transistor train 712 formed by connecting in series an N-channel depletion field effect transistor TD1, P-channel enhancement field effect transistors TP3 and TP4, and N-channel enhancement field effect transistor TN4 and TN5 in the order named, between the internal power supply voltage Vcc and the ground potential GND. The charge quantity change means 7 in the power supply voltage generation circuit 710 includes a second transistor train 713 formed by connecting in series P-channel enhancement field effect transistors TP1 and TP2, N-channel enhancement field effect transistors TN1 and TN2, and an N-channel enhancement field effect transistor TN3 between the internal power supply voltage Vcc and the ground potential GND in the order named. A clock terminal portion CLK1 which is disposed separately is connected to the gate of each of the P-channel enhancement field effect transistor TP4 and the N-channel enhancement field effect transistor TN4 and also to the gate of each of the P-channel enhancement field effect transistor TP2 and the N-channel enhancement field effect transistor TN2. On the other hand, a second control terminal S2 is connected to the gate of each of the N-channel enhancement field effect transistor TN3 and the P-channel enhancement field effect transistor TP3, and at the same time, to the gate of each of the N-channel enhancement field effect transistor TN5 and the P-channel enhancement field effect transistor PT1 through the inverter INV1. A third control terminal S3 is connected to the gate of the N-channel depletion field effect transistor TD1, and the internal power supply voltage Vcc is connected to the gate of the N-channel enhancement field effect transistor TN1. The output terminals N2-1 and N2-2 of the first and second transistor trains 712 and 713 are commonly connected to one of the end portions of the capacitance device 705. In such a power supply voltage generation circuit, the charge voltage charged in the capacitance device 705 can be set to a predetermined voltage level by appropriately switching the control voltage applied to the control terminals S1, S2 and S3 and simultaneously applying the clock in a suitable cycle. Therefore, this voltage is added to the voltage which is in advance generated in the reference voltage generation means 704 and charged in the capacitance device 705, and the reference voltage is output as the boosted voltage from the output node portion N3. Next, the operation of the power supply generation circuit 710 shown in Fig. 29 will be explained. First of all, assuming that the second control signal S2 is at the "L" level and the third control signal S3 is at the "H" level, the control signal S1 is set to the "H" level so as to drive the reference voltage generation circuit 704. Accordingly, the voltage of the power supply voltage output unit N3 is charged to the power supply voltage Vcc (this will be referred to as the "first power supply voltage"). At this time, if the clock CLK1 is set to "H" as shown in Fig.30 (A), the first control signal S1 is set to the "L" level at the point tl at which the power supply voltage output unit N3 is sufficiently charged, and the clock CLK1 is set to the "L" level at the point t2 which is somewhat retarded from the point tl at which the control signal S1 changes from the "H" level to the "L" level. Since the control signal S2 is at the "L" level at this time, the second inverter 712 constituted by the first transistor train 712 becomes effective, and since the third control signal S3 is at the "H" level, the potential at the connection node N1 between the N-channel depletion field effect transistor TD1 and the P-channel enhancement field effect transistor TP3 in the second inverter 712 becomes Vcc, so that the potential of the output node N2-1 changes from 0 V to Vcc. As described above, since the power supply voltage output unit N3 and the output node N2 are capacitance-coupled by the capacitance device 705 as shown in Fig. 30(B), the potential at the power supply voltage output unit N3 is raised from Vcc to 2Vcc, and here, the second power supply voltage is generated. Next, the case where the second control signal S2 is set to the "L" level and the third control signal S3, too, is set to the "L" level, will be taken into consideration. In the same way as in the definite example described above, the control signal S1 is set to the "H" level and the voltage of the power supply voltage output unit N3 is charged to the internal power supply voltage Vcc. As shown in Fig. 30 (C), at the time tl at which the power supply voltage output unit N3 is sufficiently charged, the first control signal S1 is kept at the "L" level and at the time t2 slightly delayed from the time t1, at which the signal level of the first control signal S1 is changed from "H" level to "L" level, the clock CLK1 is set to the "L" level. In this case, since the second control signal S2 remains at the "L" level, the second inverter 712 consisting of the first transistor train 712 becomes effective, but since the third control signal S3 is at the "L" level, the potential of the connection node N1 between the N-channel depletion field effect transistor TD1 and the P-channel enhancement field effect transistor TD3 reaches the threshold value Vtd of this transistor TD1. Accordingly, the potential of the output node N2-1 changes from 0 V to Vtd as shown in Fig. 30 (D). Since the power supply voltage output unit N3 and the output node N2 are capacitance-coupled by the capacitance device 705, the potential of the power supply voltage output unit N3 is boosted from Vcc to Vcc + Vtd, and here, the third power supply voltage is generated (refer to Fig.30 (D)). Furthermore, the case where the second control signal S2 is set to the "H" level will be taken into consideration. In the same way as in the definite example described above, the control signal S1 is set to the "H" level, and the voltage of the power supply voltage output unit N3 is charged to the internal power supply voltage Vcc. At this time, at the time tl at which the power supply voltage output unit N3 is sufficiently charged as shown in Fig. 30 (C), the first control signal S1 is kept at "L" level and at the time t2 slightly delayed from the time tl, at which signal level of the first control signal S1 is changed from "H" level to "L" level, the clock CLK1 is set to the "L" level. Since the second control signal S2 remains at the "H" level, the P-channel enhancement field effect transistor TP2 and the N-channel enhancement field effect transistors TN1 and TN2 are turned ON, so that the third inverter 713 consisting of the second transistor train 713 becomes effective, and the potential of the output node N2-2 as the connection node between the N-channel enhancement field effect transistors TN1 and TN2 in the third inverter 713 changes from 0 V to Vcc - Vth which is the difference obtained by subtracting the threshold voltage Vth of the N-channel enhancement field effect transistor TNI from Vcc. Since the power supply voltage output unit N3 and the output node N2 are capacitance-coupled by the capacitance device 705, the potential of the power supply voltage output unit N3 is boosted from Vcc to 2Vcc + Vtn, and here, the fourth power supply voltage is generated (refer to Fig. 30(E)). In other words, the control signals S1 to S3 in this definite example constitute the charge quantity selection means 708 for changing the charge voltage to be charged in the capacitance device 705 in this definite example into a plurality of kinds of voltages. In other words, this definite example makes it possible to extract four different kinds of power supply voltages from the same internal power supply voltage Vcc, and this operation can be executed by adjusting the application timings of the control signals S1 to S3 and the clock CLK. Next, the construction and operation of another definite example of the power supply voltage generation circuit 710 according to the present invention will be explained with reference to Fig. 31. The construction of the reference voltage generation means 704 shown in Fig. 31 and its connection relation with the boost means 706 including the capacitance device 705 are the same as the construction of the definite example explained with reference to Fig. 29 , but the construction of the charge quantity change means 707 is different. In other words, a P-channel enhancement field effect transistor TP6, N-channel enhancement field effect transistors TN6, TN7, a P-channel enhancement field effect transistor TP9 and an N-channel enhancement field effect transistor TN8 are connected in series in the order named between the internal power supply voltage Vcc and the ground potential GND, the internal power supply voltage Vcc is connected to the gate of the N-channel enhancement field effect transistor TN6, and the clock CLK2 is connected to the gate each of the P-channel enhancement field effect transistor TP6 and the N-channel enhancement field effect transistor TN8. A P-channel enhancement field effect transistor TP7, to the gate of which a fifth control signal S5 is input, is connected to a connection node N4 between the P-channel enhancement field effect transistor TP6 and the N-channel enhancement field effect transistor TN6, and a P-channel enhancement field effect transistor TP8, to the gate of which a sixth control signal S6 is input, is connected to a connection node N5 between the N-channel enhancement field effect transistors TN6 and TN7. The other end of each of the P-channel enhancement field effect transistors TP7, TP8 is connected to the connection node N6 between the P-channel enhancement field effect transistor TP9 and an N-channel enhancement field effect transistor TN8 to the gates of which a seventh control signal S7 is input. The other end of each of the transistors TP7 and TP8 is further connected in common to one of the ends of the capacitance device 705. The gate of the N-channel enhancement field effect transistor TN7 is connected to the connection node N5 between the N-channel enhancement field effect transistors TN6 and TN7. In the same way as in the timing chart of the definite example described above, in Fig. 32, too, the control signal S1 is set to the "H" level and the reference voltage generation means 704 is driven so that the voltage of the power supply voltage output unit N3 is charged to the internal power supply voltage Vcc. At this time, when the clock CLK1 is set to the "H" level as shown in Fig. 32 (A), the first control signal S1 is set to the "L" level at the point t1 at which the power supply voltage output unit N3 is sufficiently charged, and the clock CLK1 is set to the "L" level at the point t2 which is somewhat behind the point tl at which the control signal S1 changes from the "H" level to the "L" level. Under the situation described above, the control signal S5 is fixed to the "L" level and the control signals S6 and S7 are fixed to the "H" level among the control signals S5 to S7 applied to the gate of each of the P-channel enhancement field effect transistors TP7 to TP9. Then, at the point t2 at which the clock LCK 2 changes from the "H" level to the "L" level, only the P-channel enhancement field effect transistors TP6 and TP7 are turned ON as shown in Fig. 32 (B), and the current is supplied from the internal power supply voltage Vcc to the connection node N7 through the P-channel enhancement field effect transistors TP6 and TP7. Therefore, the potential of this connection node N7 changes from 0 V to Vcc. Accordingly, in the same way as in the definite example described above, the potential of the power supply voltage output unit N3 is boosted from Vcc to 2Vcc and here, the second power supply voltage is generated (refer to Fig. 32 (B)). Next, when the control signal S6 among the control signals applied to the gate of each of the P-channel field effect transistors TP7 to TP9 is fixed to the "L" level and the control signals S5 and S7 are fixed to the "H" level, then, only the P-channel enhancement field effect transistor TP8 becomes effective at the time t2 at which the clock CLK2 changes from the "H" level to the "L" level as shown in Fig. 32 (C), and the current is supplied from the N-channel enhancement field effect transistor TN6, which is turned ON by the internal power supply voltage Vcc, to the connection node N7 through the P-channel enhancement field effect transistor TP8. In this case, the potential at the connection node N5 between the N-channel enhancement field effect transistors TN6 and TN7 is fixed to a potential which is reduced by the threshold value Vth of the transistor TN6 from the internal power supply voltage Vcc. Accordingly, the potential of this connection node N7 changes from Vcc to Vcc - Vth. Accordingly, the potential of the power supply voltage output unit N3 is boosted to 2Vcc - Vth, and here, the third power supply voltage is generated (refer to Fig. 32(C)). Next, the control signal S7 among the control signals applied to the gate of each of the P-channel enhancement field effect transistor TP7 to TP9 is fixed to the "L" level and the control signals S5 and S6 are fixed to the "H" level. Then, at the timing t2 at which the clock CLK2 changes from the "H" level to the "L" level, only the P-channel enhancement field effect transistor TP9 becomes effective as shown in Fig. 32 (D), and the current is supplied from the N-channel enhancement field effect transistors TN6 and TN7, which are turned ON by the internal power supply voltage Vcc, to the connection node N7 through the P-channel enhancement field effect transistor TP9. In this case, the potential at the connection node N6 between the N-channel enhancement field effect transistor TN7 and the P-channel enhancement field effect transistor TP9 is fixed to a potential which is lower by 2Vth of the threshold values of these transistors TN6 and TN7. Accordingly, the potential of the connection node N7 changes from 0 V to Vcc - 2Vth. Therefore, the potential of the power supply voltage output unit N3 is boosted to 2Vcc - 2Vth, and here, the fourth power supply voltage is generated (refer to Fig. 32 (D)). Next, another definite example of the power supply voltage generation circuit 710 used for the semiconductor memory device of this embodiment will be explained with reference to Figs. 33 and 34 . Fig. 33 shows the circuit construction of the power supply voltage generation circuit 710 according to this definite example. In the reference voltage generation means 704, an N-channel depletion field effect transistor TD5, a P-channel enhancement field effect transistor TPll and an N-channel depletion field effect transistor TD6 are connected in series in the order named between the internal power supply voltage Vcc and the power supply voltage input unit 3, the control signal S8 is connected to the gate of this transistor TD5, the control signal S10 is connected to the connection node N10 between the transistors TD5 and TN10, and an N-channel enhancement field effect transistor TN11 connected to the internal power supply voltage Vcc is connected to this connection node N10. The gate of this transistor TN10 is connected to the gate of the transistor TD6 through an inverter INV3, and the control signal S9 is connected to their common node. On the other hand, boost means 706 including the capacitance device 705 connected thereto at one of the ends thereof is disposed at the connection node 11 between the transistor TD6 and the power supply voltage input unit 3, and the other end of the capacitance device 705 is connected to an inverter INV4 to which the clock CLK is input. The inverter INV4 has the construction in which a P-channel enhancement field effect transistor TP10 and an N-channel enhancement field effect transistor TN9 are connected in series in order named between the internal power supply voltage Vcc and the ground potential GND, and the clock CLK3 is input to the gates of both transistors. The operation of the power supply voltage generation circuit 710 will be explained with reference to the timing chart shown in Figs. 34(A) to 34(H). To begin with, consider the case where the control signal S10 is set to the "L" level. First, the control signal S8 is set to the "H" level and the control signal S9, too, is set to the "H" level. The potential at the connection node N11 is then charged to Vcc at the timing t3 as represented by a solid line in Fig. 34(F) (first power supply voltage). At this time, the clock CLK3 is kept under the "H" level state. As shown in Figs.34(A) to 34(D) the control signals S8 and S9 are changed to the "L" level at suitable timings t4 and t5 after the timing t3 at which the connection node N11 is charged to Vcc, and at the same time, the clock CLK3 is changed to the "L" level at a timing t6. Then, the potential of the output portion of the inverter INV4 changes from 0 V to Vcc. Since the power supply voltage output unit N11 and the output node N9 are capacitance-coupled by the capacitance device 705 in the same way as in the definite example described above, the potential at the power supply voltage output unit N11 is boosted from Vcc to 2Vcc as represented by a solid line in Fig. 34(F) and here, the second power supply voltage is generated. Next, the case where the control signal S10 is set to the "L" level and the control signal S8 is set to the "L" level will be considered. Since the control signal S8 is at the "L" level, the potential at the connection node 10 is Vtd which is the threshold voltage of the transistor TD5. Accordingly, if the control signal S9 is set to the "H" level, the power supply voltage output unit N11 is charged to Vtd. At this time, if the clock CLK3 is kept at the "H" level and is then changed to the "L" level at the timings t5 and t6 at which the potential of the power supply voltage output unit N11 is sufficiently charged, the potential of the output portion N9 of the inverter INV4 changes from 0 V to Vcc, so that the potential of the power supply voltage output unit N11 is boosted from Vcc to Vcc + Vtd as represented by a dotted line in Fig.34(F) in the same way as in the definite example described above, and here, the third power supply voltage is generated. Furthermore, the case where the control signal S10 is set to the "H" level and the control signal S8 is set to the "L" level, will be considered. Since the control signal S10 is at the "H" level, the potential of the connection node N10 is Vcc - Vth which is lower by the threshold voltage Vth of the transistor TN11, and the transistor TD5 is cut OFF. In this case, however, it is assumed that Vtd < Vcc - Vtn. Then, the power supply voltage output unit N11 is charged to Vcc - Vtn as shown in Fig. 34(G)by setting the control signal S9 to the "H" level. At this time, while the clock CLK3 is kept at the "H" level, the control signal S9 and the clock CLK3 are changed to the "L" level at the timings t5 and t6, respectively, at the point at which the potential of the power supply voltage output unit N11 is sufficiently charged. Then, the potential of the output portion N9 of the inverter INV4 changes from 0 V to Vcc. Accordingly, the potential of the power supply voltage output unit N11 is boosted from Vcc to 2Vcc - Vtn as represented by a solid line shown in Fig. 34(H) and here, the fourth power supply voltage is generated. Fig. 35 shows the construction of still another definite example of the power supply voltage generation circuit 710 in this embodiment. The construction uses the reference voltage generation means 704 shown in Fig. 33 as the reference voltage generation means 704, and uses the charge quantity change means shown in Fig. 29 as the charge quantity change means 707. Since the principle of operation is the same as those of the foregoing definite examples, the explanation of the operation will be omitted. In this definite example, five kinds of control signals ranging from a control signal S10 to a control signal S14 are used. Therefore, nine different kinds of power supply voltages can be generated from one internal power supply voltage by combining the control signals with the clock CLK4. In other words, each definite example of this embodiment provides the advantage that since the correlationship between the power supply voltages is determined by the amplitude of the clock signal and the charge voltage, the correlationship can be controlled easily. Incidentally, in the power supply voltage generation circuit 710 in each definite embodiment, external power supply voltages of several systems can be used separately, and the internal power supply voltage and the external power supply voltages can be combined and used suitably. The power supply voltage generation circuit 710 in this definite example is used as the power supply voltage of the decoder, but is particularly preferably used as a power supply voltage circuit of a decoder in a flash memory. Fig. 36 shows an example wherein the power supply voltage generation circuit 710 according to this definite example is supplied to a row decoder of a flash memory. In the drawing, reference numeral 1 denotes a cell matrix, reference numeral 730 denotes a column decoder, reference numeral 740 denotes a Y gate, reference numeral 750 denotes a sense amplifier data-out buffer, reference numeral 760 denotes a control circuit and reference numeral 770 denotes an internal power supply circuit. Furthermore, Fig. 38 shows in more detail the circuit construction of a semiconductor memory device using the power supply voltage generation circuit 710 according to this definite example, and basically, the circuit construction is the same as that shown in Fig. 36. Reference numerals 770 and 780 denote an address buffer and a pre-decoder, respectively, and reference numeral 781 denotes a negative charge pump. Judging from the function, the reference voltage generation means 704 according to this definite example charges the internal power supply voltage Vcc or the external power source voltage Vcc to the power supply voltage output units N3 and Nll, as already described. Therefore, any construction can be employed so long as it has such a circuit function. For example, a P-channel enhancement field effect transistor, an N-channel enhancement field effect transistor and an N-channel depletion field effect transistor shown in Figs. 39 to 41 can be used individually. In Fig.39 , however, when the control signal S is set to the "L" level at the time of charging and the output terminal N12 of the boost means (boosting circuit) 706 is charged to the internal power source voltage or to the external power source voltage Vcc, the P-channel enhancement field effect transistor TP20 is turned ON and the current flow from the output terminal N12 to the power supply if the boosting voltage is higher than the control signal S by the threshold voltage value of the transistor, even though the control signal S is set to the "H" level at the time of boosting. When the boosting voltage is not higher than the control signal S by at least the threshold voltage value, too, the current flows from the output terminal to the N-well if the boosting voltage is higher than Vcc by the ON voltage of the P-N junction. Therefore, the power is consumed. To prevent such problems, boosting must be done by each N-well but if such a construction is employed, the capacity of the boosting circuit must be improved to a considerable extent, so that another problem occurs in that the boosting circuit becomes greater in size and the cost of production becomes higher. In Fig.40 , the output terminal N12 of the boosting circuit (boost means) 706 is charged by setting the control signal S to the "H" level at the time of charging, and no current flows from the output terminal to the power supply or to the substrate at the time of boosting. However, since the N-channel enhancement field effect transistor TN20 is used, there remains the problem in that the output terminal N12 can be charged only up to Vcc - Vtn when the threshold voltage of the N-channel enhancement field effect transistor is Vtn. Furthermore, in Fig. 41, the output terminal N12 of the boosting circuit 706 can be charged to Vcc by setting the control signal S to the "H" level at the time of charging. If the potential Vcc of the output terminal is higher than the threshold voltage value Vtd of the N-channel enhancement field effect transistor TD20 when the control signal S is set to the "L" level at the time of boosting, no current flows from this output terminal N12 to the power supply, but if a circuit for passing a penetration current such as a decoder is connected to the power supply line as shown in Fig. 41, there is the problem that the power supply voltage Vcc becomes lower than the threshold voltage Vtd and a current flows from the output terminal N12 to the power supply. Accordingly, the reference voltage generation means 704 of the power supply voltage generation circuit 710 in this embodiment preferably has the circuit construction which does not generate the problems described above. As described in the definite example, a preferred circuit construction of the reference voltage generation means 704 connected to the boost means 706 comprises a P-channel enhancement field effect transistor TP21 which is connected to an internal power supply voltage supplied through an N-channel depletion field effect transistor TD22, for example, and to the gate of which the first control signal is inputted, and an N-channel depletion field effect transistor TD21 the drain of which is connected to the drain of the P-channel enhancement field effect transistor TP21, to the gate of which the control signal is input and at the source of which the boosting voltage appears. The first and second control signals 23, 24 in this definite example may be input independently and individually as shown in Fig. 43, or their complementary signals may be input through an inverter INV20, etc., using one control signal S22, as shown in Fig. 42 . In the definite example of this embodiment shown in Fig. 43, the leakage current from the output terminal N12 is cut off by the P-channel enhancement field effect transistor TP21 at the time of boosting, and the leakage current from the P-type region of this P-channel enhancement field effect transistor TP21 to the N-well does not occur because the threshold voltage Vtd of the N-channel depletion field effect transistor TD21 limits the potential difference between the P-type region and the N-well below the ON voltage of the O-N junction. The reference voltage generation means 704 in this definite example consists of the P-channel enhancement field effect transistor TP21 and the N-channel depletion field effect transistor TD21. Accordingly, the charge voltage of the output terminal N21 can be secured at a sufficiently high level. The definite example shown in Fig.42 will be explained. It will be hereby assumed that the internal power supply voltage is clamped at the threshold voltage Vtd of the N-channel depletion field effect transistor TD22 by this transistor TD22. Here, when the clock signal CLK22 is set to the "L" level and the control signal S22 is set to the "H" level. Then, the P-channel enhancement field effect transistor TP21 is turned OFF and the transistor TD21 is strongly turned ON at the time of charging, so that the potential of the connection node N14 between the transistor TD21 and the capacitance device 705 is charged to Vtd. The control signal S22 is set to the "L" level when the potential of the connection node N14 is sufficiently charged. At this time, the transistor TP21 is turned OFF and the transistor TD21 is weakly turned ON. Thereafter, when the clock signal CLK22 is set to the "H" level, the potential of the connection node N14 is boosted from Vtd to 2Vtd. On the other hand, since the gate of the transistor TD21 is at 0 V, the potential at the connection node N14 does not rise beyond Vtd. Since the potentials at both the source and drain of the transistor TP21 are at Vtd, no leakage current flows from this connection node N14 to the internal power supply. Furthermore, if the potential difference between Vtd and N-well is set to be below the ON voltage of the P-N junction; the leakage current from the connection node N14 to the N-well is eliminated, as well. It is preferred in this definite example to dispose control means for setting the first control signal S23 to the "L" level after the second control signal S24 reaches the "H" level and for setting the first control signal S23 to the "H" level after the second control signal S24 reaches the "L" level at the time of boosting. According to this definite example, the connection node N14 can be charged to a sufficient high voltage, and no leakage current is allowed to flow at the time of boosting. Furthermore, boosting efficiency of the booster circuit can also be improved. Since this definite example employs the technical construction described above, the power supply voltage can be controlled by controlling only the input signal and the charge voltage. Therefore, setting of the power supply voltage becomes easy and moreover, the correlationship between the power supply voltages of each mode can be set very accurately. In this way, since the correlationship of the power supply voltages of each mode can be set very accurately, this definite example makes a great contribution to the reduction of erase defects and write defects in the flash memory.

Claims: A nonvolatile semiconductor memory having circuitry including a matrix (1) of nonvolatile erasable memory cells (Mij) formed at intersections of word lines (WL1 to WLm) and bit lines (BL11 to BL1k, ..., BLn1 to BLnk), a row decoder (3), a column decoder (5), and sense amplifiers (71 to 7n) connected to the bit lines (BL11 to BL1k, ..., BLn1 to BLnk), the nonvolatile semiconductor memory further including an internal source voltage generator (8) for connection when the memory is in use to an external power source and operable selectively to produce predetermined internal source voltages (V CC , V WVER , V EVER ) in dependence upon the voltage (V PP ) of the external power source, such internal source voltages being applied to the said circuitry such that it carries out predetermined operations according to the internal source voltages, one of the said predetermined internal source voltages (W WVER , V EVER ) being a predetermined verify source voltage of a level suitable for performing a preselected verify operation on one of the said memory cells; characterised in that another one of the said internal source voltages selectively producible by the internal source voltage generator (8) is a normal source voltage (V CC ) of a level suitable for performing a normal reading operation on one of the said memory cells. A nonvolatile semiconductor memory according to claim 1, wherein said preselected verify operation is a write verify operation or an erase verify operation in which the said internal source voltage generator (8) is operable to generate a voltage (V WVER , V EVER ) different from said internal source voltage (V CC ) output from said internal source voltage generator (8) when such a normal reading operation is carried out. A nonvolatile semiconductor memory according to claim 2, wherein said internal source voltage generator includes a verify power source (8) selectively controllable to generate a write verify source voltage (V WVER ) and an erase verify source voltage (V EVER ) that is different from the write verify source voltage. A nonvolatile semiconductor memory according to claim 3, wherein the internal source voltage generator (8) is operable to generate the said normal source voltage (V CC ) when the verify power source (8) generates neither the said write verify source voltage (V WVER ) nor the said erase verify source voltage (V EVER ) . A nonvolatile semiconductor memory according to claim 2, wherein in the said preselected verify operation the said internal source voltage generator (8) supplies the said predetermined verify source voltage (V WVER ;V EVER ) to the sense amplifiers (71 to 7n) and said word lines (WL1 to WLm) selected in the preselected verify operation concerned. A nonvolatile semiconductor memory according to claim 5, wherein in the said preselected verify operation the said internal source voltage generator (8) supplies the said predetermined verify source voltage (V WVER ; V EVER ) just to said sense amplifiers and said word lines selected in the preselected verify operation concerned, while the said normal source voltage (V CC ) is supplied to the remaining parts (5) of the said circuitry of the nonvolatile semiconductor memory which operate at that normal source voltage. The nonvolatile semiconductor memory according to claim 3, wherein the write verify source voltage (V WVER ) is higher than the normal source voltage (V CC ) and the erase verify source voltage (V EVER ) is lower than the normal source voltage (V CC ). The nonvolatile semiconductor memory according to claim 3, wherein the verify power source (8) selectively generates one of the write verify source voltage (V WVER ) and erase verify source voltage (V EVER ) in response to a control signal (C). The nonvolatile semiconductor memory according to claim 1, wherein the internal source voltage generator (8) is adapted for connection, when the memory is in use, to receive at least one of a normal source voltage (Vcc) and a write/erase source voltage (Vpp) from the external power source. The nonvolatile semiconductor memory according to claim 3, wherein the verify power source (8) comprises: voltage dividers (31 to 33) for deriving, from a voltage (V PP ) supplied by the external power source, a first verify voltage (V WVER ) suitable for such a write verify operation and a second verify voltage (V EVER ) suitable for such an erase verify operation; gate circuits (34, 35) for passing the first verify voltage (V WVER ) in response to a write verify signal (WV) and for passing the second verify voltage (V EVER ) in response to an erase verify signal (EV) ; and circuits (36 to 41) having a current mirror configuration for providing the said predetermined verify source voltage (VVER) corresponding to that one of the first and second verify voltages which is passed through the gate circuits. The nonvolatile semiconductor memory according to claim 6, wherein an input terminal of each of the sense amplifiers (7i), at which terminal the verify source voltage (W WVER /V EVER ) is applied to the sense amplifier concerned, has means (14) for providing a load-resistance function. The nonvolatile semiconductor memory according to any preceding claim, wherein each of the sense amplifiers (7i) comprises: a load-resistance element (14); and a level-transmission transistor (15) connected in series with the load-resistance element (14) between the verify source voltage (V VER ) and a data line (Di) of the said circuitry that corresponds to a plurality of the said bit lines (BLi1 to BLik) ; a node, at which the load-resistance element (14) is connected to the level-transmission transistor (15), being connected to an output end (I/Oi) of the sense amplifier (7i); the level-transmission transistor (15) serving to transmit a level of the data line to the output end (I/Oi) ; and the load-resistance element (14) serving to distinguish cell data on the data line (Di) according to an ON/OFF state of the level-transmission transistor (15). The nonvolatile semiconductor memory according to claim 12, wherein: the load-resistance element (14) is a p-channel transistor whose source, gate, and drain are connected respectively to the verify source voltage (V WVER /V EVER ), a reference voltage (V SS ), and the said output end (I/Oi) of the sense amplifier (7i); and the said level-transmission transistor (15) is an n-channel transistor whose drain, gate, and source are connected respectively to the output end (I/Oi) of the sense amplifier (7i), a node providing an inversion of the data line level, and the data line (Di). The nonvolatile semiconductor memory according to claim 12 or 13, further comprising: a buffer circuit (16 to 19), disposed at the output end of the sense amplifier, and having the verify source voltage (V VER ) as its source voltage. The nonvolatile semiconductor memory according to claim 12, 13 or 14, further comprising: a voltage drop element (20) connected between the verify source voltage (V VER ) and the load-resistance element (14); and a constant current element (21) connected between the verify source voltage and the output end of the sense amplifier. The nonvolatile semiconductor memory according to claim 15, wherein the voltage drop element is a p-channel transistor (20) whose gate is connected to its drain. The nonvolatile semiconductor memory according to claim 15 or 16, wherein the constant current element is an n-channel transistor (21) whose gate is connected to its source. The nonvolatile semiconductor memory according to any preceding claim, further comprising: a power source (9) for supplying an external source voltage to the source of each transistor of each of the nonvolatile memory cells. The nonvolatile semiconductor memory according to claim 1, wherein the said internal source voltage generator comprises: voltage dropping means for dropping an external source voltage (V cc ) to a predetermined internal voltage (V ci ), the voltage dropping means having a voltage conversion transistor (Q) connected between the external source voltage and a node (N) for providing the internal voltage, the gate of the transistor (Q) receiving a reference voltage so that the node (N) may provide the dropped internal voltage. The nonvolatile semiconductor memory according to claim 19, wherein the voltage conversion transistor (Q) is an n-channel depletion transistor. The nonvolatile semiconductor memory according to claim 19, further comprising: a smoothing capacitor (C) connected to the internal voltage providing node (N). The nonvolatile semiconductor memory according to claim 20, wherein a threshold of the voltage conversion transistor (Q) is changed to adjust a voltage dropping level. The nonvolatile semiconductor memory according to claim 19, wherein the reference voltage applied to the gate of the voltage conversion transistor (Q) is a single voltage supplied from a reference power source line (V ss ) of the semiconductor memory. The nonvolatile semiconductor memory according to claim 19, further comprising: a nonvolatile memory element (QM); and a circuit (Q1 to Q5) for determining the reference voltage applied to the gate of the transistor (Q) according to the contents of the memory element (QM), the reference voltage being set to one of the external source voltage (V cc ) and reference source voltage (V ss ) of the semiconductor memory according to the contents of the memory element, so that the internal voltage providing node (N) may provide one of the dropped internal voltage (V ci ) and normal source voltage (V cc ). The nonvolatile semiconductor memory according to claim 19, further comprising: an input circuit (Q11 to Q20) for transmitting an input signal (Si) to internal circuits at least some of which are driven by the dropped internal voltage (V ci ), first elements (Q11 to Q16) of the input circuit being driven by the external source voltage (V cc ) and serving to directly receive the input signal, stabilize the level of the input signal, and provide the stabilized input signal, second elements (Q17 to Q20) of the input circuit being driven by the dropped internal voltage (V ci ) and serving to transmit the stabilized input signal to the internal circuits. The nonvolatile semiconductor memory according to claim 25, wherein at least a first part (Q17, Q18) of the said second elements (Q17 to Q20) driven by the dropped internal voltage (V ci ) is composed of transistors having a relatively high gate withstand voltage, and the said first elements (Qll to Q16) driven by the external source voltage (V cc ) are composed of transistors having a relatively high drain or gate withstand voltage. The nonvolatile semiconductor memory according to claim 19, further comprising: an output circuit (Q21 to Q28) for receiving a data signal from internal circuits at least some of which are driven by the dropped internal voltage (V ci ), and providing the data signal as data output (So) to the outside, first elements (Q21 to Q24) of the output circuit being driven by the dropped internal voltage (V ci ) and external source voltage (V cc ), and serving to convert the voltage level of the data signal into the level of the external source voltage, and second elements (Q25 to Q28) of the output circuit being driven by the external source voltage (V cc ) and serving to provide the level-converted signal as the data output. The nonvolatile semiconductor memory according to claim 27, wherein the elements (Q24, Q25 to Q28) driven by the external source voltage (V cc ) are composed of transistors having a relatively high drain or gate withstand voltage. The nonvolatile semiconductor memory according to claim 19, wherein the said voltage dropping means receives an external source voltage (V cc ) for read and external source voltage (V pp ) for write and further comprises: means (503) for dropping the external source voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation. The nonvolatile semiconductor memory according to claim 19, wherein the said voltage dropping means receives an external source voltage (V cc ) for read and an external source voltage (V pp ) for write and further comprises: means (503') for dropping the external source voltage (V cc ) for read to a fixed value to drive a circuit for carrying out a read operation in the nonvolatile semiconductor memory; and means (513) for internally producing a voltage (V ci ), which is higher than the dropped voltage of the external source voltage (V cc ) for read, and providing it as a word line potential for a verify-after-write operation. The nonvolatile semiconductor memory semiconductor memory according to claim 19, wherein the said voltage dropping means receives an external source voltage (Vcc) for read and an external source voltage (Vpp) for write and further comprises: means (Tp21) for dropping the external source voltage (Vcc) for read to a fixed value to drive a circuit for carrying out a read operation in the nonvolatile semiconductor memory; and means for prohibiting the dropping of the external source voltage (Vcc) for read at least for some circuits during a verify-after-write operation. The nonvolatile semiconductor memory according to claim 31, wherein the dropping of the external source voltage (Vcc) for read is prohibited for the row decoder. The nonvolatile semiconductor memory according to claim 19, wherein the said voltage dropping means receives an external source voltage (Vcc) for read and an external source (Vpp) for write and further comprises: means for dropping the external source voltage (Vcc) for read to a fixed value to drive a circuit for carrying out a read operation in the nonvolatile semiconductor memory; and means (Tp41, Tp42) for reducing a sense current to the sense amplifiers for a verify-after-write operation smaller than a sense current thereto for a normal read operation. A nonvolatile semiconductor memory as claimed in claim 1, having a plurality of read modes requiring different source voltages, the nonvolatile semiconductor memory comprising: a source voltage input portion (710); reference voltage generation means (704); boost means (706) including a capacitance element (705); and charging means (707) for charging the capacitance element, including charge quantity changing means (707) for changing the charge quantity of the capacitance element in several levels according to the different voltages required for the read modes. The nonvolatile semiconductor memory according to claim 34, wherein the charging means includes the reference voltage generation means (704). The nonvolatile semiconductor memory according to claim 34, wherein the charge quantity changing means provided for the charging means includes amplitude changing means (712) for changing the amplitude of a clock pulse provided to the capacitance element (705) in several levels according to the different voltages required for the read modes. The nonvolatile semiconductor memory according to claim 34, wherein the charge quantity changing means (707) provided for the charging means includes charge quantity selection means (708) for changing the charge voltage of the capacitance element in several levels according to the different voltages required for the read modes. The nonvolatile semiconductor memory according to claim 36, wherein the amplitude changing means (712) employs a clock pulse (CLK1) having a predetermined amplitude. The nonvolatile semiconductor memory according to claim 37, wherein the charge quantity selection means (708) is controlled by a clock circuit (711). The nonvolatile semiconductor memory according to claim 34, wherein the different voltages required for the read modes are obtained by selectively adding an output voltage of the reference voltage generation means (704) to an output voltage of the boost means (706). The nonvolatile semiconductor memory according to claim 34, wherein the reference voltage generation means connected to the boost means comprises: a p-channel enhancement FET (TP5) having a source connected to an internal or external power source (V CC ) and a gate receiving a first control signal ( S1 ); and an n-channel depletion FET (TD2) having a drain connected to the drain of the p-channel enhancement FET (TP5), a gate receiving a second control signal (S1), and a source connected to a node (N3) where an increased voltage appears. The nonvolatile semiconductor memcry according to claim 41, further comprising: control means (INV2) that sets the second control signal (S1) to level "H" and then the first control signal ( S1 ) to level "L" when charging, and sets the second control signal (S1) to level "L" and then the first control signal ( S1 ) to level "H" when increasing the voltage.

Inventors: AKAOGI TAKAO, KASA YASUSHI, KAWAMURA SHOUICHI, OGAWA YASUSHIGE, YOSHIDA MASANOBU, AKAOGI, TAKAO, KASA, YASUSHI, KAWAMURA, SHOUICHI, OGAWA, YASUSHIGE, YOSHIDA, MASANOBU, AKAOGI, TAKAO, C/O FUJITSU LIMITED, KASA, YASUSHI, C/O FUJITSU LIMITED, KAWAMURA, SHOUICHI, C/O FUJITSU LIMITED, Ogawa, Yasushige, c/o Fujitsu VLSI Limited, Yoshida, Masanobu, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11C29
IPC codes: G11C16, G11C29