Recording head driving device

Abstract: [Object] The recording head driving device is arranged in such that recording capable of providing a well-balanced printing density can be performed on the basis of the information recorded such as heat stored and the like between the adjacent recording heads. [Construction] A control signal which is used to control the time required for energizing a recording head 7 is input to a gate circuit 52 for driving the above described recording head from an AND gate 82 or/and an OR gate 113 in response to the present or/and past information recorded obtained from the adjacent latch circuit 21.

Description: The invention relates to a recording head driving device for a thermal printer comprising heating elements energizable over a time interval, the device comprising: a plurality of gate circuits, each for outputting drive pulse signals for energizing a respective heating element; a plurality of latch circuits, each for storing print information of the present line and previous lines for a respective heating element; and a gate signal generating unit for outputting gate signals to be gated with the print information and supplied to the gate circuits. Such a device is known, for example, from US-A-4 912 985 which discloses a print controlling apparatus for a thermal printer which is adapted to print with a thermal head having a plurality of heat generating elements on thermal paper or the like. The print controlling apparatus includes a processor for processing data to be printed and then outputting the data. A head control circuit device is coupled between the processor and the thermal head for converting the data to be printed, output from the processor, to energizing signals for selectively heating the heat generating elements. The heat control circuit device includes a timing mechanism for providing at least two predetermined energizing intervals. A storage mechanism stores the present print data and at least one previous print data. A gating circuit coupled to the timing mechanism and the storage mechanism produces energizing signals for each of the heat generating elements by logically combining the predetermined energizing intervals and present print data and previous print data. In the conventional device according to US-A-4 912 485, a control is made only through the on or off state of the immediate previous printing information of the adjacent elements. No account is given for the situation that for a respective heating element, the present print information is on for one or both of the adjacent heating elements. This can lead to a higher heat supply to the respective heating element from its neighbours, which may create problems in practice. The document US-A-4 567 488 discloses a method and a device for driving a thermal head taking into consideration not only picture data already recorded and picture data on the line containing the aimed data currently be recorded, but also picture data intended to be recorded. In the publication, a procedure is disclosed for controlling the energizing time of a given heating element, referred to as "aimed data D0". The influence of adjacent heating elements D1 to D10 on the heat to be supplied to the element D0 is predetermined by a weighting table. Depending on how close the other elements are to the aimed element D0, a different weighting is given. The thermal energy needed to print the aimed data D0 is then determined by adding up the numerical values to give heat storage data for the given point. The amount of thermal energy supplied then is adjusted by adjusting the width of amplitude of the voltage pulse applied to the heater element D0 in question. Having determined the heat storage state, one goes to a conversion table to determine the pulse width of the energizing signal to be supplied to the given heating element. For practical purposes, the thermal head driving device according to US-A-4 567 488 needs a fast acting CPU and considerable memory space. The successive patterns of printing must be input and processed in real time in the conventional device. For each aimed data point, the weighting table must be processed to determine the heat storage state. Thereafter, the conversion relationship of the table, also stored in the memory, must be consulted in order to determine the pulse width of the applied voltage. The entire processing is carried out completely digitally without gating of print data signals, gate signals and control signals. FIG. 1 is a circuit diagram showing a conventional one-dot type thermal head driving circuit which has been illustrated in a catalogue (as entitled "Thermal Head, H-C9683-E" described in P25 and issued on Feb., 1991) produced by Mitsubishi Electric Corp. Thermal heads are arranged in such a manner that the thermal head driving circuit is provided with a predetermined number of dots. In the same drawing, reference numeral 1 indicates a shift register for shifting input data on the present line in accordance with a clock. The shift register 1 has steps corresponding to the number of dots relative to the thermal heads. Designated at numeral 21 is a latch circuit for taking in data which appears at a tap of the shift register 1 so as to retain or hold it therein. Reference numeral 31 indicates a gate signal generating unit for generating three gate signals GA, GB, GC. Designated at numerals 4a, 4b are reverse logical product (hereafter called "NAND") gates serving as gate circuits supplied with latch outputs Q2, Q3 from the latch circuit 21 and gate signals GB, GC from the gate signal generating unit 31. Reference numeral 51 indicates a logical product (hereafter called "AND") gate serving as a gate circuit supplied with the outputs of the NAND gates 4a, 4b, the Q1 output of the latch circuit 21 and the gate signal GA of the gate signal generating unit 31 so as to output a pulse signal indicative of a conductible or energizable state therefrom. Designated at numeral 6 is a darlington transistor serving as a drive circuit for driving or energizing a thermal or heating resistor 7 of a thermal head in response to the pulse signal output from the AND gate 51. The operation of the thermal head driving circuit will now be described below. FIG. 2 is a timing chart for describing the relationship in time among respective signals. The shift register 1 first takes in data shown in FIG. 2(B) as an image signal in response to a clock signal shown in FIG. 2(A) and shifts it to a desired location. The latch circuit 21 successively takes in data from the tap of the shift register 1 corresponding to a dot thereof in response to a latch signal shown in FIG. 2(C). At this time, the latch circuit 21 brings data from the shift register 1 in response to the input latch signal and shifts the latched data one stage. As a result, data on the previous line relative to the dot appears at the Q2 terminal of the latch circuit 21, whereas data on the line prior to the previous line relative to the dot appears at the Q3 terminal. On the other hand, the gate signal generating unit 31 generates the gate signals GA, GB, GC represented in the form of given patterns as illustrated in FIGS. 2(D), 2(E) and 2(F). The pulse signal to be sent to the heating resistor 7 is determined by the gate signals GA, GB, GC, the outputs Q1, Q2, Q3 of the latch circuit 21, the NAND gates 4a, 4b and the AND gate 51. The darlington transistor 6 drives the heating resistor 7 in response to the signal delivered from the AND gate 51 so as to cause the heating resistor 7 to generate heat in proportion to the amount of current which flows into the heating resistor 7 driven by the darlington transistor 6, thereby subjecting a thermal recording paper or the like located on the heating resistor 7 to colour development. A description will now be made of history control of the amount of current supplied to the heating resistor 7. When the time required for the darlington transistor 6 to cause the heating resistor 7 to conduct current, i.e., energize the heating resistor 7 as shown in FIG. 3(A) is 1 ms, the temperature of the heating resistor 7 reaches 300°C. When, on the other hand, the energization of the heating resistor 7 is repeated in a period corresponding to 2 ms as shown in FIG. 3(B), the heating resistor 7 increases up to a temperature of 500°C. Thus, even if the same amount of current is provided, the temperature of the heating resistor 7 at the time of completion of the energization thereof is also high when the temperature of the heating resistor 7 at the start of the energization thereof is high. That is, a color-developed density becomes high upon energization of the heating resistor 7 in a quick repeating cycle unless the energy supplied to the heating resistor 7 is controlled. It is therefore necessary to control the amount of energy depending on the temperature of the heating resistor at the start of its energization. More specifically, the control for the energization of the heating resistor is performed based on a decision made as to whether or not desired data has been recorded at the line prior to the previous line. This history control is carried out in the following manner. That is, it is necessary to recognize the degree of an increase in temperature with respect to each of patterns (recorded conditions of dots at the present line, the previous line and the line prior to the previous line) in order to determine in what manner the energy should be supplied to a dot at the present line judging from the recorded conditions of the dots at the previous line and the line prior to the previous line, i.e., the energization with respect to its dot should be done. FIG. 4 is a simplified graph showing the result of simulated increases in temperature with respect to the respective patterns upon non-performance of the history control. In the same drawing, "H" represents that the recording (energization) of dots has been made, whereas "L" represents that the recording (energization) of the dots has not been done. For example, FIG. 4(B) shows that the recording of the dot has been made at the line prior to the previous line and the recording of the dot has not been made at the previous line. In addition, values (each of which represents the degree of an increase in temperature, but is now called a point number) obtained by normalizing respective temperatures at the time that the energization has been completed at the present line, are shown in FIG. 4. It is understood that the history control should be done in such a manner as to provide large energy because the point number is low as regards "1.0" [see FIG. 4(A)]. Also, a small amount of energy should be provided when the point number is as high as "3.0" as is shown in FIG. 4(D). FIG. 5 is a view showing the relationship between the point numbers shown in FIG. 4 and the data Q1, Q2, Q3 latched in the latch circuit 21. As has already been described above, the latch data Q1, Q2, Q3 respectively represent criterion made as to whether or not the dots are recorded at the line prior to the previous line, the previous line and the present line. Now, the number of levels is defined depending on the number of "H". The more the number of "H" produced in a pattern increases, the more the number of levels becomes high. The most suitable energized states corresponding to four kinds of patterns shown in FIG. 5 are represented by FIGS. 2(G) to 2(J). In order to establish a suitable current amount corresponding to the point numbers, the gate signal generating unit 31 generates the gate signals GA, GB and GC shown in FIGS. 2(D), 2(E) and 2(F). As a result, the outputs of the AND gate 51 corresponding to the output patterns of the latch circuit 21 are represented by FIGS. 2(G) to 2(J), and hence the amount of current associated with the point numbers is set. That is, the pattern (L, L, H) representative of the low point number is controlled in such a manner that the amount of current increases. The patterns indicative of the large point numbers are controlled such that the amount of current is reduced. Incidentally, the pulse widths of the gate signals GB, GC are identical to each other. In the case of two patterns in the same level, i.e., in the level 2, the energizing time at one of the two patterns and that at the other thereof are identical in total to each other. Incidentally, techniques related to the conventional thermal head driving circuit have been disclosed as references in JP-A-63-203346, JP-A-64-32973 and JP-A-64-67365, for example. The conventional thermal head driving circuit has been constructed as described above. It is therefore necessary to increase the number of the outputs of the latch circuit 21 when the history control is strictly performed. Thus, the number of patterns to be controlled increases, thereby causing a difficulty in suitably controlling the patterns. Further, when the respective heating resistors provided adjacent to one another are independently controlled, no attention has been paid to the influence of storage of heat generated between the adjacent respective heating resistors. Accordingly, the control of heat history cannot be performed with high accuracy. With the foregoing problems in view, it is therefore an object of the present invention to provide a recording head driving device which can provide an improved heat supply control to the individual heating elements so that a printing density with higher accuracy is achieved taking account of the history of the individual heating element and its adjacent heating elements. According to the present invention, this object is solved by a recording head driving device for a thermal printer of the type specified above which is characterized by a plurality of AND gates, each associated with one heating element, the output of each AND gate connected to gate a first control signal to each respective gate circuit, the first control signal controlling the energizing time interval of the respective heating element, wherein each of the AND gates receives the present print information for its associated heating element from its latch circuit and the present print information for adjacent heating elements from their latch circuits, and a plurality of OR gates, each associated with one heating element, for gating a second control signal to each of the gate circuits, the second control signal further controlling the energizing time interval, wherein each OR gate receives the present print information from the latch circuits for adjacent heating elements and receives no print information for its own heating element. According to another embodiment of the recording head driving device according to the present invention, the plurality of OR gates is replaced by a plurality of second AND gates, each associated with one heating element, for gating a third control signal to each of the gate circuits to control the energizing time interval, wherein each second AND gate receives the immediately previous print information from the latch circuits for adjacent heating elements and receives no print information for its own heating element. The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings. The accompanying drawings are used only for illustration and do not limit the scope of the invention. FIG. 1 is a block diagram showing a conventional thermal head driving circuit; FIG. 2 is a timing chart for describing the operation of the thermal head driving circuit shown in FIG. 1; FIG. 3 is a graph for describing the relationship between a pulse applied to each of the thermal resistors employed in the conventional thermal head driving device and the temperature of the thermal resistor; FIG. 4 is a simplified view for describing increases in temperature relative to four kinds of latch patterns output from the latch circuits in the conventional thermal head driving device; FIG. 5 is a view for describing the relationship between latch data representative of the four kinds of latch patterns output from the latch circuits in the conventional thermal head driving device and point numbers relative to increases in temperatures; FIG. 6 is a circuit diagram showing an example of a recording head driving device; FIG. 7 is a timing chart for describing signals at respective terminal points in the circuit diagram of the recording head driving device shown in FIG. 6; FIG. 8 is a view for describing the influence of heat generated by a recording head relative to one bit on other bits adjacent to the one bit; FIG. 9 is a circuit diagram showing a recording head driving device according to an embodiment of the present invention; FIG. 10 is a timing chart for describing signals at respective terminal points in the circuit diagram of the recording head driving device shown in FIG. 9; FIG. 11 is a circuit diagram illustrating a recording head driving device according to a further embodiment of the present invention; FIG. 12 is a circuit diagram depicting a recording head driving device, which corresponds to the recording head driving device shown in FIG. 6 whose parts are modified. FIG. 6 is a circuit diagram showing a recording head driving device. In FIG. 6, reference numeral 82 indicates AND gates having input terminals which are electrically connected to the Q1 terminals of the corresponding latch circuit 21 and the adjacent latch circuits 21. Reference numeral 92 indicates analog switches each of which is turned on in response to a signal output from each of the AND gates 82. Designated at numeral 102 is a control signal, which is in turn supplied to each of the analog switches 92 as a predetermined pulse signal. Reference numeral 52 indicates gate circuits serving as AND gates and reference numeral 7 indicates thermal or heating resistors. The same elements as those shown in FIG. 1 are identified by like reference numerals and the description of common elements will therefore be omitted. The operation of the recording head driving device will now be described. Each of the latch circuits 21 successively takes in data from a shift register 1 in response to an externally-input latch signal, in a manner similar to the conventional latch circuit. Thus, information recorded or retained on the previous line, i.e., at each Q1 terminal is output to the Q2 terminal of each of the latch circuits 21, whereas the information recorded or retained on the line prior to the previous line, i.e. the Q2 terminal is supplied to the Q3 terminal of each of the latch circuits 21. However, the recorded information at the Q1 terminals of adjacent dots i.e. the adjacent respective latch circuit 21 is input to each of the AND gates 82. When, on the other hand, the control signal 102 is input to each of the analog switches 92 in the timing at which the latch signal shown in FIG. 7 is input, and each of the analog switches 92 is turned on in response to the output of each of the AND gates 82, the control signal is supplied to each of the gate circuits marked 52. In this case, the time required to electrically provide or supply the control signal 102 i.e. make it active is set so as to be slightly shorter than that required to make active a gate signal GA of a gate signal generator 31 as shown in FIG. 7. When the input of any one of the AND gates 82 i.e. the signals output from the Q1 terminals of the latch circuits 21 arranged in pairs adjacent to each other are both "H" in level, the analog switch 92 electrically connected to the corresponding AND gate 82 is closed so as to supply the control signal 102 to the gate circuit 52. When, on the other hand, either one of the Q1 terminals of the adjacent latch circuits 21 or the two Q1 terminals are "L" in level, the analog switch 92 is turned off, so that the control signal 102 is not input to the corresponding gate circuit 52. Accordingly, the gate input of the gate circuit 52 is brought to a high impedance. FIG. 8 shows temperatures on the surfaces of the adjacent heating resistors at the time that the heating resistors have produced heat. Let's now assume that the adjacent heating resistors are represented as 7a, 7b, 7c as shown in FIG. 8(A). When the respective heating resistors 7a, 7b, 7c are selectively activated under a given condition, heat is generated by the heating resistor 7b but not produced by the remaining heating resistors 7a, 7c disposed adjacent to the heating resistor 7b, for example. In this case, the temperature of the generated heat is 250°C as shown in FIG. 8(B). When, on the other hand, the heat is generated by the adjacent heating resistors 7a, 7c, the temperature of the generated heat becomes 280°C as illustrated in FIG. 8(D). When the heat is generated by either one of the heating resistors 7a and 7c, the temperature of the generated heat reaches 265°C. Thus, a relative influence made by the heat generated from the adjacent heating resistors can be corrected to provide accurate printing by supplying the energy determined by the time required to make the control signal active to each of the heating resistors 7a, 7b, 7c, thereby making it possible to obtain a well-balanced density for printing under the high-level control of heat history. FIG. 9 is a circuit diagram showing a thermal head driving device according to an embodiment of the present invention. The thermal head driving device makes use of dual control signals 102 and 133 to control the time required to energize each heating resistor. In addition, the Q1 terminals of adjacent latch circuits 21 are electrically connected to corresponding AND gates 82 respectively, and the Q1 terminals of the other adjacent latch circuits 21 excluding the inherent or initial latch circuit 21 are electrically connected to respectively corresponding OR gates 113. In this condition, the control signals 102 and 133 are input to each of the gate circuits 52 via respectively corresponding analog switches 92 and 123 which are respectively opened and closed according to the output of the AND gate 82 and the output of the OR gate 113. The control signal 102 is input to each of the gate circuits 52 during a period in which each of the analog switches 92 is in the on state. Therefore, when an information pair relative to adjacent bits; of the recorded information on the present each line, are both "H" in level, the energization of each heating resistor is completed based on a width corresponding to a time interval, which is shorter than the normal maximum width, corresponding to the maximum time interval of a gate signal GA of a gate signal generating unit 31. The control signal 133 is input to each of the gate circuits 52 during a period in which each of the analog switches 123 is in an on state. Therefore, when either one of the pair of information based on the adjacent bits, of the recorded information on the present each line is "L" in level, each of the heating resistors 7 is energized based on the width shorter than that of the gate signal GA. It is therefore possible to realize a higher-level control of heat history compared with the previously described embodiment. FIG. 10 is a timing chart for describing the timing relationship between the time required to make the control signals 102 and 133 active, and the time required to make the gate signals GA, GB, GC of the gate signal generating unit 31 active. The signals 102 and 133 and the gate signal GA rise simultaneously but the time required to make the control signal 102, the control signal 133 and the gate signal GA active, takes place in the above order. That is, the time required to make the control signals 102 and 133 active, and the time required to make the gate signals GA, GB, GC active are respectively associated with 280°C, 265°C and 250°C each of which represents the temperature of the heat generated by each of the heating resistors 7 associated with the adjacent bits shown in FIG. 8. When the generated heat is high in temperature, each time referred to above is reduced. In the present embodiment, the time required to make each signal active is determined so as to be associated with 250°C or so. Accordingly, when the heat is generated by the heating resistors 7 associated with both bits adjacent to a corresponding bit relative to the remaining heating resistor 7 in the heating resistors 7 as shown in FIG. 8(D), the time required to energize each heating resistor 7 is determined by the control signal 102. When the heat is generated by the heating resistor 7 associated with one of the adjacent bits as shown in FIG. 8(C), the time required to energize each heating resistor 7 is decided by the control signal 133. When, on the other hand, the heat is not generated by the heating resistors 7 associated with both of the adjacent bits, the time required to energize each heating resistor 7 is determined by the gate signal GA of the gate signal generating unit 31. It is thus possible to perform the control for printing with a higher accuracy. FIG. 11 is a circuit diagram of a recording head driving circuit according to a further embodiment of the present invention. Even adjacent recorded information on each previous line i.e. from each Q2 terminal is input to each of gate circuits 52 as input information as well as adjacent recorded information on each present line. The recorded information on each present line is obtained from each of the first AND circuits 82a, and the past recorded information is obtained from each of second AND circuits 82b. Thus, the past adjacent recorded information is also fed back to the recorded information based on a corresponding bit at the present line, thereby controlling the energization of each heating resistor 7. In this case, the timing for making each of signals 102 and 134 active is similar to that shown in FIG. 10. The control signal 134 is based on the control signal 133. As a result, the printing density can be controlled with higher accuracy in the present embodiment, compared with the first embodiment. FIG. 12 is a circuit diagram showing a recording head driving circuit, in which normal three-state buffers 155 are used as an alternative to the analog switches 92. However, any switch similar to the analog switches 92 can be used. In this case, the present example of a head driving circuit can bring about the same advantageous effects as those obtained by the example shown in FIG. 6. In addition, the output of each present line i.e. each Q1 terminal, which is represented in the form of bits, is input to each of the AND gates 82. However, this process may be omitted. Furthermore, the first and final bits of the adjacent bits are suitably adjusted in number because the number of gates is insufficient. Further, logic circuits or the like may be used as an alternative to the three state buffers 155 and the analog switches 92. In each of the embodiments shown in FIGS. 9 and 11 analog switches 92 having three output states (on, off, high impedance) or three state buffers 155 are used. The gate circuits 52 introduce one of three states from corresponding analog switches 92 or three state buffers. However, outputs of the analog switches 92 or three state buffers 155 may be pulled up by pull-up resistors to stabilize the logic. In the above embodiments, the control signals 102, 133 and 134 are output independent of the gate signal generating unit 31. However, the respective control signals may be output from the gate signal generating unit 31. In the above embodiments, the thermal head driving circuit has been described. However, the embodiments can be applied to the control of an LED head serving as a recording head used with an LED light source, for example. Otherwise, the embodiments may also be used in the drive control of recording heads used for an ink-jet, a bubble jet, etc. Further, each of the above embodiments is directed to a case in which each of the latch circuits 21 is provided with the Q1, Q2, Q3 terminals as three stages. It may also be provided with more than three stage terminals. In the above embodiments, the reference to the adjacent bits on each previous line is made only with respect to the previous line. However, this reference may be made to further previous lines or after. In addition, this reference may be made to the bits adjacent to the corresponding bit.

Claims: A recording head driving device for a thermal printer comprising heating elements (7) energizable over a time interval, said device comprising: a plurality of gate circuits (52), each for outputting drive pulse signals for energizing a respective heating element (7); a plurality of latch circuits (21), each for storing print information (Q1, Q2, Q3) of the present line and previous lines for a respective heating element (7); a gate signal generating unit (31) for outputting gate signals (GA, GB, GC) to be gated with the print information (Q1, Q2, Q3) and supplied to said gate circuits (52), said driving device characterized by a plurality of AND gates (82), each associated with one heating element (7), the output of each AND gate (82) connected to gate a first control signal (102) to each respective said gate circuit (52), the first control signal (102) controlling the energizing time interval of the respective heating element (7), wherein each of said AND gates (82) receives the present print information (Q1) for its associated heating element (7) from its latch circuit (21) and the present print information for adjacent heating elements (7) from their latch circuits (21), and a plurality of OR gates (113), each associated with one heating element (7), for gating a second control signal (133) to each of said gate circuits (52), the second control signal (133) further controlling the energizing time interval, wherein each OR gate (113) receives the present print information (Q1) from the latch circuits (21) for adjacent heating elements (7) and receives no print information for its own heating element (7). The driving device of Claim 1, wherein said plurality of OR gates (113) is replaced by a plurality of second AND gates (82b), each associated with one heating element (7), for gating a third control signal (134) to each of said gate circuits (52) to control said energizing time interval, wherein each second AND gate (82b) receives the immediately previous print information (Q2) from the latch circuits (21) for adjacent heating elements (7) and receives no print information for its own heating element.

Inventors: ENDO TAKAFUMI C O MITSUBISHI D, ENDO, TAKAFUMI, C/O MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1992
Main classification: B41J2
IPC codes: B41J2