Digital video signal recording/playback apparatus

Abstract: An apparatus for recording/playback digital data with variable length codes which are encoded from intra-frame compression data and inter-frame compression data. The apparatus include a data rearranging circuit for rearranging the intra-frame compression data in the variable length encoded data and an address and a data length adding circuit for adding addresses and data length information of the intra-frame compression data output from the data rearrangement means. Furthermore, a device for setting an error flag in case of non-correctable errors is included, which generates zero data to replace erroneous encoded data. A second set of special video heads is provided for a variable speed replay. According to the error rate, either the signal derived from the ordinary heads or the signal from the special heads is processed by the decoder.

Description: The present invention relates generally to a digital signal recording/playback apparatus, and more particularly, to a variable length code recording in the digital signal recording/playback apparatus. A digital precessing of video data has been greatly developed in recent years. In particular, various systems for recording digital video data using a recording medium such as magnetic video cassette recorders (VCRs) have been developed. FIGURES 1(a) and 1(b) illustrate diagrams for explaining relations of the positions on a screen and the positions on the recording tracks of a recording medium in VCRs. FIGURE 1(a) indicates the positions on the screen and FIGURE 1(b) indicates the positions on the recording tracks. FIGURE 1(a) illustrates one frame of picture vertically divided into eight sections. FIGURE 1(b) indicates the record positions of the first through ninth tracks similarly divided into eight tracks. Video data are recorded in order on a recording medium starting from the lowest line position A of the first track to its top line position I, For instance, when recording one frame data on one track, data displayed in a horizontal section defined by lines a and b on a screen are recorded on a longitudinal section defined by lines A and B on a recording medium, and thereafter, in the similar manner data displayed in horizontal sections defined by lines b through i on the screen are recorded in the order on longitudinal sections defined by lines B through I on the recording medium. Further, for instance, when recording one frame data on two tracks, data in the horizontal section defined by the lines a and e on the screen are recorded on the longitudinal section defined by the lines A and I of the first track #1, while data in the horizontal section defined by the lines e and i on the screen are recorded on the longitudinal section defined by the lines E and I of the second track #2. FIGURES 2(a) through 2(d) are diagrams for illustrating the relationship between trace patterns and playback signal envelopes in data recording at a triple speed. FIGURE 2(a) illustrates trace patterns when playback data at triple speed with a head scanning time shown at the axis of abscissas and track pitch or tape traveling distance at the axis of coordinates. The signs "+" and "-" in the diagram indicate differentially oriented normal azimuths of the playback head, respectively. Further, numerals in the diagram show track numbers; thus odd number tracks are in the plus azimuth and even number tracks are in the minus azimuth. FIGURES 2(b) through 2(d) indicate the signal envelope played back by the ordinary head, the playback envelope by the special purpose head and the synthetic playback envelope obtained by both heads. FIGURE 3 is a diagram for illustrating the construction of the recording/playback heads. Now assumed that a rotary cylinder 3, as shown in FIGURE 3, is used for the data recording and playback operations. The rotary cylinder 3 is equipped with a pair of regular heads 1, 1 which have differentiated azimuths with each other and a pair of special purpose heads 2, 2 which have also differentiated azimuths with each other, and further the azimuths of one regular head 1 and its adjacent special purpose head 2 are also differentiated each other. As shown by the sign "+" in FIGURE 2(a), the first track and the third track are traced by the regular head 1 of the plus azimuth in the initial scanning period (tracing period), and the fourth track and the sixth track are traced by the regular head 1 of the minus azimuth in the next scanning period. Thus, the playback signal envelope shown in FIGURE 2(b) is obtained by the regular head 1. Further, the second track is traced by the special purpose head 2 in the initial scanning period and the playback signal envelope shown in FIGURE 2(c) is obtained in the same manner. By combining the playback output from the regular head 1 with the playback output from the special purpose head 2, the synthetic playback envelope shown in FIGURE 2(d) is obtained. Table 1 shown below indicates relations among the playback outputs at the triple speed playback operation (FIGURE 2(d)), the traces of head and the corresponding positions on the screen. Playback Track 1 Frame/1 Track 1 Frame/2 Tracks Track Frame Track Frame #1 1st Frame #1 1st Frame 1 (A) - (C) (a) - (c) (A) - (C) (a) - (c) #2 2nd Frame #2 1st Frame 2 (C) - (G) (c) - (g) (C) - (G) (f) - (h) #3 3rd Frame #3 2nd Frame 3 (G) - (I) (g) - (i) (G) - (I) (d) - (e) #4 4th Frame #4 2nd Frame 4 (A) - (C) (a) - (c) (A) - (C) (e) - (f) #5 5th Frame #5 3rd Frame 5 (C) - (G) (c) - (g) (C) - (G) (b) - (d) #6 6th Frame #6 3rd Frame 6 (G) - (I) (g) - (i) (G) - (I) (h) - (j) #7 7th Frame #7 4th Frame 7 (A) - (C) (a) - (c) (A) - (C) (a) - (b) #8 8th Frame #8 4th Frame 8 (C) - (G) (c) - (g) (C) - (G) (f) - (h) #9 9th Frame #9 5th Frame 9 (G) - (I) (g) - (i) (G) - (I) (a) - (b) As shown in FIGURE 2(d) and Table 1, data A through C on the first track #1 are played back by the regular head 1 in the first quarter (1/4) time interval in the initial scanning period, data of C through G on the second track #2 are played back by the special purpose head 2 in the next half (1/2) time interval, and data of G through I on the third track are played back by the regular head 1 in the next 1/4 time interval. Thereafter, data on three tracks are played back in the similar manner in one scanning period. When one frame video data are recorded on one track, the positions of A through C on the first track #1 correspond to the positions a through c on the first frame of image, the positions C through G on the second track #2 correspond to the positions c through g on the second frame of the frame, and the positions G through 1 on the third track #3 correspond to the positions g through i on the third frame of the image, as shown in Table 1. Therefore, in the playback operation at a triple speed, the picture patterns at the positions on the first through the third frames are combined and displayed as a playback picture. Further, when one frame video data are recorded on two tracks, the positions A through C on the first track #1 correspond to the positions a and b on the first frame, the positions C through G on the second track #2 correspond to the positions f through h on the first frame, and the positions G through I on the third track #3 correspond to the positions d through e on the second frame as shown in Table 1. Further, the positions A through C on the fourth track #4 correspond to the positions e and f on the second frame, the positions C through G on the fifth track #5 correspond to the positions b through d on the third frame, and the positions G through I on the sixth track #6 correspond to the positions h through i on the third frame. In this case, therefore, the picture patterns at the positions on the first through the third frames are presented in mix on the playback picture as shown in FIGURE 4(b). By the way, various proposals have been proposed in recent years for the standardization of high efficient encoding for compressing video data. The high efficient encoding technique is to encode video data at more lower bit rate for improving efficiency of digital transmission and recording. For instance, the CCITT (Cometi Consultafif international Telegraphique et Telephonique (International Telegraph and Telephone Consultative Committee)) has issued a recommendation for video-conference/video-telephone standardization H. 261. According to the CCITT recommendation, the encoding is made by using the frame I processed an intra-frame compression and the frame P processed an inter-frame compression (or a predictive frame compression). FIGURE 5 is a diagram for explaining the video data compression according to the CCITT recommendation. The frame I processed intra-frame compression is the one frame video data encoded by the DCT (Digital Cosine Transformation) processing. The inter-frame Compression processed frame P is the video data encoded by the predictive encoding method using the intra-frame compression processed frame I or the inter-frame compression processed frame P. In addition, more lowering of bit rate has been made by encoding these encoded data to the data encoded in variable length. As the intra-frame compression processed frame I was encoded by the intra-frame information only, it is possible to decode it by a single encoded data only. However, the inter-frame compression processed frame P was encoded using the correlation with other video data, it cannot be decoded by a single encoded data only. FIGURE 6 is a block diagram for illustrating the recording section of a conventional apparatus for recording/playback variable length codes using such the predictive encoding. A luminance signal Y and color difference signals Cr and Cb are applied to a multiplexer 11, where they are multiplexed in a block of 8 pixels x 8 horizontal scanning lines. Sampling rate of the color difference signals Cr and Cb in the horizontal direction is a half (1/2) of the luminance signal Y. Therefore, in the period when two 8 x 8 luminance blocks are sampled, one 8 x 8 block of the color difference signals Cr and Cb is sampled. As shown in FIGURES 7(a) through 7(c), two luminance signal blocks Y1 and Y2 and each of the color difference signal blocks Cr and Cb total, thus four blocks in total forms a macro block. Here, two luminance signal blocks Y1 and Y2 and each of the color difference blocks Cr and Cb represent the same position of the picture frame. The output of the multiplexer 11 is applied to a DCT (Digital Cosine Transformation) circuit 13 through a subtracter 12. When performing the intra-frame compression, a switch 14 is kept OFF and the output of the multiplexer 11 is applied directly to the DCT circuit 13 as described later. A signal composed of 8 x 8 pixels per block is applied to the DCT circuit 13. The DCT circuit 13 converts the input signal into frequency components by the 8 x 8 two dimensional DCT processing. This makes it possible to reduce the spatial correlative components. That is, the output of the DCT circuit 13 is applied to a quantizer 15 which lowers one block signal redundancy by requantizing the DCT output using a fixed quantization coefficient. Further, block pulses are supplied to the multiplexer 11, the DCT circuit 13, the quantizer 15, etc. which operate in block unit. The quantized data from the quantizer 15 is applied to a variable length encoder 16 and is, for instance encoded to the Huffman codes based on the result calculated from the statistical encoding amount of the quantized output. As a result, a short bit is assigned to data having a high appearance probability and a long bit to data having a low appearance probability and thus, transmission amount is further reduced. The output of the variable length encoder 16 is applied to an error correction encoder 17, which provides the output from the variable length encoder 16 with an error correction parity added to a multiplexer 19. The output of the variable length encoder 16 is also applied to an encoding controller 18. The amount of the output data varies largely depending on input picture. So, the encoding controller 18 monitors the amount of the output data from the variable length encoder 16 and regulates the amount of the output data by controlling the quantization coefficient of the quantizer 15. Further, the encoding controller 18 may restrict the amount of the output data by controlling the variable length encoder 16. A sync/ID generator 20 generates frame a sync signal and ID signal showing data contents and additional information and provides them to the multiplexer 19. The multiplexer 19 forms 1 sync block data with a sync signal, ID signal, compressed signal data and parity and provides this data to the recoding/encoder which is not shown. The recording/encoder, after recording/encoding the output from the multiplexer 19 according to characteristic of a recording medium, records the encoded data on a recording medium (not shown). If the switch 14 is ON, the current frame signal from the multiplexer 11 is subtracted from the motion compensated preceding frame, data which will be described later, in the subtracter 12 and applied to the DCT circuit 13. That is, in this case the inter-frame encoding is carried out to encode differential data using redundancy of inter-frame picture. When a difference between the preceding frame and the current frame is simply obtained in the inter-frame encoding, it will become large if there is any motion in the picture. So, a differential value is made small by compensating the motion by obtaining a difference at the pixel position corresponding to the motion vector while detecting the motion vector by obtaining the position of the preceding frame corresponding to the fixed position of the current frame. That is, the output of the quantizer 15 is also applied to an inverse quantizer 21. This quantized output is inverse-quantized in the inverse quantizer 21 and further, inverse DCT processed in an inverse DCT circuit 22 and restored to the original video signal. Further, the original information cannot be played back completely in the DCT processing, requantization, inverse quantization and inverse DCT processing and part of the information lacks. In this case, as the output of the subtracter is a differential information, the output of the inverse DCT circuit 22 is also a differential information. The output of the inverse DCT circuit 22 is applied to an adder 23. This output from the adder 23 is fed back through a variable delay circuit 24 which delays signal by about one frame period and a motion compensator 25, and the adder 23 restores the current frame data by adding differential data to the preceding frame data and provides them to the variable delay circuit 24. The preceding frame data from the variable delay circuit 24 and the current frame data from the multiplexer 11 are applied to a motion detector 26 where motion vector is detected. The motion detector 26 obtains motion vector through the full search motion detection by, for instance, a matching calculation. In the full search type motion detection, the current frame is divided into the fixed number of blocks and the search range of, for instance, 15 horizontal pixels x 8 vertical pixels are set for each block. In the search range corresponding to the preceding frame, the matching calculation is carried out for each block and an inter-pattern approximation is calculated. Then, by calculating the preceding frame block which provides the minimum distortion in the search range, the vector which is obtained by this block and the current frame block is detected as the motion vector. The motion detector 26 provides the motion vector thus obtained to the motion compensator 25. The motion compensator 25 extracts a corresponding block data from the variable delay circuit 24, corrects it according to the motion vector and provides it to the subtracter 12 through the switch 14 and also, to the adder 23 after making the time adjustment. Thus, the motion compensated preceding frame data is supplied from the motion compensator 25 to the subtracter 12 through the switch 14 and when the switch 14 is ON, the inter-frame compression mode results and if the switch 14 is OFF, the intra-frame compression mode results. The switch 14 is turned ON/OFF based on a motion judging signal. That is, the motion detector 26 generates the motion judging signal depending on whether the motion vector size is in excess of a fixed threshold value and outputs it to a logic circuit 27. The logic circuit 27 controls the ON/OFF of the switch 17 by the logical judgment using the motion judging signal and a refresh periodic signal. The refresh periodic signal is a signal showing the intra-frame compression processed frame I illustrated in FIGURE 5. If the input of the intra-frame compression processed frame I is indicated by the refresh periodic signal, the logic circuit 27 turns the switch 14 OFF irrespective of the motion judging signal. Further, if the motion judging signal indicates that the motion is relatively fast and the minimum distortion by the matching calculation exceeds the threshold value, the logic circuit 27 turns the switch 14 OFF and the intra-frame encoding is carried out for each block even when the inter-frame compression processed frame P data are input. Table 2 shown below indicates the ON/OFF control of the switch 14 by the logic circuit 27. Frame I Intra-Frame Compression Switch 14 OFF Processed Frame Frame P Motion Vector Detected Switch 14 ON Inter-Frame Compression Processed Frame Motion Vector Unknown Switch 14 OFF Inter-Frame Compression Processed Frame FIGURE 8 is a diagram for illustrating the data stream of record signals which are output from the multiplexer 19. As shown in FIGURE 8, the first and the sixth frames of the input video signal are converted to the intra-frames I1 and I6, respectively and the second through the fifth frames are converted to the inter-frame compression processed frames P1 through P5. The ratio of data amount between the intra-frame compression processed frame I and the inter-frame compression processed frame P is (3 - 10) : 1. The amount of data of the intra-frame compression processed frame I is relatively much while the amount of data of the inter-frame compression processed frame P is extremely reduced. Further, the data of the inter-frame compression processed frame P cannot be decoded unless other frame data are decoded. FIGURE 9 is a block diagram indicating the decoding section (playback section) of a conventional variable length code recorder. Compressed encoded data recorded on a recording medium is played back by the playback head which is not shown and applied into an error correction decoder 31. The error correction decoder 31 corrects errors produced in data transmission and recording. The playback data from the error correction decoder 31 are applied to a variable length data decoder 33 through a code buffer memory 32 and decoded to fixed length data. Further, the code buffer memory 32 may be omitted. The output from the variable length decoder 33 is inverse quantized in an inverse quantizer 34, inverse DCT processed and decoded to the original video signal in an inverse DCT circuit 35, and applied to the terminal a of a switch 36. The output of the variable length decoder 33 is also applied to a header signal extractor 37. The header signal extractor 37 retrieves a header showing whether the input data is the intra-frame compression data or the inter-frame compression data and provides it to the switch 36. When supplied with a header shown the intra-frame compression data, the switch 36 selects the terminal a and outputs decoded data from the inverse DCT circuit 35. The inter-frame compression data is obtained by adding the output from the inverse DCT circuit 35 and the preceding frame output from the predictive decoder 39 using an adder 38. That is, the output of the variable length decoder 33 is applied to a motion vector extractor 40 and the motion vector is thus obtained. This motion vector is applied to a predictive decoder 39. The decoded output from the switch 36 is delayed for one frame period by a frame memory 41. The predictive decoder 39 compensates the preceding frame decoded data from the frame memory 41 according to the motion vector and provides them to the adder 38. The adder 38 decodes the inter-frame compression data by adding the output from the predictive decoder 39 and the output from the inverse DCT circuit 35 and provides the decoded inter-frame compression data to the terminal b of the switch 36. When the inter-frame compression data is applied, the switch 36 selects the terminal b by the header and outputs the decoded data from the adder 38. Thus, the compression and expansion are carried out without delay. However, the intra-frame compression processed frame I and the inter-frame compression processed frame P differ in encoded amount and if the data stream shown in FIGURE 8 is recorded on a recording medium, one frame is not necessarily able to play back by the playback data in the playback operation at a triple speed. Further, the inter-frame compression processed frame P processed inter-frame compression will become not able to playback if any undecoded frame is generated as in the playback operation at a triple speed because it cannot be decoded for an independent frame. Thus, the conventional variable length code recorder described above has such a problem of that the picture quality of a picture played back in the special playback operation deteriorates extremely because each frame data is in variable length and some frame data of a single frame only cannot be decoded. Since data of every frame is in variable length and there are frame data which cannot be decoded only by a single frame as described above, picture quality is deteriorated extremely in special playback operation. However, even in this case it s possible on a VCR which adopted a high efficiency encoding process to play back encoded data to some extent while suppressing error propagation by synchronizing signal, etc. However, if there are data which are not transmitted in such cases as video-conference, video-telephone, etc. where high efficiency encoded signals are applied to, for instance, TV set, errors are extensively propagated relatively and quality of displayed images is extremely deteriorated. This problem will be described in reference to FIGURE 10, FIGURE 11 and FIGURES 12((a) through 12(f). FIGURE 10 is a diagram for explaining a broadcasting system adopted for video-conference, video-telephone, etc. In a broadcasting station, video signals from cameras (not shown) are high efficiency encoded in an encoder 151 and added with an error correction code in an error correction encoder 152 corresponding to a transmission line 154. A transmission modulator 153 modulates the output from the error correction encoder 152 corresponding to the transmission line 154 and then, provides it to the transmission line 154 after converting into electric waves. At the receiving section, signals being applied through the transmission line 154 are demodulated in a receiving demodulator 155. An error corrector 156 corrects errors generated in the transmission line 154 and feeds them to a switch 157 and also to a VCR 158. The VCR 158 records the input signals or plays back the signals and feeds them to the switch 157. The switch 157 is switched by an input switching signal based on user operation and selecting the output of the error corrector 156 or that of the VCR 158, provides it to a decoder 159. The decoder 159 decodes the high efficiency encoded signals to original signals and an error corrector 160 corrects errors remaining in the decoded output without being corrected and provides them to a monitor TV set (not shown). Thus, the broadcasting signals applied through the transmission line 154 or playback signals from the VCR 158 are displayed on the screen of the monitor TV set. FIGURE 11 is a block diagram for illustrating the construction of a VCR which is capable of high efficiency encoding and decoding. Further, the VCR shown in FIGURE 10 is in the same construction as the right to the broken line in FIGURE 11. Video signals are high efficiency encoded in an encoder 161 and then applied to an error correction encoder 162. The error correction encoder 162 provides the encoded data with an error correction parity code adapted to a VCR added to an adder 163. The adder 163 adds a synchronizing signal and ID signal generated in an ID generator 164 to the output of the error correction encoder 162 and provides the output to a recording/modulator 165. The recording/modulator 165 modulates this output to adapt to the recording by a recording medium and provides it to a recording amplifier 166. This recording amplifier 166 amplifies the modulated signals and feeds them to a magnetic head 167 for recording on a tape 168. In a playback operation of recorded signals, the tape 168 is traced by the magnetic head 167 to play back recorded signals and the playback signals are supplied to a playback amplifier 169. The playback signals from the playback amplifier 169 are waveform equalized in a waveform equalizer 170 to reduce inter-code interference and then applied to a synchronizer 171. The synchronizer 171 restores the playback data in unit of recorded data train and feeds them to a demodulator 172. The demodulator 172 demodulates the playback data and feeds them to an error corrector 173. The error corrector 173 corrects errors in the playback data and provides to a decoder 174. The decoder 174 and an error corrector 175 are in the construction identical to those of the decoder 159 and the error corrector 160 shown in FIGURE 10, and decodes the output of the error corrector 173 and after correcting errors, outputs the error corrected output. Now, it is assumed that the switch 157 shown in FIGURE 10 selects the VCR 158. Data transmitted from a broadcasting station via the transmission line 154 are supplied to the VCR 158. Data transmitted from a broadcasting station via the transmission line 154 are supplied to the error corrector 156. Thus, the recording data train shown in FIGURE 12(a) is applied to the VCR 158. In this drawing, the subscript n denoted track number and the subscript m denotes recorded data train number. That is, Gn, m denote the mth data train on the nth track. If the data train Gn,1 through Gn, m is recorded in the VCR 158 and this data train is played back without error, the reencoded data train will become identical to the playback data train in the normal playback operation as shown in FIGURE 12(b). However, data is played back by the magnetic head while crossing the tracks in the playback operation at triple speed as described above and therefore, the playback data does not agree with the recorded data. That is, as shown in FIGURE 12(c), the k0 data train through the k1 data train are played back on the first track, the k2 through k3 data trains are played back on the second track, and the k4 through k5 data trains are played back on the third track. The VCR 158 carries out the demodulation, error correction and decoding processes of this playback data. However, as data decoding processes of this playback data. However, as data may not be played back correctly at such portions where the recording tracks are switched and furthermore, the playback data trains become discontinuous at switching points of the recording tracks, data around the track switching points cannot be used for decoding. Further, in the VCR 158, video data are recorded with a synchronizing signal and ID signal added and demodulated in unit of synchronizing signal in the synchronizer 171 when played back and therefore, if data are not played back in the middle of a synchronizing block, it is possible to demodulate data from the start position of next synchronizing block. Thus, the portion shown by the broken line in FIGURE 12(d) of playback data by one scanning in the triple speed playback operation is not output against FIGURE 12(c). However, even if header and address are added to data, a monitor TV set is not able to reconstruct images using these data and simply displays images in order of input image data. As data trains being transmitted are variable length encoded data trains, even when data length of the broken lined part shown in FIGURE 12(d) is known, it is not possible to identify the start position of next data train k2's. Accordingly, it is not possible to display playback images using all playback outputs from the VCR 158 on the screen of a monitor TV set and information data are not used effectively even when and error flag is added to them. That is, in such a system as video-telephone, which decodes input data trains continuously, if data are interrupted, subsequent data cannot be used efficiently. So, in order to stop error propagation, decoding may be enabled for a fixed period of the top of a track by specifying the top of the track as the start position of a data train as shown in FIGURE 12(e). This will make it possible to decode a data train G1, KO' through G1, K1'. Further, FIGURE 12(f) illustrates an example where the data position with a Δ mark was set as the data train start position. In this case, the data train G1, 11 through G1, 12 can be decoded. As described above, there is also such a problem so far that if discontinuous data were transmitted, data available for effective use in playback operation of images decreases extremely. A playback signal processing method which is capable of special playback operation using the above special playback heads is shown in FIGURE 13. In this drawing, a signal played back by a playback head 210 is amplified in an amplifier 211 and supplied to a detector 250 and a switch 223. Similarly, a signal played back by a special purpose head 216 is amplified in an amplifier 17 and supplied to a detector 251 and the switch 223. In the detectors 250 and 251, envelop constituents of respective signals are detected and provide them to an amplitude comparator 252. In the amplitude comparator 252, amplitudes of these two signals are compared and the result is supplied to a switch 253. A switching signal is also supplied to the switch 253 and either one of these signals is selected by a mode selecting signal and supplied to the switch 223 as a control signal. The switch 223 selects one of the outputs from the amplifiers 211 and 217 according to this control signal and supplies to a demodulator 224 where the output signal is demodulated. This demodulated signal is restored to the original image signal in a playback processor 254. The switching signal described above is used to select a preset head output signal and if this signal is selected by the switch 253, the outputs from the amplifiers 211 and 217 are selected alternately. In the amplitude comparator 252, a signal in larger amplitude normally selected. Therefore, if the output of the amplitude comparator 252 is selected by the mode selecting signal in the switch 253, the output in larger amplitude of those outputs from the amplifiers 211 and 217 is selected in the switch 223. FIGURE 14 illustrates trace patterns in the playback operation at triple speed. In this drawing, although the tracks are aslant on a tape, the trace of the head is vertical to the traveling direction of a tape because of triple speed. Therefore, the trace of the head extends over the tracks b, c and d. However, because the azimuth angles of the tracks b and c differ from those of the tracks c and d, data on Trace 1 is played back by selecting data played back, for instance, by the playback heads from S to A out of Trace 1, by the special purpose heads from A to B and by the playback heads from B to E. If analog signals are played back in this way, an image without noise bar is obtainable on a screen. However, as data are recorded on a tape in block unit when they are digitally processed, if signals played back from two heads are switched according to the amplitude or at a preset switching point, the signals may be switched in the middle of a block. In this case, because data of the block makes no sense, invalid data was produced before or after the switching. This state is shown in FIGURES 15(a) and 15(b). FIGURE 15(a) indicates data played back by the playback head and FIGURE 15(B) is data played back by the special purpose head. "SY", "ID", "D" and "PA" indicate synchronizing signal, ID signal, data and parity signal, respectively. And, from "SY" through "PA" form one block. Here assuming that the switching points are set at the points A and B, signals are switched in the middle of data D. If the switching point is A, signals are synchronized as the positions of both "SY" are in accord with each other but data is invalid because the tracks are different. So, the portion of a in (a) and the portion of b in FIGURE 15(b) become invalid data. If the switching point is B, signals are not synchronized as both of two "SY" are out of position. As described above, if the switching point is preset or set according to the amplitude, invalid data was produced before and after the switching point and in addition, signals could not be synchronized is some cases. When a recorded video tape is played back in a VTR at triple speed, the trace of the head is made crossing three tracks on a magnetic tape. To prevent azimuth angles from becoming different or noise bars from being generated on a screen, special playback heads were provided adjacent to ordinary playback heads and recorded data were played back by switching signals played back by the respective playback heads. However, when recorded data were digitally processed, if the switching point was preset or set according to the signal amplitude, invalid data were produced before or after the switching point and furthermore, signals could not be synchronized in some cases. EP-A-0424026 discloses a video signal transmitting system having many of the features of the prior art system discussed above. According to the present invention, there is provided an apparatus for playing back digital video data with variable length codes which are encoded from intra-frame compression data and inter-frame compression data, comprising: a decoding means including an error detecting means for detecting errors in high efficiency encoded data comprising address information multiplexed on an encoded data for each block; a zero data generating means for generating zero data in block units with an error flag added; a switching means for selectively outputting the decoded data or the output from the zero data generating means; a control means for controlling the switching means to replace a decoded data block containing an error with an output from the zero data generating means by detecting an error block address from the detected result of the error detecting means; and an additional data inserting means for inserting additional data between a block of zero data and the next error-free block of decoded data in order to maintain an output data rate of the switching means constant. This has the effect of improving an image which is played back. For a better understanding of the present invention and many of the attendant advantages thereof, reference will now be made by way of example to the accompanying drawings, wherein: Figures 1(a) and 1(b) are diagrams for explaining the contrast of the positions on the frame with the positions on a recording medium in a conventional example; Figures 2(a) through 2(d) are diagrams for illustrating the relationship between the trace pattern and the playback envelope at triple speed playback; Figure 3 is a diagram for illustrating the construction of the recording/playback head; Figures 4(a) and 4(b) are diagrams for explaining the construction of the playback frame in a conventional example; Figure 5 is a diagram for explaining the compression method according to H. 261 recommendation; Figure 6 is a block diagram for illustrating the recording side of conventional variable length code recorder adopting the predictive encoding; Figure 7 is a diagram for explaining the macro block; Figure 8 is a diagram for illustrating the data stream of recorded signals in the recorder shown in Figure 6; Figure 9 is a block diagram for illustrating the decoding side (playback side) of a conventional variable length code recorder; Figure 10 is a block diagram for explaining the problem according to a conventional example; Figure 11 is a block diagram for explaining the problem according to a conventional example; Figure 12(a) through 12(f) are diagrams for explaining the problem according to a conventional example; Figure 13 is a block diagram for illustrating the conventional construction; Figure 14 is a diagram for explaining the relation between tracks and trace of the head; Figures 15(a) and 15(b) are diagrams for explaining the construction of compression encoded image data; Figure 16 is a block diagram for illustrating an embodiment of the encoding section of the apparatus of the present invention; Figure 17 is a block diagram for illustrating an embodiment of the decoding section of the apparatus of the present invention; Figures 18(a) through 18(c) are diagrams for explaining the embodiment of Figure 16; and Figures 19(a) through 19(c) are diagrams for explaining the operation of the apparatus according to the embodiment of Figure 17. An embodiment of the present invention will be described hereinafter with reference to Figures 16 through 19. Figure 16 is a block diagram showing the encoding section of the transmission apparatus according to the present invention. Further, Figure 17 is a block diagram showing the decoding section of the present invention. In Figures 16 and 17, the component parts identical to those in Figure 11 are assigned with the same letters or symbols. These aspects of the embodiment are applied to a recording/playback apparatus. In Figure 16, received video signals input through the transmission line 180 are input to the receiving demodulator 181. The received video signals are transmitted sequentially in the unit of frame, each frame is divided into such small blocks as 8 pixels in the horizontal direction x 8 pixels in the vertical direction and a top flag is added to the top of the frame. Further, each block data is encoded by DCT process, etc. The receiving demodulator 181 demodulates received video signals and provides them to the format converter 182 and the address generator 183. The multiplexer 184 multiplexes the outputs from the address generator 183 with the format converter 182. Figures 18(a) through 18(c) are diagrams for illustrating the format converter 182, the address generator 183, the multiplexer 184 and the error correction encoder 162. Image data for one frame from the transmission line 180 is affixed with a top flag showing the top of the frame as illustrated in Figure 18(a) and thereafter, the image data consists of multiple block data of block 1, 2, .... The address generator 183 assigns a series of frame numbers or headers to the top flag and generating such address data as Block (B) 1, 2, .... to each block 1, 2, ...., then provides them to the multiplexer 184. The format converter 182 converts the received image data format so that address data is arranged at the top of each block data and provides it to the multiplexer 184. The multiplexer 184 adds address data to the top of each block data and provides a data stream illustrated in Figure 18(b) to the error correction encoder. Further, to improve data playback efficiency, the format converter 182 may change playback data sequence. The error correction encoder 162 adds a parity signal P fitted for recording to the output from the multiplexer 184 and provides it to the adder 163. The synchronization/ID generator 164 generates a synchronizing signal and an ID signal and provides them to the adder 163. The adder 163 outputs the output of the error correction encoder 162 with a synchronizing signal S added. Finally, from the adder 163, a data stream with the synchronizing signal S added to the top of frame number and the parity signal P and the synchronizing signal S added to the middle of the data stream as shown in Figure 18(c) is output. The output of the adder 163 is fed to the recording/modulator 165. The recording/modulator 165 modulates the output of the adder 163 to fit for recording and provides it to the recording amplifier 166. The recording amplifier 166 amplifies the modulated signal from the recording/modulator 165 and feeds it to the magnetic head 167 for recording on the magnetic tape 168. At the decoding section, the data recorded on the magnetic tape 168 is played back by the magnetic head 167 as shown in Figure 17. The playback signals from the magnetic head 167 are supplied to the playback amplifier 169. The playback amplifier 169 amplifies the playback signals and feeds them to the waveform equalizer 170. The waveform equalizer 170 equalizes the waveforms of the playback signals to remove inter-code interference and enable to identify data and provides them to the synchronizer 171. The synchronizer 171 extracts signals and ID signals and gives playback data in the unit of synchronizing signal to the demodulator 172. The demodulator 172 demodulates playback data and feeds them to the error corrector 193. The error corrector 193 corrects errors in the playback data and provides the playback data to the delay circuit 185 and at the same time, adds an error flag to data which could not be corrected. Further, the error corrector 193 generates an error flag and address data of the decoded data to the zero data generation controller 186. The zero data generation controller 186 generates address data of a block having errors (error block) from the error flag and address data and provides them to the switches 187 and 188 and at the same time, controls the delay circuit 185. Further, if an address data error is indicated by an error flag, the zero data generation controller 186 generates address data by estimating an address from address data before and after the address data with the error. The output of the error flagged zero data generator 189 is supplied to the terminal "a" of the switch 187 and data length adjusting bit source 190 is supplied to the terminal "b". The error flagged zero data generator 189 generates and provides zero data with a flag (F) added to show that there is no redundant bit or data which is ignored in the course of decoding in the block unit. The data length adjusting bit source 190 provides adjusting bits to make a block having errors continuous with blocks having no error. The switch 187 selects the terminal "a" or "b" under the control of the output from the zero data generation controller 186 and supplies this output to the terminal "b" of the switch 188. To the terminal "a" of the switch 188, the output of the delay circuit 185 is supplied. The delay circuit 185 adjusts a timing with the output of the switch 187 by delaying the output of the error corrector 193 under the control of the zero generation controller 186. The switch 188 selects the terminal "a" or "b" under the control of the zero data generator 186 and directly outputs the output of the delay circuit 185 for a block having no error, and outputs the output of the switch 187 in place of the output of the delay circuit 185 for a block having an error. Next, the operation of the thus composed apparatus according to this embodiment is described referring to the diagrams in Figures 19(a) through 19(c). Figure 19(a) shows composite data for one scanning of the head in the playback operation at triple speed, Figure 19(b) shows the output of the switch 188, and Figure 19(c) shows the output of the error flagged zero data generator 189. In this drawing, the portion between G1, k1' and G2, k2' and the portion between G2, k3' and G3, k4' shown by the broken line, respectively show data not able to be restored, unusable data because of many errors contained or unusable data because no synchronizing signal is played back. At the recording section, the receiving demodulator 181 demodulates data input through the transmission line 180 and provides the demodulated data to the format converter 182 and the address generator 183. Received data is added with a frame number at the top of frame data by the format converter 182, the address generator 183 and the multiplexer 184 and is also added with address data for each block and supplied to the error correction encoder 162. The received data is added with a parity signal P by the error correction encoded 162 and furthermore, added with a synchronizing signal S and ID signal by the adder 163 and supplied to the recording modulator 165. The recording modulator 165 modulates the output from the adder 163 to fit for recording and feeds it to the magnetic head 167 through the recording amplifier 166 for recording on the magnetic tape 168. At the playback section, playback data illustrated in Figure 19(a) is obtained from the magnetic head 167 when played back at triple speed. This playback data is supplied to the waveform equalizer 170 for waveform equalization through the playback amplifier 169, synchronizing signals are detected by the synchronizer 171 and demodulated in the unit of synchronizing signal in the demodulator 172. The demodulated output is supplied to the delay circuit 185 after the error correction in the error corrector 193. The error corrector 183 adds an error flag to the portion shown by the broken line in Figure 19 (a), that is, the block G1, (k1 + 1)' through G2, (k2 - 1)' and the block G2, (k3 + 1)' through G3, (k4 - 1)' and provides these address data to the zero data generation controller 186. The zero data generation controller 186 decides delay amount of the delay circuit 185 from the error flag and address data and at the same time, controls the switches 187 and 188. The switch 187 provides zero data for each block (Figure 19(c)) from the error flagged zero data generator 189 to the terminal "b" of the switch 188 at a timing of an error block and then, provides a data length adjusting bit to the terminal "b" of the switch 188 for making this zero data continuous with the adjacent blocks having no errors. The output of the delay circuit 185 is supplied to the terminal "a" of the switch 188. The switch 188 selects the terminal "a" or "b" under the control of the zero data generation controller 186. Thus, the switch 188 selects the delay circuit 185 for the period corresponding to the blocks G1, k0' through G1, k1' illustrated in Figure 19(a) and outputs the demodulated output of playback data directly, while it selects the output of the switch 187 for the period corresponding to the blocks G1, k1' through G2, k2' and outputs the error flagged zero data blocks G1, (k1 + 1) through G2, (k2 - 1)' and furthermore, outputs a data length adjusting bit (oblique lined section) for adjusting recording data by making this zero data block and block G2, k2' continuous. Then, the switch 188 selects the output of the delay circuit 185 for the period corresponding to the blocks G2, k2' through G2, k3'. Then the switch 188, selecting the terminal "b", outputs the zero data blocks G2, (k3 + 1)' through G3, (k4 - 1)' and a data length adjusting bit shown by the oblique line. The switch 188 then selects the output of the delay circuit 185 for the period corresponding to the next blocks G3, k4' through G3, k5'. Thus, error flagged zero data is inserted into the unplayed back portions shown by the broken line in Figure 19(a) and continuous sequential data are output from the switch 188. As described above, in this invention, at the encoding section of this transmission apparatus, data is added with an address and at the decoding section, an error flag and its address data is generated by the error corrector 193. Even when data which became discontinuous because of lacking data are supplied, the error block is replaced with an error flagged zero data based on the error block address data and sequential data with continuous addresses added are output. Therefore, if the output of the switch 188 is supplied to an apparatus which plays back images sequentially in order of input image data, the zero data portion corresponding to the error block only is not played back but all other data are able to play back and it is possible to minimize error propagation. This will result in improvement of quality of playback images.

Claims: An apparatus for playing back digital video data with variable length codes which are encoded from intra-frame compression data and inter-frame compression data, comprising: a decoding means (172) including an error detecting means for detecting errors in high efficiency encoded data comprising address information multiplexed on an encoded data for each block; a zero data generating means (189) for generating zero data in block units with an error flag added; a switching means (188) for selectively outputting the decoded data or the output from the zero data generating means; a control means (186) for controlling the switching means to replace a decoded data block containing an error with an output from the zero data generating means by detecting an error block address from the detected result of the error detecting means; and an additional data inserting means (190, 187) for inserting additional data between a block of zero data and the next error-free block of decoded data in order to maintain an output data rate of the switching means constant.

Inventors: SHIMODA KENJI, SHIMODA, KENJI, SHIMODA, KENJI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: H04N5
IPC codes: H04N7, G11B15, H04N5, H04N9