Electronic circuit package

Abstract: An electronic circuit package having a wiring substrate (10), at least two semiconductor chips (101-106) and a bus line (100). All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

Description: The present invention relates to miniaturization of electronic circuit package and which may be usefull for an extra-small computer for use in space exploration. A number of computers are being employed for various uses and a demand for smaller and lighter computers is also increased. Computers for use in space are required to be particularly smaller and lighter in order to decrease launching cost while increasing the payload. As shown by a photograph 1 of "Development of LSI for Radiation Resistant 16-Bit Microprocessor", pp 10 - 411, Goke et al, Collection of Papers at 32nd Space Science and Technology Federation Lecture Meeting, a space computer is built of, for instance, discrete parts with reliable, resistant-to-environment single chips contained in one package. There is no serious consideration to decrease the size and weight in the computer as comprises the discrete parts. On the other hand, a so-called multiple chip mounting technique, that is, the technique of mounting a plurality of bare chips on one wiring substrate for use on the ground is being studied. It has heretofore been arranged that, as shown in Fig. 3 of "Nikkei Micro Device", pp 32 - 40, December Issue, 1989, a wiring conductor to be connected to a bonding pad is led out of the bonding pad. It was left out of consideration to make wiring density uniform in this technique. The wiring density around the die bonding pad in particular is made extremely high and consequently effective wiring cannot be implemented. The wiring density m the outermost layer thus causes a bottleneck and the package size is not sufficiently reduced. As the via hole connecting the upper and lower layers occupied most of the area on the particular multilayer wiring substrate, the via holes account for a large percentage of area on the outermost layer, particularly around the die bonding pad. With respect to a fault tolerant system, a checking unit for detecting errors and faults and a unit under check are accommodated in one and the same chip to reduce the size as described in "Trial Manufacture and Evaluation of Fault Tolerant Quartz Oscillation IC", by Tsuchimura et al, Research Material, 24th FTC Study Meeting. With the diffusion of ASICs (Application Specified ICs) in particular, attempts have been made to add an MPU inspection circuit by making an ordinary MPU a core through the ASIC technology. Faults and trouble affecting the whole chip were not taken into consideration in this technique. When the checking unit and the unit under check develop trouble simultaneously, the irregularity might not be detected. EP-A-0 279 996 disclosed an electronic circuit packing having the features a - g of claim 1. Summary of the Invention An object of the present invention is to provide a small and light electronic circuit package, with high reliability. According to the present invention, all semiconductor chips to be stantially connected by means of a bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. There is provided an electronic circuit packing as defined in claim 1. Embodiments of the present invention are expressed in the dependent claims 2-5. Preferably, the semiconductor chips include a checking unit and a unit under check. Moreover, as each semiconductor chip is subjected to bare chip packaging, a fault of one chip does not influence other chips. As lead-out lines can be formed from wiring bonding pads and via holes even under the die bonding ground, according to the present invention, the wiring density in the neighborhood of the wire bonding pads is prevented from centering therearound. Therefore, the wiring density in each wiring layer is uniformized to the extent that they are effectively utilizable. As a result, the package becomes small. Although the semiconductor element often causes transistor (gate)-based trouble in many cases, the trouble may involve the whole element (chip). In the case of the trouble involving the whole chip, the electronic apparatus comprising the checking unit and the unit under check is unable to detect the trouble, thus making the addition of the checking unit meaningless. Even when the checking unit and the unit under check are constructed of different packages, it will be essential for the checking signal lines to be provided between the checking signal lines. This will increase the size of the electronic apparatus. Consequently, the checking unit and the unit under check are separately provided in respective chips on the same wiring substrate on a bare chip basis. The wiring substrate and the bare chips are connected by wire bonding into a single package. The omission of a fault involving over the whole chip is thus prevented and furthermore, a small, light-weight electronic apparatus can be made available. Brief Description of the Drawings These and other objects, features and advantages of the present invention will be understood more clearly from the following detailed description with reference to the accompanying drawings, wherein Fig. 1 is a sectional view of a die bonding portion of a wiring substrate according to the present invention; Fig. 2 is a diagram showing an arrangement of via holes in an embodiment of the present invention; Fig. 3 is a structural view of an MPU with checking circuit and an RAM with an error correction code on a wiring substrate in an example which is not a part of the present invention; Fig. 1 is a sectional view of a die bonding portion of the wiring substrate according to the present invention. Wire bonding pads 11 are formed on the wiring substrate 10 and an insulating layer 16 is formed on a wiring conductor 14 for use in leading out the wire bonding pad. A die bonding ground 15 is formed on the insulating layer 16 and a semiconductor chip 20 is bonded thereto by die bonding. A bonding wire 30 is then used for connecting between a wire bonding pad 21 on the semiconductor chip 20 and the wire bonding pad 11 on the wiring substrate 10. According to this embodiment, as shown in Fig. 2, via holes 13, 13' may be formed in the periphery and inside of the die bonding ground 15, respectively. Said via hole 13 formed in the periphery of said die bonding ground 15 and said wire hole 13' formed inside of said die bonding ground 15 are preferably arranged alternately. As a result, a portion beneath the die bonding ground 15 as the outermost layer that has heretofore been unutilized may be put to practical use as a wiring and a via hole region. An area to be occupied by wiring and via hole regions can thus be made drastically smaller than what is occupied by the semiconductor chip of the wiring substrate. According to the embodiment shown in Figs. 1 and 2, it is also possible to package as many bare chips as possible on the wiring substrate limited in size. Fig. 3 refers to an example which is not part of the claimed invention wherein MPU 101, a checking circuit 111 of the MPU 101, and RAM 102, an error correction code encoding/decoding circuit 112 are packaged in the form of bare chips on the wiring substrate 10. In this case, a bonding wire has been omitted for simplification. MPU 101 and the checking circuit 111 are different bare chips and connected by wire bonding on the wiring substrate 10. Heretofore, various systems have been proposed as the checking circuit 111. There are the following, for instance: (1) A watch dog timer for resetting MPU 101 after sensing its operation on impulse when it is unaccessible within a fixed period of time. (2) A system having a reference MPU (not shown) within the checking circuit 111 and while comparing the output signal of the reference MPU with that of MPU 101, regards the reference MPU or MPU 101 as irregular once nonconformity is found and so on. In the conventional method of packaging MPU 101 and the checking circuit 111 separately, the number of packages, the number of wires and dimensions of the electronic apparatus tend to increase. In the method recently followed for forming the MPU 101 and the checking circuit 111 on the same chip, moreover, a fault involving the whole chip is not completely detectable as even the checking circuit 111 ceases to function then. According to this embodiment, MPU 101 with the checking circuit 111 capable of detecting a fault involving the whole chip is provided without causing the number of packages and that of wires to increase. Therefore, a small lightweight, reliable electronic apparatus can be provided. RAM 102 and the error correction code encoding/decoding circuit 112 are different bare chips and connected by wire bonding on the wiring substrate 10. The error correction code adds an error detection/correction redundant bit to the data stored in the memory, thus causing an error to be detected and corrected by making a code-to-code Hamming distance 4 or greater. When the code-to-code Hamming distance is set to 4, 1-bit error correction is possible, but a 2-bit error remains only detectable. Consequently, it is called SECDED (Single-Error-Correction, Double-Error Detection). For instance, a 6-bit detection/correction redundant bit needs adding when SECDED is meant to be realized concerning 16-bit data. A detailed description of an error correction code will be omitted since the present invention is not aimed to provide the error correction code. In the conventional method of packaging RAM 102 and the error correction code encoding/decoding circuit 112 separately, the number of packages, the number of wires and dimensions of the electronic apparatus tend to increase. In the method recently followed for forming the RAM 102 and the error correction code encoding/decoding circuit 112 on the same chip, moreover, a fault involving the whole chip is not completely detectable as even the error correction code encoding/decoding circuit 112 ceases to function then. According to this embodiment, RAM 102 with error correction code encoding/decoding circuit 112 capable of detecting a fault involving the whole chip is provided without causing the number of packages and that of wires to increase. Therefore, a small lightweight, reliable electronic apparatus can be provided. Like other semiconductor elements, the storage element (ROM) storing the program involved is packaged on the same wiring substrate in the form of a bare chip and if it is incorporated into the same package, the electronic apparatus may be made drastically smaller and lighter. If ROM is incorporated into the package, it will require to devise programming and its erasing methods. Use of EEPROM (Electrically Erasable Programmable ROM) will make programming readily possible and make the program erasable. Even when UVEPROM (Ultra-Violet Erasable Progammable ROM) is used, the program may be executed or erased by providing the apparatus with a window which allows erasing ultra-violet rays which pass therethrough. When EPROM is used as a space electronic apparatus to be exposed to cosmic rays, the data written by means of the cosmic ray may be erased. Moreover, EPROM is not fit for use as an electronic apparatus to be used over several hundred thousand years as the electronic thermal movement Therefore, mask- or fuse-ROMs will have to be used for the purpose described above.

Claims: An electronic circuit package comprising: a) a multilayer wiring substrate (10) having a surface; b) an insulating layer (16) and wiring conductors in contact with wiring pads (11) on said surface; c) said wiring conductors comprises additional wiring conductors (14) which extend beneath said insulating layer; d) first via holes (13) within said wiring substrate (10), said first via holes being below and in direct contact with said wiring conductors, said first via holes being positioned along and at the exterior of the periphery of said insulating layer, e) a die bonding ground (15) on said insulating layer; f) a semiconductor chip (20) mounted on said die bonding ground, said semiconductor chip having wire bonding pads (21) thereon; g) wire bonds (30) forming connections between said wire bonding pads and said wiring pads; characterized in that h) second via holes (13') which are in direct connection with said additional wiring conductors, said second via holes are positioned along and within the periphery of said semiconductor chip; and i) said first and second via holes are alternately arranged. An electronic circuit package according to claim 1, wherein said semiconductor chip (20) includes a microprocessing unit (101, 102) or a checking unit (111) for detecting errors and faults of said microprocessing unit. An electronic circuit package according to claim 2, wherein said semiconductor chip (20) includes a random access memory (102) or an error correction code unit (112) for detecting errors of said random access memory and for correcting said errors. An electronic circuit package according to claim 3, wherein one of said checking unit (111) and said error correction code unit (112) is included in a gate array (110). An electronic circuit package according to 1-3, wherein said semiconductor chip (20) includes a gate array (110).

Inventors: AKIYAMA MASATSUGU, IHARA HIROKAZU, KANEKAWA NOBUYASU, KAWABATA KIYOSHI, OKISHIMA TETSUYA, YAMANAKA HISAYOSHI, AKIYAMA, MASATSUGU, IHARA, HIROKAZU, KANEKAWA, NOBUYASU, KAWABATA, KIYOSHI, OKISHIMA, TETSUYA, YAMANAKA, HISAYOSHI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1992
Main classification: H01L23
IPC codes: G06F11, H01L23, H01L25, G06F1, G06F3, G06F15, G06F12