Image processing apparatus and method

Abstract: Disclosed is an image processing apparatus where plural line memories (6-10) store first image information corresponding to a first recording density based on input image data for plural lines, and a logical circuit included in a decision circuit (15, 16) determines a pixel data to be interpolated corresponding to the pixel position of second image information when the first image information is converted to the second image information in accordance with the stored first image information for plural lines. A logical circuit also included in the decision circuit detects a predetermined pattern in accordance with the stored image information for plural lines when the pixel data to be interpolated is determined, calculates a logical expressions for predetermined pattern diffusing processing, and determines a value of the pixel to be interpolated to diffuse the predetermined pattern in the second image information. With the above structure image information for a lower recording density is converted to information for a higher recording density, where half-tone images in high quality can be obtained.

Description: The present invention relates to an image processing apparatus and method for converting image data to be outputted to a recording device such as a laser-beam printer, and more particularly, to an image processing apparatus and method for converting the dot density of input image data when the dot density of the input image data is different from the recording dot density of a printer engine. In recent years, a laser-beam printer is widely used as output device of a computer. Especially, a lower-density (e.g., 300 dpi) laser-beam printer is rapidly becoming popular with the merits such as compact size and low cost. As shown in Fig. 1, a laser-beam printer for 300 dpi (dot per inch) recording density consists of a printer engine 51 and a printer controller 52. The printer controller 52, connected to the printer engine 51, receives a code data from a host computer 54, makes page information consisting of dot data in accordance with the code data and sends the dot data to the printer engine 51 in sequence. The printer engine 51 forms an electrostatic latent image on an electrostatic drum in accordance with the dot data. The latent image is transferred to a recording paper. The host computer 54 loads an application program from a floppy disk 55 having the application program, The application program is then started, the host computer acts as, e.g., a word processor. Since various application programs are nowadays produced, a user is able to make a lot of data and preserve them using these application programs. On the other hand, a printer engine has been improved for the purpose of higher printing quality. Printer engines adapted to a recording density of 600 dpi or more than 600 dpi have been provided. A printer controller connected to such high-density printer engine has a data memory having a capacity corresponding to its recording density (for example, a printer connected to a printer engine for 600 dpi recording density has a memory capacity four times as large as 300 dpi). Since most application programs are produced for printers having a lower recording density, they can not be used for printers with a higher recording density. For example, Figs. 2 and 3 respectively show the dot pattern of letters "G" and "t" for 300 dpi recording density . If these letters are recorded in 600 dpi recording density, the size of these letters is halved in both length and in width. By adopting a known data interpolation method to the above case, the pattern data for 300 dpi can be converted to a dot pattern for 600 dpi, where the length and width of the pattern data for 300 dpi are simply doubled and applied as a pattern data for 600 dpi structure. This method avoids diminishing the size of letters (Figs. 4 and 5). However, after the pattern conversion, the jagged edges of the outline portion of the letters remains the same as the jagged edges in Figs. 2 and 3. This means that it is impossible to take advantage of the high quality 600 dpi printer engine. Another data interpolation method is known as the smoothing technique, where the jagged edges of image data are detected and smoothed. This technique can improve the quality of the image data of characters and figures having at least two continuous dots. However, the technique can not obtain the same effect when recording picture images processed by the dither method, error diffusion method and the like. Generally, in an image data processed in a half-tone processing method such as the Dither method and the error diffusion method, in light portions, a black dot whose size is smaller than one dot (300 dpi for 300 dpi printer engine) can not be printed, and a white dot smaller than one dot can not be printed in dark portions. Consequently, the printed image quality of the light portions and the dark portions is lower than that of.the neutral density portions. Fig. 6 shows an example of a fattening type gray scale pattern. Fig. 7 shows an example of a light portion of a half-tone image printed using the gray scale pattern, and Fig. 8, an example of a dark portion of a half-tone image printed using the same. In these examples, isolated dots are expressed as scattered specks, and even if those dots are printed in higher recording density, the size of the smallest speck is the same as the size of a dot in 300 dpi. Therefore, this method can not improve the quality of printed half-tone images. EP-A-0356224 describes an image processing apparatus wherein smoothing means are provided to smooth jagged edge portions by interpolating pixel data when first image data is converted into second image data of higher resolution or recording density than the first image data. According to one aspect of the present invention, there is provided an image processing apparatus in accordance with claim 1. The present invention also provides an image processing method in accordance with claim 11. An embodiment of the present invention provides an image processing apparatus and method capable of the high-quality recording of picture images expressed by half-tone processing method, as well as smoothed images of characters and figures, when image data for lower recording density is converted for higher recording density. More particularly, an embodiment of the present invention improves the gradation of image data by detecting a predetermined pattern scattered in a pattern data of lower recording density (e.g. 300 dpi) and diffusing them in the dot pattern of higher recording density (e.g. 600 dpi). Other advantages besides those discussed above shall be apparent to those skilled in the art from the description of a preferred embodiment of the invention which follows. In the description, reference is made to the accompanying drawings, which form a part thereof, and which illustrate an example of the invention. Such example, however, is not exhaustive of the various embodiments of the invention, and therefore reference is made to the claims which follow the description for determining the scope of the invention. Fig. 1 is a block diagram showing a conventional image recording system; Fig. 2 is a diagram showing a conventional dot pattern of a letter "G" for recording density of 300 dpi; Fig. 3 is a diagram showing a conventional dot pattern of a letter "t" for recording density of 300 dpi; Fig. 4 is a diagram showing a dot pattern of the letter "G" in Fig. 2 for recording density of 600 dpi converted with a conventional data interpolation method; Fig. 5 is a diagram showing a dot pattern of the letter "t" in Fig. 3 for recording density of 600 dpi converted with a conventional data interpolation method; Fig. 6 is a diagram showing an example of a conventional fattening type gray scale pattern; Fig. 7 is a diagram showing a printed example of a light portion of a half-tone image processed in a conventional data interpolation method using the fattening type gray scale pattern in Fig. 6; Fig. 8 is a diagram showing a printed example of a dark portion of a half-tone image processed in a conventional data interpolation method using the fattening type gray scale pattern in Fig. 6; Fig. 9 is a block diagram showing the construction of a data conversion circuit in an image recording apparatus according to the first embodiment of the present invention; Fig. 10 is a timing chart for describing the operations of signals in the data conversion circuit shown in Fig. 9; Fig. 11 is a block diagram showing the construction of a decision circuit of the first embodiment; Fig. 12A is a diagram showing the relation between an object pixel and peripheral pixels in a case of interpolation in a main scanning direction; Fig. 12B shows a logical expression which determines a value of an object pixel, when SEL (logical selection signal) = 0 in the case of interpolation in the main scanning direction; Fig. 12C shows a logical expression which determines a value of an object pixel, when SEL = 1 holds in a case of the main scanning direction; Fig. 13A is a diagram showing the relation between an object pixel and peripheral pixels in a case of interpolation in a sub scanning direction; Fig. 13B shows logical expression which determines a value of an object pixel in a case of the interpolation in the sub scanning direction; Fig. 14A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 14B shows a logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 14A; Fig. 15A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 15B shows a logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 15A; Fig. 16A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 16B shows a logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 16A; Fig. 17A and 17B are diagrams showing an example of the smoothing result; Fig. 18A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 18B shows a logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 18A; Fig. 19A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 19B shows logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 19A; Fig. 20A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 20B shows a logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 20A; Fig. 21A is a diagram showing an example of the state where a jagged edge portion is detected in smoothing processing; Fig. 21B shows logical expression which determines a value of an object pixel corresponding to the interpolation in Fig. 21A; Fig. 22A and 22B are diagrams showing an example of the smoothing result; Fig. 23 is a diagram showing an example where the dot pattern for recording density o 300 dpi in Fig. 2 is interpolated and converted for recording density of 600 dpi in the present invention; Fig. 24 is a diagram showing an example where the dot pattern for recording density of 300 dpi in Fig. 3 is interpolated for recording density of 600 dpi in the present invention; Fig. 25 is a diagram describing an arrangement of dots according to the first embodiment; Figs. 26 to 29 show logical operations according to the second embodiment; Fig. 30 is a block diagram showing the construction of an image recording apparatus according to the third embodiment of the present invention; Fig. 31 is a block diagram showing in detail the construction of a decision circuit in Fig. 30; Fig. 32 is a diagram showing the relation between an object pixel and peripheral pixels in a case of interpolation in the main scanning direction; Figs. 33 to 38 show logical operations according to the third embodiment; and Fig. 39 is a diagram showing an arrangement of dots according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. [First Embodiment] In the first embodiment, described is an image recording apparatus having a data conversion circuit shown in Fig. 9 for dot conversion inserted between the printer controller 52 and the printer engine 51 (Fig. 1). Since the data conversion circuit is illustrated as a part of the printer engine 51 in this embodiment, it can be also a part of the printer controller 52. In this embodiment, the printer controller 52 sends an image signal for the recording density of 300 dpi, while the recording density of the printer engine 51 is 600 dpi. The data conversion circuit converts the resolution of the image signal so as to match the recording density of the printer engine 51. The printer engine 51 includes a laser driver which modulates a laser beam in accordance with the image signal (dot information), a scanner for scanning the beam and an electrostatic drum, as known to those skilled in the art. The printer controller 52 sends an image signal VDO for the recording density of 300 dpi and an image clock VCLK to the data conversion circuit in response to a horizontal synchronous signal HSYNC supplied from a horizontal synchronous signal generator 4 in the data conversion circuit. The horizontal synchronous signal generator 4 sends the horizontal synchronous signal in accordance with a well-known BD (beam detection) signal output by the printer engine 51 as a synchronous signal in a main scanning direction. The printer engine 51 receives a laser driving signal LD for recording density of 600 dpi from the data conversion circuit, the LD signal is made from the image signal VDO for recording density of 300 dpi and the image clock VCLK, and the printer engine 51 records an image in recording density of 600 dpi. Fig. 9 is a block diagram which shows the construction of the data conversion circuit according to the first embodiment of the present invention. In Fig. 9, a frequency doubler 1 doubles the frequency of the image clock VCLK and obtains a clock VCLK' having the doubled frequency as that of VCLK. An oscillator 5 generates a clock LCLK whose frequency is quadruple of that of the image clock VCLK. A demultiplexer 2 selects one of line memories 6 to 10 and supplies the image signal VDO to the selected line memory. The horizontal synchronous signal generator 4 counts the BD signals and outputs one horizontal synchronous signal per two BD signals. A device controller 3 controls the line memories 6 to 10 per line in accordance with the BD signal. More specifically, the device controller 3 directs one of the line memories to write the image signal VDO in synchronizing with the clock VCLK', while the device controller 3 directs the other four line memories to read out the image signal synchronically with the clock LCLK. During the writing operation to one of the line memories, the reading out operation from the other four line memories is performed twice . The device controller 3 alternatively carries out the writing and reading out operations as follows. When the writing operation is performed to the line memory 6, the reading out operation is performed to the line memories 7 to 10. At the next timing, the writing operation is performed to the line memory 7 and the reading out operation is performed to the line memories 8, 9, 10 and 6. At the next timing, the image signal VDO is written into the line memory 8, while the contents of the line memories 9, 10, 6 and 7 are read out. Each of the line memories 6 to 10 has a capacity for image data corresponding to recording density of 600 dpi in a main scanning direction, twice as large as that for image data of 300 dpi in the main scanning direction. As the writing operation into each line memory is synchronized with the clock VCLK' having the doubled frequency of the image clock VCLK, dot information of 300 dpi is doubled in the main scanning direction and written into these line memories. The dot information of 300 dpi can be stored in the line memories as dot information of 600 dpi. Each of signals D1 to D5 is a read out signal from each of the line memories 6 to 10 respectively. A selector 13 selects four signals of the read out signals D1 to D5 which are read from line memories under reading operation, and divides them into predetermined outputs DS1 to DS4. A four bit demultiplexer 14 alternatively outputs the output signals DS1 to DS4 from the selector 13 to a decision circuits 15 or 16 (DCT 15 or 16) at every BD signal. the decision circuits 15 and 16 compare the input image data for four lines (DS1 to DS4) and output signals Q1 or Q2 based on the comparison result. A line memory 11 stores the signal Q1 and a line memory 12 stores the signal Q2. The memory capacity of the line memories 11 and 12 is the same as that of the line memories 6 to 10. The clock LCLK is used in the writing and reading out operations of the line memories 11 and 12. A selector 17 selects an output signal D6 read out of the line memory 11 or an output signal D7 read out of the line memory 12, and outputs the selected signal as the laser driving signal LD. The device controller 3 also controls the writing and reading out operations at the line memories 11 and 12, the selecting operation to the demultiplexers 2 and 14, and the selectors 13 and 17. The decision circuits 15 and 16 receives a logical selection signal SEL. The logical selection signal can be utilized, for example, in the structure where the host computer 54 sets the SEL signal in accordance with the type of image data to change over logics for data interpolation. The operations in the structure in Fig. 9 will be described with reference to the timing chart shown in Fig. 10. As described above, when the demultiplexer 2 selects the line memory 6, the writing operation is performed at the line memory 6. While an image signal VDO for one line is written into the line memory 6 in synchronizing with the clock VCLK', the image signals for each one line stored in the line memories 7 to 10 are read out twice, synchronically with the clock LCLK. In this case, each of the output signals DS1 to DS4 is D5, D4, D3 and D2 in turn. The first output signals DS1 to DS4 from the selector 13 are input into the decision circuit 15 via the demultiplexer 14, and the data Q1 is written into the line memory 11 after a predetermined processing time. The writing and reading out operations to the line memories 11 and 12 are performed alternately. When the writing operation is carried out to the line memory 11, the reading out operation is performed at the line memory 12. The selector 17 outputs the data D7 read out of the line memory 12 as the laser driving signal LD. On the other hand, when the second reading out operation is performed to the line memories 7 to 10, the data DS1 to DS4 are input into the decision circuit 16 via the demultiplexer 14, and after a predetermined processing time, the data Q2 is written into the line memory 12. The selector 17 outputs the data D6 read out of the line memory 11 as the laser driving signal LD. Fig. 11 is a block diagram showing the structure of the decision circuit 15 (16) in the first embodiment. In Fig. 11, seven bit shift registers 18 to 21 receive the input signals DS1 to DS4. A logical circuit 22 (23) receives the data output from the shift registers 18 to 21 and carries out a logical operation. More specifically, the logical circuit 22 (23) receives each output from the shift registers 18 to 21, and after a predetermined processing, outputs as the output signal Q1 (Q2). The processings at the decision circuits 15 and 16 are different and are described below. Figs. 12A to 12 C and Figs. 13A and 13B show the logical operations at the logical circuit 22 (23) according to the first embodiment. As shown in Figs. 12B and 12C, when the SEL signal input into the logical circuit 22 (23) is "0", <logical expression 1> (Fig. 12B) is selected for the decision circuit 15, and when the SEL signal is "1", <logical expression 2> (Fig. 12C) is selected for the decision circuit 15. In this embodiment, the logical expressions for the logical circuit 23 in the decision circuit 16 are given in Fig. 13B. The logical expression in Fig. 13B has no relation with the SEL signal. In the decision circuit 15, when SEL = 0 holds, a jagged edge portion of the image data is detected and an interpolation data to smooth the jagged edge portion is generated. The interpolation operation in the case where SEL = 0 holds will be described below. Fig. 12A illustrates the positional relation between an object pixel and peripheral pixels. The reference numerals of each pixel (1A, 1B, ...4G) correspond to those in the <logical expression 1> in Fig. 12B. Figs. 12A and 12B are correlated as the reference pixels and the corresponding logical expression in the interpolation of the data of an object pixel. Each of the pixels has a value of "1" or "0". The pixel with a value "1" is a black pixel, and the pixel with a value "0" is a white pixel. In Figs. 13A and 13B indicate the same correlation as in Figs. 12A and 12B. In the decision circuit 16, an output signal Q is set in accordance with the logical expression in Fig. 13B and an interpolation data in the sub scanning direction is generated, which means the pixel between the lines (the pixel corresponds to the position between 2D and 3D) of an image data for recording density of 300 dpi is interpolated. In the decision circuit 15, the data of 3D is newly set in accordance with the <logical expression 1> in Fig. 12B and thus an interpolation data in the main scanning direction is generated. The logic for the interpolation of jagged edge portions in a sideward direction will be described below. In Fig. 14A, if 2G and 3B to 3F are recording information indicating black pixels ("1") and 2A indicates a white pixel ("0"), the image data is determined as a pattern with a jagged edge portion and an object pixel Q is decided to be black for the smoothing of the jagged edge. The logical expression corresponding to this processing is given in Fig. 14B. Similarly, in Figs. 15A and 16A, a jagged edge portion is detected and the object pixel Q is determined to be black. The corresponding logical expressions are given in Figs. 15B and 16B. The jagged edge portion in an image for recording density of 300 dpi as shown in Fig. 17A can be smoothed as shown in Fig. 17B, with the combination of the above logical expressions. Regarding jagged edge portions symmetric along with the main scanning direction and the sub scanning direction, the logical expressions for the interpolation of the jagged edge portions in the sideward direction can be obtained by combining the similar logical expressions. Next, the logic for the interpolation of jagged edge potions in the vertical direction (the sub scanning direction) will be described below. In Fig 18A, if 4C and 1E to 3E are recording information indicating black pixels ("1") and 1C is a white pixel ("0"), it is determined that there is a jagged edge portion in the image and the object pixel 3D is determined to be black for the interpolation of the jagged edge. The corresponding logical expression is given in Fig. 18B. In Figs. 19A and 20A, data interpolation is carried out in the similar manner, and the corresponding logical expressions are given in Figs. 19B and 20B. Regarding jagged edge portions symmetric along with the main scanning direction and the sub scanning direction, interpolation of the jagged edge portions in the vertical direction can be performed by combination of the similar logical expressions. Next, the interpolation in the main scanning direction will be described. In Fig. 21A, the line including a pixel 3D is to be interpolated. When a jagged edge portion in the vertical direction is detected, the object pixel is determined to be black ("1"). As shown in Fig. 21A, if 4C, 2E and 3E are indicating black pixels ("1") and 2C is a white pixel ("0"), it is determined that there is a jagged edge portion in the vertical direction, and the object pixel data 3D is determined to be black ("1"). The corresponding logical expression is given in Fig 21B. These logics can be applied to jagged edge portions symmetric along with the main scanning direction and the sub scanning direction. Note that in case the 3D data is initially depicted to be "black", it can be kept "black". Thus jagged edge portions of a image in the dot pattern for recording density of 300 dpi as shown in Fig. 22A can be smoothed as in Fig. 22B by the combination of the aforementioned logics. The <logical expression 1> in Fig. 12B and the logical expression in Fig. 13B include all the above logics. As shown in Figs. 23 and 24, the jagged edge portions of the letters "G" and "t" in Figs. 2 and 3 can be smoothed with the interpolation based on the <logical expression 1> and the logical expression in Fig. 13B, which makes use of the characteristic advantage of the dot pattern of 600 dpi. According to the first embodiment, interpolation dot information in the main scanning direction and the information in the sub scanning direction are generated in accordance with the information of peripheral dots of a dot to be interpolated. The recording density of the interpolation dot information is higher than that of the input image data in a fixed ratio. The printer engine having a corresponding recording density records the image in accordance with the interpolation dot information. Even when application programs for lower recording densities are used, the dot information developed for the lower recording density can be converted to the dot information for higher recording density with a small memory, thus images of high quality recorded with a higher density can be obtained. Next, when SEL = "1" holds, the logical expressions when SEL = "0" holds is logically ORed with a logical expression for diffusion of isolated black dots. The ORed <logical expression 2> is given in Fig. 12C. When SEL = "1" holds, the logic for smoothing can be applied to an image data having continuous dots such as a character and figure. In images processed with halftone processing such as Dither method and error diffusion method, isolated dots are also detected and diffused in the dot pattern for higher recording density (600 dpi). In Fig. 12C, logical expressions for removing isolated dots is added to an expression when SEL = "0" holds. For example, when the dot pattern (shown in Fig. 7) of an image processed with the Dither method for recording density of 300 dpi is converted to the dot pattern for recording density of 600 dpi using the above logical expression. In Fig. 25, isolated dots having dot size of 300 dpi can be divided into small dots of 600 dpi and diffused. As the isolated dots in the light portions of a half-tone image are minimized and diffused, the image quality of the light portions can be improved. In accordance with a kind of image data described below, the logical selection signal SEL may be set to change over the interpolation logics. In case where the image data such as character or figure does not include a pixel data expressed in only one dot, the SEL signal is set to "1" so that the smoothing for graphic patterns and figures and the dot diffusion for images processed with half-tone processing such as the Dither method are carried out. In case where the image data such as character or figure includes a pixel data expressed in only one dot, only the smoothing for graphic patterns and figures is carried out and the dot diffusion for half-tone image is not carried out. [Second embodiment] Figs. 26 to 29 show logical operations according to the second embodiment. In the second embodiment, the logical expression when SEL = 1 holds in the first embodiment is modified. In this case, logics for detection of isolated white dots and for diffusion of the isolated white dots are logically ORed to the logical expression of the first embodiment. Accordingly, isolated white dots (300 dpi) in a dark portion of Dither pattern as shown in Fig. 8 can be minimized and diffused in the dot pattern of 600 dpi, thus the image quality in the dark portions of half-tone image can be improved. [Third Embodiment] Fig. 30 is a block diagram which shows the structure of an image recording apparatus according to the third embodiment of the present invention. Fig. 31 is a block diagram which shows the structure of a decision circuit according to the third embodiment. In Fig. 30, like reference numerals designate corresponding parts in the structure of Fig. 9, therefore explanations will be omitted. Each of decision circuits 115 and 116 according to the third embodiment has a counter 151 which receives the clock signal LCLK (Figs. 30 and 31) and controls outputs α, β in order of α = 0, β = 0 → α = 1, β = 0 → α = 0, β = 1 → α = 1, β = 1, every N-time count of the clock signal LCLK. The predetermined number N is selected, e.g., as N = 8. In this case, the outputs α, β are changed in line with the above cycle, every eighth count of the LCLK signals. Shift registers 118 to 121 function similarly to the shift registers 18 to 21 in Fig. 11. Logical circuits 122 and 123 are based on the third embodiment. The logical expressions for the logical circuit 122 (123) are given in Figs. 33 to 38. Fig. 32 illustrates the relation between an object pixel and peripheral pixels, and Figs. 33 to 38 showing corresponding logical expressions are correlated with Fig. 32, similarly to the first embodiment. Figs. 33 to 38 show logical expressions based on the third embodiment, and Fig. 39 illustrates the distribution of dots according to the third embodiment. The logical expressions in the third embodiment are modifications of the logical expression in Figs. 12B and 12C. When SEL = 0 holds, the same logical expressions as <logical expression 1> are selected (Fig. 33), and when SEL = 1 holds, <logical expressions 2> are selected (Figs. 34 to 38). When SEL = 1 holds, the logical circuit 122 (123) ORs a smoothed data such as a text image and figure with a data where isolated black dots are diffused. At the diffusion of isolated black dots, as values of outputs α, β are changed, e.g., every the eighth clock signal LCLK count, the logical expressions for the diffusion are changed as γ1 → γ2 → γ3 → γ4 → in accordance with the values of α, β. The corresponding logical expressions are given in Figs. 35 to 38. According to the third embodiment, the regular distribution of the diffused dots in the first embodiment (Fig. 25) can be more irregular and inconspicuous (Fig. 39), which further improves the image quality. In addition, the diffusion of isolated white dots in the second embodiment can be improved in the third embodiment. The counter 51 may be reset with the BD signal indicating the start of main scanning. Further, an image recording apparatus for the present invention is not limited to a laser-beam printer which is employed in the above embodiments. Each of isolated dots detected in the present invention is not limited to a dot size of 300 dpi and a couple of dots of 300 dpi may be detected as an isolated dot. As described above, the present invention enables recording where data of graphic characters and figures are expressed smoothly, and enables improvement of image quality in images processed by half-tone processings such as Dither method. The present invention may be applied to a system constituted by a plurality of apparatus or to a single apparatus. Further, it goes without saying that the invention is applicable also to a case where a program for implementing the invention is supplied to a system or apparatus. The present invention is not limited to the above embodiments and various changes and modifications can be made within the scope of the present invention. Therefore, to apprise the public of the scope of the present invention, the following claims are made.

Claims: An image processing apparatus comprising: memory means (6 to 10) for storing first image information corresponding to a first recording density; pixel interpolation means (15,16) for, when said first image information is to be converted to second image information corresponding to a second recording density higher than said first recording density, determining a pixel data to be interpolated corresponding to the pixel position of said second image information, in accordance with said first image information stored by said memory means; and smoothing means (15,16) for, when said pixel interpolation means determines that pixel data is to be interpolated, detecting a jagged edge portion in accordance with said first image information stored by said memory means and for, when said pixel data to be interpolated is determined, determining a value of said pixel data to be interpolated to smooth said jagged edge portion, characterised by further comprising: predetermined pattern diffusion means (15,16) for, when said pixel interpolation means determines pixel data to be interpolated, detecting predetermined pattern data in accordance with said first image information stored by said memory means (6 to 10) and for, when said predetermined pattern is detected, determining a value of said pixel data to be interpolated so that the predetermined pattern data is diffused in said second image information. An apparatus according to claim 1, further comprising expanding/compressing means (1,5) for expanding or compressing said first image information in a main scanning direction corresponding to said second recording density, said memory means (6,7,8,9,10) being arranged to store the image information expanded or compressed by said expanding/compressing means. An apparatus according to claim 1 or 2, wherein said pixel interpolation means (15,16) is arranged to determine a pixel data to be interpolated corresponding to the pixel position of said second image information by carrying out predetermined logical operations on said first image information for plural lines stored by said memory means, with the logical operation for a main scanning direction being different from a logical operation for a sub scanning direction. An apparatus according to claim 1, 2 or 3, wherein said memory means (6,7,8,9,10) includes plural line memories for storing image information, the number of plural line memories being more than said pixel interpolation means needs to execute interpolation, arranged so that while image information are simultaneously read out from several of said plural line memories, the next image data is written into a line memory of the rest of said plural line memories. An apparatus according to claim 1, 2, 3 or 4, wherein said predetermined pattern diffusion means (15,16) is arranged to detect said predetermined pattern data by carrying out a predetermined logical operation on image information for plural lines stored by said memory means, and when said predetermined pattern data is detected, to determine a value of said pixel data to be interpolated so as to diffuse said predetermined pattern. An apparatus according to claim 5, wherein said predetermined pattern diffusion means (15,16) is arranged to determine logical expressions in a predetermined order and to carry out said predetermined logical operation in accordance with a selected one of the logical expressions. An apparatus according to claim 6, further comprising count means (51) for counting the number of pixels interpolated by said pixel interpolation means, said predetermined pattern diffusion means (15,16) being arranged to change over said logical expression to another logical expression when the counting value of said count means reaches at a predetermined value. An apparatus according to any one of the preceding claims, further comprising selection means for selecting either a first mode in which both said predetermined pattern diffusion means (15,16) and said smoothing means (15,16) are activated or a second mode in which only said smoothing means (15,16) is activated. An image processing apparatus according to any one of the preceding claims, further comprising output means (17) for outputting said second image information generated by said pixel interpolation means (15,16), and either or both of said predetermined pattern diffusion (15,16) and smoothing means to a printer engine. A printer comprising an image processing apparatus in accordance with any one of the preceding claims. An image processing method comprising the steps of: storing first image information corresponding to a first recording density; determining a pixel data to be interpolated corresponding to the pixel position of a second image information when said first image information is to be converted to a second image information corresponding to a second recording density higher than said first recording density, in accordance with said stored first image; and detecting a jagged edge portion in accordance with said stored first image information when said pixel data to be interpolated is determined, and determining a value of said pixel data to be interpolated so that said jagged edge portion can be smoothed when said jagged edge portion is detected; characterised by: detecting a predetermined pattern in accordance with said stored first image information when said pixel data to be interpolated is determined in said pixel interpolating step, and determining a value of said pixel data to be interpolated so that the predetermined pattern data can be diffused in said second image information when said predetermined pattern is detected. A method according to claim 11, further comprising expanding or compressing said first image information in a main scanning direction corresponding to said second recording density and storing the expanded or compressed image information. A method according to claim 11 or 12, which comprises determining a pixel data to be interpolated corresponding to the pixel position of said second image information by carrying out predetermined logical operations on plural stored lines of first image information, and carrying out a logical operation in a main scanning direction different from a logical operation in a sub scanning direction. A method according to claim 11, 12 or 13, which comprises detecting said predetermined pattern data by carrying out a predetermined logical operation on plural stored lines of image information and, when said predetermined pattern data is detected, determining a value of said pixel data to be interpolated so as to diffuse said predetermined pattern. A method according to claim 14, which comprises determining logical expressions in a predetermined order and carrying out said predetermined logical operation in accordance with a selected one of the logical expressions. A method according to claim 15, further comprising counting the number of interpolated pixels and changing over said logical expression to another logical expression when the count value reaches a predetermined value. A method according to any one of claims 11 to 16, further comprising selecting either a first mode in which both said predetermined pattern diffusion and smoothing are activated or a second mode in which only smoothing is activated.

Inventors: KASHIHARA ATSUSHI, SETO KAORU, KASHIHARA, ATSUSHI, SETO, KAORU, KASHIHARA, ATSUSHI, C/O CANON KABUSHIKI KAISHA, SETO, KAORU, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N1
IPC codes: G06T3, G06K15