Apparatus and method for data check in storage system

Abstract: In an apparatus and method for data checking in a storage system such as a disk array system which includes a plurality of storage devices, the write data have error detecting codes for a host device thereof checked and stored in a register unit (46), the write data are divided, error detecting codes for the storage devices are generated, the write data are written in the storage devices and are simultaneously transferred through paths used for the read data, the write data are combined into host data, error detecting codes for the host device are generated, and the generated codes are compared with the codes stored in the register unit (46) so as to check whether they correspond to each other. Alternatively, the read data have error detecting codes for the storage devices thereof checked and stored in a register unit (47), the read data are combined into host data to be transferred to the host device, the combined data is transferred through the paths used for the write data, the data are divided into storage device data, error detecting codes for the storage devices are generated, and the generated codes are compared with the codes stored in the register unit (47) so as to check whether they correspond to each other.

Description: The present invention relates to an apparatus and method for data check for a storage system, e.g., a disk array system which is provided with a plurality of magnetic disk drives and which operates these magnetic disk drives in parallel and which allows data to be simultaneously input to these magnetic disk drives and to be output therefrom. There is recently a tendency to demand, in a computer system, a transfer of large amounts of data at high speed, and therefore, an auxiliary storage system is also required to transfer large amounts of data at high speed to exchange data with a host device. To meet this requirement, the auxiliary storage system, e.g., magnetic disk array system, has been developed, which is mainly constituted from a plurality of storage devices such as several units of magnetic disk drives and which enables plural bytes of data to be transferred in parallel between the host device and the storage devices. Here, the conventional magnetic disk array system, which is representative of the storage system, will be explained more specifically. In general, in a single unit of a magnetic disk drive, data transfer speed is limited by a rotation speed of a motor which rotates a magnetic disk as a recording medium. Accordingly, it it is intended to attain high speed operation by increasing a data transfer speed, it is necessary to perform write/read operations in parallel by driving a plurality of disk drives simultaneously. At this time, according to a command from a host device, the spindle motors of the magnetic disk drives connected in parallel with the host device are synchronously rotated, so that it becomes possible to perform a parallel transfer of data. Such a construction is called a disk array system, or a disk array device. Further, in addition to the data transfer at high speed, fault tolerance of the whole system is also required for such a disk array system so that sufficient reliability for the large amounts of data can be ensured without decreasing the data transfer speed. To attain such a fault tolerant system, even though a failure, such as the inability to read data from one disk drive of a plurality of disk drives, has occurred, it is necessary for the disk array system to be constructed so that the data of the failed disk drive can be reconstructed immediately without stopping operation of the whole disk array system. Some kinds of disk array systems in practical use, in which the above-mentioned data transfer at high speed and the fault tolerance can be satisfied simultaneously, have begun to be announced by various computer manufacturers as the products of disk array system called RAID (Redundant Arrays of Inexpensive Disks) 1 to RAID 5. Among these RAIDs 1 - 5, RAID 3, which is especially adequate for the case where large amounts of data have to be processed continuously at high speed, e.g., scientific calculations, will be described in more detail. In the RAID 3, the disk array system typically includes a plurality of disk drives for data transfer (for example, eight (8) disk drives) and a disk drive for parity checking, all these disk drives operating in parallel simultaneously. In this case, some given parity data corresponding to the parallel data of the respective disk drives for data transfer are previously stored in the disk drive for parity checking (parity disk drive). In such a construction, even though one disk drive of a plurality of disk drives fails so that the data cannot be read out, the data can be reconstructed by reading the parity data from the parity disk drive. Further, in the RAID 3, a spare storage disk drive is also provided. All the data in the failed disk drive is automatically reconstructed and transferred into the spare storage disk drive. If the reconstruction process is completed, the spare storage device can be utilized as a normal disk drive, in cooperation with the other disk drives for data transfer. In this manner, the disk array system as represented by the RAID 3, which enables large amounts of data to be transferred at relatively high speed (for example, 36M Bytes/sec) and has substantially fault tolerant characteristics, can be prepared. Further, when such large amounts of data are actually transferred into a plurality of disk drives in parallel and are written therein simultaneously, it is necessary to examine whether or not all the written data are correct, so that the reliability of the above-mentioned large amounts of written data can be ensured as highly as that of small amounts of data. In this case, it is desirable that some measures for confirming the write data in a simple manner and in a relatively short time should be taken, in order to maintain the data reliability without remarkably decreasing data transfer speed. As a typical one of these measures, a method of adding an error detecting code such as CRC (cyclic redundancy check) data, for each data block of a certain byte length, is in pratical use. Hereinafter, a conventional apparatus and method for data checking executed by adding CRC data will be described with reference to Figs. 1 to 3, so that a process of data checking for a disk array system will be understood more clearly. Figs. 1 to 3 are block diagrams for explaining a process of data checking according to a prior art. To be more specific, Fig. 1 is a block diagram of a disk array system, Fig. 2 is a block diagram for explaining a CRC adding process, and Fig. 3 is a block diagram of a data path control circuit. In these figures, 31 denotes a host computer (HOST), 32 a disk array system, 33 a disk controller, 34 storage devices (e.g., magnetic disk drives), and 35 a data path control circuit. Especially, in Fig. 3, 36, 37, 44 and 45 denote register units, respectively, and 38 denotes a host CRC checker, 39 a host CRC generator, 40 a write data converter, 41 a device CRC generator, 42 a read data converter, and 43 a device CRC checker. A currently used disk array system is constructed, for example, as shown in Fig. 1. As illustrated in Fig. 1, the disk array system 32 is provided with a disk controller 33 and a plurality of storage devices 34, e.g., a plurality of magnetic disk drives. This disk array system 32 is connected to a host device, e.g., a host computer (HOST) 31 and is used as a subsystem (which is so-called DIA: Disk In Array) for the host computer 31. Among the plurality of storage devices 34, typically, eight storage devices (DV0 to DV7) are used for storing normal data, one storage device (DVP) is used for storing parity data, and one storage device (DVS) is used as a spare storage device. The disk array system 32 realizes data transfer at high speed by operating the plurality of storage devices 34 in parallel, and by inputting and outputting data to and from these storage devices 34 simultaneously. The disk array system 32 also operates the parity storage device (DVP) in parallel independently of the storage devices (e.g., DV0 to DV7) for storing the data, thereby storing parity data in this storage device (DVP). With this arrangement, even if one of the eight storage devices (DV0 to DV7) for storing the data becomes unable to read data, the data can be reconstructed from the parity storage device (DVP). Further, when a failure has occurred in one of the eight storage devices (DV0 to DV7), the data stored in the failed storage device is transferred to the spare storage device (DVS), and thereafter the spare storage device can be used for normal operation. In the disk array system 32, data blocks from the host computer 31 is divided and written in the plurality of storage devices 34. At this time, typically, CRC data is added as an error detecting code to each of the divided data blocks (normally data to be stored in one sector) including a specified number of bytes of data from the disk controller 33, and is written in each of the storage devices 34 together with the data, thereby securing the data. The CRC data adding process is illustrated in Fig. 2. In this case, it is assumed that the data transmitted through four paths from the host computer 31 (hereinafter referred to as four path data) is converted by the data path control circuit 35 provided in the disk controller 33 so as to be transferred to the storage devices through eight paths (hereinafter referred to as eight path data). In this way, the four path data are converted into the eight path data, which are written in the plurality of storage devices (DV0 to DV7). At this time, the CRC data are generated from each data transferred through the paths from the host computer 31. For instance, in the case of a host CRCH0 (CRC data added in the host computer 31), it is generated from data DT0, DT4, DT8, DT12, DT16, DT20, etc. Further, a host CRCH1 is generated form DT1, DT5, DT9, DT13, DT17, DT21, etc., and a host CRCH2 is generated from DT2, DT6, DT10, DT14, DT18, DT22, etc. Device CRCs (CRC data added to the data to be read from the storage devices in the data path control circuit) are generated for each of the eight divided paths. For instance, a CRCD0 is generated from DT0, DT8, DT16, etc. Further, a CRCD1 is generated from DT1, DT9, DT17, etc., and a CRCD2 is generated from DT2, DT10, DT18, etc. An exemplary data path control circuit 35 will be described with reference Fig. 3. As shown in Fig. 3, the data path control circuit 35 is provided with register units (REG) 36, 37, 44 and 45, a host CRC checker (HOST CRC CHK) 38, a host CRC generator (HOST CRC GEN) 39, a write data converter 40, a read data converter 42, and the like. Further, the write data converter 40 includes a device CRC generator (DV CRC GEN) 41, and the read data converter 42 includes a device CRC checker (DV CRC CHK) 43. The register unit 36 is used when the write data are input to the data path control circuit 35, and the register unit 36 includes registers WI0 to WI3 corresponding to the four paths. The register unit 37 is used when the read data are output from the data path control circuit 35, and the register unit 37 includes registers RO0 to RO3 corresponding to the four paths. The register unit 44 is used when the write data are output from the write data converter 40, and the register unit 44 includes registers WO0 to WO7 for storing normal data, a parity register WOP for storing a parity data, and a spare register WOS. The register unit 45 is used when the read data are input to the read data converter 45, and the register unit 45 includes registers RI0 to RI7 for storing the normal data, a parity register RIP for storing a parity data, and a spare register RIS. During the transfer of the write data, the data transmitted to the four paths from the host computer 31 are temporarily stored in the register unit 36. Thereafter, the data are converted from four path data into eight path data by the write data converter 40 after the CRC data are checked by the host CRC checker 38. As this time, the CRC data are added to the data for the respective paths by the device CRC generator 41, and the eight path data and the parity data are temporarily stored in the register unit 44. Thereafter, the data are transferred to the respective storage devices 34 and are stored and the recording media (magnetic disks). Further, during the transfer of the read data, the eight path data and the parity data read from the respective storage devices are temporarily stored in the register unit 45. Thereafter, these data are read into the read data converter 42, in which each CRC data is checked for each path by the device CRC checker 43, and the eight path data are converted into the four path data. Thereafter, each CRC data is added to each of the four path data, which are transferred to the host computer after they are stored temporarily in the register unit 37. In regard to the process of data check according to a prior art described above, there are the following problems. (1) The data path control circuit 35 is provided with a large number of multiplexers, and therefore it is necessary for a complicated switching control of the multiplexers to be executed to switch paths for data conversion. At this time, the data may be erroneously transferred due to a failure of switching operations of some multiplexers. (2) For instance, the write data converter 40 and the read data converter 42 actually include a large number of multiplexers for executing such a switching control at high speed. Accordingly, if these devices fail during switching operations, a data error may occur. In this case, for example, even if the paths #0 and #1 at the device side are erroneously changed with each other due to a failure of the switching operations, such a data error cannot be detected even when the CRC check is applied. Further, even if the same data as in the path #0 is output to the path #1 due to undesired switching operations, the error cannot be detected by the CRC check. (3) In such a process of CRC checking, since the CRC data is added and checked for the data of each path separately, the above-mentioned data error, which may occur when the paths are erroneously changed with each other, cannot be detected. When these situations have occurred, erroneous data are transferred to the respective devices 34. Further, a user cannot notice that the data are erroneous, until the data are read from the devices 34 later and the dRC data check is executed for the read data. Consequently, the reliability of the data is deteriorated. EP-A-0 503 417 by the present applicant constitutes prior art under Article 54(3) and (4) EPC. It discloses (Figure 1) an apparatus for data checking in which blocks of write data from a host computer are first routed through a host CRC generator to be given host CRC data. The write data are then fed to a data sequencer to be divided into four data ports, are given respective port CRC data, and are written to respective storage devices. The divided write data are also fed back--to a read data path, allowing the host CRC to be extracted and checked. If required the port CRCs can be checked by separate circuitry. According to a first aspect of the present invention, there is provided an apparatus for data checking in a storage system which includes a plurality of storage devices operated in parallel, the apparatus receiving write data as data blocks each including data of an error detecting code generated in a host device, said apparatus comprising: means for simultaneously transferring said write data to respective storage devices in a write operation; means for checking data in said storage system, said means for checking data being operative to execute a write data checking process when said write data are transferred to said respective storage devices in said write operation; first data transfer paths for transferring said write data; second data transfer paths for transferring read data; means for distributing said data blocks of write data so as to be written in said plurality of storage devices and at the same time transferred to said second data transfer paths; combining means for combining said write data transferred to said second data transfer paths into blocks of combined data which are transferred back to said host device; means connected to an output of said combining means, for generating data of an error detecting code again for said host device for each of said blocks of combined data; storing means for storing the data of error detecting codes from said host device; and comparing means for comparing each of the data of error detecting codes generated again for said host device, with each of the data of error detecting codes stored in said storing means so as to check whether or not the two kinds of said data of error detecting codes correspond to each other and to check whether or not said write data have been correctly written in said respective storage devices. Preferably, said storing means for storing said data of said error detecting codes includes a register unit for a cyclic redundancy check of said host device, and said comparing means for comparing said two kinds of data with each other includes a comparator. According to a second aspect of the present invention, there is provided a method for data checking in a storage system which includes a plurality of storage devices operated in parallel, the apparatus receiving write data as data blocks each including data of an error detecting code generated in a host device, said method comprising the steps of: executing a write data checking process when said write data are to be transferred to said respective storage devices in said write operation; storing the data of error detecting codes from said host device; transferring and distributing said data blocks of write data along a write data transfer path so as to write them simultaneously in respective said storage devices and also along a read data transfer path which is normally unused during a write operation; combining said write data transferred to said read data transfer path into blocks of combined data which are transferred back to said host device; generating data of an error detecting code again for said host device for each of said blocks of combined data; and comparing each of the data of error detecting codes generated again for said host device, with each of the data of error detecting codes stored previously so as to check whether or not the two kinds of said data of error detecting codes correspond to each other and to check whether or not said write data have been correctly written in said respective storage devices. In an embodiment of the invention, the above apparatus and method are applied to a disk array system. Embodiments of the present invention may therefore provide an apparatus and method for data checking in a storage system, which enable high reliability of data in write/read operation to be ensured without disturbing data transfer at high speed. Embodiments of the present invention may provide an apparatus and method for data checking in a storage system, e.g., disk array system, which enable a data error, that may occur due to a failure of switching operations of data paths when large amounts of write data or read data are transferred to or from a plurality of storage devices, to be detected. Embodiments of the present invention may provide an apparatus for data checking in a storage system, which enables such a data error to be detected by merely adding a simple circuit, thereby preventing the reliability of data from being deteriorated. Embodiments of the present invention may also provide a method for data checking in a storage system, which enables the data error to be detected by a simple process without increasing the time required for the data check. Embodiments of the present invention may also provide an apparatus and method for data checking, which is applicable to a disk array system that can process large amounts of data at high speed. According to the above-mentioned apparatus and method for data checking, the write data checking process can be executed as accurately as the read data checking process. Therefore, even if a data error occurs due to the undesired switching operations of the data paths during the transfer of the write data, such a data error can be immediately detected. Further, the write data and read data may not simultaneously transfer. In view of this, the write data can be checked by effectively utilizing the paths for the read data, whereas the read data can be checked by effectively utilizing the paths for the write data. Thus, the transfer data can be checked merely by adding a simple construction such as the register unit and comparator. For a better understanding cf the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, wherein: Fig. 1 is a block diagram of a conventional disk array system; Fig. 2 is a block diagram for explaining a CRC adding process according to a prior art; Fig. 3 is a block diagram of data path control circuit according to a prior art; Fig. 4 is a block diagram of a data path control circuit showing an embodiment of the present invention; Figs. 5(A) and 5(B) are timing charts for explaining the write data checking process in the data path control circuit shown in Fig. 4; Fig. 6 is a perspective view, partially cut away, showing a mechanism of a magnetic disk drive; Fig. 7 is a perspective view showing the whole magnetic disk array system; Fig. 8 is a perspective view showing an appearance of a plurality of disk array devices according to an embodiment of the present invention; and Fig. 9(A) and 9(B) are block diagrams of a magnetic disk array control unit and the overall disk array devices, respectively. Fig. 4 is a block diagram of a data path control circuit showing an embodiment of the present invention, in which the same elements as in Figs. 1 to 3 are indicated with the same reference numerals. In this case, it should be understood that the circuit shown in Fig. 4 is a circuit provided in the disk controller 33 in Fig. 1. The data path control circuit in this embodiment is provided with a register unit 46 for a host CRC check (hereinafter referred to as a host CRC register unit 46), a register unit 47 for a device CRC check (hereafter referred to as a device CRC register unit 47), a CRC checker (comparator) 48, and multiplexers 49, 50 in addition to the construction of the data path control circuit of the prior art shown in Fig. 3. The host CRC register unit 46 includes four registers CRC0, CRC1, CRC2 and CRC3 corresponding to four paths, each register being adapted to store the CRC data for the corresponding path, i.e., first data transfer path for the write data. The device CRC register unit 47 includes registers CRC0, CRC1, CRC2, ..., CRC7, CRCP, and CRCH for respective paths corresponding to storage device 34 (DV0 to DV7, DVP, and DVHS), each register being adapted to store the CRC data for the corresponding path, i.e., second data transfer path for the read data. The CRC checker 48 is adapted to receive and compare two CRC data and, for example, includes a comparator. The multiplexers 49, 45 are circuits for switching the two inputs. Although a processor and the like are provided so as to control the respective components shown in Fig. 4, these devices are not illustrated in Fig. 4. Further, a detailed description is omitted for the components included in the same construction as the prior art. Hereinafter, a data check process of this embodiment will be described. It will be appreciated that the number of data paths is the same as the prior art and that host CRC and device CRC represents CRC data. First, a write data check processsing, executed when the write data are transferred to the respective devices 34, will be explained in detail. In the data path control circuit 35 which is provided in the disk controller 33 (Fig. 1) and has received the write data from the host computer 31 (Fig. 1), the CRC check is carried out in the following sequence. The host CRC added to the write data from the host computer is checked by the host CRC checker 38, and is stored in the host CRC register unit 46 at the same time. The write data from the host computer 31 are transferred through the four paths, and are stored in the registers WI0 to WI3 of the register unit 36 temporarily. Then, the CRC data is checked for each path of data by the host CRC checker 38. Thereafter, the checked CRC data for the respective paths of data are stored in the registers CRC0 to CRC3 of the host CRC register unit 46. The write data stored in the register unit 36 are converted by the write data converter 40 into eight path data and parity data, to which the CRC data are added for each path by the device CRC generator 41, and are stored in the register unit 44. Subsequently, the data stored in the register unit 44 are transferred to the respective storage devices to be stored therein. At the same time, the eight path data and the parity data are transferred through the second data transfer paths used for reading the data to the register unit 45 and are stored therein. The data stored in the register unit 45 have the CRC data thereof checked by the device CRC checker 43 in the read data converter 42, and are then converted into four path data. The converted four path data have the CRC data which are added thereto for each path by the host CRC generator 39. At this time, the CRC data added by means of the host CRC generator 39 are input to the CRC checker 48 through the multiplexer 50, while CRC data stored in the host CRC register 46 are input to the CRC checker 48 through the multiplexer 49. The two kinds of CRC data, which are input to the CRC checker 48, are compared with each other in the CRC checker 48. If the comparison result shows that these two kinds of CRC data correspond to each other, it is determined that there is no error and accordingly no data error has occurred during the transfer of write data. However, if a data error has occurred due to a failure in the write data converter 40 or in the read data converter 42, the above two kinds of data are different from each other. Consequently, the data error is easily and accurately detected by executing such a comparison. Second, a read data process, executed when the read data are transferred to the host computer 31, will be explained in detail. In the data path control circuit 35 which has received the read data from the respective storage devices 34, the CRC check is carried out in the following sequence. The device CRC data added to the read data from the respective storage devices are checked in the device CRC checker 43, and are stored in the host CRC register unit 47 at the same time. The read data from the storage devices 34 are transferred through the eight paths for the normal data and the one path for the parity data, and are stored in the registers RI0 to RIS of the register unit 45 temporarily. Thereafter, the CRC data for the respective paths of read data are checked by the cavice CRC checker 43, and are stored in the registers CRC0 to CRCS of the device CRC register unit 47 (stored for each path). Subsequently, the data for the respective paths after the CRC check are combined and converted by the read data converter 12 into four path data, to which the CRC data are added by the host CRC generator 39, and are stored in the register unit 37. The combined data stored in the register unit 37 are transferred to the host computer for each path of data, but are simultaneously transferred to the register unit 36. After the respective CRC data stored in the register unit 36 are checked by the hcst CRC checker 38, the four path data are transferred through the first data transfer paths to the write data converter 40. Further, the four path data are divided and converted by the write data converter 40 into eight path data and parity data, to which the CRC data are added by the device CRC generator 41. The respective CRC data added to the eight path data and the parity data in the device CRC generator 41 are input to the CRC checker 48 through the multiplexer 50, while the CRC data for the respective paths stored in the device CRC register 47 are input to the CRC checker 48 through the multiplexer 49. The two kinds of CRC data, which are separately input to the CRC checker 48, are compared with each other in the CRC checker 48 (comparison of the CRC data for each path). If the comparison result shows that these data correspond to each other, it is determined that there is no error and accordingly no data error has occurred during the transfer of read data. However, if a data error has occurred due to a failure in the read data converter 42, the above two kinds of data are different from each other. Consequently, the data error is also easily and accurately detected by executing such a comparison. Besides the CRC data described in the foregoing embodiment, embodiments of the present invention are applicable to various other error detecting codes. Further, data flow of the write data will be illustrated in Figs. 5(A) and 5(B) by using timing charts, to clarify the data checking process, Figs. 5(A) and 5(B) are time charts for explaining the write data checking process in the data path control circuit shown in Fig. 4. In Fig. 5(A), CLK denotes a clock signal which is a reference for synchronously rotating a plurality of storage device, e.g., a plurality of disk drives, in a disk array system. In the condition that the system is synchronous with the clock signal CLK, first the write data of four data channels (BUS to BUS), to which the respective host CRC data of eight bytes are added, are transferred from the host computer 31 through the first data transfer paths, and are stored in the register unit 36 temporarily (WI0 to WI3). Next, the write data are divided and converted by the write data converter 40 into eight path data and parity data, and are stored in the register unit 44 (WO0 to WOP). At this time, the device CRC data are added to these eight path data and the parity data. Further, as shown in Fig. 5(a), the eight path data are transferred to the respective storage devices 34, and are simultaneously transferred through the second data transfer path to the register unit 45 to be stored therein (RI0 to RIP). Further, the respective CRC data of the data stored in the register unit 45 are checked by the device CRC checker 43 in the read data converter 42. Thereafter, the eight path data are combined and converted again into four path data. Further, the CRC data are generated again by the host CRC generator 39 for each four path data (RI - CRC). Finally, the CRC data, which are added to each of the four path data by the host CRC generator, are compared with the CRC data stored previously in the host CRC register unit 46, in the CRC checker 48. In this case, as apparent from Figs. 5(A) and 5(B), the time required for completing the data checking process is relatively short, only as much as a length of time equivalent to several clock cycles. Therefore, the data checking process according to the present invention can be prevented from disturbing the data transfer at high speed. As described above, the present invention has the following advantages. (1) Even if a data error occurs due to a data path failure or the like, such an error can be detected during a data transfer. Accordingly, the reliability of the data can be improved. (2) The data error can be reliably detected merely by adding a simple circuit. Accordingly, the reliability of a disk array system can be also improved while minimizing a cost increase due to the data checking process. Here, in order to facilitate understanding of the embodiment according to the present invention, a perspective view, partially cut away, showing a mechanism of one magnetic disk drive is illustrated in Figs. 6. As seen from this figure, a plurality of disks (e.g., eleven disks) 15 are rotated simultaneously by means of a spindle motor 17. The tracks on a recording surface of each disk 15 are written with a predetermined data pattern. However, the tracks at both ends of the inner zone and the outer zone of the disk 15 are formed as guard bands 150 in which a particular pattern is written, instead of a data pattern, the particular pattern being used for stopping a seek operation of two kinds of heads 130 and 131. Further, at the inner and the outer sides of the guard band 150, an erase zone 155 is formed for mechanically stopping the heads 130 and 131. Preferably, embodiments of the present invention are adapted to a disk array system 140 as shown in Fig. 7, wherein reference numeral 14 denotes a magnetic disk drive that includes the disks 15, and 141 denotes a housing that can accommodate a plurality of magnetic disk drives. In this case, the disk array system, 140, i.e., disk array device is composed of eight disk drives for data transfer, one parity disk drive and one spare storage disk drive. The magnetic disk drives 14 constituting each unit of disk array devices comprise a disk enclosure 18. The disk enclosure 18 serves to contain the disks 15 and the peripheral circuit module 17 inside the disk enclosure 18 per sec. Each magnetic disk drive 14 is constructed to be easily inserted into the housing 141 and also easily removed therefrom, so that a maintenance operation can be rapidly performed when a failure, etc., has occurred. Further, in order to clarify the whole construction of a disk array system to which the present invention is applied, an appearance of a plurality of disk array devices including the operation panel 226 is illustrated in Fig. 8. In Fig. 8, a disk array system 140 is constituted by a plurality of disk array devices, e.g., two disk array devices 140' and a disk array control unit 120 for controlling these disk array devices 140'. The two disk array devices 140' and the disk controller is arranged to be contained in a housing 141. In this case, the front side of the housing 141 at each disk array device 140' is provided with the operation panel 226, in addition to a plurality of ventilation windows 143 for radiating heat generated from a plurality of disk drives (not shown in Fig. 8). Further, the front side of the housing 141 at the disk array control unit 120 is also provided with the operation panel 226. Finally, block diagrams of a disk array ccntrol unit 120 and a plurality of disk array devices 140 controlled by the disk array control unit 120 are illustrated in Figs. 9(A) and 9(B), respectively. In this case, eight disk drives at maximum can be controlled by the disk array control unit 120 having a plurality of directors. In Fig. 9(A), high-speed optical channels A, B, C and D, and a high-speed optical control module functioning as an optical/electric interface (O/E interface), are provided to enable date to be transferred at high speed between the channel and the disk array devices 140'. The disk array control unit 120 consists of two directors. Each director consists of two modules: the optical control module as described above; and an array control module to control the disk array devices 140'. The latter module is divided into ten device controllers to control the respectively corresponding disk drives (Drive 0 - 7, Drive P and Drive S as shown in Fig. 16(B)) and an array date controller to transfer the data to or from each of the device controllers. The two directors in the disk array control unit are independent of each other. These directors can control two groups of disk array devices simultaneously. In this case, the operation panel 226 (Fig. 8) can display the status information of each of two disk array devices.

Claims: An apparatus for data checking in a storage system which includes a plurality of storage devices (15) operated in parallel, the apparatus receiving write data as data blocks each including data of an error detecting code generated in a host device, said apparatus comprising: means (36, 44) for simultaneously transferring said write data to respective storage devices in a write operation; means (38) for checking data in said storage system, said means for checking data being operative to execute a write data checking process when said write data are transferred to said respective storage devices in said write operation; first data transfer paths for transferring said write data; second data transfer paths for transferring read data; means (40) for distributing said data blocks of write data so as to be written in said plurality of storage devices and at the same time transferred to said second data transfer paths; combining means (42) for combining said write data transferred to said second data transfer paths into blocks of combined data which are transferred back to said host device; means (39) connected to an output of said combining means (42), for generating data of an error detecting code again for said host device for each of said blocks of combined data; storing means (46) for storing the data of error detecting codes from said host device; and comparing means (48) for comparing each of the data of error detecting codes generated again for said host device, with each of the data of error detecting codes stored in said storing means (46) so as to check whether or not the two kinds of said data of error detecting codes correspond to each other and to check whether or not said write data have been correctly written in said respective storage devices. An apparatus for data checking as claimed in claim 1, wherein said storing means (46) for storing said data of said error detecting codes includes a register unit (46) for a cyclic redundancy check of said host device, and wherein said comparing means (48) for comparing said two kinds of data with each other includes a comparator. A method for data checking in a storage system which includes a plurality of storage devices (15) operated in parallel, the apparatus receiving write data as data blocks each including data of an error detecting code generated in a host device, said method comprising the steps of: executing a write data checking process when said write data are to be transferred to said respective storage devices in said write operation; storing the data of error detecting codes from said host device; transferring and distributing said data blocks of write data along a write data transfer path so as to write them simultaneously in respective said storage devices and also along a read data transfer path which is normally unused during a write operation; combining said write data transferred to said read data transfer path into blocks of combined data which are transferred back to said host device; generating data of an error detecting code again for said host device for each of said blocks of combined data; and comparing each of the data of error detecting codes generated again for said host device, with each of the data of error detecting codes stored previously so as to check whether or not the two kinds of said data of error detecting codes correspond to each other and to check whether or not said write data have been correctly written in said respective storage devices. An apparatus according to claim 1 or 2 or a method according to claim 3, wherein said storage system is a disk array system.

Inventors: NISHIYAMA SHINJI, NISHIYAMA, SHINJI, Nishiyama, Shinji, c/o FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11B20
IPC codes: G06F3, G11B20