Register control circuit for initialization of registers

Abstract: A register control circuit has a plurality of registers (L0-L7), a control circuit for producing clock signals (S CK1 ,S CK2 ), and a logic circuit (G1,G2) for producing latch clocks based on a reset signal (S RST ) and the clock signals. A shift data (D IN ) is inputted to a first one (L0) of the plurality of registers through a 2-input AND gate (G3). The latch clocks are forced to become active simultaneously under a state in which an input to the first stage register (L0) being controlled to "0". The shift register is initialized in such a way that a "0" input is sequentially transferred from the first stage register (L0) to the final stage register (L7). The shift register can be formed without the need of registers having reset inputs and initialized speedily, while keeping the increase in the device elements at the minimum.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a register control circuit, and more particularly to a register control circuit for initializing registers without a dedicated reset input. (2) Description of the Related Art Conventionally, an initialization of a D-type flip-flop circuit (hereinafter referred to as "DFF") which is formed by 2-INPUT AND 2-INPUT NOR gates (hereinafter abbreviated as, e.g., "2AND2NOR gate") 1 ∼ 4 and an inverter 5 as shown in Fig. 1A is performed by supplying a reset signal S RST directly to a 2AND3NOR gate 13 at a master stage and a 2AND3NOR gate 12 at a slave stage as shown in Fig. 1B, so that the outputs of 2AND2NOR gates 11, 14 are set to "1" and the outputs of the 2AND3NOR gates 12, 13 are set to "0", respectively. To initialize a multi-register circuit such as a shift register, a plurality of DFFs each having a reset input are used so as to form the shift register and a reset input signal is directly applied to the respective DFFs. Fig. 2A shows an example of a conventional shift register and Fig. 2B shows timing-charts thereof. In the conventional shift register shown in Fig. 2A, a plurality of the D-type flip-flop circuits (DFFs) R0 ∼ R7, each having an internal circuit of the same circuit configuration as that shown in Fig. 1B, are connected in series and are commonly supplied with shift clocks S CK1 , S CK2 and a reset signal S RST . A shift data D IN inputted from a shift data input terminal (D IN ) is outputted from a shift data output terminal D OUT through the DFFs R0 ∼ R7. While the reset signal S RST remains "0" immediately after the power is turned on, the states of the DFFs R0 ∼ R7 are and remain undefined. When the reset signal S RST is set to "1", the outputs of the DFFs R0 ∼ R7 are all and immediately initialized to "0". Subsequently, the shift clocks S CK2 and S CK1 are supplied and, though not shown in the timing charts given in Fig. 2B, the shift data is inputted to the input terminal D IN of the shift register circuit and is shifted out from the output terminal D OUT . One advantage of the above conventional shift register is that it can be immediately reset when the reset signal is set to "1" because each of the DFFs R0 ∼ R7 forming the shift register has a reset input terminal. However, since all bits are implemented by DFFs each having a reset input terminal, the shift register suffers from a disadvantage of requiring more logic elements in number than those which constitute DFFs having no reset input terminals as shown in Fig. 1A. To avoid increasing in the number of elements, there has been known a shift register in which, as shown in Fig. 3A, a DFF having a reset input terminal is used for a DFF Q0 of the first stage and DFFs not having a reset input terminal are used for the remaining DFFs Q1 ∼ Q7 that follow. The operation of this shift register is described below. While the reset signal stays at "0" immediately after the power is turned on, the outputs of the DFFs Q0 ∼ Q7 remain undefined, respectively, as shown in the timing charts in Fig. 3B. When the reset signal S RST is set to "1", the first stage DFF Q0 is initialized immediately, but the remaining DFFs Q1 ∼ Q7 stay at undefined states since they are given no reset input. Subsequently, when the shift clocks S CK1 and S CK2 are supplied to the respective DFFs with the reset signal being held at "1", the output "0" from the DFF Q0 is shifted into the following DFF Q1 in response to the first clock of the shift clocks, whereby the output of the DFF Q1 becomes "0". In response to the second clock of the shift clocks, the output of the DFF Q1 is shifted into the following DFF Q2 and, thus, the output of the DFF Q2 becomes "0". In a similar manner, the output of the DFF Q7 becomes "0" at last in response to the seventh clock of the shift clocks, thereby completing the initialization of the shift register. Thereafter, a shift data is loaded into the shift register from the data input terminal D IN . Since the above circuit adopts only one DFF which is equipped with a reset input terminal, it contributes substantially to the reduction in the number of the necessary elements. However, as can be readily understood from the timing charts shown in Fig. 3B, the circuit takes an extra amount of time to generate the shift clocks that are necessary to completely initialize the entire shift register. This suffers from the disadvantages of increasing the initialization time and also making the shift clock control for the register initialization more complex. As described above, the conventional register initialization circuits have problems in that the number of the necessary elements is increasing because of the need to directly supply the reset signal to the respective DFFs and, in that the initialization time has increased because of the need for generating shift clocks for initialization. These problems in the conventional shift registers are to be solved by the present invention. "Patent Abstracts of Japan, Vol. 5 No. 84 (P-64)(756) 2 June 1981" discloses a clear control circuit and a way of enabling a high-speed clearing without adding a special clear function by the shiftclock control in a shift register. Data is read in the first stage half-bit register of the one-bit shift register of each stage of the N-stage shift register with a first clock from an input terminal. The data is fixed to the next stage half-bit register of the register with the succeeding clock, and as far as the clear signal is not fed from a second terminal, the input data is sequentially shifted. When the clear signal is fed from a second terminal, the first clock is fed to the two-half bit registers constituting the register via a NAND-circuit, an AND-circuit and an OR-circuit, allowing to conduct each stage of registers. The preamble of Claim 1 is based on this prior art. "Patent Abstracts of Japan, Vol. 12, No. 29 (P-660) 28 January 1988" discloses a resetting system for a dynamic shift register circuit. Resetting is executed in synchronism with a clock by forcibly conducting a MOS transistor to constitute respective clock inverters and supplying a resetting signal to the input stage of the first stage clock inverter. SUMMARY OF THE INVENTION It is, therefore, an object of the invention to solve the problems existing in the conventional shift registers and to provide an improved shift register which is formed by registers having no reset inputs and in which an initialization can be performed speedily, while keeping the increase in the device elements at the minimum. A register control circuit according to the present invention is defined in independent claim 1. Dependent claim 2 discloses a particular embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS The objects features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention explained with reference to the accompanying drawings, in which: Fig. 1A is a circuit diagram of a conventional DFF circuit having no reset input terminal; Fig. 1B is a circuit diagram of a conventional DFF circuit having a reset input terminal; Fig. 2A is a circuit diagram showing a conventional shift register; Fig. 2B are timing charts of the shift register shown in Fig. 2A; Fig. 3A is a circcuit diagram showing another conventional shift register; Fig. 3B are timing charts of the shift register shown in Fig. 3A; Fig. 4A is a circuit diagram of another shift register Fig. 4B are timing charts of the shift register shown in Fig. 4A; Fig. 5A is a circuit diagram of a register control circuit of an embodiment according to the present invention, which is embodied to a microcomputer; Fig. 5B are timing charts of the register control circuit shown in Fig. 5A; and Fig. 6 is a circuit diagram of a DFF used in the microcomputer shown in Fig. 5A. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 4A shows another shift register Shift clocks S CK1 , S CK2 are inputted into 2-input OR gates G1 and G2, respectively, in each of which a logical OR is taken with a reset signal S RST , and fed into a plurality of DFFs L0 ∼ L7 each of which has no reset input terminal. A shift input signal D IN together with an inverted reset signal is inputted to a 2-input AND gate G3. An output of the AND gate G3 is inputted to a first stage DFF L0. An operation of the above shift register is as follows. While the reset signal S RST is "0" immediately after the power is turned on, the shift clocks S CK1 and S CK2 are both at "0" and, thus, the states of the DFFs L0 ∼ L7 remain undefined. At this moment, since an output of an inverter G4 is "1", the input signal D IN is transferred to the output of the 2-input AND gate G3 as it is. When the reset input signal S RST becomes "1", the outputs of both the 2-input OR gates G1 and G2 become "1". Since the reset input signal S RST is now "1", the output of the inverter G4 is "0" and, thus, the output of the 2-input AND gate G3 is "0", whereby a "0" is inputted to the first-stage DFF L0. Since the clock inputs, that is, the outputs of the OR gates G1 and G2 supplied to the DFF L0 have been set to "1", which is the same as the DFF shown in Fig. 1A wherein the input signal D is "0" and the clock signal C1 is "1", the output of the inverter 5 becomes "1", the output of the 2AND2NOR gate 3 becomes "0", and the output of the 2AND2NOR gate 1 becomes "1". Since the clock signal C2 is also "1", the outputs from the master side are transferred to the slave side and, as a result, the output of the 2AND2NOR gate 2 becomes "0" and that of the 2AND2NOR gate 4 becomes "1", thus completing the initialization of this DFF. In this way, the initialization of the first stage DFF LO is performed. Upon the completion of the initialization of the first stage DFF LO, the input signal which is forwarded to the second stage DFF L1 becomes "0". As a result, the DFF L1 is initialized in the same manner as the DFF LO. Subsequently, the remaining DFFs L2 through L7 are sequentially initialized. The above operations occur asynchronously, so that, after a delay time corresponding to the 24 gate delay stages from the top stage DFF LO to the final stage DFF L7, the initialization of the registers is completed. Since a delay time for a single gate is 1 ns or less, the total delay time amounts to 24 ns or less, which means that the registers can be initialized in a very short time. Since the shift register uses DFFs each of which has no reset input, only the control gates G1 through G4 entail an increased number of logic elements, which is negligible in a practical use. Next, Fig. 5A shows an embodiment of this invention. The circuit of this embodiment performs an initialization of the respective registers of an internal circuit of a microcomputer. As shown in the timing charts of Fig. 5B, while the reset input signal is "0", an output of an AND gate 103 is "0" and, thus, the signals 1 and 2 from the clock generator circuit 106 are supplied as they are to the microcomputer 107 as the system clocks 1' and 2'. After the reset signal S RST rises to "1", an output of an inverter 102 becomes "0" after a delay time td which is established by a delay circuit 101 and, thus, the output of the AND gate 103 and also the outputs of 2-input OR gates 104, 105 are kept at "1" for the interval td. As shown in Fig. 6 in the internal circuit of the microcomputer 107, a register circuit is formed by a latch which has no reset input and comprises an inverter Il, 2AND2NOR gates NR1 ∼ NR4, and a 2-input NOR gate N1. When the clock signals 1' and 2' become "1" simultaneously, the output of the 2-input NOR gate N1 is forwarded to the master stage of the latch and, then, to the slave stage of the latch, in the same manner as for the shift register of fig. 4., thus initializing the Q output of the register to "0". Since the microcomputer 107 uses a number of internal registers, this register control circuit can bring about substantial reduction in device elements as compared with the case where DFFs having reset inputs as shown in Fig. 2B are used. As explained above, according to the present invention, it is possible to initialize stand-alone shift registers and registers in a microcomputer speedily and asynchronously by forcing the DFF latch clocks to become active based on a reset input, while keeping the increase in the device element at the minimum. While the invention has been described in its preferred embodiment, it is to be understood that the words which have been used are words of description rather than limitation and that changes may be made without departing from the scope of the invention as defined in the claims.

Claims: A register control circuit comprising: a plurality of master-slave type registers (LO-L7) connected in series in such a manner that a data output terminal of a preceding one of said master-slave type registers is connected to a data input terminal of a succeeding one of said master-slave type registers, each of said master-slave type registers having a master side circuit (1,3,5; NR1,NR2,I1) provided with a master clock terminal and a slave side circuit (2,4;NR3,NR4) provided with a slave clock terminal; a first signal terminal supplied with a master clock signal (SCK2,1); a second signal terminal suppled with a slave clock signal (SCK1,2); a first signal line connected in common to said master clock terminals of said master side circuit of each of said plurality of master-slave type registers to transfer said master clock signal; a second signal line connected in common to said slave clock terminals of said slave side circuit of each of said plurality of master-slave type registers to transfer said slave clock signal; a reset terminal supplied with a reset signal (SRST); and a first logic circuit (G3,G4;N1) responding to said reset signal and transferring a data signal (DIN) to the data input terminal of said first one of said plurality of master-slave type registers; characterized in that said register control circuit further comprises a one-shot pulse generator (101,102,103) responding to said reset signal to generate a one-shot pulse (1',2'), and a second logic circuit (G1,G2;104,105) transferring said one-shot pulse to both of said first and second signal lines when said one-shaft pulse is generated and coupling said master clock signal and said slave clock signal respectively to said first and second signal lines when said one-shot pulse is not generated, in each of said master-slave type registers being formed an electrical path between the data input and the data output terminal during said one-shot pulse. The circuit as claimed in claim 1, characterized in that said one-shot pulse generator comprises a delay circuit (101) with a delay time (td), an inverter (102) and an AND gate (103), said delay circuit receiving said reset signal and outputting a delayed-reset signal, said inverter inverting said delayed-reset signal, said AND gate receiving said reset signal and said delayed-reset signal, and outputting said one-shot pulse for a period of said delay time.

Inventors: AOYAMA KOICHIRO, AOYAMA, KOICHIRA, Aoyama, Koichiro, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G11C19
IPC codes: G11C19, G06F1, G06F15