Reference generator

Abstract: A reference generator system that operates in either a current-controlled mode or a voltage-controlled mode and includes a power-down circuit connected to the operational amplifier to power down the operational amplifier when the reference generator is switched to the current-controlled mode.

Description: This invention relates to reference generators, controllably operable in a voltage mode or a current mode. There are incorporated herein by reference in their entireties European Patent Application 92303885.5 and 92303886.3, filed on the same day as the present Application, and claiming priority respectively from US Application 07/691,711 & US Application 07/691,712. US-A-4 814 688 discloses a reference generator which is either responsive to a constant current (current-controlled mode) or a reference voltage (voltage-controlled mode) in maintaining an energizing voltage at a substantially constant value. This reference generator isolates an operational amplifier from the circuit during the current-controlled mode and prevents a reference voltage affecting the operation of the reference generator. In the accompanying drawings, Figure 1 is a schematic diagram of a selectable "voltage-controlled mode" or "current-controlled mode" circuit, in accordance with the prior art. This reference generator includes an operational amplifier 2, switches 4 and 6, a resistor 8, a current source 10, a voltage source V CC , and a p-channel transistor 12. The voltage V BIAS is the reference output voltage which is used by the rest of the chip to generate current. When switches 4A and 4B are at their "on" (i.e. closed) position and switches 6A and 6B are at their "off" (i.e. open) position, as shown, the circuit is in its "voltage-controlled mode". In this configuration, the output V BIAS of operational amplifier 2 is applied to the gate of transistor 12. Therefore, the gate to source voltage V GS of transistor 12 is represented by the equation V GS = V G - V S where V G is the gate voltage and V S is the source voltage. It logically follows from the illustrated circuit that V GS = V BIAS - V CC Transistor 12, a p-type MOSFET transistor, conducts when |V GS | exceeds the threshold voltage of transistor 12. Accordingly, current flows along a current path 14 that includes the voltage source V CC , the transistor 12, the resistor 8, and ground. The voltage produced across the resistor 8 is introduced to the positive input of operational amplifier 2 which results in an output voltage appropriate to maintain substantially constant current through the path 14. Current through path 14 is calculated by the following equation: Current = V BIAS /R 8 in which R 8 is the resistance of resistor 8. When switches 4A and 4B are at their "off" position and switches 6A and 6B are at their "on" position, the circuit is in its "current-controlled mode". Since the output of operational amplifier 2 is disconnected from the gate of transistor 12, operational amplifier 2 has no effect on transistor 12. Instead, the gate of transistor 12 is connected by switch 6A to the drain of transistor 12, so that V BIAS = V CC - V SD where V SD is the source-to-drain voltage. The current through path 14 is maintained by the constant current source 10. In both cases, the voltage V BIAS is determined by the source-drain current of transistor 12. One major drawback of switching the output of the operational amplifier 2 is that the operational amplifier 2 is "open loop" when switches 4A and 4B are "off". Because the operational amplifier is typically designed with a large voltage gain and bandwidth, this open loop condition causes adverse effects. For example, the open loop condition may cause the output to fluctuate in an exaggerated manner. This fluctuation draws current from the power line or the substrate. Drawing current in this manner causes noise which can propagate to other parts of the circuit, thereby reducing the circuit's performance predictability. In accordance with this invention, a reference generator system is provided which overcomes certain of the disadvantages of the prior art by eliminating the "open-loop" operational amplifier previously required in the prior art. According to the present invention there is provided a reference generator, controllably operable in a voltage mode or a current mode, comprising: means for providing a reference current path, two voltage input means (VREF), one of which is coupled to the reference current path providing means, and means for amplifying a voltage difference between the two voltage input means with high gain and bandwidth, characterised in that the amplifying means has an output coupled to the reference current path providing means, and the reference generator further comprises means for powering down the amplifying means, the powering down means being responsive to a transition from voltage mode operation to current mode operation for selectively disabling current flow in the amplifying means and responsive to a transition from current mode operation to voltage mode operation for selectively enabling current flow in the amplifying means. In one embodiment of the present invention the amplifying means comprises an operational amplifier having two input terminals forming said two voltage input means. One of the input terminals is connected to a VREF node, and the other input terminal is connected to an IREF terminal. The output of the operational amplifier is connected to a control terminal of a transistor which, along with the IREF terminal, forms part of a current path. The control terminal of the transistor is connected to a VBIAS node A power-down circuit is connected to the operational amplifier. For the voltage-controlled mode, the IREF node is connected to a resistor for obtaining a voltage and the VREF node is connected to a voltage reference. In addition, the power-down circuit is responsive to a first condition on a control terminal thereof indicative of the voltage-controlled mode for powering-up the operational amplifier. For the current-controlled mode, the IREF node is connected to a current source and to the VBIAS node. In addition, the power-down circuit is responsive to a second condition on the control terminal thereof indicative of the current-controlled mode for powering-down the operational amplifier. In a variation of this embodiment, the power-down circuit control terminal floats for the current-controlled mode, and is connected to V BIAS for the voltage-controlled mode. This invention is more fully described below by way of example, with reference to the remaining figures of the accompanying drawings, in which: Figure 2 is a schematic diagram of a selectable "voltage-controlled mode" or "current-controlled mode" circuit, in accordance with the present invention. Figure 3 is a schematic diagram of an illustrative power-down circuit. Figure 4 is a component-level schematic diagram of a controllable voltage-controlled mode/current-controlled mode reference generator. Figures 5 and 6 are schematic diagrams showing an illustrative integrated circuit and switch in the current-controlled mode and voltage-controlled mode, respectively. As shown in Figure 2, the reference voltage V REF is connected to the negative terminal of the operational amplifier 22. Node 27 is connected to the positive input of operational amplifier 22. The output of operational amplifier 22 is connected to the gate of transistor 12. Node 27 is a common terminal for switches 24B and 26B. The other terminal of switch 24B is connected to resistor 8, which in turn is connected to ground. The other terminal of switch 26B is connected to current source 10, which in turn is connected to ground. The drain of transistor 12 is connected to node 27. Voltage V CC is connected to the source of transistor 12. The voltage introduced to the gate of the transistor 12 is also introduced to node 28. Nodes 27 and 28 are controllably connected or disconnected by the use of switch 26A. Node 28 is controllably connected or disconnected to a power-down circuit 20 with switch 24A. Power-down circuit 20 is connected to the operational amplifier 22, which is modified to receive the output of the power down circuit 20. The basic circuit structure shown in Figure 2 differs from the circuit shown in Figure 1 in at least two aspects. First, there is no switch between the gate of transistor 12 and the operational amplifier 22. Second, when switches 26 (i.e. 26A and 26B) are "on" and switches 24 (i.e. 24A and 24B) are "off", node 28 is disconnected from the power-down circuit 20, which then generates a power-down signal to the operational amplifier 22. Figure 3 shows an illustrative power-down circuit 20. The power-down circuit 20 includes a comparator 40, a pulldown resistor 42, and a reference voltage 44. The negative input of comparator 40 is connected to resistor 42 which is grounded, and to switch 24A. The reference voltage 44 provides input to the positive input terminal of comparator 40. When switch 24A is "off", no voltage is present at the negative input of the operational amplifier 40, and the voltage on the positive input from source 44 causes the output of the comparator 40 to rise to the supply voltage. When the switch 24A is "on", V BIAS is imposed on the negative input of the comparator 40. Because reference voltage 44 is between ground and V BIAS , the output of comparator 40 is low. This output is the power-down signal "PD" which is sent to the modified operational amplifier 22 to power it up or down, as appropriate, in a controllable manner for reducing the level of noise introduced into the circuit. An illustrative component-level embodiment of the controllable voltage-controlled mode / current-controlled mode reference generator is shown in Figure 4. The operation of this circuit is as follows. The operation amplifier 22 shown in Figure 4A is generally a conventional operational amplifier that is modified to respond to control signals at power-down ("PD") node 150 and power-down complement ("PDZ") node 152. Other operational amplifier designs may be suitable as well. P-channel MOSFETs 106 and 108 are connected as a differential pair receiving at their commonly connected sources a constant current from the current path comprising V DD and cascode p-channel MOSFET transistors 102 and 104. The gate of transistor 106 is connected to the IREF node 100 which is made accessible, for example, through a pin of the packaged integrated circuit. The gate of transistor 108 is connected to a VREF node 101, which is made accessible, for example, through a pin of the packaged integrated circuit. In the current-controlled mode, IREF node 100 is connected to a constant current source, such as source 10 in Figure 2, and VREF node 101 is left floating or connected to a constant voltage reference such as source 7 in Figure 2. In the voltage-controlled mode, VREF node 101 is connected to a constant voltage reference such as source 7 in Figure 2, and IREF node 100 is connected to one terminal of a suitable resistor such as resistor 8 of Figure 2, the other terminal of which is connected to ground. The drains of the transistors 106 and 108 are connected to respective output branch circuits 110 and 120. Branch 110 comprises V DD , cascode p-channel MOSFETs 112 and 114, cascode n-channel MOSFETs 116 and 118, and ground. Branch 120 comprises V DD , cascode p-channel MOSFETs 122 and 124, cascode n-channel MOSFETs 126 and 128, and ground. The gates of transistors 102, 112, and 122 are commonly connected, and connected to the drain of transistor 122 and source of the transistor 124 in the output branch 120. The gates of transistors 104, 114 and 124 are commonly connected, and connected to the drain of transistor 114 and the drain of the transistor 116 in the output branch 110. The node common to the drain of transistor 124 and the drain of transistor 126 in the output branch 120 is VBIAS node 172. In branch 110, the source of transistor 116 and the drain of transistor 118 are connected in common with the drain of transistor 106. In branch 120, the source of transistor 126 and the drain of transistor 128 are connected in common with the drain of transistor 108. Whether the operational amplifier 22 is in a power-up or power-down condition depends on the bias on the commonly connected gates of transistor 116 and 126, and on the commonly connected gates of transistor 118 and 128. These biases are determined by circuit branch 130, which comprises V DD , cascode p-channel MOSFETs 132 and 134, cascode n-channel MOSFETs 136 and 138, and ground. The gate of transistor 132 is connected to PD terminal 150. The gates of transistors 134 and 136 are commonly connected with the drains of transistors 134 and 136, and with the gates of transistors 116 and 126 in output circuits 110 and 120. The gate of transistor 138 is connected to the commonly connected source of transistor 136 and drain of transistor 138, and to the gates of transistors 118 and 128 in output circuits 110 and 120. Another circuit is provided to help pull up V BIAS node 172 during the current-controlled mode. During the current-controlled mode, signal PDZ at node 152 is low. P-channel MOSFET 146, which has its source connected to V DD and its drain connected to p-channel MOSFET 148, turns "on". Transistor 148, which has its gate and drain connected to VBIAS, also turns "on", thereby supplying current to node V BIAS . The current path is completed through p-channel MOSFET 142, which has its source connected to V BIAS node 172, and through n-channel MOSFET 140, which has its gate and drain connected in common with the gate and drain of transistor 142, and its source connected to ground. Once V BIAS node 172 is sufficiently pulled up, current through transistor 142 diminishes and is steered through transistor 144, which has its source connected to V DD and its gate and drain connected in common with the gates and drains of, respectively, transistor 142 and 140. During the voltage-controlled mode, transistor 146 and 148 are "off", since signal PDZ at node 152 is high, and current is steered through transistor 144 rather than transistor 142. P-channel MOSFET 149, which has its gate connected to VBIAS node 172 and its source and drain connected to V DD , acts generally like a capacitor to reduce noise on V BIAS node 172. IREF node 100 also is shorted to V BIAS node 172, which is made accessible, for example, through a pin of the packaged integrated circuit. The power-down circuit 20 shown in Figure 4B operates in conjunction with the operational amplifier 22 as follows. In the current-controlled mode, IREF terminal 100 is connected to a current source, such as source 10 of Figure 2, and also shorted to V BIAS node 172, and OPA node 170 in the power-down circuit 20, which is accessible, for example, through a pin of the packaged integrated circuit, is left floating. These connections are shown in Figure 5 for an illustrative integrated circuit 200 and switch 202, which may be implemented mechanically or electrically. The voltage at the gate of n-channel MOSFET 158 is established to turn on transistor 158. In the embodiment of Figure 4B, two volts is sufficient to turn on transistor 158. When transistor 158 is "on", i.e. conducting, OPA node 170 is pulled toward ground. The voltage at the output of inverter 154 is established by the ratio of the p-type and n-type transistors comprising inverter 154. One example of a ratio used in the present invention is where the p-type transistor has a width of 2.5µ and a length of 20µ and the n-type transistor has a width of 20µ and a length of 2.5µ. Transistor 156 acts as a loading element to eliminate noise which would otherwise be created by this fast circuit. When OPA node 170 is pulled to ground, a logical zero signal is asserted at the input of inverter 160. Inverter 160 inverts this signal into a logical one, which is in turn inverted by inverter 162 to produce a logical zero. Hence, the signal delivered to PDZ node 152 is zero. As seen in Figure 4, inverter 164 inverts the logical zero signal and outputs a signal of logical one to PD node 150. A logical one signal to PD node 150 turns off transistor 132 of the operational amplifier circuit branch 130. Therefore, no current flows through circuit branch 130. It follows that the gates of transistors 134, 136, 138, 116, 126, 118 and 128 are floating. If there is no bias, then the operational amplifier 22 enters into a power-down state in which the transistors 102, 104, 106, 108, 112, 114, 116, 118, 122, 124, 126 and 128 turn off. Because node 152 is a logical zero signal in the current-controlled mode, transistors 146 and 148 are "on". Transistor 149 functions to stabilize the circuit, and serves as a customized element of the circuit. V BIAS node 172 has a voltage of V DD - 2V TD where V DD is the source voltage and V TD is the threshold voltage drop of transistors 146 and 148. Typically, V DD is five volts and the voltage V TD is about one volt. The voltage at V BIAS node 172 is applied to the gate of p-channel MOSFET 174, which has its source connected to V DD and its drain connected to IREF node 100. The value of V BIAS is suitably selected to operate transistor 174 in its linear region. In the voltage-controlled mode, IREF terminal 100 is connected to a suitable resistor 8 (Figure 2) of, for example, 147 ohms; the VREF terminal 102, which is accessible, for example, through a pin of the packaged integrated circuit, is connected to a suitable voltage reference source 7 (Figure 2) of, for example, 1.235 volts; and OPA node 170 of power-down circuit 20 is shorted to V BIAS node 172. These connections are shown in Figure 6 for an illustrative integrated circuit package 200 and switch 202. Hence, the voltage at V BIAS node 172 is introduced to OPA node 170, although a separate voltage reference may be used if desired. Typically, the voltage applied to OPA node 170 is three volts. Transistor 158 is ineffective in pulling down V BIAS . Three volts is considered a "high" voltage. Therefore, in the voltage-controlled mode, a logical one signal is inverted by inverter 160. The resulting logical zero signal is subsequently inverted to a logical one signal by inverter 162 and becomes the voltage applied to node PDZ. Inverter 164 inverts the logical one signal to zero which is applied to PD node 150. A logical one at PDZ node 152 causes transistors 146 and 148 to turn off. The logical zero signal at PD node 150 will turn on all the other transistors in the operational amplifier 22 required to establish suitable bias potentials of the commonly connected gates of transistors 116 and 126, and at the commonly connected gates of transistors 118 and 128. Hence, the voltage-controlled mode is established with IREF equal to 8.4 milliamps (1.235/147 amps). The width and length of the transistors in Figures 4A and 4B are as set forth in Table 1, in which the first number is channel width in microns and the second number is channel length in microns. (Transistor # (Width:Length)) 102 (320:4) 104 (400:2) 106 (120:4) 108 (120:4) 112 (160:4) 114 (200:2) 116 (60:4) 118 (120:6) 122 (160:4) 124 (200:2) 126 (60:4) 128 (120:6) 132 (50:2) 134 (10:10) 136 (30:6) 138 (30:6) 140 (3:6) 142 (20:4) 144 (20:4) 146 (11:2) 148 (5.5:4) 149 (360:4) 154P (2.5:20) 154N (20:2.5) 156 (10:10) 158 (5.5:50) 160P (11:44) 160N (11:44) 174 (2500:4) While our invention has been described with respect to certain embodiments, the scope of the present invention is defined by the appended claims and is not necessarily limited to the embodiments described herein, which are merely illustrative. For example, the fabrication technology, the specific voltage levels, and the specific arrangement of conventional circuits are illustrative.

Claims: A reference generator, controllably operable in a voltage mode or a current mode, comprising: means (12) for providing a reference current path, two voltage input means (VREF. 27), one (27) of which is coupled to the reference current path providing means (12), and means (22) for amplifying a voltage difference between the two voltage input means with high gain and bandwidth, the amplifying means (22) having an output coupled to the reference current path providing means (12), and characterised in that the reference generator further comprises means (20) for powering down the amplifying means (22), the powering down means (20) being responsive to a controlled transition from voltage mode operation to current mode operation for selectively disabling current flow in the amplifying means (22) and responsive to a controlled transition from current mode operation to voltage mode operation for selectively enabling current flow in the amplifying means (22). A reference generator as claimed in claim 1 wherein the reference current path providing means (12) comprises means for indicating a bias voltage (VBIAS) coupled to the output of the amplifying means (22), and wherein, in the current mode, the bias voltage indicating means (VBIAS) is connected to a current source (10) and wherein, in the voltage mode, the voltage bias indicating means (VBIAS) is disconnected from the current source (10). A reference generator according to claim 1, wherein the amplifying means (22) comprises an operational amplifier (22). A reference generator according to claim 3, wherein the amplifying means (22) comprises an operational amplifier (22) having first and second input terminals (-,+) coupled to said two voltage input means (VREF 27) and said reference current path providing means comprises a transistor (12) and the one voltage input means (27) comprising and an IREF node (27), the transistor (12) having a control terminal connected to an output of the operational amplifier (12), wherein the other voltage input means (VREF) comprises a VREF node connected to the first input terminal (-) of the operational amplifier (22); the IREF node (27) is connected to the second input terminal (+) of the operational amplifier (22); the bias voltage indicating means comprises a VBIAS node (28) connected to the control terminal of the transistor (12); and the power-down means (20) is connected to the operational amplifier (22); wherein for a voltage-controlled mode, the IREF node (27) is connected to a resistor (8) for obtaining a voltage, the VREF node is connected to a reference voltage, and the power-down means (20) is responsive to a first condition on a control terminal thereof indicative of the voltage-controlled mode for powering-up the operational amplifier (22); and wherein for a current-controlled mode, the IREF node (27) is connected to a current source (10) and to the VBIAS node (28), and the power-down means (20) is responsive to a second condition on the control terminal thereof indicative of the current-controlled mode for powering-down the operational amplifier (22). A reference generator as claimed in claim 4, wherein: the control terminal of the power-down means (20) is node OPA, the first condition of the OPA node being a connection to the VBIAS node, and the second condition of the OPA node being a floating condition. A reference generator as claimed in any of claims 3 to 5 wherein the operational amplifier (22) comprises a biasing circuit (130) connected to biasing points (116,118,126,128) in the operational amplifier, the biasing circuit (130) being responsive to the power-down circuit (22) for furnishing bias potentials to the biasing points (116,118,126,128) during the voltage-controlled mode, and for floating the biasing points (116,118,126,128) during the current-controlled mode. A reference generator according to any of claims 3 to 6 wherein the operational amplifier comprises: a first transistor (102) having a source connected to a voltage source (VDD); a second transistor (104) having a source connected to a drain of the first transistor (102); a third transistor (106), a gate of the third transistor (106) being connected to a reference current source (10) in a current-controlled mode or a resistor (8) in a voltage-controlled mode, and a source of the third transistor (106) being connected to a drain of the second transistor (104); a fourth transistor (108), a gate of the fourth transistor (108) being connected to a reference voltage source (VREF) and a source of the fourth transistor (108) connected to the drain of the second transistor (104); a fifth transistor (112) having a source connected to the voltage source (VDD); a sixth transistor (122) having a source connected to the voltage source (VDD); a seventh transistor (114) having a source connected to a drain of the fifth transistor (112); an eighth transistor (124) having a source connected to a drain of the sixth transistor (122); a ninth transistor (116) having a drain connected to a drain of the seventh transistor (114); a tenth transistor (126) having a drain connected to a drain of the eighth transistor (124); an eleventh transistor (118), a drain of the eleventh transistor (118) being connected to a source of the ninth transistor (116), and a source of the eleventh transistor (118) being connected to ground; a twelfth transistor (128), a drain of the twelfth transistor (128) being connected to a source of the tenth transistor (126), and a source of the twelfth transistor (128) being connected to the ground; a thirteenth transistor (132) having a source connected to the voltage source (VDD); a fourteenth transistor (134) having a source connected to a drain of the thirteenth transistor (132); a fifteenth transistor (136) having a drain connected to a source of the fourteenth transistor (134); and a sixteenth transistor (138), a drain of the sixteenth transistor (138) being connected to a source of the fifteenth transistor (136), and a source of the sixteenth transistor (138) being connected to the ground; wherein gates of the first, fifth, and sixth transistors are connected to the source of the eighth transistor, gates of the second, seventh, and eighth transistors are connected to the drain of the ninth transistor, drains of the third and fourth transistors are connected to the drain of the eleventh transistor and to the drain of the twelfth transistor, respectively; wherein gates to the ninth, tenth, fourteenth, and fifteenth transistors are connected to a drain of the fifteenth transistor, and gates of the eleventh, twelfth, and sixteenth transistors are connected to the source of the fifteenth transistor; and wherein a logical one signal applied to a gate of the thirteenth transistor powers down the operational amplifier. A reference generator according to claim 7, wherein the operational amplifier further comprises a seventeenth transistor (146) having a source connected to the voltage source (VDD); and an eighteenth transistor (148), a source of the eighteenth transistor (148) being connected to a drain of the seventeenth transistor (146), a drain and gate of the eighteenth transistor (148) being connected to the drain of the eighth transistor (124); wherein a logical one signal to a gate of the seventeenth transistor (146) powers up the operational amplifier. A reference generator according to claim 8, wherein the power-down circuit (20) comprises a nineteenth transistor (158), a source of the nineteenth transistor (158) being connected to ground, and a drain of the nineteenth transistor (158) being connected to the gate (PDZ) of the eighteenth transistor (148) when the operational amplifier (22) is in a voltage-controlled mode or left floating in a current-controlled mode; a first inverter (170) having an input and an output connected to a gate of the nineteenth transistor (158); a second invertor (160) having an input connected to the drain of the nineteenth transistor (158); a third inverter (162) having an input connected to the output of the second inverter (160); and a fourth inverter (164) having an input connected to the output of the third inverter (162); wherein the output of the fourth inverter (164) is connected to the gate of the thirteenth transistor (132); and wherein the ouput of the third inverter (162) is connected to the gate of the seventeenth transistor (146).

Inventors: CHEN FRED TUN-JEN, HSU WEI-CHAN, NGUYEN CHINH D, CHEN, FRED TUN-JEN, HSU, WEI-CHAN, NGUYEN, CHINH D.
Applicants: WINBOND ELECTRONICS CORP, WINBOND ELECTRONICS CORPORATION
Application year: 1992
Main classification: G05F1
IPC codes: G05F1, H03F3, G06G7