Capacitive circuit

Abstract: A capacitive circuit (10), which is incorporated in an integrated circuit, includes a high-pass type non-inverting amplifier (12) which receives an input signal (ei) and a differential amplifier (14) which receives the input signal and an output signal (eo) of the non-inverting amplifier. A differential component between the both signals is detected by the differential amplifier and fed-back to the input signal, whereby an input impedance shows a capacitive characteristic because the input signal is phase-shifted by 90 degrees.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a capacitive circuit. More specifically, the present invention relates to a novel capacitive circuit capable of forming an equivalent capacitor having a relatively large capacitance value in an integrated circuit. Description of the Prior Art In a conventional integrated circuit, an equivalent capacitor is formed by utilizing a PN junction. In such a prior art, although it is possible to change a capacitance value by changing a voltage applied to the PN junction; however, the capacitance value was normally small and a variable range thereof was also narrow. A capacitive circuit according to the preamble of claim 1 is known from WO-A-81/02819. In this capacitive circuit is included a capacitance multiplier including capacitance multipliers in different combinations operatively coupled to a DC bias controlled current circuit. The capacitance multiplier circuit can be used to construct a predictable low pass, bandpass or high pass filter circuit with frequency characteristics that do not vary over temperture. Elektor Electronics, Vol. 13, No 149, October 1987, Canterbury, GB, pages 54 to 55, A.B. Bradshaw: "The Posivite Impedenance Converter" shows a positive impedance converter using operational amplifiers four of which are required to simulate a balance inductor. From U. Titze and Ch. Schenk: Halbleiter-Schaltungstechnik, 9th edition, Pringer, Berlin, 1990, pages 380 to 387 a negative impedance converter is known which can realize negative impedances by means of an UNIC or an INIC which change the polarity of the voltage which constant current or the current with constant voltage, respectively. SUMMARY OF THE INVENTION Therefore, a principal of the present invention is to provide a novel capacitive circuit. Another object of the present invention is to provide a capacitive circuit capable of forming an equivalent capacitor having a relatively large capacitance value in an integrated circuit. Another object of the present invention is to provide a capacitive circuit capable of forming an equivalent capacitor having a wider variable range. Another object of the present invention is to provide a capacitive circuit capable of forming an equivalent capacitor which can be utilized as a coupling capacitor. Another object of the present invention is to provide a capacitive circuit capable of forming an equivalent capacitor by which only lesser distortion of a signal occurs. These objects are solved by the features of claim 1. Further embodiments of the invention are shown in the subclaims. The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram showing one embodiment according to the present invention; Figure 2 is a circuit diagram showing a modified embodiment of Figure 1 embodiment; Figure 3 is a circuit diagram showing an example in which Figure 2 embodiment is utilized in an LC resonance circuit; Figure 4 is a circuit diagram showing another embodiment according to the present invention; Figure 5 is a circuit diagram showing a modified embodiment of Figure 4 embodiment; Figure 6 is a circuit diagram showing another embodiment according to the present invention; Figure 7 is a circuit diagram showing an equivalent capacitive circuit; Figure 8 is a circuit diagram showing another embodiment according to the present invention; Figure 9 is a circuit diagram showing a modified embodiment of Figure 8 embodiment; and Figure 10 is an equivalent circuit diagram of Figure 9 embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to Figure 1, a capacitive circuit 10 of this embodiment shown includes a high-pass type non-inverting amplifier 12 and a differential amplifier 14, and an input signal e i is given from an input terminal 16. The input signal e i is applied to a base of a transistor Q2 which is an input end of the non-inverting amplifier 12 through a transistor Q1 constituting an emitter-follower. The transistor Q2 constitutes a differential pair 18 together with a transistor Q3, and an output of the differential pair 18 is outputted to an emitter of a transistor Q4 from a collector of the transistor Q3. To the emitter of the transistor Q4, a series circuit of a resistor R and a capacitor C is connected. The output of the differential pair 18, that is, the emitter of the transistor Q4 is connected to a base of a transistor Q5 of the differential amplifier 14, and a base of a transistor Q6 which constitutes a differential pair 20 together with a transistor Q5 is connected to an emitter of the transistor Q1, that is, to the input end of the amplifier 12. An output of the differential pair 20 is outputted to a collector of the transistor Q5, and then fed-back via a feed-back path to a base of the transistor Q1, that is, the input terminal 16. In addition, in the capacitive circuit 10 shown in Figure 1, reference numerals 22, 24, 26, 28, 30 and 32 denote constant current sources (DC current sources), respectively, and a reference numeral 34 denotes a bias voltage source (DC voltage source). In the capacitive circuit 10 of Figure 1, an output signal e o of the non-inverting amplifier 12 which comes out at the emitter of the transistor Q4 is given by the following equation (1). e o = (1 + R 1/jω C ) e i = (1 + jω CR)e i The output signal e o of the non-inverting amplifier 12 is applied to one input of the differential pair 20 of the differential amplifier 14, and the other input of the differential pair 20 receives the input signal e i . Therefore, a current i which flows-in from the input terminal 16 is given by the following equation (2) when a differential resister of each of the transistors Q5 and Q6 is r e . i = e o -e i 2r e = 1 2r e {(1+jω CR) e i - e i } = jω CR 2r e e i Then, on the assumption that CR/2r e = C eq , the equation (2) can be modified as follows: i = e i /( 1 jω C eq ) Therefore, a phase of the current i is advanced with respect to the input signal e i by 90 degrees, and therefore, a capacitive characteristic can be obtained. A capacitance value of the equivalent capacitor C eq formed in the capacitive circuit 10 is given by the following equation (4). C eq = CR 2r e = CR 52 I 0 ∵ r e = 26[mV] I 0 [mA] Thus, the capacitance value of the equivalent capacitor C eq which is obtained by the capacitive circuit 10 shown in Figure 1 is determined by the capacitor C, the resistor R and a bias current I 0 of the differential amplifier 14. Therefore, in this embodiment shown in Figure 1, by utilizing a variable constant current source 32 capable of changing the bias current I 0 , it is possible to obtain a variable equivalent capacitance circuit. In addition, in this embodiment, as seen from the equation (4), it is possible to make the equivalent capacitor C eq large in proportion to the bias current I 0 . A capacitive circuit 10 shown in Figure 2 includes attenuators 36 and 38 which are added to the non-inverting amplifier 12 and the differential amplifier 14 shown in Figure 1, respectively. More specifically, the attenuator 36 includes transistors Q7 and Q8, and an input of the transistor Q7 is connected to an output of the transistor Q1 via a resistor R 1 , and an input of the transistor Q8 is connected to the bias voltage source 34. Then, constant current sources 40 and 42 are utilized for the attenuation 36 in this embodiment, and a diode 44 is inserted between the constant current source 40 and a collector of the transistor Q7. The diode 44 and a transistor Q11 are utilized for adjusting of biases of the two attenuators 36 and 38. On the other hand, the attenuator 38 includes transistors Q9 and Q10, and an input of the transistor Q9 is connected to the output of the transistor Q4 via a resistor R 2 , and an input of the transistor Q10 is connected to an emitter of the transistor Q11. Constant current sources 46 and 48 are utilized for the attenuator 38 in the embodiment. In addition, the base of the transistor Q6 of the differential pair 20 is also connected to the emitter of the transistor Q11, and a base of the transistor Q11 is fed-back to a point between the constant current source 40 and the diode 44. Furthermore, a constant current source 50 is inserted between the emitter of the transistor Q11 and the ground. In the capacitive circuit 10 shown in Figure 2, when the input signal e i is applied to the input terminal 16, the input signal e i is attenuated by the attenuator 36, and an output signal e A of the attenuator 36 is given by the following equation (5) on the assumption that a differential resistor of each of the transistors Q7 and Q8 is r el and an attenuation factor of the attenuator 36 is k 1 . e A = k 1 e i , k 1 = 2r e1 R 1 + 2r e1 The output signal e A shown by the equation (5) is amplified by the non-inverting amplifier 12 as similar to the embodiment shown in Figure 1, and therefore, an output signal e B of the non-inverting amplifier 12 is given by the following equation (6). e B = (1 + jω CR) e A In addition, a signal which is applied to a point between the bases of the transistors Q5 and Q6 is a signal obtained by attenuating a signal (e B - e A ) by means of the attenuator 38, and therefore, the signal is given by the following equation (7) on the assumption that a differential resistor of each of the transistors Q9 and Q10 is r e2 and an attenuation factor of the attenuator 38 is k 2 . k 2 (e B - e A ), k 2 = 2r e2 R 2 + 2r e2 Therefore, a current which flows-in from the input terminal 16 is given by the following equation (8) from the above described equation (5) through equation (7), and the equivalent capacitor C eq is given by the following equation (9). i = k 2 (e B - e A ) 2r e = k 2 ·jω CR 2r e e A = k 1 ·k 2 ·jω CR 2r e e i = e i · { 1 jω k 1 ·k 2 CR 2r e } -1 C eq = k 1 k 2 CR 2r e If R 1 = R 2 and I 1 = I 2 , the equation (9) is modified as shown by the following equation (10) because k 1 = k 2 . C eq = ( 2r e1 R 1 + 2r e1 )2 . CR 2r e Then, if R 1 >> 2r e1 , R 1 + 2r e1 ≒ R 1 is obtained, the equation (10) can be modified as shown by the following equation (11). C eq = 2CR r e R 1 2 . r e1 2 = 2 x 26 2 x CR r e R 1 2 . 1 I 1 2 ∵ r e1 = 26(mV) I 1 (mA) [Ω] Thus, in the capacitive circuit 10 shown in Figure 2, by controlling a bias current I 1 of the constant current source 40 for the attenuator 36, it is possible to obtain the equivalent capacitor C eq having a capacitance value which is in reverse-proportion to a square of the bias current I 1 . In a case where an LC resonance circuit shown in Figure 3 is constructed by utilizing the embodiment shown in Figure 2, since a resonance frequency f c of the LC resonance circuit is given by the following equation (12), it is possible to change the resonance frequency f c in a linear manner by adjusting the bias current I 1 . f c = 1 2π LC eq With reference to Figure 4, a capacitive circuit 100 of this embodiment shown includes a high-pass type non-inverting amplifier 112 and a differential amplifier 114, and an input signal e A is given from an input terminal 116. The input signal e A is applied to a base of a transistor Q2 which is a non-inverting input of the high-pass type amplifier 112 through a transistor Q1 constituting an emitter-follower. The transistor Q2 constitutes a differential pair 118 together with a transistor Q3, and an output of the differential pair 118 is outputted to an emitter of a transistor Q4 from a collector of the transistor Q3. To the emitter of the transistor Q4, a series circuit of a resistor R and a capacitor C is connected. To a base of the transistor Q3, an output signal e B from an output terminal 120 is inputted through a transistor Q5 constituting an emitter-follower and the capacitor C. Then, the output of the differential pair 118, that is, the emitter of the transistor Q4 is connected to a base of a transistor Q6 of the differential amplifier 114, and a base of a transistor Q7 which constitutes a differential pair 122 together with the transistor Q6 is connected to an output of the transistor Q1. An output of the transistor Q6 is connected to a base of the transistor Q1, that is, the input terminal 116, and an output of the transistor Q7 is connected to the output terminal 120. In addition, in the capacitive circuit 100 shown in Figure 4, reference numerals 124, 126, 128, 130, 132, 134, 136 and 138 denote constant current sources (DC current sources), respectively. In the capacitive circuit 100 of Figure 4, an output signal e o of the non-inverting amplifier 112 which comes out at the emitter of the transistor Q4 is given by the following equation (13). e o = (1 + jω CR)e A - jω CRe B The output signal e o of the non-inverting amplifier 112 is applied to one input of the differential pair 122 of the differential amplifier 114, and the other input of the differential pair 122 receives the input signal e A . Therefore, a current i which flows-in from the input terminal 116 and then flows-out from the output terminal 120 is given by the following equation (14) when a differential resistor of each of the transistors Q6 and Q7 is r e . i = e o - e A 2r e Then, r e is equal to 26 mV/I 0 mA, that is, r e = 26 mV/I 0 mA is obtained. Therefore, if the equation (14) is substituted with the equation (13), the following equation (15) can be obtained. i = jω C 2r e (e A - e B ) In addition, on the assumption that CR/2r e = C eq , the equation (15) can be modified as follows: i = jω C eq (e A - e B ) = (e A - e B )/( 1 jω C eq ) Therefore, a capacitive characteristic can be obtained between the input terminal 116 and the output terminal 120, and accordingly, an equivalent capacitor C eq in the capacitive circuit 100 is given by the following equation (17). C eq = CR 52 I o Thus, a capacitance value of the equivalent capacitor C eq which is obtained by the capacitive circuit 100 shown in Figure 4 is determined by the capacitor C, the resistor R and a bias current I 0 . Therefore, in this embodiment shown in Figure 4, by utilizing a variable constant current source 136 or 138 capable of changing the bias current I 0 , it is possible to obtain a variable equivalent capacitance circuit. In addition, in this embodiment, the capacitance value of the equivalent capacitor C eq is in proportion to the bias current I 0 . For example, assuming that C= 30 pF, R=100 kΩ , I 0 =0.1 mA, the capacitance value of the equivalent capacitance C eq becomes 5800 pF approximately. A capacitive circuit 100 shown in Figure 5 includes attenuators 140, 142 and 144 are added to Figure 4 embodiment. More specifically, the attenuator 140 includes transistors Q8 and Q9, and an input of the transistor Q8 is connected to the output of the transistor Q1 via a resistor R 1 , and an input of the transistor Q9 is connected to a bias voltage source 146. At each of emitters of the transistors Q8 and Q9, a differential resistor r e1 is formed. Then, constant current sources 148 and 150 are utilized for the attenuator 140 in this embodiment, and a diode 152 is inserted between the constant current source 148 and a collector of the transistor Q8. In addition, the attenuator 142 includes transistors Q10 and Q11, and an input of the transistor Q10 is connected to the output of the transistor Q4 via a resistor R 1 , and an input of the transistor Q11 is connected to an emitter of the transistor Q12. At each of emitters of the transistors Q10 and Q11, a differential resistor r e1 is formed. Constant current sources 154 and 156 are utilized for the attenuator 142 in the embodiment. In addition, the base of the transistor Q7 is connected to the emitter of the transistor Q12, and a base of the transistor Q12 is fed-back to a point between the constant current source 148 and the diode 152. Furthermore, the attenuator 144 includes transistors Q14 and Q15, and an input of the transistor Q15 is connected to the emitter of the transistor Q5 via a resistor R 1 . A differential resistor r e1 is formed at each of emitters of the transistors Q14 and Q15. In Figure 5, reference numerals 158, 160 and 162 denote constant current sources, respectively. As similar to Figure 4 embodiment, in the capacitive circuit 100 shown in Figure 5, the output signal e o from the transistor Q4 of the high-pass type amplifier 112 is given by the following equation (18) on the assumption that an attenuator factor of each of the attenuators 140, 142 and 144 is k although a detailed description of the development is omitted here. e o = k(1 + jω CR)e A - jω CR·ke B k = 2r e1 R 1 + 2r e1 , ∵ r e1 [Ω] = 26[mV] I 1 [mA] Therefore, since a signal of k(e o - ke A ) is applied between the bases of the transistors Q6 and Q7, the current which flows-in from the input terminal 116 is given by the following equation (19) , and the equivalent capacitor C eq is given by the following equations (20). i = k(e o - ke A ) 2r e = jω k 2 CR 2r e (e A - e B ) C eq = k 2 CR 2r e = CR 52 I o ·k 2 = CR 52 I 0 · ( 2r e1 R 1 +2r e1 ) 2 If it is assumed that R 1 ≽ 2r e , the following equation (21) is also obtained. C eq ≒ CR 52 I 0 · 4r e1 2 R 1 2 = 52CR R 1 2 · I 0 · I 1 -2 Thus, in the capacitive circuit 100 shown in Figure 5, by controlling the bias current I 0 or I 1 , it is possible to change the capacitance value of the equivalent capacitor C eq in a manner that it is changed to be in proportion to the bias current I 0 or in reverse-proportion to a square of the bias current I 1 . With reference to Figure 6, a capacitive circuit 200 of this embodiment shown includes a negative feedback amplifiers 212 and 214, and a differential amplifier 216, and an input signal e i is given from an input terminal 218. The input signal e i is applied to a base of a transistor Q1 which is a inverting input of the negative feed-back amplifier 212 through a capacitor C. The transistor Q1 constitutes a differential pair 220 together with a transistor Q2, and a base of the transistor Q2 becomes a non-inverting input thereof of the negative feed-back amplifier 212, and an output signal e o which is outputted at an output terminal 222 is inputted to the transistor Q2. An output of the differential pair 220 is outputted as a signal e A through the transistors Q1 and Q3. A feed-back resistor R is inserted between the base of the transistor Q1 and an emitter of the transistor Q3. Therefore, the signal e A is applied to a base of a transistor Q4 which becomes one input of the differential amplifier 216 via the feed-back resistor R, and a base of a transistor Q5 which becomes the other input of the differential amplifier 216 is connected to the output terminal 222. The transistor Q5 constitutes a differential pair 224 together with the transistor Q4. At each of emitters of the transistors Q4 and Q5, a differential resistor r e is formed. Then, an output current from the collector of the transistor Q5 flows to a bias voltage source Vx via a load resistor RL, and then fed-back to the base of the transistor Q6. The base of the transistor Q7 is connected to the bias voltage source Vx. An output of the transistor Q6 is inputted to a base of a transistor Q8 which is an inverting input of the negative feed-back amplifier 214 via a resistor R 1 . An output of the transistor Q7 is applied to a base of a transistor Q9 which constitutes a differential pair 226 together with a transistor Q8, that is, to a non-inverting input of the negative feed-back amplifier 214. An output of the differential pair 226, i.e. the negative feed-back amplifier 214 is outputted at an emitter of a transistor Q10 from a collector of the transistor Q8, and a feedback resistor R 2 is connected between the emitter of the transistor Q10 and the base of the transistor Q8. In addition, the emitter of the transistor Q10 is connected to the ground. In addition, in the capacitive circuit 200 shown in Figure 6, reference numerals 228, 130, 232, 234, 236, 238, 240, 242, 244, 246, 248 and 250 denote constant current sources (DC current sources), respectively, and a constant current 2I 0 flows in the constant current source 240 and a constant current I 0 flows in the constant current source 250. As described above, the reference symbol Vx denotes the bias voltage source (DC voltage source). In the capacitive circuit 200 of Figure 6, since the input signal e i is inputted to the base of the transistor Q1 through the capacitor C and an output signal e o is inputted to the base of the transistor Q2, the signal which comes out at the emitter of the transistor Q3 is given by the following equation (22). e A = {1 + R/( 1 jω C )}e o - R/ 1 jω C e i = (1 + jω CR)e o - jω CRe i Then, the signal e A is inputted to the base of the transistor Q4, and the output signal e o is inputted to the base of the transistor Q5. A differential signal according to the signal e A and the output signal e o is outputted from the collector of the transistor Q5, and then fed-back to the base of the transistor Q6. At this time, a current flowing in the load resistor R L is given by the following equation (23). i = (e A - ke o ) 2r e = jω CR(e o - e i ) 2r e The base signal of the transistor Q6 is the input signal of the negative feed-back amplifier 214 and a signal which comes out at the emitter of the transistor Q10 is the above described output signal e o , and therefore, if R 1 = R 2 , the base signal of the transistor Q6 can be represented by -e o . Therefore, the current i can be represented by the following equation (24). i = -e o R L Therefore, a result shown by the following equation (25) can be obtained by the equations (23) and (24). - e o R L = jω CR(e o - e i ) 2r e (jω C 2r e + 1 R L )e o = jω CR 2r e · e i ∵ e o e i = R L /(R L +( 1 jω CR/2r e ) A transfer characteristic of a capacitive circuit shown in Figure 7 can be represented by the following equation (26). e o e i = R o /( R o + 1 jω C o ) R o = R A R B R A + R B If the result shown by the equation (25) is compared with the equation (26), the both become coincident with each other. Therefore, the output signal e o from the capacitive circuit 200 indicates a capacitive characteristic equivalently. In addition, a capacitance value of an equivalent capacitance C eq thus obtained can be given by the following equation (27). C eq = CR 2r e = CR 52 I 0 [ ∵ r e = 26(mV) I 0 (mA) ] In the equation (27), values of the capacitor C and the resistor R are fixed. Therefore, if the I 0 is set such that (RI 0 /52)>1 is obtained in the equation (27), it is possible to make the equivalent capacitor C eq larger than the capacitor C, and by increasing the current I 0 , capacitance value of the the equivalent capacitor C eq can be increased in proportion to the current I 0 . Accordingly, since the equivalent capacitor C eq can be set at a desired value by controlling the current I 0 , it is possible to incorporate an equivalent capacitor having a relatively large capacitance in an integrated circuit. With reference to Figure 8, a capacitive circuit 300 of this embodiment shown includes an input terminal 312 to which an input signal e i is applied. The input terminal 312 is connected to a base of a transistor T10 which constitutes a common-emitter type amplifier, and an emitter of the transistor T10 is connected to a resistor R 10 . A collector of the transistor T10 is connected to a collector of a transistor T11 and a capacitor C 10 . An emitter of the transistor T11 is connected to a resistor R 11 . In order to suppress a fluctuation of a DC level at an output, a DC voltage suppression circuit 314 is provided. The DC voltage suppression circuit 314 suppresses an AC component of the output which comes out at the collector of the transistor T11 and negatively feeds-back only a DC component to the transistor T10. More specifically, the collector of the transistor T10 is connected to a base of transistor T12, and a base of the transistor T11 is connected to a base of a transistor T13. The transistor T11 is utilized as a current source for the transistor T10. The output obtained at the collector of the transistor T10 is withdrawn from an emitter of the transistor T12 as an output signal e o . On the other hand, an AC component of an output signal which comes out at an emitter of the transistor T12 is suppressed by the resistor R12, capacitor C11 and resistor R13, and therefore, only the DC component is supplied to a base of a transistor T14. Therefore, a voltage corresponding to a base voltage of a transistor T15 comes out at a collector of the transistor T14, and a current flows in the transistor T14, and therefore, a voltage drop due to the current is supplied to the base of the transistor T11. Accordingly, the emitter of the transistor T10 becomes coincident in potential with an emitter of a transistor T16, and thus, the DC level of the output at the collector of the transistor T10 is made stable by a constant voltage source B1. In the capacitive circuit 300 shown in Figure 8, the transistor constitutes a common-emitter amplifier, and an amplification degree A thereof is represented by the following equation (28). A = 1/jω C 10 R 10 Therefore, the output of the collector of the transistor T10 becomes l/jω C 10 ·R 10 , only an imaginary part remains. Then, the output is withdrawn from an output terminal 316 as the output signal e o through the emitter of the transistor T12, and the output signal e o can be represented by the following equation (29). e o = e i 1 jω C10·R10 Thus, the output signal e o becomes equal to that an imaginary part is multiplied by the input signal e i , and therefore, the output signal e o is phase-shifted with respect to the input signal e i by 90 degrees. In addition, the capacitor C 10 may be replaced with the equivalent capacitor C eq shown in Figure 1, for example. An embodiment of this case is shown in Figure 9. Therefore, Figure 9 can be modified as shown in Figure 10 by using the equivalent capacitor C eq . In Figure 10 embodiment, a differential pair composed of transistors T20 and T21 constitutes a feed-back amplifier in which a signal equivalent to the input signal e i is outputted to bases of the transistors T20 and T21, and therefore, a current i ceq flowing the equivalent capacitor C eq is given by the following equation (30). iC eq = jω C eq ·e i Then, jω C eq is only an imaginary part, and therefore, the current i ceq is shifted by 90 degrees with respect to the input signal e i . Accordingly, the output signal e o can be withdrawn from a path of the current i ceq . By the Figure 9 embodiment, it is possible to omit the capacitor C 11 of Figure 8 embodiment, and therefore, there is an advantage that a capacitor having a large capacitance value is not needed to be incorporated an integrated circuit. I addition, each of the above described capacitive circuit can be incorporated in an integrated circuit for processing a video signal and/or an audio signal. Such an integrated circuit is used in a video signal reproducing apparatus such as a television receiver, video tape recorder, camcorder, video disc player, and etc. and an audio signal reproducing apparatus such as a radio receiver, tape recorder, audio disc player, and etc. Especially, the embodiment shown in Figure 4 or Figure 5, or the embodiment shown in Figure 6 is suitable for a coupling capacitor, and the embodiment shown in Figure 8 or Figure 9 is suitable for a phase-shifting circuit for shifting a phase of a signal. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A capacitive circuit, comprising: an input terminal (16) for inputting an input signal; a high-pass type amplifier (12) for receiving said input signal; and a differential amplifier (14), characterized in that said differential amplifier (14) detects a difference component between an output signal of said high-pass type amplifier (12) and said input signal; and said capacitive circuit further comprises a feed-back means for feeding-back said difference component to said input terminal (16), whereby a phase of a current (i) which flows into the input terminal (16) is phase-shifted with respect to the input signal by 90 degrees. A capacitive circuit according to claim 1, further comprising a first attenuator (36) for attenuating a signal inputted to said high-pass type amplifier (12); and a second attenuator (38) for attenuating a signal inputted to said differential amplifier (14). A capacitive circuit according to claim 1 or 2, wherein said differential amplifier (14) includes two outputs, and one output of said differential amplifier is connected to said input terminal (16) and the other output of said differential amplifier is connected to an output terminal (120). A capacitive circuit, comprising: an input terminal (218) for inputting an input signal (e i ); an ouput terminal (222) for outputting an output signal (e A ); and a differential amplifier (216), characterized by a first negative feed-back amplifier (212) having an inverting input which is connected to said input terminal (218) via a capacitor (C) and a non-inverting input which is connected to said output terminal (222); and a second negative feed-back amplifier (214) having a non-inverting input which receives an input according to an output of said differential amplifier (216) through a load resistor (R L ) and an inverting input which is connected to said output terminal (222) through a second resistor (R 2 ), an output of said second negative feed-back amplifier (214) being applied to said non-inverting input of said first negative feed-back amplifier (212) ; wherein said differential amplifier (216) has a first input which is connected to said inverting input of said first negative feed-back amplifier (212) through a first resistor (R) and receives an output of said first negative feed-back amplifier (212) and a second input which is connected to said output terminal (222). A video signal reproducing apparatus which includes an integrated circuit for processing a video signal, said integrated circuit comprising a capacitive circuit according to claim 1. An audio signal reproducing apparatus which includes an integrated circuit for processing an audio signal, said integrated circuit comprising a capacitive circuit according to claim 1. A video signal reproducing apparatus which includes an integrated circuit for processing a video signal, said integrated circuit comprising a capacitive circuit according to claim 4. An audio signal reproducing apparatus which includes an integrated circuit for processing an audio signal, said integrated circuit comprising a capacitive circuit according to claim 4.

Inventors: HONDA FUMIAKI, HOSOYA NOBUKAZU, HONDA, FUMIAKI, HOSOYA, NOBUKAZU
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1992
Main classification: H03H11
IPC codes: H03H11