Semiconductor memory

Abstract: The present invention provides a nonvolatile semiconductor memory that is partially rewritable. The present invention combines a large-capacity mask ROM (1) with a small-capacity PROM (2) between which selection is made for use as required.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a nonvolatile semiconductor memory in general, and to a nonvolatile semiconductor memory that is partially rewritable and inexpensive in construction in particular. 2. Description of the Prior Art: Nonvolatile semiconductor memories are known in the art. Masked read-only memories (mask ROMs) have been used for applications that require low-cost large-volume production. For low volume-production or for applications that may subsequently require altering the stored data, programmable read-only memories (PROMs) have been the logical choice. The mask ROM is a type of read-only memory in which data is written using a mask during fabrication of the memory. Therefore, the stored data cannot be altered by any means once the memory is fabricated, but the advantage is that the mask ROM can be manufactured economically by large-volume production. On the other hand, the PROM, though a nonvolatile memory, allows the stored data to be altered electrically under specified conditions. However, for large-volume production, the PROM is more expensive than the mask ROM of the comparable capacity. There are several types of PROM, among which the erasable PROM (EPROM) uses ultraviolet radiation for data erasure and the electrically erasable PROM (EEPROM) achieves data erasure by electrical means. However, in the case of using mask ROMs in large-volume production, if any data error is discovered before the start of volume production, all the prepared chips have to be scrapped and the manufacture must be started over again from the mask design stage. Furthermore, with the increasing packing density and memory capacity of semiconductor memory in recent years, the risk involved in the manufacture of the memory also has been increasing. For example, all the large-capacity memory chips prepared for production would be rendered useless even if only a slight modification to the data should become necessary. In addition, the demand for shortening the time for product development has been rising each year. Such demand makes it even more difficult to ensure the ROM data is free from error before the start of volume production. Thus, the possibility of having to rewrite data for correction is increased. In view of the above, it will be appreciated that a particular problem with the conventional mask ROM is that a great deal of time and money is needed for corrective measures when errors are found in the stored data. If PROMs of comparable memory size are used to avoid the above problem associated with ROMs, the major advantage of large-volume production will be lost. Furthermore, writing data to a PROM requires a great deal of time, and consequently productivity suffers greatly. This is particularly true in the case of EPROMs which are relatively cheap compared with EEPROMs. In the case of EPROMs, the entire chip must be rewritten even when only part of the data needs altering. Therefore, there is a strong need in the art for a nonvolatile semiconductor memory which can be partially rewritten without having to rewrite the entire chip. There is a strong need in the art for such a nonvolatile memory which reduces the time and expense associated with taking corrective measures when using conventional nonvolatile semiconductor memories. The document EP-A-0 383 452 discloses a semiconductor memory device having the pre-characterising features of claim 1. IBM Technical Disclosure Bulletin vol. 7 no. 6, November 1964, pages 436-437 and FR-A- 2 312 837 disclose devices having a main memory and a programmable secondary memory for storing data to replace data stored in the main memory. The present invention aims to overcome the aforementioned and other short comings of the above known nonvolatile semiconductor memories. The present invention is summarized and described in detail below. SUMMARY OF THE INVENTION According to the present invention, there is provided a semiconductor memory as claimed in claim 1. Thus, the present invention may provide a nonvolatile semiconductor memory that is partially rewritable and inexpensive in construction. The present invention may combine a large-capacity mask ROM with a small-capacity PROM between which selection is made for use as required. The mask ROM uses in the invention has a prescribed capacity that is large enough for the designed purpose, and data may be written in the mask ROM during manufacture of the memory. On the other hand, the PROM in the preferred embodiment has a capacity sufficiently smaller than that of the mask ROM. An address storage circuit is formed from a nonvolatile semiconductor memory such as an EPROM and is capable of storing modified addresses by associating them with the addresses on the PROM. The modified addresses designate the data portions that were identified as differing from the original data stored in the mask ROM when modified data was compared with the data stored in the mask ROM. When the data stored in the mask ROM needs modification, the data is sequentially read out of the mask ROM for one-on-one comparison with the modified data, and only when a mismatch is found in the data, the modified data is written into the PROM, while the address of the modified data is stored as a modified address in the address storage circuit by associating it with the address on the PROM at which the modified data is written. Rewriting data can be done as many times as required by erasing the memory contents of the address storage circuit and the PROM. Associating the modified address with the address on the PROM can be easily accomplished by, for example, matching the address on the address storage at which the modified address is stored with the address on the PROM at which the modified data is stored. An address match detection means is used to determine if the accessed address matches any of the modified addresses stored in the address storage circuit. When the address match detection means has detected the address match between them, the output data selector outputs the data that is read from the PROM at the address associated with the modified address. Therefore, in this case, the wrong or old data stored in the mask ROM is prevented from being output, and only the modified data is output. On the other hand, when no address match exists, the output data selector outputs the data that is read from the mask ROM at the accessed address. Therefore, in this case, the original data remaining intact by the modification is output from the mask ROM. If no data modification has been done and therefore there is no modified address stored in the address storage, the data stored in the mask ROM is directly output at all times since no address match is detected by the address match detection means. Thus, rewriting data is possible as much as the memory capacity of the PROM allows, and the modified data can be output in a reliable manner despite the original data being stored in the mask ROM. Furthermore, by making the memory capacity of the PROM sufficiently smaller than that of the mask ROM, the cost increase from a single mask ROM construction can be minimized. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but only a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS This invention may be better understood and its numerous advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1 is a block diagram of a semiconductor memory in accordance with one embodiment of the present invention; Figure 2 is a flowchart illustrating a data rewrite operation in the semiconductor memory of Figure 1 in accordance with the present invention; Figure 3 is a timing chart showing the state of each signal at the time of rewriting data in the semiconductor memory in accordance with the present invention; Figure 4 is a flowchart illustrating an operation of data write to a PROM in the semiconductor memory in accordance with the present invention; and Figure 5 is a flowchart illustrating the operation of data read from the semiconductor memory in accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings where like reference numerals are used to refer to like elements throughout, the semiconductor memory 15 of the present embodiment is a partially rewritable read-only memory including, as shown in Figure 1 , a mask ROM array 1 and a PROM array 2 . Preferably, the mask ROM array 1 is a large-capacity nonvolatile semiconductor memory array in which the stored data are written during manufacture of the memory. The PROM array 2 , on the other hand, preferably has a relatively small memory capacity. An external input address A IN transferred through a plurality of address lines is input to the mask ROM array 1 via a decoder 3 , to an address storage circuit 6 , and to an address match detection circuit 7 . When the input address A IN is given, the addressed data D ROM is read from the mask ROM array 1 and is transferred via a data selector 4 and an output circuit 5 onto an external data bus 5′ . The PROM array 2 is a nonvolatile EPROM memory array in which data can be written electrically. An address A PROM which is output from the address storage circuit 6 is given to the PROM array 2 via a decoder 8 . When the address A PROM is given, modified data D PROM is read from the PROM array 2 and is transferred via the data selector 4 and the output circuit 5 onto the external data bus 5′ . The decoders 3 and 8 are provided to perform row decoding of addresses, etc. within the semiconductor memory. The output circuit 5 is an interface circuit that interfaces with the external data bus 5′ . The address storage circuit 6 is formed from a nonvolatile EPROM that stores modified addresses equivalent to the memory capacity of the PROM array 2 , and is capable of outputting the stored modified addresses sequentially to the address match detection circuit 7 via line 12 . The address match detection circuit 7 is a circuit which, when the input address A IN is given, compares the input address A IN with each modified address sent from the address storage circuit 6 , and when the addresses match, issues an active select signal Q₂ to the data selector 4 . In addition, when an address match is detected by the address match detection circuit 7 , the address storage circuit 6 outputs the address at which the modified address is stored, to deliver it as the address A PROM to the PROM array 2 via the decoder 8 . The data selector 4 is a multiplexer that selects the modified data D PROM read from the PROM array 2 to be output as output data D OUT when the select signal Q₂ from the address match detection circuit 7 is set active, and selects the data D ROM read from the mask ROM array 1 to be output as output data D OUT when the select signal Q₂ is inactive. The input address A IN is also given to the address storage circuit 6 so that modified data can be input at the time of rewriting data as is described in detail below. The semiconductor memory 15 of the present embodiment is also provided with an input circuit 9 for inputting new data when rewriting data. The input circuit 9 is an interface circuit that interfaces with the external data bus 5′ , and the input data D IN transferred through the input circuit 9 from the external data bus 5′ is fed to a comparator circuit 10 and to the PROM array 2 . Besides the input data D IN , the output data D OUT from the data selector 4 is also fed to the comparator circuit 10 so that the input data D IN and the output data D OUT are compared. When these data do not match, the comparator circuit 10 issues an active mismatch signal Q₁ to the address storage circuit 6 and the PROM array 2 , causing them to store the input address A IN and the input data D IN , respectively. The operation of the thus constructed semiconductor memory 15 will now be described with reference to Figures 2 to 5 . Suppose an error is discovered in the data stored in the mask ROM array 1 of the semiconductor memory 15 , making it necessary to rewrite or modify the stored data. First, in step S1 shown in Figure 2 , a high write voltage is applied to a write power supply terminal V pp (not shown) on the PROM array 2 , and then (in step S2), the lowest address 0 is set as the input address A IN , and at the same time, modified data corresponding to the address 0 is transferred onto the external data bus 5′ . Using the input address A IN , data D ROM is read from the mask ROM array 1 . Since no modified addresses are stored in the address storage circuit 6 yet in this particular example, the data selector 4 outputs the data D ROM as output data D OUT . Next, the comparator circuit 10 compares the data D ROM , which is read from the mask ROM array 1 at the address corresponding to the input address A IN , with the input data D IN supplied through the input circuit 9 (step S3). If these data match, then it is checked if the processing has been done on all the addresses of the semiconductor memory (step S4), and if not yet, the process returns to step S3 after incrementing the input address A IN (step S5), the process being repeated thereafter as long as a data match exists. On the other hand, if, in step S3, the output data D OUT read from the mask ROM array 1 does not match the input data D IN which is the modified data, the input address A IN is stored as a modified address in the address storage circuit 6 (step S6), and at the same time, the input data D IN is written as modified data into the PROM array 2 (step S7). At this time, the address storage circuit 6 sends the address A PROM , at which the modified address is stored, to the PROM array 2 via the decoder 8 so that the input data D IN is written at the equivalent address. Therefore, the modified address stored in the address storage circuit 6 and the modified data stored in the PROM array 2 are related to each other in that the modified data is stored in the PROM array 2 at the same address at which the modified address is stored in the address storage circuit 6 . The sequence of operation that leads to the writing of the input data D IN into the PROM array 2 (step S7) will be described below with reference to the timing chart of Figure 3 . First, by the processing in step S1 referred to in Figure 2 , a high write voltage is applied to the write power supply terminal V pp at time t₁ , to ready the PROM array 2 for data write. Next, at time t₂ , the input address A IN and the input data D IN are entered to the semiconductor memory 15 . After a short delay, at time t₃ , the output data D OUT becomes valid and is compared with the input data D IN . If a mismatch is detected between these two data, the mismatch signal Q₁ is set active at time t₄ , which causes the address storage circuit 6 to store the input address A IN as a modified address, while, at the same time, the chip enable signal CE is set active (i.e., goes "low"), causing the PROM array 2 to store the input data D IN as modified data at the address A PROM given from the address storage circuit 6 . When the modified address is stored in the address storage circuit 6 , an address match with the input address A IN is detected and the select signal Q₂ is set active at time t₅ . As a result, the data selector 4 is caused to switch to the PROM array 2 side and, at time t₆ , the out enable signal OE is set active, thus reading the just stored modified data D PROM from the PROM array 2 . The modified data D PROM is supplied as output data D OUT to the comparator circuit 10 where it is compared with the input data D IN . When these data match and thus the write proves to be successful, the processing in step S7 is completed. The above description has dealt with the case in which the data has been written successfully to the PROM array 2 at the first attempt. However, because of variations in the write characteristics of EPROM, the write time will become long with a resultant decrease in productivity if reliable data write is to be ensured at the first attempt. Therefore, the actual write operation to the PROM preferably is performed in the procedure shown in Figure 4 . First, the counter n is set to 0 (step S11), and after incrementing the value of the counter n by 1 (step S12), data write is performed for 1 ms (step S13). Next, read check is performed to verify the written data (step S14), and if the data write has not been successful, the loop starting from step S12 is repeated until the value of the counter n reaches 25 (step S15). If successful data write has not been attained until the value of the counter n has reached 25, the process is suspended and appropriate error processing is performed (step S16). If it is determined in the read check in step S14 that the write has been made successfully, the current value of the counter n that represents the number of writes so far tried is tripled, and additional write is performed for a duration of time equal to ((3 x n) ms) (step S17), then terminating the process normally. Thus, the average write time is reduced as compared with the case in which data write is performed only once. When the write to the PROM array 2 is completed as described above, the process proceeds from step S7 to step S4 in which it is checked if the processing has been performed on all the addresses. If not yet, the processing of steps S6 and S7 is repeated each time a mismatch occurs between input data D IN and data D ROM . When the processing has been completed on all the addresses, the write voltage applied to the write power supply terminal V pp is removed (step S8), and after read check is performed on all the addresses (step S9), the data rewrite process is completed. As described, in the semiconductor memory of the present embodiment, the modified data is compared with the original data stored in the mask ROM array 1 and only portions of data that differ from the original are stored in the PROM array 2 , thus achieving partial rewriting of data. In the present embodiment, the comparison check in step S3 of the above data rewrite process is performed using the comparator circuit 10 internal to the semiconductor memory, and the chip enable signals CE , etc. are controlled externally by monitoring the state of the mismatch signal Q₁ . However, all such processing may be performed by internal hardware of the semiconductor memory, or alternatively, the processing including the comparison check by the comparator circuit 10 may be performed using an external operation program. An operation of data read from the thus rewritten semiconductor memory will now be described with reference to the flowchart of Figure 5 . The same read operation is also performed in the read check in step S9 in Figure 2 . First, the input address A IN accessed by the system is input (step S21), and the address match detection circuit 7 checks if any modified address that matches the accessed address is stored in the address storage circuit 6 (step S22). If there is no address match, since the select signal Q₂ remains inactive, the data D ROM read from the mask ROM array 1 is output as output data D OUT (step S23). Therefore, the data originally stored in the mask ROM array 1 is directly output for the portions of data that have not been modified. On the other hand, if an address match is detected by the address match detection circuit 7 in step S22, the address A PROM on the address storage circuit 6 at which the modified address is stored is transferred to the PROM array 2 to read modified data D PROM from the corresponding address. The modified address stored in the address storage circuit 6 represents the input address A IN which was input when a mismatch was detected between the data D ROM stored in the mask ROM array 1 and the input data D IN during the previous data rewrite process, and the modified data D PROM read from the PROM array 2 corresponds to the input data D IN that was input at that time. When the address match is detected, the address match detection circuit 7 sets the select signal Q₂ active, which causes the data selector 4 to switch to the PROM array 2 side. As a result, the original data D ROM read from the mask ROM array 1 is blocked by the data selector 4 , allowing the modified data D PROM read from the PROM array 2 to be output as the output data D OUT (step S24). Thus, according to the semiconductor memory of the present embodiment, the data read from the mask ROM array 1 is directly output for the portions of data that were not the objects of modification at the time of rewriting data, while for the portions that were modified, the data read from the PROM array 2 is output, thus making it possible to essentially rewrite part of the stored data within the memory capacity of the PROM array 2 despite the construction being a read-only memory consisting primarily of an inexpensive mask ROM. In the present embodiment, since the addresses of the semiconductor memory are random-accessed, it is necessary for the address match detection circuit 7 to compare the input address A IN with each modified address sequentially given from the address storage circuit 6 (though it is possible to speed up the detection process by such processing as determining that no address match exists when the modified address being given sequentially becomes higher than the input address A IN ). However, in cases where the data stored in the semiconductor memory is always accessed sequentially, it may be so configured that the address match detection circuit 7 first reads out the top modified address from the address storage circuit 6 and increments the modified address each time it matches the input address A IN , thus requiring comparison with only one modified address each time. As is apparent from the above description, according to the semiconductor memory of the present invention, since the output data selector 4 automatically reads data from the PROM and outputs the thus readout data only for modified portions despite the original data being stored in the mask ROM, it is possible to essentially rewrite the stored data within the memory capacity of the PROM. Furthermore, by making the memory capacity of the PROM sufficiently smaller than that of the mask ROM, the cost increase from a single mask ROM construction can be minimized. It will be appreciated that only those data stored in the mask ROM array 1 which contain errors need be rewritten to the PROM array 2 , thus reducing the required memory capacity of the PROM 2 . Also, since an ordinary write algorithm can be used to rewrite the mask ROM, partially rewriting the mask ROM data can be achieved in a short time. It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the specific embodiments described herein.

Claims: A semiconductor memory comprising: a read-only memory (ROM) (1) having original data (D ROM ) stored therein; a programmable read-only memory (PROM) (2) for storing substitute data (D PROM ) to replace a portion of said original data; address storage means (6) for storing one or more addresses which correspond to one or more addresses in said ROM which contain said portion of original data to be replaced; address comparison means (7) for comparing an accessed address (A IN ) with at least one of said stored addresses and, based on said comparison, providing either a first or second comparison response (Q₂); and output data selector means (4) for outputting said substitute data read from said PROM and corresponding to one of the stored addresses when said first comparison response is detected, and for outputting said original data read from said ROM at said accessed address when said second comparison response is detected, characterised by comparator means (10) for comparing input data (D IN ) to said original data read from said ROM, automatically storing portions of the input data which differ from said original data as said substitute data in said PROM, and automatically storing the addresses of the original data which differ from the input data in the address storage means. A semiconductor memory as claimed in claim 1, characterized in that said addresses are stored in said address storage means (6) at addresses which correspond respectively to the addresses (A PROM ) in said PROM at which said substitute data are stored. A semiconductor memory according to claim 1 or claim 2, wherein said first comparison response is provided when said accessed address (A IN ) and one of said stored addresses match, and said second comparison response is provided when said accessed address does not match said stored addresses. A semiconductor memory according to any one of claims 1 to 3 wherein the memory capacity of said PROM (2) is smaller than the memory capacity of said ROM (1). A semiconductor memory according to any preceding claim, wherein said ROM (1) comprises a mask ROM. A semiconductor memory according to any preceding claim, wherein said PROM (2) comprises an erasable PROM (EPROM). A semiconductor memory according to any one of claims 1 to 5 wherein said PROM (2) comprises an electrically erasable PROM (EEPROM).

Inventors: HOTTA YASUHIRO, HOTTA, YASUHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1992
Main classification: G06F11
IPC codes: G11C29, G06F9, G11C16, G11C17, G11C8