Multichannel amplifier with gain matching

Abstract: A multichannel amplifier employs field-effect transistors (22,35) to vary the gain of operational amplifiers (15,30) in each respective channel (10,11). Gain matching of the respective channels (10,11) is obtained by providing each channel with a respective DC bias voltage (V B1 ,V B2 ) which compensates for differences in pinch-off voltage of the field-effect transistors (22,35). The invention permits the use of inexpensive, unmatched JFETs in the amplifier. Close gain tracking achieves very accurate stereo imaging in an audio system.

Description: The present invention relates in general to a multichannel amplifier wherein each channel employs an operational amplifier connected to a field-effect transistor to vary the amplifier gain, and more specifically, to a gain-matched multichannel amplifier wherein each channel has a respective DC bias voltage which compensates for differences in the field-effect transistors. Amplification of electrical signals by a desired gain can be achieved using operational amplifier (op amp) integrated circuits. By providing negative feedback between the output of the op amp and its inverting input, the gain provided by such an amplifier is controlled by external resistances connected to the op amp as is known in the art. If one or more of the external resistances are variable resistances, the amplifier gain may be varied. Thus, a variable-gain amplifier can be realised by employing a potentiometer in the feedback path between the output and inverting input of the op amp, for example. US-A-4,794,343 discloses a multichannel amplification system wherein a plurality of input signals are each amplified by respective gains in response to a control signal, said system comprising control means for generating said control signal; and a plurality of channel means each coupled to said control means, each channel means comprising an amplifier for amplifying a respective input signal. This system foresees the use of a PIN diode to set the gain of the amplifier and does not use a field effect transistor. FR-A-2,381,416 discloses an operational amplifier the gain of which is set by means of a field effect transistor (FET) connected via a capacitor between the inverting input and the output terminals. In this patent, the non inverting input is connected to ground and no arrangement is provided to adjust the bias voltage of the FET. It is also known to employ a voltage-controlled attenuator such as a junction field-effect transistor (JFET) operating in its linear or triode region of operation as a variable gain-setting resistance used in conjunction with an op amp. Thus, a gate control voltage supplied to the JFET determines the amplifier gain. However, several disadvantages are associated with certain inherent properties of JFETs. Due to uncontrollable variations in the fabrication process of JFETs, various electrical properties, such as pinch-off voltage V p , on-resistance R ds(on) , and the resistance curve between R ds(on) and V p , have a wide variation from one JFET to another JFET of the same design. The use of a JFET as a voltage-controlled attenuator is strongly influenced by these uncontrolled characteristics, thus limiting the usefulness of JFETs as attenuators. Testing of JFETs after manufacture to sort them according to similar characteristics greatly increase the costs associated with using JFETs as attenuators. Furthermore, sorting cannot eliminate all variability in the JFET characteristics. Variations in the electrical properties of JFETs create problems if JFET-controlled op amps are to be used in multichannel audio amplifiers (e.g., audio limiters) which require that separate channel gains closely track each other. Even sorted JFETs do not provide sufficiently matched characteristics to obtain the required gain tracking. The present invention seeks to provide a multichannel amplifier with accurate gain tracking between channels. According to the present invention, there is provided a multichannel amplification system wherein a plurality of input signals are each amplified by respective gains in response to a control signal, said system comprising control means for generating said control signal; and a plurality of channel means each coupled to said control means, each channel means comprising an amplifier for amplifying a respective input signal; characterised in that each channel means comprises an operational amplifier having an inverting input, a non inverting input, and an output; a field-effect transistor with a gate, a source, and a drain and providing a respective pinch-off voltage, said drain being coupled to said inverting input, said field-effect transistor being connected to control the gain provided by said operational amplifier; and bias means for providing an adjustable DC bias voltage to said non inverting input; and in that said DC bias voltages have respective voltage values which compensate for differences in the respective pinch-off voltages of said field-effect transistors. The invention provided a method of matching the gain characteristics of the individual amplification channels of such a multichannel amplifier which comprises the steps of applying a fixed, predetermined input signal to each channel of said multichannel amplifier; applying a common control voltage to each of the gates of the field effect transistor at an initial voltage value which is sufficient to cause each field-effect transistor to become pinched-off; monitoring the magnitude of each output signal from each respective channel; adjusting said common control voltage until a first one of said output signals is attenuated; maintaining said common control voltage at a final voltage where said first output signal is attenuated; and adjusting a bias voltage to the operational amplifier of each remaining channel until its respective output signal is substantially equal to said first output signal. The invention will now be described further, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a multichannel amplifier according to the present invention. Figure 2 is a plot of resistance characteristics for first and second JFETs. Figure 3 is a plot of multichannel gain curves without the compensation provided by the present invention. Figure 4 is a flow chart illustrating a preferred method according to the present invention. Figure 1 shows a multichannel amplifier including a first channel 10 and a second channel 11 of the type that is useful in a stereo reproduction system, for example. First channel 10 includes an operational amplifier (op amp) 15 for receiving an input signal v 1 at a terminal 16 and providing an amplified output signal OUT1 at a terminal 17. A variable gain is provided in response to a control signal v c provided from a control signal generator 18. Input signal v 1 is coupled to the inverting input of op amp 15 through a resistor 20. Negative feedback between the inverting input and the output of op amp 15 are provided by a resistor 21 connected in parallel with a JFET 22 and a resistor 23. Control signal v c is coupled to the gate of JFET 22 through a resistor 24. A resistor 25 couples the gate of JFET 22 with the source terminal of JFET 22 in order to maximise the linear or triode region of operation. In order to allow AC operation of op amp 15 with a single supply voltage, the op amp is operated with a DC bias as is known in the art. Specifically, the non inverting input of op amp 15 is biased to a DC bias voltage V B1 obtained by dividing a reference voltage V REF at terminal 26 using a voltage divider comprising a resistor 27 connected in series with a trim resistor 28. Second channel 11 of the multichannel amplifier includes an op amp 30 which amplifies an input signal v 2 at an input terminal 31 to provide an output signal OUT2 at an output terminal 32. Input signal v 2 is coupled to the inverting input of op amp 30 through a resistor 33. Negative feedback between the inverting input and the output of op amp 30 is provided by a resistor 34 connected in parallel with a JFET 35 and a resistor 36. The gate of JFET 35 receives control signal v c through a resistor 37. A resistor 38 is coupled between the gate and source terminals of JFET 35. The non inverting input of op amp 30 receives a bias voltage V B2 obtained from a voltage divider comprising a resistor 40 and a trim resistor 41 which is connected to receive the reference voltage V REF . Op amps 15 and 30 are connected to a single power supply providing a voltage of +V with respect to ground. When operating an op amp with a single power supply, it is known that the non inverting input of the op amp should be provided with a DC bias equal to about one-half the power supply voltage +V. Typically, each op amp in a prior art multichannel amplifier would receive the same bias voltage. However, since the actual DC bias is removed from each signal by filtering prior to the final stage of amplification, the particular value of the DC bias is not important (as long as there is sufficient voltage swing available to avoid clipping). Thus, the DC bias applied to each op amp in a multichannel amplifier need not be the same. Gain in channels 10 and 11 are limited between minimum and maximum gains set by fixed resistors. With JFETs 22 and 35 each pinched-off by a control signal v c which is greater than their respective pinch-off voltages V p , channels 10 and 11 provide their maximum gain. When control signal v c is reduced in voltage level (thus allowing the JFETs to conduct current through their respective channels), the amplifier gains are reduced and a limiting function is performed. Figure 2 shows a variation in JFET characteristics which may be expected between individual devices due to uncontrollable parameters in JFET manufacturing. The resistance between the drain and source of a p-channel JFET is controlled by the gate-to-source voltage v gs when the JFET is operating in its linear or triode region (i.e., the drain-to-source voltage v ds must be small). With the gate voltage equal to zero, the drain-to-source resistance is at its minimum. The resistance increases substantially linearly with increasing gate voltage until prior to reaching the pinch-off voltage of the FET. A first JFET exhibits a characteristic 45 having a first pinch-off voltage V p1 and a second FET has a characteristic 46 with a second pinch-off voltage V p2 . The difference in pinch-off voltage could lead to different gain curves between the amplifier channels as shown in Figure 3. Gain curve 47 corresponds to the JFET having characteristic 46 in Figure 2, and gain curve 48 corresponds to the JFET with characteristic 45. Thus, for control voltages between the separate pinch-off voltages of the FETs, one channel provides its maximum gain while the other provides less than its maximum gain. This problem is corrected by modifying gain curve 48 so that it corresponds with gain curve 47 by means of separately adjusting the DC bias level provided to the op amps. In Figure 1, bias voltages V B1 and V B2 are adjusted so that their difference equals the difference between the pinch-off voltages of JFETs 22 and 35. Since the inputs to the respective op amps are biased at different voltages, the JFETs can reach pinch-off simultaneously even though they receive the same control signal (the gate-to-drain voltage v gd is approximately equal to the gate-to-source voltage v gs since the drain-to-source voltage v ds is small). The appropriate bias voltages are obtained by adjusting trim resistors 28 and/or 41 which preferably comprise a laser-trimmable, thick-film resistor but could alternatively be comprised of a potentiometer or other variable resistance. A preferred method for adjusting the DC bias voltage in a multichannel amplifier is shown in Figure 4. Such adjustment is preferably done as a final adjustment in the manufacturing process of an audio amplifier system. In step 50, a fixed AC input signal is applied to the input of each channel of the amplifier while all channels receive substantially equal bias voltages. The AC input signal has a constant magnitude and constant frequency, for example. The AC input signal remains fixed throughout the entire calibration procedure. In step 51, control signal v c is provided at an initial value which is sufficiently large to keep all JFETs pinched off; i.e., all channels are at their maximum gain. In step 52, control signal v c is gradually adjusted (i.e., reduced) while the output signal magnitude is measured for all channels. Since the pinch-off voltages of the JFETs are not matched, one channel will be the first to show a reduced gain as control signal v c is adjusted. The channel which first begins to show a decrease in gain becomes the reference channel for adjusting the remaining channels. In step 53, control signal v c is fixed at a point where the reference channel output signal is attenuated. In step 54, each remaining channel is individually adjusted by monitoring the channel output signal while adjusting the bias voltage to decrease the output signal magnitude until it matches the output signal magnitude in the reference channel. The trim resistor may preferably be contained in a hybrid thick-film resistor which is trimmed using a laser trimmer. An alternative method would be to directly measure the pinch-off voltages and to set the bias voltage according to the differences in pinch-off voltage. In addition, the present invention is useful with amplifier circuits using a double-ended power supply. In order to set the bias voltage applied to a particular op amp, the non inverting input of the op amp would be coupled to each power supply voltage through a respective resistance. At least one of the resistances would be variable to allow trimming of the bias voltage to an appropriate value between the power supply voltages.

Claims: A multichannel amplification system wherein a plurality of input signals are each amplified by respective gains in response to a control signal, said system comprising: control means (18) for generating said control signal; and a plurality of channel means (10,11) each coupled to said control means (18), each channel means (10,11) comprising an amplifier for amplifying a respective input signal; characterised in that each channel means (10) comprises an operational amplifier (15) having an inverting input, a non inverting input, and an output; a field-effect transistor (22) with a gate, a source, and a drain and providing a respective pinch-off voltage, said drain being coupled to said inverting input, said field-effect transistor being connected to control the gain provided by said operational amplifier (15); and bias means (VREF, 27,28) for providing an adjustable DC bias voltage (VB1) to said non inverting input; and in that said DC bias voltages have respective voltage values which compensate for differences in the respective pinch-off voltages of said field-effect transistors (22). A system as claimed in claim 1, wherein said control means (18) generates a common control signal coupled to each of said gates. A method of matching the gain characteristics of the individual amplification channels of a multichannel amplifier as claimed in claim 1 or 2, said method comprising the steps of: applying a fixed, predetermined input signal to each channel (10,11) of said multichannel amplifier; applying a common control voltage (v c ) to each of the gates of the field effect transistor (22,35) at an initial voltage value which is sufficient to cause each field-effect transistor to become pinched-off; monitoring the magnitude of each output signal from each respective channel (10,11); adjusting said common control voltage until a first one of said output signals (OUT1,OUT2) is attenuated; maintaining said common control voltage (v c ) at a final voltage where said first output signal is attenuated; and adjusting a bias voltage (V B1 , V B2 ) to the operational amplifier (15) of each remaining channel (10,11) until its respective output signal is substantially equal to said first output signal. A method as claimed in claim 3, wherein each respective bias voltage (V B1 , V B2 ) is obtained from a respective resistive voltage divider (27,28; 40,41) and wherein said bias voltage adjusting step is comprised of trimming a respective resistive voltage divider. A method according to claim 4, wherein said trimming step is comprised of laser trimming a thick-film resistor.

Inventors: DIFIORE NICHOLAS LAWRENCE, GINGRICH RANDAL ROSS, DIFIORE, NICHOLAS LAWRENCE, GINGRICH, RANDAL ROSS
Applicants: FORD FRANCE, FORD MOTOR CO, FORD WERKE AG, FORD FRANCE S. A., FORD MOTOR COMPANY LIMITED, FORD-WERKE AKTIENGESELLSCHAFT
Application year: 1992
Main classification: H03G1
IPC codes: H03G3, H03G1