HIGH VOLTAGE GENERATOR HAVING OUTPUT CURRENT CONTROL

Abstract: High voltage generator comprising several voltage multiplying stages connected in series, each comprising a diode and a capacitor one terminal of which being connected to the cathode of the respective diode, every cathode of a diode being connected to the anode of the diode of the next voltage multiplying stage, a clock generator generating two clock pulses being 180 DEG out of phase to one another and being supplied alternately to the other terminal of the capacitors of successive voltage multiplying stages, the last diode in the series supplying a high voltage output and said high voltage output being connected to feed-back means, modifying said two clock pulses in dependence on the voltage level on the high voltage output, at least the capacitor (Cn) in the last voltage multiplying stage receiving a control current (I1) determined by said feed-back means instead of one of both clock pulses.

Description: High voltage generator having output current control. The invention relates to a high voltage generator comprising several voltage multiplying stages connected in series, each com- prising a diode and a capacitor one terminal of which being con¬ nected to the cathode of the respective diode, wherein every cathode of a diode is connected to the anode of the diode- of the next voltage multiplying stage, a clock generator generating clock pulses being 180° out of phase with one another, and being supplied alternately to the other terminal of the capacitors of successive voltage multiplying stages, the last diode in the series supplying a high voltage output and said high voltage output being connected to feed-back means, which modifies said two clock pulses in depend¬ ence on the voltage on the high voltage output. Such a high voltage generator is known from the European patent application 350,462. Said known high voltage generator gen¬ erates a high voltage pulse for instance to program (E)EPROM-memory cells. Therefore, a voltage of about 5 V is converted in a pulse of about 16 V, which value is sufficient to program (E)EPROM-memory cells. Every voltage multiplying stage functions as a charge pump and after each stage a voltage increase at most equal to the step value of the clock pulse less the threshold voltage of the diodes occurs. A disadvantage of said known arrangement is that the high voltage output shows spikes whenever one of both clock pulses switches. The object of the invention is to provide an arrangement neutralizing this disadvantage and the output voltage of which does not show any spikes any more. The arrangement according to the invention is therefore char¬ acterized in that at least the capacitor in the last voltage multi¬ plying stage receives a control current being determined by said feed-back means instead of one of both clock pulses. By shaping the control current in a proper way the spikes on the high voltage output may be substantially reduced. The invention will be hereinafter explained by reference to a drawing. In the drawing figure 1 shows the circuit according to the invention, partly in block diagram; figure 1A shows an alternative circuit according to the in¬ vention; figure 2 shows the voltage being supplied to the last capa- citor instead of one of both clock pulses; figure 3 shows a simulated diagram of the two clock pulses controlling the charge pumps; figure 4 shows a simulated diagram of a part of the rising edge of a programming pulse without current control of the last capacitor; figure 5 shows a simulated diagram of a part of the rising edge of a programming pulse with current control of the last capa¬ citor; figure 6 shows a simulated diagram of a programming pulse generated by means of the arrangement according to the invention- Figure 1 shows the invention partly in block diagram. The figure shows a voltage multiplier known as such comprising several charge pumps connected in series. Every charge pump consists of a diode Di and a capacitor Ci+1 connected to its cathode. At its other terminal each capacitor receives a clock pulse (φl or φ2) generated by an oscillator 3. The oscillator 3 generates two clock pulses being 180° out of phase with respect to one another, said clock pulses being supplied alternately to the successive capa¬ citors Ci. In this voltage multiplier known as such every stage substantially doubles its input voltage. The diodes DO ... Dn may be MOS-transistors connected as diodes. In the arrangement according to the invention the last capa¬ citor Cn is not controlled by one of both clock pulses φl or φ2, but by a control current 11 - This provides the possibility to reduce spikes on the high voltage output during switching of the clock pulses φl and φ2. The current control of the last capacitor is provided by means of feed-back means comprising a high voltage feed-back cir¬ cuit 1, a reference source 2, an operational amplifier A, a current source 11 and two switches S1 and S2 controlled by the clock pulses φl and φ2. The output of the high voltage feed-back circuit 1 is connected to the inverting input of the operational amplifier A, the non-inverting input of which receives a reference voltage (or reference current) from a reference voltage or reference current source 2. The output of the operational amplifier A controls the output current of the current source 11. The output of the current source 11 is connected to ground (VSS) through two switches S1 and S2 being connected in series and being controlled by φl and φ2, respectively. The junction of the switches S1 and S2 provides the voltage Vn to the last capacitor Cn, as well as the input voltage of the oscillator 3. Figure 2 shows the voltage Vn to the last capacitor Cn as a function of time. If Vn increases Cn is discharged through Dn and a load connected to the high voltage output HV out . Then, the switch S2 controlled by φ2 is closed, while the switch S1 controlled by φl is opened. Switch S2 supplies the current 11 to the capacitor Cn, in such a way that the output current I out is also equal to 11. At a certain moment t1 Vn exceeds a predetermined threshold value and the oscillator 3 switches: the outputs φl and φ2 change sign. The switches S1 and S2 controlled by φl and φ2, respectively, switch, i.e. S2 opens and S1 closes. The voltage Vn decreases to ground potential (VSS) the rate of which being determined by the resis- tance of S1 , after which the capacitor Cn is charged through diode Dn-1. At moment t2 oscillator 3 switches again, after which Vn increases again and Cn discharges again by the current I out = 11 through Dn and the load. If 11 is a controlled current also the output current I out is a controlled current. The voltage Vn has a saw-tooth shape. The slope of the rising edge is determined by 11 being in turn control¬ led by the high voltage feed-back circuit 1. Since the high voltage feed-back circuit 1 is controlled by the high voltage output HV out the slope of Vn is determined by the load connected to the high voltage output. Furthermore, because Vn also controls the oscil¬ lator the frequency of the clock pulses φl and φ2 is determined by the load. The voltage multiplier, therefore, only pumps charge to the output HV out when it is needed there. So, the voltage multi¬ plier according to the invention does not only have the advantage of having an output being current controlled and having reduced spikes on the output voltage, but also shows frequency control of the oscillator. In figure 1 a single multiplying circuit is shown. A disad- vantage of such a single circuit is that no output current I o . t can flow during the falling edge of control signal Vn. In practice this problem is solved by applying an additional, identical voltage mul¬ tiplier, in which the voltages φl and φ2 have inverted values com- pared to those in the arrangement of figure 1. At the moments that Vn in the arrangement according to figure 1 decreases and, there¬ fore, no output current is supplied, the other identical voltage multiplier in such a double-phase arrangement will supply an output current 11, so that always: I o . t = 11. Such a double-phase circuit is shown in figure A. Figure 3 shows a simulation of a double-phase embodiment of the arrangement according to figure 1. Here, Vn1 is equivalent to Vn in figure 1 for one phase and Vn2 for the other phase- The fre¬ quencies of φl and φ2 correspond to those of Vn1 and Vn2, respec - ively. In figure 3 one can see -how this frequency is determined by the load. On top of figure 3 a part of the simulated curve of. he rising edge of a programming pulse VPP may be seen. VPPID shows the ideal, desired curve of VPP. The two other curves show the control signals Vn1 and Vn2. After 60 μs a heavier load is connected to the output HV- ^t . One can clearly observe the slopes of Vn1 and Vn2 becoming more steep and, therefore, the frequency increases- The voltage jump at the beginning of every pulse is caused by the charge pump diode threshold voltage to be exceeded. The spikes in the control signals only reach the capacitors being controlled by them, however, they do not reach the output of the charge pump as long as the circuit is properly dimensioned. Figures 4, 5 and 6 show resulting programming pulses VPP as a function of time. Figure 4 shows VPP in case the last capacitor Cn is not current controlled, but like the other capacitors receives one of both clock pulses φl or φ2. Figure 4 only shows a part of the rising edge of the programming pulse- VPP is the output signal of the charge pump, while VPPOUT is the output signal of a (small) low pass filter receiving VPP as input signal. Figure 5 shows that in the arrangement according to the invention, applying current control of the last capacitor Cn, spikes caused by the clock pulses are less powerful in the programming pulse VPP. When comparing figures 4 and 5 it has to be observed that figure 5 has been simu¬ lated utilizing a capacitor (CHV) between HV 0 --_ t and ground (VSS) having a magnitude of more than six times smaller than the one in figure 4. If figure 4 would have been simulated utilizing the same capacitor as used in the simulation of figure 5 the spikes on the VPP-signal in figure 4 would have been about six times larger. Figure 6 shows an entire programming pulse as may be realized with the arrangement according to the invention. One can clearly see how exactly the real pulse VPPOUT precisely follows the ideal pulse VPPID. The invention is not limited to the current control of the last capacitor Cn. Principally, it is possible to control the cur¬ rent of other capacitors. However, generally this results in a lower efficiency of the charge pump. Moreover, then the output current no longer equals 11 and, therefore, this current is defined less well.

Claims: Claims 1. High voltage generator comprising several voltage multi¬ plying stages connected in series, each comprising a diode and a capacitor one terminal of which being to the cathode of the respec¬ tive diode, wherein every cathode of a diode is connected to the anode of the diode of the next voltage multiplying stage, a clock generator generating clock pulses being 180° out of phase with one another, and being supplied alternately to the other terminal of the capacitors of successive voltage multiplying stages, the last diode in the series supplying a high voltage output and said high voltage output being connected to feed-back means, which modifies said two clock pulses in dependence on the voltage on the high voltage output, characterized in that at least the capacitor (Cn) in the last voltage multiplying stage receives a control current (11 ) determined by said feed-back means instead of one of both clock pulses. 2. High voltage generator according to claim 1 , wherein only said capacitor (Cn) in said last voltage multiplying stage receives said control current (11) determined by said feed-back means. 3. High voltage generator according to claim 1 or 2, wherein said feed-back means comprises a high voltage feed-back circuit (1) connected to the high voltage output (HV oι _ t ), the output of the high voltage feed-back circuit (1 ) being connected to the input of an operational amplifier (A) , the other input of which receives a reference signal, the output of the operational amplifier control¬ ling the magnitude of the control current (11), the control current being able to flow through a first switch (S2) controlled by one of the two clock pulses (φ2) to said last capacitor (Cn), the junction of the first switch (S2) and said last capacitor (Cn) may be con¬ nected to ground (VSS) through a second switch (S1 ) controlled by the other clock pulse (φl ) and supplies an input voltage (Vn) to the oscillator to control the slope and frequency of both clock pulses (φl , φ2). 4. High voltage generator according to claims 1 , 2 or 3, wherein when the input voltage (Vn) to the oscillator exceeds a predetermined threshold value, said clock pulses (φl, φ2) switch in such a way that said first switch (S2) controlled by said clock pulse (φ2) is opened and said second switch (S1) controlled by clock pulse (φl ) is closed and when the input voltage decreases below an other predetermined threshold value said clock pulses switch again resulting in closing the first switch (S2) and an opening of said second switch (S1). 5. High voltage generator according to one of the preceding claims, wherein a second identical, but inverse high voltage gener¬ ator is being applied, the high voltage outputs of both high volt¬ age generators being connected to one another in such a way, that when one of both high voltage generators does not supply any con- trol current (11) but charges its respective last capacitor the other high voltage generator supplies said control current (11). *****

Inventors: SEESINK PETRUS HENDRIKUS, SEESINK, PETRUS, HENDRIKUS
Applicants: SIERRA SEMICONDUCTOR BV, SIERRA SEMICONDUCTOR B.V.
Application year: 1992
Main classification: G11C5
IPC codes: G11C5, G11C16, H02M3