CMOS logic circuit

Abstract: A CMOS logic circuit with biased inputs to a predetermined logic level, being of a type including at least one signal input (IN) and logic gates (4,5) for handling said signal, further includes a circuit portion (7) which is connected to the signal input (IN), and the equivalent of a high-value resistance effective to bias said input (IN).

Description: This invention relates to a CMOS logic circuit having inputs biased to a predetermined logic level. More particularly, the invention relates to a sub-family of high-speed CMOS logic circuits (HCMOS) adapted to replace, in many applications, TTL (Transistor-Transistor Logic) technology devices including low-power Schottky transistors (LSTTL). The description herein below will make reference to this field of application for convenience of illustration. As is known, CMOS logic circuits are currently gaining increased acceptance on account of their negligible electric current, and hence power, requirements for nearly the same performance as the logic families of the TTL or LSTTL types. The single drawback of CMOS devices, when used as substitutes for LSTTLs, may possibly be that the threshold voltage value Vin whereat commutation of the circuit is established is one half the value of the supply voltage Vdd, the latter lying within the range of 2 to 6 Volts for a HCMOS. In order to be compatible with TTL logic families, however, the threshold voltage should be a smaller value, e.g. close to a value of 1.3 Volts with a voltage supply in the 4.5 to 5.5 Volts range (as is typical of the LSTTL family). To fill this requirement, CMOS logic circuits have been proposed which have on their input side at least one inverter with a p-channel MOS of the implanted type and an n-channel MOS. That approach allows the threshold voltage to be lowered both on account of the p-channel MOS having a higher trigger voltage Vth and because the ratio of the β parameters of the two transistors can be manipulated. In this way, the threshold voltage of the CMOS circuit can be brought to a compatible value with that of the LSTTL families. However, with many applications, there is the added requirement that CMOS circuit inputs should be biased to a predetermined logic level dependent on their functions. This requirement is more heavily felt in peripheral units and computer bus connections. Now, where an LSTTL technology circuit is to be exchanged in applications for which the electronic board designer's goal is to impose a predetermined logic value on the inputs left floating, it is necessary that a bias network comprising external resistances with a high value in the 100 to 300 kOhms be associated with the HCMOS circuit. All this clashes with the current trend toward lower assembling costs, size and power consumption of electronic boards. Such demands are specially notable in the instance of miniaturized assembly procedures carried out using a Surface Mounting technology and of battery powered systems. A possible remedy to this drawback could be that of incorporating, to the CMOS integrated circuit, a resistance of appropriate value to each input, but it is quite apparent that such a solution would be unacceptable in terms of occupied silicon area due to the large value that said resistance ought to have. A known solution of this kind is disclosed in the: "Maxim 1989 Integrated Circuit Data Book, pages 8-14 and 8-15. The underlying technical problem of this invention is to provide a logic circuit of the CMOS type which has such structural and functional characteristics as to overcome the aforementioned drawbacks and affords full compatibility with logic families of the TTL or LSTTL type, to the point of making it feasible to exchange between different family circuits. Another object of the invention is to reduce the assembly costs, as well as the size and power consumption of electronic boards incorporating said logic circuits. Thus, the reliability of the inventive circuit can be improved over that of the two discrete circuits connected on a board, to provide a single integrated circuit whose overall performance can be guaranteed by the manufacturer. The solutive idea on which this invention stands is one of providing an equivalent bias resistor within the CMOS technology integrated circuit. A circuit according to the preamble portion of Claim 1 is known from EP 0 438 172 A. Based on this solutive idea, the technical problem is solved by a logic circuit of the kind set forth above and defined in the characterizing part of Claim 1. The features and advantages of a circuit according to the invention will become apparent from the following detailed description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. In those drawings: Figure 1 is a diagramatic representation of a CMOS logic circuit; Figure 2 is a diagramatic representation of a CMOS technology integrated circuit; Figure 3 shows a detail of the circuit in Figure 1; and Figure 4 shows a further alternative CMOS circuit Figure 5 shows an embodiment of the present invention. With reference to the drawing figures, generally and schematically shown at 1 is a logic circuit implemented in the CMOS technology. The circuit 1 has a signal or data input IN and an output OUT. Provided after the input IN are a set of cascade-connected inverters 3, each implemented in the CMOS technology with a p-channel MOS transistor being associated with an n-channel MOS transistor. In the first of said inverters, namely the external one that is to exhibit a TTL-compatible switch threshold, the p-channel MOS transistor has a higher trigger voltage Vthp, and by adjustment of the ratio of the β parameters of the two transistors, an unbalanced inverter can be obtained which operates with a switch threshold Vin compatible with the typical levels of the TTL logic families. Basically, the threshold voltage on the input IN would be defined by the following relation: Vin = [Vdd+Vth p +Vth n (βn/βp) ]/[1+ (βn/βp)] where: Vdd is the supply voltage (approximately 5 Volts) and Vth n is the threshold voltage for the n-channel MOS transistor. The output of the last inverter 3 in the cascade connection is connected to respective inputs of two logic gates 4 and 5 which receive, on other inputs, respective enable signals EN and ENN. Each logic gate 4, 5 has its output side connected to a corresponding gate electrode of a MOS transistor pair 6 being connected into an inverter configuration and having their connection point arranged to coincide with said output OUT of circuit 1. Advantageously, the circuit 1 has a circuit portion 7 connected to said signal input IN and being the equivalent of a high value resistance capable of biasing the input IN. More specifically, this portion 7 is a current mirror comprising a pair of transistors, M1 and M2. These transistors are preferably an enhancement p-channel MOS type and have the source electrode S in common. The drain D1 of the first transistor M1 is connected to both the gate G1 of that same transistor and the gate G2 of the second transistor M2. The drain D2 of the second transistor is connected to the data input IN of circuit 1. Also, the gate G1 is associated with a terminal RES for its connection to ground or, alternatively, to a reference potential via a resistor R1, as shown more detailedly in Figure 3. Therefore, the first transistor M1 in the mirror 7 and the resistor R1 will be unrelated to changes in the input voltage Vin and form a current generator whose value is stable even if Vin may vary. The second transistor M2 supplies, in turn, a near-constant current IIL until the value of the input voltage Vin approaches that of the voltage supply Vdd. In this way, the drain-to-source voltage drop Vds across the transistor can be reduced. As brought out by the foregoing considerations, the transistors M1 and M2 will exhibit the same gate-to-source voltage drop Vgs, thereby to ensure the current mirror structure and proper biasing of the input IN. By appropriate selection of the width to length ratio W/L for the channel region of the second transistor M2, the value of the current flowing through that transistor can be decreased, with obvious fan-out advantages for the drive circuits upstream of circuit 1. An exemplary use of the circuit 1 will now be described with reference to Figure 2. This circuit has been embedded in an integrated circuit 10 of the bus buffer type, also known as octal IC in the art since it includes eight circuits 1 arrayed on the IC. The circuit 10 has two enable inputs 1G and 2G which are connected, via some inverters T, to the various inputs ENi and ENNi of the logic gates 4 and 5 of each circuit 1. The circuit 10 also has plural outputs OUTi of the so-called inverted 3-state type whose basic feature is that they will not load the data buses while disabled. Each circuit 1 is connected in the IC 10 with the signal input IN led to a corresponding data input 1Ai or 2Ai. Advantageously, the terminals RES of the plural circuits 1 are all connected to ground through a single resistor R2 integrated, in turn, to the circuit 10. This resistor R2 is formed in a well of the p type by a process which is known per se. Thus, substantial savings can be achieved in silicon area, as the resistor R2 is shared by the eight inputs RES of the CMOS circuits 1. In order for the resistor R2 to be the full equivalent of the resistor R1 associated with the current mirror 7, it is selected to have a value which is n times that of R1, where n is the number of the circuits 1 embedded in the IC 10. Thus, since in the example being discussed n is eight, the savings in silicon area will be, in the connection used herein, n times the area to be occupied by a resistor of design value. It is understood that the circuit 1 may be implemented in the so-called dual form. An example of this is shown in Figure 4, wherein the current mirror portion 7 is implemented by a pair of n-channel MOS transistors M3 and M4 having gate electrodes in common. These transistors also have in common their source electrodes, with the latter being connected to ground as well. The resistor R1 is connected, in this case, to the voltage supply Vdd, whereas the drain D3 of the first transistor M3 in the pair is connected to the input IN. Briefly, this solution results in the inputs IN being fixed at a logic low. An embodiment of the invention is illustrated by Figure 5. In this embodiment, an inverter 9 is connected to the resistor R1. More particularly, the inverter 9 comprises a pair of MOS transistors M5, M6 having their gates in common and connected to a terminal A to receive an enable signal. The transistors M5, M6 are, the one a p-channel type and the other an n-channel type, and connected between the voltage supply Vdd and ground. The junction between the drains D5 and D6 of these transistors is connected to one end of the resistor R1. Thus, a turn-off circuit is provided which is effective to cut off the current mirror 7, and hence the input IN bias under control by the enable signal on the terminal A. The above embodiment of the inventive logic circuit does solve, therefore, the technical problem and affords a number of advantages, ensuring in the first place full exchangeability of different families of logic circuits for the same function. Another major advantage of the invention is that the lower power draw of the CMOS circuit provides an improved fan-out value at the drive gate. In addition, the linear pattern of the current IIL to the input at voltage Vin provides a near-constant value for said current with input voltages Vin that lie quite close to the supply voltage. It matters to observe, moreover, that the solution provided by this invention results in a uniquely flat input characteristic, being a definite improvement on that to be obtained through the use of a high-value integrated resistor. The resultant integrated circuit from embedding the inventive CMOS circuit therein, has involved a very modest increase in the circuit area as a trade-in for improved overall reliability.

Claims: 1. A CMOS logic circuit fully compatible with TTL logic families, of the type having inputs biased to a predetermined logic level and comprising at least one signal input (IN) and logic gates (4,5) for handling said signal to produce a buffered output (OUT), characterized in that it comprises a circuit portion (7) connected to said signal input (IN) and being equivalent to a high-value resistance adapted to bias said input (IN), wherein said circuit portion (7) comprises a current mirror connected between a reference potential (Vdd) and said signal input (IN); said logic circuit further comprising a resistor (R1) connected between an input of said current mirror (7) and ground and a turn-off circuit (9) of said circuit portion (7) operative to cut-off the input bias under control by an enable signal, said turn-off circuit including an inverter (9) connected to one end of said resistor (R1). A logic circuit according to Claim 1, characterized in that said circuit portion (7) is free of resistors. A logic circuit according to Claim 2, characterized in that said reference potential is either a supply pole or a signal ground. A logic circuit according to Claim 2, characterized in that said current mirror comprises a pair of p-channel MOS transistors. A logic circuit according to Claim 2, characterized in that said current mirror comprises a pair of n-channel MOS transistor. A circuit according to Claim 2, characterized in that it is embedded in an integrated circuit (10) together with a resistor (R2) having a predetermined value and an input of said current mirror connected thereto. A logic circuit according to Claim 6, characterized in that said resistor is formed in a p-type well. A circuit according to Claims 1 and 6, characterized in that said resistor has a value which is n times said resistance, where n is the number of the logic circuits (1) embedded in the integrated circuit (10).

Inventors: BENENATI GIOVANNI, IMBRUGLIA ANTONIO, BENENATI, GIOVANNI, IMBRUGLIA, ANTONIO
Applicants: CO RI M ME BR CONSORZIO PER LA, CO.RI.M.ME.<BR>CONSORZIO PER LA RICERCA SULLA<BR>MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1992
Main classification: H03K19
IPC codes: H03K19