Active matrix substrate device and related method

Abstract: An active matrix substrate includes a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to the n-type and p-type transistors for controlling the n-type and p-type transistors, and pixel-corresponding electrodes controlled by the transistor pairs respectively. Drains of an n-type transistor and a p-type transistor in each of the pairs are connected to each other via a related pixel corresponding electrode. First pulses are applied to gates of the n-type transistors. Second pulses are applied to gates of the p-type transistors. There is provided a difference in phase between the first pulses and the second pulses.

Description: This invention relates to a liquid crystal display, an image sensor, or other devices using an active matrix substrate. This invention also relates to a method of driving an active matrix substrate, and a method of fabricating an active matrix substrate. Japanese published unexamined patent application 63-82177 discloses a liquid crystal display apparatus using an active matrix substrate. The active matrix substrate has a matrix array of gate electrodes and source electrodes. Each of intersections of the gate electrodes and the source electrodes is provided with a pair of p-type and n-type thin-film transistors (TFTs) for controlling a liquid crystal display element corresponding to a pixel. In the display apparatus of Japanese patent application 63-82177, each pair of p-type and n-type TFTs are activated by drive signals having opposite polarities to prevent or reduce a drop in a drive voltage. In addition, off-timings of gate pulses applied to the p-type and n-type TFTs are made coincident to prevent the occurrence of noise induced via parasitic capacitances. Japanese published unexamined patent application 2-178632 also discloses a liquid crystal display apparatus using an active matrix substrate. The active matrix substrate has a matrix array of gate electrodes and source electrodes. Each of intersections of the gate electrodes and the source electrodes is provided with a pair of p-type and n-type thin-film transistors (TFTs) for controlling a liquid crystal display element corresponding to a pixel. In the display apparatus of Japanese patent application 2-178632, drain electrodes of p-type and n-type TFTs in each pair are electrically connected to each other, and there are provided additional (supplemental) capacitors between the drain electrodes and the gate electrodes. In the display apparatus of Japanese patent application 2-178632, it is necessary to make coincident off-timings of gate pulses applied to the p-type and n-type TFTs. Patents Abstracts of Japan, Vol. 14, No. 219 (P-1045) of May 9, 1990 & JP-A-2 050 132 disclose an active matrix liquid cristal display with a circuit arrangement removing the DC component at a pixel-corresponding electrode caused by a gate threshold of a transistor. It is an object of this invention to provide an improved device using an active matrix substrate and to provide an improved method of driving an active matrix substrate. Furthermore, this invention aims to provide an improved method of fabricating an active matrix substrate. In particular, the present invention aims at compensating for the DC offset caused by the switching transient and the capacitive coupling between the gate and drain of the n-type transistor. This object is achieved by a method of driving an apparatus comprising an active matrix substrate as defined in claim 1. Furthermore, this object is achieved by an apparatus as set out in claim 6. Claim 9 specifies a method of fabricating the apparatus of claim 6. Advantageous further developments are as set out in the dependent claims. Fig. 1 is a schematic diagram of an equivalent circuit of a background-art active matrix substrate. Fig. 2 is a plan view of a part of the active matrix substrate of Fig. 1. Fig. 3 is a sectional view of a part of the active matrix substrate taken along the line III-III of Fig. 2. Fig. 4 is a sectional view of a part of a liquid crystal display using the active matrix substrate of Figs. 1-3. Fig. 5 is a schematic diagram of an equivalent circuit of an active matrix substrate and associated registers according to a first embodiment of this invention. Fig. 6 is a time-domain diagram showing the waveforms of various signals in the circuit of Fig. 5. Figs. 7 and 8 are block diagrams of the vertical shift registers in Fig. 5. Fig. 9 is a schematic diagram of an equivalent circuit of an active matrix substrate and associated registers according to a second embodiment of this invention. Fig. 10 is a time-domain diagram showing the waveforms of various signals in the circuit of Fig. 9. Figs. 11 and 12 are block diagrams of the vertical shift registers in Fig. 9. Fig. 13 is a time-domain diagram showing the waveforms of various signals in a modification of the circuit of Fig. 5. Figs. 14 and 15 are block diagrams of vertical shift registers in a circuit according to a third embodiment of this invention. Figs. 16(a)-16(i) are sectional views of a substrate in various states which occur during fabrication based on a fourth embodiment of this invention. With reference to Fig. 1, an active matrix substrate in a liquid crystal display includes a second substrate or a transparent substrate, and a matrix array of thin-film transistors (TFTs) 1 formed on the transparent substrate. Liquid crystal display elements or cells 2 are arranged in a matrix. The display elements 2 are controlled by the TFTs 1 respectively. Each display cell 2 includes a given pixel-corresponding region of liquid crystal held between a transparent electrode and an opposed electrode. The transparent electrode is electrically connected to the drain of the related TFT 1. The opposed electrode extends on another transparent substrate forming a color filter. The display cells 2 correspond to pixels in an image indication region 3 respectively. In some cases, supplemental capacitors are provided on the active matrix substrate in addition to the capacitances related to the liquid crystal in the display cells 2. The active matrix substrate is provided with a set of parallel gate wiring lines 4, and a set of parallel source wiring lines 5 perpendicular to the gate wiring lines 4. The gate wiring lines 4 correspond to rows of the matrix, while the source wiring lines 5 correspond to columns of the matrix. The gate electrodes of the TFTs 1 in a common row are electrically connected to corresponding one of the gate wiring lines 4. The source electrodes of the TFTs 1 in a common column are electrically connected to corresponding one of the source wiring lines 5. Each of the TFTs 1 in Fig. 1 has the following design. As shown in Figs. 2 and 3, a TFT 1 formed on a glass substrate member (a transparent substrate member) 6 includes a gate electrode 7, a gate insulating layer 9, a semiconductor layer 10, an etching stopper layer 11, a drain electrode 14, and a source electrode 15. In addition, the TFT 1 includes an n + semiconductor layer 12 which provides ohmic contacts among the semiconductor layer 10, the drain electrode 14, and the source electrode 15. A transparent electrode 17 extending on the glass substrate member 6 is electrically connected to the drain electrode 14. The transparent electrode 17 constitutes a pixel-corresponding electrode which enables the application of a voltage to a given pixel-corresponding region of a liquid crystal layer. As shown in Fig. 4, the liquid crystal display includes the active matrix substrate 25 (see Figs. 1-3), and another substrate 26 opposed to the substrate 25. The opposed substrate 26 includes a second substrate or a transparent substrate 20, and a transparent electrode 21 formed on the transparent substrate 20. The active matrix substrate 25 and the opposed substrate 26 are spaced by a given gap. The space between the active matrix substrate 25 and the opposite substrate 26 is filled with twist nematic (TN) liquid crystal. One surfaces of the two substrates 25 and 26 are provided with polarizers. During the operation of the liquid crystal display, gate pulses are applied to the TFTs 1. In each of the TFTs 1, when a related gate pulse changes to an off state, this change is transmitted to the drain of the TFT via a gate-drain parasitic capacitance so that a drain electrode voltage is shifted or varied by a level ΔV. The voltage shift level ΔV is given by the following equation. ΔV = C P C ST + C P + C LC • V P-P where C LC denotes the capacitance of a cell (a display element) corresponding to one pixel; C ST denotes the supplemental capacitance; C P denotes the parasitic capacitance of the TFT 1; and V P-P denotes the height (amplitude) of the gate voltage. The voltage shift levels are always in a same direction (a minus direction), so that voltages applied to the display cells have DC offset components. Such DC offset components cause a degradation of the reliability of the liquid crystal display and a degradation of the quality. DESCRIPTION OF THE FIRST PREFERRED EMBODIMENT With reference to Fig. 5, an active matrix substrate in a liquid crystal display includes a second substrate or a transparent substrate, a matrix array of n-type thin-film transistors (TFTs) 31a-31i formed on the transparent substrate, and a matrix array of p-type thin-film transistors (TFTs) 32a-32i formed on the transparent substrate. The semiconductor layer of these TFTs are basically made of polycrystalline silicon or amorphous (non-crystalline) silicon. Liquid crystal display elements or cells 33a-33i are arranged in a matrix. The n-type TFTs 31a-31i, the p-type TFTs 32a-32i, and the cells 33a-33i are separated into groups which correspond to pixels respectively and which are arranged in a matrix. Specifically, each group has one n-type TFT, one p-type TFT, and one cell. Each of the cells 33a-33i has a given pixel-corresponding region of liquid crystal held between a transparent electrode (a pixel-corresponding electrode) and an opposite electrode 37. The transparent electrode (the pixel-corresponding electrode) is connected to the drain electrodes of the related n-type TFT and the related p-type TFT. The opposite electrode 37 extends on an opposite substrate (not shown). In Fig. 5, the display cells 33a-33i are illustrated as capacitors. In fact, each of the display cells 33a-33i has a capacitance which depends on various factors such as the dielectric constant of the liquid crystal and the design of the related transparent electrode (the pixel-corresponding electrode). It should be noted that the active matrix substrate may be formed with supplemental capacitors which provide capacitances in addition to the capacitances of the display cells 33a-33i. A first set of gate bus lines 34a-34c, and a second set of gate bus lines 35a-35c correspond to rows of the matrix. A set of source bus lines 36a-36c correspond to columns of the matrix. The gate electrodes of the n-type TFTs in a common row are electrically connected to corresponding one of the gate bus lines 34a-34c. The gate electrodes of the p-type TFTs in a common row are electrically connected to corresponding one of the gate bus lines 35a-35c. The source electrodes of the n-type TFTs and the p-type TFTs in a common column are electrically connected to corresponding one of the source bus lines 36a-36c. The gate bus lines 34a-34c electrically lead to a vertical shift register 38 which outputs gate pulse signals for the n-type TFTs. The gate bus lines 35a-35c electrically lead to another vertical shift register 39 which outputs gate pulse signals for the p-type TFTs. The source bus lines 36a-36c electrically lead to a horizontal shift register 40 which outputs image-information signals. The operation of the liquid crystal display of Fig. 5 will now be described. For the simplicity, the following description relates mainly to the operation of a group of the n-type TFT 31a, the p-type TFT 32a, and the display cell 33a which is connected to the gate bus lines 34a and 35a, and the source bus line 36a. During a 1-field interval, image-information signals which correspond to respective vertical segments of an image are fed from the horizontal shift register 40 to respective columns of the matrix. Each image-information signal sequentially represents pieces of image information which correspond to respective pixels in the related column of the matrix. During the 1-field interval, the vertical shift register 38 sequentially feeds gate pulses to rows of the matrix, and also the vertical shift register 39 sequentially feeds gate pulses to rows of the matrix. Pixels in one row of the matrix are scanned during the application of a single gate pulse from the vertical shift register 38 and the application of a single gate pulse from the vertical shift register 39. In each group of an n-type TFT, a p-type TFT, and a display cell, when the n-type TFT and the p-type TFT receive gate pulses from the vertical shift registers 38 and 39, the n-type TFT and the p-type TFT become conductive so that the image information is transferred from the sources of the n-type TFT and the p-type TFT to the display cell. Thus, in each group, the n-type TFT and the p-type TFT serve as switches for selectively enabling and inhibiting the transmission of image information from the source side to the display cell, and the switches are closed and opened in response to signals fed to the gates of the n-type TFT and the p-type TFT. It is now assumed that, as shown in Fig. 6, a source input signal s outputted from the horizontal shift register 40 changes in polarity from a negative state to a positive state at a moment t 0 and then remains at the positive state for a 1-field interval until a moment t 3 , and the source input signal s changes in polarity from the positive state to the negative state at the moment t 3 and then remains at the negative state for a next 1-field interval. Such a source input signal s corresponds to, for example, a vertically-extending black or white linear segment of an indicated image. During the period where the source input signal s remains at the positive state, at a moment t 1 which follows the moment t 0 , the n-type TFT 31a starts to be fed with a gate pulse Gn from the vertical shift register 38 so that the n-type TFT 31a becomes conductive and thus the related capacitor 33a starts to be charged by the source input signal s. The gate pulse Gn lasts for a given interval. During the period where the source input signal s remains at the positive state, at a moment which follows the moment t 1 by a given short interval Δt 1 , the p-type TFT 32a starts to be fed with a gate pulse Gp from the vertical shift register 39 so that the p-type TFT 32a also becomes conductive and thus the related capacitor 33a is charged by the source input signal s at a higher rate. Then, the gate pulse Gn terminates and subsequently the gate pulse Gp terminates. When the gate pulse Gn terminates, that is, when the voltage of the gate of the n-type TFT 31a drops from the higher level to the lower level, this gate voltage drop is undesirably transmitted to the drain of the n-type TFT 31a via the parasitic capacitance between the gate and the drain of the n-type TFT 31a so that the voltage of the drain of the n-type TFT 31a shifts in accordance with the gate voltage drop. Specifically, when the gate pulse Gn terminates, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change or shift ΔVn which is given as follows. ΔVn = C P C ST + C P + C LC • ( V n gh - V n gℓ ) where C LC denotes the capacitance of a display cell corresponding to one pixel; C ST denotes the supplemental capacitance; Cp denotes the parasitic capacitance between the gate and the drain of the n-type TFT 31a; V n / gh denotes the higher level of the gate signal Gn; and V n / gℓ denotes the lower level of the gate signal Gn. At the moment of the termination of the gate pulse Gn, the gate pulse Gp remains present and thus the p-type TFT 32a continues to be conductive so that the capacitor 33a keeps charged. Thus, at the moment of the termination of the gate pulse Gn, the previously-mentioned level change AVn in the drain voltage Vs is suppressed or compensated. During the subsequent period until the moment t 2 of the termination of the gate pulse Gp, the capacitor 33a is charged to the level of the source input signal s. At the moment t 2 of the termination of the gate pulse Gp, the voltage of the gate of the p-type TFT 32a rises from the lower level to the higher level, this gate voltage rise is undesirably transmitted to the drain of the p-type TFT 32a via the parasitic capacitance between the gate and the drain of the p-type TFT 32a so that the voltage of the drain of the p-type TFT 32a shifts in accordance with the gate voltage rise. Specifically, at the moment t 2 of the termination of the gate pulse Gp, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change ΔVp which is given as follows. ΔVp = - C P C ST + C P + C LC •( V p gh - V p gℓ ) where C LC denotes the capacitance of a display cell corresponding to one pixel; C ST denotes the supplemental capacitance; Cp denotes the parasitic capacitance between the gate and the drain of the p-type TFT 32a; V p / gh denotes the higher level of the gate signal Gp; and V p / gℓ denotes the lower level of the gate signal Gp. During the next 1-field interval which starts at the moment t 3 , the source input signal s remains at the negative state. During this 1-field interval, at a moment t 4 subsequent to the moment t 3 , the p-type TFT 32a starts to be fed with a gate pulse Gp from the vertical shift register 39 so that the p-type TFT 32a becomes conductive and thus the related capacitor 33a starts to be charged (discharged) by the source input signal s. The gate pulse Gp lasts for a given interval. During the period where the source input signal s remains at the negative state, at a moment which follows the moment t 4 by a given short interval Δt 2 , the n-type TFT 31a starts to be fed with a gate pulse Gn from the vertical shift register 38 so that the n-type TFT 31a also becomes conductive and thus the related capacitor 33a is charged (discharged) by the source input signal s at a higher rate. Then, the gate pulse Gp terminates and subsequently the gate pulse Gn terminates. When the gate pulse Gp terminates, that is, when the voltage of the gate of the p-type TFT 32a rises from the lower level to the higher level, this gate voltage rise is undesirably transmitted to the drain of the p-type TFT 32a via the parasitic capacitance between the gate and the drain of the p-type TFT 32a so that the voltage of the drain of the p-type TFT 32a shifts in accordance with the gate voltage rise. Specifically, when the gate pulse Gp terminates, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change ΔVp which is expressed by the previous-mentioned equation (3). At the moment of the termination of the gate pulse Gp, the gate pulse Gn remains present and thus the n-type TFT 31a continues to be conductive so that the capacitor 33a keeps charged (discharged). Thus, at the moment of the termination of the gate pulse Gp, the previously-mentioned level change ΔVp in the drain voltage Vs is suppressed or compensated. During the subsequent period until the moment t 5 of the termination of the gate pulse Gn, the capacitor 33a is charged (discharged) to the level of the source input signal s. At the moment t 5 of the termination of the gate pulse Gn, the voltage of the gate of the n-type TFT 31a drops from the higher level to the lower level, this gate voltage drop is undesirably transmitted to the drain of the n-type TFT 31a via the parasitic capacitance between the gate and the drain of the n-type TFT 31a so that the voltage of the drain of the n-type TFT 31a shifts in accordance with the gate voltage drop. Specifically, at the moment t 5 of the termination of the gate pulse Gn, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change ΔVn which is expressed by the previously-mentioned equation (2). As shown in Fig. 6, the voltage shift ΔVp which occurs at the moment t 2 of the termination of the gate pulse Gp is opposite in direction (polarity) to the voltage shift ΔVn which occurs at the moment t 5 of the termination of the gate pulse Gn. Thus, the voltage shifts ΔVp and ΔVn are cancelled so that a DC offset component of the related drain voltage Vs can be reduced or removed in time average. A DC offset component of the drain voltage Vs can be completely removed by equalizing the absolute values of the voltage shifts ΔVp and ΔVn. Equalizing the absolute values of the voltage shifts ΔVp and ΔVn is realized by suitably choosing the heights of the gate pulses Gn and Gp and the parasitic capacitances of the n-type and p-type TFT transistors 31a and 32a. In cases where a given DC offset component is required to be added to the drain voltage Vs, a suitable choice of the heights of the gate pulses Gn and Gp can meet this requirement. As shown in Fig. 7, the vertical shift register 38 includes a shift register main part 51, delay circuits 52a-52c, and switches 53a-53c. The shift register main part 51 outputs original gate pulses to the switches 53a-53c as non-delayed pulses respectively. The shift register main part 51 also outputs the original gate pulses to the delay circuits 52a-52c respectively. The delay circuits 52a-52c delay the original gate pulses by given times and thus output delayed pulses respectively. The delay circuits 52a-52c output the delayed pulses to the switches 53a-53c respectively. The switch 53a selects either the non-delayed pulse or the delayed pulse in response to a binary field signal F which changes between a higher level and a lower level at a period corresponding to a field. For example, during a first 1-field interval, the switch 53a selects the non-delayed pulse and transmits the non-delayed pulse to the gate bus line 34a (see Fig. 5) as a gate pulse Gn. During a second 1-field interval, the switch 53a selects the delayed pulse and transmits the delayed pulse to the gate bus line 34a (see Fig. 5) as a gate pulse Gn. Similarly, the switch 53b selects either the non-delayed pulse or the delayed pulse in response to the binary field signal F, and transmits the selected pulse to the gate bus line 34b (see Fig. 5). In addition, the switch 53c selects either the non-delayed pulse or the delayed pulse in response to the binary field signal F, and transmits the selected pulse to the gate bus line 34c (see Fig. 5). As shown In Fig. 8, the vertical shift register 39 includes a shift register main part 61, delay circuits 62a-62c, and switches 63a-63c. The shift register main part 61 outputs original gate pulses to the switches 63a-63c as non-delayed pulses respectively. The shift register main part 61 also outputs the original gate pulses to the delay circuits 62a-62c respectively. The delay circuits 62a-62c delay the original gate pulses by given times and thus output delayed pulses respectively. The delay circuits 62a-62c output the delayed pulses to the switches 63a-63c respectively. The switch 63a selects either the non-delayed pulse or the delayed pulse in response to the binary field signal F. For example, during a first 1-field interval, the switch 63a selects the delayed pulse and transmits the delayed pulse to the gate bus line 35a (see Fig. 5) as a gate pulse Gp. During a second 1-field interval, the switch 63a selects the non-delayed pulse and transmits the non-delayed pulse to the gate bus line 35a (see Fig. 5) as a gate pulse Gp. Similarly, the switch 63b selects either the non-delayed pulse or the delayed pulse in response to the binary field signal F, and transmits the selected pulse to the gate bus line 35b (see Fig. 5). In addition, the switch 63c selects either the non-delayed pulse or the delayed pulse in response to the binary field signal F, and transmits the selected pulse to the gate bus line 35c (see Fig. 5). It should be noted that gate pulses Gn and Gp may have a timing relation such as shown in Fig. 13. According to the timing relation of Fig. 13, during a first 1-field interval, at a moment t 1 preceding a 1-H period (a horizontal scanning period) for which the display cell 33a is scanned, the n-type TFT 31a starts to be fed with a gate pulse Gn. Before a moment t 2 which follows the 1-H period, the gate pulse Gn terminates. At the moment t 2 , the p-type TFT 32a starts to be fed with a gate pulse Gp. At a moment t 3 following the moment t 2 , the gate pulse Gp terminates. During a second 1-field interval, at a moment t 5 preceding a 1-H period (a horizontal scanning period) for which the display cell 33a is scanned, the p-type TFT 32a starts to be fed with a gate pulse Gp. Before a moment t 6 which follows the 1-H period, the gate pulse Gp terminates. At the moment t 6 , the n-type TFT 31a starts to be fed with a gate pulse Gn. At a moment t 7 following the moment t 6 , the gate pulse Gn terminates. It should be noted that "field" may be replaced by "frame" or other given periods. DESCRIPTION OF THE SECOND PREFERRED EMBODIMENT Fig. 9 shows a second embodiment of this invention which is similar to the embodiment of Figs. 5-8 except for design changes indicated hereinafter. The embodiment of Fig. 9 has modified vertical shift registers 38A and 39A. It is now assumed that, as shown in Fig. 6, a source input signal s outputted from a horizontal shift register 40 changes in polarity from a negative state to a positive state at a moment t 0 and then remains at the positive state for a 1-field interval until a moment t 3 , and the source input signal s changes in polarity from the positive state to the negative state at the moment t 3 and then remains at the negative state for a next 1-field interval. Such a source input signal s corresponds to, for example, a vertically-extending black or white linear segment of an indicated image. During the period where the source input signal s remains at the positive state, at a moment t 1 which follows the moment t 0 , an n-type TFT 31a and a p-type TFT 32a start to be fed with gate pulses Gn and Gp from the vertical shift registers 38A and 39A so that both the n-type TFT 31a and the p-type TFT 32a become conductive and thus a related capacitor 33a starts to be charged by the source input signal s. The gate pulse Gn lasts for a given interval which is shorter than the duration of the gate pulse Gp. Thus, the gate pulse Gn terminates before the gate pulse Gp terminates. During the period where the source input signal s remains at the positive state, the gate pulse Gn terminates and subsequently the gate pulse Gp terminates. When the gate pulse Gn terminates, that is, when the voltage of the gate of the n-type TFT 31a drops from the higher level to the lower level, this gate voltage drop is undesirably transmitted to the drain of the n-type TFT 31a via the parasitic capacitance between the gate and the drain of the n-type TFT 31a so that the voltage of the drain of the n-type TFT 31a shifts in accordance with the gate voltage drop. Specifically, when the gate pulse Gn terminates, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change or shift ΔVn which is expressed by the previously-mentioned equation (2). At the moment of the termination of the gate pulse Gn, the gate pulse Gp remains present and thus the p-type TFT 32a continues to be conductive so that the capacitor 33a keeps charged. Thus, at the moment of the termination of the gate pulse Gn, the previously-mentioned level change ΔVn in the drain voltage Vs is suppressed or compensated. During the subsequent period until the moment t 2 of the termination of the gate pulse Gp, the capacitor 33a is charged to the level of the source input signal s. At the moment t 2 of the termination of the gate pulse Gp, the voltage of the gate of the p-type TFT 32a rises from the lower level to the higher level, this gate voltage rise is undesirably transmitted to the drain of the p-type TFT 32a via the parasitic capacitance between the gate and the drain of the p-type TFT 32a so that the voltage of the drain of the p-type TFT 32a shifts in accordance with the gate voltage rise. Specifically, at the moment t 2 of the termination of the gate pulse Gp, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change ΔVp which is expressed by the previously-mentioned equation (3). During the next 1-field period which starts at the moment t 3 , the source input signal s remains at the negative state. During this 1-field period, at a moment t 4 subsequent to the moment t 3 , the n-type TFT 31a and the p-type TFT 32a start to be fed with gate pulses Gn and Gp from the vertical shift registers 38A and 39A so that both the n-type TFT 31a and the p-type TFT 32a become conductive and thus the related capacitor 33a starts to be charged (discharged) by the source input signal s. The gate pulse Gn lasts for a given interval which is longer than the duration of the gate pulse Gp. Thus, the gate pulse Gn terminates after the gate pulse Gp terminates. During the period where the source input signal s remains at the negative state, the gate pulse Gp terminates and subsequently the gate pulse Gn terminates. When the gate pulse Gp terminates, that is, when the voltage of the gate of the p-type TFT 32a rises from the lower level to the higher level, this gate voltage rise is undesirably transmitted to the drain of the p-type TFT 32a via the parasitic capacitance between the gate and the drain of the p-type TFT 32a so that the voltage of the drain of the p-type TFT 32a shifts in accordance with the gate voltage rise. Specifically, when the gate pulse Gp terminates, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) is subjected to a level change ΔVp which is expressed by the previous-mentioned equation (3). At the moment of the termination of the gate pulse Gp, the gate pulse Gn remains present and thus the n-type TFT 31a continues to be conductive so that the capacitor 33a keeps charged (discharged). Thus, at the moment of the termination of the gate pulse Gp, the previously-mentioned level change ΔVp in the drain voltage Vs is suppressed or compensated. During the subsequent period until the moment t 5 of the termination of the gate pulse Gn, the capacitor 33a is charged (discharged) to the level of the source input signal s. At the moment t 5 of the termination of the gate pulse Gn, the voltage of the gate of the n-type TFT 31a drops from the higher level to the lower level, this gate voltage drop is undesirably transmitted to the drain of the n-type TFT 31a via the parasitic capacitance between the gate and the drain of the n-type TFT 31a so that the voltage of the drain of the n-type TFT 31a shifts in accordance with the gate voltage drop. Specifically, at the moment t 5 of the termination of the gate pulse Gn, the voltage Vs at the drains of the n-type TFT 31a and the p-type TFT 32a (the voltage at the pixel-corresponding electrode) Is subjected to a level change ΔVn which is expressed by the previously-mentioned equation (2). As shown in Fig. 10, the voltage shift ΔVp which occurs at the moment t 2 of the termination of the gate pulse Gp is opposite in direction (polarity) to the voltage shift ΔVn which occurs at the moment t 5 of the termination of the gate pulse Gn. Thus, the voltage shifts ΔVp and ΔVn are cancelled so that a DC offset component of the related drain voltage Vs can be reduced or removed in time average. A DC offset component of the drain voltage Vs can be completely removed by equalizing the absolute values of the voltage shifts ΔVp and ΔVn. Equalizing the absolute values of the voltage shifts ΔVp and ΔVn is realized by suitably choosing the heights of the gate pulses Gn and Gp and the parasitic capacitances of the n-type and p-type TFT transistors 31a and 32a. In cases where a given DC offset component is required to be added to the drain voltage Vs, a suitable choice of the heights of the gate pulses Gn and Gp can meet this requirement. As shown In Fig. 11, the vertical shift register 38A includes a shift register main part 71, monostable multivibrators 72a-72c, and switches 73a-73c. The shift register main part 71 outputs original gate pulses to the switches 73a-73c as shorter pulses respectively. The shift register main part 71 also outputs the original gate pulses to the monostable multivibrators 72a-72c respectively. The monostable multivibrators 72a-72c lengthen the original gate pulses by given times and thus output longer pulses respectively. The monostable multivibrators 72a-72c output the longer pulses to the switches 73a-73c respectively. The switch 73a selects either the shorter pulse or the longer pulse in response to a binary field signal F which changes between a higher level and a lower level at a period corresponding to a field. For example, during a first 1-field interval, the switch 73a selects the shorter pulse and transmits the shorter pulse to a gate bus line 34a (see Fig. 9) as a gate pulse Gn. During a second 1-field interval, the switch 73a selects the longer pulse and transmits the longer pulse to the gate bus line 34a (see Fig. 9) as a gate pulse Gn. Similarly, the switch 73b selects either the shorter pulse or the longer pulse in response to the binary field signal F, and transmits the selected pulse to a gate bus line 34b (see Fig. 9). In addition, the switch 73c selects either the shorter pulse or the longer pulse in response to the binary field signal F, and transmits the selected pulse to a gate bus line 34c (see Fig. 9). As shown In Fig. 12, the vertical shift register 39A includes a shift register main part 81, monostable multivibrators 82a-82c, and switches 83a-83c. The shift register main part 81 outputs original gate pulses to the switches 83a-83c as shorter pulses respectively. The shift register main part 81 also outputs the original gate pulses to the monostable multivibrators 82a-82c respectively. The monostable multivibrators 82a-82c lengthen the original gate pulses by given times and thus output longer pulses respectively. The monostable multivibrators 82a-82c output the longer pulses to the switches 83a-83c respectively. The switch 83a selects either the shorter pulse or the longer pulse in response to the binary field signal F. For example, during a first 1-field interval, the switch 83a selects the longer pulse and transmits the longer pulse to a gate bus line 35a (see Fig. 9) as a gate pulse Gp. During a second 1-field interval, the switch 83a selects the shorter pulse and transmits the shorter pulse to the gate bus line 35a (see Fig. 9) as a gate pulse Gp. Similarly, the switch 83b selects either the shorter pulse or the longer pulse in response to the binary field signal F, and transmits the selected pulse to a gate bus line 35b (see Fig. 9). In addition, the switch 83c selects either the shorter pulse or the longer pulse in response to the binary field signal F, and transmits the selected pulse to a gate bus line 35c (see Fig. 9). DESCRIPTION OF THE THIRD PREFERRED EMBODIMENT Figs. 14 and 15 relate to a third embodiment of this invention which is similar to the embodiment of Figs. 5-8 except for design changes indicated hereinafter. The embodiment of Figs. 14 and 15 has modified vertical shift registers 38B and 39B. As shown in Fig. 14, the vertical shift register 38B includes amplifiers 54a-54c which follow switches 53a-53c respectively. The amplifiers 54a-54c output gate pulses Gn to gate bus lines 34a-34c (see Fig. 5) respectively. As shown In Fig. 15, the vertical shift register 39B includes amplifiers 64a-64c which follow switches 63a-63c respectively. The amplifiers 64a-64c output gate pulses Gp to gate bus lines 35a-35c (see Fig. 5) respectively. The gains of the amplifiers 54a-54c are different from the gains of the amplifiers 64a-64c so that the height of the gate pulses Gn is different from the height of the gate pulses Gp. DESCRIPTION OF THE FOURTH PREFERRED EMBODIMENT A fourth embodiment of this invention relates to a method of fabricating an active matrix substrate of the embodiments of Figs. 5-15. The fourth embodiment will now be explained with reference to Figs. 16(a) to 16(i). A transparent substrate 150 made of quartz or Corning #7059 was prepared. As shown in Fig. 16(a), a buffer layer 151 was formed on the transparent substrate 150. The buffer layer 151 was made of silicon dioxide or silicon nitride. An amorphous (non-crystalline) silicon layer 152 and a dielectric film 153 were successively formed on the buffer layer 151 by a plasma CVD method. The dielectric film 151 was made of silicon oxide, silicon nitride, a mixture of silicon oxide and silicon nitride, or another metal oxide. Then, as shown in Fig. 16(b), the substrate was subjected to a given process 154 so that the amorphous silicon layer 152 changed to a polycrystalline silicon layer 155. The given process included a heating process, an energy beam process, or a composite process having both a heating process and an energy beam process. For example, during the heating process, the substrate was located in a vacuum or in an inert gas, and the substrate was heated by a resistor-based heating device or a lamp annealing device. The energy beam process was executed by using an argon ion laser or an excimer laser. Subsequently, as shown in Fig. 16(c), given regions of the dielectric film 153 and the polycrystalline silicon layer 155 were removed from the substrate by a photographic etching technique. Then, as shown In Fig. 16(d), a dielectric film 156 and an electrically-conductive layer 157 were formed on the substrate. The dielectric film 156 was made of silicon oxide or silicon nitride. The electrically-conductive layer 157 was made of a metal or an impurity-doped polycrystalline silicon. Given regions of the dielectric films 153 and 156 and the electrically-conductive layer 157 were removed from the substrate. Then, as shown in Fig. 16(e), impurity ions 158 were implanted into the substrate by an ion implantation apparatus or an ion shower apparatus, and an activating process was done so that n-type or p-type TFT source-drain regions 159 were formed. During the subsequent period, after an inter-layer insulating member 160 was formed on the substrate as shown in Fig. 16(f), given regions of the inter-layer insulating member 160, the electrically-conductive layer 157, and the dielectric films 153 and 156 were removed from the substrate. Then, as shown in Fig. 16(g), impurity ions 161 were implanted into the substrate by the ion implantation apparatus or the ion shower apparatus, and an activating process was done so that p-type or n-type TFT source-drain regions 162 were formed. The impurity ions 158 were phosphor ions while the impurity ions 161 were boron ions. It may be good that the impurity ions 158 are boron ions while the impurity ions 161 are phosphor ions. Thus, there were formed pairs each having one n-type TFT and one p-type TFT. After an inter-layer insulating member 163 was formed on the substrate, given regions of the inter-layer insulating member 163 which extended above the source-drain regions of the TFTs were removed from the substrate as shown in Fig. 16(h). Then, as shown in Fig. 16(i), transparent electrically-conductive films 164 were formed on given regions of the substrate, and the source-drain regions of the TFTs were metalized by members 165 made of metal such as aluminum. The transparent electrically-conductive films 164 constituted pixel-corresponding electrodes. During the formation of the transparent electrically-conductive films 164 and the metalization of the source-drain regions of the TFTs, the drains of an n-type TFT and a p-type TFT in each pair were electrically connected via a related pixel-corresponding electrode 164. In this way, the active matrix substrate was fabricated.

Claims: A method of driving an apparatus comprising an active matrix substrate including pairs of transistors, each pair having an n-type switching transistor ( 31 ) and a p-type switching transistor ( 32 ), and pixel-corresponding electrodes ( 33 ) connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel-corresponding electrode via the pair; the method comprising the steps of: applying two first pulses to gates of said n-type transistors in said pairs contained in a common row of the matrix in a given interval; and applying two second pulses to gates of said p-type transistors in said pairs contained in said common row of the matrix in a given interval; the method being characterized by i) turning off said n-type transistors before said p-type transistors during one half ( t 0 -t 3 ) of said given interval, ii) turning off said p-type transistors before said n-type transistors during the other half of said given interval. A method according to claim 1, further comprising the step of providing a difference in pulse width between said first pulses and said second pulses. A method according to claim 2, further comprising the steps of changing a pulse width of said first pulses every field, and changing a pulse width of said second pulses every field. A method according to claim 2, further comprising the steps of changing a pulse width of said first pulses every frame, and changing a pulse width of said second pulses every frame. A method according to claim 1, further comprising the step of providing a difference in pulse height between said first pulses and said second pulses. An apparatus comprising; an active matrix substrate including pairs of transistors, each pair having an n-type switching transistor ( 31 ) and a p-type switching transistor ( 32 ), and pixel-corresponding electrodes ( 33 ) connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel-corresponding electrode via the pair; means ( 38 ) for feeding two first pulses to gates of n-type switching transistors ( 31 ) in said pairs contained in a common row of the matrix in a given interval; and means ( 39 ) for feeding two second pulses to gates of p-type switching transistors ( 32 ) in said pairs contained in said common row of the matrix in said given interval; characterized in that said means for feeding are arranged to: i) turn off said n-type switching transistors before said p-type switching transistors during one half ( t 0 -t 3 ) of said given interval, ii) turn off said p-type switching transistors before said n-type switching transistors during the other half of said given interval. An apparatus according to claim 6, further comprising means for providing a difference in pulse width between the first pulses and the second pulses. An apparatus according to claim 6, further comprising means for providing a difference in pulse height between the first pulses and the second pulses. A method of fabricating the apparatus of claim 6, the method comprising the steps of: forming n-type thin-film transistors and p-type thin-film transistors; and applying laser light to an intermediate substrate during said forming step.

Inventors: FURUTA MAMORU, KAWAMURA TETSUYA, MIYATA YUTAKA, TSUTSU HIROSHI, YOSHIOKA TATSUO, FURUTA, MAMORU, KAWAMURA, TETSUYA, MIYATA, YUTAKA, TSUTSU, HIROSHI, YOSHIOKA, TATSUO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: G11C11
IPC codes: G02F1, G09G3, G11C11