Constant-voltage generating circuit

Abstract: In a constant-voltage generating circuit wherein a first series circuit of PMOS transistors (Q P 1,Q P 2), a second series circuit of a PMOS transistor (Q P 3) and an NMOS transistor (Q N 1) and a third series circuit of PMOS transistors (Q P 4,Q P 5) are connected between a power source line (V CC ) and a ground line (GND), a capacitive element (Q N C) is connected between a common junction node (N1) of the PMOS transistors (Q P 1,Q P 2) of the first series circuit and the ground line (GND). In addition to this capacitive element, another capacitive element (Q P C) may be connected between the node and the power source line. Since the node (N1) is connected to gates of one (Q P 1) of the PMOS transistors of the first series circuit and the PMOS transistor (Q P 3) of the second series circuit, the capacitance at this node with respect to the power source line is large. Thus, when the power supply voltage fluctuates abruptly, the voltage at the first node also changes and thus the output voltage (V REF ) also changes. This phenomenon can be suppressed by the action of the capacitive element connected between the common junction node of the first series circuit and the ground line.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention: The present invention relates to a constant-voltage generating circuit and, more particularly, to a constant-voltage generating circuit which is used such as in an internal voltage dropping circuit (step-down circuit) in a MOS memory circuit. (2) Description of the Related Art; First, an explanation will be given on the circuit and the operation of an internal voltage dropping circuit provided with a prior art constant-voltage generating circuit. Fig. 1 is a circuit diagram of the prior art constant-voltage generating circuit and Fig. 2 is a chart showing voltage dependencies with respect to power supply voltages at internal nodes. In Fig. 1, symbols Q P 1 through Q P 5 each denotes a P-channel MOS field effect transistor (hereinafter simply referred to as a "PMOS"); Q N 1 denotes an N-channel MOS field effect transistor (hereinafter referred to as an "NMOS"); N1, N2 each denotes an internal node; and V REF denotes a constant-voltage output node. It should be noted that the PMOSs Q P 2 and Q P 3 have a higher current capability than that of the PMOS Q P 1 and the NMOS Q N 1. In the following explanation, a power supply voltage is represented by V CC , and an absolute voltage of threshold voltage of a PMOS transistor is represented by V TP . Here, an explanation will be made as to how the potentials at the internal nodes N1, N2 and further at the output node V REF are determined. The NMOS Q N 1 is always in a conductive state (on-state) since the gate potential thereof is at the power supply voltage V CC . Therefore, the potential at the node N2 falls towards a ground potential. Accordingly, the gate potential of the PMOS Q P 2 falls so that the PMOS Q P 2 turns on and, thus, the potential at the node N1 also falls towards the ground potential. As a result, the PMOSs Q P 1 and Q P 3, the gate terminals of which are connected with the node N1, turn on. When all of the PMOSs Q P 1 through Q P 3 and the NMOS Q N 1 become conductive states, the potential at the node N1 becomes closer to the ground potential and that at the node N2 becomes closer to the power supply voltage V CC because of the relations to the current capability of the respective transistors concerned. As a result, the PMOS Q P 2 turns off, and the potential at the node N1 rises up to (V CC - V TP ) again and becomes stable there. On the other hand, since the potential at the node N1 is (V CC - V TP ) and thus the PMOS Q P 3 is in a non-conductive state, that is, "off-state", the potential at the node N2 drops towards the ground potential. When this potential at the node N2 drops to the (V CC - 2 × V TP ) or lower, the PMOS Q p 2 turns on again. Then, the potential at the node N1 falls again so that the PMOS Q P 3 turns on and the potential at the node N2 starts to rise. The potential at the node N2 becomes stable at (V CC - 2 × V TP ) where the PMOS Q P 2 eventually turns on. The potential (V CC - 2 × V TP ) at the node N2 is applied to a gate terminal of the PMOS Q P 4. Then, since the voltage across the gate and source terminals of the PMOS Q P 4 is 2 × V TP regardless of the V CC , the PMOS Q P 4 operates as a constant-current element. On the other hand, the PMOS Q P 5 is always in an conductive state, so that it substantially operates as a resistor (impedance) element. The voltage (hereinafter also referred to as "V REF ") appearing at the constant-voltage output node V REF becomes substantially constant, so that the circuit shown in Fig. 1 operates as a constant-voltage generating circuit as apparent from the graph shown in Fig. 2. In recent years, a transistor used in a memory circuit has a tendency of being scaled down owing to the highly integrated memory circuit, and the size of its design rule has almost reached half micron. This gives rise to the problem of a lowering of reliability in the transistor due to hot carriers. This requires that a power supply voltage be reduced. On the other hand, in order to meet user's desires to continue to use the power supply voltage in the same value as is available now in view of its relationship with other products, it has been proposed to adopt an internal voltage dropping circuit which is about to be put in practical use. Such an internal voltage dropping circuit can be designed with the use of the constant-voltage generating circuit described above. Fig. 3 shows an example of an internal voltage dropping circuit of the kind which is used for the above purpose. In Fig. 3, a reference numeral 1 denotes the constant-voltage generating circuit explained in connection with Fig. 1, symbols Q P 6 through Q P 8 each denotes a PMOS transistor; Q N 2 through Q N 4 each denotes an NMOS transistor; N3 denotes an internal node; and V INT denotes an output node for an internal dropped voltage. The PMOSs Q P 6, Q P 7 and the NMOSs Q N 2 through Q N 4 constitute a current-mirror type amplifier which, using as a reference voltage the constant-voltage V REF generated at and forwarded from the constant-voltage generating circuit 1, serves to produce the same potential as the V REF at the internal dropped voltage output node V INT . More specifically, in such circuit construction, if the potential at the internal dropped voltage output node V INT falls from the constant-voltage V REF , the potential at the node N3 falls by the operation of the amplifier, so that the current supplying capability of the PMOS Q P 8 increases. Thus, the potential at the internal output node V INT rises again and returns to the desired constant-voltage. In contrast thereto, if the potential at the internal output node V INT rises from the desired constant-voltage V REF , the potential at the node N3 rises by the operation of the amplifier, so that the current supplying capability of the PMOS Q P 8 decreases. Thus, the potential at the internal output node V INT falls again and returns to the desired constant-voltage. Accordingly, the constant-voltage with a good response characteristic and sufficient current supplying capability can be provided at the internal dropped voltage output node V INT . The voltage dropping circuit incorporating the conventional constant-voltage generating circuit described above has the following defects. Generally, in operation, a large current flows through the MOS memory circuit for a short period of time, so that the power supply voltage fluctuates at a time unit of several nanoseconds. On the other hand, as mentioned above, the potentials at the nodes N1 and N2 in the constant-voltage generating circuit are (V CC - V TP ) and (V CC - 2 × V TP ), respectively, and thus the PMOSs Q P 1 through Q P 3 are in their conductive states which states are very close to the non-conductive states. In short, the node N1 is in a high impedance state. Therefore, if there occurs a fluctuation in the power supply voltage, the potential at the node N1 transiently shifts to the value which is determined by the ratio between the capacitance of the gates, diffusion layers and wirings connected to the node N1 with respect to the power supply source and the capacitance thereof with respect to the ground GND. As already described above, since the PMOS Q P 3 connected with the node N1 is designed to have a sufficient current supplying capability, the capacitance at the node N1 with respect to the power supply source V CC is larger than the capacitance at the same node N1 with respect to the ground GND. Therefore, when there occurs the above mentioned fluctuation in the power supply voltage, the potential at the node N1 shifts transiently and abruptly towards the power supply voltage V CC . As a consequence, the potential at the constant-voltage output node V REF also shifts towards the power supply voltage abruptly. This is a problem to be solved. IBM Technical Disclosure Bulletin; vol. 32, no. 2, July 1989, pages 26 - 27; "ON-CHIP REFERENCE VOLTAGE REGULATOR" discloses an on-chip reference voltage regulator using a capacitance coupled between a node and the ground line in order to increase the capacitive coupling between said node and the ground thereby decoupling the node from a supply voltage potential. An insensitivity to fast supply voltage variations is consequently achieved. On the other hand JP-A-57 113 602 discloses the possibility for decoupling a node from the supply voltage by connecting this node to the voltage supply line and the ground line by means of respective capacitors, and to give these capacitors a ratio to each other which equals the ratio of the potential between the node and the power source line to the potential between the node and the ground line. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to overcome the problems existing in the conventional circuit and to provide an improved constant-voltage generating circuit. It is another object of the present invention to provide a constant-voltage generating circuit which can generate a highly stabilized constant-voltage regardless of the abrupt fluctuation in the power supply voltage. According to one aspect of the invention, there is provided a constant-voltage generating circuit according to claim 1. The dependent claims are related to further advantageous aspects of the invention. The constant-voltage generating circuit further comprises an capacitive element connected between the first node and the power source line for increasing a capacitance therebetween. The above capacitive element(s) serves to make the ratio of (the total capacitance between the first node and the power source line) to (the total capacitance between the same first node and the ground line) substantially equal to the ratio of (the power supply voltage - the absolute value of the threshold voltage of the P-channel MOS transistor) to (the absolute value of the threshold voltage of the P-channel MOS transistor). BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional constant-voltage generating circuit; Fig. 2 is a graph showing the operation of the circuit shown in Fig. 1; Fig. 3 is a circuit diagram showing an application of the circuit of Fig. 1 to an internal voltage dropping circuit; Fig. 4 is a circuit diagram showing a constant-voltage generating circuit embodying a part of the invention; and Fig. 5 is a circuit diagram showing an embodiment of a constant-voltage generating circuit according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, referring to the accompanying drawings, an explanation will be given on the embodiment according to the present invention. Fig. 4 shows an arrangement of a constant-voltage generating circuit of a first embodiment showing a part of the invention. In Fig. 4, like reference numerals refer to like parts in Fig. 1 showing the conventional circuit. The arrangement of this circuit is the same as that of the conventional circuit shown in Fig. 1 only except that there is provided an NMOS Q N C transistor with a gate connected to the node N1, and a source and a drain both connected to the ground GND. In this circuit, since the NMOS Q N C connected between the node N1 and the ground GND is added as a capacitive element to the arrangement of the conventional circuit, the operation of this circuit in a normal state is the same as that of the conventional circuit. In this circuit, the gate size (the gate width and/or the gate length) of the NMOS Q N C is set for a sufficiently large value, so that a large capacitance with respect to the ground GND is added to the node N1. It should be noted that the amount of potential fluctuation appearing at the node N1 when the potential of the power supply voltage changes abruptly is decided by the ratio between the capacitance at the node N1 with respect to the power supply source and that at the same node N1 with respect to the ground GND. In this circuit, the capacitance with respect to the ground GND is increased by the provision of the NMOS Q N C, so that the potential fluctuation appearing at the node N1 caused by a possible change in the power source voltage is alleviated. If the gate size, that is, a gate width and/or a gate length, of the NMOS Q N C is so adjusted that the ratio of (the capacitance at the node N1 with respect to the power supply source) : (that at the node N1 with respect to the ground GND) becomes the ratio of (V CC - V TP ) : V TP , a constant-voltage required can be generated more quickly. Fig. 5 shows an arrangement of a constant-voltage generating circuit of an embodiment according to the invention. The arrangement of this embodiment is the same as that of the circuit explained with respect to Fig. 4 only except that a PMOS transistor Q P C which functions as another capacitive element and whose gate is connected with the node N1, and whose source and drain are connected with the power supply source V CC is added to the circuit shown in Fig. 4. In this embodiment, since two transistors Q P C and Q N C each serving as a capacitive element are provided, one being connected between the node N1 and the power supply source V CC and the other being connected between the node N1 and the ground GND, the values of these capacitances can be set at any desired values with the ratio between the capacitance at the node N1 with respect to the power supply source and that with respect to the ground GND being maintained constant. In the above embodiment, although a MOS transistor(s) is used as a capacitive element to be added to the node N1, the present invention should not be limited to it. The capacitor in other forms (e.g., junction capacitor) can be adopted. Further, the NMOS Q N 1 serving as a current source may be replaced by a PMOS transistor, and the PMOS Q P 5 serving as an impedance element may be replaced by an NMOS transistor. As has been described hereinabove, in accordance with the present invention, the node having a large capacitance with respect to a power supply source is supplied with a capacitance with respect to the ground, so that the transient voltage fluctuation appearing at the above node caused by the change in the power supply voltage can be effectively suppressed. Therefore, where the constant-voltage generating circuit according to the present invention is used for a voltage dropping circuit for a MOS memory circuit, a highly stabilized constant-voltage can be generated regardless of a possible abrupt change in the power supply voltage caused by a memory activated operation. While the invention has been described in its preferred embodiment, it is to be understood that the words which have been used are words of description rather than limitation and that changes within the purview of the appended claims may be made without departing from the scope of the invention in its broader aspects.

Claims: A constant-voltage generating circuit comprising a first P-channel MOS transistor (Q P 1) having its source connected to a power source line (V CC ), and its gate and drain both connected to a first node (N1); a second P-channel MOS transistor (Q P 2) having its source connected to said first node, its gate connected to a second node (N2), and its drain connected to a ground line (GND); a third P-channel MOS transistor (Q P 3) having its source connected to said power source line, its gate connected to said first node, and its drain connected to said second node; a fourth P-channel MOS transistor (Q P 4) having its source connected to said power source line, its gate connected to said second node, and its drain connected to an output terminal (V REF ); a current source element (Q N 1) connected between said second node and said ground line; and an impedance element (Q P 5) connected between said output node and said ground line, said constant-voltage generating circuit being characterized by an N-channel MOS transistor (Q N C) functioning as a capacitive element and having its gate connected to said first node, and its source and its drain both connected to the ground line; and a fifth P-channel MOS transistor (Q P C) also functioning as a capacitive element and having its gate connected to said first node, and its source and its drain both connected to said power source line, wherein the capacitance of said N-channel MOS transistor (Q N C) and said fifth P-channel MOS transistor (Q P C) is set so that the ratio of the total capacitance between the first node (N1) and the power source line to the total capacitance between the first node (N1) and the ground line equals the ratio of the difference between the power source voltage (V CC ) and the absolute value of the threshold voltage (V TP ) of said first P-channel MOS transistor (Q P 1) to the absolute value of the threshold voltage (V TP ) of said second P-channel MOS transistor (Q P 2) as expressed by the following equation C N1 →Supply line C N1 →Ground line = V CC - V TP V TP wherein C N1 -> Supply line indicates the total capacitance between the first node (N1) and the power source line and C N1 -> Ground line indicates the total capacitance between the first node (N1) and the ground line. A constant-voltage generating circuit according to claim 1, in which said current source element is an N-channel MOS transistor (Q N 1) having its gate connected to said power source line, its drain connected to said second node, and its source connected to said ground line. A constant-voltage generating circuit according to claim 1, in which said impedance element is a P-channel MOS transistor (Q P 5) having its source connected to said output terminal, and its gate and its drain both connected to said ground line.

Inventors: AIZAKI SHINGO, AIZAKI, SHINGO, Aizaki, Shingo, c/o Nec Ic Microcomputer Sys. Ltd.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: G05F1
IPC codes: G05F3, H01L21, G11C11, G05F1, H01L27