Semiconductor planarization process

Abstract: A method for planarizing an integrated circuit structure having a glass layer (15) overlying an oxide layer (13) 0f an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass (15) structure that overlie portions of the oxide layer (13) that have higher elevations than other portions of the oxide layer (13), and then etching the glass layer (15) overall. The etching step includes forming a layer of photoresist (17) over the glass layer (15), exposing selected areas (20) of the photoresist (17) over the portions of the oxide layer (13) that have higher elevations than other portions of the oxide layer (13), removing the exposed areas of the photoresist (17), and etching the glass layer (15) within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer (11) over which the oxide (13) and glass layers (15) have been formed. Additionally, an integrated circuit structure is presented that includes a substrate (10) in which integrated circuit elements are constructed, a first interconnection metalization (11) over the substrate (10) interconnecting selected ones of the integrated circuit elements, and an oxide layer (13) over the substrate (10) and the first metal interconnection pattern (11). A glass layer (15) over the oxide layer (13) is substantially planar between portions that overlie the metalization (11) and portions that do not over lie the metalization (11).

Description: This invention relates to improvements in semiconductor fabrication processes, and more particularly to improvements in semiconductor planarization processes, and to semiconductor products utilizing the improved planarization process of the invention. In the fabrication of integrated circuits in many instances it is desired to provide a planarized surface, that is, a top surface for the integrated circuit that has relatively even or smooth topography. US 4662064 relates to a method of forming multi-level metallization. A thick layer of planarizing material is applied over a first level of metallization. A photoresist is formed in the depressions on the surface of the planarizing material. The surface of the planarizing material is planarized by an isotropic etch-back, to at least the depth of the planarizing layers's greatest depression. The photoresist is removed. The structure is isotropically etched to expose the first level metallization layer. A layer of oxide is applied to the surface of the resultant structure and a second layer of metallization is applied over the oxide layer. EP 0312154 relates to a method of forming an interconnection between conductive levels. A passivating material is provided to cover a first conductive level. The passivating material is removed from a contact area on the first conductive level. Spin-on glass is provided over the structure and etched back to expose the contact area. A second conductive level is provided on the structure to make contact with the contact area on the first conductive level. EP-A-0441653 relates to a method of forming a planar surface. An insulating layer is applied over underlying conductive regions, and the resulting structure is planarized by the application of a planarizing material. An overall etch is performed. In one embodiment only the planarizing material is etched, in a second embodiment both the planarizing material and insulating material are etched. The document teaches that the planarizing material should be chosen to etch at the same rate as the insulating material. In the light of the above, it is, therefore, an object of the invention to provide an improved process for planarizing the surface of an integrated circuit on which spin-on glass or the like as been applied. It is another object of the invention to provide a method of the type described in which the etch rate of spin-on glass is not as critical a process parameter as heretofore. It is another object of the invention to provide a method of the type described which can be used to enhance the yield and reliability for integrated circuits having multilevel metallization. It is another object of the invention to provide a method of the type described which does not require complete design of additional masks and does not unduly complicate the integrated circuit process flow. These and other objects, features, and advantages will become apparent to those skilled in the art from the following detailed description when read in conjunction with the accompanying drawing and appended claims. According to claim 1 of the present invention there is provided a method for planarizing an integrated circuit structure having a spin-on glass layer overlying an oxide layer of an integrated circuit, comprising the steps of: selectively etching portions of said spin-on glass layer that overlie portions of said oxide layer that have higher elevations than other portions of said oxide layer; and then etching overall to etch the spin-on glass layer and exposed portions of said oxide layer underlying regions in which said selective etching of the spin-on glass layer occurred. In accordance with one aspect of the invention, a method for planarizing an integrated circuit structure having a spin-on glass layer overlying an oxide layer of an integrated circuit is presented. The method includes the steps of selectively etching portions of the spin-on glass structure that overlie portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the spin-on glass layer overall. The etching step includes forming a layer of photoresist over the spin-on glass layer, exposing selected areas of the photoresist over the portions of the oxide layer that have higher elevations than other portions of the oxide layer, removing the exposed areas of the photoresist, and etching the spin-on glass layer within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer over which the oxide and spin-on glass layers have been formed. The invention is illustrated in the accompanying drawings in which: Figures 1a-1f illustrate side elevation cross-sectional views of a portion of an integrated circuit in various stages of fabrication, in accordance with a preferred embodiment of the method of the invention. Structures in the various figures of the drawing are not drawn to scale, and the sizes and the dimensions of the various parts illustrated have been exaggerated for clarity of illustration and ease of description. Additionally, in the various figures of the drawing, like reference numerals are used to denote like or similar parts. It should be noted that the process steps and structures herein described do not necessarily form a complete process flow for manufacturing integrated circuits. It is anticipated that the present invention may be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. A preferred embodiment of the invention is described hereinbelow beginning with a partially completed integrated circuit structure, as shown in Figure 1a. The structure is formed on a substrate 10 (which may itself comprises layers of structure stacked one upon the other, such structures being referred to generally as a substrate), and includes metal lines 11 which may be, for example, aluminium or the like, that serve to interconnect various parts of the integrated circuit components (not shown) that have been previously formed on the stack of underlying structure or substrate 10. A layer of oxide 13 is formed over the surfaces of the metal lines 11 and the surface of the substrate 10 between the metal lines 11. The oxide 13 may be formed, for example, in accordance with various techniques presently known in the art, preferably by plasma-enhanced techniques. The oxide layer 13 is conformal with the hills and valleys over which it is formed; consequently, the oxide layer 13 forms mountain regions overlying the metal lines 11 over which it is formed with respect to the valley regions between the metal lines 11. A layer of spin-on glass 15 is then formed overall. In accordance with the method of the invention, with reference now to Figure 1b, a layer 17 of photoresist is formed and patterned over the layer of spin-on glass 15. A mask, not shown, which may be a reverse or negative mask of the mask used in the formation of the metal lines 11 is used to expose regions 20 of the photoresist layer 17 that overlie the metal lines 11 on the substrate 10. Alternatively, a negative photoresist layer may be used in place of the layer 17 described above, and exposed through the metal mask used in the formation of the metal lines 11, followed by removal of the portions within the regions 20 overlying the metal lines 11 to form the patterned photoresist layer, as shown. Next, the regions of the spin-on glass 15 and oxide 13 underlying the windows of the photoresist layer 17 are partially etched, as shown in Figure 1c. Figure 1c, schematically illustrates two alternative preferred etch depths, one terminating within the spin-on glass 15 (upper line at the bottom of opening 20) and the other extending through the spin-on glass and terminating within the oxide 13 (lower line at the bottom of opening 20). The exact depth of the etch will be experimentally determined to achieve a planar final result, described below, and may be, for example, to a depth of between 10% and 90%, preferably between 33% and 66%, of the total depth of the layer 15 and oxide 13 overlying the metal lines 11. The etch process may be any commercially known etch, preferably the dry etch to accomplish the etched structure shown. As shown next in Figure 1d, the layer 17 of photoresist is removed, such as by an ashing process or the like. Finally, as shown in Figure le, the overall structure is exposed to a final planarization etch, which may be, for example, a dry etch, to reduce the thickness of the spin-on glass layer 15 in the regions 25 in the "valleys topography between the metal lines 11. Since the regions overlying the metal lines 11 may have portions of the oxide layer 13 exposed, the etch of the spin-on glass layer 15 in the areas of valley topography will proceed relatively rapidly, but not uncontrollably rapidly. A final integrated circuit structure having a relatively planar surface as shown in Figure 1e can therefore be accomplished. The integrated circuit structure shown in Figure 1e can then be further processed in accordance with known integrated circuit technology for example, by the formation of additional metallization 30 (Figure 1f) planarization, passivation layers and the like.

Claims: A method of planarizing an integrated circuit structure having a spin-on glass layer (15) overlying an oxide layer (13) of an integrated circuit, comprising the steps of: selectively etching portions of said spin-on glass layer (15) that overlie portions of said oxide layer (13) that have higher elevations than other portions of said oxide layer (13); and then etching overall to etch the spin-on glass layer (15) and exposed portions of said oxide layer (13) underlying regions in which said selective etching of the spin-on glass layer (15) occurred. The method of claim 1, wherein said oxide layer (13) has been deposited by plasma-enhanced oxide deposition techniques. The method of any preceding claim further comprising providing metal layers (11) under said oxide. The method of claim 1 or 2, wherein said step of selectively etching portions of said spin-on glass layer (15) comprises forming a layer of photoresist (17) over said spin-on glass layer (15), exposing selected areas of said photoresist (20) over said portions of said oxide layer (13) that have higher elevations than other portions of said oxide layer (13), removing said exposed areas (20) of said photoresist (17), and etching said spin-on glass layer (15) within said removed areas (20) of said photoresist (17). The method of claim 3, wherein said step of selectively etching portions of said spin-on glass layer (15) comprises forming a layer of photoresist (17) over said spin-on glass layer (15), exposing selected areas (20) of said photoresist that overlie said metal layers (11), removing said exposed areas (20) of said photoresist, and etching said spin-on glass layer (15) within said removed areas of said photoresist (17). The method of claim 5, wherein said step of exposing selected areas of said photoresist (17) that overlie said metal layers (11) comprises providing a mask that is a negative of a mask used to form said metal layers (11), aligning the mask over the oxide (13) that overlies said metal layers (11), and exposing said layer of photoresist (17) through said mask. The method of claim 5, wherein said step of forming a layer of photoresist (17) over said spin-on glass layer (15) comprises forming a layer of positive resist over said spin-on glass layer (15), and wherein said step of exposing selected areas of said photoresist (17) that overlie said metal layers (11) comprises utilizing a mask that was used to form said metal layers (11), aligning the mask with the oxide (13) that overlies said metal layers (11), and exposing said layer of photoresist (17) through said mask. A method of manufacturing an integrated circuit, comprising: providing a substrate (10); forming a first metal interconnection pattern (11) over said substrate for interconnecting selected components of said integrated circuit; forming an oxide layer (13) over said substrate and said first metal interconnection pattern (11); forming a layer of spin-on glass material (15) over said oxide layer to form a spin-on glass layer (15); and planarizing the resultant integrated circuit structure according to the method of claim 1. The method of claim 8, wherein said step of forming an oxide layer (13) over said substrate (10) and said first metal interconnection pattern (11) comprises forming CVD oxide over said substrate (10) and said first metal interconnection pattern (11). The method of claim 8 or 9, wherein said step of selectively etching portions of said spin-on glass layer (15) comprises forming a layer of photoresist (17) over said spin-on glass layer (15), exposing selected areas of said photoresist over said first metal interconnection pattern (11) removing said exposed areas of said photoresist (17), and etching said spin-on glass layer (15) within said removed areas of said photoresist. The method of claim 10, wherein said step of forming a layer of photoresist (17) comprises forming a layer of positive photoresist (17), and wherein said step of exposing selected areas of said photoresist (17) over said first metal interconnection pattern (11) comprises providing a mask that is a negative of a mask to form said metal interconnection pattern (11), and exposing said layer of photoresist (17) through said mask. The method of claim 10, wherein said step of forming a layer of photoresist (17) comprises forming a layer of negative photoresist (17), and wherein said step of exposing selected areas of said photoresist (17) over said first metal interconnection pattern (11) comprises providing a mask used to form said metal interconnection pattern (11), and exposing said layer of photoresist (17) through said mask. The method of any preceding claim wherein said step of selectively etching comprises etching portions of said spin-on glass layer (15), and portions of said oxide layer (13) that have higher elevations than other portions of said oxide layer (13), and which underlie said spin-on glass layer (15). The method of any preceding claim, wherein said step of selectively etching said spin-on glass layer (15) comprises etching between 10 and 90 percent of the thickness of said spin-on glass layer (15) and oxide layer (13). The method of any preceding claim, wherein said step of selectively etching said spin-on glass layer (15) comprises etching between 33 and 66 percent of the thickness of said spin-on glass layer. The method of any preceding claim, wherein said selective etch is a dry etch. The method of any preceding claim, further comprising forming a passivating layer (30) over the spin-on glass layer, after said etch overall. The method of any preceding claim, further comprising forming a second level of metal over the spin-on glass layer (15).

Inventors: HUANG KUEI-WU, HUANG, KUEI-WU
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS, INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21