CIRCUIT FOR SLICING DATA

Abstract: A circuit for slicing data, in which caption data, etc., included in a television signal are sliced at optimum voltages. A clock-run signal is sliced at provisional reference voltages by a comparator (1). The product of the clock-run signal and a clock signal whose frequency is about sixteen times as high as that of the clock-run signal is stored in a shift register (6) as sixteen bit information. Only the central eight bits of the sixteen bit information are taken in a duty check block (8), and thereby, whether the provisional slice levels are suitable or not is judged. According to the result, the value of a counter (9) is increased or decreased, and new reference voltages are determined through a pulse width conversion circuit (11) and an integrating circuit (12). The data which is sliced at the new reference voltages, is also checked similarly, and slicing data with the optimum levels is performed.

Description: TECHNICAL FIELD The present invention relates to a data slice circuit having a function for slicing data signals such as caption data at an optimum voltage. BACKGROUND ART In recent years, a necessity for adding a tele-caption function to a television set has arisen from the consideration for auditorily handicapped persons. Accordingly, a necessity for installing a one-chip microcomputer containing a caption decoder has been increasing. In the following, an explanation is given on a data slice circuit of the prior art. FIG.5 shows a data slice circuit of the prior art, wherein numeral 1 is a comparator having a caption data input and a reference voltage input, and numeral 2 is a block of the caption decoder accepting the output of numeral 1 as its input. On a slice level correction circuit constituted as has been described above, its action is explained below. First, the reference voltage of the comparator 1 is set to a constant value. The caption data inputted into the comparator are sliced taking this reference voltage as its reference and then inputted into the caption decoder 2. By looking up the result of the caption decoder, when the slice level is anomalous and hence the caption data cannot be taken in correctly, once again the caption data are taken in with changing the reference voltage of the comparator 1. In the above constitution, however, whether the caption data are correctly sliced and inputted into the caption decoder or not must be judged by the result obtained through the caption decoder by seeing the character data appearing on e.g. a television screen. And the slice level must be corrected in accordance with this result. In order to achieve this, due to the diversity of constitution of various tele-caption systems, there has been a problem that the check and correction on slice levels of respective system were required. As a data slice circuit having a function by which the slice level of caption data is corrected, there is a circuit that was disclosed on the Gazette of Japanese Unexamined Patent publication Sho 61-43886 (Inventor: Teiji OKAMOTO). This circuit is a circuit wherein a signal including predetermined n-pulse trains (clock-run signal) is converted into digital data by a comparator which compares them with a reference voltage; it comprises a pulse width detection means for detecting the pulse width of the above-mentioned n-pulse train, an averaging means for averaging the output of the above-mentioned pulse width detection means and a digital-to-analog conversion means for converting the output of the above-mentioned averaging means into an analog voltage, and thereby the output voltage of the above-mentioned digital-to-analog conversion means is taken as the reference voltage of the above-mentioned comparator. There has been a problem that the above-mentioned circuit was not suited to the circuit integration because the circuit became large since it necessitated an averaging means, a memory means, and a digital-to-analog conversion means. The present invention is for solving the above-mentioned problems having been existing and purposes to offer a data slice circuit having a constitution that is suitable for circuit integration, which has functions for checking the slice level of data signal and for issuing the signal for correcting the level thereof. DISCLOSURE OF THE INVENTION A data slice circuit of the present invention for slicing a data signal containing a clock-run signal comprises: comparison means for issuing a result of comparison of the clock-run signal of said data signal with a first reference voltage during an arbitrary one period only of said clock-run signal; product means for producing a product of a signal derived from the output of said comparison means and a clock signal having a frequency of at least two times a frequency of said data signal; bit storage means for storing the output of said comparison means as a bit train, the storage being controlled by the output of said product means; and reference voltage variation means for varying said first reference voltage and for providing said first reference voltage to said comparison means during said arbitrary one period only and for providing a varied reference voltage after said arbitrary one period, said reference voltage variation means being responsive to values of said bit storage means based on a predetermined rule. Claims 2 to 6 refer to preferred embodiments of such a data slice circuit. BRIEF DESCRIPTION OF DRAWINGS FIG.1 and FIG.2 are block diagrams of data slice circuits in the present invention. FIG.3 is a chart showing signal waveforms of different parts of the data slice circuits shown in FIG.1 and FIG.2. FIG.4 is a table showing mutual correlation between various values of clock-run signal taken into the shift registers responding to the slice levels and the counter action activated by the result of a duty-factor check. FIG.5 is a block diagram showing a data slice circuit of the prior art. BEST MODE FOR CARRYING OUT THE INVENTION In the following, an explanation is given on preferable modes of the present invention, referring to the drawings. In FIG.1: numeral 1 is a comparator into which a reference voltage and caption data are inputted; numeral 2 is a caption decoder having the sliced data of the comparator 1 as its input, "a" is a line-enable signal which allows the arbitrary horizontal synchronous signal period (hereinafter, called "line") including caption data issued from the caption decoder 2; numeral 3 is an AND circuit having the output of the comparator 1 and the line enable signal "a" as its input; numeral 4 is an RS flip-flop circuit which is set by the output of the AND circuit 3 and is initially-reset by the horizontal synchronous signal; numeral 5 is an AND circuit having the output of the RS flip-flop circuit 4 and a signal of 8 MHz which becomes a fundamental clock of an on-screen display as its input; numeral 6 is a shift register which is shifted by the output of the AND circuit 5 and takes in the output of the comparator 1 during the period of the line enable signal "a"; numeral 7 is a counter which counts the output of the AND circuit 5 during the period of the line enable signal "a", "b" is an overflow signal of the counter 7; and numeral 8 is a block which checks the duty-factor of the clock-run signal taken in the shift register 6 at the timing of the overflow signal "b". Mark "c" is a signal issued from the caption decoder 2 in synchronism with the vertical synchronization signal; numeral 9 is a counter which determines either one action from up, down, or no-action in accordance with the result from the block 8 that is for checking the duty-factor of the clock-run signal and works and acts taking the signal "c" as its clock; numeral 10 is a register for setting the initial data of the counter 9, and numeral 11 is a digital-to-analog (D/A) converter which inputs the result of the counter 9 as its data and outputs the result as a reference voltage of the comparator 1. In FIG.3, principal signals and output waveforms of constitutional elements are shown. On the check function and the correction function of the slice level in the data slice circuit which was constructed as has been described above, its action is explained below. First, an explanation is given on the check function of the slice level. Signal including the clock-run signal and caption data is sliced at a certain reference voltage in the comparator 1 and inputted into the caption decoder 2. This initial reference voltage is the one that was D/A-converted from the initial data of the counter 9 determined by the value of the register 10. As the initial value of the register 10, a value corresponding to an expected optimum reference voltage has been stored. Hereupon, as other determination method for the initial value of the counter 9, first the value of the counter 9 is set to be a sufficiently large value, and then the slicing action is tried with the value determined above. The result should become that, because of an excessive value of the reference voltage, bit information entering into the counter 9 is all "0". Next, after decreasing the value of the counter 9, the same action is tried. This process is repeated until "1" appears on the bit information of the shift register 6. The process can proceed to the checking by the duty-factor check block 8, taking as its initial value the value of the counter 9 at the time when "1" firstly appears. This action may be performed by a microcomputer program or it may be done by hardware. In the caption decoder 2, by finding arbitrary lines including caption data, the line enable signal "a" is issued. The enable signal "a" and the output of the comparator 1 are being inputted into a set terminal of the RS flip-flop circuit through the AND circuit 3. Accordingly, after inputting the horizontal synchronization signal, when the clock-run signal enters as the output of the comparator 1, the RS flip-flop circuit is set; and the AND circuit 5 starts supplying the 8-MHz clock to the shift register 6 and the counter 7. And, at this time, since the shift register 6 is also in the action enable state by the line enable signal "a" of the caption decoder 2, it becomes possible to take the sliced clock-run signal that is the output of the comparator 1 into the shift register 6, taking the output of the AND circuit 5 as its clock. The counter 7, which works with the output of the AND circuit 5 as its clock, generates the overflow signal "b" after a definite time elapsed, thereby resetting the RS flip-flop circuit 4. Consequently, at the time of generation of the overflow signal "b", the counter 7 and the shift register 6 stop their action. At the same time, data of the shift register 6 under this situation are taken into the duty-factor check block 8 by the overflow signal "b". In the present working example, a sampling is executed on the initial one period of the clock-run signal. The frequency of the clock-run signal is approximately 500 kHz; and in the case that this is sampled at a clock of 8 MHz, the counter 7 issues the overflow signal at the time when the counted number becomes 16. And, during a period of one period length of the clock-run signal, information of 16 bits is obtained and stored in the shift register 6. For the sampling clock given to the AND circuit 5, a frequency of at least two times high as the frequency of the signal which is the object of the slicing action is required, and favorably, it should be eight times or more. This duty-factor check block 8 has a function of converting the bit information stored in the shift register 6 into 2-bit information in accordance with a predetermined rule. In this case, it is also possible to check the duty-factor using all the bits (in the above example, 16 bits) which were sampled during one period of the clock-run signal. In actual cases, however, in one period of the clock-run signal, in such time-intervals near its both ends, even the duty-factor deviates considerably from 50 %, it is fixed actually to "1" or "0"; and hence its importance as the sampling action is low. Then it is more favorable to execute the sampling only for those time intervals that are limited to regions which are equi-distance before and after from the center of one period. For example, it can be said to be a more favorable mode of embodiment that, employing a clock of 8 MHz, the sampling is executed only for 8 pulses in total, that is, only for as many as respectively 4 pulses which are before and after from the center of one period time interval of the clock-run signal. In such a mode of embodiment, the data slice circuit has such features in its constitution as is described below. That is, it has a constitution that, among those 16 bit information stored in the shift register 6, only those 8 bit information excluding each 4 bits at both ends (8 bits in total) are sent to the duty-factor check block. This means that, among those series -connected shift registers, only the output of those 8 bits around the center are connected to the duty-factor check block 8. FIG.4 is a table showing how the sampled information collected in the above-mentioned favorable mode of embodiment and the values of the up-down counter 9 are controlled responding to the above-mentioned extracted information. In case that no less than six bits of the sampled bit train of 8 bit configuration are "1", a signal "10" by which the value of the up-down counter is up-counted is issued. Conversely, in case that "1" of the sampled bit train is no more than two bits, a signal "01" by which the value of the up-down counter is down-counted is issued. In case that "1" of the sampled bit train is no less than 3 bits and no more than 5 bits, the duty-factor is considered to be approximately 50 %, then an output signal "11" is issued, and the value of the up-down counter is kept as it was. And, in case that the sampled bit train is all "0", the output signal "00" is issued since there is a fear that any anomaly arises in the sampling; and in this case also, the value of the up-down counter is kept as it was. Namely, in case that the duty-factor of the result of the slice of the clock-run signal is not 50 %, but is less than a predetermined lower limit value, the duty-factor check block 8 issues a signal for executing the down count to the counter 9. Then, the counter 9 receives the signal "c" during a time interval before the next caption data enter thereinto, the down count action is executed only one time, and thereby the value is decreased. As a result, a renewed reference voltage, which is outputted through the D/A converter 11 and is corrected slightly downward in comparison with the initial tentative reference voltage, is given to the comparator 1. And, conversely, in case that the duty-factor of the result of the slicing action of the clock-run signal exceeds a predetermined upper limit value, a signal for executing the up-count is issued to the counter 9. Thereby the value of the counter 9 increases. The result thereof is issued through the D/A converter 11, and then a renewed reference voltage, which is corrected slightly upward in comparison with the initial tentative reference voltage, is given to the comparator 1. In case that the duty-factor is between the above-mentioned lower limit value and upper limit value, or when there is no duty-factor present, that is, when the clock-run signal could not be taken in, the counter 9 does not act (value does not change). FIG.2 is a block diagram showing the constitution of a data slice circuit in accordance with another favorable mode of embodiment of the present invention. In comparison with the mode of embodiment shown in FIG.1, the means through which a digital signal is converted into an analog signal is different. In the mode of the embodiment in FIG.1, although the digital signal was converted into an analog signal by a D/A converter, in working example of FIG.2, the digital signal is converted into an analog signal by a pulse width conversion circuit 12 and an integration circuit 13. The pulse width conversion circuit 12 receives the value of the counter 9, then converts it into a pulse width with a clock of, for example, 2 MHz. If the clock of 2 MHz is used in common with the system clock of the microcomputer, it becomes a constitution suitable for realizing a one chip microcomputer including a data slice circuit and a data decoder. The integration circuit 13 is a means which receives the output of the pulse width conversion circuit 12 and converts it into an analog value, it can be realized with the use of a low-pass filter (LPF). By use of such a constitution described above for the conversion means, any D/A converter, whose circuit size normally is large, is not required, hence it is suited to bring the circuit into an integrated circuit, and hence it becomes possible to realize a microcomputer including a data slice circuit provided with functions of check and correction of the slice level in a single chip. In the mode of embodiment shown in FIG.2 also, its action is the same as the one explained in the working example of FIG.1. It is not necessarily required to execute the sampling of the slice data in the first one period, but it is also possible to do it in any one period after the first period. As has been described above, according to the present invention, it becomes possible to realize a data slice circuit, by which the duty-factor of e.g. the clock-run signal is checked and as a result thereof the slice level can be corrected automatically. INDUSTRIAL APPLICABILITY As has been described, by the data slice circuit in accordance with the present invention, an optimum slice level in the slice operation of the data signal in e.g. data caption included in the television signal can be obtained, and in addition to the above, since it can be constituted with a compact circuit, a circuit integration of the circuit including also the data decoder becomes easy. Table of Reference Numbers of the Drawing 1 comparator 2 caption decoder 3, 5 AND circuits 4 RS flip-flop circuit 6 shift register 7, 9 counters 8 duty-factor check block 10 digital-t-analog register 11 converter 12 pulse conversion circuit 13 integration circuit

Claims: A data slice circuit for slicing a data signal containing a clock-run signal, comprising: comparison means (1) for issuing a result of comparison of the clock-run signal of said data signal with a first reference voltage during an arbitrary one period only of said clock-run signal; product means (5) for producing a product of a signal derived from the output of said comparison means and a clock signal having a frequency of at least two times a frequency of said data signal; bit storage means (6) for storing the output of said comparison means (1) as a bit train, the storage being controlled by the output of said product means (5); and reference voltage variation means (9) for varying said first reference voltage and for providing said first reference voltage to said comparison means (1) during said arbitrary one period only and for providing a varied reference voltage after said arbitrary one period, said reference voltage variation means (9) being responsive to values of said bit storage means (6) based on a predetermined rule. A data slice circuit according to claim 1, wherein said reference voltage variation means (9) provides said varied reference voltage to said comparison means (1) on the basis of a predetermined rule by using only bits of said bit storage means output which are included in effectively the same time period before and after the center of said stored bit train. A data slice circuit according to claim 1 or 2, wherein reference voltage generating means (11) for generating said first and said varied reference voltage are provided; said data signal has a first frequency; said product means (5) samples the output of said comparison means (1) with the clock signal having a second frequency of at least two times said first frequency, during the arbitrary one period only of the clock-run signal of said data signal; said reference voltage variation means (9) increases said first reference voltage in a first case in which an amount, by which said clock-run signal of said data signal during said arbitrary one period is higher than said reference voltage, is more than a predetermined upper limit value, and for decreasing said first reference voltage in a second case in which an amount, by which said clock-run signal of said data signal during said arbitrary one period is lower than said reference voltage, is less than a predetermined lower limit value. A data slice circuit according to claim 3, wherein said second frequency is greater than " n " times said first frequency, "n" being equal to or greater than two; sampling start means (4) are provided for starting said product means (5) when said output of said comparison means (1) changes; duty-factor check means (8) are provided for detecting a duty factor of said clock-run signal of said data signal on the basis of the series of binary data stored in the bit storage means (6), said reference voltage variation means (9) is a counter for counting up or down on the basis of an output of said duty-factor check means (8). A data slice circuit according to any one of claims 1 to 4, wherein said product means (5) samples a signal derived from said output of said comparison means (1) at a frequency of at least eight times a frequency of said data signal. A data slice circuit according to any one of claims 2 to 5, wherein said first reference voltage is not changed when all data of said bit train are data representing that said data signal is lower than said reference voltage.

Inventors: NAKAIMUKI MASAYUKI, TAKAHASHI SHINICHI, YAGI YUKIHIRO, NAKAIMUKI, MASAYUKI, TAKAHASHI, SHINICHI, YAGI, YUKIHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: H04N7
IPC codes: H04L25, H04N7