Process for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process

Abstract: The process comprises the steps of: depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity.

Description: This invention relates, in a first aspect thereof, to a process of measuring the degree of planarity of a dielectric layer in an integrated circuit, and in a second aspect, to an integrated circuit including means for performing the process. In the manufacture of integrated circuits, a variously shaped intermediate layer of polycrystalline silicon is first deposited onto a semiconductor substrate and then covered with a dielectric layer, both depositions being carried out using conventional photolithographic techniques. Due to the intermediate layer being discontinuous, the dielectric layer overlay usually exhibits a surface which is not perfectly than truly planar. In view of the trend toward ever smaller minimum dimensions for the device structures formed by the photolithographic process, the planarity of the dielectric layers has attained outstanding importance vis-a-vis the lithographic definition of the structures to be subsequently formed. Owing to the extremely small magnitude of the geometric quantities involved, the technique which is more generally employed to measure the degree of planarity is based on observation under the electron scan microscope of a section of the surface; thus, it becomes necessary to have the integrated circuit cut and destroyed. Consequently, this known technique can only be applied on a sampling basis and provides, in practice, a way of monitoring only the average quality of a production. The article of R. F. Leinen II in Solid State Technology, vol. 21 no. 5, May 1978, pages 77-81, different technologies are disclosed for measuring the degree of planarity of a substrate. First, a laser interferometer technology is disclosed, in which the distance between a reference surface and the surface of the substrate is related to the number of interference bands of a laser beam. Then, an electrical capacitance technology is disclosed, in which flatness is determined by comparing an internal capacitance to the capacitance established between the tip of an electrical probe and the nearby substrate surface. Also, an air gauging technology is disclosed, in which flatness is determined by measuring the volume of pressurized gas (nitrogen) allowed to escape between a precision nozzle and the nearby surface of the substrate. As possible future developments, electron beam technology is mentioned. GB-A-2083229 discloses a flatness measuring apparatus making use of a number of detecting probes, each of them being of the types mentioned above. The problem addressed by this invention is that of providing a non-destructive process whereby the degree of planarity of a dielectric layer in an integrated circuit can be measured. Accordingly, this invention provides, in a first aspect thereof, a process of measuring the degree of planarity of a dielectric layer in an integrated circuit, being characterized in that it comprises the steps of: depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film; depositing a reference path identical with the measure path over a perfectly planar surface; and measuring the electric resistance through said measurement path against the electric resistance of the reference path. The resistance of the measure path is minimal where the deposition surface is perfectly planar, and increases as the surface deviates from perfect planarity. This is thought to be due to the length of the conductive film path being longer, the more irregular is the surface shadowed by the path; then, as is well known, the resistance opposed by a material to an electric current flowing through it will be, for given resistivity and cross-sectional area, directly proportional to the length of the material. The measure path resistance is measured against the resistance of a reference path identical with the measure path but deposited across a perfectly planar surface, so that the resistance value is not affected by errors; moreover, a comparative process is definitely more convenient. In order for the resistance differences to be assessed with the utmost accuracy, it is preferable to have the comparison carried out on a Wheatstone bridge arrangement made up of the measure path and three identical reference paths. This arrangement is well known by the very high accuracy with which it can measure electric resistance. Also for the purpose of maximizing the measure accuracy, the measure and reference paths are formed on the same integrated circuit, the former onto the portion to be tested for planarity and the latter onto perfecty planar portions. In this way, both the measure path and the reference paths can be formed jointly under the same conditions and on the same equipment, to thereby minimize the likelihood of resistance differentials arising from structural differences in the paths which are unrelated to the degree of planarity. A second aspect of the invention provides an integrated circuit comprising a continuous semiconductor substrate, a discontinuous intermediate layer (typically of polycrystalline silicon) disposed over a portion of the substrate, a dielectric layer deposited onto the substrate and the discontinuous intermediate layer, said dielectric layer having a surface to be tested for planarity, characterized in that it is provided with a measure path of a conductive film deposited across said surface of the dielectric layer at the location of the portion with the discontinuous intermediate layer and a reference path of a conductive film being identical with the measure path and deposited onto a perfectly planar portion of the integrated circuit. Such an integrated circuit includes the barely necessary for performing the aforesaid process. Preferably, the circuit includes said measure path and three such reference paths so interlinked electrically as to form a Wheatstone bridge arrangement. Conveniently, the three reference paths are formed on peripheral portions of the integrated circuit. Further features and advantages of a process and an integrated circuit according to the invention will become more clearly apparent from the following detailed description of preferred embodiments thereof, to be read in conjunction with the accompanying drawings. In the drawings: Figures 1 to 6 illustrate in schematic form subsequent manufacturing steps of an integrated circuit according to the invention, and specifically: Figure 1 shows a cross-section through a portion of the integrated circuit, with a substrate on which a discontinuous intermediate layerhas been deposited; Figure 2 is a sectional view of the same circuit portion as in Figure 1, with a dielectric layer deposited thereon; Figure 3 is a sectional view of the same circuit portion as in Figure 2, with a measure path deposited thereon; Figure 4 is a sectional view of a portion of the integrated circuit having no discontinuous intermediate layer over the substrate; Figure 5 is a sectional view of the same circuit portion as in Figure 4, with a dielectric layer deposited thereon; Figure 6 is a sectional view of the same circuit portion as in Figure 5, with a reference path deposited thereon; Figure 7 is a plan view showing schematically the measure and reference paths; and Figure 8 is a circuit diagram for the measure and reference paths. In the drawing figures, specifically in Figures 1 and 4, there is shown at 1 a continuous semiconductor substrate of an integrated circuit. In a portion 2 of the integrated circuit, a discontinuous intermediate layer 3, e.g. of polycrystalline silicon, is deposited over the substrate 1. At (preferably peripheral) portions 4, the substrate 1 has no discontinuous intermediate overlay, and the portions 4 are, therefore, perfectly planar. During the next manufacturing step of the integrated circuit, as particularly illustrated by Figures 2 and 5, a dielectric covering layer 5 is added. In the portion 2 provided with the discontinuous intermediate layer, the surface of the dielectric layer 5 is not perfectly planar, and shows undulations which follow the run of the underlying layer 3; in the portions 4, the surface of the dielectric layer 5 is instead perfectly planar because perfectly planar is the surface on which it is deposited. A metallic conductive film is deposited over the dielectric layer 5 into a measure path 6 and three reference paths 7, as shown in Figures 3, 6 and 7. The four paths are all identical with one another (in plan view, as previously explained) and laid into a preferably meandering pattern so as to concentrate the longest possible path within the smallest possible area. The measure path 6 is deposited at the portion 2 of the integrated circuit, whilst the reference paths 7 are deposited at the portions 4 thereof. As for the measure path 6, it is laid such that its individual straight sections are oriented substantially perpendicular to any substantially straight sections of the discontinuous intermediate layer 3. Formed from the same metallic film as the paths 6 and 7 are also electric connection sections, collectively designated 9, which are connected to the paths themselves and to four terminals 10a, 10b, 10c, 10d. Where the surface of the dielectric layer 5 is perfectly planar, the electric resistance of the path will show a given value; on the other hand, where the surface is not planar, then the electric resistance of the path will be the higher, the greater is the deviation of the surface from perfect planarity. In summary, the resistance R M of the measure path 6 is higher than the resistance R C of the reference path 7, and the degree of planarity of the surface can be appreciated from the value of the resistance R M . To find the value of the resistance R M , the measure path 6, three reference paths 7, connecting sections 9, and terminals 10 are all disposed into a Wheatstone bridge arrangement. This arrangement is well-known in electrical technology and enables a difference between the resistance R M of the measure path 6 and the resistance RC of the reference paths 7 to be assessed with great accuracy. Specifically, when a voltage VAB is applied to the terminals 10a and 10b, the voltage VCD measured across the terminals 10c and 10d will be given by the following relation: (1) V CD = V AB (1/2 - R C /(R C + R M ) By appropriate computation, it can be shown that the resistive value for the measure path 6 is given by the following relation: (2) R M = R C [(V AB + 2V CD )/(V AB - 2V CD )] The resistive value thus obtained is then checked against a preset scale indicating the degree of planarity. This scale can be established empirically. It will be readily apparent that an integrated circuit embodying this invention is inherently equipped to measure the degree of planarity of the dielectric layer non-destructively. This measure can be taken by the following process of this invention. In particular, this measuring process of the degree of planarity can be readily incorporated to the standard sequence of electric tests which any integrated circuit is to go through.

Claims: A process of measuring the degree of planarity of a dielectric layer (5) in an integrated circuit (1), characterized in that it comprises the steps of: depositing, onto a dielectric layer (5) to be measured for planarity, a predetermined measure path (6) of a conductive film; depositing a reference path (7) identical with the measure path (6) over a perfectly planar surface (4) ; and measuring the electric resistance through said measure path (6) against the electric resistance of the reference path (7). A process according to Claim 1, wherein the comparative measure is effected on a Wheatstone bridge arrangement comprising the measure path (6) and three identical reference paths (7). A process according to Claim 2, wherein the measure and reference paths (6, 7) are formed on the same integrated circuit (1), the former onto the portion (2) thereof to be measured for planarity and the latter onto perfectly planar portions (4). A process according to Claim 3, wherein the perfectly planar portions having the reference paths (7) deposited thereon are peripheral portions (4) of the integrated circuit (1). An integrated circuit comprising a continuous substrate (1), a discontinuous intermediate layer (3) disposed over a portion (2) of the substrate (1), a dielectric layer (5) deposited onto the substrate (1) and the discontinuous intermediate layer (3), said dielectric layer (5) having a surface to be tested for planarity, characterized in that it comprises a measure path (6) of a conductive film deposited across said surface of the dielectric layer (5) at the location of the portion (2) with the discontinuous intermediate layer (3) and a reference path (7) of a conductive film being identical with the measure path (6) and deposited onto a perfectly planar portion (4) of the integrated circuit (1). An integrated circuit according to Claim 5 and including said measure path (6) and three such reference paths (7) electrically connected to one another into a Wheatstone bridge arrangement. An integrated circuit according to Claim 6, wherein the three reference paths (7) are formed on peripheral portions (4) of the integrated circuit (1).

Inventors: CRISENZA GIUSEPPE PAOLO, DE SANTI GIORGIO, LOSAVIO ALDO, CRISENZA, GIUSEPPE PAOLO, DE SANTI, GIORGIO, LOSAVIO, ALDO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: G01B7
IPC codes: G01B7, G01B21, H01L21