High performance asynchronous bus interface

Abstract: A bus interface coupling an asynchronous bus and a slave device, such as a memory. The bus interface comprises an asynchronous bus controller and a synchronous bus controller. The asynchronous bus controller is implemented as two PAL state machines. One state machine controls the connection and disconnection phases of the bus protocol, while the other controls the data transfer phase. The synchronous bus controller controls data transfer between the bus and the slave device. The state machines are closely interlinked to each other and the synchronous bus controller allowing for increased bus efficiency.

Description: Field of the Invention The present invention is directed to an interface for coupling a device to an asynchronous bus. More particularly, the present invention relates to a high efficiency asynchronous bus interface. Background of the Invention In a computer system, a plurality of devices such as computer processors, memories, communication devices, etc. are typically coupled together via a common bus. As more devices are added to the bus, the efficiency of the entire system depends on the speed at which transactions between devices take place on the bus. A typical series of bus transactions occurs between a master processing device and a slave memory device. In this series of transactions, the master will transmit a request, via the bus, to all of the other devices coupled to the bus. It is up to the slave to determine whether or not it has been selected by the master. The selected slave will then send an acknowledgement to the master, thus establishing communication between the two devices. Next, data is transferred between the master and slave according to the original request. Finally, the master terminates the transaction with the slave and releases the bus. A short turnaround time delay between the master's request and the slave's response is important for efficient bus performance. This is achieved with a quick slave-bus interface controller. If the network bus is asynchronous, it is advantageous to make the slave-bus interface side of the controller asynchronous to take full advantage of the speed afforded by the asynchronous bus. This is generally accomplished using a state machine implemented as a programmable array logic (PAL) device. In an asynchronous bus protocol that utilizes a plurality of handshaking signals between a master and a slave to affect bus transactions, a large PAL may be required to detect and generate the appropriate handshaking signals. The operating speed of a PAL is a function of the number of terms that must be handled, and the large PAL that may be required by the asynchronous bus protocol will not provide an acceptable turnaround speed, particularly in high performance computer systems. Thus, there is a need for an asynchronous bus interface controller that can accommodate a plurality of handshaking signals and which operates with a quick turnaround time. There is also a need for an asynchronous bus interface controller that is easily adaptable to different devices couples to a standardized network bus. Summary of the Invention According to the present invention, there is provided an interface controller for a computer system as claimed in claim 1. The asynchronous bus interface controller of the present invention is implemented as two state machines utilizing two smaller and faster PAL devices. The first state machine is utilized as an address phase controller which controls the connection and disconnection phases of the bus protocol. The second state machine is utilized as a data phase controller which controls the data transfer phase of the bus protocol. The two state machines are closely interlinked, exchanging handshaking signals quickly and efficiently. The invention in its broad form resides in an interface controller adapted to be coupled between an asynchronous bus and a slave device, the asynchronous bus including address/data lines and handshaking signal lines and operating according to a bus protocol including a plurality of phases with handshaking signals on the handshaking signal lines to control the transition of phases on the asynchronous bus, the interface controller comprising: an asynchronous bus controller adapted to be coupled to the handshaking signal lines of the asynchronous bus, the asynchronous bus controller comprises first and second state machines coupled together, each of the first and second state machines operating to detect, and generate and transmit handshaking signals on the handshaking signal lines of the asynchronous bus during certain ones of the phases; and a transceiver separately coupled to at least one of the state machines and adapted to be coupled to each of the address/data lines of the asynchronous bus and the slave device, such that said transceiver can receive and transmit address and data information between the slave device and the address/data lines of the asynchronous bus under the control of at least one state machine. The asynchronous controller utilizes four handshaking signals with a synchronous "back-end" controller, which interfaces with the memory of the slave device and a transceiver coupled directly to the bus. The back-end controller also asserts the proper bus status signals and controls the data flow between the memory and the bus. One of these handshaking signals is used as an advance warning that more data is imminent at the bus transceiver inputs, on a read operation, or the data at the bus transceiver inputs is soon to be latched, on a write operation. This handshaking signal also initiates a delay. In response to the signal, the asynchronous controller sends back a second handshaking signal to the back-end controller if another bus request for a read or write is present. When the delay has timed out, the data at the transceiver will be clocked out, on a read operation, or latched in, on a write operation. Therefore, there is no lag when reading or writing successive blocks of data, and a certain amount of pipelining is achieved in the operation of this interface. To increase the efficiency of the asynchronous bus, one of the state variables for the data phase controller also serves as the latch enable and clock for a transceiver which is coupled between the memory of the slave and the bus. When changing states in the data phase controller, the same state variable always changes first, setting off a delay and causing the state to change from a stable to a cycle state. When the delay has timed out, the state changes to the appropriate next stable state. By using one of the state variables in this manner, several advantages are realized. First of all, delaying the changing of states insures that skewing errors seen in propagating signals on the bus will not occur. Also, using one of the state variables as a latch enable and clock on the bus transceiver allows data to be read from or written to the memory before the handshaking signals are stable on the bus. Because one of the state variables is used for these operations, the state machine has fewer terms and operates at a faster speed. Brief Description of the Drawings A more detailed understanding of the invention can be had from the following description of a preferred exemplary embodiment to be understood in conjunction with the accompanying drawing wherein: Fig. 1 is a block diagram of a computer system including a master/slave coupling through a system bus. Fig. 2 is a block diagram of the asynchronous bus controller of Fig. 1. Fig. 3A illustrates a state diagram for the address phase controller of the asynchronous bus controller of Fig. 2. Fig. 3B illustrates a flow diagram for state transitions in the address phase controller of Fig. 2. Fig. 4A illustrates a state diagram for the data phase controller of the asynchronous bus controller of Fig. 2. Fig. 4B illustrates a flow diagram for state transitions in the data phase controller of Fig. 2. Fig. 5 is a timing diagram for a read data transfer over the bus of Fig. 1. Fig. 6 is a timing diagram for a write data transfer over the bus of Fig. 1. Figs. 7A & 7B are additional timing diagrams for write and read data transfers over the bus of Fig. 1. Fig. 8 illustrates a detail of the data phase controller of the asynchronous bus controller of Fig. 2. Detailed Description Referring to Fig. 1, there is illustrated a block diagram of a computer system incorporating a bus interface according to the present invention. In this embodiment, two components are coupled to an asynchronous bus 50. The first component comprises a master 100 that operates to read and write data over the system bus from/to the second component that comprises a slave 101. The master 100 can be any of a variety of devices such as an I/O controller or a central processing unit. The slave 101 can comprise, for example, a memory device to be used by the master 100 for the storage of data. Pursuant to a feature of the present invention, the slave 101 comprises a synchronous multiplex address/data bus 1 which is coupled to each of a memory device 5 and a transceiver 11. The transceiver 11 operates as a latch in a write transfer of data to the memory device 5 and operates as a flip-flop in a read transfer of data from the memory device 5. In order to store address and data information used for read and write operations, the memory device 5 can be coupled to the bus 1 via an address latch 7 and a data latch 9 for input of address information and input/output of write and read data, respectively. The input and output data comprises data packets received and transmitted by other components, such as the master 100 coupled to the asynchronous bus 50. The transceiver 11 is also coupled to the address/data lines of the asynchronous system bus 50 for transfer of address information and data between the bus 1 and the bus 50. A synchronous bus controller 13 is further coupled to an asynchronous bus controller 15, that is, in turn, coupled to control lines of the asynchronous bus 50, as will be described in more detail below. The asynchronous bus interface of the memory slave comprises the synchronous bus controller 13 and the asynchronous bus controller 15. The synchronous bus controller 13 controls the synchronous multiplex address/data bus 1 for stabilization of address information and data on the bus 1 and also synchronizes the operation of the multiplex address/data bus 1 with the phases of the asynchronous bus 50 via the asynchronous bus controller 15, as will now be described. The bus 50 can be implemented according to the Futurebus asynchronous bus protocol promulgated by the IEEE (ANSE/IEEE Std. 896.1). The IEEE standard Futurebus protocol implemented on the bus 50 operates on a master/slave basis. A master is defined as a module that has acquired control of the bus 50 through the control acquisition procedure provided in the Futurebus protocol. A slave is defined as a module that is capable of being addressed by and is able to carry out transactions with a master. In order to maximize the performance of the asynchronous bus based network, the synchronous and asynchronous bus controllers 13, 15 of the slave 101 have been implemented to provide high speed data transfers over the bus 50 during each bus transaction. A bus transaction in the Futurebus protocol comprises three phases, as follows: 1) a connection phase: the bus master selects and establishes a connection to a desired slave; 2) a data transfer phase: where data are interchanged between the master and the connected slave; and 3) a disconnection phase: where the master terminates the transaction and disconnects from the slave. The Futurebus protocol provides for asynchronous handshaking during each bus transaction for high speed synchronization between the master 100 and slave 101 during the transmission of address information and data over the bus 50. The handshaking occurs over control lines of the bus 50 and includes three address handshake signals and three data handshake signals for data valid and acknowledge indications during address and data transfers, as follows: address handshake ADDRESS SYNC (AS*) is a synchronization signal controlled by the master 100 that handshakes with the following corresponding signals asserted by the slave 101 in response to the AS* signal, the AS* signal indicates that the address information is stable on the address/data lines of the bus 50; ADDRESS ACKNOWLEDGE (AK*) is an acknowledge signal controlled by the slave 101 to handshake with the AS* signal asserted by the master 100; ADDRESS ACKNOWLEDGE INVERSE (AI*) is an additional acknowledge signal controlled by the slave 101 to handshake with the AS* signal asserted by the master 100; data handshake DATA SYNC (DS*) is a synchronization signal controlled by the master 100 that handshakes with the following corresponding signals asserted by the slave 101 in response to the DS* signal. In the case of a write, the DS* signal indicates that the data is stable on the address/data lines of the bus 50, and in the case of a read, the DS* signal indicates that the master 100 is requesting more data; DATA ACKNOWLEDGE (DK*) is an acknowledge signal controlled by the slave 101 to handshake with the DS* signal asserted by the master; DATA ACKNOWLEDGE INVERSE (DI*) is an additional acknowledge signal controlled by the slave 101 to handshake with the DS* signal asserted by the master 100. The asynchronous bus controller 15 is responsible for completing the handshake scheme with the bus interface 17 of the master 100 in an asynchronous operation. Moreover, the synchronous and asynchronous bus controllers 13, 15 of the slave 101 are designed to interact with one another through their own handshake scheme that does not depend upon the specific capabilities of the synchronous bus controller 13 in performing its logic operations such as address decode and memory access. The synchronous and asynchronous bus controllers 13, 15 are coupled together by a point-to-point connection 19 which passes signals designated as KEN_SEL, ARDY, FRDY, and ARMRDY (described below). In order to achieve as high a performance asynchronous interface as possible between the asynchronous bus controller 15 and a respective bus interface 17, the asynchronous bus controller 15 is split into two individual state machines, an address phase controller 102 to control the connection and disconnection phases of the Futurebus protocol and a data phase controller 103 to control the data transfer phase of the protocol, as illustrated in Fig. 2. The splitting of the asynchronous bus controller 15 into two state machines allows the controller to be implemented in two seven term equation, 4.5 nsec. 16L8 PALs rather than one large but slow 10 nsec. PAL. The two state machines 102, 103 are closely interlinked. Referring now to Fig. 2, there are five signals exchanged between the address phase controller 102 and the data phase controller 103. An ADD_GO signal 104 indicates that the address phase controller 102 is done processing for the time being and enables the data phase controller 103 to change states. When negated, a STAT_GO signal 106 indicates to the data phase controller 103, that the address phase controller 102 has finished the connection phase and the data phase controller 103 is to commence the data transfer phase. A CONN_GO signal 108 indicates to the address phase controller 102 that the data phase controller 103 is ready for the data transfer phase. A START_DECODE signal 110 indicates that the data phase controller 103 is not in the data transfer phase and is awaiting information from the address phase controller 102. A DAT_GO signal 112 indicates the commencement of the data transfer phase. The difference between the DAT_GO signal 112 and the STAT_GO signal 106 is that the DAT_GO signal 112 generates its value based on the state variables of the address phase controller 102. Each of the START_DECODE signal 110 and CONN_GO signal 108 is generated with the state variables of the data phase controller 103. The handshake signals required by the Futurebus protocol are exchanged between the state machines 102, 103 and the bus 50. The AS* signal 114 is received by the address phase controller 102 from the bus 50, while each of the AI* signal 116 and the AK* signal 118 is sent to the bus 50 by the address phase controller 102. The DS* signal 120 is received by the data phase controller 103 from the bus 50, while each of the DI* signal 122 and the DK* signal 124 is sent to the bus 50 by the data phase controller 103. Both the address phase controller 102 and data phase controller 103 control the DI* signal 122 and DK* signal 124. The synchronous bus controller 13 monitors the AS* control line of the bus 50 and asserts and sends an ARDY signal 126 to the address phase controller 102 when it sees the AS* signal ("address sync" signal asserted by the master 100 during the connection phase to inform the slave 101 that address and command data are valid on the bus 50) and has decoded the address on the bus 50. Before completion of the address decoding and if the synchronous bus controller 13 has determined that the slave 101 has been selected and should participate in the bus transaction, the synchronous bus controller 13 will also assert and send an SL* signal (indicating that the 101 has been selected) to the transceiver 95 and a KEN_SEL signal 128 to the address phase controller 102. The data phase controller 103 generates and sends an FRDY signal 130 to the synchronous bus controller 13 and receives an ARMLRDY signal 132 from the synchronous bus controller 13. The ARMLRDY signal 132 is also coupled to a 25 nsec. delay which results in a second signal, an LRDY signal 133 that is received at the data phase controller 103. The ARMLRDY signal 132 is an advance warning that data is imminent at the bus transceiver 11 (if executing a read operation) or data in the bus transceiver 11 is soon to be latched (if executing a write operation). The FRDY signal 130 is toggled by the data phase controller 103 immediately if another DS* signal 120 has come in from the bus 50 in the meantime (See states B 206 and D 218 of the data phase controller 103, Figs. 4A and 4B). The synchronous bus controller 13 will interpret the received FRDY signal 130 as another read or write request. When the 25 nsec. delay line has timed out, the resulting LRDY signal 133 causes the data phase controller 103 to clock out the new data on a read or open the latch 11 on a write. This allows for a high degree of pipelining to be achieved in the slave 101. There are several delay signals used in the state machines 102, 103. The purpose of these signals is to insure that signals asserted onto the bus 50 or received from the bus 50 have been appropriately latched. Also, these delays eliminate skewing errors that occur in the propagation of a series of signals. In the address phase controller 102, the assertion of an ARMDLY1 signal 134 will result in a return DLY_IN1 signal 136 to the address phase controller 20 nsec. later. The DLY_IN1 signal 136 is used to control certain state changes in the address phase controller 102, as will appear. In the data phase controller 103, an ARMDLY2 signal 138 serves two purposes. First, the ARMDLY2 signal 138 serves as one of the state variables of the data phase controller 103. When the ARMDLY2 signal 138 is asserted, it sets off a 15 nsec. delay resulting in the receipt of a DLY_IN2 signal 140 at the data phase controller 103 used to control state changes in the data phase controller 103. There are four stable states in the data phase controller 103 and three state variables. Each transfer between stable states begins with the toggling of the ARMDLY2 signal 138, thus insuring at least a 15 nsec. delay between stable states. The synchronous bus controller 13 uses the delay to assert its own signals in proper timing. The second use for the ARMDLY2 signal 138 is that it serves as an ACLK input and LE (Latch Enable) input to the transceiver 11. Therefore, the ARMDLY2 signal 138 controls the latching of data on writes and the clocking of data on reads. Since the data phase controller 103 asserts the same signals for both reads and writes, the state machine is made much simpler. There is no delay in clocking read data out or in opening the latch to let write data in. The data is also given a head start through the transceiver 11 before all other handshake signals have been decoded. Finally, the hold time of the write data at the transceiver 11 is guaranteed since the latch operation of the transceiver 11 is closed well before the appropriate DI* or DK* signals (which indicate the latching of the data by the slave) are asserted on the bus 50, as will appear. Fig. 3A illustrates a state diagram for the address phase controller 102 and Fig. 3B illustrates a flow diagram for state transitions in the address phase controller 102. Upon reset, the address phase controller 102 remains in state A 150, until each of the AS* signal 114 (controlled by the master on the bus 50), the ARDY signal 126 (controlled by the synchronous bus controller 13), and the START_DECODE signal 110 (controlled at reset by the data phase controller 103, as will be described below) is asserted. In state A 150, the AI* signal 116 (address acknowledge inverse) remains asserted, and each of the AK* signal 118 (address acknowledge) and DK* signal 124 (data acknowledge) remains negated. Also, in state A 150, the ARMDLY1 signal 134 is asserted as well as the STAT_GO signal 106. When the slave 101 receives the AS* signal 114, the address on the bus 50 is latched through the transceiver 11 and decoded by the synchronous bus controller 13. Upon completion of address decode, the synchronous bus controller 13 asserts the ARDY signal 126. A transition from state A 150 to state B 156 occurs when AS* signal 114 and the ARDY signal 126 are both asserted in decision block 152 and the START_DECODE signal 110 is asserted in decision block 154. In state B 156, each of the STAT_GO signal 106, ARMDLY1 signal 134, and AI* signal 116 remains asserted while the DK* signal 124 remains negated. The ADD_GO signal 104 is asserted and the AK* signal 118 is changed to an asserted state. Referring now for a moment to Figs. 4A and 4B, Fig. 4A illustrates a state diagram for the data phase controller 103 and Fig. 4B illustrates a flow diagram of the state transitions of the data phase controller 103. In state A 200 and upon reset of the data phase controller 103, the ARMDLY2 signal 138 is asserted which causes the DLY_IN2 signal 140 to be asserted 15 nsec. later. Moreover, each of the DI* signal 122, DK* signal 124, START_DECODE signal 110 and FRDY 130 signal is asserted and the CONN_GO signal 108 is negated. The state will change to state B 206 in the data phase controller 103 once the DLY_IN2 140 is received (15 nsec. after asserting the ARMDLY2 signal 138) in decision block 202 and the ADD_GO signal 104 is received from the address phase controller 102 in decision block 204 (see state B 156, Figs. 3A and 3B). At state B 206 in the data phase controller 103, each of the DI* signal 122 and the FRDY signal 130 remains asserted. In addition, the CONN_GO signal 108 is asserted and the ARMDLY2 signal 138 and the DK* signal 124 are each negated. Referring back to Figs. 3A and 3B, the detection of the negation of the ARDY signal 126 by the synchronous bus controller 13 in decision block 158, the assertion of the CONN_GO signal 108 by the data phase controller 103 in decision block 160 and the assertion of the KEN_SEL signal 128 by the synchronous bus controller 13 in decision block 162 causes the state in the address phase controller 100 to change from state B 156 to state C 164. In state C 164, each of the AI* signal 116, AK* signal 118, and STAT_GO signal 106 remains asserted while the DK* signal 124 remains negated. In addition, the ARMDLY1 signal 134 is negated which will cause the DLY_IN1 signal 136 to be negated 20 nsec. later and the ADD_GO signal 104 is negated causing the data phase controller (see Figs. 4A and 4B) to switch from state B 206 back again to the original state A 200 (see decision blocks 208 and 210). As described below, the ARMDLY2 signal 138 is coupled to transceiver 11. The transitions from state A 200 to state B 206 and back to state A 200 cause a rising and falling edge on the ARMDLY2 signal 138 in order to clock the status into the futurebus transceiver 95. Finally, the DI* signal 122 (data acknowledge inverse) is asserted to prepare for the data transfer phase. The 20 nsec. delay started by the ARMDLY1 signal 134 provides the synchronous bus controller 13 with sufficient time to assert status signals onto the bus 50, pursuant to the Futurebus protocol. Once the negated DLY_IN1 signal 136 is detected by the address phase controller 102 in decision block 166 and the negated CONN_GO signal 108 in decision block 168, the state of the address phase controller 100 changes from state C 164 to state G 170 (CONN_GO 108 had been negated in state A 200 in the data phase controller 103, see Fig 4B). In state G 170, each of the AK* signal 118, STAT_GO signal 106 and DI* signal 122 remains asserted while each of the DK* signal 124 and ARMDLY1 signal 124 remains negated. The AI* signal 116 signal (address acknowledge inverse) is negated indicating to the master 100 that the status and capability information on the bus, pursuant to the Futurebus protocol is valid. The ADD_GO signal 104 is asserted which causes the state of the data phase controller 103 to change from state A 200 to state B 206 (see Figs. 4A and 4B). As mentioned previously, state B 206 in the data phase controller 103 causes the CONN_GO signal 108 to become asserted. As illustrated in Figs. 4A and 4B, the state of the address phase controller 102 will change from state G 170 to state D 174 when it sees the asserted CONN_GO signal 108 in decision block 172. In state D 174, each of the AK* signal 118, ADD_GO signal 104 and DI* signal 122 remains asserted while each of the AI* signal 116, DK* signal 124 and ARMDLY1 signal 134 remains negated. In addition, the STAT_GO signal 106 is negated and the DAT_GO signal 112 is asserted. At this time, the connection phase is ended and the data transfer phase is ready to begin. The address phase controller 102 will remain in state D 174 until the data transfer phase is completed. Referring to Fig. 5, a standard timing diagram for a compelled read data transfer according to the Futurebus protocol is shown. A read data transfer involves a read of data stored in the 101 by one of the masters 100. In this diagram an asserted line indicates that the signal on that line is a low signal (i.e., logic 0). Conversely a negated line indicates that the signal on that line is a high signal (i.e., logic 1). As mentioned previously, an assertion of the AS* signal 114 indicates that valid address and command data is on the bus 50. This transition is followed by an assertion of the AK* signal 118. Some time later the AI* signal 116 is negated indicating that the slave's status and capability data is valid on the bus 50. The negation of the AI* signal 116 also indicates the end of the connection phase. During the data transfer phase, the slave 101 asserts the DK* signal 124 after receiving the asserted DS* signal 120 from the master 100. The slave 101 then places the requested data into its transceiver 11 and negates the DI* signal 122 indicating that valid read data is on the bus 50. This transition of the DS* 120, DI* 122, and DK* 124 signals is referred to as an ODD beat. During an EVEN beat, the DS* signal 120 is negated by the master 100 and, in response, the DI* signal 122 is asserted by the slave 101. The DK* signal 124 is negated by the slave when the slave has placed valid read data on the bus 50. During the data transfer phase, ODD and EVEN beats alternate until the master 100 negates the AS* signal 114, indicating that no more read data is to be transferred. At the completion of the disconnection phase, the DS* signal 120 remains negated as does the DK* signal 124. During the disconnection phase, the master 100 places valid disconnect command data on the bus 50 and negates the AS* signal 114. The AI* signal 116 is asserted soon after. When the AK* signal 118 is negated by the slave, status information on the bus 50 from the slave 101 is valid. The negation of the AK* signal 118 also indicates the end of the disconnection phase. Referring to Fig. 6, a standard timing diagram for a compelled write data transfer according to the Futurebus protocol is shown. A write data transfer involves a write of data by one of the masters 100 to the slave 101. Comparing the timing diagram of Fig. 6 with the one of Fig. 5 indicates that the timing of the AS* 114, AK* 118, AI* 116, DS* 120, DK* 124, and DI* 122 signals is similar. The notable difference between the two diagrams is the earlier timing of valid data on the bus 50 during the write operation. During an ODD beat of a write data transfer the master asserts the DS* signal to indicate that valid write data is on the bus 50. When the slave sees the asserted DS* signal, it asserts DK* and captures the data through the transceiver 11. The slave 101 then negates DI* to indicate that it has captured the write data. During the EVEN beat, the master negates DS* to again indicate that valid write data is on the bus 50. When the slave 101 sees the negation of DS*, it asserts DI* and again captures the write data on the bus 50. Thereafter the slave 101 negates DK* to notify the master that it has captured the data. During the data transfer phase, ODD and EVEN beats alternate until the master 100 negates the AS* signal 114, indicating that no more read data is to be transferred. The connection and disconnection phases of the write transfer are similar to the read transfer. Referring to Figs. 4A and 4B, the data phase controller 103 remains in state B 206 until the DS* signal 120 is received from the master 110 on the bus 50 in decision block 212. The state then changes to state C 214 where the DI* signal 122 remains asserted and the ARMDLY2 signal 138 is asserted. The DK* signal 124 (data acknowledge) is asserted indicating that the slave 101 is ready to transfer information to/from the bus 15. The FRDY signal 130 is negated. The FRDY signal 130 indicates to the synchronous bus controller 13 that another read or write request is forthcoming. In decision block 216, once the DLY_IN2 signal 140 is returned to the data phase controller 103 (as a result of asserting the ARMDLY2 138 signal) the state is changed from state C 214 to state D 218. In state D 218, each of the DK* signal 124 and CONN_GO signal 108 remains asserted while the FRDY 130 signal remains negated. The ARMDLY2 signal 138 is negated which will result in a negated DLY_IN2 signal 140 15 nsec. later. The DI* signal 122 is negated to indicate that data has been latched in from the bus 50 or sent to the bus 50. The data phase controller 103 transitions from state C 214 to state D 218 during the ODD beat of the data write or read. In the EVEN beat, the DS* signal 120 changes to a negated state (see decision block 224) and the data phase controller 103 transitions through state A 200 and B 206. In decision block 222 the DAT_GO 112 signal is still asserted (from state D 170 of the address controller 102). The state changes from state D 218 to state A 200 as long as LRDY is asserted, indicating that the synchronous bus controller 13 is ready (see decision block 220). In state A 200, the DI* signal 122 and the ARMDLY2 signal 138 are each asserted. Since the ADD_GO signal 104 is still asserted (from state D 174 of the address phase controller 102), the state changes from state A 200 to state B 206 after the DLY_IN2 signal is received 15 nsec. later (see decision block 202) where the DK* signal 124 is negated do indicate that the data has been latched in or sent to the bus 50. The data phase controller 103 continues jumping from state to state and between ODD and EVEN beats until the AS* signal 114 is negated by the master indicating that no more data is to be read or written. Referring back to Figs. 3A and 3B, the address phase controller 102 remains in state D until the synchronous bus controller 13 returns an ARDY signal informing the address phase controller 102 that the AS* signal from the master 100 has been negated to indicate the disconnection (see decision block 176). Upon receiving the ARDY signal 126, the state changes from state D 174 to state F 178. In state F 178, the AK* signal 118 remains asserted while the DK* signal 124 remains negated. The AI* signal 116 is asserted indicating the disconnection phase has started. The ARMDLY1 signal 134 is asserted resulting in the receipt of the DLY_IN1 signal 136 20 nsec. later. The STAT_GO signal 106 is asserted and each of the ADD_GO signal 104 and the DAT_GO signal 112 is negated indicating the disconnection phase to the data phase controller 103. Negation of each of the ADD_GO signal 104 and the DAT_GO signal 112 will cause the data phase controller 103 to remain in state A 200 (see decision blocks 204 and 222 of Fig. 4B). The DI* signal 122 is negated indicating that no more reading or writing will be done until another AS* signal 114 is received from the master. The DAT_GO signal 112 is negated which also places the data phase controller 103 into its A state 200. In state A 200 of the data phase controller 103, the CONN_GO signal 108 is negated. The address phase controller 102 remains in state F 178 until the negated CONN_GO signal 108 is received from the data phase controller 103 (see decision block 180). Both controllers 102, 103 are now in their respective reset states and ready for the next read or write operation. One further branch exists in the state transition flow of the address phase controller 102 which is executed if the slave 101 has not been selected. In decision block 162, if the KEN_SEL signal 128 has not been asserted by the synchronous bus controller 13 to indicate that the slave 101 has not been selected as such then the state changes from state B 156 to state E 182. In state E 182, the AK* signal 118 and the STAT_GO signal 106 remain asserted. Each of the AI* signal 116, ARMDLY1 signal 134, and ADD_GO signal 104 is negated. Because the ADD_GO signal 104 is negated, the data phase controller 103 will remain in state A 200 (see Figs. 4A and 4B) and never reach the data transfer phase. Upon receipt of the ARDY signal 126 from the synchronous bus controller 13 in decision block 186 and receipt of the negated DLY_IN2 signal in decision block 184, the state changes from state E 182 to state F 178. Therefore, once the master 100 has initiated a read or write request, the address phase controller 102 will return back to the reset state A 150. Referring to Fig. 4A, each cycle state is defined by three state variables. The first of these variables is the ARMDLY2 signal 138. As mentioned previously, this signal is the first to change. As can be seen in Fig. 4A, each change in ARMDLY2 138 causes the state to change from a stable state to one of four cycle states 226, 228, 230, and 232. Before the connection phase is complete, the data phase controller 103 changes from state A 200 to state B 206 and back to state A 200. This is done in order to get a rising edge on the input to the transceiver 11. Without cycle states, two state variables may have next states at the same time leading to an unwanted next state. With the states shown in Fig. 4A only one state variable can be changed at a time in order to change states. Referring to Figs. 7A and 7B, more detailed timing diagrams for write and read operations are shown. As mentioned previously, an ODD or EVEN beat in the data transfer phase begins with a transition of the DS* signal 120. For this embodiment of the invention, 4.5 nsec. PALs are used. Referring to Fig. 7A, one PAL delay (4.5 nsec.) takes place between the transition of the DS* signal 120 and the transition of the ARMDLY2 signal 138. This signal starts off a 12 nsec. delay, for example, resulting in another transition of the ARMDLY2 signal 138 one PAL delay later. Finally, the DI* signal 122 is negated one more PAL delay later. This results in a total 25.5 nsec. time span between the DS* transition and the release of either the DI* signal 122 or the DK* signal 124, depending on the type of data beat being executed. Referring to Fig. 7B, the timing diagram for a read operation is shown. The timing is similar except that the transition of the DI* signal 122 occurs simultaneously with the ARMDLY2 signal 138. This one PAL delay savings is due to the fact that the data transceiver 11, which can be implemented in a DS3886 transceiver, is a flip-flop in the read direction and a latch in the write direction. Upon receipt of a negated ARMDLY2 signal 138, the DI* and DK* signals are decoded directly from the stable state and the input condition, rather than the transition state. Thus, on reads, the DS* to DI*/DK* turnaround time by this interface is one PAL delay faster than for writes. On a read operation, a total 21 nsec. time span exists between the DS* transition and the release of either the DI* 122 or DK* 124 signals, depending on the type of data beat being executed. Referring to Fig. 8, the connection of the ARMDLY2 signal to the transceiver 11 is shown. The data phase controller 103 is implemented as a PAL 250. As mentioned previously, the PAL 250 can comprise a 4.5 nsec. 16L8 PAL. The state transition signal received by the PAL 250 is the DLY_IN2 signal which is delayed 12 nsec. from the ARMDLY2 signal using a delaying device 254. However, the ACLK input and LE (Line Enable) input of the transceiver 11 are each coupled directly to the ARMDLY2 output of the PAL 250 so that read and write data are immediately available at the transceiver 11 for transfer onto or from the bus 50. The synchronous bus controller 13 and asynchronous bus controller 15 arrangement of the present invention provides a high speed interface to the bus 50 through the use of 4.5 nsec. PALs for rapid execution of Futurebus transactions involving the slave 101. This facilitates the prompt completion of the bus transactions required during the operation of the asynchronous bus 50.

Claims: An interface controller for a computer system, the computer system comprising a master device (100), a slave device (5), an asynchronous bus (50), including address/ data lines and handshaking signal lines, operating according to a bus protocol including a connection phase, a data phase and a disconnection phase, with handshaking signals (AS*,AK*,DK*,DI*) on the handshaking signal lines controlling the transition of the phases, and a transceiver (11,95) coupled to the slave device by means of a synchronous bus (1), and to the address/ data lines of the asynchronous bus for transfer of address and data between the slave device and the address/ data lines, characterised in that the interface controller comprises a synchronous bus controller (13), and an asynchronous bus controller (15), coupled together by means of a signal line (19), the synchronous controller being operable to synchronise phases of the synchronous bus with the phases of the asynchronous bus, and adapted to be additionally coupled to the transceiver and to the asynchronous bus by means of handshaking signal lines, the asynchronous bus controller being adapted to be coupled to handshaking lines of the asynchronous bus and to a signal line coupled to the transceiver, the asynchronous bus controller comprising first and second state machines (102,103), the state machines being operable to receive and generate handshaking signals from and to the master device and each other in accordance with the bus protocol whereby the first state machine (102) controls the connection and disconnection phases and the second state machine (103) controls the data transfer phase. An interface controller according to claim 1, wherein the first and second state machines comprises respective first and second programmable array logic devices. An interface controller according to claim 1 or claim 2, wherein the master device asserts an address synchronisation signal (AS*) indicating that addressing information placed on the asynchronous bus is valid, the address synchronisation signal indicating the beginning of the connection phase, and a data synchronisation signal (DS*) indicating that, in the case of the master device writing data to the slave, data information placed on the asynchronous bus is valid, and, in the case of the master reading data from the slave, that there is a request by the master for more data from the slave, and wherein the interface controller asserts address acknowledge signals (AK*,AI*) indicating the receipt of address information by the slave from the master, the address acknowledge signals indicating completion of the connection and disconnection phases, and data acknowledge signals (DK*,DI*) indicating, in the case of the master writing data to the slave, the receipt of data information by the slave from the master, and, in the case of the master reading data from the slave, that data information from the slave is valid on the asynchronous bus, the first state machine controlling the address and data acknowledge signals during the connection and disconnection phases, and the second state machine controlling the data acknowledge signals during the data transfer phase. An interface controller according to any preceding claim, wherein each of the first and second state machines comprises a plurality of state variables, and stable state transitions occur in the second state machine by first toggling a first state variable (ARMDLY2), such that the second state machine changes from a stable state (200,206,214,218) to a cycle state (226,228,230,232), the interface controller further comprising a first delay device having an input and an output coupled to the second state machine such that the first state variable is supplied to the input of the first delay device and the output is coupled to the second state machine, such that a toggling of the output causes the second state machine to change from a cycle state to a stable state. An interface controller according to claim 4, wherein the first state variable is coupled to the transceiver and controls the receiving and transmission of data information in the transceiver. An interface controller according to any one of claims 3 to 5, wherein the synchronous bus controller sends a first handshaking signal (ARMLRDY) to the second state machine when data is imminent at the transceiver, in the case of the master writing data to the slave device, or when data is soon to be latched in the transceiver, in the case of the master reading data from the slave device, the interface controller further comprising a second delay device having an input and an output coupled between the synchronous controller and the second state machine such that the first handshaking signal is supplied to the input of the second delay device, the second state machine being operable to send a second handshaking signal (FRDY) to the synchronous bus controller upon receipt of the data synchronisation signal from the asynchronous bus, the output of the second delay device being supplied to the second state machine such that the output of the second delay device and the second handshaking signal in the synchronous bus controller controls the receiving and transmission of data information in the transceiver.

Inventors: CREEDON TADHG, CREMIN CON D, MURPHY CIARAN P, CREEDON, TADHG, CREMIN, CON D., MURPHY, CIARAN P.
Applicants: CABLETRON SYSTEMS INC, CABLETRON SYSTEMS, INC.
Application year: 1992
Main classification: G06F13
IPC codes: G06F13