Method of forming vias structure obtained

Abstract: A first metal region (12,14) is formed over an underlying region (10). A first insulating layer (16) is formed over the integrated circuit. A second insulating layer (18) is then formed over the first insulating layer (16). A portion of the second insulating (18) layer is etched to expose a portion of the first insulating layer (16) wherein the exposed first insulating layer (16) and the remaining second insulating layer (18) form a substantially planar surface. A metal oxide layer (20) is formed over the exposed first insulating layer (16) and the remaining second insulating layer (18). A photoresist layer (22) is formed and patterned over the metal oxide layer (20). The metal oxide layer (20) is then selectively etched to form a via (24) exposing a portion of the first insulating layer (16). The first insulating layer (16) in the via (24) is then selectively etched to expose a portion of the first metal region (12). The photoresist layer (22) is removed and a second metal layer (26) is then formed over the metal oxide layer (20) and in the via (24) contacting the first metal region (12).

Description: The present invention relates generally to semiconductor integrated circuits, and more specifically to a contact structure and method of forming the same. As integrated circuit devices become more complex and increased device density becomes a necessity, greater numbers of interconnect levels are required to connect the various portions of the device. Complex devices are being designed which have two or more levels of polycrystalline silicon interconnect, followed by one or more levels of metal interconnect. One of the more critical process steps is the interconnection of two metal or conducting layers on different levels separated by an interlevel dielectric. Presently, an underlying conductive layer is covered with an interlevel oxide layer. The interlevel oxide layer follows the topography of the underlying conductive layer. A contact or via is then formed through the interlevel layer exposing a selected area of the surface of the underlying conductive layer. An upper conducting layer is then patterned and interconnected through the contact or via to the underlying conducting layer. EP-A-0249173 discloses a method of fabricating a multilevel MOS wafer which incudes the steps of applying a first layer of dielectric over a metal layer, applying a layer of spin-on-glass over the first dielectric layer, etching the spin-on-glass layer to reveal at least a portion of the first dielectric layer, and applying a second layer of dielectric over the first dielectric layer. EP-A-0241729 discloses a method of fabricating a VLSI device in which a layer of aluminium oxide or other metal oxide is employed as an etch stop. Historically, the size of the via was typically smaller than the width of the underlying conductive layer in order to compensate for any mask misalignment. If any misalignment occurred whereby a part of the via extended beyond the width of the underlying conductive layer, it was probable to etch through the interlevel oxide into the substrate or layer underlying the oxide to the side of the conductive layer. The prior art, shown in Figure 1, illustrates the problem. Metal conductive regions 32 and 34 are formed over an underlying region 30. An interlevel oxide layer 36 is formed over the surface of the integrated circuit following the topography of the metal regions 32, 34 and the underlying region 30. Contact opening or via 38 is formed through the interlevel oxide 36 to expose a portion of the metal region 32. Metal layer 32 will interconnect with an overlying metal layer. However, if there is a mask misalignment, the contact or via 38 will be etched through the junction between layer 36 and region 30 into the underlying layer 30. When a subsequent metal layer 40 is formed to interconnect with metal layer 32, layer 40 will also contact the underlying layer 30 in the bottom of via 38 at the region shown as 42. Where metal layer 40 interconnects layer 30 at region 42, the integrity of the interconnection between metal layers 32 and 40 will be compromised. A short circuit condition may exist between layer 40 and an underlying layer 30. There may also be a leakage current if there is a transistor under metal layer 32 causing substantial degradation of the transistor. In other words, there may be short circuit conditions between metals and doped polysilicon formed in different levels or there may be short circuit conditions between metals formed in the same levels. It would be desirable to provide a process for fabricating semiconductor devices, and structures formed thereby, which increases device density through the use of smaller metal interconnects while preventing leakage current or a short circuit condition. It is desirable for such technique to provide a smaller enclosure for the underlying metal region of the interconnect without causing degradation of device functionality. It would further be desirable to provide an interconnect which is very nearly planar on its upper surface. It is also desirable for such a technique to be compatible with present day manufacturing processes, and be relatively simple to use. The present invention provides, according to claim 1, a method of forming a contact structure of an integrated circuit device, comprising the steps of: forming a lower metal interconnect structure over an underlying surface; forming a lower, plasma oxide layer over the lower interconnect structure and the underlying surface; planarizing the thus obtained surface by forming a planarizing insulating layer over the lower oxide layer; forming an upper oxide layer over the lower oxide layer and the planarizing layer; forming an opening through the lower oxide, planarizing insulating and upper oxide layers to expose a portion of the lower interconnect structure in the bottom thereof; and forming an upper metal interconnect layer over the upper oxide layer and in the opening contacting the lower interconnect structure; characterized in that the upper oxide layer is formed from a metal oxide, and in that the step of forming an opening comprises the steps of selectively etching the upper oxide layer to form a via and selectively etching the lower oxide layer and any exposed planarizing layer in the via to expose a portion of the lower interconnect structure, in that a portion of the bottom of the opening exposes a portion of the lower oxide layer, and in that the upper interconnect layer lays over and contacts the exposed portion of the lower oxide layer in the opening. The present invention also provides, according to claim 1, a contact structure of an integrated circuit device, comprising: a lower metal interconnect structure disposed over an underlying surface; a lower, plasma oxide layer disposed over the lower interconnect structure and the underlying surface; a planarizing insulating layer disposed over at least a portion of the lower oxide layer, wherein the planarizing layer has an etch rate approximately the same as the etch rate of the lower oxide layer; an upper oxide layer disposed over the planarizing layer and the lower oxide layer; an opening extending through the lower oxide, planarizing insulating and upper oxide layers to expose a portion of the lower interconnect structure in the bottom thereof; and an upper metal interconnect layer which contacts the lower interconnect structure in the bottom of the opening; characterized in that the upper oxide layer is formed from a metal oxide whereby the upper oxide layer can be selectively etched over the lower oxide layer and the planarizing layer and the lower oxide layer and the planarizing layer can be selectively etched over the lower interconnect structure, a portion of the bottom of the opening exposes a portion of the lower oxide layer, and in that the upper interconnect layer lays over and contacts the exposed portion of the lower oxide layer in the opening. The present invention may provide a method wherein the metal interconnect structure has a thickness of between approximately 5000 to 8000 angstroms (10 Angstroms = 1 nm), the lower oxide layer has a thickness of approximately 5000 angstroms, the planarizing oxide layer has a thickness of between approximately 3000 to 5000 angstroms, the metal oxide layer has a thickness of approximately 5000 angstroms, or the upper interconnect layer has a thickness of approximately 5000 to 8000 angstroms. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: Figure 1 is a cross-sectional view of the fabrication of a semiconductor device structure according to the prior art. Figures 2-6B are cross-sectional views of the fabrication of a semiconductor device structure according to the present invention. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. Referring to Figure 2, a first conductive layer shown as regions 12 and 14 are to be formed over an underlying region 10 by methods known in the art. Regions 12, 14 will typically be the first and underlying metal regions of a subsequently manufactured interconnect. Regions 12, 14 will have a thickness of between approximately 5000 to 8000 angstroms. These regions may also typically be formed from an aluminum or a refractory metal. For simplicity, these regions will be referred to herein as metal regions. Also, for purposes of illustrating this invention, only an interconnect formed with region 12 will be depicted. The underlying region 10 or various portions of region 10 may be a substrate, an oxide layer, or an active area such as a source/drain region of a transistor or the gate of a transistor (not shown). While regions 12, 14 are formed from the same metal layer, regions 12, 14 do not need to lie necessarily in the same plane on the integrated circuit. A first interlevel dielectric layer 16 is an insulating layer formed on the integrated circuit. Layer 16 will typically be a plasma oxide layer having a thickness of approximately 5000 angstroms. A second interlevel dielectric layer 18 is also an insulating layer formed over layer 16. This upper layer 18 tends to form a more planar surface than the underlying features. Layer 18 may typically be a spin-on-glass or a polyimide or any material that can be applied to planarize the surface and subsequently be etched back such as photoresist. Layer 18 will have a thickness of between approximately 3000 to 5000 angstroms. Device fabrication up to this stage utilizes conventional process steps well known in the art. Referring to Figure 3, the second insulating layer 18 is etched to form a substantially planar surface with a total thickness of approximately that of the first insulating layer 16. This etch step will thus expose a portion of the first insulating layer 16 while layer 18 remains in the uneven areas to form the more planar surface. A metal oxide layer 20 is then deposited over the surface of the first and second interlevel dielectric layers 16 and 18 to increase the overall interlevel dielectric region between metal 12 and an upper level interconnect. The increase in the overall thickness of the dielectric region will reduce capacitance thus increasing circuit performance. Metal oxide layer 20 can be formed from any material which is an electrical insulator such as a refractory metal oxide or an aluminum oxide. Layer 20 will typically have a thickness of approximately 5000 angstroms. Additionally, metal oxide layer 20 and its etch chemistry should be chosen such that layer 20 may be selectively etched over the underlying interlevel dielectric layers 16 and 18. Similarly, the interlevel dielectric layers 16 and 18 and their etch chemistries should be chosen such that they etch at substantially the same rate and may be selectively etched over the material chosen for the underlying metal layer 12. A photoresist layer 22 is formed over the device and patterned to define a contact opening or via 24 in which a contact will be made to the underlying metal region 12. The exposed portion of the metal oxide layer 20 is then selectively etched away within the via 24 without removing significant portions of the underlying interlevel dielectric layers 16 and 18. Referring to Figure 4, the interlevel dielectric layers 16 and 18 are etched in the via 24 to expose a portion of the metal region 12. The dielectric layers 16 and 18 will etch away within the via 24 at substantially the same rate and will overetch to a depth slightly lower than the upper surface of the metal region 12. As shown in Figure 4, misalignment of the via 24 is not critical where the interlevel dielectric layers are substantially planar. The interlevel dielectric layer 16 will not be etched such that penetration of the junction between layer 16 and the underlying region 10 occurs. Referring to Figure 5A, photoresist layer 22 is removed. A second conductive layer 26 is then formed over the metal oxide layer 20 and in the via 24. Layer 26 will typically have a thickness of between approximately 5000 to 8000 angstroms and will form the upper layer of an interconnect with the first conductive region 12. Since there is no etching through the junction between layer 16 and region 10, no short circuit condition will occur and there will be no leakage current as a result of the formation of the interconnect. Referring to Figure 5B, an alternative process is to first selectively etch the metal oxide layer 20. With this alternative, there is no etch back performed to thin out the interlevel dielectric layers 16 and 18 before the deposition of the metal oxide layer 20. Referring to Figure 6A, the via 24 may be larger than the metal region 12. Again, selectively etching the metal oxide layer 20 and then layers 16 and 18 on top of the metal region 12 will ensure that there is no overetching into region 10. The metal layer 26 which forms the upper layer of the interconnect with metal region 12 will not cause any short circuit conditions or leakage current. Figure 6B illustrates the same conditions but without the etch back step of layer 18. It will be appreciated by those skilled in the art that the method described above, and the structures formed thereby, provide for an interconnect which prevents short circuit and leakage current conditions. This technique does not allow for the etch of the interlevel dielectric layers to go deep into region 10. Misalignment of the via over the metal layer 12 can thus be tolerated allowing for a higher density of device fabrication. This technique further provides an interconnect layer which can be easily used to form multiple levels of metal interconnect without creating severe topographical features which make formation of later interconnect levels difficult.

Claims: A method of forming a contact structure of an integrated circuit device, comprising the steps of: forming a lower metal interconnect structure (12,14) over an underlying surface (10); forming a lower, plasma oxide layer (16) over the lower interconnect structure (12,14) and the underlying surface (10); planarizing the thus obtained surface by forming a planarizing insulating layer (18) over the lower oxide layer (16); forming an upper oxide layer (20) over the lower oxide layer (16) and the planarizing layer (18); forming an opening (24) through the lower oxide, planarizing insulating and upper oxide layers (16,18,20) to expose a portion of the lower interconnect structure (12,14) in the bottom thereof; and forming an upper metal interconnect layer (26) over the upper oxide layer (20) and in the opening (24) contacting the lower interconnect structure (12,14); characterized in that the upper oxide layer (20) is formed from a metal oxide, and in that the step of forming an opening comprises the steps of selectively etching the upper oxide layer (20) to form a via (24) and selectively etching the lower oxide layer (16) and any exposed planarizing layer (18) in the via to expose a portion of the lower interconnect structure (12,14), in that a portion of the bottom of the opening (24) exposes a portion of the lower oxide layer (16), and in that the upper interconnect layer (26) lays over and contacts the exposed portion of the lower oxide layer (16) in the opening (24). The method of claim 1, wherein said selective etching to expose the lower interconnect structure comprises etching through the planarizing layer and lower oxide layer. The method of claim 1, wherein said step of planarizing the obtained surface comprises the steps of: depositing a planarizing insulating layer over the lower oxide layer; performing an etchback of the planarizing layer to expose first portions of the lower oxide layer, said first portions and the remaining planarizing layer forming a substantially planar surface wherein said selective etching to expose the lower interconnect structure comprises etching through the first portions of the lower oxide layer. The method of any preceding claim, further comprising the step of forming and patterning a photoresist layer (22) over the metal oxide layer (20) prior to the selective etching steps, and the step of removing the photoresist layer (22) after the selective etching steps. The method of any preceding claim, wherein the lower interconnect structure (12,14) contains aluminium. The method of any preceding claim, wherein the lower interconnect structure (12,14) contains a refractory metal. The method of any preceding claim, wherein the planarizing layer (18) is formed of a spin-on-glass. The method of any preceding claim, wherein the metal oxide layer (20) is formed of a refractory metal oxide. The method of any one of claims 1 to 7, wherein the metal oxide layer (20) is formed of an aluminium oxide. The method of any preceding claim, wherein the etch rate of the lower oxide layer (16) and planarizing layer (18) are substantially the same. The method of any preceding claim, wherein the underlying surface (10) is an active region. The method of claim 11, wherein the active region is a source/drain region of a transistor. The method of claim 11, wherein the active region is a gate electrode of a transistor. The method of any one of claims 1 to 10, wherein the underlying surface (10) is a dielectric layer. A contact structure of an integrated circuit device, comprising: a lower metal interconnect structure (12,14) disposed over an underlying surface (10); a lower, plasma oxide layer (16) disposed over the lower interconnect structure (12,14) and the underlying surface (10); a planarizing insulating layer (18) disposed over at least a portion of the lower oxide layer (16), wherein the planarizing layer (18) has an etch rate approximately the same as the etch rate of the lower oxide layer (16); an upper oxide layer (20) disposed over the planarizing layer (18) and the lower oxide layer (16); an opening (24) extending through the lower oxide, planarizing insulating and upper oxide layers (16,18,20) to expose a portion of the lower interconnect structure (12,14) in the bottom thereof; and an upper metal interconnect layer (26) which contacts the lower interconnect structure (12,14) in the bottom of the opening (24); characterized in that the upper oxide layer (20) is formed from a metal oxide whereby the upper oxide layer (20) can be selectively etched over the lower oxide layer (16) and the planarizing layer (18) and the lower oxide layer (16) and the planarizing layer (18) can be selectively etched over the lower interconnect structure (12,14), a portion of the bottom of the opening (24) exposes a portion of the lower oxide layer (16), and in that the upper interconnect layer (26) lays over and contacts the exposed portion of the lower oxide layer (16) in the opening (24). The structure of claim 15, wherein the underlying surface (10) is an active region. The structure of claim 16, wherein the active region is a source/drain region of a transistor. The structure of claim 16, wherein the active region is a gate electrode of a transistor. The structure of claim 15, wherein the underlying surface (10) is a dielectric layer. The structure of claim 15, wherein the metal oxide comprises a refractory metal oxide. The structure of claim 15, wherein the metal oxide comprises aluminium oxide. The structure of claim 15, wherein the planarizing layer (18) covers the lower oxide layer (16), and has thinner portions over higher topographical features of the lower oxide layer (16) and thicker portions over lower topographical features of the lower oxide layer (16). The structure of claim 15, wherein the planarizing layer (18) covers less than all of the lower oxide layer (16), and is not formed over higher topographical features of the lower oxide layer (16), instead forming pockets of planarizing material which fill in lower topographical features of the lower oxide layer (16). The structure of claim 15, wherein the opening (24) further exposes a portion of the planarizing layer (18). The structure of claim 15, wherein the opening (24) is wider than a width of the lower interconnect structure (12,14) at the location of the opening (24).

Inventors: CHEN FUSEN E, DIXIT GIRISH A, LIOU FU-TAI, CHEN, FUSEN E., DIXIT, GIRISH A., LIOU, FU-TAI
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS, INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L23