Non-volatile electrically erasable semiconductor memory devices

Abstract: An electrically programmable and electrically erasable non-volatile semiconductor memory device having an array (1a) of single transistor cells (C mn ). The device provides protection against reading faults even in the event that adjacent transistors are over-erased. Each of the cell transistor rows (C m1 to C mj ) has an associated word line (WL m ) and an associated select element (SG 1m ). The select elements (SG 1m ) are connected to the sources of their associated cell transistors (C m1 to C mj ) and are arranged to activate those cell transistors only when their associated word lines are selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over-erased condition.

Description: The present invention relates generally to non-volatile electrically erasable semiconductor memory devices. Recently, personal computers have become popular due to their ability to deliver good computing performance at affordable prices. Although present computers are quite powerful and efficient, there are continuing efforts to increase their performance by increasing speed and reducing costs. One traditional source of time delays in computing systems has been the amount of time required to access auxiliary memory devices. In particular, the magnetic disc auxiliary memory devices are considered to be quite slow. Therefore, there is a tendency for semiconductor memory devices to be used as auxiliary memory devices. Most of the semiconductor memory devices presently available for use as auxiliary memory devices are DRAMs (SRAMs are seldom used). However, if power is cut off, data stored in a DRAM will be erased. Therefore, DRAMs require backup batteries, which is disadvantageous. Because of the above drawbacks of the most popular auxiliary memory devices, EEPROMs (electrical erasable programmable read only memories), which are electrically programmable, are now being proposed for use as auxiliary semiconductor memory devices. Traditional EEPROMs require two transistors per cell. However, such EEPROMs suffer the drawback of requiring a relatively large area per cell, which in turn results in higher fabrication cost. The use of all-erase (flash-erase) EEPROMs whose cell area is similar in size to ultraviolet-erasable EEPROMs (erasable programmable read only memories) is being reviewed. A single transistor EEPROM cell in the form of a tunnel-erase/avalanche-write cell transistor C is shown schematically in Fig. 13. This transistor C has a double-gate structure including a control gate and a floating gate. As seen in Fig. 14, when data "0" is to be written into such a cell transistor, a high-voltage V pp is applied to both the drain and the control gate while the source is connected to ground GND. With this arrangement, electrons are injected into and charge accumulates in the floating gate. After the data "0" has been written by this operation, the cell transistor C operates as indicated by a characteristic curve DO shown in Fig. 12. Accordingly, when a 1/0 determination voltage V 0/1 or a cell select signal is applied to the control gate, no current (I DS ) flows between the drain and the source. Thus, the cell transistor C is effectively "off". As shown in Fig. 13, in order to erase the written data "0", the drain is opened, the control gate is connected to ground GND, and a high-voltage V pp is applied to the source. This removes the charge from the floating gate. The cell transistor C, after the data erase, operates as indicated by a characteristic curve D1 in Fig. 12. Thus, the cell transistor C is turned "on" when the 1/0 determination voltage V 0/1 is applied to the control gate. The condition where a transistor C is turned "on" when subjected to the 1/0 determination value is read as data "1" in that transistor. An example of a conventional cell array consisting of cell transistors of this type will be explained below with reference to Fig. 11. A similar array on which the two part form of claims 1 and 11 is based in known from IEEE Journal Of Solid-State Circuits, vol. 24, no.5, October 1989, pages 1250-1258. The cell transistors C of each row have their control gates commonly connected to a word line WL m . For example, a word line WL 1 is commonly connected to the control gates of cell transistors C 11 to C 1j . The multiple cell transistors C of each column have their drains commonly connected to a bit line BL n . Every cell transistor C has its source connected to ground GND. A voltage V cc is applied to the bit lines BL 1 to BL j through load resistors R2 1 to R2 j , for example, in order to steadily set the potentials of the cell transistors depending on whether data is written in the cell transistors. When one word line and one bit line are selected from among the lines WL 1 to WL i and BL 1 to BL j , respectively, a single cell transistor is selected. Specifically, the selected cell is the cell C mn where the selected work line WL m and selected bit line BL n cross each other. If the data "O" is stored in the cell transistor C mn , the cell transistor C mn is turned "off" and the selected bit line BL n becomes a high level. On the other hand, if the data "1" is stored in the cell transistor C mn , the cell transistor C mn is turned on, and the selected bit line BL n becomes a low level. The potential of the bit line is then read out as cell information by a sense amplifier. The inventors have recognised a drawback of this arrangement, as follows. If too many electrons are removed from the floating gate of a cell transistor C while erasing the data "0", this cell transistor C will be "over-erased". In the over-erased condition, the cell transistor C operates according to a characteristic curve D1 0 as shown in Fig. 12. That is, it now has a negative threshold voltage, and will thus always be in a depletion condition such that it is always effectively "on". When a particular cell transistor C is in an over-erase condition, the potential of the bit line BL connected to that cell transistor C will always be low. Thus, if another cell transistor C connected to the same bit line BL is selected, its cell information cannot be read out, thereby causing a reading failure. One possible way of overcoming this shortcoming would contemplate an erasing method which repeats electrical erasing and data reading until the threshold value of the erased cell transistor becomes a certain value while checking to insure that the threshold value does not fall negative. However, this method would require a considerable amount of CPU and bus time to control the erasing operations, which would undesirably decrease the operation speed of a computer system. The invention is defined by a device according to claim 1 and a method according to claim 11. An embodiment of the present invention can provide a non-volatile semiconductor memory device which has a cell array consisting of tunnel-erase/avalanche-write cell transistors with a double-gate structure including a floating gate, and for which reading failure is prevented even when a cell is over-erased. In an embodiment of the present invention, an electrically programmable and electrically erasable non-volatile semiconductor memory device is provided which includes a cell array having a plurality of electrically erasable and programmable non-volatile cell transistors arranged in rows and columns. Each cell transistor includes a source, a drain and a control gate. Each of the cell transistor rows has an associated word line. The word lines are connected to the control gates of each of their associated cell transistors. Each cell transistor column has an associated bit line. Thus, the word lines and bit lines are arranged such that any one of said cell transistors can be selected for writing or reading cell information by selecting its associated word and bit lines. Each row also has an associated first select element that is connected to the sources of its associated cell transistors. The first select elements are arranged so as to activate a selected cell transistor in synchronism with the selection of the word lines with which the selected transistor is associated, by electrically connecting the sources of the cell transistors associated with the relevant row to a first power supply when their associated word line is selected. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a schematic diagram illustrating a first embodiment of the present invention; Fig. 2 is a schematic diagram illustrating a second embodiment of the present invention; Fig. 3 is a circuit diagram illustrating sections of a semiconductor memory device using a cell array in accordance with the second embodiment of this invention; Fig. 4 is a schematic diagram illustrating a third embodiment of the present invention; Fig. 5 is a circuit diagram illustrating sections of a semiconductor memory device using a cell array in accordance with the third embodiment of this invention; Fig. 6 is a schematic diagram illustrating a fourth embodiment of the present invention; Fig. 7 is a block diagram showing memory control circuitry of a semiconductor memory device using a cell array in accordance with the fourth embodiment of this invention; Fig. 8 is a timing diagram showing output levels of various signals in the memory control circuitry shown in Fig. 7, in the read mode; Fig. 9 is a timing diagram showing output levels of various signals in the write mode; Fig. 10 is a timing diagram showing output levels of various signals in the erase mode; Fig. 11 is a circuit diagram showing a conventional cell array; Fig. 12 is a graph showing characteristics of cell transistors of a tunnel-erase EEPROM; Fig. 13 is a schematic diagram of a cell transistor illustrating voltages applied to the cell transistor to erase data therein; and Fig. 14 is a schematic diagram of a cell transistor shown in Fig. 13, illustrating voltages applied to write data therein. A first embodiment of the present invention will be explained with reference to Fig. 1. A cell array 1 comprises a plurality of electrically erasable and programmable non-volatile cell transistors C ij arranged in rows and columns. The cell transistors C mj of each row are connected to a common word line WL m , and the cell transistors of each column are connected to a common bit line BL n . By selecting one of the word lines WL m and one of the bit lines BL n , a single cell transistor C mn is selected for write-in or for read-out of cell information. A common first select element E1 m for activating a row of cell transistors C mj is connected to the sources of each of the cell transistors C mj in the particular row concerned. When activated, the first select element E1 m electrically connects the sources of the cell transistors C mj to a power supply V S1 (e.g. ground). The first select element E1 m is turned on by a first select signal SG1 m which is sent in synchronism with the selection of the word line WL m that selects that row. In alternative embodiments to be discussed in more detail below, a second power supply V S2 may be provided for deactivating the cell transistors C mj when the first select element E1 m is inactive. In one such embodiment, as seen in Fig. 2, the second power supply may be coupled to the sources of a row of cell transistors C mj through an associated resistor R1 m , as a regulating element. In another such embodiment, as shown in Fig. 4, each row of cell transistor sources may be coupled to the power supply V S2 through an associated second select element E2 m , as a regulating element. In this latter embodiment, the second select element E2 m is a transistor having its gate supplied with a second select signal SG2 m , which is synchronised with the first select signal SG1 m . When the m-th word line WL m is selected, the first select element E1 m corresponding to that word line WL m is turned "on", thereby activating the cell transistors C mj connected to the corresponding word line WL m . If the n-th bit line BL n is then selected in this condition, cell information is only read from the selected cell transistor C mn on to the bit line BL n . On the other hand, when the word line WL m is not selected, the first select element E1 m associated with that word line is turned "off". Accordingly, the sources of the cell transistors C mj in the unselected row are not grounded, thus these cell transistors C mj are deactivated. Indeed, in the embodiments shown in Figs. 2 and 4 the sources of the cell transistors C in non-selected rows are coupled to power supply V S2 , which ensures deactivation. The second embodiment of the present invention will now be described in detail with reference to Figs. 2 and 3. A cell array 1a shown in Fig. 2 includes a multiplicity of cell transistors C 11 to C ij provided in i rows and j columns. The rows of cell transistors have their control gates respectively connected to word lines WL 1 to WL i , and the columns of the cell transistors have their drains connected respectively to the bit lines BL 1 to BL j . The sources of the cell transistors in each row (1-i) are connected to an associated first select element E1 1-i . In this embodiment, the first select elements are N-channel MOS transistors E1 1 to E1 i . Therefore, the sources of the cell transistors C mj of each row are each connected to the drain of the associated first select element transistor E1 m . The sources of the cell transistors are powered by V S2 through resistors R1 1 to R1 i . The first select signals SG1 1 to SG1 i , which are synchronised with the selection of the corresponding word lines WL 1 to WL i , are sent to the gates of the select transistors E1 1 to E1 i , respectively. The sources of the select transistors E1 1 to E1 i are connected to the power supply V S1 . That is, grounded in this embodiment. In the cell array 1a with this arrangement, when the word line WL 1 is selected, for example, a cell select signal is sent to the control gates of the cell transistors C 11 to C 1j . A select signal SG1 1 is input to the gate of the select transistor E1 1 (only) in synchronism with the input of the cell select signal, thereby turning the select transistor E1 1 on. Accordingly, the potentials of the sources of the cell transistors C 11 to C 1j drop to ground level. When the bit line BL 1 is selected under these conditions, the cell transistor C 11 is selected and cell information is read from that cell transistor on to the bit line BL 1 . If data "0" is written in the cell transistor C 11 , the cell transistor C 11 is turned off and the bit line BL 1 is "high". On the other hand, if data "1" is written in the cell transistor C 11 , the cell transistor C 11 is turned on, which sets the bit line BL 1 at a low level. It is noted that only the select element associated with the selected word line is turned on. Thus, in the example above, only the select transistor E1 1 would be turned on while the remaining transistors remain off. Therefore, even if one of the other cell transistors C 21 to C i1 connected to the bit line BL 1 is over-erased such that it is always "on", the source of the over-erased cell transistor(s) is not grounded. Accordingly, the information in the cell transistor C 11 can be read without interference from the over-erased transistor. Thus, with the described arrangement, cell information can always be read from the selected cell transistor even if one of the cell transistors in the cell array 1a is over-erased. A peripheral circuit suitable for accomplishing the data writing, data reading and data erasing functions in co-operation with the above-described cell array 1a will now be functionally described with reference to Fig. 3. In order to simplify this explanation, the cell array 1a for this example is a simple 2 x 2 matrix. Thus, the address bus in Fig. 3 includes a single word-line select signal input terminal AØ and a single bit-line select signal input terminal A1. Reference numerals "2a" to "2g" denote AND gates, "Tr1" to "Tr6" N-channel MOS transistors, and "3a" an inverter. The terminal V S1 of the cell array 1a is connected to the ground GND, and to the sources of the select transistors E1 1 to E1 i in the cell array 1a. The AND gates 2b and 2c output a high-voltage V pp to write data in the cell transistors, while the AND gates 2f and 2g output the high-voltage V pp when erasing data. As seen in Fig. 3, components such as AND gate 2a and other components that output V cc level signals are marked by single bar power supplies. Components that are marked by a double bar power supply, such as AND gates 2b and 2c, output V cc or V pp level signals depending on the EEPROM's mode. Components that are marked by triple bar power supplies, such as AND gates 2f and 2g output V pp level signals. In a data reading mode, an erase signal E and a write signal W as seen in Fig. 3 are both "high". In this condition, the AND gate 2a outputs a high-level signal, which turns the transistor Tr2 "on". At the same time, the output signal of the inverter 3a (which is connected to the erase signal line E ) is "low", which turns the transistor Tr1 off. Accordingly, a bias voltage B which is set to provide the desired 0/1 determination voltage is supplied to the power supply terminal V S2 of the cell array 1a (and/or set to provide for deactivation of cells on the non-selected word line). When reading data, the data address is supplied to the address lines AØ and A1. In this simplified embodiment, the AØ line contains the word line information, while the A1 line contains the bit line information. Thus, the first word line can be selected by sending a high signal to terminal AØ. Specifically, when the address signal AØ is high, the output signal of the AND gate 2b is also high since the second input of the AND gate 2b is connected to the erase line. At the same time, the output signal of the AND gate 2c is at a low level. This effectively selects the word line WL 1 which is now at a high level, that is, V pp . At the same time, a high-level select signal to SG1 1 is sent to the gate of the first select transistor E1 1 , thereby turning on the first select transistor as discussed previously. At the same time, the selected bit line information is transferred over address line A1. Again, in this simplified example, the first bit line can be selected merely by making the address signal A1 high. Specifically, when a high signal A1 is sent, the output signal of the AND gate 2d becomes high and the output signal of the AND gate 2e is low. Consequently, the transistor Tr3 is turned on to select the bit line BL 1 by connecting the bit line BL 1 to a sense amplifier 4. The cell information of the selected cell transistor is then amplified by the sense amplifier 4 to output a signal as an output signal D out . It is therefore possible to read out cell information of the cell transistor selected according to the address signal. In order to write data, a high-level erase signal E and a low-level write signal W are input. In this mode, the low-level write signal makes the output of the AND gate 2a low. At the same time the inverter 3a is also low since the erase signal is high. Accordingly, both the transistors Tr1 and Tr2 are off. No voltage is therefore supplied to the power supply terminal V S2 of the cell array 1a. If the address signal for cell C 11 is input, line AØ is high. Accordingly, the AND gate 2b outputs a high-voltage V pp for data writing. This high-voltage signal is supplied from the AND gate 2b to the word line WL 1 and the gate of the select transistor E1 1 . The voltage V pp is therefore applied to the control gates of all of the cell transistors C 11 to C ij connected to the word line WL 1 . At the same time, a high-level select signal SG1 1 is sent to the gate of the first select transistor E1 1 , thereby turning on the first select transistor which connects the sources of the first line cell transistors to ground GND. At the same time, the output signals of the AND gates 2d and 2e are low due to the low-level write signal W . When a high-level input data D in is input to the AND gates 2f and 2g, one of the AND gates 2f and 2g becomes a high-level, and the other a low-level, permitting the voltage V pp to be supplied via the transistor Tr5 or Tr6 to either bit line BL 1 or BL 2 . The selected cell transistor therefore has control gate and drain supplied with the voltage V pp , and source connected to the ground GND, so that data is written there. As a voltage V cc is applied as an input signal to the sense amplifier 4 through the resistor R2, the output signal will be fixed at a high level. When an erasing operation is performed, the erase signal E is set at a low level. Consequently, the output signal of the AND gate 2a is low, and the output signal of the inverter 3a becomes high. The high-voltage V pp is thus applied to the voltage supply terminal V S2 in the cell array 1a. The output signals of the AND gates 2b to 2g are all low regardless of the address signals AØ and A1, and the input data D in , rendering the transistors Tr3 to Tr6 off. The individual cell transistors in the cell array 1a therefore have their drains open, the control gates supplied with a low-level signal, and the sources supplied with the high voltages V pp . Accordingly, data is erased from each of the cell transistors at the same time. Although the peripheral circuitry has been described as applied to a simple cell matrix, it will be readily apparent to those skilled in the art how the peripheral circuitry can be arranged to apply to practically-sized EEPROMs. The third embodiment of the present invention will now be described referring to Figs. 4 and 5. The layout of the third embodiment is very similar to the layout of the second embodiment. Accordingly, where appropriate, similar reference signs are used to designate similar components. The cell array, 1b in this embodiment, has P-channel MOS transistors E2 1 to E2 i as its second select elements (regulating elements) in place of the resistors R1 1 to R1 i of the cell array 1a in the second embodiment. Select signals SG2 1 to SG2 2 are sent to the gates of the respective second select transistors E2 1 to E2 i . Again, an appropriate peripheral drive circuitry will be explained as applied to a 2 x 2 cell matrix, in order to simplify explanation. A suitable peripheral drive circuit is shown in Fig. 5. Reference signs "Tr7" and "Tr8" denote N-channel MOS transistors, "2h" and "2i" AND gates, "5a" and "5b" OR gates, "3b" an inverter, and "6a" a NAND gate. The bias voltage B is always supplied to the terminal V S2 of the cell array 1b, and is thus connected to the sources of the select transistors E2 1 to E2 i . To read data from cell array 1b, the erase signal E and the write signal W are set high. Thus, the transistor Tr7 is turned off and the transistor Tr8 on. The potential at the ground (GND) level is thus supplied to the terminal V S1 of the cell array 1b, and the sources of the select transistors E1 1 to E1 i have the ground potential in the cell array 1b. Since the NAND gate 6a outputs a low-level signal, the select transistors E2 1 to E2 i are rendered on in the cell array 1b, thereby supplying the bias voltage B to the sources of the individual cell transistors. If the address of cell C 11 is applied to the address lines, the levels of the address signals AØ and A1 are each. high. Thus, the output signals of the AND gate 2h and the OR gate 5a are both "high". At the same time, the output signals of AND gate 2i and OR gate 5b are both "low". Accordingly, the word line WL 1 is selected and a select signal SG1 1 is sent to the select transistor E1 1 associated with that word line WL 1 . As a result, the cell transistors C 11 to C ij are activated and the select transistor E1 1 is turned on, setting the sources of the individual cell transistors C 11 to C ij at the ground level. The output signal of the AND gate 2d becomes high, and those of the AND gates 2e to 2g become low, which turn the transistor Tr3 on. Consequently, the bit line BL 1 is selected which combines with selected word line WL 1 to select the cell transistor C 11 . The cell information of that cell transistor C 11 is then read out via the bit line BL 1 , and is amplified by the sense amplifier to be an output signal D out . At this time, the select transistors E1 2 to E1 i are off. Therefore, even if one or more of the other cell transistors C 21 to C i1 connected to the bit line BL 1 is in an over-erase condition, reading cell information from the cell transistor C 11 is not affected at all. Cell information of other cell transistors can likewise be read out based on the address signal. Meanwhile, when an erasing operation is performed, the erase signal E is set at a low level, so that the transistor Tr7 is turned on to supply the high-voltage V pp to the terminal V S1 of the cell array 1b. The output signals of the OR gates 5a and 5b become a high-level, while the output signals of the AND gates 2d to 2i all become low. Data erasing is thus executed in the individual cell transistors in the cell array 1b. In writing data, the erase signal E becomes high and the write signal W low. The ground potential is then supplied to the terminal V S1 of the cell array 1b. One word line WL is selected by the address signal AØ, and one bit line BL is selected by address signal A1. When the level of the input data D in becomes high, the high-voltage V pp is applied to the selected bit line BL. As a result, the high-voltage V pp is supplied to the drain and gate of the selected cell transistor in the cell array 1b, with the ground potential supplied to the source of that cell transistor, allowing data to be written there. Next, a cell array in accordance with a fourth embodiment of the present invention will be described referring to Figs. 6 to 10. As shown in Fig. 6, a first power supply V S1 is connected to the sources of cell transistors C in each row through a corresponding N-channel MOS transistor (a first select element E1 m ). A second power supply V S2 is connected to sources of cell transistors C in each row through a P-channel transistor (a second select element E2 m ). When a word line WL m is selected, a select signal SG1 m is input into both of the corresponding select elements E1 m to E2 m . According to this signal SG1 m , the first select element E1 m is turned on and the second select element E2 m is turned off. Then, the sources of the cell transistors C m1 to C mj are electrically connected to the power supply V S1 . When the word line WL m is not selected, the first select element E1 m is turned off and the second select element E2 m is turned on in accordance with the signal SG1 m . Therefore, the sources of the cell transistors C m1 to C mj are electrically connected to the power supply V S2 . With this arrangement, the potential of the non-selected cell transistors and the potential of bit line are maintained at substantially the same level and are thus deactivated. A semiconductor memory device using the cell array shown in Fig. 6 will be described referring to Fig. 7. The device has a voltage detector 21, a state control circuit 22, a program/erase voltage switch 23, an input/output buffer 24, an X-decoder 26, a Y-decoder 25, a Y-gate 27 and an amplifier 28. The voltage detector 21 judges whether a high-voltage V pp is available. If so, the voltage detector outputs a "high" signal V hh to the state control circuit 22. If not, a "low" V hh signal is output. The state control circuit 22 receives a chip enable signal CE , a write enable signal WE and an output enable signal OE in addition to the signal V hh . From these signals, the desired mode can be determined. For example, the read, write and erase modes can all be determined. In response to these signals, the state control circuit 22 outputs an output control signal O , an input control signal I , an erase signal E , a write control signal W and a read signal R . For example, when the read mode is set, the state control circuit 22 receives a "low" chip enable signal CE , a "low" output enable signal OE and a "high" write enable signal WE . At the same time, the voltage signal V hh is "low". In turn, the state control circuit provides "low" output control O and read R signals. When the write mode is set, the state control circuit 22 receives a "high" voltage signal and a "high" output enable signal OE . At the same time, the chip enable signal CE and the write enable signal WE are "low". In turn, the state control circuit outputs a "low" input control signal I and a "low" write signal W . When the erase mode is set, the state control circuit 22 outputs a "low" erase signal E . This is done in response to the input of a "high" voltage signal V hh , a "high" chip enable signal CE , a "high" output enable signal OE and a "low" write enable signal WE . When the program/erase voltage switch 23 receives a "low" erase signal E , it switches the voltage of the cell array power supply V S1 to the high-voltage V pp . When a "low" erase signal or a "low" write signal is input, the switch 23 switches an output-voltage V per into the high-voltage V pp . This voltage is supplied to the Y-decoder 25. When a declining step input control signal I is received by the input/output buffer 24, the buffer latches input data D in that is received from an external device. The input data is then output to the cell array. In contrast, when a declining step output control signal O is received, the buffer 24 latches output data D out from the cell array, and then outputs the data to the external device. The X-decoder is arranged to receive the address signals A m (m = 0 to 9), the write signal W , the read signal R and the erase signal E . In response to these inputs, the X-decoder 26 outputs a select signal SG1 m ("high"-level) to the cell array in order to select the desired word line WL m . At the same time, a "high"-level signal is sent to the selected word line WL m . The Y-decoder 25 is arranged to receive the address signals A n (n = 10 to 16), the write signal W and the read signal R . In response to these inputs, the Y-decoder 25 outputs a bit line control signal CL n to a Y-gate. The Y-gate 27 selects the bit line BL n in order to read and write data responding to the bit line control signal CL n . More specifically, in the write mode (i.e. when the write signal W is"low"), a high-voltage V pp is supplied to the selected bit line BL n . Then, the input data D in is input into the bit lines from the buffer 24. In the read mode (i.e. when a "low" read signal R is input into the Y-gate 27), the selected bit line BL n is connected to an amplifier 28. Then, the cell information is output from the amplifier 28 as the output data D out . Fig. 8 is a timing diagram showing the output levels of various signals in the read mode. In the Figure, the letter "L" indicates "low" while the letter "H" indicates "high". The set signals include:- V hh = L, V per = V cc , V S1 = ground, V S2 = V cc , E = H, W = H and I = L. In this state, the write enable signal WE and the address signal are input into the state control circuit 22, X and Y decoders 25 and 26 respectively. For the purposes of illustration, we will assume that the desired cell transistor is C 11 . In this condition the chip enable signal CE is shifted "low", which causes the read signal R to shift "low". Accordingly, a select signal SG1 m (SG1 1 ) having a voltage level of "V cc " is input into the select elements E1 m and E2 m which correspond to the address signal (in this case, E1 1 and E2 1 ). Thus, the first select element E1 m (E1 i ) turns on and the second select element E2 m (E2 1 ) turns off. Therefore, the select signal SG m having a voltage-level of "V pp " level is input into the both select elements E1 m and E2 m . In this condition, the first select element E1 m turns on while the second select element E2 m turns off. Then, one word line WL m (WL 1 ) is selected. Accordingly, the source of each cell transistor in the selected word line WL m (WL 1 ) is connected to the power supply V S1 and the potentials thereof shift to ground level. In response to the input of the address signal, the bit line control signal CL n (C L1 ) which corresponds to the address signal shifts to the "V cc " level. Then, the corresponding bit line BL n (BL 1 ) is selected. Accordingly, the data from the cell transistor C mn (C 11 ) specified by the address is read. Thus, when both of the output enable signal and the output control signal shift to a "low" level, the information in the cell transistor C mn (C 11 ) is output as the output signal D out . In the above case, even if one or more of the non-selected cell transistors is over-erased, only the first select element will be turned on. Therefore, the operation of reading the information in a selected cell transistor is not affected by over-erased transistors. Fig. 9 is a timing diagram showing the output levels of various signals in the write mode. In the write mode, the output levels of various signals are set as follows:- V hh = H, V S1 = ground, V S2 = open, OE = H, E = H, R = H and O = H. In the above state, the address signal, a "low" chip enable signal CE and a "low" output control signal O are input into the appropriate circuits. Thereafter, the voltage signal V per switches to the "V pp " level, and the write enable signal WE and the write signal W shift to "low" levels. Accordingly, the word line WL m that corresponds to the address signal is selected. Additionally, a select signal SG1 m at a "V pp " level is input into the select elements E1 m and E2 m which correspond to the selected word line. Thus, the associated first select element E1 m is turned on and the associated second select element E2 m is turned off. This insures that the source of each cell transistor in the selected word line is connected to the power supply V S1 , which in this case is at ground level. In response to the address signal, the bit line control signal CL n which corresponds to the address signal shifts to the "V pp " level. Therefore, one bit line BL n is selected. Accordingly, one cell transistor C mn is specified, and then, the input data D in are programmed into the cell transistor C mn . Fig. 10 is a timing diagram showing the output levels of various signals in the erase mode. The output levels of various signals are set as follows:- V hh = H, CE = H, OE = H, V S2 = open, W = H, R = H, O = H, I = H, WL 1 = ground, CL j = ground and D out = H. In this above state, the voltages V per and V S1 are shifted to the "V pp " level. The write enable signal WE at a "low" level and the erase signal E at a "low" level are input. Therefore, the select signals SG i at "V pp " levels are input into all select elements E1 i and E2 i , all of the first select elements E1 i are turned on and all of the second elements E2 i are turned off. In this case, since each of the word lines and each of the bit line control signals are fixed at the ground levels, all of the sources of the cell transistors are connected to the power supplies V S1 through the first select elements. Thus, the voltage in "V pp " level is applied to each of the sources. Accordingly, the information in all of the cell transistors is erased simultaneously. As described above, an electrically erasable and electrically programmable non-volatile semiconductor device according to an embodiment of the present invention has a cell array comprised of tunnel-erase cell transistors with a double-gate structure including a floating gate. The semiconductor memory device is excellent in preventing reading failure even if a cell transistor is in an over-erase condition. An embodiment of the present invention provides an electrically programmable and electrically erasable non-volatile semiconductor memory device having an array of single transistor cells. The device provides protection against reading faults even in the event that adjacent transistors are over-erased. Each of the cell transistor rows has an associated word line and an associated select element. The select elements are connected to the sources of their associated cell transistors and are arranged to activate those cell transistors only when their associated word lines are selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over-erased condition.

Claims: An electrically programmable and electrically erasable non-volatile semiconductor memory device including:- a cell array (1) having:- a plurality of electrically erasable and electrically writable non-volatile cell transistors (C ij ) arranged in rows and columns, each cell transistor (C ij ) including a source, a drain, a control gate and a floating gate; a plurality of word lines (WL m ) each associated with a particular one of said cell transistor rows and being connected to the control gates of each of its associated cell transistors (C mj ); and a plurality of bit lines (BL n ) each associated with a particular one of said cell transistor columns, such that any one of said cell transistors (C mn ) can be selected for writing or reading cell information by selecting the word line (WL m ) and the bit line (BL n ) associated with the selected cell transistor (C mn ), and further comprising:- switching means (E1) for alternatively supplying first and second potentials to the sources of said cell transistor (C mn ), said switching means (E1) being arranged such that during reading operations, the sources of transistor cells in a selected row are supplied with said first potential to permit reading of those transistor cells characterized in that the sources of transistor cells in unselected rows are supplied with said second potential to ensure that their associated transistor cells remain off during the read operations. A device as claimed in claim 1, wherein said switching means includes a plurality of select element (E1 m ) each connected to the sources of the cell transistors in an associated row of said cell transistor array, and each arranged to be activated in synchronism with the selection of its associated word lines (WL m ) to electrically connect the sources of its associated cell transistors (C mj ) to a first power supply (V S1 ) when its associated word line is selected. A device as claimed in claim 2, wherein the switching means further includes a plurality of regulating elements (R1 m ) each being associated with a particular row of said cell transistors and each for electrically connecting its associated cell transistors to a second power supply (V S2 ) having a potential different than said first power supply, when its associated word line is not selected. A device as claimed in claim 3, wherein said regulating elements are resistors (R1 m ). A device as claimed in claim 3, wherein said regulating elements are regulating transistors (E2 m ). A device as claimed in claim 5, wherein said regulating elements are P-channel type MOS transistors (E2 m ). A device as claimed in any one of claims 2 to 6, wherein each of the select elements is an N-channel type MOS transistor (E1 m ), a gate of each such MOS transistor being connected to its associated word line, a drain of each such MOS transistor being connected to the sources of each of the cell transistors in its associated word line, and a source of each such MOS transistor being connected to the first power supply (V S1 ). A device as claimed in claim 6, wherein each regulating element is activated by the same signal as activates the first select element (E1 m ) associated with the same word line (WL m ). A device as claimed in any preceding claim, further comprising means (25, 26) arranged to select the word line and the bit line associated with a selected transistor cell, to permit reading of information from and writing of information to any selected one of said transistor cells. A device as claimed in any preceding claim, wherein the first potential is ground potential. A method of reading information from an electrically programmable and electrically erasable non-volatile semiconductor memory device, the device comprising:- a cell array (1) formed from single transistor cells (C ij ) each having a source, a drain, a control gate and a floating gate, the cell array being divided into a multiplicity of rows and columns, each row having an associated word line (WL m ) connected to the control gates of the transistor cells (C mj ) in that row, and each column having a bit line (BL n ) connected to the drains of the transistor cells (C mn ) in that column, the method including the steps of selecting the column including a desired transistor cell (C ij ), reading information from the bit line (BL j ) associated with the selected column selecting the row including the desired transistor cell (C ij ) and being characterised by:- activating only the transistor cells (C mj ) in the selected row by connecting the sources of the transistor cells in the selected row to a first potential (V S1 ) while maintaining the sources of the transistor cells in unselected rows at a second potential that does not activate the transistor cells. A method as claimed in claim 11 wherein the first potential is ground potential level.

Inventors: OGURA KIYONORI, YOSHIDA MASANOBU, OGURA, KIYONORI, YOSHIDA, MASANOBU, OGURA, KIYONORI, FUJITSU VLSI LIMITED, YOSHIDA, MASANOBU, FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1992
Main classification: G11C16
IPC codes: G11C16, G11C17