Programmable logic unit circuit

Abstract: A programmable logic unit circuit comprising a data memory circuit (10), a combinational logic circuit (13) supplied with at least two input signals, two input select circuits (11,12) for, based on the stored data in the data memory circuit (10), selecting the two input signals supplied to the combinational logic circuit (13) from more than two input signals, a clock-synchronized circuit (14) for supplying the output signal from the combinational logic circuit (13) in synchronization with a clock signal, and a 3-state-output type output select circuit (16) for selecting either the output signal of the combinational logic circuit (13) or the output signal of the clock-synchronized circuit (14), depending on the stored data in the data memory circuit (10).

Description: This invention relates to a programmable logic unit circuit according to the preamble of claim 1. The features of such a circuit are disclosed in document US-A 4 878 200. There are various techniques developed to realize the circuits fulfilling users' requirements, using semiconductor integrated technology. A gate array is one of the most useful integrated circuits. Gate arrays, as commonly known, are integrated circuits that realize desired logic circuits by previously forming transistors in wafers and then selectively connecting those transistors with suitable metallization patterns. The connection of transistors through metal wiring is made by manufactures, almost at the last stage of the manufacturing processes of integrated circuits. This makes it possible to offer the product to the users very quickly. However, the user normally has to wait for several days to several weeks before he receives the product after having ordered it, since the manufacturer first receives the circuit information from the user, forms a mask pattern for metal wiring layers based on the circuit information, and then forms the integrated circuit using the mask. Should the user has given the wrong circuit information to the manufacturer by mistake, the produced integrated circuits cannot be used. To correct the error, it is necessary to design a new integrated circuit from scratch. It is a field programmable gate array (FPGA) that have been developed to eliminate this problem. FPGAs allow the user himself to program them to realize the desired circuit without presenting the circuit information to the manufacturer. One of the features of gate arrays is that selective metal wiring provides a desired logic circuit, as described earlier. By previously forming many wires and internal switches in an integrated circuit and then selectively connecting them through the internal switches, it is possible for the integrated circuit to emulate the same function as a conventional gate array. One of such FPGAs is disclosed in U.S. Pat. No. 4,706,216 and U.S. Pat. No. 4,758,985. Specifically, the former discloses a unit circuit that is constructed of a memory circuit consisting of shift registers, a combinational logic circuit, a temporary storage circuit (a D flip-flop), and select circuits. The latter discloses a unit circuit that is constructed of a memory circuit consisting of shift registers, a combinational logic circuit, a temporary storage circuit (a D flip-flop), and select circuits. It also discloses a circuit configuration of these circuit units arranged in matrix form. What should be kept in mind in developing such FPGAs is the size of the unit circuit and the design of the program memory circuit. The above-described FPGA unit circuit provides a wide variety of combinational logic circuits and it has a D flip-flop in it, making the size larger. To observe the state of the unit circuit's internal nodes requires more circuits, which would increase the size further. A larger-scale unit circuit has the advantage of realizing more types of circuits with a single unit, but has the disadvantage of being less suitable for integrating a number of unit circuits due to a corresponding increase in the circuit area. In addition, if the desired logic circuit is a simple combinational logic circuit, the number of unused circuits in the unit circuit exceeds that of operating circuits, in resulting a lot of waste. On the other hand, in the shift registers of the memory circuit, serial data transfer takes a long time to send a large volume of data. In addition, when part of the data in the memory circuit needs to be rewritten, or part of the data needs to be read, all of the data has to be transferred again. Accordingly, the object of the present invention is to provide a programmable logic unit circuit the most suitable for constructing a field programmable gate array. The foregoing object is accomplished by providing a programmable logic unit circuit according to Claim 1. In the programmable logic unit circuit, the input signals are selected by the input select circuits based on the data stored in the data memory circuit and are supplied to the combinational logic circuit. Similarly, based on the stored data in the data memory circuit, the output select circuit selects either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit. Accordingly, a desired logic circuit can be achieved according to the data stored in the data memory circuit. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a master unit circuit according to an embodiment of the present invention; Fig. 2 is a block diagram of a slave unit circuit according to an embodiment of the present invention; Fig. 3 is a detailed circuit diagram of the master unit circuit of Fig. 1; Fig. 4 is a detailed circuit diagram of the slave unit circuit of Fig. 2; Fig. 5 is another detailed circuit diagram of the master unit circuit of Fig. 1; Fig. 6 is another detailed circuit diagram of the slave unit circuit of Fig. 2; Fig. 7A shows the block diagram symbol for the master unit circuits of Figs. 3 and 5; Fig. 7B shows the block diagram symbol for the slave unit circuits of Figs. 4 and 6; Fig. 8 is a concrete circuit diagram of the RAM cell used in the circuits of Fig. 3 to Fig. 6; Fig. 9 is another concrete circuit diagram of the RAM cell used in the circuits of Fig. 3 to Fig. 6; Fig. 10 is a concrete circuit diagram of the input select circuit used in the circuits of Fig. 3 to Fig. 6; Fig. 11 is another concrete circuit diagram of the input select circuit used in the circuits of Fig. 3 to Fig. 6; Fig. 12 is a circuit diagram of a D flip-flop circuit composed of the master unit circuit of Fig. 3 or Fig. 5 and the slave unit circuit of Fig. 4 and Fig. 6; Fig. 13 is a block diagram of a master unit circuit, centering around the portion containing short-distance wiring associated with the inputs; Fig. 14 is a block diagram of a master unit circuit, centering around the portion containing short-distance wiring associated with the output; Fig. 15 is a view showing the long-distance wiring in a matrix arrangement of a plurality of master unit circuits and slave unit circuits; Fig. 16 is a circuit diagram of a programmable logic unit containing a signal observing means; Fig. 17 is another circuit diagram of a programmable logic unit containing a signal observing means; Fig. 18 is a circuit diagram of a matrix arrangement of Fig. 16 unit circuits with a decoder for selecting those circuits; Fig. 19 is a circuit diagram of a matrix arrangement of Fig. 17 unit circuits with a decoder for selecting those circuits; Fig. 20 is a more detailed circuit diagram of the master unit circuit of Fig. 3; Fig. 21 is another more detailed circuit diagram of the master unit circuit of Fig. 3; Fig. 22 is a block diagram illustrating the construction of the entire system that controls the reading of data from and the writing of data into each RAM cell in a matrix arrangement of unit circuits, and the reading of the output from each unit circuit; and Fig. 23 is a timing chart for the operation of the system in Fig. 22. Referring to the accompanying drawings, embodiments of the present invention will be explained in detail. In a programmable logic circuit according to the present invention, a plurality of programmable logic unit circuits, which will be explained later in detail, are arranged in matrix form. The individual unit circuits are systematically connected to each other by wiring. The unit circuits are basically of two types: master unit circuits and slave unit circuits. Fig. 1 is a schematic diagram of a master unit circuit. The master unit circuit is composed of a data memory circuit 10, two input select circuits 11 and 12, a 2-input combinational logic circuit 13, a clock-synchronized circuit 14 containing a latch circuit, a polarity select circuit 15, and an output select circuit 16. One input select circuit 11 selects input A from N inputs I0 (N is a positive integer) to supply it to the combinational logic circuit 13, depending on the stored data in the data memory circuit 10. Similarly, the other input select circuit 12 selects input B from M inputs I1 (M is a positive integer) to supply it to the combinational logic circuit 13, depending on the stored data in the data memory circuit 10. Based on the previously set logical state, the combinational logic circuit 13 accepts the two logic signals A and B. The output of this logic circuit 13 is supplied to the clock-synchronized circuit 14, which synchronizes the output of the logic circuit 13 with a clock signal. Use of the clock-synchronized circuit 14 makes it easy to construct a sequential circuit, which is useful in circuit design. Input A selected from the inputs I0 is used as the clock signal to the clock-synchronized circuit 14. Therefore, input A serves as both the input to the combinational logic circuit 13 and the clock signal to the clock-synchronized circuit 14. The clock signal supplied to clock-synchronized circuit 14 is supplied as the clock output to related circuitry outside the master unit circuit. The clock-synchronized circuit 14 is also supplied with a reset input signal RI to reset the internal latch circuit. The output of the clock-synchronized circuit 14 is supplied to the polarity select circuit 15. The polarity select circuit 15 supplies either the same polarity output as the clock-synchronized circuit 14, or reverse one. This selecting action is controlled according to the stored data in the data memory circuit 10. The output Q of the polarity select circuit 15 is supplied to related circuits outside the master unit circuit. The output Q of the polarity select circuit 15 is also supplied to the output select circuit 16, to which input A and the stored data in the data memory circuit 10 are also supplied. The output select circuit 16 selects at least one from K output terminals (K is a positive integer), which supplies the output Q of the polarity select circuit 15. This selecting action is controlled according to the stored data in the data memory circuit 10. The output select circuit 16 may allow more than one output terminal to supply the output Q. The output is, hereinafter, referred to as QO. The output QO of the output select circuit 16 can go to a high-impedance state as well as to a "1" level or a "0" level. Because of this, the output select circuit 16 has a 3-state output. Fig. 2 is a schematic block diagram of the slave unit circuit. The slave unit circuit, like the master unit circuit, is composed of a data memory circuit 10, two input select circuits 11 and 12, a 2-input combinational logic circuit 13, a clock-synchronized circuit 14, a polarity select circuit 15, and an output select circuit 16. The slave unit circuit differs from the master unit circuit in the clock signal to the clock-synchronized circuit 14. That is, in the slave unit circuit, an externally input clock signal CI is supplied as the clock signal to the clock-synchronized circuit 14. The clock signal CI is the clock signal CO supplied from the master unit circuit. The output of the input select circuit 11 is the input to the clock-synchronized circuit 14 to reset the latch in the slave unit circuit. This reset signal is supplied as a reset output signal RO to a related circuit outside the slave unit circuit. Fig. 3 illustrates a detail structure of the master unit circuit of Fig. 1. This master unit circuit is provided with several MOS switches, gate circuits, and the like, in addition to the circuits of Fig. 1. Nine RAM cells R0 to R8 constitute the data memory circuit 10. One input select circuit 11 selects one from three external inputs I00 to I02 and the output of the other input select circuit 12, while the other input select circuit 12 selects one from three external inputs I10 to I12 and the output of the one input select circuit 11. Thus, N = M = 4 holds here. The input selecting action at one input select circuit 11 is determined by complementary data D0 and /D0, and D1 and /D1 read from two RAM cells R0 and R1 in the data memory circuit 10. Similarly, the input selecting action at the other input select circuit 12 is determined by complementary data D6 and /D6, and D7 and /D7 read from two RAM cells R6 and R7 in the data memory circuit 10. Input A selected by the input select circuit 11 is supplied in parallel to one terminal of each of three OR gates 21, 22, and 23. The other terminal of OR gate 21 is supplied with data D2 read from RAM cell R2, the other terminal of OR gate 22 is supplied with data /D2 read from RAM cell R2, and the other terminal of OR gate 23 is supplied with data /D3 read from RAM cell R3. The combinational logic circuit 13 is a 2-input NAND gate 24 here. The output of OR gate 21 and signal B selected by the other select circuit 12 are supplied to NAND gate 24. The clock-synchronized circuit 14 is composed of MOS switch 25 one end of whose source-drain current path is supplied with the output of NAND gate 24, an inverter 26 whose input terminal is connected to the other terminal of the source-drain current path of MOS switch 25, and a 2-input NOR gate 27 whose one input terminal is supplied with the output of inverter 26, whose other input terminal is supplied with the reset input signal RI externally supplied, and whose output is returned to the input terminal of inverter 26. The gate of MOS switch 25 is supplied with the output of OR gate 22, which is also supplied as CO to related circuitry outside the unit circuit. The polarity select circuit 15 is made up of MOS switch 28 one end of whose source-drain current path is connected to the output terminal of inverter 26, MOS switch 29 one end of whose source-drain current path is connected to the output of NOR gate 27, and inverter 30 whose input terminal is connected to both the other end of MOS switch 28 and that of MOS switch 29. The gates of MOS switches 28 and 29 are supplied with data D8 and /D8 read from the RAM cell R8, respectively. The output of inverter 30 is supplied as the signal Q to related circuits outside the unit circuit. The output select circuit 16 is composed of MOS switch 31 whose source-drain current path has its one end connected to the output of inverter 30, and MOS switches 32 and 33 whose source-drain current paths have their one ends each connected to the other end of the source-drain current path of MOS switch 31. The gate of MOS switch 31 is supplied with the output of OR gate 23, and the gates of MOS switches 32 and 33 are supplied with the outputs D4 and D5 from RAM cells R4 and R5, respectively. The other end of the source-drain current path of MOS switch 32 supplies a signal QOH, and the other end of the source-drain current path of MOS switch 33 supplies a signal QOV. Therefore, the output select circuit 16 has two outputs, that is, the number K of outputs equals 2. The master unit circuit thus constructed is represented by a symbol shown in Fig. 7A, hereinafter. Fig. 4 illustrates the structure of the slave unit circuit of Fig. 2 in detail. This slave unit circuit differs from the master unit circuit in Fig. 3 in that 2-input NAND gate 34 is provided in place of OR gate 22 and that additional 2-input AND gate 35 is provided. A clock input signal CI and the D output D2 of RAM cell R2 are supplied to NAND gate 34, whose output is supplied to the gate of MOS switch 25 in the clock-synchronized circuit 14. Signal A and the D output D2 of RAM cell R2 are supplied to AND gate 35, whose output is supplied to one end of NOR gate 27 in the clock-synchronized circuit 14, and is supplied as a reset output signal RO to related circuits outside the unit circuit. The slave unit circuit thus constructed is represented by a symbol shown in Fig. 7B, hereinafter. The MOS switches used in the master unit circuit and the slave unit circuit are made up of, for example, n-channel type MOS transistors. The operation of the master unit circuit and slave unit circuit constructed as described above will be explained. In these unit circuits, various types of functional control are performed as follows, based on the stored data in the nine RAM cells R0 to R8 in the data memory circuit 10: (1) Selecting one as signal A from N inputs to input select circuit 11. (2) Selecting one as signal B from M inputs to input select circuit 12. (3) Determining whether to use signal A as the input to the combinational logic circuit 13, as the control signal for the 3-state output of the output select circuit 16 in each of the master unit circuit and the slave unit circuit, as the clock signal to the clock-synchronized circuit 14, in the master unit circuit, or as the reset signal to the clock-synchronized circuit 14 in the slave unit circuit. (4) Polarity select control in the polarity select circuit 15. (5) Determining which one of K output terminals in the output select circuit 16 supplies the output Q. Selection of inputs A and B at the select circuit 11 and 12 in items (1) and (2) is made based on the stored data in RAM cells R0 and R1 and RAM cells R6 and R7. Control in item (3) is performed as follows. Signal B is supplied to one input of NAND gate 24 acting as the combinational logic circuit. The other input of NAND gate 24 is supplied with signal A via OR gate 21, not directly with signal A itself. The reason for this is that as mentioned earlier, input A is not only supplied to the input of the combinational logic circuit 13, but also used as the clock signal for the clock-synchronized circuit 14 in the master unit circuit, and as the reset signal for the clock-synchronized circuit 14 in the slave unit circuit. Therefore, to use input A as the clock signal to the clock-synchronized circuit 14 in the master unit circuit, or as the reset signal to the clock-synchronized circuit 14 in the slave unit circuit, input A must be separated from the input of NAND gate 24. Input A is used either as clock signal or reset signal is determined by the stored data in RAM cell R2. Specifically, when the stored data is at the "1" level, input A is used as clock signal or reset signal. On the other hand, when the data is at the "0" level, input A is not used as clock signal or reset signal. When input A is used as clock signal in the master unit circuit of Fig. 3, the output of OR gate 21 goes to a "1" level independently of input A, causing the NAND gate 24 to reverse input B. With the reset input signal RI being a "0," the latch circuit composed of inverter 26 and NOR gate 27 can latch the signal transferred via MOS switch 25. When input A has been selected as a clock signal, the /D output /D2 of RAM cell R2 is at the "0" level, allowing OR gate 22 to supply input A as clock signal to the gate of MOS switch 25. MOS switch 25 then turns on, allowing the output of NAND gate 24 to be supplied to the latch circuit. In this case, the clock-synchronized circuit 14 acts as a clock-synchronized latch circuit with the input of /B and the clock signal of A. If input A is not used as clock signal, /D2 goes to the "1" level, and the output of OR gate 22 goes to the "1" level independently of input A, causing the MOS switch 25 to remain in the "on" state. Because of this, the clock synchronizing function is lost, and the clock-synchronized circuit 14 acts just as a combinational circuit. In the slave unit circuit of Fig. 4, when input A is used as reset signal, the output of OR gate 21 goes to a "1" level, irrespective of input A, causing NAND gate 24 to reverse input B, as with the master unit circuit in Fig. 3. With input A selected as reset signal, the D output D2 of RAM cell R2 is in the "1" level, allowing AND gate 35 to supply input A of the "1" level as the reset signal to one input terminal of NOR gate 27 in the clock-synchronized circuit 14. This enables the output of NOR gate 27 to be at the "0" level and the output of the inverter 26 to be the "1" level without ambiguity, which resets the latch circuit made up of inverter 16 and NOR gate 27. The output of AND gate 35 is supplied as a reset output signal RO to the outside world. If input A is not used as reset signal, D2 goes to the "0" level, permitting the output of AND gate 35 to go to the "0" level, irrespective of input A, which has no effect on the output of NOR gate 27. The reason why the input select circuits 11 and 12 use each other's outputs A and B as one of their inputs will be explained. A case will be considered where input I10 is just reversed for output Q. This case means that the logical state of the combinational logic circuit 13 is changed from NAND logic to NOT logic. Here, the clock signal is not necessary, and input A is selected by the input select circuit 11 as the input signal to the NAND gate 24. The input select circuit 12 selects I10 as input B. One method of obtaining the reversed signal of input B at NAND gate 24 is to place inputs A and B in phase with each other. To achieve this, input B is supplied as one input to the input select circuit 11. Similarly, input B is required to gate input A. This is why the select circuits 11 and 12 use each other's output as one of their inputs. To change the logical state of the combinational logic circuit 13 from NAND logic to NOT logic, the master unit circuit may be changed to the arrangement in Fig. 5, and the slave unit circuit to the arrangement in Fig. 6. Specifically, in the master unit circuit in Fig. 3, to change the logical state of the combinational logic circuit 13 from NAND logic to NOT logic, the outputs A and B of the input select circuits 11 and 12 are selected as each other's inputs. Instead of supplying the output B of the input select circuit 12 to the input select circuit 11 and the output A of the input select circuit 11 to the input select circuit 12, a "1" level logic signal may be supplied to both input select circuits 11 and 12. In the slave unit circuit in Fig. 6, a "1" level logic signal is supplied to both input select circuits 11 and 12 for similar purposes. When a NOR gate is used for the combinational logic circuit 13 instead of NAND gate, a "0" level logic signal may be supplied as an input to both input select circuits 11 and 12. The master unit circuit in Fig. 5 is expressed by a block diagram symbol shown in Fig. 7A, and the slave unit circuit in Fig. 6 is represented by a block diagram symbol shown in Fig. 7B. The output of each of inverter 26 and NOR gate 27 in the clock-synchronized circuit 14 is transferred to inverter 30 via two MOS switches 28 and 29 in the polarity select circuit 15. The two MOS switches 28 and 29 select the polarity of the output. To control this selection, the stored data in RAM cell R8 in the data memory circuit 10 is used. Specifically, when the store data in RAM cell R8 is at the "1" level, and output D8 is at the "1" level, MOS switch 28 turns on, enabling the output of inverter 26 to be transmitted to inverter 30. As a result, the output Q of the unit circuit comes in phase with the output of NAND gate 24, with the result that the output of NAND gate 24 is supplied in the unreversed state. In contrast, when the stored data in RAM cell R8 is at the "0" level, and /D output D8 is at the "1" level, MOS switch 29 turns on, enabling the output of NOR gate 27 to be transferred to the inverter 30. As a result, the output Q of the unit circuit is the opposite in phase of the output of NAND gate 24, with the result that the output of NAND gate 24 is supplied in the reverse state. The output select circuit 16 selectively supplies the output Q to the two output terminals and is capable of placing the output terminals at a high impedance state, which will be explained below. MOS switch 31 is for 3-state control. When the stored data in the RAM cell R3 in the data memory circuit 10 is at the "1" level, and its /D output /D3 goes to the "0" level, permitting the gate of MOS switch 31 to be supplied with input A. Thus, input A of the "1" level turns on MOS switch 31, enabling output Q to be transferred to the connection point of two MOS switches 32 and 33. In contrast, input A of the "0" level turns off MOS switch 31, preventing output Q from being transferred. On the other hand, when the stored data in RAM cell R3 is at the "0" level, the /D output /D3 goes to the "1" level, which causes the output of OR gate 23 to be at the "1" level independently of input A, thereby turning on MOS switch 31 constantly. In this case, based on the stored data in two RAM cells R4 and R5, two MOS switches 32 and 33 are turned on or off to determine whether or not the output of MOS switch 31 is transferred to each of QOH and QOV. Specifically, when the stored data in both RAM cells R4 and R5 are at the "0" level and the D outputs D4 and D5 are both at the "0" level, two MOS switches 32 and 33 both turn off, preventing output Q from being transferred to both QOH and QOV. When the stored data in RAM cell R4 is at the "1" level, and the output D4 is at the "1" level, the MOS switch 32 turns on, permitting output Q to be transmitted to QOH. Similarly, when the stored data in RAM cell R5 is at the "1" level, and the output D5 is at the "1" level, the MOS switch 33 turns on, permitting output Q to be transmitted to QOV. Fig. 8 depicts a concrete configuration of a single RAM cell used in the data memory circuit 10 in the master unit circuit or the slave unit circuit. This cell contains two inverters 41 and 42 and two transfer gates 43 and 44. One end of the source-drain current path of each of transfer gates 43 and 44 is connected to bit line BL and /BL, respectively, with their gates both connected to word line WL. The other end of the source-drain current path of transfer gate 43 is connected to both the input terminal of inverter 41 and the output terminal of inverter 42, while the other end of the source-drain current path of transfer gate 44 is connected to both the input terminal of inverter 42 and the output terminal of inverter 41. Outputs D and /D are supplied at the output terminals of inverters 41 and 42, respectively. Therefore, this RAM cell is of the static type. Fig. 9 shows a concrete configuration of a single RAM cell used in the data memory circuit 10 in the master unit circuit or the slave unit circuit. This cell contains a data storage capacitor 45 and a capacitor select MOS switch 46 connected to word line WL and bit line BL. Outputs D and /D are obtained as the stored data in the capacitor and the output of an inverter (not shown) to which the stored data is supplied. Thus, this RAM cell is of the dynamic type. Fig. 10 illustrates a concrete arrangement of the input select circuit 11 used in the data memory circuit 10 in the master unit circuit or the slave unit circuit. The input select circuit 11, which is composed of six MOS switches 51 to 56, selects one from four inputs. Specifically, the source-drain current path of MOS switch 51 is inserted between the external input I00 and node N1. The source-drain current path of MOS switch 52 is inserted between the external input I01 and node N1. The source-drain current path of MOS switch 53 is inserted between the external input I02 and node N2. The source-drain current path of MOS switch 54 is inserted between input B or a "1" level logic signal and node N2. The source-drain current path of MOS switch 55 is inserted between node N1 and the node at which input A appears. The source-drain current path of MOS switch 56 is inserted between node N2 and the node supplying input A. The gates of the two MOS switches 51 and 53 are supplied with the /D output of RAM cell R0, while the gates of the two MOS switches 52 and 54 are supplied with the D output of RAM cell R0. The gates of the two MOS switches 55 and 56 are supplied with the D and /D outputs of RAM cell R1, respectively. Depending on two bits of data stored in the two RAM cells R0 and R1, the six MOS switches 51 to 56 are selectively turned on to select one from three external inputs I00 to I02 and input B or a "1" level logic signal. For example, when both pieces of data stored in RAM cells R0 and R1 are at the "1" level, MOS switches 54 and 56 turn on to select input B or a "1" level logic signal. Because the other input select circuit 12 is constructed in the same way as the above input select circuit 11, its explanation will be omitted. Fig. 11 illustrates another concrete arrangement of the input select circuit 11 used in the data memory circuit 10 in the master unit circuit or the slave unit circuit. This is the case where the above-mentioned dynamic RAM cells are used for RAM cells R0 and R1. Here, two inverters 57 and 58 are added to the Fig. 10 circuit to obtain /D output. The reason for use of two types of unit circuits, master and slave, is as follows. As mentioned earlier, the clock-synchronized circuit 14 in the master unit circuit contains a latch circuit. Generally, in addition to latch circuits, D flip-flops are also used very often in sequential circuits. As is commonly known, a D flip-flop is such that two stages of latch circuits are connected in series, with each clock signal in opposite phase, so that the two stages of latch circuits operate in a complemental manner. To realize a D flip-flop with unit circuits, two unit circuits, each of which has the opposite clock signal of the other, are connected in series. Thus, the master unit circuit differs from the slave unit circuit only in that the clock signal is supplied from the clock-synchronized circuit 14 or the clock signal is received at the clock-synchronized circuit 14, and in that the latch reset signal is supplied to the clock-synchronized circuit 14 or the reset signal is received at the clock-synchronized circuit 14. An example of a D flip-flop composed of a master unit circuit and a slave unit circuit is shown in Fig. 12. This D flip-flop uses the input I00 of the master unit circuit MU as clock input, I10 as data input, and Q of the slave unit circuit SU as the output. The input I00 of the slave unit circuit SU is used as a reset signal input, and the reset output signal RO of the slave unit circuit SU is supplied as a reset input signal RI to the master unit circuit MU. The two unit circuits are formed in the same integrated circuit. An explanation will be given as to structuring groups of wires when a plurality of master unit circuits and slave unit circuits described earlier are arranged in matrix form to fabricate an FPGA (field programmable logic circuit). There are two types of wiring groups in the FPGA: groups that connect adjacent unit circuits (hereinafter, groups of this type are referred to as short-distance wiring groups) and groups that connect matrix-arranged unit circuits in rows or in columns (hereinafter, groups of this type are referred to as long-distance wiring groups). Fig. 13 is a block diagram of a master unit circuit, centering on a portion containing short-distance wiring groups associated with the input. Four slave unit circuits SU1 to SU4 are each placed above, below, on the right, and on the left of the master unit circuit MU. Wiring are done so that the outputs Q of the four slave unit circuits SU1 to SU4 may be the inputs I01, I10, I02, and I11 of the master unit circuit MU, respectively. The inputs I00 and I12 of the master unit circuit MU will be explained later. With this arrangement, signal transmission from the nearest unit circuit is very easy. Fig. 14 is a block diagram of a master unit circuit, centering on a portion containing short-distance wiring groups associated with the output. Four slave unit circuits SU1 to SU4 are each placed above, below, on the right, and on the left of a single master unit circuit MU. Wiring is done so that the output Q of the master unit circuit MU may be the inputs I10, I11, I10, and I10 to the four slave unit circuits SU1 to SU4. Figs. 13 and 14 illustrate the short-distance wiring groups, centering around the master unit circuit. The same holds true for the slave unit circuit, and its short-distance wiring groups are not shown here. The long-distance wiring groups will be explained. In Fig. 15, a plurality of master unit circuits (marked with M in the figure) and slave unit circuits (marked with S in the figure) are arranged in matrix form. In the figure, the inputs I12 and outputs QOV of the unit circuits placed in the direction of column are all connected to two wires V1 and V2 extending in the column direction. The inputs I00 and outputs QOH of the unit circuits placed in the direction of row are all connected to two wires H1 and H2 extending in the row direction. With such long-distance wires V1, V2, H1 and H2, a unit circuit at a given position can transfer data by way of more than one unit circuit. Because the outputs QOH and QOV of each unit circuit are of 3-state output, each long-distance wire can be used as a data bus of the microcomputer system. Specifically, since the output select circuit 16 of each unit circuit can turn on and off MOS switch 31, the unit circuits that are required to supply a signal at the output QOH or QOV to the wires, place their MOS switch 31 in the on state, while the unit circuits that need not supply a signal, place their MOS switch 31 in the off state. This allows the long-distance wires V1 and V2, and H1 and H2 are shared by more than one unit circuit without interference. This feature makes it much easier to program the peripheral circuits for the microcomputer. Explanation will be given as to a circuit configuration for observing signals, one of the important techniques of the present invention. After a given circuit function has been programmed in the FPGA, a signal is supplied to the input terminal of the FPGA and the output appears at its output terminal. If the circuit does not operate as expected, it is necessary to determine which portion is malfunctioning. In that case, observation of the node signals in each unit circuit in the FPGA enables a faster finding of defective parts. For this reason, each unit circuit of the present invention is provided with a means for observing a signal at any node. Fig. 16 is a circuit diagram of a programmable logic unit circuit containing such a signal observing means. In the figure, reference characters R0 to R8 indicate RAM cells of Fig. 3 or Fig. 4 constituting the data memory circuit 10. The details of each RAM cell have been described in Fig. 9. Both RAM cells R0 and R6 are connected to bit line BL1, both RAM cells R1 and R7 to bit line BL2, both RAM cells R2 and R8 to bit line BL3, RAM cell R3 to bit line BL4, RAM cell R4 to bit line BL5, and RAM cell R5 to bit line BL6. RAM cells R0 to R5 are all connected to word line WL1, and RAM cells R6 to R8 are all connected to word line WL2. An n-channel MOS switch 61 for signal observation is provided between the output Q of the unit circuit and the bit line BL6. This unit circuit has an additional word line WL3 different from the above two word lines, the word line WL3 being connected to the gate of signal observing MOS switch 61. The three word lines WL1 to WL3 are supplied with the output of an address decoder described later. With such a configuration, to observe the output Q of the unit circuit, the signal on the word line WL3 is set to the "1" level. This turns on MOS switch 61, enabling the output Q to be read onto bit line BL6. The signal read onto bit line BL6 is supplied to related circuit outside the unit circuit by means of the circuit (not shown) for reading the stored data from each RAM. Fig. 17 is a circuit diagram of a programmable logic unit circuit containing the signal observing means. In place of word line WL3 of Fig. 16, this unit circuit is provided with an additional bit line BL7. The signal observing MOS switch 61 is inserted between the bit line BL7 and the output Q of the unit circuit. The gate of MOS switch 61 is connected to the same word line WL1 as that for selecting RAM cells R0 to R5. In this unit circuit, when the stored data is read from RAM cells R0 to R5, the output Q of the unit circuit is read at the same time. Explanation will be made as to a method of selecting word lines in a matrix arrangement of unit circuits of Fig. 16 or Fig. 17. Fig. 18 shows a matrix arrangement of 16 unit circuits of Fig. 16 with a decoder DEC for selecting them, with four columns and four rows, each containing four unit circuits. Selection of the individual RAM cells in the 16 unit circuits and selection of the outputs Q of the unit circuits are based on the 3-bit complementary address signals A0 and /A0 to A2 and /A2 supplied to the decoder DEC. In the figure, word lines WL1-1 to WL1-4 correspond to the word line WL1 of Fig. 16. Similarly, word lines WL2-1 to WL2-3 correspond to the word line WL2, and word lines WL3-1 to WL3-4 correspond to the word line WL3. In the figure, seven AND gates 71 to 77 to which different combinations of the 3-bit address signals A0 and /A0 to A2 and /A2 are supplied are provided to produce seven different decode outputs. The AND gates 71, 74, and 77 are provided to select RAM cells only, with their decode outputs supplied to word lines WL2-1, WL2-2, and WL2-3. The remaining AND gates 72, 73, 75, and 76 are used to select RAM cells and the outputs Q of the unit circuits. The decode output of each of AND gates 72, 73, 75, and 76 is supplied in parallel to each pair of AND gates 78 and 79, 80 and 81, 82 and 83, and 84 and 85, respectively. Each pair of AND gates 78 and 79, 80 and 81, 82 and 83, and 84 and 85 is controlled by means of the signal RA for selecting RAM cells and the signal OB for selecting the outputs Q of the unit circuits. Specifically, when signal RA is at the "1" level, the decode output of each of AND gates 72, 73, 75, and 76 is transmitted to the AND gates 79, 80, 83, and 84, respectively, and is supplied to word lines WL1-1 to WL1-4, respectively. When signal OB is at the "1" level, the decode output of each of AND gates 72, 73, 75, and 76 is transmitted to the AND gates 78, 81, 82, and 85, respectively, and is supplied to word lines WL3-1 to WL3-4, respectively. Fig. 19 shows a matrix arrangement of 16 unit circuits of Fig. 17 with a decoder DEC for selecting them, with four columns and four rows, each containing four unit circuits. Selection of the individual RAM cells in the 16 unit circuits and selection of the outputs Q of the unit circuits are based on the 3-bit complementary address signals A0 and /A0 to A2 and /A2. In the figure, word lines WL1-1 to WL1-4 correspond to the word line WL1 of Fig. 17. Similarly, word lines WL2-1 to WL2-3 correspond to the word line WL2. In the figure, seven AND gates 91 to 97 to which different combinations of the 3-bit address signals A0 and /A0 to A2 and /A2 are supplied are provided to produce seven different decode outputs, with their decode outputs supplied to word lines WL2-1, WL1-1, and WL1-2, WL2-2, WL1-3, WL1-4, and WL2-3. In this example, four bit lines BL7-1 to BL7-4 corresponding to the bit line BL7 are provided to read the output of each unit circuit. Fig. 20 is a detailed circuit diagram of an entire master unit circuit, whose RAM cells R0 to R8 are of the static type as shown in Fig. 8, whose input select circuits 11 and 12 are those as shown in Fig. 10, and whose signal observing means is that as shown in Fig. 16. In this example, two MOS switches 61A and 61B corresponding to the MOS switch 61 are provided to read complementary signals as the output Q onto bit lines BL6 and /BL6. One MOS switch 61A is inserted between the input terminal of inverter 30 in the polarity select circuit 15 and the bit line /BL6, while the other MOS switch 61B is inserted between the output terminal of inverter 30 and the bit line BL6. The gates of both MOS switches 61A and 61B are connected to word line WL3 provided independently of those for selecting RAM cells R6 to R8. Fig. 21 is a detailed circuit diagram of an entire master unit circuit, whose RAM cells R0 to R8 are of the static type as shown in Fig. 8, whose input select circuits 11 and 12 are those as shown in Fig. 10, and whose signal observing means is that as shown in Fig. 17. In this example, two MOS switches 61A and 61B corresponding to the MOS switch 61 are provided to read complementary signals as the output Q onto bit lines BL7 and /BL7. One MOS switch 61A is inserted between the input terminal of inverter 30 in the polarity select circuit 15 and the bit line /BL7, while the other MOS switch 61B is inserted between the output terminal of inverter 30 and the bit line BL7. The gates of both MOS switches 61A and 61B are connected to the same word line WL1 as that for selecting RAM cells R0 to R5. In this way, each unit circuit enables the signal Q at the output node to be read outside for observation. The node to be observed is not limited to the output node of the unit circuit. The signal at any node in the unit circuit may be observed. The number of nodes to be observed is not restricted to only one. The signals at more than one node may, of course, be observed. The observing means shown in Figs. 16 and 17 are not restrictive, but may be embodied in other forms. Fig. 22 is a block diagram showing an entire system that controls the writing of data into and the reading of data from each RAM cell in a plurality of unit circuits arranged in matrix form, and the reading of the output Q from each unit circuit. In the figure, reference character DB indicates a data bus, and ADB an address bus. For example, in an 8-bit system, the data bus DB generally has 8 parallel signals, and the address bus has 16 parallel signals. The row address on the address bus ADB is latched in the row address latch 101, which supplies it to the row decoder 102. The column address on the address bus ADB is latched in the column address latch 103, which supplies it to the column decoder 104. The control data on the data bus DB is supplied to the control register 105. This control register 105, based on the control data, produces a signal RA for selecting RAM cells and a signal OB for selecting the outputs Q of the unit circuits. Both signals RA and OB are supplied to the row decoder 102, which is controlled by these signals. The decode outputs of the row decoder 102 and the column decoder 104 are supplied to the unit circuit matrix 106 in which a plurality of unit circuits are arranged in matrix form. The operation of the system in Fig. 22 will be described. Fig. 23 depicts the waveforms of the control signals used to control the system in Fig. 22. Reference characters /CE, /WR, and /RD indicate a chip enable signal, a write signal, and a read signal, respectively, well known signals in the field of the microcomputer system. /WR is set to the "0" level when the CPU writes the data into the FPGA of the present invention, whereas /RD is set to the "0" level when the CPU reads the data from the FPGA. As an example of data read, it will be explained that the procedures for reading the stored data from any RAM cell in each unit circuit in the unit circuit matrix 106. As shown in the Fig. 23, /CE is first brought at the "0" level. After the FPGA has been selected, /WR is placed at the "0" level, and the control data is written into the control register 105. A unique address has been previously allocated to the control register 105. With /WR = "0," when the address data is supplied onto the address bus ADB, then the control data is written into the control register 105. At this time, the data bus DB is supplied with such data as causes the output RA of the control register 105 to be at the "1" level and the output OB to be at the "0" level. This enables the row decoder 102 to select one from its outputs for RAM selection. Next, when /RD is brought at the "0" level, the RAM cell corresponding to the address being supplied at that time is selected by the row decoder 102 and column decoder 104, causing the stored data to be supplied onto the data bus DB. In this way, the stored data in any RAM cell in the unit circuit is read out. As might be easily imagined, to read the output Q of the unit circuit, the same reasoning holds for each control signal. That is, when the control data is first written into the control register 105, the data should be written in a manner that causes the output RA to be at the "0" level and OB to be at the "1" level. As described above, in the system in Fig. 22, only the change of data on the data bus allows the same control signal to be used for reading both the stored data from any RAM cell in the unit circuit and the output Q of the unit circuit. While in the system in Fig. 22, the row decoder is of the structure in Fig. 18, but may be of that in Fig. 19. It should be noticed in this case that the control register 105 is not required and the initial write operation is unnecessary in the Fig. 23 timing chart. In this way, with the programmable logic unit circuit and programmable logic circuit in the above embodiment, it is possible to simplify the circuit configuration as compared with the conventional equivalent. It is also possible to easily observe the signal at any node in the unit circuit. This feature is useful in structuring a field programmable gate array. As described above, with the present invention, it is possible to provide a programmable logic unit circuit and a programmable logic circuit suitable for constructing a field programmable gate array.

Claims: A programmable logic unit circuit having: a data memory circuit (10) for storing at least first, second and third selecting data; a combinational logic circuit (13) which is supplied with at least two input signals (A, B) and produces a particular logic output signal from those input signals; at least two input select circuits (11, 12) for, based on said first selecting data, selecting at least two input signals (A, B) supplied to said combinational logic circuit (13) from more than two input signals; a clock-synchronized circuit (14) which latches the output signal from said combinational logic circuit (13) and outputs it upon receipt of a clock signal; a 3-state-output type select circuit (16) having a plurality of output terminals, for selecting one of the output terminals on the basis of said second selecting data and a signal output from one of said at least two input select circuits (11, 12); characterized by comprising: a polarity select circuit (15) for selecting a signal or inverted signal output from the clock-synchronized circuit (14), depending on said third selecting data, and for supplying the same to said 3-state output type select circuit (16), for outputting the same from the selected terminal of said 3-state-output type select circuit (16). A programmable logic unit circuit according to claim 1, wherein said clock-synchronized circuit (14) resets the latched contents of said clock-synchronizing circuit (14) in response to a reset signal. A programmable logic unit circuit according to claim 1 or 2, characterized in that said combinational logic circuit (13) allows the logical state of the output signal for said input signals to be changed according to fourth data stored in said data memory circuit (10). A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1 or 2 arranged in matrix form. A programmable logic unit circuit according to claim 1 or 2, characterized in that each of said input select circuits (11, 12) selects a signal, based on first data of complementary levels stored in said data memory circuit (10). A programmable logic unit circuit according to claim 1 or 2, characterized in that one of said at least two input select circuits (11, 12) supplies at least one of its output signal as an input signal to the other input select circuit. A programmable logic unit circuit according to claim 1 or 2, characterized in that said at least two input select circuits (11, 12) are each supplied with a fixed value logic signal as one of two or more input signals. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 2, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said reset signal. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1 or 2, at least one of which has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for 3-state control. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal, and has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for 3-state control. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 2, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said reset signal, and has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for 3-state control. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1, a first one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal; and a second one of which has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for output selection, and has said clock-synchronized circuit (14) supplied with the clock signal used in said first programmable logic unit circuit as a clock signal. A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 2, a first one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal; a second one of which has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for output selection, and has said clock-synchronized circuit (14) supplied with the clock signal used in said first programmable logic unit circuit as a clock signal; said second programmable logic unit circuit also having said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as a reset signal; and said first programmable logic unit circuit also having its clock-synchronized circuit (14) supplied with the reset signal to the clock-synchronized circuit (14) of said second programmable logic unit circuit, as a reset signal. A programmable logic circuit according to claim 13 or 14, characterized in that the clock signals supplied to the clock-synchronized circuits (14) of said first and second programmable logic units, respectively, are complementary to each other. A programmable logic circuit according to claim 15, characterized in that said first and second programmable unit circuits are formed in the same integrated circuit so as to adjoin each other. A programmable logic unit circuit according to claim 1 or claim 2, wherein said logic circuit (13) has a circuit function which is changed according to the stored data in said memory circuit (10); and further comprising: read control means (WL1, WL2, WL1-1 to WL1-4, WL2-1 to WL2-3, WL3-1 to WL3-4) for controlling the reading of data from said memory circuit (10); data lines (BL6, BL7) for transferring the data read from said memory circuit (10); and observation control means (61, WL1, WL3) which contain part of said read control means and which control the reading of the signal at any node in said logic circuit for observation. A programmable logic unit circuit according to claim 17, characterized in that the signal read from a given node in said logic circuit is transferred via said data lines. A programmable logic unit circuit according to claim 18, characterized in that a pair of signals of complementary levels are read from a given node in said logic circuit. A programmable logic unit circuit according to claim 17, characterized in that said read control means contains a memory circuit select line (WL1) connected to said memory circuit. A programmable logic unit circuit according to claim 20, characterized in that said observation control means contains: signal lines (BL6, BL7) for transferring the signal read from a given node in said logic circuit; and switch means (61) which is inserted between a given node in said logic circuit and said signal lines, and which is controlled by the signal on said memory circuit select line. A programmable logic unit circuit according to claim 17, characterized in that said observation control means is inserted between a given node in said logic circuit and said data lines, and is controlled by a separate signal different from the signal on said memory circuit select line.

Inventors: AUSTIN KENNETH, HIBI TOSHIO, KAWAHARA YASUO, MARU KAZUNAO, MUROGA HIROKI, SAEKI YUKIHIRO, SHIGEMATSU TOMOHISA, WEDGWOOD DARREN MARTIN, WORK GORDON STIRLING, AUSTIN, KENNETH, HIBI, TOSHIO, KAWAHARA, YASUO, MARU, KAZUNAO,, MUROGA, HIROKI, SAEKI, YUKIHIRO, SHIGEMATSU, TOMOHISA, WEDGWOOD, DARREN MARTIN, WORK, GORDON STIRLING, Hibi, Toshio, c/o Intellectual Property Div., Kawahara, Yasuo, c/o Intellectual Property Div., Maru, Kazunao, c/o Intellectual Property Div., Muroga, Hiroki, c/o Intellectual Property Div., SAEKI, YUKIHIRO, C/O INTELLECTUAL PROPERTY DIV., SHIGEMATSU, TOMOHISA C/O INTELLECTUAL PROPERTY DIV
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: H03K19
IPC codes: H03K19, G11C11