High efficiency coding recording and reproducing apparatus

Abstract: The coding controlling circuit (68) time-divisionally multiplexes intra-picture coded data I, forward predictively coded data P and bidirectionally predictively coded data B. In the intra-picture coded data, an I process flag showing the intra-picture coded data is generated by the sub-code making circuit (74). At the time of the reproduction, when this I process flag is detected, the reproducing speed designating circuit (96) will adjust the reproducing speed and the intra-picture coded data will be reproduced, because the intra-picture coded data can be decoded by the data of a single frame. At the time of special reproduction, the reproduced intra-frame data will be able to be decoded. Then the output type changing circuit (92) outputs the reproduced decoded data with a certain period corresponding to the designated speed multiplying number.

Description: Background of the Invention: Field of the Invention: This invention relates to a high efficiency coding recording and reproducing apparatus adopting a high efficiency coding adapted to digital video tape recorders and digital audio tape recorders. EP-A-0 396 285 describes a high efficient decoding video recording and reproducing apparatus where an inter-frame coded and inter-frame coded video data are recorded and the recorded coded data are reproduced and decoded, comprising a high efficiency coding video recording and reproducing apparatus wherein intra-frame coded and inter-frame coded video data are recorded and the recorded coded data are reproduced and decoded, comprising a recording means 62, 75, 76 77 fed with coded data in which intra-frame coded data I and inter-frame coded data P, B are time-divisionally multiplexed and recording them in a recording medium 79; a reproducing means 84 for tracing the recording medium 79, reproducing the recorded data and outputting the reproduced data; a judging means 95 judging the correctness of the reproduced data; and a reproduction controlling means 96 to 98 for controlling the running of the recording medium 79 and controlling the trace of the reproducing means 84. US-A-4,942,465 describes a method for coding a digital video signal for reverse reproduction of pictures. An apparatus carrying out this method uses a basic inter-frame predictive coder and an intra-frame coder. Related Art Statement: Recently, the digital processing of pictures is investigated. Particularly, on the high efficiency coding for compressing picture data, various systems have been suggested for the standardization. In order to improve the efficiency of the digital transmission and recording, the high efficiency coding technique is to code picture data with a smaller bit rate. As such high efficiency coding systems, the CCITT (International Telegraph and Telephone Consultative Committee) has suggested the JPEG (Joint Photographic Experts Group) system for color still pictures and the MPEG (Moving Picture Experts Group) system for moving pictures of the television conference/television telephone standardizing recommendation draft H.261 (as described in detail in "High Efficiency Picture Coding System Integrated" in the "Electronics" No.511, October 15, 1990, published by Japan Economic Journal Company). All of these three suggestions are of systems based on the DCT (Discrete Cosine Transform). Fig. 4 is an explanatory diagram for explaining the MPEG encoding system. In the diagram, the predictive directions in the coding are shown by arrows. Fig. 5 is an explanatory diagram showing the order of the picture data by the coding process, the arrangement on the media and the decoding process in the MPEG coding system. In the MPEG coding system, a GOP (Group Of Pictures) is formed of a predetermined number of frame pictures and contains at least one intra-picture coded picture I. The intra-picture coded picture I is picture data of one frame as coded by the DCT. The picture data of one frame of each predetermined frame a from the intra-picture coded picture I are converted to a forward predictive coded picture P by the forward predictive coding. Further, the picture data of each frame between the intra-picture coded picture I or forward predictively coded picture P and the forward predictively coded picture P are converted to a bidirectionally predictively coded picture B by the bidirectional predictive coding using the forward and rearward predictive coding. As shown in Fig. 5, the intra-picture coded picture I is coded first by only the information within the frame and contains no prediction in the time direction. Then, as shown in Fig. 5, a forward predictively coded image P is made and a bidirectionally predictively coded picture B is coded after the intra-picture coded picture I or the forward predictively coded picture P. The forward predictively coded picture P and bidirectionally predictively coded picture B utilize the correlation with the other picture data. Thus, because of the predicting method of the respective picture data, the coded picture B is recorded on the medium after the coded pictures I and P and is returned to the original order at the time when they are decoded. The intra-picture coded picture I is coded by only the information within the frame and therefore can be decoded by only the coded data alone. On the other hand, the forward predictively coded picture P and bidirectionally predictively coded picture B are coded by utilizing the correlation with the other picture data and can not be decoded by only the coded data alone. Now, the circuit shown in Fig. 6 is adopted for the predictive coder and decoder and is mentioned in the "TV Picture Multidimensional Signal Process" (written by Keihiko Fukinuki and published by Daily Industrial Newspaper Company, Japan, pages 221-). Fig. 7 is a waveform diagram for explaining the predictive coding of a television signal. In the television signal, the correlation between the pixels is high but the difference signal between the pixels is small. The predictive coding utilizes such statistical property and sight characteristic (difference sensitivity). In the simplest front value prediction, the predictive value xi' is determined by using the pixel xi-1 one pixel before the present pixel xi. Usually, the linear prediction represented by the predictive value xi' = a · xi-1 (a represents a prediction coefficient) is made. If the difference (prediction error) from the true value is represented by Σ i, the Σ i will be calculated by the below mentioned formula (1) and will be coded. By the way, Fig. 7 shows the case that the prediction coefficient a is 1: Σ i = xi - xi' = xi - a · xi-1 That is to say, in Fig. 6(a), the video signal from the camera 42 is converted by the A/D converter 43 to a digital signal which is input into the subtractor 44 and delaying circuit 45. The signal input into the delaying circuit 45 is delayed by one pixel signal, is then multiplied by the prediction coefficient a in the multiplier 46 and is given to the subtractor 44. In the subtractor 44, the output of the multiplier 46 is subtracted from the output of the A/D converter 43 to determine Σ i of the above mentioned formula (1). Further, the output of the subtractor 44 is quantized by the non-linear quantizing circuit 47 and is output to the transmitting path 48. By the way, as the prediction error deviates in the distribution as seen statistically, the non-linear quantization is adopted in the coding. On the other hand, in the decoder, the signal from the transmitting path 48 is input into the typical value circuit 49. In the typical value circuit 49, in order to obtain characteristics reverse to the compression characteristics in the non-linear quantizing circuit 47 of the coder, the elongation characteristics are obtained by using the reverse function of the function adopted in the non-linear quantizing circuit 47. The output of the typical value circuit 49 is given to the D/A converter and LPF (low pass filter) 51 through the adder 50, is converted to an analogue signal and is given also to the delaying circuit 52. The output of the delaying circuit 52 is given to the adder 50 through the multiplier 53 multiplying the prediction coefficient a. That is to say, the pixel xi of the above mentioned formula (1) is obtained by the loop of the adder 50, delaying circuit 52 and multiplier 53. The output of the D/A converter and LPF 51 is given to the monitor 54 and is displayed. By the way, in order to prevent the quantizing strains of the non-linear quantizing circuit 47 from being accumulated, in fact, in the coder, the circuit shown in Fig. 6(b) is adopted. That is to say, the local decoder 55 comprising the typical value circuit 49, adder 50, delaying circuit 52 and multiplier 53 is adopted to make a signal to be given to the subtractor 44. Thus, the quantizing strains will not be accumulated. Now, the above described MPEG coding system is considered to be applied to the DAT (digital audio tape recorder) or VTR (video tape recorder). Fig. 8 is a trace pattern diagram showing the recorded tracks in this case by the track pattern coordinate method. In the diagram, the hatched parts show the recording positions of the intra-picture coded pictures I. As described above, in the MPEG coding system, first, the data of the coded pictures I shown by the hatches are recorded on the recording medium. Then, the data of the bidirectionally predictively coded pictures B and forward predictively coded pictures P are successively repeatedly recorded. In Fig. 8, the first GOP is recorded until the midway of the fourth track. The next GOP is recorded from the midway of the fourth track to the last of the sixth track. The coded picture I in the picture at the top of the next GOP is recorded at the top of the seventh track. In the MPEG coding system, the recording rate is regulated (typ. 1.2 Mbps) but the data length is variable. Therefore, as shown in Fig. 8, the position of the track in which the intra-picture coded picture I always contained in the GOP is recorded can not be specified and the data length of 1 GOP can not be also specified. Even in this case, in the usual reproduction, the respective coded pictures I, B and P are successively reproduced and therefore there is no particular problem. However, at the time of special reproduction such as the quick fed reproduction, only a part of the recorded track will be reproduced, therefore the recording position on the recording medium of the intra-picture coded picture I will not be regularly arranged and the intra-picture coded picture I may not be reproduced. In such case, even in case the other coded data are positively reproduced, these data will not be able to be decoded. On the other hand, as a moving picture coding system, there is a method wherein only the intra-picture coding is adopted instead of the above described MPEG system. Fig. 9 is a block diagram showing a related art of a high efficiency coding recording and reproducing apparatus suggested in "An Experimental Study for a Home-Use Digital VTR" (IEEE Trans. CE Vol. 35. No. 3, Aug. 1989, pp. 450-457). In Fig. 9, of video signals, a luminance signal Y is sampled with a sampling clock, for example, of a frequency of 13.5 MH z and color difference signals Cr and Cb are sampled with a sampling clock, for example, of a frequency of 13.5/4 MH z . These signals Y, Cr and Cb are input into the memory 1 which converts the input interlaced signals to be of a frame structure and outputs horizontal and vertical direction 8 × 8 pixels as one block in a block unit to the bit rate reducing circuit 2. Fig. 10 is a block diagram showing the concrete formation of the bit rate reducing circuit 2. In the DCT circuit 3 of the bit rate reducing circuit 2, a signal in which one block is formed of 8 × 8 pixels is input and is converted to a frequency component by the two-dimensional DCT (Discrete Cosine Transforming) processing of the 8 × 8 pixels. Thereby, the spatial correlative component can be reduced. That is to say, the output of the DCT circuit 3 is given to the adapted quantizing circuit 5 through the buffer memory 4 and is re-quantized by the adapted quantizing circuit 5 so that the redundancy of the signal of one block will be reduced. In this case, in the data amount evaluating circuit 7, the data amount is evaluated from the data from the DCT circuit 3 and the coefficient based on the evaluated result is generated. In the adapted quantizing circuit 5, the quantization is made on the basis of this coefficient. Further, the quantized data are given to the variable length coding circuit 6 and are, for example, Haffman-coded on the basis of the result calculated from the statistical coded amount of the quantized output. Thereby, short bits are allotted to data high in the appearing probability and long bits are allotted to data low in the appearing probability so that the transmitted amount will be further reduced. Thus, the data of 162 Mbps are compressed to 19 Mbps and are given to the coder 8 in Fig. 9. In the coder 8, the parity for correcting errors is added to the data and they are output to the channel coder 10. In this case, in the coder 8, the variable length data of respective blocks are synchronized with synchronous signal s , are converted to synchronous blocks of a fixed length and are output. In the channel coder 10, the output of the coder 8 and the voice signal from the voice processing circuit 9 are recorded and coded in response to the characteristics of the recording media, are given to the recording amplifier (R/A) 11 and are recorded in the medium 12. Thus, as shown in Fig. 11, the data of the respective blocks are converted to synchronous blocks of the same data length and are recorded. On the other hand, at the time of the reproduction, the signal reproduced from the recording medium 12 will be given to the detector 14 through the reproduction amplifier (H/A) 13. In the detector 14, the bit clock of the reproduced signal is detected, the recorded data are decoded, the TBC (Time Base Correction) process correcting the time axis or the like is made and then the data are output to the decoder 15 in which such errors as random errors and burst errors generated at the time of the recording and reproduction are corrected by using correcting codes and are given to the bit rate decoder 16. In the bit rate decoder 16, the variable length code from the decoder 15 is decoded, the reverse quantizing process and reverse DCT process are made and the original information is restored. In this case, a non-reversible compressing process will be made by the re-quantizing process and some strains will be generated. The data decoded by the bit rate decoder 16 are given to the memory 17, are converted to be of the same format as of the input and are output. By the way, in the voice processing circuit 18, the voice signal from the detector 14 is voice-processed and is output. Thus, the coded data will be recorded in a synchronous block unit of a fixed length at the time of the recording, the picture and recording position correspond to each other and such special reproduction as of the VTR is possible to some extent. However, in this method, there is a defect that the compression efficiency is low. Also, in the "Fixed Electronic Still Camera Rate Adapted Type DCT Coding System" suggested in the 1989 Telecommunication Society (Japan) Spring Nation-wide General Meeting D-159 is disclosed an example that the recording is made by limiting the code amount in a unit recording time to a fixed range. Fig. 12 is a circuit diagram for explaining this suggestion. A signal of one block of 8 × 8 pixels input through the input terminal 21 is DCT-processed by the DCT circuit 22 and is then given to the scan converting circuit 23. As shown in Fig. 13, the outputs (DCT conversion coefficients) of the DCT circuit 22 are arranged in the order from the low region components to the high region components in the horizontal and vertical directions. In the scan converting circuit 23, as the information concentrates in the low region components in the horizontal and vertical directions of the DCT conversion coefficients, as shown by the numbers in Fig. 13, the scan is made zigzag from the low region components toward the high region components in the horizontal and vertical directions to output the DCT conversion coefficients to the quantizing circuit 24. By the way, the part of the number 0 in Fig. 13 shows a DC component (direct current component) and its value is an average value of all the conversion coefficients. The other parts are AC components. On the other hand, a parameter α showing the information amount of the input image is input into the multiplier 26 through the input terminal 28. In the multiplier 26, the information of the basic quantizing coefficient preset for each frequency component of the DCT conversion coefficient is given from the Q table 27 and this information is multiplied by the parameter α and is output to the quantizing circuit 24 through the limiting circuit 25. In the quantizing circuit 24, the DCT conversion coefficient is quantized on the basis of the quantizing coefficient from the limiting circuit 25. That is to say, in the quantizing circuit 24, the quantization is corrected for each frequency component by the output of the limiting circuit 25 and the coding rate is controlled. By the way, in the limiting circuit 25, the minimum quantizing coefficient is limited on the basis of the encoding efficiency and the data of the Q table 27. Further, a picture coding system is suggested by the present applicant in the specification of Japanese Patent Application No. 404811/1990 (published under JP-A-04 220 889) and the data appearing at the output terminal 30 in Fig. 12 are made to be of a fixed length. Fig. 14 is a block diagram for explaining this suggestion. A signal of the macro-block shown in Fig. 15 is input into the input terminal 31. As shown in Fig. 15, in case the sampling frequency is 4 f sc (f sc is a color sub-carrier frequency), the number of effective pixels of one frame picture will be approximately horizontal 768 pixels × vertical 488 pixels. In the color difference signals Cr and Cb, the sampling rate in the horizontal direction is half, that is, 2 f sc . Therefore, while two luminance blocks of 8 × 8 pixels are sampled, in the color difference signals Cr and Cb, respectively one block of 8 × 8 pixels will be sampled. A macro-block is formed of these four blocks. The data of this macro block are input into the DCT circuit 33 through the buffer memory 32, are DCT-processed and are further quantized by the quantizing circuit 34 to obtain the same quantized output as the quantized output in Fig. 12. In this case, as shown in Fig. 16, at the top of each macro-block are added code amount data L showing the code amount of the macro-block. This quantized output is divided in the frequency, the low region component is coded by the low region coding circuit 35 and the high region component is coded by the high region coding circuit 36. The coded data from the low region and high region coding circuits 35 and 36 are given to the multiplexer (mentioned as MUX hereinafter) 39 respectively through the buffer memories 37 and 38 and are time-divided and multiplexed. Figs. 17(a) and (b) are explanatory diagrams for explaining the multiplex method. In Fig. 17(a), the low region component and high region component are successively arranged following the code amount data L. In Fig. 17(b), the low region component is arranged before the code amount data L and the high region component is arranged after the code amount data L. The output of the MUX 39 is given to the packing circuit 40 and is provided with a macro-block address (MBA) and macro-block pointer (MBP) in a synchronous block unit. Fig. 18 is an explanatory diagram showing this state. The macro-block address shows the data of the position on the picture of the macro-block, that is to say, the order within one frame or one field, for example, added following the synchronous signal. The macro-block pointer is added following this macro-block address and then the code amount data L and macro-block in Fig. 16 are arranged in the picture coding data sector. The picture coding data sector is sectioned by a unit of 54 bytes. As shown in Fig. 19, the macro-block is started or ended in the midway of the picture coding data sector. The macro-block pointer shows the byte position of the picture coding data sector from which the macro-block is started. Thus, the coded data fixed in the length within the frame are output from the packing circuit 40. By the way, in the format in Fig. 18, two data P of the C1 series (61, 57) of the Read Solomon codes (R.S. codes) are added as error correcting codes. As error correcting codes in the magnetic recording system, as adopted in the "Error Correcting Apparatus" in the Japanese Patent Publication No. JP-A-54 0 32240 (1979), D-1 digital VTR, D-2 digital VTR and DAT, the Read Solomon codes are mostly used. For example, in the D-1 standard, the codes of the C1 series (64, 60) and C2 series (32, 30) are adopted, in the D-2 standard, the codes of the C1 series (93, 85) and C2 series (68, 64) are adopted and, in the DAT, the codes of the C1 series (32, 28) and C2 series (32, 26) are adopted. Fig. 20 is an explanatory diagram for explaining the D-1 standard. Fig. 21 is an explanatory diagram showing the recorded state of recording tracks of a VTR. In the C1 series of the D-1 standard, as shown in Fig. 36, four correcting codes p, q, r and s are allotted to 60 data. In the C2 series, two correcting codes P and Q are allotted to 30 data. As shown in Fig. 21, in one track of the VTR, a plurality of data as shown in Fig. 20 are continuously recorded. By the way, in one synchronous block, n (n ≧ 1) codes of the C1 series are provided. Thus, in this example, the quantized output is classified in each frequency component of the conversion coefficient and the low frequency component is arranged in the reference position of each macro-block. Further, the macro-block pointer and the macro-block address showing the position on the picture are arranged in each synchronous block having an integral number of synchronous informations. Further, by adding the code amount data L, the gross code amount of the macro-block can be caught and is fixed in the length within the frame. By the macro-block address and macro-block pointer, each macro-block and the position on the picture can correspond to each other. However, if such information as of the macro-block address, macro-block pointer and code amount data L lacks, the decoding cannot be carried out. For example, if an error is generated in the code amount data L, not only the lacking macro-block data but also the following macro-block will be erroneous and will not be able to return from the error until the macro-block address and macro-block pointer of the next synchronous block reach the designated part. Also, the respective macro-blocks are variable length coded and there has been a problem that such special reproduction as the quick fed reproduction of a VTR is impossible. Object and Summary of the Invention: An object of the present invention is to provide a high efficiency coding recording and reproducing apparatus wherein, in order to improve the coding efficiency, a variable length coding is adopted, even in case an error is generated in predetermined data, the return from the error will be easy and the reproduced picture quality is kept constant. Another object of the present invention is to provide a high efficiency coding recording and reproducing apparatus wherein, at the time of such special reproduction as of a VTR, a decoded picture will be able to be positively obtained. These objects are solved by an apparatus according to claim 1. According the one aspect the high efficiency coding recording and reproducing apparatus according to the present invention comprises a recorded code arranging means fed with coded data in which intra-frame coded data and inter-frame coded data are time-divisionally multiplexed and outputting the intra-frame coded data with the addition of a flag showing that they are intra-frame coded data, a flag detecting means fed with reproduced data from a recording medium in which the coded data are recorded and detecting the flag, a decoding means switching the intra-frame decoding process or inter-frame decoding process on the basis of the output of the flag detecting means and decoding the reproduced data from the recording medium, a recording position presuming means presuming the recording position on the recording medium of the intra-frame coded data from the output of the flag detecting means, a reproducing speed designating means controlling the trace of the the recording tracks of the recording medium on the basis of the data of the speed multiplying number at the time of the reproduction and the output of the recording position presuming means and an outputting means outputting the output of the decoding means at a period based on the data of the speed multiplying number. The other features and advantages of the present invention will become apparent enough with the following description. Brief Description of the Drawings: Fig. 1 is a block diagram showing an embodiment of the high efficiency coding recording and reproducing apparatus according to the present invention. Fig. 2 is a tracing pattern diagram showing by a track pattern coordinate method the recorded tracks in the embodiment in Fig. 1. Fig. 3 is an explanatory diagram for explaining the operation of the embodiment in Fig. 1. Fig. 4 is an explanatory diagram for explaining an MPEG coding system. Fig. 5 is an explanatory diagram showing the order of image data by the encoding process, arrangement on the medium and decoding process in the MPEG encoding system. Fig. 6 is a circuit diagram showing a predictive coder and decoder. Fig. 7 is a waveform diagram for explaining the predictive coding of a television signal. Fig. 8 is a tracing pattern diagram showing by a track pattern coordinate method the recording tracks in the case that the MPEG coding system is applied to a DAT or VTR. Fig. 9 is a block diagram showing a conventional high efficiency coding recording and reproducing apparatus. Fig. 10 is a block diagram showing a concrete formation of a bit rate reducing circuit in Fig. 25. Fig. 11 is an explanatory diagram showing a data recording format in Fig. 25. Fig. 12 is a block diagram for explaining a conventional example. Fig. 13 is an explanatory diagram for explaining a DCT conversion coefficient. Fig. 14 is a block diagram showing a conventional high efficiency coding recording and reproducing apparatus. Fig. 15 is an explanatory diagram for explaining a macro-block. Fig. 16 is an explanatory diagram for explaining the data format of the conventional example in Fig. 30. Fig. 17 is an explanatory diagram for explaining the data format of the conventional example in Fig. 30. Fig. 18 is an explanatory diagram for explaining the data format of the conventional example in Fig. 30. Fig. 19 is an explanatory diagram for explaining the data format of the conventional example in Fig. 30. Fig. 20 is an explanatory diagram for explaining error correcting codes. Fig. 21 is an explanatory diagram for explaining error correcting codes. Detailed Description of the Preferred Embodiments: Fig. 1 is a block diagram showing one embodiment of the high efficiency coding recording and reproducing apparatus according to the present invention. In this embodiment, the present invention is applied to a video tape recorder. An interlaced video signal is input into the format circuit 61 which has a memory, makes the input signal a frame, makes 8 × 8 pixels one block and outputs data in a block unit. These data are given to the intra-picture coding circuit 64, forward predictively coding circuit 65 and bidirectionally predictively coding circuit 66 through the demultiplexer (mentioned as the DeMUX hereinafter) 63 in the recorded code arranging circuit 62 enclosed with the broken lines. These coding circuits 64, 65 and 66 make respectively the intra-picture coding process I, forward predictively coding process P and bidirectionally predictively coding process B and output the coded data through the MUX 67. The coding controlling circuit 68 controls these DeMUX 63 and MUX 67 on the basis of the signal from the format circuit 61. The high efficiency coded data from the MUX 67 are given to the parity adding circuit 70 through the buffer 69. The parity adding circuit 70 adds an error correcting parity to the input data and outputs them to the adder 72. On the other hand, the sub-code making circuit 74 makes sub-codes for various data and outputs them to the adder. In this embodiment, in case it is shown by the output of the coding controlling circuit 68 that the output of the intra-picture coding circuit 64 is output, an I process flag showing that it is an intra-picture coding process I will be generated in the flag part of the sub-code included in the recording track in which this intra-picture coded picture I is recorded. By the way, even in case the corresponding recording track precedes in the time, there will be a processing time delay in the parity adding circuit 70 and therefore the I process flag will be able to be described. The synchronous ID making circuit 71 outputs to the adder 73 the synchronous signal for taking the block synchronization and the ID number showing the block number or the like. The adder 73 adds the output of the sub-code making circuit 74 and the output of the synchronous ID making circuit 71 and gives them to the adder 72. The adder 72 adds the output of the adder 73 and the output of the parity adding circuit 70 and outputs them to the record modulating circuit 75. The record modulating circuit 75 converts the input bit stream to be of a type adapted to the record of the recording medium and gives it to the video head 78 within the drum assembly 77 through the record amplifier 76. The video head 78 records in the magnetic tape 79 the signal from the record amplifier 76, reproduces the recorded signal and gives it to the reproducing and equalizing circuit 81 through the reproduction amplifier 80. The reproducing and equalizing circuit 81 removes the waveform interference (inter-code interference) from the input data and outputs the data to the record demodulating circuit. The record demodulating circuit 82 demodulates the data modulated at the time of recording, returns them to the original data row and outputs them to the synchronous TBC circuit 83. The synchronous TBC circuit 83 corrects the time axis of the input data and gives the data to the error correcting circuit 85 within the reproduced code restoring circuit 84. The error correcting circuit 85 corrects the error generated on the magnetic tape 79 and gives the data to the buffer 86. The output of the buffer 86 is given to the intra-picture decoding circuit 88, forward predictively decoding circuit 89 and bidirectionally predictively decoding circuit 90 through the DeMUX 87. These decoding circuits 88, 89 and 90 decode respectively the intra-picture coded data, forward predictively coded data and bidirectionally predictively coded data and outputs the decoded data to the output type converting circuit 92 through the MUX 91. The output of the buffer 86 is given also to the coding controlling circuit 93 which judges the kind of the coding process from the input data row and controls the DeMUX 87 and MUX 91 on the basis of the judged result. On the other hand, the output of the synchronous TBC circuit 83 is given also to the sub-code decoder 94 which detects the I process flag from the input data and gives the detected signal to the speed designating circuit 96. Also, the output from the coding controlling circuit 93 is given also to the effectiveness judging circuit 95 which judges whether there is an error of the reproduced data or not and gives the judged signal to the speed designating circuit 96. In the speed designating circuit 96, the speed multiplying number based on the user operation is designated and, on the basis of these speed multiplying number data, the detected signal from the sub-code decoder 94 and the judged signal from the effectiveness judging circuit 95, the speed designating signal for controlling the running speed of the magnetic tape 79 is output to the tape speed controlling system 97 and the drum speed and phase controlling system 98. The tape speed controlling system 97 outputs to the adder 101 the signal designating the tape running speed on the basis of the FG (frequency) signal fed back from the capstan motor (not illustrated) rotating and driving the capstan 100. Also, the reproduced signal from the head 78 is given to the tracking controlling system 99 which outputs to the adder 101 the output for obtaining the optimum tracking position. The adder 101 adds the outputs of the tape speed controlling system 97 and tracking controlling system 99 and outputs the controlling signal to the capstan motor so that the rotating speed of the capstan 100 may be controlled and the transmitting speed of the magnetic tape 79 transmitted as held between the capstan 100 and pinch roller 102 may be regulated. On the other hand, the speed designating circuit 96 gives the timer 103 the output based on the speed multiplying number. The timer 103 operates at the set period based on the speed multiplying number data and controls the reading out of the output type converting circuit 92 in each set period so that the output type converting circuit 92 may output the video data from the MUX 91 at each predetermined time based on the speed multiplying number data. The operation of the thus formed high efficiency coding recording and reproducing apparatus shall be explained in the following with reference to Figs. 2 and 3. Fig. 2 is a tracing pattern diagram showing by a track pattern coordinate method the recording tracks in this embodiment. In the diagram, the hatched parts represent recording positions of intra-picture coded pictures I. The input interlaced video signal is made a frame by the format circuit 61 and is output to the DeMUX 63 in a block unit of 8 × 8 pixels. The data from the DeMUX 63 are given to the coding circuits 64, 65 and 66 and are subjected respectively to the intra-picture coding process I, forward predictively coding process P or bidirectionally predictively coding process B. The coding controlling circuit 68 controls the DeMUX 63, gives picture data to coding circuits 64, 65 and 66, controls the MUX 67 and outputs the coded data by the time division to make the MPEG coding. The variable length bit stream from the MUX 67 is output to the parity adding circuit 70 through the buffer 69 and an error correcting parity is added to it. A synchronous signal, ID signal and sub-code are also added to the bit stream by the adders 72 and 73. In this embodiment, an I process flag showing that an intra-picture coding is being processed by the sub-code making circuit 74 is generated and is described in the flag part of the sub-code included in the recording track in which the intra-picture coded data in the bit stream are recorded. Thus, in the bit stream from the adder 72, for example, as shown in Fig. 3, at the top, the synchronous signal is arranged, then, the ID number and sub-code are arranged and the I process flag is written into this sub-code. In the example in Fig. 3, the set of the coded data and parity is repeatedly arranged next the sub-code. The bit stream from the recorded code arranging circuit 62 is given to the record modulating circuit 75 and is converted to be of a type adapted to be recorded in the medium, is given to the video head 78 through the record amplifier 76 and is magnetically recorded in the magnetic tape 79. At the time of the reproduction, the reproducing signal from the video head 78 will be input into the reproducing and equalizing circuit 81 which will equalize the input data and will remove the waveform interference. The data from the reproducing and equalizing circuit 81 are returned to the same data row as of the bit stream from the recorded code arranging circuit 62 by the record demodulating circuit 82 and synchronous TBC circuit 83 and are given to the reproduced code restoring circuit 84. The sub-code decoder 94 detects the I process flag from the output of the synchronous TBC circuit 83 and outputs the detecting signal to the speed designating circuit 96 in which is also input the judging signal showing whether there is an error or not from the effectiveness judging circuit 95. The speed designating circuit 96 controls the conveying speed of the magnetic tape 79 and the speed and phase of the drum on the basis of the speed multiplying number data and detected signal by the user operation. Now, as shown by the hatched parts in Fig. 2, the intra-picture coded data are assumed to be recorded in the tracks Nos. 1, 4, 7, 11, 12, ... . After the track No.1 is traced, when, by the detecting signal of the sub-code decoder 94, the reproduction end of the intra-picture coded data in the track No.1 is caught from the reproduced data, or the reproduction end of the intra-picture coded data in the track No.2 is caught, the speed designating circuit 96 will predict the occurence of the intra-picture coded data and will designate a speed multiplying number or will designate a predetermined speed multiplying number to control the running of the magnetic tape 79 and, as shown in the trace A indicated by the arrow, by the speed multiplying reproduction, the video head 78 will be moved to the track No.4. Then, the track No.4 is traced to reproduce the intra-picture coded data. When the reproduction of the track No.4 ends, the speed designating circuit 96 will designate the speed multiplying reproduction again by the detecting signal of the sub-code decoder 94. When the sub-code decoder 94 detects the I process flag at the top of the track No.7, the ordinary reproduction will be returned and the track No.7 will be reproduced. Thus, the traces A and B shown by the arrows are made. By the way, as shown by the track No.7 of the trace B, when it is shown by the detecting signal from the sub-code detector 94 that the reproduction of the intra-picture coded data has ended, the speed designating circuit 96 may move the speed multiplying reproduction to the track No.11 from the midway of the track. Further, as shown by the trace C of the arrows in the diagram, the speed designating circuit 96 may run the magnetic tape 79 in the reverse direction so that the sub-code decoder 94 may detect the I process flag. Thus, by properly repeating the ordinary reproduction and quick feeding reproduction, the speed designating circuit 96 reproduces positively at least the intra-picture coded data. The reproduced signal is given to the reproduced code restoring circuit 84 through the reproducing and equalizing circuit 81, record demodulating circuit 82 and synchronous TBC circuit 83, has the errors at the time of the recording and reproduction corrected by the error correcting circuit 85 of the reproduced code restoring circuit 84 and is given to the DeMUX 87 and coding controlling circuit 93 through the buffer 86. The coding controlling circuit 93 judges the kind of the coding process of the data row input into the DeMUX 87 and controls the DeMUX 87. The output of the DeMUX 87 is given to the decoding circuits 88, 89 and 90, is decoded and is given to the output type converting circuit 92 through the MUX 91. As described above, the speed designating circuit 96 properly repeats the ordinary reproduction and quick feeding reproduction and therefore the time axis of the reproduced data is not always constant. Therefore, the speed designating circuit 96 gives the data of the speed multiplying number to the timer 103 and controls the set period. The signal of a predetermined period corresponding to the speed multiplying number is given to the output type converting circuit 92 from the timer 103 so that the output type converting circuit 92 may output the data at fixed intervals corresponding to the designated speed multiplying number and a reproduced picture favorable to the sight may be obtained. Thus, in this embodiment, by the sub-code making circuit 74, the I process flag showing the intra-picture coded data is described and recorded within the sub-code and, at the time of the reproduction, this I process flag will be detected so that the speed designating circuit 96 may regulate the reproducing speed and may positively reproduce at least only the intra-picture coded data. These intra-picture coded data can be decoded with only the data of one frame and, even if such special reproduction as the speed multiplying reproduction is made, the reproduced data will be able to be decoded. Further, by the signal from the timer 103, the output type converting circuit 92 outputs the decoded data at a fixed period in response to the designated speed multiplying number and a special reproduced picture natural to the sight can be obtained.

Claims: A high efficiency coding video recording and reproducing apparatus wherein intra-frame coded and inter-frame coded video data are recorded on a recording medium and the recorded coded data are reproduced and decoded according to the MPEG-standard involving a variable length coding, where said video data is recorded as successive groups of pictures (fig. 4, 8, 2) and each group of pictures is formed of a predetermined number of inter-frame coded pictures and at least one intra-frame coded picture and said intra-frame picture is coded first in the group of pictures, comprising: means (62) for arranging the coded data to recorded, said means (62) being fed with said coded data in which said intra-frame coded data and said inter-frame coded data (P, B) are time-divisionally multiplexed, and outputting the intra-frame coded data (I) with the addition of a flag showing that they are intra-frame coded data; means (77, 80-84) for reproducing the data recorded on said recording medium (79); a flag detecting means (94) for detecting the flag in the reproduced data given from the recording medium (79) in which the coded data are recorded; a decoding means (84, 93) for decoding the reproduced data from the recording medium (79); a coding controlling circuit (93) for controlling the intraframe decoding process or inter-frame decoding process on the basis of a judgement of the kind of the coding process from the reproduced data; a judging means (95) judging whether there is an error of the reproduced data or not on the basis of an output from the coding controlling circuit (93); a recording position presuming means (96) for presuming the recoding position on the recording medium (79) of the intra-frame coded data (I) from the output of the flag detecting means (94); a reproducing speed designating means (96) for controlling the conveying speed of the recording medium (79) at the time of the reproduction on the basis of a reproducing speed multiplying number input by a user, the detected signal from the flag detecting means (94), the output of the recording position presuming means (96), and the judged signal from the judging means (95), said reproducing speed designating means (96) performing a quick feeding reproduction betweeen two intra-frame coded data (I) followed by an ordinary reproduction for said respective intra-frame coded data (I); and an outputting means (92) outputting the output of the decoding means at a period based on said reproducing speed multiplying number.

Inventors: SHIMODA KENJI, SHIMODA, KENJI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: H04N5
IPC codes: G11B20, G11B15, H04N5, H04N9, G11B5