Method and apparatus for controlling coefficients of adaptive filter

Abstract: A method or apparatus for controlling coefficients of an adaptive filter (3) for identifying unknown system or predicting periodic signals by correcting coefficients of the adaptive filter (3) in such a manner that the difference signal obtained by subtracting an output signal of the adaptive filter (3) from a mixed signal of the output signal from the unknown system and an interference signal comprises steps or means (9) for obtaining the information relating to the magnitude of the coefficients or output of the adaptive filter, and adaptively varying the amount of correction in coefficients of the adaptive filter in response to the obtained information.

Description: The present invention relates to a method and apparatus for controlling coefficients of an adaptive filter for identifying an unknown system or predicting periodic signals using such adaptive filter, wherein interference signals are superimposed with the output signal from the unknown system. Its practical applications include noise cancellers to eliminate noise mixed with a signal from a main input terminal, echo cancellers to eliminate undesired reflection signals acoustically coupled to a microphone from a speaker or mismatching of 2-line to 4-line conversion circuit, line equalizers to equalize distortion caused by transmission lines and adaptive line enhancers to pick up periodic signals buried in a wideband signal or to suppress periodic interference signals to a wideband signal. In identifying unknown systems or predicting periodic signals using an adaptive filter, noise cancellers and adaptive line enhancers (referred to as ALE hereunder) are known as typical examples where strong interference signals are superimposed with an output signal from an unknown system. See p.p. 1692-1716 of the PROCEEDINGS OF IEEE, 1975; Vol. 63, No. 12 (referred to as the Reference 1 hereunder). Also known are echo cancellers as disclosed in the IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1984, Vol. 2, No. 2 at p.p. 283-297 (referred to as the Reference 2 hereunder). In echo cancellers, if double talk is not detected properly, the near-end signal acts as a strong interference signal. No double talk detection is made in echo cancellers to be used in 2-line bidirectional transmission. In this case, additional noise superimposed in the transmission lines will be a weak interference signal to the adaptive operation of the filter. Noise cancellers suppress noise in the signal by applying a noise replica corresponding to the noise components in the main input terminal. Used for this end is an adaptive filter having a transfer function similar to the impulse response of the noise path from the noise source to the main input terminal. At this time, a coefficient for each tap of the adaptive filter is successively modified by correlating the reference noise derived at the reference input terminal with a difference signal obtained by subtracting the noise replica from the mixed signal of the noise and the signal. On the other hand, echo cancellers suppress the echo by subtracting a pseudo echo or an echo replica from the echo signal caused by mismatching of the 2-line to 4-line conversion circuit in a 2-line bidirectional transmission line or a long distance telephone line or acoustical coupling between a microphone and a speaker. The echo replica is generated by using an active filter having a transfer function similar to the impulse response of the echo path. A coefficient of each tap of the adaptive filter is successively modified by correlating the reference signal on the reference input terminal with a difference signal obtained by subtracting the echo replica from the mixed signal of the echo signal and the additional noise. Used in ALEs is an adaptive filter having a transfer function to pass only signal components whose periods are equal to those of the periodic signals for enhancing the periodic signals buried in a wideband signal. A coefficient of each tap of the adaptive filter for this application is a prediction coefficient to predict the periodic signals. It is successively modified by correlating the difference signal obtained by subtracting the predicted periodic signals or the output from the adaptive filter from the mixed signal of the periodic signals and the wideband signal on the main input terminal with the delayed mixed signal on the reference input. For enhancing the periodic signals, the output from the adaptive filter is used as the ALE output and the ALE is also used to suppress periodic interference signal to the wideband signal. In the latter case, the output signal is the difference or error signal instead of the output from the adaptive filter. There are two typical coefficient modifications or converging algorithms. One is an LMS algorithm (see the Reference 1). The other is a Learning Identification Method (LIM) as set forth in p.p. 282-287 of The IEEE Transactions on Automatic Control, Vol. 12, No. 3 in 1967 (referred to as Reference 3 hereunder). Illustrated in FIG. 14 is a block diagram of a conventional noise canceller. A mixed signal of a signal and noise detected on a main input terminal 1 is supplied to a subtracter 4. On the other hand, supplied to an adaptive filter 3 is a reference noise detected on a reference input terminal 2. The noise components are cancelled by the subtracter 4 which subtracts the noise replica generated by the adaptive filter 3 from the mixed signal. The subtracted output is supplied to an output terminal 6. Simultaneously, the output of the subtracter 4 is supplied to a multiplier 5 to be multiplied by the coefficient 2α to be used for correcting the coefficient of the adaptive filter 3. Here, α is a constant and 2α is known as a step size. Let the signal, the reference noise, the noise to be cancelled and an additional noise to the signal be S k (k being an index to represent time), n k , V k and δ k , respectively. The signal u k to be actually supplied to the subtracter 4 from the input terminal 1 is given by the following expression: u k = S k + V k + δ k A purpose of the noise cancellers is to generate the noise replica V k of the noise components v k in the above expression (1) for cancelling the noise. The noise replica V k is adaptively generated by using a closed loop comprising the adaptive filter 3, the subtracter 4 and the multiplier 5 in FIG. 14. The closed loop provides the difference or error signal d k given by the following expression as the output signal from the subtracter 4. However, it is to be noted that δ k is sufficiently small as compared to S k and is neglected in the expression: d k = S k + v k - V k In the above expression (2), (v k - V k ) is known as a residual noise. In the LMS algorithm, the m-th coefficient C m.k of the adaptive filter 3 is corrected in accordance with the following expression: C m,k = C m,k-1 + 2α·d k ·n m,k-1 A matrix format of the expression (3) for all of the N coefficients is as follows: C k = C k-1 + 2α·d k ·n k-1 Where, C k and n k are given by the following expressions, respectively: C k = [C 0 C 1 ... C N-1 ] T n k = [n k n k-1 .. n k-N+1 ] T Here, [·] T represents a transposition of the matrix. On the other hand, in the LIM algorithm, correction of coefficients will be carried out in accordance with the following expression (7) rather than the expression (4). C k = C k-1 + (2µ/Nσ n 2 ·d k ·n k-1 µ in the above expression (7) is the step size for LIM and σ n 2 represents an average power of the input to the adaptive filter 3. σ n 2 is used to make the step size µ counter proportional to the average power for stable convergence. There are a few methods to calculate σ n 2 . One example is to calculate in accordance with the following expression (8): The step sizes in the above expressions (4) and (7) define the converging speed of the adaptive filter and the residual noise level after convergence. In case of the LMS algorithm, if the value of α is larger, the convergence speed is faster but the final residual noise level increases. On the contrary, it is required to choose relatively small α in order to achieve a sufficiently low final residual noise level. However, this causes a relatively slow convergence speed. This is true about the step size µ in the LIM algorithm. A VS algorithm has been proposed in order to meet the conflicting requirements in the step size to the converging speed and the final residual noise. See p.p. 309-316 of the IEEE Transactions on Acoustics, Speech and Signal Processing, 1986. Vol. 34, No. 2 (referred to as Reference 4 hereunder). The VS algorithm uses step size matrix 2A instead of the step size 2α in the LMS algorithm as represented by the above expression (4). Each component of A is controlled in response to the progress in convergence of the adaptive filter. The use of individual step sizes given by the step size matrix A rather than a common step size for each coefficient allows optimum step size for each coefficient depending on variations in magnitude of the self-correlation matrix component, thereby improving the converging speed. Actual correction of the coefficients will be performed by the following expression: C k = C k-1 + 2A·d k ·n k-1 A = [a i,j ] a i,j = 0 for i ≠ j ≠ 0 for i = j a m.m is determined by the successive pattern of the polarity sgn[G m.k ] of the gradient component G m.k corresponding to the m-th tap , where G m.k is given by the following expression: G m,k = 2·α m,m ·d k ·n m,k-1 In an ideal case where d k = v k - V k , the polarity of G m.k directly represents the progress of convergence. However, d k is generally affected by S k as understood from the expression d k = S k +v k -V k . In order to reduce the influence of S k , a m.m is halved if sgn[G m,k ] changes m o times consecutively. On the other hand, it is doubled if sgn [G m.k ] are equal for m 1 times consecutively. That is, the VS algorithm features to make equivalently S k +v k -V k ≃ v k -V k by detecting succession of identical polarities or successive alternations of the polarity. However, there is a certain limitation in the variable range of a m.m . That is, the maximum value α max = 1/λ and the minimum value α min is defined by a desired final residual noise. Here, λ is the maximum inherent value of the autocorrelation matrix. The performance of the VS algorithm depends largely on the relationship between S k and v k -V k . The polarity changing pattern of the above G m.k is a function of the signal-to-noise ratio (SNR) and the spectrum of S k . When the SNR is large, |S k | > |v k -V k | is almost always true and seriously affects polarity detection. Considering the fact that SNR is defined by the ratio of the signal and the noise in mathematical expectation of their instantaneous powers, |S k | > |v k -V k | is satisfied with a greater probability as S k contains more higher- frequency components even if SNR is low. In other words, when S k has many peaks and dips, it is most likely that |S k | is larger than |v k -V k | in some of the peaks even if SNR is sufficiently low. Illustrated in FIG. 15 is a block diagram of a conventional ALE corresponding to the noise canceller in FIG. 14. A mixed signal to be supplied to an input terminal 1 comprises a wideband signal S k , a periodic signal v k and an additive noise δ k . On the other hand, supplied to an adaptive filter 3 is a delayed signal of the mixed signal on the input terminal 1 delayed by L by a delay element 8 and is given by: u k-L = S k-L + V k-L However, δ k is neglected in the above expression (11) because it is sufficiently small compared with S k . The difference signal d k given by the expression (2) is obtained by subtracting the prediction signal V k of v k generated by the adaptive filter 3 from the mixed signal u k of the expression (1). Derived from an output terminal 6 is a wideband signal with suppressed periodic interference signals. Also derived from an output terminal 7 is the enhanced periodic signals obtained by suppressing wideband noise. Coefficient correction of the adaptive filter 3 should be carried out by using (v k -V k ) which is a prediction error of the periodic signals. However, the actually derived difference signal d k contains the wideband signal S k . As a result, the above discussions on |S k | and |v k -V k | in the noise canceller are also applicable to the ALE. That is, a correct step size control in the VS algorithm depends on the relationship between|S k | and |v k -V k | and no correct step size is obtained if |S k | is larger than |v k -V k |. Illustrated in FIG. 16 is a block diagram of a conventional echo canceller corresponding to the noise canceller in FIG. 14. The block diagrams in FIGS. 16 and 14 are identical to each other but differ only in input signals. Supplied to an input terminal 1 is a signal comprising an echo v k and an additive noise δ k . u k = v k + δ k On the other hand, supplied to an adaptive filter 3 is n k through an input terminal 2. n k represents an input signal to a 2-line to 4-line conversion transformer in case of a bidirectional transmission circuit or a signal to be supplied to a speaker in case of an echo due to acoustic coupling. An echo replica V k of v k generated by the adaptive filter 3 is subtracted from u k in the expression (12) derived from the input terminal 1 to obtain the difference signal d k in the following expression (13): d k = v k - V k + δ k Derived from an output terminal 6 is the echo cancelled signal. Coefficient correction of the adaptive filter 3 should be performed using the residual echo (v k -V k ). In practice, however, the additional noise δ k is contained in the difference signal d k . Although δ k is fairly small in general, it interferes the residual echo when the residual echo becomes sufficiently small. IEEE, Speech Processing 2 Digital Signal Processing, International Conference on Acoustics, Speech and Signal Processing, vol 2. 26 May 1989, Glasgow, GB, pages 892-895, Sugiyama et al discloses a first convergence algorithm for adaptive FIR filters using the error signal s k + v k - v and k for the step size control. In order to minimize the effect of interference signals, it is required to increase both m o and m 1 and minimize α min . However, this will adversely make the advantage of the VS algorithm less attractive. Additionally, as understood from the expression (9), the VS algorithm requires to store in a memory a large number of step sizes equal to the number of coefficients, thereby requiring a large memory capacity as the number of taps increases and in turn making the hardware very expensive. It is therefore an object of the present invention to provide a method and an apparatus for controlling coefficients of an adaptive filter with shorter converging time and smaller scale of hardware. This object is solved with the features of the claims. The coefficient control method and apparatus for an adaptive filter according to the present invention reduces converging time by controlling the magnitude of the step size by using the fact that the absolute values of coefficients of the adaptive filter increase and saturate as the coefficients converge. Since the absolute values of coefficients depend on the transfer function of the path to be identified, such dependency can be avoided by using the ratio of the long-time and short-time averages in the average value of the coefficients. FIG. 1 is a block diagram of one embodiment of the present invention; FIG. 2 is a detailed scheme of the adaptive filter 3 in FIG. 1; FIG. 3 is a first example of an information extraction circuit 9; FIG. 4 is a second example of an information extraction circuit 9; FIG. 5 is one example of an arithmetic circuit 10 to obtain y k ; FIG. 6 is an example of the averaging circuit; FIG. 7 is an example of the divider circuit 54; FIG. 8 is an example of the inverse circuit 32; FIG. 9 is a block diagram of adaptively controlling the step size using the filter output; FIG. 10 is a block diagram of ALE according to the present invention corresponding to the noise canceller in FIG. 1; FIG. 11 is a block diagram of ALE according to the present invention corresponding to the noise canceller in FIG.2; FIGS. 12 and 13 are block diagrams of applying the present invention to an echo canceller; FIG. 14 is a block diagram of a conventional noise canceller; FIG. 15 is a block diagram of a conventional ALE corresponding to the noise canceller in FIG. 14; and FIG. 16 is a block diagram of a conventional echo canceller corresponding to the noise canceller in FIG. 14. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail hereunder by reference to the accompanying drawings. Illustrated in FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. 14 are used to refer like functional blocks. A primary difference between FIGS. 1 and 14 is in the magnitude of the step size. That is, the step size 2α to be supplied to the multiplier 5 in FIG. 14 is fixed but varies in FIG. 1 in response to the magnitude of coefficients for the adaptive filter. For this end, there is employed an information extraction circuit 9 to extract the information relating to the magnitude of coefficients. Also employed in FIG. 1 is an arithmetic circuit 10 for controlling the step size using the extracted information. By reference to FIG. 1, supplied to the information extraction circuit 9 are the adaptive filter coefficients from the adaptive filter 3. The information extraction circuit 9 extracts the information relating to the magnitude of coefficients for supplying to the arithmetic circuit 10. The arithmetic circuit 10 performs arithmetic operation as defined by b = f[a] based on the signal a to be supplied from the information extraction circuit 9 and the output is supplied to the adaptive filter 3. Illustrated in FIG. 2 is a detailed block diagram of the adaptive filter 3 in FIG. 1. For convenience, it is assumed that the adaptive filter 3 has only 2 taps. An input signal from the input terminal 2 in FIG. 1 is supplied to an input terminal 201 in FIG. 2. Also, supplied to an input terminal 209 is the output from the subtracter 4 in FIG. 1, or the error signal. The output signal on an output terminal 212 is supplied to the subtracter 4 as the output of the adaptive filter 3 in FIG. 1. Both signals from output terminals 222 and 223 are supplied to the information extraction circuit 9. The output signal of the arithmetic circuit is supplied to an input terminal 221. The input signal to be supplied to the input terminal 201 is supplied to a delay element 202 and multipliers 205 and 207. The input signal on the input terminal 201 is also supplied to multipliers 206 and 208 after a delay equivalent to one sampling period. In other words, the signals to be supplied to the multipliers 205-206 and 207-208 have a time difference equal to one sampling period. Now, the input signal sample to be supplied to the input terminal 201 at time kT (T representing the sampling period) is represented as n k , n k and n k-1 are supplied to the multipliers 205-207 and 206-208, respectively. On the other hand, let d k and y k be the error signal to a multiplier 210 from the input terminal 209 and the signal to the multiplier 210 from the arithmetic circuit 10 by way of the input terminal 221, respectively. Then, the output from the multiplier 210 is equal to 2α·y k ·d k . The output of the multiplier 210 is multiplied by the-input signals n k and n k-1 in the multipliers 205 and 206 before being transferred to adders 213 and 214, respectively. That is, the signals to be supplied to the adders 213 and 214 are 2α·y k ·d k ·n k and 2α·y k ·d k ·n k-1 , respectively. Fedback respectively to the adders 213 and 214 are the outputs from delay elements 203 and 204, respectively. The outputs from the delay elements 203 and 204 are coefficients for the adaptive filter 3 and are represented by C o,k and C 1,k at respective time kT. Then, the added outputs transmitted to the delay elements 203 and 204 from the adders 213 and 214 will be C 0.k +2α·y k ·d k ·n k and C 1.k +2α·y k ·d k ·n k-1 , respectively. These signals are delayed by one sampling period due to the delay elements 203 and 204. Therefore, C 0,k+1 = C 0,k + 2α·y k ·d k ·n k C 1,k+1 = C 1,k + 2α·y k ·d k ·n k-1 C 0.k and C 1.k are supplied respectively to the output terminals 214 and 215 for step size control. Illustrated in FIG. 3 is a block diagram of a first example of the information extraction circuit 9, wherein a squared value of the coefficient is used as the information relating to the magnitude of the coefficients of the adaptive filter. Supplied to input terminals 30 0 30 1 , ..., 30 N-1 are N coefficients from the adaptive filter 3. It is to be noted here that N is the number of taps of the adaptive filter 3. N = 2 is the particular example of the adaptive filter 3 in FIG. 2. The signals supplied to the input terminals 30 0 , 30 1 , ..., 30 N-1 are squared by respective squaring circuits 31 0 , 31 1 , ..., 31 N-1 to be supplied to a multi-input adder 32. The multi-input adder 32 provides the sum of the squared values to be derived from its output terminal 33. Referring to the description for FIG. 2, the signal a k derived from the output terminal 33 is given by the following expression: Illustrated in FIG. 4 is a block diagram of a second example of the information extraction circuit 9, wherein absolute values of the coefficients are used as the information relating to the magnitude of the coefficients of the adaptive filter. It is to be noted that the absolute value of each coefficient saturates as adaption of the adaptive filter coefficients progresses, thereby saturating the sum of the absolute values. Accordingly, the absolute values can be used as a measure to see the degree of convergence. That is, the step size can be controlled by the sum of the absolute values of the filter coefficients instead of the squared values thereof. Supplied to the input terminals 30 0 , 30 1 , 30 2 , ..., 30 N-1 are N coefficients from the adaptive filter 3, which are then converted into the corresponding absolute values by absolute value circuits 41 0 , 41 1 , ..., 41 N-1 before being supplied to the multi-input adder 32. The multi-input adder 32 operates to provide from its output terminal 33 the sum of the absolute values a k which is given by the following expression: For simplicity, a description is given hereunder for a case where a k is defined by the expression (16). The obtained a k is supplied to the arithmetic circuit 10 which calculates and provides an output b k in accordance with the definition b k = f[a k ] . The calculated output b k is fed to the adaptive filter 3 by way of the input terminal 213. Therefore, The equations (14), (15) are basically the same as the equation (3). Only the difference is the use of a variable step size 2α.y k instead of the fixed step size 2α. A method of controlling y k , i.e., how to calculate f[·] is an essential factor to achieve high-speed, stable convergence. Illustrated in FIG. 5 is a block diagram of the arithmetic circuit 10 to obtain y k . The input signal derived from the input terminal 51 is fed to both averaging circuits 52, 53. That is, the inputs to the averaging circuits 52. 53 are a k or the output from the information extraction circuit 9. The averaging circuit 52 calculates a short-time-constant moving average [·] of the input signal while the averaging circuit 53 calculates a long-time-constant moving average · of the input signal. The outputs u k and z k from the averaging circuits 52 and 53 are given by the following expressions, respectively: The divider 54 calculates the ratio of u k and z k to provide on its output terminal 55 y k given by the following expression: Now, a k increases and saturates as k increases. The short-time average a k increases faster than the long-time average [a k ]. As a result, it is understood that the ratio y k = a k /[a k ] decreases gradually from a value larger than 1 to converge ultimately to 1. This means that the signal y k to be supplied to the output terminal 55 from the divider 54 is relatively large immediately after initiation of the coefficient correction but decreases gradually as the adaptive filter 3 continues its adaptation. Finally, it becomes equal to 1. The signal y k as obtained in the above manner is fed to the input terminal 213 in FIG. 2 as the output from the arithmetic circuit 10 in FIG. 1. The use of this value y k multiplied by the fixed step-size in accordance with the equations (14) and (15) will make the effective step-size large initially and subsequently equal to the final value 2α after convergence, thereby shortening the converging time. Illustrated in FIG. 6 is a block diagram of the averaging circuit which is known as a first-order leaky integrator with a leaky factor β (0 < β < 1). A signal supplied to its input terminal 61 is multiplied by the factor of β in an integrator 62 before being fed to an adder 63. The output from the adder 63 is fed to an output terminal 66 and also to a delay element 65. A delayed signal delayed by one clock period in the delay element 65 is multiplied by the coefficient of 1 - β in a multiplier 64 before being fed to the adder 63. The adder 63 accumulates the signals fed to the input terminal 61 with 1 clock delay, thereby integrating the signals. At this time, "leak " will be caused in the multiplier 64. As understood from the values of the multipliers 62 and 64, when the signal fed to the input terminal 61 is relatively stationary, the output signal from the output terminal 66 increases gradually before saturating. By proper selection of the constant β, the saturation value can simulate the average value of the input signal. If β is small, 1 - β is approximately 1 and the signal on the output terminal 66 is fed back to the adder 63 with no modification, thereby providing a moving averaging circuit of relatively long time constant. On the other hand, if β is large, the feedback signal from the output terminal 66 to the adder 63 will be rapidly decreasing. This will increase the contribution of the current signal fed to the multiplier 62 from the input terminal 61, thereby shortening the time constant of the moving averaging circuit. Accordingly, it is understood that the averaging circuit as illustrated in FIG. 6 can be used for the averaging circuits 52 and 53 by proper selection of the leaky factor β. When the first-order leaky integrator in FIG. 6 is used for the averaging circuits 52 and 53, the leaky factors of the averaging circuits 52 and 53 are chosen respectively as β s and β 1 to obtain the following equations from the above equations (19) and (20): As a result, y k is expressed as follows: Considering that y k is a decreasing function with z o = u o = 0, the maximum value of y k is y 1 = β s /β 1 and is constant regardless of any external condition such as coefficients of the adaptive filter and the reference signals therefor. Although FIG. 6 illustrates an example of a recursive type averaging circuit, any other circuit configuration such as a transversal type may be used as well. Illustrated in FIG. 7 is a block diagram of the divider 54 comprising an inverter and a multiplier. The signals fed to the divider 54 in FIG. 5 from the averaging circuits 52 and 53 are fed to input terminals 70 and 71, respectively. The inverter 72 provides an inverse of the signal fed to the input terminal 71 to be transferred to the multiplier 73 where the inverse signal and the signal from the input terminal 70 are multiplied before being transferred to an output terminal 74. The product on the output terminal is fed to the output terminal 55 in FIG. 5. Illustrated in FIG. 8 is a block diagram of one example of the inverse circuit 32 to simulate the inverse calculation using exponent. Let a signal to be inverted be p k and the inverse q k = 1/p k . q k may be approximated by the following linear equation: q k = -2 -2r-1 p k + 2 -r-1 ·(2 -1 +1) Here, r is the largest integer not exceeding log 2 (p k ). The equation (25) is simple to realize because it comprises exponent of 2 and additions and subtractions. The inverter in FIG. 8 operates as follows: Applied to an input terminal 800 in FIG. 8 is the signal to be fed to the inverter 72 from the input terminal 71 in FIG. 7. The signal is fed to an amplitude evaluation circuit 801 and a multiplier 809. The amplitude evaluation circuit 801 calculates the maximum integer r not exceeding log 2 (p k ) for the input signal p k . The maximum integer r is fed to a multiplier 802 which is multiplied by -1 before being transmitted to adders 803 and 804. In the adder 803, -1 is added to the signal from the multiplier 802 to obtain -r-1 to be fed to an address generation circuit 806. Added to the signal from the multiplier 802 in the adder 804 is -r-1, or the output from the multiplier 803 to feed the resulting signal -2r-1 to the address generation circuit 805. The address generation circuits 805 and 806 generate respective addresses to a RAM 807 for obtaining from the RAM exponents of 2 corresponding to the fed signals. The RAM 807 supplies to a multiplier 808 2 -2r-1 corresponding to the address generation circuit 805 while 2 -r-1 is supplied to a multiplier 810 in response to the address generation circuit 806. The multiplier 810 multiplies the signal fed from the RAM 807 by 1.5 before being fed to a multiplier 811. The multiplier 808 multiplies the signal fed from the RAM 807 by -1 before being fed to the multiplier 809. The signal -2 -2r-1 fed to the multiplier 809 is multiplied by the input signal p k fed from the input terminal 800 to be fed to the adder 811. The adder 811, then, adds the signal -2 -2r-1 p k from the multiplier 809 and the signal 1.5·2 -r-1 from the multiplier 810 to derive the resulting output -2 -2r-1 ·p k + 1.5·2 -r-1 from an output terminal 812. The output signal from the output terminal 812 is the signal to be fed to the multiplier 73 in FIG. 7. It is assumed so far that a k is defined by the equation (16), i.e., the sum of the squared values of filter coefficients is fed to the arithmetic circuit 10. However, it is to be understood that the descriptions also apply to a k defined by the equation (17), i.e., the sum of the absolute values of filter coefficients is fed to the arithmetic circuit 10. Also, similar descriptions hold true for adaptive filters having more than 2 taps. Although the above descriptions are made on the step-size control using the sum of the squared values of the filter coefficients, it is to be understood that the step-size control may be made using the information relating to the magnitude of the filter output signal instead of the filter coefficients because the average values of the adaptive filter output in either absolute or squared values will saturate as well as the absolute values in the coefficients to a stationary or a pseudo stationary input signal. Illustrated in FIG. 9 is a block diagram for adaptively controlling the step size using the filter output. A difference from the embodiment as illustrated in FIG. 1 is in that the signal to be supplied to the information extraction circuit 9 is the output from the adaptive filter 3. As a result, there is only one input in the information extraction circuit 9. However, the same construction as illustrated in FIG. 3 or FIG. 4 may be used without any correction. When there are more than one input terminals in the information extraction circuit 9, either one of the terminals may be used to feed the output from the adaptive filter 3 thereto. Also, the adaptive filter 3 may be the same as illustrated in FIG. 2 with leaving the output terminals 214 and 215 unconnected. Illustrated in FIG. 10 is a block diagram of the ALE according to the present invention corresponding to the noise canceller in FIG. 1. The mixed signal supplied to the input terminal 1 comprises a wideband signal S k , a periodic signal v k and an additional noise δ k . Fed to the adaptive filter 3 is the mixed signal on the input terminal 1 delayed by the time L in the delay element 8, or the signal u k-L given by the equation (11). A predicted signal V k of v k as generated by the adaptive filter 3 is subtracted from the mixed signal u k to obtain the difference signal d k as given by the equation (2). Derived from output terminals 6 and 7 are the wideband signal with suppressed periodic interference signal and the periodic signal enhanced by suppressing the wideband noise. Coefficient correction of the adaptive filter 3 will be carried out in the exactly same manner as the embodiment in FIG. 1 using the filter coefficients. Illustrated in FIG. 11 is a block diagram of the ALE corresponding to the noise canceller in FIG. 9. The relationship between the embodiments in FIGS. 11 and 10 is equal to that between the embodiments in FIGS. 9 and 1, thereby requiring no detailed description of FIG. 11. The present invention is also applicable to an echo canceller. Illustrated in FIGS. 12 and 13 are embodiments to apply the present invention to an echo canceller. FIGS. 12 and 13 are simply replacement of S k +v k and S k +v k -V k by v k +δ k and v k -V k +δ k in FIGS. 1 and 9. Accordingly, no detailed description will be given herein. As described hereinbefore, a difference between LIM and LMS is the use of the step size µ divided by the average power σ n 2 fed to the adaptive filter 3 instead of α. The method of varying the step size in the above description in connection with the present invention will be applied to LIM without any correction.

Claims: A method of controlling coefficients of an adaptive filter (3) for identifying an unknown system or predicting periodic signals by correcting coefficients of said adaptive filter by means of a difference signal which is obtained by subtracting an output signal of said adaptive filter from a mixed signal of the output signal from said unknown system and an interference signal, said method comprising the steps of: obtaining the information relating to the magnitude of the coefficients of said adaptive filter; and adaptively varying the adaptation step size of the coefficients of said adaptive filter in response to said obtained information. A method as defined in claim 1, wherein as said information relating to the coefficient a summed value of the squared values of the coefficients of said adaptive filter is used. A method as defined in claim 1, wherein as said information relating to the coefficient a.summed value of the absolute values of said adaptive filter coefficients is used. A method as defined in any of claims 1, 2 and 3, wherein the amount of correction in coefficients of said adaptive filter is adaptively varied in response to the ratio between the short-time average and the long-time average of the information on the magnitude of the coefficients. A coefficient control apparatus for an adaptive filter (3) comprising an adaptive filter to generate a pseudo output of an unknown system on receiving a reference signal and a first subtracter (4) for subtracting the pseudo output from a mixed signal of the output signal of the unknown system and interference signals for identifying the unknown system or predicting periodic signals, characterized by: an information extraction circuit (9) to extract information a on the magnitude of coefficients by receiving the coefficients for the adaptive filter (3); and an arithmetic circuit (10) to adaptively vary the adaptation step size of the coefficients of said adaptive filter by receiving the output a of said information extraction circuit (9) for calculating and providing a signal b which decreases as the output a increases or increases as the output a decreases; thereby correcting the coefficients of the adaptive filter (3) in response to the outputs from the first subtracter (4) and said arithmetic circuit (10) and the reference signal. An apparatus as set forth in claim 5, wherein said information extraction circuit (9) comprises a group of squaring circuits (31) each developing a squared value of each coefficient value, and a summer for developing a summed value of the outputs of said group of squaring circuits. An apparatus as set forth in claim 5, wherein said information extraction circuit (9) comprises a group of absolute value circuits (41) each developing an absolute value of each coefficient value, and a first summer for developing a summed value of the outputs of said group of absolute value circuits. An apparatus as set forth in any of claims 5 to 7, wherein said arithmetic circuit (10) comprises a first averaging circuit (52) for averaging an input signal, a second averaging circuit (53) for averaging the same input signal with a different averaging time constant from the averaging time constant in said first averaging circuit, and a divider (54) for developing a ratio of the outputs of said first averaging circuit and said second averaging circuit. An apparatus as set forth in claim 8, wherein said divider (54) comprises an inverter (72) for outputting an inverted signal of the output from said second averaging circuit (53) and a first multiplier (73) for multiplying the inverted signal with the output from said first averaging circuit (52). An apparatus of claim 9, wherein said arithmetic circuit (10) is an inverse circuit comprising: an amplitude evaluation circuit (801) to provide the maximum integer r not exceeding log 2 (X) of an input signal X; a second multiplier (802) to multiply the output of said amplitude evaluation circuit by -1; a second adder (803) to add -1 to the output of said second multiplier; a third adder (804) to provide the sum of the outputs of said second multiplier (802) and said second adder (803); a first address generation circuit (805) to provide a RAM address signal to give an exponent of 2 corresponding to the output of said third adder (804); a second address generation circuit (806) to provide a RAM address signal to give an exponent of 2 corresponding to the output of said second adder (803); a RAM (807) to provide a corresponding exponent output of 2 on receiving the outputs of said first and second address generation circuits; a third multiplier (808) to multiply the output corresponding to the address generated from said first address generation circuit in said RAM by -1; a fourth multiplier (809) to multiply the output of said third multiplier (808) by the input signal to the input terminal; a fifth multiplier (810) to multiply the output corresponding to the address generated by said second address generation circuit in said RAM by 1.5; and a fourth adder (811) to add the outputs of said fifth and fourth multipliers for outputting from the output terminal.

Inventors: SUGIYAMA AKIHIKO, SUGIYAMA, AKIHIKO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H03H21
IPC codes: H04B1, H03H21