Semiconductor memory unit used as external storage

Abstract: A semiconductor memory unit (12) is operated by supplying an electric power from a system power source (200v) used so as to be cut off at a predetermined time. The semiconductor memory unit (12) includes a volatile memory (14) for storing data that can be accessed by a host unit (10) coupled to the semiconductor memory unit, a battery (16) used as a back-up power source for the volatile memory (14), and a power supply controller (15), coupled to the system power source (200v), the battery (16) and an all-day service power source (100v) having a capacity less than that of the system power source (200v), for switching a power source by which electric power is supplied to the volatile memory (14) from the system power source (200v) to the all-day service power source (100v) when the system power source (200v) is cut off, and for switching it from the all-day service power source (100v) to the battery (16) when a service interruption of the all-day service power source (100v) occurs.

Description: The present invention relates to a semiconductor memory unit, such as a semiconductor disk unit, used as an external storage unit. In a high performance and high speed computer system such as has been proposed recently, the performance of a CPU (Central Processing Unit) is being improved rapidly with the development of semiconductor technology. Thus, it is required to improve the performance of an external storage unit coupled to the computer system. In compliance with the above requirement, a semiconductor "disk" using a semiconductor memory device capable of being electrically accessed at a high speed has been proposed as an alternative to a magnetic disk unit accessed mechanically. Due to the development of recent semiconductor technology, the capacity of the semiconductor memory device can become large and the price thereof can be decreased. However, when the power supplied to the semiconductor device is cut off, data stored therein normally disappears (volatility). Thus, in the semiconductor memory unit used as an external storage unit, it is required to provide ways for making the data not disappear (non-volatility). To achieve the above requirement, a magnetic disk unit is coupled to the semiconductor memory unit. When the power is cut off, the data stored in the semiconductor memory unit is transferred therefrom to the magnetic disk, and when the power is again supplied to the semiconductor memory unit, the data stored in the magnetic disk is returned therefrom to the semiconductor memory unit. However, as large amounts of data can be stored in the semiconductor memory unit, a long time is needed to transfer the data from the semiconductor memory unit to the magnetic disk unit and vice versa. Thus, it is difficult to save the data when a service interruption occurs; further-more, a long time is required to restart the computer system to which the semiconductor memory unit and the magnetic disk unit are coupled. Accordingly, in a conventional semiconductor memory unit, a back-up power supply is provided for the semiconductor memory device so that when a service interruption occurs, the data stored in the semiconductor memory device is maintained. FIG.1 shows an example of a conventional semiconductor memory unit. The semiconductor memory unit shown in FIG.1 is a so-called semiconductor disk unit. Referring to FIG.1, a semiconductor disk unit 2 is coupled to a host unit 1, and is used as an external storage unit. The semiconductor disk unit 2 includes a semiconductor memory portion 4 and an input/output controller 3. Data is stored in the semiconductor memory portion 4 in a format appropriate for a magnetic disk. The input/output controller 3 accesses the semiconductor memory portion 4 in accordance with instructions (e.g. a read/write command) supplied from the host unit 1 so that data read out from the semiconductor memory portion 4 is supplied to the host unit 1, and data output from the host unit 1 is written into the semiconductor memory portion 4. The semiconductor memory unit 2 is operatively coupled to a large-scale CPU in the host unit 1, and has a large capacity and high level functions. Thus, the semiconductor memory portion 4 and the input/output controller 3 require a large amount of electric power. Thus, electric power is supplied to the semiconductor memory unit 2 from the same system power source (e.g. 200v) as the host unit 1 which also requires a large amount of electric power. The semiconductor memory portion 4 is formed by DRAM (Dynamic Random Access Memory), enabling high speed operations. However data stored in the DRAM disappears when the service interruption occurs. Thus, batteries are used as the back-up power source for the DRAM (Japanese Patent Laid-Open Application No. 3-58111). That is, the semiconductor memory unit 2 is provided with a main power supply circuit 5a for converting an AC voltage (200v) supplied from the system power supply into a DC voltage (5v), a secondary battery 6a, and a primary battery 6b. The semiconductor memory unit 2 is further provided with a power monitoring circuit 5b and a power selecting circuit 5c. The power monitoring circuit 5b constantly monitors whether or not the system power source is cut off, and does so based on the output voltage of the main power supply circuit 5a. The DC voltage output from the main power supply circuit 5a is normally supplied to the semiconductor memory portion 4 via the power selecting circuit 5c. When the power monitoring circuit 5b detects that the system supply is cut off, the power selecting circuit 5c selects the secondary and primary batteries 6a and 6b so that the DC voltage is supplied from the secondary and primary batteries 6a and 6b to the semiconductor memory portion 4. Even if a service interruption occurs so that the system power source is cut off, the system power source is normally restored shortly thereafter. In addition, a relatively small amount of power is dissipated to maintain the data stored in the semiconductor memory portion 4 (the DRAM). Thus, the required capacity of each of the secondary and primary batteries 6a and 6b may be relatively small. However, there are the following disadvantages in the above conventional semiconductor memory unit 2. The system power source is generally used for the computer system. Thus, when the computer system is deactivated, the large capacity system power source, which supplies a great amount of electric current, is cut off for safety reasons. That is, the computer system is managed such that the computer system is turned off overnight and during other long periods, such as holidays, by disconnecting the system power source. The back-up power must be supplied from the batteries 6a and 6b to the semiconductor memory portion 4 during the time the computer system is turned off. In a case where the computer system is turned off during the weekend, for example, the batteries 6a and 6b must supply electric power to the semiconductor memory portion 4 for at least 48 hours. In this case, large capacity back-up batteries 6a and 6b are required in the semiconductor memory unit 2, so that the semiconductor memory unit 2 becomes large and expensive. In addition, a small-sized computer system, such as a workstation or a personal computer, may be turned off for an even longer time. In this case, the back-up batteries must have an even larger capacity. EP-A-0 187 369 discloses a semiconductor memory unit according to the preamble of accompanying claim 1. According to this document, there is no means for detecting a service interruption of the second power source (auxiliary power source) and in response for selecting between the second power source and the battery. When the first power source (main power source) is cut off, both the second power source and the battery are connected as power sources to the memory. US-A-3 980 935 discloses a similar semiconductor memory unit to that of EP-A-0 187 369. According to this document, the battery is continuously connected without any switching mechanism, leading to a possible problem of overcharging. JP-A-3 058 111 discloses a semiconductor memory unit similar to the type described above with reference to Figure 1, having both a primary battery and a secondary battery for providing backup power to a semiconductor memory. According to the present invention, there is provided a semiconductor memory unit normally operated by supplying electric power from a first power source, said first power source being liable to be cut off, said semiconductor memory unit comprising: volatile memory means for storing data that can be accessed by a host unit coupled to said semiconductor memory unit, said volatile memory means maintaining the data while electric power is supplied to it; a battery used as a back-up power source for said volatile memory means; a connection to a second power source, said second power source being available continuously when there is no service interruption of said second power source; and power supply control means, coupled to said first power source, said battery, and said second power source, for switching a power source by which electric power is supplied to said volatile memory means from said first power source to said second power source when said first power source is cut off, and for providing electric power from said battery as a backup for said second power source when a service interruption of said second power source occurs, said power supply control means having detection means including first detection means for detecting whether or not said first power source is cut off, and selecting means for selecting a power source by which electric power is supplied to said volatile memory means from among said first and second power sources and said battery based on results obtained by said detection means, said selecting means including first selecting means for selecting said first power source when said first detection means detects that said first power source is not cut off; characterised in that: said power supply control means is operable to switch the source by which electric power is supplied from said second power source to said battery when a service interruption of said second power source occurs, by means of: second detection means for detecting whether or not a service interruption of said second power source has occurred; second selecting means for selecting said second power source when said first detection means detects that said first power source is cut off; and third selecting means for selecting said battery when said first detection means detects that said first power source is cut off and said second detection means detects that a service interruption of said second power source has occurred. An embodiment of the present invention may provide a novel and useful semiconductor memory unit to be used as an external storage unit in which the disadvantages of the aforementioned prior art are eliminated. An embodiment of the present invention may provide a semiconductor memory unit in which the electric power can be supplied to the semiconductor memory for a long time without a large capacity battery, when the system power supply is cut off. In the present invention, when the first power supply is cut off (disconnected), a power source by which electric power is supplied to the volatile memory means is switched from the first power source to the second power source. The power back-up of the volatile memory means can be provided by the second power source for a long time without a large capacity battery. That is, the time for which the electric power is supplied from the battery to the volatile memory means is reduced, so that the capacity of the battery can be also reduced. Reference is made, by way of example, to the accompanying drawings in which: FIG.1 is a block diagram illustrating a conventional semiconductor memory unit; FIG.2 is a block diagram illustrating an essential part of a semiconductor memory unit according to an embodiment of the present invention; FIG.3 is a block diagram illustrating the semiconductor memory unit according to the embodiment of the present invention; FIG.4 is a block diagram illustrating a power supply controller shown in FIG.3; and FIG. 5A and 5B are tables illustrating operations of the power supply controller. A description will now be given of the principle of an embodiment of the present invention with reference to FIG.2. Referring to FIG.2, a host unit 1 (a host computer) is coupled with a semiconductor memory unit 2 (e.g. a semiconductor disk unit). The electric power is supplied from a system power source (e.g. 200v) to the host unit 1. The system power source has a large capacity (e.g. in the range between a few hundred amperes and a few thousand amperes). The semiconductor memory unit 2 includes an input/output controller 3, a volatile semiconductor memory 4, a power controller 5 and a battery 6. The input/output controller 3 performs the input/output control of data between the host unit 1 and the semiconductor memory 4. The semiconductor memory unit 2 is connected to the system power source and to an all-day service power source (mains electricity supply) (e.g. 100v). The all-day service power source can be used for the semiconductor memory all day. The capacity of the all-day service power source is a few tens of amperes less than that of the system power source. The power supply controller 5 selects either the system power source, the all-day service power source or the battery 6, and the electric power is supplied from the selected power source to the input/output controller 3 and the semiconductor memory 4 via the power supply controller 5. The electric power is normally supplied from the system power source to the semiconductor memory unit 2. When the system power source is cut off along with the shutting down of the host unit 1, the power supply controller 5 detects that the system power source is disconnected and selects the all-day service power source. As a result, the electric power is supplied from the all-day service power source to the semiconductor memory 4 via the power supply controller 5. Thus, even if the system power source is cut off, electric power is continuously supplied to the semiconductor memory 4 and the data stored in the semiconductor memory 4 is maintained. Further, when a service interruption occurs so that both the system power source and the all-day service power source are cut off, the power supply controller 5 selects the battery 6. In this case, electric power is continuously supplied from the battery 6 to the semiconductor memory 4. A description will now be given of an embodiment of the present invention with reference to FIGS. 3-5B. Referring to FIG.3, which shows a computer system, a host unit 10 (a host computer) has a channel 11 and is connected with the system power source (A) (200v) enabling a supply of high electric power. A semiconductor disk unit 12 includes an input/output controller coupled to the host unit 10 via the channel 11, a semiconductor memory 14 accessed by the input/output controller 13, a power supply controller 15, a battery 16 (a secondary battery) and a charging circuit 17. The semiconductor memory 14 stores data in accordance with a magnetic disk format. The system power source (A), an all-day service power source (B), and the battery 16 (a back-up DC power source (C)) are coupled to the power supply controller 15. The power supply controller 15 selects either the system power source (A), the all-day service power source (B) or the battery 16, and the electric power is supplied from the selected power source to the input/output controller 13 and the semiconductor memory 14 via the power supply controller 15. The electric power output from the power supply controller 15 is also supplied to the charging circuit 17, and the charging circuit 17 charges the battery 16. The semiconductor memory 14 is formed of a DRAM, and is coupled to a magnetic disk unit 20. The semiconductor disk unit 12 is always provided with electric power from the all-day service power source (B). Other equipment, such as facsimile machines and emergency lights, is also provided with electric power from the all-day service power source (B). The power supply controller 15 is formed as shown in FIG.4. Referring to FIG.4, the power supply controller 15 includes an AC-to-DC converter 57 coupled to the system power source (A), an AC-to-DC converter 58 coupled to the all-day service power source (B), a power monitoring circuit 15b, a switching circuit 15c and a voltage stabilizer 15d. The AC-to-DC converter 57 converts an AC voltage (200v) supplied from the system power source (A) into a DC voltage (5v). The AC-to-DC converter 58 converts an AC voltage (100v) supplied from the all-day service power source (B) into a DC voltage (5v). The power monitoring circuit 15b includes a first power sensor 50 connected to the AC-to-DC converter 57, a second power sensor 51 connected to the AC-to-DC converter 58, a third power sensor 52 connected to the battery 16, inverters 53 and 54, and AND gates 55 and 56. The first power sensor 50 detects whether or not the system power source (A) is cut off based on the output voltage of the AC-to-DC converter 57, and outputs a first detection signal activated when the system power source (A) is not cut off. The second power sensor 51 detects whether or not the all-day service power source (B) is cut off based on the output voltage of the AC-to-DC converter 58, and outputs a second detection signal activated when the all-day service power source (B) is not cut off. The third power sensor 52 detects whether or not electric power is being supplied from the battery 16, and outputs a third detection signal activated when the battery 16 supplies sufficient electric power. The first detection signal output from the first power sensor 50 is input, via the inverter 53, to the AND gate 55. The second detection signal output from the second power sensor is also input to the AND gate 55. The first and second detection signals output from the first and second power sensors 50 and 51 are input, via the inverters 53 and 54 respectively, to the AND gate 56. The third detection signal output from the third power sensor 52 is input to the AND gate 56. The switching circuit 15c includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and diodes D1, D2, D3 and D4 for cutting off backward currents. The first and second switches S1 and S2 are connected with the AC-to-DC converter 57 via diodes D1 and D2, respectively. The third switch S3 is connected with the AC-to-DC converter 58 via a diode D3. The fourth switch S4 is connected to the battery 16 via a diode D4. The first and second switches S1 and S2 are provided with, as a control signal, the first detection signal output from the first power sensor 50, and are opened or closed in accordance with the state of the first detection signal. The third switch S3 is provided with, as a control signal, the output signal of the AND gate 55, and is opened or closed in accordance with the state of the output signal of the AND gate 55. The fourth switch S4 is provided with, as a control signal, the output signal of the AND gate 56, and is opened or closed in accordance with the state of the output signal of the AND gate 56. The voltage stabilizer 15d includes a first voltage converter 59 (a DC-DC converter) and a second voltage converter 60 (a DC-DC converter). The first voltage converter 59 is coupled with the AC-to-DC converter 57 via the diode D1 and the first switch S1. The second voltage converter 60 is coupled with the AC-to-DC converter 57 via the diode D2 and the second switch S2, with the AC-to-DC converter 58 via the diode D3 and the third switch S3, and with the battery 16 via the diode D4 and the fourth switch S4. The first and second voltage converters 59 and 60 carry out constant voltage control of voltages supplied thereto and output constant DC voltages. The DC voltages output from the first and second voltage converters 59 and 60 are respectively supplied to the input/output controller 13 and the semiconductor memory 14. Operations of the semiconductor disk unit 12 will be described below with reference to FIGS.5A and 5B. Electric power is supplied to the semiconductor disk unit 12 normally in a state (1) shown in FIG.5A. In this state (1), the power supply monitoring circuit 15b operates as shown in row No. 1 of FIG.5B. That is, the electric power is supplied from the system power source (A) to the semiconductor disk unit 12, and the first detection signal output from the first power sensor 50 is activated ("1"). Due to the activated first detection signal, the switches S1 and S2 are closed, and the DC voltage output from the AC-to-DC converter 57 coupled to the system power source (A) is supplied to both the first and second voltage converters 59 and 60 respectively via the switches S1 and S2. That is, the semiconductor memory 14 and the input/output controller 13 are provided with electric power from the system power source (A). In this case, the activated first detection signal output from the first power sensor 50 is inverted by the inverter 53 and supplied to both the AND gates 55 and 56. Thus, the output signals output from the AND gates 55 and 56 are inactive, so that the switches S3 and S4 are open. As a result, neither the AC-to-DC converter 58 nor the battery 16 supplies the voltage to the voltage stabilizer 15d. In addition, the voltage output from the AC-to-DC converter 57 is supplied to the charging unit 17, so that the battery 16 is charged by the charging circuit 17. When the host unit 10 (the computer system) is shut down for a holiday or overnight, the system power source (A) is disconnected. In this case, electric power is supplied to the semiconductor disk unit 12 in a state (2) shown in FIG.5A. In this state (2), the power supply monitoring circuit 15b operates as shown in row No.2 of FIG.5B. That is, the first detection signal output from the first power sensor 50 is inactive ("0"), and the second detection signal output from the second power sensor 51 is activated ("1") due to the electric power supplied from the all-day service power source (B). As a result, the output signal from the AND gate 55 is activated ("1"). Due to the activated output signal from the AND gate 55, the switch S3 is closed, and the DC voltage output from the AC-to-DC converter 58, coupled to the all-day service power source (B), is supplied to the second voltage converter 60 via the switch S3. That is, only the semiconductor memory 14, through the voltage converter, and the charging circuit 17, are provided with the electric power from the all-day service power source (B). In this case, as the activated second detection signal output from the second power sensor 51 is inverted by the inverter 54, the output signal from the AND gate 56 is inactive, and the switch S4 is opened. Thus, the voltage output from the battery 16 is not supplied to the voltage stabilizer 15d. In addition, the voltage output from the AC-to-DC converter 58 is supplied to the charging circuit 17, so that the battery 16 is charged by the charging circuit 17. In the above state (2), as the system power source (A) is cut off, neither the host unit 1 nor the input/output controller 13 in the semiconductor disk unit 12 is provided with electric power. Thus, in a state where the system is shut down, only the semiconductor memory 14 is provided with electric power, and the data stored in the semiconductor memory 14 is maintained. Further, when a service interruption of the all-day service power source (B) occurs, electric power is supplied from neither the system power source (A) nor the all-day service power source (B) to the semiconductor disk unit 12. In this case, electric power is supplied to the semiconductor disk unit 12 in a state (3) shown in FIG.5A. In this state (3), the power source monitoring circuit 15b operates as shown in row No.3 of FIG.5B. That is, both the first and second detection signals, output from the first and second power sensors 50 and 51 respectively, are inactive, and only the third detection signal output from the third power sensor 52 is activated. Thus, the switches S1, S2 and S3 are opened, and only the switch S4 is closed. The electric power is supplied from the battery 16 (the back-up power source (C)) to the second voltage converter 60, and the output voltage from the second voltage converter 60 is supplied to the semiconductor memory 14. As a result, even if both the system power source (A) and the all-day service power source (B) are cut off, due to the electric power supply from the battery 16 (the back-up power source (C)), the data stored in the semiconductor memory 14 is maintained. Service interruption of the all-day service power source (B) is normally restored within two hours. Thus, it is sufficient to provide the battery 16 with a capacity sufficient for enabling continuous supply of electric power to the semiconductor memory 14 for four hours. However, if a service interruption of the all-day service power source continues for much more than four hours, neither the system power source (A), the all-day service power source (B), nor the battery 16 (the back-up power source (C)) supplies electric power to the semiconductor disk unit 12. In this case, the power supply monitoring circuit 15b operates as shown in row (4) of FIG.5B. That is, all the first, second and third detection signals respectively output from the first, second and third power sensors 50, 51 and 52, are inactive ("0"), and all the switches S1-S4 are open. Thus, neither the input/output controller 13 nor the semiconductor memory 14 is provided with electric power, so that the data stored in the semiconductor memory 14 is lost. The capacity of the battery 16, however, can be determined based on a time slightly longer than that for which the service interruption of all-day service power source normally lasts. According to the above embodiment, even if the system power source (A) is cut off for a night or a weekend, the semiconductor memory 14 is provided with electric power from the all-day service power source (mains supply) (B) instead of the system power source (A). That is, the battery 16 does not need to supply electric power to the semiconductor memory 14 when the system power source (A) is cut off. The battery 16 must supply electric power to the semiconductor memory 14 only when a service interruption (power cut) of the all-day service power source (B) occurs. Service interruption of the all-day service power source can normally be restored within a short time. Thus, the capacity of the battery used as the back-up power source for the semiconductor memory 14 can be reduced. When maintenance of this system is needed, the data stored in the semiconductor memory 14 is transferred to the magnetic disk unit 20. The host unit 10 may be a large-sized computer, a small-sized computer, a work station, a personal computer or the like. The semiconductor memory unit according to the present invention is not limited to the semiconductor disk unit 12 as has been described above. The present invention may be applied to various types of semiconductor memory unit. The battery 16 may be a primary battery, and a set comprising a secondary battery and a primary battery can be provided, as the back-up battery for the semiconductor memory 14 in the semiconductor disk unit 12. The present invention is not limited to the aforementioned embodiments, and variation and modifications may be made without departing from the scope of the claimed invention.

Claims: A semiconductor memory unit (2,12) normally operated by supplying electric power from a first power source, said first power source being liable to be cut off, said semiconductor memory unit comprising: volatile memory means (4,14) for storing data that can be accessed by a host unit (1,10) coupled to said semiconductor memory unit (2,12), said volatile memory means maintaining the data while electric power is supplied to it; a battery (6,16) used as a back-up power source for said volatile memory means; a connection to a second power source, said second power source being available continuously when there is no service interruption of said second power source; and power supply control means (5,15), coupled to said first power source, said battery (6,16), and said second power source, for switching a power source by which electric power is supplied to said volatile memory means (4,14) from said first power source to said second power source when said first power source is cut off, and for providing electric power from said battery as a backup for said second power source when a service interruption of said second power source occurs, said power supply control means (5,15) having detection means (50,51) including first detection means (50) for detecting whether or not said first power source is cut off, and selecting means (53-56,S2-S4) for selecting a power source by which electric power is supplied to said volatile memory means (4,14) from among said first and second power sources and said battery (6,16) based on results obtained by said detection means (50,51), said selecting means including first selecting means (S2) for selecting said first power source when said first detection means (50) detects that said first power source is not cut off; characterised in that: said power supply control means is operable to switch the source by which electric power is supplied from said second power source to said battery when a service interruption of said second power source occurs, by means of: second detection means (51) for detecting whether or not a service interruption of said second power source has occurred; second selecting means (53,55,S3) for selecting said second power source when said first detection means (50) detects that said first power source is cut off; and third selecting means (53,54,56,S4) for selecting said battery when said first detection means detects that said first power source is cut off and said second detection means (51) detects that a service interruption of said second power source has occurred. A semiconductor memory unit as claimed in claim 1, wherein said semiconductor memory unit (2,12) is a semiconductor disk unit in which data is stored in said volatile memory means (4,14) in accordance with a magnetic disk format. A semiconductor memory unit as claimed in claim 1, wherein said battery (6,16) is a secondary battery which is rechargeable. A semiconductor memory unit as claimed in claim 1, wherein a mains supply is used as said second power source. A semiconductor memory unit as claimed in claim 1, wherein: said first detection means is a first power sensor (50) having an input connected to a system power source constituting said first power source; said second detection means is a second power sensor (51) having an input connected to a mains electricity supply constituting said second power source; a third power sensor (52) is provided, having an input connected to said battery; and a charging circuit (17) is provided connected to an input of said battery; and wherein said selecting means comprises: a first switch (S2) disposed between said system power source and said volatile memory (4,14) and said charging circuit (17), said first switch (S2) being operatively connected to an output of said first power sensor (50); a second switch (S3) disposed between said mains electricity supply and said volatile memory (4,14) and said charging circuit (17), said second switch (S3) being operatively connected to an output of said second power sensor (51); and a third switch (S4) disposed between said battery (6,16) and said volatile memory (4,14), said third switch (S4) being operatively connected to an output of said third power sensor (52). A semiconductor memory unit as claimed in claim 5, wherein: said operative connections of said first, second, and third power sensors (50,51,52) to said first, second, and third switches (S2-S4) are formed by an array of logic gates (53-56); and said array operates said first, second, and third switches (S2-S4) based on outputs of said first, second, and third power sensors (50-52) to connect said mains electricity supply to said volatile memory (4,14) and said charging circuit (17) when said first sensor (50) detects that said system power source is off, and to connect said battery (6,16) to said volatile memory (4,14) when said first sensor (50) detects that said system power source is off and said second sensor (51) detects that said mains electricity supply is off.

Inventors: NAGASAWA SOICHIRO, NAGASAWA, SOICHIRO, Nagasawa, Soichiro, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G06F1
IPC codes: G06F12, G06F1