Apparatus to solve a system of linear equations

Abstract: A linear calculating equipment comprises a memory for storing a coefficient matrix, a known vector and an unknown vector of a given system of linear equations, a pivoting device for choosing pivots of the matrix, a plurality of preprocessors for executing K steps of preprocessing for multi-pivot simultaneous elimination, an updating device for updating the elements of the matrix and the components of the vectors, a register set for storing values of the variables, a back-substitution device for obtaining a solution and a main controller for controlling the linear calculating equipment as a whole.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to apparatus for solving systems of linear equations, parallel computer for solving systems of linear equations, and methods of parallel computation for solving systems of linear equations. 2. Description of the Related Art The need for solving systems of linear equations at high speed frequently arises in numerical analysis of the finite element method and the boundary element method and other processes of technical calculation. Among algorithms based on direct methods of solving systems of linear equations is Gauss elimination method based on bi-pivot simultaneous elimination, which is described in Takeo Murata, Chikara Okuni and Yukihiko Karaki, "Super Computer--Application to Science and Technology," Maruzen, 1985. pp 95-96. The bi-pivot simultaneous elimination algorithm eliminates two columns at the same time by choosing two pivots at one step. It limits simultaneous elimination to two columns and the choice of pivots to partial pivoting by row interchanges. Furthermore it considers the speeding up of its process in terms of numbers of repetition of do-loops only. If simultaneous elimination is not limited to two columns and extended to more than two columns, the corresponding algorithms will be hereafter called multi-pivot simultaneous elimination algorithms. A similar algorithm to multi-pivot simultaneous elimination algorithms is described in Jim Armstrong, "Algorithm and Performance Notes for Block LU Factorization," International Conference on Parallel Processing, 1988, Vol. 3, pp 161-164. It is a block LU factorization algorithm intended to speed up matrix operations and should be implemented in vector computers or computers with a few multiplexed processors. Therefore, according to prior art, there has not yet been developed Gauss elimination method or Gauss-Jordan elimination method which is based on multi-pivot simultaneous elimination and can be efficiently implemented in scalar computers and parallel computers. SUMMARY OF THE INVENTION The object of the present invention is therefore to provide high-speed parallel calculating equipment and methods of parallel computation for solving systems of linear equations by means of Gauss elimination method and Gauss-Jordan's method based on multi-pivot simultaneous elimination. In order to achieve the aforementioned objective, according to one aspect of the present invention, there are provided a memory that stores reduced coefficient matrices A (r) with zeroes generated from the first to the r-th column and corresponding known vectors b (r) and an unknown vector x expressed by A ( r ) = ( a ( r ) ij ), 1 ≤ i , j ≤ n , b ( r ) = ( b ( r ) 1 , b ( r ) 2 , . . . , b ( r ) n ) t , x = ( x 1 , x 2 , . . . , x n ) t for a given system of linear equations A (0) x = b (0) . a pivot choosing section that is connected to the memory, chooses a pivot in the i-th row of A (i-1) , and interchanges the i-th column with the chosen pivotal column, a preprocessing section A 1 that, immediately after the pivot choosing section's above operation determines the transposed pivot a ( pk ) pk +1 pk +1 , calculates a ( pk +1) pk +1 j = a ( pk ) pk +1 j / a ( pk ) pk +1 pk +1 for pk + 2 ≤ j ≤ n and b ( pk +1) pk +1 = b ( pk ) pk +1 /a ( pk ) pk +1 pk +1 , k - 1 preprocessing sections A t , where t = 2, 3, . . . , k, each of which is connected to the memory and calculates Reg (0) pk + t = a ( pk ) pk + tpk +1 , Reg (1) pk + t = a ( pk ) pk + tpk +2 - Reg (0) pk + t a ( pk +1) pk +1 pk +2 , . . . , for pk + t ≤ j ≤ n, and, immediately after the pivot choosing section determines the transposed pivot a ( pk + t -1) pk + tpk + t , calculates a ( pk + t ) pk + tj = a ( pk + t -1) pk + tj / a ( pk + t -1) pk + tpk + t , b ( pk + t ) pk + t = b ( pk + t -1) pk + t / a ( pk + t -1) pk + tpk + t for pk + t + 1 ≤ j ≤ n, an updating section B that is connected to the memory, comprises a set of k registers and an arithmetic unit, and calculates Reg (0) i = a ( pk ) ipk +1 , Reg (1) i = a ( pk ) ipk +2 - Reg (0) i a ( pk +1) pk +1 pk +2 , for (p + 1)k + 1 ≤ i, j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, a back-substitution section that is connected to the memory and obtains the value of the unknown vector x by calculating x i = b ( n ) i and b ( n + h - i +1) h = b ( n + h - i ) h - a ( h ) hi x i for 1 ≤ h ≤ i - 1 for i = n, n - 1, . . . , 1 in this order of i, and a main controller G that, if n is a multiple of k, instructs the pivot choosing section, the preprocessing sections A 1 , . . . , A k , and the updating section B to repeat their above operations for p = 0, 1, . . . , n/k - 2, and instructs the pivot choosing section and the preprocessing sections A 1 , . . ., A k to execute their above operations for p = n/k -1, and, if n is not a multiple of k, instructs the pivot choosing section, the preprocessing sections A 1 , . . . , A k , and the updating section B to repeat their above operations for p = 0, 1, ... [n/k] - 1, where [x] denotes the greatest integer equal or less than x, and instructs the pivot choosing section and the preprocessing sections A 1 , . . . , A n-[n/k]k to execute their above operations, and in both cases, instructs the back-substitution section to obtain the unknown vector x. According to another aspect of the present invention there are provided a memory that stores coefficient matrices A (r) , known vectors b (r) and the unknown vector x expressed by (1) for a given system of linear equations (2), a pivot choosing section that is connected to the memory, chooses a pivot in the i-th row of A (i-1) , and interchanges the i-th column with the chosen pivotal column, a preprocessing section A 1 that, immediately after the pivot choosing section's above operation determines the transposed pivot (3), calculates (4) for pk + 2 ≤ j ≤ n and (5), k - 1 preprocessing sections A t , where t = 2, 3, . . . , k, each of which is connected to the memory, calculates (6), (7), . . . , (10) for pk + t ≤ j ≤ n, and, immediately after the pivot choosing section determines the transposed pivot (11), calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, an updating section B' which is connected to the memory, comprises a set of k registers and an arithmetic unit, and calculates (14), (15), . . . , (18) for 1 ≤ i ≤ pk, (p + 1)k + 1 ≤ i ≤ n, (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k and p < [n/k] and for 1 ≤ i ≤ [n/k]k, [n/k]k + 1 ≤ j ≤ n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, k - 1 postprocessing sections C t , where t = 1, 2, . . . , k - 1, each of which is connected to the memory and calculates Reg (0) = a ( pk + t ) pk +1 pk + t +1 , Reg (1) = a ( pk + t ) pk +2 pk + t +1 , . . . , Reg ( t -1) = a ( pk + t ) pk + tpk + t +1 , a ( pk + t +1) pk +1 j = a ( pk + t ) pk +1 j - Reg (0) a ( pk + t +1) pk + t +1 j , a ( pk + t +1) pk +2 j = a ( pk + t ) pk +2 j - Reg (1) a ( pk + t +1) pk + t +1 j , . . . , a ( pk + t +1) pk + tj = a ( pk + t ) pk + tj - Reg ( t -1) a ( pk + t +1) pk + t +1 j , b ( pk + t +1) pk +1 = b ( pk + t ) pk +1 - Reg (0) b ( pk + t +1) pk + t +1 , b ( pk + t +1) pk +2 = b ( pk + t ) pk +2 - Reg (1) b ( pk + t +1) pk + t +1 , . . . . . b ( pk + t +1) pk + t = b ( pk + t ) pk + t - Reg ( t -1) b ( pk + t +1) pk + t +1 for pk + t + 2 ≤ j ≤ n, a main controller J that, if n is a multiple of k, instructs the pivot choosing section, the preprocessing sections A 1 , . . . , A k , the updating section B', and the postprocessing sections C 1 , . . . , C k-1 to repeat their above operations for p = 0, 1, . . . , n/k - 1, and, if n is not a multiple of k, instructs the pivot choosing section, the preprocessing sections A 1 , . . . , A k , the updating section B', and the postprocessing sections C 1 , . . . , C k-1 to repeat their above operations for p = 0, 1, . . . [n/k] - 1, and instructs the pivot choosing section, the preprocessing sections A 1 , . . . , A n-[n/k]k , the updating section B', and the postprocessing sections C 1 , . . . , C n-[n/k]k to execute their above operations for p = [k/n]. According to another aspect of the present invention there is provided a system of nodes α 0 , . . . . , α P-1 , each of which is connected to each other by a network and comprises: a memory that stores blocks of k rows of each coefficient matrix A (r) and corresponding k components of each known vector b (r) and an unknown vector x expressed by (1) for a given system of linear equations (2), a pivot choosing section that is connected to the memory, chooses a pivot in the i-th row of A (i-1) , and interchanges the i-th column with the chosen pivotal column, a preprocessing section A 1 that is connected to the memory and calculates (4) for pk + 2 ≤ j ≤ n and (5), k - 1 preprocessing sections A t , where t = 2, 3, . . . , k, each of which is connected to the memory, calculates (6), (7), . . . , (10) for pk + t ≤ j ≤ n, and calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, an updating section B that is connected to the memory, comprises a set of k registers and an arithmetic unit, and calculates (14), (15), . . . , (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, a back-substitution section that is connected to the memory and obtains the unknown x by back-substitution, that is, by calculating (19) and (20), a gateway that is connected to the memory and is a junction with the outside, and a transmitter that is connected to the memory and transmits data between the memory and the outside through the gateway. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the node α u , then the pivot choosing section of the node α u determines the pivot (3), and the preprocessing section of the node α u calculates (4) and (5) for pk + 2 ≤ j ≤ n, and the transmitter transmits the results to the memory of every other node through the gateway, while the updating section B of the node in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A 1 . The preprocessing section A t of the above node α u calculates (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n, and, immediately after the pivot choosing section of α u determines the pivot (11), calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter transmits the results to the memory of every other node through the gateway, while the updating section B of the node in charge of the i-th row calculates for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A t , where 2 ≤ t ≤ k. The updating section B of each node in charge of the i-th row such that (p + 1)k + 1 ≤ i ≤ n also calculates (14) through (18) retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operations are below called parallel updating B. According to a further aspect of the present invention there is provided a main controller G p that is connected to the system of nodes by the network, distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the nodes in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to the memory of one node in the cyclic order of α 0 , . . . , α P-1 , α 0 , α 1 , . . . , and, if n is a multiple of k, instructs each node to execute parallel preprocessing A 1 through A k and parallel updating B for p = 0, 1, . . . , n/k - 1, and, if n is not a multiple of k, instructs each node to execute parallel preprocessing A 1 through A k and parallel updating B for p = 0, 1, . . . , [n/k] - 1 and to execute parallel preprocessing A 1 through A n-[n/k]k for p = [n/k], and instructs the nodes to obtain unknown vector by means of back-substitution. According to another aspect of the present invention there is provided a system of nodes α 0 , . . . . , α P-1 , each of which is connected to each other by a network and comprises: a memory that stores blocks of k rows of each coefficient matrix A (r) and corresponding k components of each known vector b (r) and an unknown vector x expressed by (1) for a given system of linear equations (2), a pivot choosing section that is connected to the memory, chooses a pivot in the i-th row of A (i-1) , and interchanges the i-th column with the chosen pivotal column, a preprocessing section A 1 that is connected to the memory and calculates (4) for pk + 2 ≤ j ≤ n and (5), k - 1 preprocessing sections A t , where t = 2, 3, . . . , k, each of which is connected to the memory, calculates (6), (7), . . . , (10) for pk + t ≤ j ≤ n, and calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, an updating section B' that is connected to the memory, comprises a set of k registers and an arithmetic unit, and calculates (14), (15), . . . , (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, k - 1 postprocessing sections C t , where t = 1, 2, . . . , k - 1, each of which is connected to the memory and calculates (21), (22), . . . , (29) for pk + 2 + 2 ≤ j ≤ n, a gateway that is connected to the memory and is a junction with the outside, and a transmitter that is connected to the memory and transmits data between the memory and the outside through the gateway. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the node α u , then the pivot choosing section of α u determines the pivot (3), and the preprocessing section of α u calculates (4) and (5) for pk + 2 ≤ j ≤ n, and the transmitter transmits the results to the memory of every other node through the gateway, while the updating section B of the element processor in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A 1 . The preprocessing section A t of the node α u calculates (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n, and, immediately after the pivot choosing section 2 of α u determines the pivot (11), calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter transmits the results to the memory of every other node through the gateway, while the updating section B' of the node in charge of the i-th row calculates (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A t , where 2 ≤ t ≤ k. The updating section B' of each node in charge of the i-th row such that 1 ≤ i ≤ pk or (p + 1)k + 1 ≤ i ≤ n if n is a multiple of k or p < [n/k] and 1 ≤ i ≤ [n/k]k otherwise also calculates (14) through (18) for (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for [n/k]k + 1 ≤ j ≤ n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operations are below called parallel updating B'. The postprocessing section C t of the above node α u calculate (21), (22), . . . , (29) for pk + t + 2 ≤ j ≤ n for t = 1, 2, . . . , k - 1 if n is a multiple of k or p < [n/k] and for t = 1, 2, . . . , n - [n/k]k otherwise. This series of operations is below called post-elimination C. According to a further aspect of the present invention there is provided a main controller J p that is connected to the system of nodes by the network, distributes the rows of the coefficient matrix A (0) and the components of b (0) and x to the coefficient matrix A (0) and the components of b (0) and x to the nodes in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to the memory of one node in the cyclic order of α 0 , . . . , α P-1 , α 0 , α 1 , . . . , and, if n is a multiple of k, instructs each node to execute parallel preprocessing A 1 through A k , parallel updating B' and post-elimination C for p = 0, . . . , n/k - 1, and, if n is not a multiple of k, instructs each node to execute parallel preprocessing A 1 through A k , parallel updating B' and post-elimination C for p = 0, 1, . . . , [n/k] - 1 and to execute parallel preprocessing A 1 through A n-[n/k]k , parallel updating B', and post-elimination C for p = [n/k]. According to another aspect of the present invention there is provided an element processor comprising: a pivot choosing section that, for coefficient matrices A (r) , known vectors b (r) and an unknown vector x expressed by (1) for a given system of linear equations (2), chooses a pivot in the i-th row of A (i-1) and interchanges the i-th column with the chosen pivotal column, a preprocessing section A 1 that is connected to the pivot choosing section and calculates (4) for pk + 2 ≤ j ≤ n and (5), k - 1 preprocessing sections A t , where t = 2, 3, . . . , k, each of which is connected to the pivot choosing section, calculates (6), (7), . . . , (10) for pk + t ≤ j ≤ n, and calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, an updating section B which is connected to the pivot choosing section, comprises a set of k registers and an arithmetic unit, and calculates (14), (15), . . . , (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, a back-substitution section that is connected to the pivot choosing section and obtains the unknown x by back-substitution, that is, by calculating (19) and (20), and a gateway that is connected to the pivot choosing section and is a junction with the outside. According to a further aspect of the present invention there is provided a system of clusters, CL 0 , . . . , CL P-1 , each of which is connected to each other by a network and comprises: above element processors PE 1 , . . . , PE P c , a memory that stores blocks of k rows of each coefficient matrix A (r) and corresponding k components of each known vector b (r) and the unknown vector x, a C gateway that is a junction with the outside, and a transmitter that transmits data between the memory and the outside through the C gateway. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the cluster CL u , then the pivot choosing section, the updating section and the back-substitution section of each element processor of CL u take charge of part of the k rows and 2k components row by row, while the preprocessing section A t of each element processor of CL u takes charge of elements of the (pk + t)th row of A (r) and the (pk + t)th component of b (r) one by one. Specifically, the pivot choosing section of the element processor PE 1 of CL u determines the transposed pivot (3) of the (pk + 1)th row, and the preprocessing sections A 1 of element processors of CL u simultaneously calculate (4) and (5) for pk + 2 ≤ j ≤ n and (5) with each A 1 calculating for elements and components in its charge, and the transmitter transmits the results to the memory of every other cluster through the C gateway, while the updating section B of the element processor in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA 1 . The preprocessing sections A t of the above cluster CL u simultaneously calculate (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n with each A t calculating for elements and components in its charge, immediately after the pivot choosing section of PE t of CL u determines the pivot (11), simultaneously calculate (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter transmits the results to the memory of every other cluster through the C gateway, while the updating section B of the element processor in charge of the i-th row calculates (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA t , where 2 ≤ t ≤ k. The updating sections B of each element processor in charge of the i-th row such that (p + 1)k + 1 ≤ i ≤ n calculate (14) through (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operation are below called parallel updating B c . According to a further aspect of the present invention there is provided a main controller G pc that is connected to the above system, distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the clusters in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to the memory of one cluster in the cyclic order of CL 0 , . . . , CL P-1 , CL 0 , CL 1 , . . . , and, if n is a multiple of k, instructs each cluster to execute parallel preprocessing CLA 1 through CLA k and parallel updating B c for p = 0, 1, . . . , n/k - 2 and to execute CLA 1 through CLA k for p = n/k - 1, and, if n is not a multiple of k, instructs each cluster to execute CLA 1 through CLA k and B c for p = 0, 1, . . . , [n/k] - 1 and to execute CLA 1 through CLA n-[n/k]k for p = [n/k], and instructs each cluster to obtain the unknown vector x by means of the back-substitution sections of its element processors and its transmitter. According to another aspect of the present invention there is provided an element processor comprising: a pivot choosing section that, for coefficient matrices A (r) , known vectors b (r) and an unknown vector x expressed by (1) for a given system of linear equations (2), chooses a pivot in the i-th row of A (i-1) and interchanges the i-th column with the chosen pivotal column, a preprocessing section A 1 that is connected to the pivot choosing section and calculates (4) for pk + 2 ≤ j ≤ n and (5), k - 1 preprocessing sections A t , where t = 2, 3, . . . , k, each of which is connected to the pivot choosing section, calculates (6), (7), . . . , (10) for pk + t ≤ j ≤ n, and calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, an updating section B' which is connected to the pivot choosing section, comprises a set of k registers and an arithmetic unit, and calculates (14), (15), . . . , (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, k - 1 postprocessing sections C t , where t = 1, 2, . . . , k - 1, each of which is connected to the pivot choosing section and calculates (21), (22). . . , (29) for pk + t + 2 ≤ j ≤ n, and a gateway that is connected to the pivot choosing section and is a junction with the outside. According to a further aspect of the present invention there is provided a system of clusters, CL 0 , . . . , CL P-1 , each of which is connected to each other by a network and comprises: above element processors PE 1 , . . . , PE P c , a memory that stores the coefficient matrices A (r) , the known vectors b (r) and the unknown vector x, a C gateway that is a junction with the outside, and a transmitter that transmits data between the memory and the outside through the C gateway. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the cluster CL u , then the pivot choosing section and the updating section B' of each element processor of CL u take charge of part of the k rows and 2k components row by row, while the preprocessing section A t and postprocessing section C t of each element processor of CL u take charge of elements of the (pk + t)th row of A (r) and the (pk + t)th component of b (r) one by one. Specifically, the pivot choosing section of the element processor PE 1 of CL u determines the transposed pivot (3) of the (pk + 1)th row, and the preprocessing sections A 1 of element processors of CL u simultaneously calculate (4) and (5) for pk + 2 ≤ j ≤ n with each A 1 calculating for elements and components in its charge, and the transmitter transmits the results to the memory of every other cluster through the C gateway, while the updating section B' of the element processor in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA 1 . The preprocessing sections A t of element processors of the above cluster CL u simultaneously calculate (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n with each A t calculating for elements and components in its charge and, immediately after the pivot choosing section of PE t of CL u determines the pivot (11), simultaneously calculate (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter transmits the results to the memory of every other cluster through the C gateway, while the updating section B' of the element processor in charge of the i-th row calculates (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA t , where 2 ≤ t ≤ k. The updating section B' of each element processor in charge of the i-th row such that 1 ≤ i ≤ pk or (p + 1)k + 1 ≤ i ≤ n if n is a multiple of k or p < [n/k] and 1 ≤ i ≤ [n/k]k otherwise also calculates (14) through (18) for (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for [n/k]k + 1 ≤ j < n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operations are below called parallel updating B' c . The postprocessing sections C t of element processors of the above CL u simultaneously calculate (21), (22) , . . . , (29) for j such that pk + t + 2 ≤ j ≤ n for t = 1, 2, . . . , k - 1 if n is a multiple of k or p < [n/k] and for t = 1, 2, . . . , n - [n/k]k otherwise. This series of operations is below called postelimination C c . According to a further aspect of the present invention there is provided a main controller J pc that is connected to the above system, distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the clusters in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to the memory of one cluster in the cyclic order of CL 0 , . . . , CL P-1 , CL 0 , CL 1 , . . . , and, if n is a multiple of k, instructs each cluster to execute parallel preprocessing CLA 1 through CLA k , parallel updating B' c and parallel postelimination C c for p = 0, 1, . . . , n/k - 1, and if n is not a multiple of k, instructs each cluster to execute parallel preprocessing CLA 1 through CLA k , parallel updating B' c , and post-elimination C c for p = 0, 1, . . . , [n/k] - 1 and to execute parallel preprocessing CLA 1 through CLA n-[n/k]k , parallel updating B' c , and postelimination C c for p = [n/k]. According to another aspect of the present invention, there is provided a parallel elimination method for solving the system of linear equations (2) in a parallel computer comprising C clusters CL 1 , . . . , CL C connected by a network. Each of the clusters comprises P c element processors and a shared memory that stores part of the reduced matrices A (r) and the known vectors b (r) and the unknown vector x. This method will be carried out by means of the following parallel computer : a data distribution means that distributes the rows of the coefficient matrix A (0) and the components of b (0) and x to the shared memory of the clusters in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to the shared memory in the cyclic order of CL 1 , . . . , CL C , CL 1 , CL 2 , . . . , and assigns those distributed to the cluster's shared memory to its element processors row by row, a pivot choosing means that chooses a pivot in a row assigned to each element processor, an elementary pre-elimination means that, after the pivot choosing means chooses the pivot a ( kP c ) kP c +1 kP c +1 , calculates a ( kP c +1) kP c +1 j = a ( kP c ) kP c +1 j / a ( kP c ) kP c +1 kP c +1 , b ( kP c +1) kP c +1 = b ( kP c ) kP c +1 / a ( kP c ) kP c +1 kP c +1 , in the element processor in charge of the (kP c + 1)th row, transmits the results to the shared memory of every other cluster to which the element processor in charge of an i-th-row such that kP c + 1 ≤ i ≤ n belongs, and, for l = 2, . . . , P c , calculates for kP c + l ≤ i ≤ n in the element processor in charge of the i-th row, calculates in the element processor in charge of the (kP c + l)th row, and, after the pivot choosing means determines the pivot a ( kP c + l -1) kP c +1 kP c +1 , calculates a ( kP c + l ) kP c + lj = a ( kP c + l -1) kP c + lj / a ( kP c + l -1) kP c + lkP c + l , b ( kP c + l ) kP c + l = b ( kP c + l -1) kP c + l / a ( kP c + l -1) kP c + lkP c + l in the element processor in charge of the (kP c + l)th row, transmits the results (38) and (39) to the shared memory of every other cluster to which the element processor in charge of an i-th row such that kP c + l + 1 ≤ i ≤ n belongs, a multi-pivot elimination means that calculates in each element processor in charge of the i-th row such that (k + 1)P c + 1 ≤ i ≤ n, a means for testing if the operation of the multi-pivot elimination means was repeated [n/P c ] times, and a remainder elimination means that executes the above elementary pre-elimination means for the ([n/P c ]P c + 1)th row through the n-th row, if the above testing means judges that the operation of the multi-pivot elimination means was executed [n/P c ] times, and n is not a multiple of P c . According to a further aspect of the present invention, there is provided a parallel computation method comprising: an back-substitution means that calculates x i = b ( n ) i in the element processor in charge of the i-th row after the elimination process of the above parallel elimination method, an back-transmission means that transmits x i to the shared memory of every cluster to which the element processor in charge of an h-th row such that 1 ≤ h ≤ i - 1 belongs, an back-calculation means that calculates b ( n + h - i +1) h = b ( n + h - i ) h - a ( h ) hi x i , for 1 ≤ h ≤ i - 1 in the element processor in charge of the h-th row, and a means for testing if the operation of the elementary back-substitution means was repeated from i = n to i = 1. The solution of the system of linear equation (1) is thus obtained by the elementary back-substitution as x n = b ( n ) n , . . . , x 1 = b ( n ) 1 in this order. According to another aspect of the present invention, there is provided a parallel elimination method for solving the system of linear equations (2) in a parallel computer comprising C clusters CL 1 , . . . , CL C connected by a network. Each of the clusters comprises P c element processors and a shared memory that stores part of the reduced matrices A (r) and the known vectors b (r) and the unknown vector x. This method will be carried out by a parallel computer comprising: a data distribution means that distributes the rows of the coefficient matrix A (0) and the components of b (0) and x to the clusters in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to the shared memory in the cyclic order of CL 1 , . . . , CL C , CL 1 , CL 2 , . . . , and assigns those distributed to the cluster's shared memory to its element processors row by row, a pivot choosing means that chooses a pivot in a row assigned to each element processor, an elementary pre-elimination means that, after the pivot choosing means chooses the pivot (31), calculates (32) and (33) in the element processor in charge of the (P c k + 1)th row, transmits the results to the shared memory of every other cluster to which the element processor in charge of an i-th row such that kP c + 2 ≤ i ≤ n belongs, and, for l = 2, . . . , P c , calculates (34) for kP c + l ≤ i ≤ n in the element processor in charge of the i-th row, calculates (35) and (36) in the element processor in charge of the (kP c + l)th row, and, after the pivot choosing means chooses the pivot (37), calculates (38) and (39) in the element processor in charge of the (kP c + l)th row, and transmits the results (38) and (39) to the shared memory of every other cluster to which an element processor in charge of the i-th row such that kP c + l + 1 ≤ i ≤ n belongs, calculates, a multi-pivot elimination means that calculates (43) and (44) in each element processor in charge of the i-throw such that (k + 1)P c + 1 ≤ i ≤ n, an post-elimination means that calculates a ( r +1) ij = a ( r ) ij - a ( r ) ii + l a ( r +1) i + lj , b ( r +1) i = b ( r ) i - a ( r ) ii + l b ( r +1) i + l in the element processor in charge of the i-th row, a post-elimination processing means that calculates (45) and (46) for l = - w + q + 1 for w = 1, . . , q and q = 1, . . . , P c - 1 for kP c + 1 ≤ i ≤ kP c + q in the element processor in charge of the i-th row, a means for testing if the operation of the post-elimination means was executed [n/P c ] times, and a remainder elimination means that enables the above pre-elimination means for the ([n/P c ]P c + 1)th through the n-th rows and enables the above multi-pivot elimination means and the post-elimination means, if the above testing means judges that the operation of the post-elimination means was executed [n/P c ] times. According to a further aspect of the present invention, there is provided a search means whereby an above element processor searches for a nonzero element in the order of increasing column numbers from that diagonal element in the same row, if a diagonal element of a coefficient matrix is 0, a column number broadcasting means that notifies other element processors of the column number of a nonzero element found by the above search means, an element interchange means whereby each element processor interchanges the two elements which are in its charge and have the same column numbers as the above diagonal zero element and the found nonzero element, and a component interchange means whereby two element processors interchange the two components of the unknown vector which are in their charge and have the same component indices as the column numbers of the above diagonal zero element and the found nonzero element. According to a further aspect of the present invention, there is provided a search means whereby an above element processor searches for an element with the greatest absolute value in the order of increasing column numbers from a diagonal element in the same row, a column number broadcasting means that notifies other element processors of the column number of an element found by the above search means, an element interchange means whereby each element processor interchanges the two elements which are in its charge and have the same column number as the above diagonal element and the found element, and a component interchange means whereby two element processors interchange the two components of the unknown vector which are in their charge and have the same component indices as the column numbers of the above diagonal element and the found component. The present invention will be carried out by an apparatus according to the attached independent claims 1, 2, 5, 8. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a block diagram of a linear calculating equipment according to the first embodiment of the present invention. Fig. 2 is a flow chart of a control algorithm to be performed in the first embodiment. Fig. 3 is a block diagram of a linear calculating equipment according to the second embodiment of the present invention. Fig. 4 is a flow chart of the control algorithm to be performed in the second embodiment. Fig. 5 is a block diagram of a parallel linear calculating equipment according to the third embodiment of the present invention. Fig. 6 is a block diagram of a node shown in Fig. 5. Fig. 7 is a flow chart of the control algorithm to be performed in the third embodiment. Fig. 8 is a block diagram of a parallel linear calculating equipment according to the fourth embodiment of the present invention. Fig. 9 is a block diagram of a node shown in Fig. 8. Fig. 10 is a flow chart of the control algorithm to be performed in the fourth embodiment. Fig. 11 is a block diagram of a parallel linear calculating equipment according to the fifth embodiment of the present invention. Fig. 12 is a block diagram of a cluster shown in Fig. 11. Fig. 13 is a block diagram of an element processor shown in Fig. 12. Fig. 14 is a flow chart of the control algorithm to be performed in the fifth embodiment. Fig. 15 is a block diagram of a parallel linear calculating equipment according to the sixth embodiment of the present invention. Fig. 16 is a block diagram of a cluster shown in Fig. 15. Fig. 17 is a block diagram of an element processor shown in Fig. 16. Fig. 18 is a flow chart of the control algorithm to be performed in the sixth embodiment. Fig. 19 is a block diagram of an element processor or processor module in a parallel computer which implements the 7th and 8th embodiments. Fig. 20 is a block diagram of a cluster used in the 7th and 8th embodiments. Fig. 21 is a block diagram of the parallel computation method according to the 7th embodiment. Fig. 22 is a block diagram of the parallel computation method according to the 8th embodiment. Fig. 23 is a diagram for showing the pivoting method according to the 7th and 8th embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments according to the present invention will be described below with reference to the attached drawings. Fig. 1 is a block diagram of linear calculating equipment in the first embodiment of the present invention. In Fig. 1, 1 is a memory; 2 is a pivoting section connected to the memory 1; 3, 4, 5 are preprocessing sections A 1 , A t , A k respectively, each connected to the memory 1; 6 is an updating section B connected to the memory 1; 7 is a back-substitution section connected to the memory 1; 8 is a main controller G; 101 is a register set composed of k registers; 102 is an arithmetic unit. Following is a description of the operation of each component of the first embodiment. The memory 1 is ordinary semiconductor memory and stores reduced coefficient matrices A (r) with zeroes generated from the first to the r-th column and corresponding known vectors b (r) and an unknown vector x expressed by (1) for a given system of linear equations (2). The pivoting section is connected to the memory 1, chooses a pivot in the i-th row following the instruction of the main controller G (8) when the first (i - 1) columns are already reduced, and interchanges the i-th column with the chosen pivotal column and the i-th component with the corresponding component of x. The choice of the pivot is based on a method called partial pivoting whereby an element with the largest absolute value in the i-th row is chosen as the pivot. The interchange can be direct data transfer or transposition of column numbers and component indices. Immediately after the pivoting section (2) determines the transposed pivot (3), the preprocessing section A 1 (3) calculates the expression (4) for pk + 2 ≤ j ≤ n and the expression (5) following the instruction of the main controller G. Each preprocessing sections A t (4), where t = 2, 3, . . . , k, is connected to the memory (1), calculates the expressions (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n, and, immediately after the pivoting section determines the transposed pivot (11), calculates expressions (12) and (13) for pk + t + 1 ≤ j ≤ n following the instruction of the main controller G (8). The updating section B (6) is connected to the memory (1), comprises a register set (101) of k registers and an arithmetic unit (102), and calculates expressions (14), (15), (16), (17), (18) for (p + 1)k + 1 ≤ i, j ≤ n in the arithmetic unit (102), retaining each value of Reg (0) / i , . . . , Reg ( k ) / i in the corresponding register of the register set (101) following the instruction of the main controller G (8). Expressions (14), (15), (16) are preliminary formulas, and expressions (17) and (18) are formulas that determine updated components. The back-substitution section (7) is connected to the memory (1) and obtains the value of the unknown vector x by calculating expressions (19) and (20) for 1 ≤ h ≤ i - 1 for i = n, n - 1, . . . , 1 in this order of i. The operation of the main controller G (8) is described below with reference to Fig. 2, which shows a flow chart of its control algorithm. The first step tests if n is a multiple of k. If it is, then the next step initializes p as p = 0 and enters the loop of the left side. The t-th step within this loop where, t = 1, . . . , k, instructs the pivoting section (2) and the preprocessing section A t (4) to execute their operations for the (pk + t)th row of the current reduced matrix A (pk+t-1) . The next step tests if p = n/k - 1. If it is, then the next step escapes the loop. If p < n/k - 1, then the next step instructs the updating section B (6) to execute its operation. The next step increments p by 1 and returns to the operations of the pivoting section 2 and the preprocessing section A 1 3. If n is not a multiple of k, then the next step initializes p as p = 0 and enters the loop of the right side. Within this loop, the operations are the same except the fact that the condition for escaping the loop is p = [n/k], and the position of the testing for escape is immediately after the operation of A n-[n/k]k . After escaping one of the loops the final step instructs the back-substitution section 7 to execute its operation and terminates the whole operation to obtain the unknown vector x. Fig. 3 is a block diagram of linear calculating equipment in the second embodiment of the present invention. In Fig. 3, (1) is a memory, (2) is a pivoting section connected to the memory (1); (3), (4), (5) are preprocessing sections A 1 , A t , A k respectively, each connected to the memory (1); (9) is an updating section B' connected to the memory (1); (10), (11), (12) are postprocessing sections C 1 , C t , C k-1 respectively, each connected to the memory (1); (13) is a main controller J; (103) is a register set composed of k registers; (104) is an arithmetic unit for, (101) is an arithmetic unit. Following is a description of the operation of each component, which is different from one in the first embodiment. The updating section B' (9) is connected to the memory 1 and calculates (14), (15), . . . , (18) for 1 ≤ i ≤ pk, (p + 1)k + 1 ≤ i ≤ n, (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for 1 ≤ i ≤ [n/k]k, [n/k]k + 1 ≤ j ≤ n otherwise in the arithmetic unit 104, retaining each value of Reg (0) / i , . . . , Reg ( k ) / i in the corresponding register of the register set 103. The k - 1 postprocessing sections C t (11), where t = 1, 2, . . . , k - 1, are connected to the memory 1 and calculate (21), (22), . . . . , (29) for pk + t + 2 ≤ j ≤ n. The operation of the main controller J 13 is described below with reference to Fig. 4, which shows a flow chart of its control algorithm. The first step tests if n is a multiple of k. If it is, then the next step initializes p as p = 0 and enters the left side loop. The t-th step within this loop, where t = 1, . . . , k, instructs the pivoting section 2 and the preprocessing section A t 4 to execute their operations for the (pk + t)th row of the current reduced matrix A (pk+t-1) . The next step instructs the updating section B' 9 to execute its operation. The following k - 1 steps instruct the postprocessing sections C 1 (10) through C k-1 (12) to execute their operations in this order. The next step tests if p = n/k - 1. If it is, then the next step escapes the loop and terminates operation. If p < n/k - 1, then the next step increments p by 1 and returns to the operation of the pivoting section 2. If n is not a multiple of k, then the next step initializes p as p = 0 and enters the right side loop. Within this loop, the first n - [n/k]k + 1 steps are the same as those in the loop of the left side. After instructing the preprocessing section A n-[n/k]k (4) to execute its operation, the step tests if p = [n/k]. If it is not, then the following steps order the operations of the pivoting section (2) and the preprocessing section A n-[n/k]+1 (4) through the operations of the pivoting section (2) and the preprocessing section A k (5) followed by the operation of the updating section B'(9) and then the operations of the postprocessing sections C 1 (10) through C k-1 (12). Then the step increments p by 1 and returns to the operation of the pivoting section (2). If p = [n/k], then the following steps instruct the updating section B'(9) to execute its operation, instruct the postprocessing sections C 1 (10) through C n-[n/k]k (11) to execute their operations, and terminates the whole process to obtain the unknown vector. Fig. 5 is a block diagram of parallel linear calculating equipment in the third embodiment of the present invention. In Fig. 5, (21) is a network; (22), (23), (24) are nodes α 0 , α u , α P-1 mutually connected by the network (21); (25) is a main controller G p connected to each node. Fig. 6 is a block diagram of a node in Fig. 5. In Fig. 6, (1) is a memory; (2) is a pivoting section connected to the memory 1; (3), (4), (5) are preprocessing sections A 1 , A t , A k respectively, each connected to the memory (1); (6) is an updating section B connected to the memory (1); (7) is a back-substitution section connected to the memory (1); (26) is a gateway that is a junction with the outside ; (27) is a transmitter that transmits data between the memory (1) and the outside through the gateway (26); (101) is a register set composed of k registers; (102) is an arithmetic unit. Following is a description of the operation of each component of the third embodiment. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (r) and x are assigned to the node α u (23), then the pivoting section 2 of the node α u (23) determines the pivot (3), and the preprocessing section of the node α u (23) calculates (4) and (5) for pk + 2 ≤ j ≤ n, and the transmitter (27) transmits the results to the memory (1) of every other node through the gateway (26), while the updating section B (6) of the element processor in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A 1 . The preprocessing section A t 4 of the node α u (23) calculates expressions (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n, and, immediately after the pivoting section 2 of α u (23) determines the pivot (11), calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter (27) transmits the results to the memory (1) of every other node through the gateway (26), while the updating section B (6) of the element processor in charge of the i-th row calculates (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of parallel operations is below called parallel preprocessing A t , where 2 ≤ t ≤ k. The updating section B (6) of each node in charge of the i-th row such that (p + 1)k + 1 ≤ i ≤ n also calculates expressions (14) through (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operations are below called parallel updating B. The back-substitution sections 7 of nodes α u (23) calculate (19) and (20) using necessary data transmitted by the transmitters (27) of other nodes. These operations are called back-substitution. The operation of the main controller G p (25) is described below with reference to Fig. 7, which shows a flow chart of its control algorithm at the level of above definition. The first step distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the nodes α 0 (22),. . . , α u (23), . . . , α P-1 (24) in such a manner as each block of k rows and corresponding 2k components (n - [n/k]k rows and 2(n - [n/k]k) components in the final distribution) are transmitted to the memory (1) of one node at a time in the cyclic order of α 0 , . . . , α P-1 , α 0 , α 1 , . . . . The next step tests if n is a multiple of k. If it is, then the next step initializes p as p = 0 and enters the loop of the left side. The t-th step within this loop orders the execution of the parallel preprocessing A t for the (pk + t)th row of the current reduced matrix A (pk+t-1) . The next step tests if p = n/k - 1. If it is, then the next step escapes the loop. If p < n/k - 1, then the next step orders the execution of the parallel updating B. The next step increments p by 1 and returns to the execution of the parallel preprocessing A 1 . If n is not a multiple of k, then the next step initializes p as p = 0 and enters the loop of the right side. Within this loop, the operations are the same except the fact that the condition for escaping the loop is p = [n/k], and the position of the testing for escape is between the parallel preprocessing A n-[n/k]k and A n-[n/k]k+1 . After escaping one of the loops the final step orders the execution of back-substitution and terminates the whole operation to obtain the unknown vector x. Fig. 8 is a block diagram of parallel linear calculating equipment in the fourth embodiment of the present invention. In Fig. 8, (31) is a network; (32), (33), (34) are nodes α 0 , α u , α P-1 mutually connected by the network (31); (35) is a main controller J p connected to each node. Fig. 9 is a block diagram of a node in Fig. 8. In Fig. 9, (1) is a memory; (2) is a pivoting section connected to the memory 1; (3), (4), (5) are preprocessing sections A 1 , A t , A k respectively, each connected to the memory (1); (9) is an updating section B' connected to the memory (1); (10), (11), (12) are postprocessing sections C 1 , C t , C k-1 respectively, each connected to the memory (1); (26) is a gateway that is a junction with the outside ; (27) is a transmitter that transmits data between the memory (1) and the outside through the gateway (26); (103) is a register set composed of k registers; (104) is an arithmetic unit. Following is a description of the operation of each component of the fourth embodiment. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the node α u (33), then the pivoting section (2) of the node α u 33 determines the pivot (3), and the preprocessing section of the node α u (33) calculates (4) and (5) for pk + 2 ≤ j ≤ n, and the transmitter (27) transmits the results to the memory 1 of every other node through the gateway (26), while the updating section B 6 of the element processor in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A 1 . The preprocessing section A t (4) of the node α u (23) calculates expressions (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n, and, immediately after the pivoting section (2) of α u (23) determines the pivot (11), calculates (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter (27) transmits the results to the memory (1) of every other node through the gateway (26), while the updating section B' (9) of the element processor in charge of the i-th row calculates (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing A t , where 2 ≤ t ≤ k. The updating section B' (9) of each node in charge of the i-th row such that 1 ≤ i ≤ pk or (p + 1)k + 1 ≤ i ≤ n if n is a multiple of k or p < [n/k] and 1 ≤ i ≤ [n/k]k otherwise also calculates expressions (14) through (18) for (p + 1)k + 1 ≤ j ≤ n if n is a multiple of K or p < [n/k] and for [n/k]k + 1 ≤ j ≤ n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operations are below called parallel updating B'. The postprocessing section C t 11 of the above node α u (33) calculate (21), (22), . . . , (29) for pk + t + 2 ≤ j ≤ n for t = 1, 2, . . . , k - 1 if n is a multiple of k or p < [n/k] and for t = 1, 2, . . . , n - [n/k]k otherwise. This series of operations is below called post-elimination C. The operation of the main controller J p (35) is described below with reference to Fig. 10, which shows a flow chart of its control algorithm at the level of above definition. The first step distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the nodes α 0 (32), . . . , α u (33), . . . , α P-1 (34) in such a manner as each block of k rows and corresponding 2k components (n - [n/k]k rows and 2(n - [n/k]k) components in the final distribution) are transmitted to the memory (1) of one node at a time in the cyclic order of α 0 , . . . , α P-1 , α 0 , α 1 , . . . . The next step tests if n is a multiple of k. If it is, then the next step initializes p as p = 0 and enters the loop of the left side. The t-th step within this loop orders the execution of the parallel preprocessing A t for the (pk + t)th row of the current reduced matrix A (pk+t-1) . The next step orders the execution of the parallel updating B'. The next step orders the execution of the post-elimination C. The next step tests if p = n/k - 1. If it is, then the next step escapes the loop. If p < n/k - 1, then the next step increments p by 1 and returns to the execution of the parallel preprocessing A 1 . If n is not a multiple of k, then the next step initializes p as p = 0 and enters the loop of the right side. Within this loop, the operations are the same except the fact that the condition for escaping the loop is p = [n/k], and if p = [n/k], the steps skip the order for the execution of the parallel preprocessing A n-[n/k]k+1 through A k . By the above processing, the unknown vector is obtained. Fig. 11 is a block diagram of a parallel linear calculating equipment according to the fifth embodiment of the present invention. In Fig. 11, (41) is a network; (42), (43), (44) are clusters CL 0 , CL u , CL P-1 mutually connected by the network (41); (45) is a main controller G pc connected to each cluster. Fig. 12 is a block diagram of a cluster in Fig. 11. In Fig. 12, (1) is a memory; (46) is a C gateway that is a junction with the outside; (47), (48), (49) are element processors PE 1 , PE 2 , PE P c , each connected to the memory 1 ; (50) is a transmitter that transmits data between the memory (1) and the outside through the C gateway (46). Fig. 13 is a block diagram of an element processor in Fig. 12. In Fig. 13, (2) is a pivoting section; (3), (4), (5) are preprocessing sections A 1 , A t , A k respectively, each connected to the pivoting section (2); (6) is an updating section B connected to the pivoting section (2); (7) is a back-substitution section connected to the pivoting section (2); (51) is a gateway that is a junction with the outside ; (101) is a register set composed of k registers; (102) is an arithmetic unit. Following is a description of the operation of each component of the fifth embodiment. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the cluster CL u (43), then the pivoting section (2), the updating section (6) and the back-substitution section (7) of each element processor of CL u (43) take charge of part of the k rows and 2k components row by row, while the preprocessing section A t (4) of each element processor of CL u (43) takes charge of elements of the (pk + t)th row of A (r) and the (pk + t)th component of b (r) one by one. Specifically, the pivoting section (2) of the element processor PE 1 of CL u (43) determines the transposed pivot (3) of the (pk + 1)th row, and the preprocessing sections A 1 (3) of element processors of CL u simultaneously calculate (4) and (5) for pk + 2 ≤ j ≤ n with each A 1 3 calculating for elements and components in its charge, and the transmitter (50) transmits the results to the memory of every other cluster through the C gateway (46), while the updating section B (6) of the element processor in charge of the i-th row calculates (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA 1 . The preprocessing sections A t (4) of the above cluster CL u (43) simultaneously calculate expressions (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n with each A t (4) calculating for elements and components in its charge and, immediately after the pivoting section of PE t of CL u (43) determines the pivot (11), simultaneously calculate expressions (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter (50) transmits the results to the memory (1) of every other cluster through the C gateway (46), while the updating section B (6) of the element processor in charge of the i-th row calculates (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA t , where 2 ≤ t < k. The updating sections B (6) of each element processor in charge of the i-th row such that (p + 1)k + 1 ≤ i ≤ n calculate (14) through (18) for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set (101). These operations are below called parallel updating B c . The back-substitution sections (7) of element processors calculate expressions (19) and (20) using necessary data transmitted by the transmitters (50) of other clusters. These operations are called back-substitution. The operation of the main controller G pc (45) is described below with reference to Fig. 14, which shows a flow chart of its control algorithm at the level of above definition. The first step distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the cluster CL 0 (42), . . . , CL u (43), . . . , CL P-1 (44) in such a manner as each block of k rows and corresponding 2k components (n - [n/k]k rows and 2(n - [n/k]k) components in the final distribution) are transmitted to the memory (1) of one node at a time in the cyclic order of CL 0 , . . . , CL P-1 , CL 0 , CL 1 , . . . . The next step tests if n is a multiple of k. If it is, then the next step initializes p as p = 0 and enters the loop of the left side. The t-th step within this loop orders the execution of the parallel preprocessing CLA t for the (pk + t)th row of the current reduced matrix A (pk+t-1) . The next step tests if p = n/k - 1. If it is, then the next step escapes the loop. If p < n/k - 1, then the next step orders the execution of the parallel updating B c . The next step increments p by 1 and returns to the execution of the parallel preprocessing CLA 1 . If n is not a multiple of k, then the next step initializes p as p = 0 and enters the loop of the right side. Within this loop, the operations are the same except the fact that the condition for escaping the loop is p = [n/k], and the position of the testing for escape is between the parallel preprocessing CLA n-[n/k]k and CLA n- [n/k]k+1 . After escaping one of the loops the final step orders the execution of back-substitution and terminates the whole operation to obtain the unknown vector x. Fig. 15 is a block diagram of a parallel linear calculating equipment according to the sixth embodiment of the present invention. In Fig. 15, (61) is a network; (62), (63), (64) are clusters CL 0 , CL u , CL P-1 mutually connected by the network (61); (65) is a main controller J pc connected to each cluster. Fig. 16 is a block diagram of a cluster in Fig. 15. In Fig. 16, (1) is a memory; (46) is a C gateway that is a junction with the outside; (66), (67), (68) are element processors PE 1 , PE 2 , PE P c , each connected to the memory (1); (50) is a transmitter that transmits data between the memory (1) and the outside through the C gateway (46). Fig. 17 is a block diagram of an element processor shown in Fig. 16. In Fig. 17,(2) is a pivoting section; (3), (4), (5) are preprocessing sections A 1 , A t , A k respectively, each connected to the pivoting section (2); (9) is an updating section B' connected to the pivoting section (2); (10), (11), (12) are postprocessing sections C 1 , C t , C k-1 respectively, each connected to the pivoting section (2); (51) is a gateway that is a junction with the outside; (103) is a register set composed of k registers; (104) is an arithmetic unit. Following is a description of the operation of each component of the fourth embodiment. If the (pk + 1)th through (p + 1)k-th rows of A (0) and corresponding components of b (0) and x are assigned to the cluster CL u (63), then the pivoting section (2) and the updating section B' (9) of each element processor of CL u (63) take charge of part of the k rows and 2k components row by row, while the preprocessing section A t (4) and postprocessing section C t 11 of each element processor of CL u (63) take charge of elements of the (pk + t)th row of A (r) and the (pk + t)th component of b (r) one by one. Specifically, the pivoting section (2) of the element processor PE 1 of CL u (63) determines the transposed pivot (3) of the (pk + 1)th row, and the preprocessing sections A 1 (3) of element processors of CL u 63 simultaneously calculate expressions (4) and (5) for pk + 2 ≤ j ≤ n with each A 1 (3) calculating for elements and components in its charge, and the transmitter (50) transmits the results to the memory (1) of every other cluster through the C gateway (46), while the updating section B' (9) of the element processor in charge of the i-th row calculates expression (14) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA 1 . The preprocessing sections A t (4) of the above cluster CL u (63) simultaneously calculate expressions (6), (7), (8), (9), (10) for pk + t ≤ j ≤ n with each A t (4) calculating for elements and components in its charge and, immediately after the pivoting section (2) of the element processor PE t of CL u (63) determines the pivot (11), simultaneously calculate expression (12) and (13) for pk + t + 1 ≤ j ≤ n, and the transmitter (50) transmits the results to the memory (1) of every other cluster through the C gateway (46), while the updating section B' (9) of the element processor in charge of the i-th row calculates expression (30) for every i such that (p + 1)k + 1 ≤ i ≤ n. This series of operations is below called parallel preprocessing CLA t , where 2 ≤ t ≤ k. The updating section B' (9) of each element processor in charge of the i-th row such that 1 ≤ i ≤ pk or (p + 1)k + 1 ≤ i ≤ n if n is a multiple of k or p < [n/k] and 1 ≤ i ≤ [n/k]k otherwise also calculates expression (14) through (18) for (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for [n/k]k + 1 ≤ j ≤ n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set. These operations are below called parallel updating B' c . The postprocessing sections C t 11 of element processors of the above CL u (63) simultaneously calculate expressions (21), (22), . . . , (29) for j such that pk + t + 2 ≤ j ≤ n for t = 1, 2, . . . , k - 1 if n is a multiple of k or p < [n/k] and for t = 1, 2, . . . , n - [n/k]k otherwise with each C t (11) calculating for elements and components in its charge. This series of operations is below called post-elimination C c . The operation of the main controller J pc (65) is described below with reference to Fig. 18, which shows a flow chart of its control algorithm at the level of above definition. The first step distributes and assigns the rows of the coefficient matrix A (0) and the components of b (0) and x to the clusters CL 0 (62), . . . , CL u (63), . . . , CL P-1 (64) in such a manner as each block of k rows and corresponding 2k components (n - [n/k]k rows and 2(n - [n/k]k) components in the final distribution) are transmitted to the memory (1) of one node at a time in the cyclic order of CL 0 , . . . , CL P-1 , CL 0 , CL 1 , . . . . The next step tests if n is a multiple of k. If it is, then the next step initializes p as p = 0 and enters the loop of the left side. The t-th step within this loop orders the execution of the parallel preprocessing CLA t for the (pk + t)th row of the current reduced matrix A (pk+t-1) . The next step orders the execution of the parallel updating B' c . The next step orders the execution of the post-elimination C c . The next step tests if p = n/k - 1. If it is, then the next step escapes the loop. If p < n/k - 1, then the next step increments p by 1 and returns to the execution of the parallel preprocessing CLA 1 . If n is not a multiple of k, then the next step initializes p as p = 0 and enters the loop of the right side. Within this loop, the operations are the same except the fact that the condition for escaping the loop is p = [n/k], and if p = [n/k], the steps skip the order for the execution of the parallel preprocessing CLA n-[n/k]k+1 through CLA k . By the above processing, the unknown vector is obtained. Fig. 19 shows a block diagram of an element processor or processor module of a parallel computer that implements the seventh embodiment of the present invention. In Fig 19, (201) is a gate way; (202) is a cache memory; (203) is a central processing unit; (204) is a local memory; (205) is a shared buss. Fig 20 shows a block diagram of a cluster composed of element processors (212), (213), . . . , (214), a C gateway (210), and a shared memory (211). A network of the parallel computer connects each of the clusters to each other, so that data can be transmitted between any two clusters. Let the number of element processors in each cluster be P c and the total number of clusters be C. Then the total number P of element processors in the parallel computer is C·P c . Furthermore, let the clusters be denoted by CL 1 , CL 2 , . . . , CL C , and let the element processors of CL u be denoted by PR u 1 , . . . , PR u P c . Fig. 21 is a block diagram of parallel linear computation method according to the seventh embodiment of the present invention implemented by a parallel computer structured above. In Fig. 21, (220) is a data distribution means; (221) is a pivoting means; (222) is an elementary pre-elimination means; (223) is a multi-pivot elimination means; 224 is an elimination testing means; (225) is a remainder elimination means; (226) is an elementary back-substitution mean; (227) is an elementary back-transmission means; (228) is an elementary back-calculation means; (229) is a back-processing testing means. The operation of the parallel linear computation method of the seventh embodiment is described below with reference to Fig. 21. In the first step, the data distribution means (220) distributes each i-th row of A (0) and i-th component of b (0) and x to the cluster CL u such that u = [i/P c ] - [[i/P c ]/C]C + 1. Then the data distribution means (220) assigns each i-th row of A (0) and i-th component of b (0) distributed to the cluster CL u to the element processor PR u v such that v = i - [i/P c ]P c + 1. Then the data distribution means initializes k as k = 0. In the second step, the elimination testing means (224) tests if the multi-pivot elimination means repeated its operation [n/P c ] times, that is, whether k = [n/P c] . If it did, then the process jumps to the fifth step. If it did not, the process goes to the third step. In the third step, the elementary pre-elimination means (222) executes preliminary processing for the i-th rows of reduced matrices and the corresponding known vectors such that i = kP c + l and l = 1, . . . , P c in this order. The processing involves a pivot choosing process for each 1. Methods of choosing a pivot are in general classified into either partial pivoting or full pivoting. Partial pivoting chooses as a pivot in each reduced matrix A (r) an element with the largest absolute value in the relevant column or row. Full pivoting chooses as a pivot in each reduced matrix A (r) the element with the largest absolute value in the submatrix of the columns or rows which have not hitherto been pivotal. Besides, if precision is not important so much, then choosing of a pivot is necessary only when the relevant diagonal element is 0, and in that case any nonzero element can be chosen as a pivot in partial pivoting. Pivoting methods in the present invention employ partial pivoting, and the present first method chooses the first nonzero element in the relevant row, and the present second method chooses an element with the greatest absolute value in the relevant row. Fig. 23 shows the process of the pivot choosing means (221). In Fig. 23, (240) is a search means; (241) is a column number broadcasting means; (242) is an element interchange means; (243) is an component interchange means. In the present first method of pivot choosing, the element processor in charge of each i-th row, by the search means (240), tests if a (i-1) i j = 0 with i = j. If it is not, then the process terminates. If it is, then the element processor, by the search means (240), searches for a nonzero element in the i-th row of A (i-1) from a (i-1) i j with j = i+1 to a (i-1) i j with j = n in this order. If a (i-1) i j with j = h is the first such element, then the element processor, by the broadcasting means (241), notifies each element processor of the column number h by a broadcast. Specifically, the element processor either transmits h to a specified word of the shared memory (211) of each cluster, and each element processor refers to the word, or the element processor transmits h to a dedicated bus line, and each element processor fetches h into its local memory (204). Then each element processor, by the element interchange means (242), simultaneously interchanges the element with the column number i with the element with the column number h in the row in its charge. Then two element processors in charge of the i-th component and the h-th component of the unknown vector x respectively interchange these component by the component interchange means (243). The pivot choosing process terminates hereby. In the present second method of pivot choosing, the element processor in charge of each i-th row, by the search means (240), sets Max = a (i-1) i j and with j = i and Col = j. The element processor then compares max with a (i-1) i j for j = i + 1, . . . , n in this order and updates Max and Col as Max = a (i-1) i j and Col = j, only if a (i-1) i j is greater than Max. Then the element processor notifies each element processor of Col by a broadcast. The remaining steps are the same as above. In the process of the elementary pre-elimination means (222), if l = 1, then the element processor PR u 1 in charge of the (kP c + 1)th row in the cluster CL u , where u = k - [k/C] + 1, calculates expressions (32) and (33), and transmits the results to the shared memory of every other cluster to which the element processor in charge of an i-th row such that kP c + 2 ≤ i ≤ n belongs. If 2 ≤ l ≤ P c , then each element processor in charge of the i-th row such that kP c + l ≤ i ≤ n calculates expression (34), and the element processor PR u l calculates expressions (35) and (36). Then after the pivot choosing means determines the pivot (37), the element processor PR u l calculates expressions (38) and (39) and transmits the results to the shared memory of every other cluster to which the element processor in charge of an i-th row such that kP c + l + 1 ≤ i ≤ n belongs. In the fourth step, by the multi-pivot elimination means (223), each element processor in charge of the i-th row such that (k + 1) P c + 1 ≤ i ≤ n calculate expressions (40) and (41) for i. In the fifth step, by the remainder elimination means (225), each element processor in charge of the i-th row such that [n/P c ]P c + 1 ≤ i ≤ n executes the same operation as in the elementary pre-elimination means (232) for l = 2, . . . , n - [n/P c ]P c . Then this step initializes i as i = n, and goes to the sixth step. In the sixth step, by the elementary back-substitution means (226), the element processor in charge of the i-th row calculates expression (42). In the seventh step, the back-processing testing means (229) tests if i = n. If it is, then the solution of the system of linear equation (2) has been obtained by the above elementary back-substitution as (44), and the process terminates. If it is not, then the process proceeds to the eighth step. In the eighth step, an elementary back-transmission means that transmits x i to the shared memory of every clusters such that the element processor in charge of an h-th row such that 1 ≤ h ≤ i - 1 belongs. In the ninth step, by the elementary back-calculation means, each element processor in charge of the h-th row such that 1 ≤ h ≤ i - 1 calculates (43). Then this step decrements i by 1, and increments goes to the sixth step. Fig. 22 is a block diagram of parallel linear calculating method in the eighth embodiment of the present invention implemented by a parallel computer structured as in the seventh embodiment. In Fig. 22, (220) is a data distribution means; (221) is a pivot choosing means; (231) is an elimination testing means, (232) is an elementary pre-elimination means; (233) is a multi-pivot elimination means; (234) is an elementary post-elimination means; (225) is a post-elimination processing means; (236) is a remainder elimination means. The operation of the parallel linear computation method of the seventh embodiment is described below with reference to Fig. 22. In the first step, the data distribution means (220) distributes each i-th row of A (0) and i-th component of b (0) and x to the cluster CL u such that u = [i/P c ] - [[i/P c ]/C]C + 1. Then the data distribution means (220) assigns each i-th row of A (0) and i-th component of b (0) distributed to the cluster CL u to the element processor PR u v such that v = i - [i/P c ]P c + 1. Then the data distribution means initializes k as k = 0. In the second step, the elimination testing means (231) tests if the multi-pivot elimination means repeated its operation [n/P c ] times, that is, whether k = [n/P c] . If it did, then the process jumps to the sixth step. If it did not, the process goes to the third step. In the third step, the elementary pre-elimination means (232) executes preliminary processing for the i-th rows of the reduced matrices and the corresponding known vectors such that i = kP c + l and l = 1, . . . , P c in this order. The processing involves a pivot choosing process for each l, which is the same as in the seventh embodiment. In the pre-elimination means (232), if l = 1, then after the pivot choosing means (221) determines the pivot (31), the element processor PR u 1 in charge of the (kP c + 1)th row in the cluster CL u , where u = k - [k/C] + 1, calculates expressions (32) and (33), and transmits the results to the shared memory of every other cluster. If 2 ≤ l ≤ P c , then each element processor in charge of the i-th row such that kP c + l ≤ i ≤ n calculates expression (34), and the element processor PR u l calculates expressions (35) and (36). Then after the pivot choosing means determines the pivot (37), the element processor PR u l calculates expressions (38) and (39) and transmits the results to the shared memory of every other cluster. In the fourth step, by the multi-pivot elimination means (233), each element processor in charge of the i-th row such that 1 ≤ i ≤ kP c or (k + 1) P c + 1 ≤ i ≤ n calculates (40) and (41). In the fifth step, the post-elimination processing means (235) eliminates unnecessary elements generated by the multi-pivot elimination means (233). The core of the post-elimination processing means (235) is the elementary post-elimination means 234, which calculates expressions (45) and (46) in the element processor in charge of the i-th row. By the post-elimination processing means the element processor in charge of the (kP c + w)th row calculates expressions (45) and (46), where i = P c + w and l = - w + q + 1, from w = 1 to w = q for q = 1, 2, . . . , P c - 1. In the sixth step, by the remainder elimination means (236), each element processor in charge of the i-th row such that [n/P c ]P c + 1 ≤ i ≤ n executes the operation of the elementary pre-elimination means (232). Then the remainder elimination means executes operation of the multi-pivot elimination means (233) followed by the post-elimination processing means (235). The operation of pre-elimination processing means (232) should be executed for l = 1, . . . , n - [n/P c ]P c . The operation of the multi-pivot elimination means (233) should be executed by calculating expressions (40) and (41) for 1 ≤ i ≤ [n/P c ]P c and k = [n/P c ]. The operation of the post-elimination processing means (235) should be executed from q = 1 to q = n - [n/P c ]P c for k = [n/P c ]. The unknown vector x is obtained as the vector b (r) after the above operation. If the preprocessing section A t and the postprocessing section C t have their own register sets as the updating section B and B' in the first embodiment through the six embodiment, and their operations are executed by retaining values of variables and divisors, then the number of load-and-store operations for the memory are reduced, and further improvement in computation speed can be achieved. In the seventh and eighth embodiments two components of the unknown vector should be interchanged if the corresponding columns are interchanged by the pivoting means. However, it is not necessary to actually transpose the components. By simply memorizing the correct position of the components after each interchange of columns, the correct solution is obtained by considering the positions in the final substitution to the components of the unknown vector. Thus the present invention provides high-speed linear calculating equipment and parallel linear calculating equipment for solving systems of linear equations by means of Gauss's elimination method and Gauss-Jordan's method based on multi-pivot simultaneous elimination and scalar operations. The speed-up is achieved by reducing the number of load-and-store operations for the memory by retaining values of variables in register sets in updating processing, and reducing the number of iteration by multi-pivot simultaneous elimination. And the present invention is easily implemented in scalar computers. In fact, an experiment done in a scalar computer by means of software showed that Gauss's method and Gauss-Jordan's method based on 8-pivot simultaneous elimination was 2.5 times faster than original Gauss's elimination method and Gauss-Jordan's elimination method. As for the parallel calculating equipment of the third through sixth embodiments of the seventh and eighth embodiments, each memory is assigned blocks of k rows of the coefficient matrix A (0) for the k-pivot simultaneous elimination method, so that effects of parallel computation are enhanced. In the fifth and sixth embodiments, where element processors are clustered, the preprocessing or both the preprocessing and the postprocessing are also made parallel, and the computation is more effective. In these embodiments, a theoretical estimation has shown that if the number of components of the unknown vector X is sufficiently large for a definite number of processors, then the effects of parallel computation are sufficiently powerful. Therefore, parallel linear calculating equipment effectively employing Gauss method and Gauss-Jordan method based on multi-pivot simultaneous elimination has been obtained. Furthermore, the present invention effectively makes possible high-speed parallel computation for solving systems of linear equations using a parallel computer with a number of element processors by means of the methods of the seventh and eighth embodiments. Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims.

Claims: Apparatus to solve a system of linear equations comprising: memory means to store a coefficient matrix A (0) and a corresponding known components vector b (0) and to store intermediate reduced matrix A (r) and corresponding known components vector b (r) an unknown vector x expressed by A ( r ) = ( a ( r ) ij ), 1 ≤ i, j ≤ n , b ( r ) = ( b ( r ) 1 , b ( r ) 2 , . . . , b ( r ) n ) t , x = ( x 1 , x 2 , . . . , x n ) t where r = 0, 1, . . . , n, for a given system of linear equations A (0) x = b (0) , a pivoting means connected to said memory means and to control means for choosing a pivot in the i-th row of A (i-1) according to a partial pivoting algorithm, that is the pivot of a row is the element having the maximum value; and interchanging the i-th column with the chosen pivotal column for 1 ≤ i ≤ n, further comprising means to determine the transposed pivot for a given positive integer k and a value of a nonnegative integer parameter p, and wherein said transposed pivot is a ( pk ) / pk + l pk + l a preprocessing means connected to said memory means and to control means, comprising k preprocessing element A 1 wherein each of said preprocessing element A 1 comprising means to calculate a ( pk +1) pk +1 j = a ( pk ) pk +1 j / a ( pk ) pk +1 pk +1 for pk + 2 ≤ j ≤ n and b ( pk +1) pk +1 = b ( pk ) pk +1 / a ( pk ) pk +1 pk +1 , after said pivot choosing means determining said transposed pivot a ( pk ) / pk + lpk + l a plurality of preprocessing means A t , where t = 2, 3, . . . , k, each of which is connected to said memory means and control means to calculate Reg (0) pk + t = a ( pk ) pk + tpk +1 , Reg (1) pk + t = a ( pk ) pk + tpk +2 - Reg (0) pk + t a ( pk +1) pk +1 pk +2 , . . . , for pk + t ≤ j ≤ n, and wherein each of said plurality of preprocessing means A t further comprising means to calcultate, a ( pk + t ) pk + tj = a ( pk + t -1) pk + tj / a ( pk + t -1) pk + tpk + t , b ( pk + t ) pk + t = b ( pk + t -1) pk + t / a ( pk + t -1) pk + tpk + t for pk + t + 1 ≤ j≤ n after said pivot choosing means determines said transposed pivot a ( pk + t - l ) / pk + t pk + t , whereby 1 ≤ t ≤ k updating means connected to said memory means and control means, comprising a register set of k registers and an arithmetic means, and wherein said arithmetic means comprising means to calculate Reg (0) i = a ( pk ) ipk +1 , Reg (1) i = a ( pk ) ipk +2 - Reg (0) i a ( pk +1) pk +1 pk +2 , . . . . . and wherein said arithmetic means further comprising means either to store retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in said register set for (P+1)k + 1 ≤ i, j ≤ n, or for 1 ≤ i ≤ pk, (p + 1)k + 1 ≤ i ≤ n, and (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for 1 ≤ i ≤ [n/k]k, [n/k]k + 1 ≤ j ≤ n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in said register set, a back-substitution means which is connected to said memory means, to obtain the value of said unknown vector x, wherein said back-substitution means comprising means to calculate x i = b ( n ) i and b ( n + h - i +1) h = b ( n + h - i ) h - a ( h ) hi x i for 1 ≤ h ≤ i - 1 for i = n, n - 1 , . . . , 1 in this order of i, k - 1 postprocessing means C t , where t = 1, 2, . . . , k - 1, each of which is connected to said memory and comprising means to calculate Reg (0) = a ( pk + t ) pk +1 pk + t +1 , Reg (1) = a ( pk + t ) pk +2 pk + t +1 , . . . , Reg ( t -1) = a ( pk + t ) pk + tpk + t +1 , a ( pk + t +1) pk +1 j = a ( pk + t ) pk +1 j - Reg (0) a ( pk + t +1) pk + t +1 j , a ( pk + t +1) pk +2 j = a ( pk + t ) pk +2 j - Reg (1) a ( pk + t +1) pk + t +1 j , . . . , a ( pk + t +1) pk + tj = a ( pk + t ) pk + tj - Reg ( t -1) a ( pk + t +1) pk + t +1 j , b ( pk + t +1) pk +1 = b ( pk + t ) pk +1 - Reg (0) b ( pk + t +1) pk + t +1 , b ( pk + t +1) pk +2 = b ( pk + t ) pk +2 - Reg (1) b ( pk + t +1) pk + t +1 , . . . . . b ( pk + t +1) pk + t = b ( pk + t ) pk + t - Reg ( t -1) b ( pk + t +1) pk + t +1 for pk + t + 2 ≤ j ≤ n, respectively, main controller means G further comprising means to check whether n is a multiple of k; and in case n is a multiple of k said main controller means G comprising means to: to instruct said pivot choosing means said preprocessing sections A 1 , . . . , A k , and said updating means to repeat their operations for p = 0, 1, . . . , n/k - 2, and to instruct said pivot choosing means and said preprocessing means A 1 , . . . , A k to execute their operations for p = n/k -1, or in case instructs said pivot choosing section, said preprocessing sections A 1 , . . . , A k , said updating means B', and said postprocessing means C 1 , . . . , C k-1 to repeat their operations for p = 0, 1, . . . , n/k - 1, respectively, if u is not a multiple of k said main controller means G comprising means to instruct said pivot choosing means, said preprocessing means A 1 , . . . , A k , and said updating means B to repeat their operations for p = 0, 1, . . . [n/k] - 1, where [n/k] denotes the greatest integer not exceeding n/k, and to instruct said pivot choosing means and said preprocessing means A 1 , . . . A n-[n/k]k to execute their operations, and to instruct said back substitution means to obtain said unknown vector, or to instruct said pivot choosing means, said preprocessing means A 1 , . . . , A k , said updating means and said postprocessing means C 1 , . . . , C k-1 to repeat their operations for p = 0, 1, . . . [n/k] - 1, and to instruct said pivot choosing means said preprocessing means A 1 , . . . , A n-[n/k]k , said updating means B', and said postprocessing means C 1 , . . . , C n-[n/k]k to execute their operations for p = [k/n], respectively. Apparatus to solve a system of linear equation comprising: a network means, a main controller means connected to said network means and comprising means to execute flow control, a plurality of nodes α u , where u = 0, 1, . . . , P - 1, each of which is connected to each other by said network means and comprises: a memory means to store blocks of k rows of a coefficient matrix A (0) and a corresponding known components vector b (0) and to store blocks of k rows of intermediate reduced matrix A (r) and corresponding known components vector b (r) and an unknown vector x assigned to said node and expressed by A ( r ) = ( a ( r ) ij ), 1 ≤ i , j ≤ n , b ( r ) = ( b ( r ) 1 , b ( r ) 2 , . . . , b ( r ) n ) t , x = ( x 1 , x 2 , . . . , x n ) t for 0 ≤ r ≤ n where r is a positive integer, for a given system of linear equations A (0) x = b (0) , a pivot choosing means which is connected to said memory means, to choose a pivot in the i-th row of A (i-1) according to a partial pivoting algorithm, that is the pivot of a row is the element having the maximum value; and interchanging the i-th column with the chosen pivotal column for i in said node's charge further comprising means to determine the transposed pivot for a given positive integer k and a value of a nonnegative integer parameter p, and wherein said transposed pivot is a ( pk ) / pk + l pk + l a preprocessing means connected to said memory means and to control means, comprising k preprocessing element A 1 wherein each of said preprocessing element A 1 comprising means to calculate a ( pk +1) pk +1 j = a ( pk ) pk +1 j / a ( pk ) pk +1 pk +1 for pk + 2 ≤ j ≤ n and b ( pk +1) pk +1 = b ( pk ) pk +1 / a ( pk ) pk +1 pk +1 for pk + 1 in said node's charge after said pivot choosing means determines said transposed pivot a ( pk ) / pk + l pk + l , k - 1 preprocessing means A t , where t = 2, 3, . . . , k, connected to said memory means comprising means to calculate Reg (0) pk + t = a ( pk ) pk + tpk +1 , Reg (1) pk + t = a ( pk ) pk + tpk +2 - Reg (0) pk + t a ( pk +1) pk +1 pk +2 , . . . , for pk + t ≤ j ≤ n for pk + t in said node's charge, and, wherein each of said k -1 preprocessing means A t further comprising a ( pk + t ) pk + tj = a ( pk + t -1) pk + tj / a ( pk + t -1) pk + tpk + t , b ( pk + t ) pk + t = b ( pk + t -1) pk + t / a ( pk + t -1) pk + tpk + t for pk + t + 1 ≤ j ≤ n and for pk + t in said node's charge after said pivot choosing means determines said transposed pivot a ( pk + t - l ) / pk + t pk + t updating means connected to said memory means and to said main controller means, comprising a register set of k registers and arithmetic means, and wherein said arithmetic means comprising means to calculate Reg (0) i = a ( pk ) ipk +1 , Reg (1) i = a ( pk ) ipk +2 - Reg (0) i a ( pk +1) pk +1 pk +2 , . . . . . for (p + 1)k + 1 ≤ j ≤ n and for i in said node's charge, and means to retain said values of Reg (0) / i , . . . , Reg ( k ) / i in said register set, a back-substitution means connected to said memory means, to obtain the value of said unknown vector x by calculating x i - b ( n ) i and b ( n + h - i +1) h = b ( n + h - i ) h - a ( h ) hi x i for i and h in said node's charge, k - 1 postprocessing means C t , where t = 1, 2, . . . , k - 1, each of which connected to said memory means, to calculate Reg (0) = a ( pk + t ) pk +1 pk + t +1 , Reg (1) = a ( pk + t ) pk +2 pk + t +1 , . . . , Reg ( t -1) = a ( pk + t ) pk + tpk + t +1 , a ( pk + t +1) pk +1 j = a ( pk + t ) pk +1 j - Reg (0) a ( pk + t +1) pk + t +1 j , a ( pk + t +1) pk +2 j = a ( pk + t ) pk +2 j - Reg (1) a ( pk + t +1) pk + t +1 j , . . . , a ( pk + t +1) pk + tj = a ( pk + t ) pk + tj - Reg ( t -1) a ( pk + t +1) pk + t +1 j , b ( pk + t +1) pk +1 = b ( pk + t ) pk +1 - Reg (0) b ( pk + t +1) pk + t +1 , b ( pk + t +1) pk +2 = b ( pk + t ) pk +2 - Reg (1) b ( pk + t +1) pk + t +1 , . . . . . b ( pk + t +1) pk + t = b ( pk + t ) pk + t - Reg ( t -1) b ( pk + t +1) pk + t +1 for pk + t + 2 ≤ j ≤ n and pk + t in said node's charge, a gateway means connected to said memory means, a transmitter means connected to said memory means, to transmit data between said memory means and the outside of said node through said gateway means, and wherein said main controller means comprising means to control said memory means, said pivot choosing means, said preprocessing means A 1 , said preprocessing means A t , said updating means, said backsubstitution means and said postprocessing means C t in such a way that either if the (pk + 1)th through (p + 1)k-th rows of said A (0) and corresponding components of b (0) and x are assigned to said node α u , then said pivot choosing means of said node α u determining said pivot a ( pk ) / pk +1 pk +1, and said preprocessing means of said node α u calculating a ( pk +1) / pk +1 j and b ( pk +1) / pk +1 for pk + 2 ≤ j ≤ n, and said transmitter means transmitting the results to said memory means of said every other node through said gateway means, while said updating means B of said node in charge of the i-th row calculates Reg (0) / i for every i such that (p + 1 )k + 1 ≤ i ≤ n, said preprocessing means A t of said node α u calculating Reg (0) / pk + t , Reg (1) / pk + t , Reg ( t -2) / pk + t , a ( pk + t -1) / pk + tj and b ( pk + t -1) / pk + t for pk + t ≤ j ≤ n, and, immediately after said pivot choosing means of α u determining said pivot a ( pk + t -1) / pk + t pk + t , calculating a ( pk + t ) / pk + tj and b ( pk + t ) / pk + t for pk + t + 1 ≤ j ≤ n, and said transmitter means transmitting the results to said memory means of said every other node through said gateway means, while said updating means B of said node in charge of the i-th row calculating for every i such that (p + 1 )k + 1 ≤ i ≤ n, said updating means B of said each node in charge of the i-th row such that (p + 1 )k + 1 ≤ i ≤ n calculating Reg (0) / i , Reg (1) / i , Reg ( k -1) / i , a (( p +1) k ) / ij , b (( p +1) k ) / i for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in said register set, and said back-substitution means of said each node in charge of the i-th and h-th components calculating x i , b ( n + h - i +1) / h for 1 ≤ h ≤ i - 1 for i = n, n - 1, ..., 1 in this order of i, or if the (pk + 1)th through (p + 1)k-th rows of said A (0) and corresponding components of said b (0) and x are assigned to said node α u , then said pivot choosing means of said node α u determining the pivot a ( pk ) / pk +1 pk +1 , and said preprocessing means of said node α u calculating a ( pk +1) / pk +1 j and b ( pk +1) / pk +1 for pk + 2 ≤ j ≤ n, and said transmitter means transmitting the results to said memory means of said every other node through said gateway means, while said updating means B' of said node in charge of the i-th row calculating Reg (0) / i for every i such that (p + 1 )k + 1 ≤ i ≤n, for t = 2, 3, . . . , t, said preprocessing means A t of said node α u calculating Reg (0) / pk + t , Reg (1) / pk + t , Reg ( t -2) / pk + t , a ( pk + t -1) / pk + tj , b ( pk + t -1) pk + t for pk + t ≤ j ≤ n and, immediately after said pivot choosing means of α u determining the pivot a ( pk + t -1) / pk + t pk + t , calculating a ( pk + t ) / pk + tj and b ( pk + t ) / pk + t for pk + t + 1 ≤ j ≤ n, and said transmitter means transmitting the results to said memory means of said every other node through said gateway means, while said updating means B' of said node in charge of the i-th row calculating for every i such that (p + 1)k + 1 ≤ i ≤ n, said updating means B' of said each node in charge of the i-th row such that 1 ≤ i ≤ pk or (p + 1)k + 1 ≤ i ≤ n if n is a multiple of k or p < [n/k], and 1 ≤ i ≤ [n/k]k calculating Reg (0) / i , Reg (1) / i , Reg ( k -1) / i , a (( pk +1) k ) / ij and b (( p +1) k ) / i for (p + 1 )k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for [n/k]k + 1 ≤ j ≤ n, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in said register set, and wherein said postprocessing sections C t of said node α u calculating Reg (0) , Reg (1) , Reg (t-1) , a ( pk + t +1) / pk +1 j , a ( pk + t +1) / pk +2 j , a ( pk + t +1) / pk + tj , b ( pk + t +1) / pk +1, b ( pk + t +1) / pk +2 and b ( pk + t +1) / pk + t for pk + t + 2 ≤ j ≤ n for t = 1, 2, ..., k - 1 if n is a multiple of k or p < [n/k] and for t = 1, 2, ... , n - [n/k]k, respectively, in order to carry out a post elimination. The apparatus of claim 2 wherein said main controller means further comprising means to distribute and assign the rows of said coefficient matrix A (0) and the components of said b (0) and x to said nodes in such a manner as each block of consecutive said k rows and corresponding 2k components is transmitted to said memory means of said one node in the cyclic order of said α 0 , ..., α P-1 , α 0 , α 1 , ..., and, wherein said main controller means further comprising means to instruct, in case n is a multiple of k, said each node to execute parallel preprocessing and parallel updating for p = 0, 1, ..., n/k - 2 and to execute parallel preprocessing for p = n/k - 1, and, wherein said main controller means further comprising means to instruct, in case n is not a multiple of k, said each node to execute parallel preprocessing and parallel updating for p = 0, 1, ..., [n/k] - 1, and to execute parallel preprocessing for p = [n/k], and to instruct said nodes to obtain said unknown vector x by executing back-substitution. The apparatus of claim 2, wherein said main controller means further comprising means to distribute the rows of said coefficient matrix A (0) and the components of said b (0) and x to said nodes in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to said memory means of said one node in the cyclic order of α 0 , ..., α P-1 , α 0 , α 1 , ..., and, wherein said main controller means further comprising means to instruct, in case n is a multiple of k, said each node to execute parallel preprocessing parallel updating, and post-elimination for p = 0, 1, ..., n/k - 1 and, wherein said main controller means further comprising means to instruct, in case n is not a multiple of k, said each node to execute parallel preprocessing parallel updating, and post-elimination for p = 0, 1, ..., [n/k] - 1 and to execute said parallel preprocessing parallel updating, and post-elimination for p = [n/k]. Apparatus to solve a system of linear equations comprising: a network means a main controller means connected to said network means, to execute flow control, and a plurality of clusters CL u of processing elements, where u = 0, 1, ..., P - 1, each of which is connected to each other by said network means and comprises: a memory means to store blocks of k rows a coefficient matrix A (0) and a corresponding known components vector b (0) and to store blocks of k rows of intermediate reduced matrix A (t) and corresponding known components vector b (t) and an unknown vector x assigned to said node and expressed by A ( r ) = ( a ( r ) ij ), 1 ≤ i, j ≤ n, b ( r ) = ( b ( r ) 1 , b ( r ) 2 , . . . , b ( r ) n ) t , x = ( x 1 , x 2 , . . . , x n ) t for 0 ≤ r ≤ n and r is a positive integer, for a given system of linear equations A (0) x = b (0) , a C gateway means between each of said clusters and the outside, a transmitter means to transmit data between said memory and the outside of said cluster through said C gateway means, and a plurality of processing elements PE t , where t = 1, 2, ..., P C' each of which is connected to said memory means and comprising: a pivot choosing means connected to said memory means, to choose a pivot in the i-th row of A (i-1) according to a partial pivoting algorithm, that is the pivot of a row is the element having the maximum value; and to interchange the i-th column with the chosen pivotal column for i in said element processor's charge further comprising means to determine the transposed pivot for a given positive integer k and a value of a nonnegative integer parameter p, and wherein said transposed pivot is a ( pk ) / pk +1 pk +1 a preprocessing means connected to said memory means and to control means, comprising k preprocessing element A 1 wherein each of said preprocessing element A 1 comprising means to calculate a ( pk +1) pk +1 j = a ( pk ) pk +1 j / a ( pk ) pk +1 pk +1 for pk + 2 ≤ j ≤ n and b ( pk +1) pk +1 = b ( pk ) pk +1 / a ( pk ) pk +1 pk +1 for pk + 1 in said element processor's charge, after said pivot choosing means determines said transposed pivot a ( pk ) / pk +1 pk +1 k - 1 preprocessing means A t , where t = 2, 3, ..., k, each of which connected to said memory means and further comprising means to calculate Reg (0) pk + t = a ( pk ) pk + tpk +1 , Reg (1) pk + t = a ( pk ) pk + tpk +2 - Reg (0) pk + t a ( pk +1) pk +1 pk +2 , . . . , for pk + t ≤ j ≤ n, and, wherein each of said k-1 preprocessing means A t further comprising a ( pk + t ) pk + tj = a ( pk + t -1) pk - tj / a ( pk + t -1) pk + tpk + t , b ( pk + t ) pk + t = b ( pk + t -1) pk + t / a ( pk + t -1) pk + tpk + t for pk + t + 1 ≤ j ≤ n after said pivot choosing means determines said transposed pivot a ( pk + t -1) / pk + t pk + t an updating means B connected to said memory means and to said main controller means, comprising a register set of k registers and an arithmetic means, and wherein said arithmetic means comprising means to calculate Reg (0) i = a ( pk ) ipk +1 , Reg (1) i = a ( pk ) ipk +2 - Reg (0) i a ( pk +1) pk +1 pk +2 , . . . . . for (p + 1 )k + 1 ≤ j ≤ n and for i in said element processor's charge, means to retain the values of Reg (0) / i , . . . , Reg ( k ) / i in said register set, a back-substitution means connected to said memory means, to obtain the value of said unknown vector x and means to calculate x i = b ( n ) i and b ( n + h - i +1) h = b ( n + h - i ) h - a ( h ) hi x i for i and h in said element processor's charge, an updating means connected to said pivot choosing means comprising a register set of k registers and an arithmetic means, wherein said arithmetic means comprising means to calculate Reg (0) i = a ( pk ) ipk +1 , Reg (1) i = a ( pk ) ipk +2 - Reg (0) i a ( pk +1) pk +1 pk +2 , . . . . . for (p + 1)k + 1 ≤ j ≤ n and means to retain the values of Reg (0) / i , . . . , Reg ( k ) / i in said register set, k - 1 postprocessing means C t , where t = 1, 2, ..., k - 1, each of which connected to said pivot choosing means and further comprising means to calculate Reg (0) = a ( pk + t ) pk +1 pk + t +1 , Reg (1) = a ( pk + t ) pk +2 pk + t +1 , . . . , Reg ( t -1) = a ( pk + t ) pk + tpk + t +1 , a ( pk + t +1) pk +1 j = a ( pk + t ) pk +1 j - Reg (0) a ( pk + t +1) pk + t +1 j , a ( pk + t +1) pk +2 j = a ( pk + t ) pk +2 j - Reg (1) a ( pk + t +1) pk + t +1 j , . . . , a ( pk + t +1) pk + tj = a ( pk + t ) pk + tj - Reg ( t -1) a ( pk + t +1) pk + t +1 j , b ( pk + t +1) pk +1 = b ( pk + t ) pk +1 - Reg (0) b ( pk + t +1) pk + t +1 , b ( pk + t +1) pk +2 = b ( pk + t ) pk +2 - Reg (1) b ( pk + t +1) pk + t +1 , . . . . . b ( pk + t +1) pk + t = b ( pk + t ) pk + t - Reg ( t -1) b ( pk + t +1) pk + t +1 Reg (0) = a ( pk + t ) pk +1 pk + t +1 , Reg (1) = a ( pk + t ) pk +2 pk + t +1 , . . . , Reg ( t -1) = a ( pk + t ) pk + tpk + t +1 , a ( pk + t +1) pk +1 j = a ( pk + t ) pk +1 j - Reg (0) a ( pk + t +1) pk + t +1 j , a ( pk + t +1) pk +2 j = a ( pk + t ) pk +2 j - Reg (1) a ( pk + t +1) pk + t +1 j , . . . , a ( pk + t +1) pk + tj = a ( pk + t ) pk + tj - Reg ( t -1) a ( pk + t +1) pk + t +1 j , b ( pk + t +1) pk +1 = b ( pk + t ) pk +1 - Reg (0) b ( pk + t +1) pk + t +1 , b ( pk + t +1) pk +2 = b ( pk + t ) pk +2 - Reg (1) b ( pk + t +1) pk + t +1 , . . . . . b ( pk + t +1) pk + t = b ( pk + t ) pk + t - Reg ( t -1) b ( pk + t +1) pk + t +1 for pk + t + 2 ≤ j ≤ n, a gateway means connected to said memory means or to said pivot choosing means, respectively, to enable communication with the outside of said processing element, and wherein said main controller means further comprising means to control said plurality of clusters of processing elements, said network means, said memory means, said gateway means, said transmitter means, said pivot choosing means, said preprocessing means A 1 , said preprocessing means A t , said updating means B, said backsubstitution means, said updating means and said post processing means C t in such a way that either wherein if the (pk + 1 )th through (p + 1 )k-th rows of said A (0) and corresponding components of said b (0) and x are assigned to said cluster CL u , then said pivot choosing means of said processing element PE 1 of said CL u determining the transposed pivot a ( pk ) / pk +1 pk +1 of the (pk + 1)th row, and said preprocessing means A 1 of said processing element of CL u simultaneously calculating a ( pk +1) / pk +1 j and b ( pk +1) / pk +1 for pk + 2 ≤ j ≤ n and Reg (0) / pk + t pk + t with said each preprocessing means A 1 calculating for elements and components in its charge, and said transmitter means transmitting the results to said memory means of said every other cluster through said C gateway means, while said updating means of said processing element in charge of the i-th row calculating Reg (0) / i for every i such that (p + 1)k, + 1 ≤ i ≤ n, for 2 ≤ t ≤ k, said preprocessing means A t of said cluster CL u simultaneously calculating Reg (0) / pk + t , Reg (1) / pk + t , Reg ( t -2) / pk + t , a ( pk + t -1) / pk + tj and b ( pk + t -1) / pk + t for pk + t ≤ j ≤ n with said each preprocessing means A t calculating for elements and components in its charge, immediately after said pivot choosing means of said PE t of said CL u determining the pivot a ( pk + t -1) / pk + t pk + t , and a ( pk + t ) / pk + tj and b ( pk + t ) / pk + t for pk + t + 1 ≤ j ≤ n, and said transmitter means transmitting the results to said memory means of said every other cluster through said C gateway means, while said updating means of said processing element in charge of the i-th row calculating for every i such that (p + 1)k + 1 ≤ i ≤ n, and wherein said updating means B of said each processing element in charge of the i-th row such that (p + 1 )k + 1 ≤ i ≤ n calculating Reg (0) / i , Reg (1) / i , Reg ( k -1) / i , a (( p +1) k ) / ij and b (( p +1) k ) / i for (p + 1)k + 1 ≤ j ≤ n retaining the values of Reg (0) / i ,..., Reg ( k ) / i in said register set, and wherein said back-substitution means of said each cluster in charge of the i-th and h-th components calculating x i and b ( n + h - i +1) / h for 1 ≤ h ≤ i - 1 for i = n, n - 1, ..., 1 in this order of i, or wherein if the (pk + 1)th through (p + 1)k-th rows of said A (0) and corresponding components of said b (0) and x are assigned to said cluster CL u , then said pivot choosing means of said processing element PE 1 of said CL u determining the transposed pivot a ( pk ) / pk +1 pk +1 the (pk + 1)th row, and said preprocessing means A 1 of said processing element of said CL u simultaneously calculating a ( pk +1) / pk +1 j and b ( pk +1) / pk +1 for pk + 2 ≤ j ≤ n with said each preprocessing means A 1 calculating for elements and components in its charge, and said transmitter means transmitting the results to said memory means of said every other cluster through said C gateway means, while said updating means B' of said processing element in charge of the i-th row calculating Reg (0) / i for every i such that (p + 1)k + 1 ≤ i ≤ n, for t = 2, 3, ..., k, said preprocessing means A t of said processing element of said cluster CL u simultaneously calculating Reg (0) / pk + t , Reg (1) / pk + t , Reg ( t -2) / pk + t , a ( pk + t -1) / pk + ti and b ( pk + t -1) / pk + t for pk + t ≤ j ≤ n with said each preprocessing means A t calculating for elements and components in its charge and, immediately after said pivot choosing means of said processing elements PE t of said CL u determining the pivot a ( pk + t -1) / pk + t pk + t , simultaneously calculating a ( pk + t ) / pk + tj and b ( pk + t ) / pk + t for pk + t + 1 ≤ j ≤ n, and said transmitter means transmitting the results to said memory means of said every other cluster through said C gateway means, while said updating means B' of said processing element in charge of the i-th row calculating for every i such that (p + 1)k + 1 ≤ i ≤ n, wherein said updating means B' of said each processing element in charge of the i-th row such that 1 ≤ i ≤ pk or (p + 1 )k + 1 ≤ i ≤ n if n is a multiple of k or p < [n/k] and 1 ≤ i ≤ [n/k]k also calculating Reg (0) / i , Reg (1) / i , Reg ( k -1) / i , a (( p +1) k ) / ij and b (( p +1) k ) / i for (p + 1)k + 1 ≤ j ≤ n if n is a multiple of k or p < [n/k] and for [n/k]k + 1 ≤ j ≤ n otherwise, retaining the values of Reg (0) / i , . . . , Reg ( k ) / i in the register set, and wherein said postprocessing means C t of said processing element of said CL u simultaneously calculating Reg (0) , Reg (1) , Reg (t-1) , a ( pk + t +1) / pk +1 j , a ( pk + t +1) / pk +2 j , a ( pk + t +1) / pk + tj , b ( pk + t +1) / pk +1, b ( pk + t +1) / pk +2 and b ( pk + t +1) / pk + t for j such that pk + t + 2 ≤ j ≤ n for t = 1, 2, ..., k - 1 if n is a multiple of k or p < [n/k] and for t = 1, 2, ..., n - [n/k]k otherwise, respectively, in order to carry out a post elimination. The apparatus claim 5 wherein said main controller means further comprising means to distribute and assign the rows of said coefficient matrix A (0) and the components of said b (0) and x to said clusters in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to said memory means of said one cluster in the cyclic order of CL 0 , ..., CL P-1 , CL 0 , CL 1 , ..., and wherein said main controller means further comprising means to instruct, in case n is a multiple of k, said each cluster to execute parallel preprocessing and parallel updating for p = 0, 1, ..., n/k - 2 and to execute parallel preprocessing for p = n/k - 1, wherein said main controller means further comprising means to instruct, in case n is not a multiple of k, and, said each cluster to execute parallel preprocessing and parallel updating for p = 0, 1, ..., [n/k] - 1 and to execute parallel preprocessing for p = [n/k], and to instruct said each cluster to obtain said unknown vector x by executing said back-substitution. The apparatus of claim 5 wherein said main controller means further comprising means to distribute and assign the rows of said coefficient matrix A (0) and the components of said b (0) and x to said clusters in such a manner as each block of consecutive k rows and corresponding 2k components is transmitted to said memory means of said one cluster in the cyclic order of CL 0 , ..., CL P-1 , CL 0 , CL 1 ,..., and, wherein said main controller means further comprising means to instruct, in case n is a multiple of k, said each cluster to execute parallel preprocessing parallel updating and parallel post-elimination for p = 0, 1, ..., n/k - 1, and wherein said main controller means further comprising means to instruct, in case n is not a multiple of k, said each cluster to execute parallel preprocessing parallel updating, and post-elimination for p = 0, 1,..., [n/k] - 1 and to execute said parallel preprocessing parallel updating, and post-elimination for p = [n/k]. A parallel computer to solve a system of linear equations comprising, a plurality CL 1 -CL C of C clusters of processing elements, connected by network means, said each cluster comprising a plurality P c of processing element and a shared memory means to store a coefficient matrix A (0) and a corresponding known components vector b (0) and to store part of intermediate reduced matix A (r) and corresponding known components vector b (r) and an unknown vector x expressed by A ( r ) = ( a ( r ) ij ), 1 ≤ i, j ≤ n , b ( r ) = ( b ( r ) 1 , b ( r ) 2 , . . . , b ( r ) n ) t , x = ( x 1 , x 2 , . . . , x n ) t for 0 ≤ r ≤ n and r is a positive integer, for a given system of linear equations A (0) x = b (0) , said parallel computer further comprising: a data distribution means to distribute the rows of said coefficient matrix A (0) and the components of said vectors b (0) and x to said shared memory means of said clusters wherein said distribution means further comprising means to transmit each block of consecutive k rows and corresponding 2k components to said shared memory in the cyclic order of CL 1 , ..., CL C , CL 1 , CL 2 , ..., and means to assign said blocks distributed to said cluster's shared memory means to its said element processors row by row, a pivot choosing means to choose a pivot in a row assigned to said each element processor according to a partial pivoting algorithm, that is the pivot of a row is the element having the maximum value; a pre-elimination means comprising means further comprising means to determine the transposed pivot for a given positive integer k and a value of a nonnegative integer parameter p, and wherein said transposed pivot is a ( kPc ) / kPc +1 kPc +1 to calculate a ( kP c +1) kP c +1 j = a ( kP c ) kP c +1 j / a ( kP c ) kP c +1 kP c +1 , b ( kP c +1) kP c +1 = b ( kP c ) kP c +1 / a ( kP c ) kP c +1 kP c +1 in said element processor in charge of the (kP c + 1)th row after said pivot choosing means determines said transposed pivot a ( kPc ) / kPc +1 kPc +1 , means to transmit the results to said shared memory means of said every other cluster to which said processing element in charge of an i-th row such that kP c + 1 ≤ i ≤ n belongs, and means to calculate, for I = 2, ... , P c , for kP c + | ≤ i ≤ n in said element processor in charge of the i-th row, means to calculate in said processing element in charge of the (kP c + l)th row, and, means to calculate a ( kP c + l ) kP c + lj = a ( kP c + l -1) kP c + lj / a ( kP c + l -1) kP c + lkP c + l , b ( kP c + l ) kP c + l = b ( kP c + l -1) kP c + l / a ( kP c + l -1) kP c + lkP c + l in said processing element in charge of the (kP c + l)th row after said pivot choosing means determines said transposed pivot a ( kPc + l -1) / kPc + l kPc + l , means to transmit the results a ( kP c + l ) kP c + lj = a ( kP c + l -1) kP c + lj / a ( kP c + l -1) kP c + lkP c + l , b ( kP c + l ) kP c + l = b ( kP c + l -1) kP c + l / a ( kP c + l -1) kP c + lkP c + l to said shared memory means of every other cluster to which said processing element in charge of an i-th row such that kP c + I + 1 ≤ i ≤ n belongs, a multi-pivot elimination means comprising means to calculate in said each element processor in charge of the i-th row such that (k + 1)P c + 1 ≤ i ≤ n, a post-elimination processing means to calculate a ( r +1) ij = a ( r ) ij - a ( r ) ii + l a ( r +1) i + lj , b ( r +1) i = b ( r ) i - a ( r ) ii + l b ( r +1) i + l for I = - w + q + 1 for w = 1, ..., q and q = 1, ..., P c - 1 for kP c + 1 ≤ i ≤ kP c + q in said element processor in charge of the i-th row, means for testing whether said operation executed by said multipivot elimination means or said post-elimination processing means were executed [n/P c ] times, whereby said post-elimination means further comprising means to calculate a ( r +1) ij = a ( r ) ij - a ( r ) ii + l a ( r +1) i + lj , b ( r +1) i = b ( r ) i - a ( r ) ii + l b ( r +1) i + l in said element processor in charge of the i-th row, and a remainder elimination means to enable calculation of said pre-elimination means for the ([n/P c ]P c + 1)th row through the n-th row - and in case (b) also to enable calculation of said multi-pivot elimination means and said post-elimination means - if said testing means judges that the operation of said multi-pivot elimination means was executed [n/P c ] times, and n is not a multiple of P c . The parallel computer of claim 8, whereby said testing means further comprising means to check if the multipivot elimination means executed their operations in [n/P c ] times, said computer further comprising an elementary back-substitution means to calculate x i = b ( n ) i in said processing element in charge of the i-th row back-transmission means to transmit x i to said shared memory means of said every cluster to which said processing element in charge of an h-th row such that 1 ≤ h ≤ i - 1 belongs, a back-calculation means to calculate b ( n + h - i +1) h = b ( n + h - i ) h - a ( h ) hi x i for 1 ≤ h ≤ i - 1 in said processing element in charge of the h-th row, and a means for testing if the operation of said elementary back-substitution means was repeated from i = n to i = 1. The parallel computer of claim 8, whereby said testing means further comprising means to check if the multi-pivot elimination means executed their operations in [n/P c ] times and wherein said pivot choosing means further comprising: a search means to search for a nonzero element in the order of increasing column numbers from the diagonal element in the same row, if a diagonal element of said coefficient matrix A (r) is 0, a column number broadcasting means to notify said other processing element of the column number of a nonzero element found by said search means, an element interchange means to interchange said two elements which are in charge of said processing element and have the same column numbers as the above diagonal zero element and the found nonzero element, and a component interchange means to enable said two processing element to interchange the two components of said unknown vector which are in their charge and have the same component indices as the column numbers of said diagonal zero element and said found nonzero element. The parallel computer of claim 8, whereby said testing means further comprising means to check if the multi-pivot elimination means executed their operations in [n/P c ] times and wherein said pivot choosing means further comprising: a search means to search for an element with the greatest absolute value in the order of increasing column numbers from a diagonal element in the same row, a column number broadcasting means to notify said other processing element of the column number of an element found by said search means, an element interchange means to interchange said two elements which are in charge of said processing element and have the same column number as said diagonal element and the found element, and a component interchange means to enable said two processing element to interchange the two components of the unknown vector which are in their charge and have the same component indices as the column numbers of said diagonal element and said found component. The parallel computer of claim 8, wherein said pivot choosing means further comprising: a search means to search for a nonzero element in the order of increasing column numbers from the diagonal element in the same row, if a diagonal element of said coefficient matrix A (r) is 0, a column number broadcasting means to notify said other processing element of the column number of a nonzero element found by said search means, an element interchange means to interchange said two elements which are in charge of said processing element and have the same column numbers as the above diagonal zero element and the found nonzero element, and a component interchange means to enable said two processing element to interchange the two components of said unknown vector which are in their charge and have the same component indices as the column numbers of said diagonal zero element and said found nonzero element. The parallel computer of claim 8, wherein said pivot choosing means further comprising : a search means to search for an element with the greatest absolute value in the order of increasing column numbers from a diagonal element in the same row, a column number broadcasting means to notify said other processing element of the column number of an element found by said search means, an element interchange means to interchange said two elements which are in charge of said processing element and have the same column number as said diagonal element and the found element, and a component interchange means to enable said two processing elements to interchange the two components of the unknown vector which are in their charge and have the same component indices as the column numbers of said diagonal element and said found component.

Inventors: MOCHIZUKI YOSHIYUKI, MOCHIZUKI, YOSHIYUKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1992
Main classification: G06F17
IPC codes: G06F17