Switch coupled between input and output ports in a communication system

Abstract: A switch includes a plurality of memories (30 11 -30 1N ) respectively having write terminals connected to input ports and output terminals, each of the memories including an input acknowledgement signal generating block for generating an input acknowledgement signal (IP) when data is received thereto. A multiplexer (25), which is coupled between the read terminals of the memories and an output port, connects one of the memories to the output port in response to a port number signal. An output controller (80 1 ), which is coupled to the memories and the multiplexer, receives the input acknowledgement signal from each of the memories in order of receipt and generating the port number signal so that data stored in the memories is selected by the multiplexer in order of receipt of the input acknowledgement signal.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention generally relates to cross-point type switches used in an ATM (Asynchronous Transfer Mode) system or a high-bit-rate packet communication system of a broadband ISDN (Integrated Services Digital Network). More specifically, the present invention is concerned with an arrangement for controlling a switching operation on a switch, such as a cross-point type switch, so that input data are switched in order of receipt of the input data. (2) Description of the Prior Art Fig.1 shows a conventional cross-point type switch. The cross-point type switch shown in Fig.1 is composed of an input port group 1 having N input ports (N is an integer larger than 2), an output port group 2 having N output ports, a memory 3, N route setting units 4, and an output controller 8. Memories are arranged in rows and columns. More specifically, the memories are provided at cross points of input lines running in the row direction and output lines running in the column direction. Each of the memories can be formed with, for example, an FIFO (First-In First-Out) memory. The routing units 4 receive data, such as ATM data, received via the input port group 1, and determine paths to which the received data should be output. For example, if data received via input port #1 is requested to be transferred to the output port #2, the received data is stored in the memory located at the cross point of the input line connected to input port #1 and the output line connected to output port #2. The output controller 8 controls the memory 3 so that each of the output lines connected to the output port 2 carries, at one time, one data block (a cell or packet) transferred from any one of input ports #1-#N. That is, the output controller 8 prevents two or more data blocks from being transferred on one of the output lines at one time. Fig.2 shows a procedure how the output controller 8 controls the memory 3. More specifically, Fig.2 shows N FIFO memories 3 11 - 3 1N arranged in the first column, an output-port-#1 controller 8 1 which a part of the output controller 8, and a multiplexer 25. The FIFO memories 3 11 - 3 1N are connected to the multiplexer 25, which is connected to output port #1. When each of the FIFO memories 3 11 - 3 1N receives data transferred to the corresponding output port, each FIFO memory sets an empty flag EF to zero when the FIFO memory has been filled with data and there is no available storage area therein. It will now be assumed that the controller 8 1 controls the memory 3 so that data is transferred to the multiplexer 25. The controller 8 1 sequentially determines whether or not the empty flags EF received from the FIFO memories 3 11 - 3 1N are equal to zero. Then the controller 8 1 controls the multiplexer 25 so that data from the FIFO memories from which the empty flags EF equal to zero have been output are sequentially transferred to output port #1. However, the conventional memory control procedure has the following disadvantages. The controller 8 1 sequentially accesses input ports #1 - #N one by one in order to sequentially determine whether or not the FIFO memory being accessed has an available storage area. It should be noted that the above sequential access to the FIFO memories is carried out without considering how full each FIFO memory is. Hence, there is a possibility that some FIFO memories connected to a certain output port are full and hence it takes a long time to read out all the data therefrom. From document EP 0 292 962 A2 a header driven type packet switching system is known. A first-in/first-out memory is shown for storing the sequence of the requested order of process requests for data stored in memories. In particular, all incoming and outgoing lines required for the system are divided into groups to constitute a two stage structure of incoming and outgoing modules, which are prepared for the respective incoming and outgoing line groups. In each incoming module, outgoing module and outgoing line, information is given to packets, and the data packets are successively transferred from the outgoing modules to the corresponding outgoing lines. SUMMARY OF THE INVENTION It is a general object of the present invention to provide a switch in which the above disadvantages are eliminated. A more specific object of the present invention to provide a switch in which data temporarily stored in memories located at the cross points can be efficiently read out therefrom. The above objects of the present invention are achieved by the features according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional cross-point type switch; Fig.2 is a block diagram showing a part of the switch shown in Fig.1 related to output port #1; Fig.3 is a block diagram showing an outline of the present invention; Fig.4 is a block diagram of a first embodiment of the present invention; Fig.5 is a block diagram of a second embodiment of the present invention; Fig.6 is a block diagram of a third embodiment of the present invention; Fig.7 is a block diagram of a fourth embodiment of the present invention; Fig.8 is a block diagram of a fifth embodiment of the present invention; Fig.9 is a block diagram of a sixth embodiment of the present invention; Fig.10 is a block diagram of a seventh embodiment of the present invention; Fig.11 is a block diagram of an eighth embodiment of the present invention; Fig.12 is a block diagram showing the structure of each FIFO memory provided at each cross point; and Fig.13 is a block diagram of a multiplexer shown in Fig.3. DESCRIPTION OF THE PREFERRED EMBODIMENTS The entire block structure of the present invention is as shown in Fig.3. That is, the present invention includes a memory, an output controller, and route setting units. The memory of the present invention is indicated by a reference numeral "30", and the output controller thereof is indicated by a reference numeral "80". Fig.3 is a block diagram of a part of the switch of the present invention. In Fig.4, there are illustrated a part of the memory 30 related to output port #1, and an output-port-#1 controller 80 1 which is a part of the output controller 80. The memory 30 includes FIFO memories 30 11 - 30 1N connected to output port #1. The controller 80 1 receives an input data existence/non-existence signal IP, which is generated by each of the FIFO memories 30 11 - 30 1N each time data is received. Hereinafter, the input data existence/non-existence signal IP is simply referred to as an input acknowledgement signal IP. In this manner, the output controller 80 receives the input acknowledgement signals IP from all the FIFO memories arranged in rows and columns, and puts them in receiving order. The controller 80 1 controls the multiplexer 25 on the basis of the input acknowledgement signals IP from the FIFO memories 30 11 - 30 1N so that data stored therein are read out in receiving order. The controller 80 1 outputs the oldest input acknowledgement signal IP to the multiplexer 25, which selects the FIFO memory related to the oldest input acknowledgement signal IP and passes data read out therefrom to output port #1. As a result, the aforementioned problem in which data continuously remain in the FIFO memories for a long time. Fig.4 shows a first embodiment of the present invention. The structure shown in Fig.4 is a part of the output controller 80, and corresponds to the controller 80 1 . The controller 80 1 is composed of coders 26 1 - 26 N , a multiplexer 27 and an order control memory formed with, for example, an FIFO memory 28. The coders 26 1 - 26 N receive the input acknowledgement signals IP 1 - IP N and convert them into the corresponding port numbers. For example, when the coder 26 1 receives the input acknowledgement signal IP1, it generates the input port number indicating port #1. The multiplexer 27 receives the port numbers from the coders 26 1 - 26 N and multiplexes them (outputs the port numbers one by one). The order control memory 28 stores the port numbers from the multiplexer 27 in receiving order. The port numbers sequentially stored in the order control memory 28 are sequentially output to the multiplexer 25 shown in Fig.3. In other words, the port numbers are written into the order control memory 28 and read out therefrom by the first-in first-out procedure. In response to the port number, the multiplexer 25 selects the corresponding FIFO memory and transfers data stored therein to the corresponding output port (#1 in the case shown in Fig.3). The number of bits for forming the port number depends on the number of input ports. If 128 input ports are used, the port number is described by seven bits. In the structure shown in Fig.4, if some of the decoders 26 1 - 26 N simultaneously output the port numbers to the multiplexer 27, the multiplexer 27 processes these port numbers one by one in a predetermined sequence, for example, an increasing order of port number. That is, the priority becomes higher as the port number decreases. Fig.5 is a block diagram of the controller 80 1 according to a second embodiment of the present invention. In Fig.5, parts which are the same as those shown in the previously described figures are given the same reference numerals. The controller 801 shown in Fig.5 includes timing controllers 29 1 - 29 N , a write controller 30, a read controller 31 and a coder 32 in addition to the above-mentioned order control memory 28. The timing controllers 29 1 - 29 N synchronize the input acknowledgement signals IP 1 - IP N with each other. The synchronized input acknowledgement signals IP 1 - IP N , which are arranged, for example, in parallel, are applied to the order control memory 28 and the write controller 30. The synchronized input acknowledgement signals IP 1 - IP N are sequentially written into the FIFO memory under the control of the write controller 30. When each of the input acknowledgement signals IP i (i = 1, 2, ..., N) is equal to 1, it shows that the corresponding FIFO memory stores data which should be transferred to the corresponding output port. When each of the input acknowledgement signals IP i is equal to 0, it shows that the corresponding FIFO memory does not store data. In this case, the synchronized input acknowledgement signals IP 1 - IP N arranged in parallel are as follows: "100111100.....". This N-bit data train is written into the order control memory 28. The position of each bit of the N-bit data train corresponds to the port number. For example, the beginning bit of the N-bit data train corresponds to input port #1. If all the bits are zeros, the write controller 30 inhibits such data from being written into the order control memory 28. The read controller 31 sequentially reads out the N-bit data train from the order control memory 28, and outputs it to the coder 32. The coder 32 receives each bit "1" contained in the N-bit data train and generates the corresponding port number. The multiplexer 25 selects the FIFO memory connected to the output port specified by the port number, and transfers the data read out therefrom to the output port. Fig.6 shows a third embodiment of the present invention. In Fig.6, parts which are the same as those shown in Fig.4 are given the same reference numerals. The control part 80 1 shown in Fig.6 includes a counter 33 and a selector 34 in addition to the coders 26 1 - 26 N , the multiplexer 27 and the order control memory 28. The counter 33 increments its counter value by 1 in response to an increment signal when there is no port number stored in the order control memory 28. The incremented counter value is output to the selector 34, which outputs the incremented counter value to the multiplexer 25 by a poling process. The incremented counter number serves as the port number. Normally, no data is read out from the FIFO memory specified by the incremented counter number, because the incremented counter number is generated when there is no data stored in the FIFO memories 30 11 - 30 1 (Fig.3). However, there is a possibility that data may be stored in some FIFO memories in some cases, such that the input acknowledgement signal IP i was not generated due to a certain cause, or the coder 26 did not generate the port number. The above poling process is effective to such cases. The FIFO memories 30 11 - 30 1 are sequentially accessed by the poling process. The selector 34 selects either the port number read out from the order control memory 28 or the port number (counter value) output by the counter 33. When the incremented signal is output from the order control memory 28, the selector 34 selects the counter 33. Fig.7 shows a fourth embodiment of the present invention. In Fig.7, parts which are the same as those shown in the previously described figures are given the same reference numerals. The fourth embodiment shown in Fig.7 is obtained by adding the poling process used in the third embodiment shown in Fig.6 to the structure of the second embodiment shown in Fig.5. That is, the counter 33 and the selector 34 as shown in Fig.6 are added to the structure shown in Fig.5. When there is no data in the order control memory 28, the increment signal is output to the counter 33 via the read controller 31. The counter 33 increments its counter value by 1, and the selector 34 selects the incremented counter value output by the counter 33. Fig.8 shows a fifth embodiment of the present invention. In Fig.8, parts which are the same as those shown in the previous figures are given the same reference numerals. The structure shown in Fig.8 is obtained by adding a counter 35 to the structure shown in Fig.4. The basic operation of the controller 80 1 is the same as that of the controller 80 1 shown in Fig.4. As has been described previously, if some of the coders 26 1 - 26 N output the port numbers to the multiplexer 27 at the same time, the multiplexer 27 processes these port numbers one by one in the predetermined sequence or priority. The counter 35 is a cyclic counter, which sequentially and periodically generates the port numbers of the input ports #1 - #N by periodically increasing the counter number by a predetermined number. The multiplexer 27 compares the counter value of the counter 35 with the port numbers simultaneously received from the coders 26 1 - 26 N . The multiplexer 27 selects the port number which is closest to the counter value. That is, the highest priority is assigned to the port number closest to the counter value. In the above manner, the priority of selection in the multiplexer 27 is sequentially varied based on the counter value of the counter 35. Fig.9 shows a sixth embodiment of the present invention. In Fig.9, parts which are the same as those shown in the previous figures are given the same reference numerals. The sixth embodiment shown in Fig.9 is obtained by adding the counter shown in Fig.8 to the structure shown in Fig.5. The counter 35 shown in Fig.5 is connected to the coder 32. The basic operation of the sixth embodiment is the same as the operation of the structure shown in Fig.5. The counter 35 cyclically increments its counter value, which is converted by the coder 32. The input port number closest to the counter value is given the highest priority. Since the counter value is incremented, the reference value for selecting one of the input port numbers simultaneously generated is changed. Fig.10 shows a seventh embodiment of the present invention. In Fig.10, parts which are the same as those shown in the previous figures are given the same reference numerals. The structure shown in Fig.10 is obtained by adding the counter 35 to the structure shown in Fig.6. Fig.11 shows an eighth embodiment of the present invention. In Fig.11, parts which are the same as those shown in the previous figures are given the same reference numerals. The structure shown in Fig.11 is obtained by adding the counter 35 to the structure shown in Fig.7. Each of the FIFO memories provided at the cross points of the memory is configured as shown in Fig.12. As shown in Fig.12, each of the FIFO memories 30 11 - 30 1N is formed with a dual-port memory, which is composed of a two-port RAM 41, a write counter 42, a read counter 43, a comparator 44 and a logic gate 45. The two-port RAM 41 receives data via a data input terminal D, and outputs data via a data output terminal D. A write signal is applied to the write counter 42, which generates a write address. A read signal is applied to the read counter 43, which generates a read address. The write address is applied to a write address terminal A of the two-port RAM 41, which receives the read address via a write address terminal A. Normally, the write address proceeds to the read address. The comparator 44 compares the write address and the read address with each other, and outputs a full flag signal to the logic gate 45. The full flag signal switches to a low level from a high level when the two-port RAM 41 has become filled with data. The logic gate 45 is formed with an AND gate. When the write signal is applied to the write counter 42 in the state where the two-port RAM 41 has not yet been filled with data, the input acknowledgement signal IP i is generated by the logic gate 45. Fig.13 shows the multiplexer 25 shown in Fig.3. The multiplexer 25 is composed of a selector 51 and a decoder 52. The port number output by the output controller 80 is applied to the selector and the decoder 52. The selector 52 selects the FIFO memory specified by the received port number. The decoder 52 decodes the received port number and generates a read signal which should be applied to the FIFO memory connected to the selected input port. The read signal thus generated is applied to, for example, the read counter 43. The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the invention as defined by the appended claims. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A switch comprising: a plurality of memories (30 1l -30 1N ) respectively having write terminals connected to input ports and output terminals, each of said memories comprising input acknowledgement signal generating means (45) for generating an input acknowledgement signal (IP) when data is received thereto; multiplexer means (25), coupled between the read terminals of said memories and an output port, for connecting one of the memories to the output port in response to a port number signal; and output control means (80 1 ), coupled to said memories and said multiplexer means, for receiving said input acknowledgement signal from each of said memories in order of receipt and generating said port number signal so that data stored in said memories is selected by said multiplexer means in order of receipt of said input acknowledgement signal, said output control means (80 1 ) including an order control memory means (28) and a coder means (32) ; characterized in that said output control means further comprises: synchronizing means (29 1 -29 N ) for synchronizing input acknowledgement signals from the memories with each other and for outputting N-bit data trains of synchronized input acknowledgement signals sequentially into the order control memory means (28); control means (31) for sequentially reading each N-bit data train stored in the order control memory means (28) into the coder means (32); and counter means (35), coupled to said coder means (32), for generating a cyclic counter value to the coder means (32), and wherein said multiplexer means (25) is operable to select periodically one of the memories in response to the port number signal derived from said cyclic counter value by said coder means, wherein said order control memory means (28) is coupled to said synchronizing means, for storing the input acknowledgement signals and outputting the input acknowledgement signals by a first-in first-out process; and said coder means (32) is coupled between said order control memory means (28) and said multiplexer means (25) for sequentially generating the input port number more closest to the value generated by the counter means (35) and thereby periodically indicating one of the memories to the multiplexer means (25) each time the input acknowledgement signal is read out from said order control memory means (28). A switch as claimed in Claim 1, wherein said output control means further comprises: counter means (33), coupled to said order control memory means, for generating a counter number which is incremented when there is no data in said order control memory means, said counter number serving as a port number signal; and selector means (34), coupled to said order control memory means (28), said counter means and said multiplexer, for outputting the port number signal from said order control memory means to said multiplexer means when said order control memory means stores the port number signal and for outputting the counter number from said counter means when there is no data in said order control memory means. A switch as claimed in Claim 1, wherein said output control means comprises: further counter means (33), coupled to said order control memory means, for generating a counter number which is incremented when there is no data in said order control memory means, said counter number serving as a port number signal; and selector means (34), coupled to said order control memory means, said further counter means and said multiplexer, for outputting the port number signal from said coder means to said multiplexer means when said order control memory means stores the port number signal and for outputting the counter number from said further counter means when there is no data in said order control memory means.

Inventors: SHIMOE TOSHIO, SHINOMIYA TOMOHIRO, TAKEO HIROSHI, SHIMOE, TOSHIO, SHINOMIYA, TOMOHIRO, TAKEO, HIROSHI
Applicants: FUJITSU LTD, NIPPON TELEGRAPH AND, FUJITSU LIMITED
Application year: 1992
Main classification: H04L12
IPC codes: H04J3