Improved method and circuit for historical control of thermal printing

Abstract: A historical control circuit in a thermal printer controls the drive current fed to a resistive heating element (2) according to the printing of previous dots by that resistive heating element (2). The circuit remembers whether or not the heating element (2) printed a certain number of preceding dots and, for each printed dot among those dots, masks an interval in the drive signal. This is done in such a way that if two patterns of previous dots contain unequal numbers of printed dots but generate equal residual temperatures, the drive signal for the pattern with more printed dots is divided into more separate pulses. Adjustments can be made by masking or unmasking a specific interval for a specific pattern. Cutoff of the drive signal may be delayed for patterns in which a certain number of most recent dots were all unprinted.

Description: This invention relates to the art of thermal printing, more particularly to an improved circuit for performing historical control of the printing process. Because of their simple construction, quiet operation, and low cost, thermal printers are widely used as output devices of facsimile machines, word processors, and personal computers. A thermal printer has a number of resistive heating elements equal, for example, to the number of dots across a page in the horizontal direction, or the number of dots per character in the vertical direction. Printing takes place as a page is scrolled past these resistive heating elements, or as the resistive heating elements travel across the page on a movable print head. When a dot is to be printed, current is fed to the corresponding resistive heating element, raising its temperature. The heat thus generated darkens the adjacent portion of the page, if thermosensitive paper is used, or causes transfer of ink from a ribbon to the page in printers using plain paper. A problem in thermal printing is that when a resistive heating element prints a series of dots, the dots tend to get successively darker because of residual heat. This problem can be overcome by regulating the amount of printing current fed to the resistive heating element according to the printing or non-printing of the last few dots, a technique known as historical control. A prior-art method of historical control supplies a current pulse of a certain length to print a dot, but masks parts of that pulse for dots printed by the same resistive heating element in the previous two lines. (The "line" may be horizontal or vertical, depending on the configuration of the printer.) This method improves the appearance of the printed output, but does not achieve completely uniform dots; more refined forms of historical control are necessary. Attempts at refining historical control, however, have encountered certain problems. One problem is that the heating curve of a resistive heating element is not linear, so simplistic schemes of regulating the amount of current according to the number of historical dots printed are unsatisfactory. An ideal solution would be to track the printing history of the resistive heating element through a large number of past dots and calculate the optimum current to be fed for every historical pattern of dots, but this scheme would encounter a second problem: the necessary control circuitry would be highly complex and require an impractically large number of signal lines. It is accordingly an object of the present invention to provide simple but accurate means of historical control. Another object of the invention is to compensate for non-linearity in historical control. According to the present invention, a historical control circuit is provided as defined in claim 1. The invention will be explained in more detail below with reference to preferred embodiments and the accompanying drawings. Fig. 1 is a graph of the heating and cooling curve of resistive heating element. Fig. 2 is a graph illustrating heating and cooling when consecutive dots are printed. Fig. 3 is a graph illustrating four two-dot historical heating patterns. Fig. 4 is a chart summarizing the information in Fig. 3. Fig. 5 is a block diagram illustrating a prior-art historical control circuit. Fig. 6 is a timing diagram illustrating prior-art historical control. Fig. 7 is a block diagram illustrating a first embodiment of the historical control circuit according to the invention. Fig. 8 is a timing diagram illustrating historical control by the first embodiment of the invention. Fig. 9 is a drawing illustrating a pattern of dots. Fig. 10 is a graph of a heating curve for the pattern in Fig. 9. Fig. 11 is a drawing illustrating another pattern of dots. Fig. 12 is a graph of the heating curve for the pattern in Fig. 11. Fig. 13 is a chart summarizing the eight three-dot historical heating patterns. Fig. 14 is a block diagram of another circuit arrangement. Fig. 15 is a timing diagram illustrating historical control with the circuit of Fig. 14. Fig. 16 is a chart summarizing the sixteen four-dot historical heating patterns. Fig. 17 is a block diagram of a further circuit arrangement. Fig. 18 is a timing diagram illustrating historical control with the circuit of Fig. 17. Fig. 19 is a block diagram of an embodiment of the invention. Fig. 20 is a block diagram of a further arrangement not part of the invention. Fig. 21 is a timing diagram illustrating historical control with the circuit of Fig. 20. Fig. 22 is a block diagram of another circuit not part of the invention. Fig. 23 is a timing diagram illustrating historical control with the circuit of Fig. 22. Fig. 24 is a block diagram of another circuit not part of the invention. Fig. 25 is a timing diagram illustrating historical control with the circuit of Fig. 24. Before the invention is described in detail, it will be useful to discuss certain aspects of the theory of thermal printing and illustrate how the theory works in the relevant prior art. Temperature values and other numerical values will be shown, but these values are illustrative only and do not restrict the scope of the invention. Fig. 1 illustrates the effect of feeding a one-millisecond current pulse to a resistive heating element, showing the temperature on the vertical axis and the time on the horizontal axis. During the duration of the pulse the temperature of the resistive heating element rises from 20 °C to 300 °C, rising steeply at first and then more gradually. After the current has been switched off the resistive heating element cools at an even more gradual rate. The heating and cooling curves are both nonlinear. The heating curve can be described by an equation of the form: Δ T = Pd·Rth {1 - exp(-t/τ)} where Pd is applied power, Rth is the thermal resistance of the resistive heating element, t is the length of the current pulse, and τ is a time constant. Fig. 2 shows the effect of successive current pulses. Because the resistive heating element cools more slowly than it heats, each successive pulse takes the resistive heating element from a higher starting temperature to a higher peak temperature, until a saturation state is reached at a maximum peak temperature of nearly 500 °C. Fig. 3 shows a somewhat simplified simulation of the printing of a dot preceded by four different two-dot historical patterns, without historical control. The letter H (High) is used to represent the feeding of current, i.e. the printing of a dot. The letter L (Low) is used to present non-feeding of current, i.e. non-printing of the dot. Similar notation will be used throughout the description of the invention: H will represent the high or active state; L will represent the low or inactive state. The L-L-H pattern takes the resistive heating element to a certain maximum temperature, e.g. the temperature 300 °C shown in Fig. 1, and leaves it at a certain residual temperature, represented in Fig. 3 by the value 1 on a normalized point scale. The H-L-H pattern yields higher maximum and residual temperatures, hence a darker dot. The L-H-H pattern yields a still higher maximum temperature and an even darker dot. The highest temperature and darkest dot of all are given by the H-H-H pattern. Fig. 4 summarizes the information in Fig. 3 in chart form. The four patterns are listed in the center column; the symbols Q1, Q2, and Q3 refer to latch outputs described later. The left-hand column indicates the level of each pattern. Here the word "level" is used to mean the number of printed dots in the pattern, including the present dot which is printed in all four patterns. The right-hand column lists the point values which represent residual temperature on the normalized scale employed in Fig. 3. Fig. 5 shows a prior-art circuit for historical control. The circuit comprises a resistive heating element 2, a driver circuit 4, a latch 6, a pulse generator 8, and a logic circuit 10. Data to be printed are supplied from a shift register 12. The resistive heating element 2 generates printing heat when fed current from the driver circuit 4. The driver circuit 4, which comprises two transistors connected in a Darlington pair configuration, is activated by a drive signal. The latch 6 has a data input terminal coupled to the shift register 12, a latch input terminal (LA) for receiving a latch signal, and three output terminals Q1, Q2, and Q3. When it receives a latch signal, the latch 6 latches the input at its data terminal and outputs this data value at the Q1 terminal. At the same time, it shifts data stored in well-known internal circuits so that the previous Q1 output becomes the new Q2 output, and the previous Q2 output becomes the new Q3 output. The Q1 output is a dot printing signal indicating whether or not to print the present dot. The Q2 output is an historical dot signal indicating whether or not the immediately preceding dot was printed. The Q3 output is another historical dot signal indicating whether the dot before that was printed. The pulse generator 8 generates a drive pulse at an output terminal marked GA, and two masking pulses at output terminals marked GB and GC. Pulse generating circuits are well known, so that internal structural details of the pulse generator 8 are omitted. The logic circuit 10 comprises two NAND gates 14 and 16 and a four-input AND gate 18. The NAND gate 14 gates the masking pulse from the GC terminal of the pulse generator 8 with the historical dot signal from the Q2 terminal of the latch 6: the output of the NAND gate 14 is inactive when GC and Q2 are both active, and active at all other times. The NAND gate 16 similarly gates the GB masking pulse with the Q3 historical dot signal. The AND gate 18 receives as inputs the dot printing signal from the Q1 terminal of the latch 6, the drive pulse from the GA terminal of the pulse generator 8, and the outputs of the NAND gates 14 and 16, and generates the drive signal that activates the driver circuit 4. The drive signal is active when all inputs to the AND gate 18 are active, and inactive at other times. The shift register 12 receives serial dot data in synchronization with a clock signal, stores the quantity of dot data necessary for printing one line, and outputs this line of dot data in parallel to a plurality of historical control circuits identical to the one illustrated in Fig. 5. These historical control circuits all share the same pulse generator 8. Referring to Fig. 6, the prior-art historical control circuit operates as follows. First the shift register 12 receives a series of clock signals, causing it to input and store one line of dot data. Next a latch signal is input, causing the latch 6 to latch one bit of dot data output by the shift register 12; then the pulse generator 8 generates a drive pulse at GA and masking pulses at GB and GC. The masking pulses GB and GC are of equal length. The masking pulse GC is timed to coincide with an initial interval of the drive pulse GA; the masking pulse GB coincides with an immediately following interval. If a dot is to be printed, as indicated by active (H) output at Q1, the logic circuit 10 sends a drive signal to the driver circuit 4. The shape and duration of the drive signal depend on the pattern of historical dots. The current pulse fed by the driver circuit 4 to the resistive heating element 2 has the same shape as the drive signal. If the two preceding dots were not printed, i. e. when Q2 and Q3 are both inactive (L), the drive signal consists of a single pulse equal in duration to the drive pulse GA, as shown for the L-L-H pattern in Fig. 6. If the preceding dot was not printed but the dot before that was printed (the H-L-H pattern), the historical dot signal Q3 is active, so the drive signal is masked during the interval while the masking pulse GB is active. Similarly, in the L-H-H pattern the drive pulse is masked in the interval while GC is active. In the H-H-H pattern the drive signal is masked in both of these intervals. Referring back to Fig. 4, it can be seen that the resistive heating element 2 receives the most current for the L-L-H pattern on level one, which has the lowest point value, and the least current for the H-H-H pattern on level three, which has the highest point value. The two patterns on level two, which have intermediate point values, receive an intermediate amount of current. In this way the historical control circuit compensates for residual heat effects over the two preceding dots. Due to the nonlinearity of the heating-cooling curve in Fig. 1, however, the historical control illustrated in Figs. 5 and 6 does not compensate for residual heating with complete accuracy. Specifically, dots printed by the H-L-H, L-H-H, and H-H-H patterns tend to be darker than a dot printed by the L-L-H pattern. Fig. 7 shows an embodiment of the present historical control circuit that provides additional compensation. The resistive heating element 2, the driver circuit 4, the latch 6, the pulse generator 8, the logic circuit 10, and the shift register 12 are similar to the elements with the same reference numerals in Fig. 5. The only difference is that the AND gate 18 in the logic circuit 10 has five inputs instead of four. The further elements in Fig. 7 are a strobe circuit 20 and a pulse replacing circuit 22. The strobe circuit 20 comprises, for example, an inverting amplifier that inverts a strobe input signal to generate a second drive pulse. The second drive pulse is shorter than the drive pulse GA generated by the pulse generator 8, whlch will be referred to below as the first drive pulse. The strobe input signal is active low; the second drive pulse output by the strobe circuit 20 is active high. The pulse replacing circuit 22 comprises a NOR gate 24 and an OR gate 26. The NOR gate 24 receives the historical dot signals from the Q2 and Q3 terminals of the latch 6, and generates a replace signal that is active (high) when Q2 and Q3 are both inactive (low). The OR gate 26 receives this replace signal from the NOR gate 24 and the second drive pulse from the strobe circuit 20 as inputs, and generates an output that is active when either of these inputs is active. The output of the OR gate 26 will also be referred to as the second drive pulse. The effect of the OR gate 26 is to extend the active duration of the second drive pulse by locking the second drive pulse in the active state whenever the replace signal is active. The operation of this first embodiment of the invention is illustrated in Fig. 8. Clock, data, and latch signals are input as in the prior art. The first drive pulse GA and the masking pulses GB and GC are also as in the prior art. The strobe input is timed to start simultaneously with the first drive pulse GA. When Q2 and Q3 are both inactive ( the L-L-H pattern), the replace signal generated by the NOR gate 24 becomes active, holding the second drive pulse in the high state. The circuit then produces a drive signal comprising a single pulse equal in duration to the first drive pulse GA. When either Q2 or Q3 is active ( the H-L-H, L-H-H, and H-H-H patterns), the replace signal is inactive, so the second drive pulse produced by the strobe circuit 20 passes unaltered through the OR gate 26. Since the drive signal can be active only when all inputs to the AND gate 18 are active, and since the second drive pulse is shorter than the first drive pulse, the duration of the drive signal is now limited to the duration of the second drive pulse, i.e. to the low duration of the strobe signal. In addition, parts of the drive signal are masked by the masking pulses GB and GC as in the prior art. The embodiment of the invention in Fig. 7 thus usually generates the drive signal by gating the second drive pulse (the inverted strobe input) by the dot printing signal (Q1), and masking intervals of the second drive pulse defined by the masking pulses (GB and GC) when the corresponding historical dot signals (Q3 and Q2) are active. When the historical dot signals (Q3 and Q2) are both inactive, however, the pulse replacing circuit 22 holds the second drive pulse high, allowing the first drive pulse to replace the second drive pulse and extending the active duration of the drive signal. Figs. 9 to 12 illustrate simulated operation of this historical control circuit for two cases. The first case consists of repetitions of the L-H-L-L-H pattern. Fig. 9 illustrates simultaneous printing of this pattern by all dots in a line, showing an interval of eight lines. Fig. 10 illustrates the resulting temperature variations of the heating elements over an interval of sixteen lines, showing temperature on the vertical axis and time on the horizontal axis. Regardless of whether a printed dot is preceded by one or two non-printed dots, the maximum temperature reached is substantially 270 °C, resulting in dots of substantially uniform darkness. Figs. 11 and 12 illustrate a similar simulation of repetitions of the L-L-L-L-H pattern. Although each printed dot is now preceded by four non-printed dots, the maximum temperature is again substantially 270 °C. The preceding circuit provides refined historical control by delaying cutoff of the drive signal when the two preceding dots were not printed. Historical control can also be improved by extension to a larger number of preceding dots: for example, to three preceding dots instead of two, as described next. Referring to Fig. 13, with three preceding dots there are eight possible historical patterns. The levels and point values of these patterns are defined in the same way as in Fig. 4. A particular problem which the control circuit must overcome is that the L-L-L-H pattern on level one has the same point value (1,0) as the H-L-L-H pattern on level two. Fig. 14 illustrates a circuit, which is not part of the invention, that controls drive current according to three historical dots. The resistive heating element 2 and the driver circuit 4 are identical to the corresponding elements in the Figs. 6 and 8. The latch 28 is similar to the latch 6 in Figs. 6 and 8 but has an additional Q4 terminal for output of a third historical dot signal, indicating whether the third dot preceding the present dot was or was not printed. The pulse generator 30 is similar to the pulse generator 8 in Figs. 6 and 8 but has an additional terminal GD for output of a third masking pulse. The logic circuit 32 is similar to the logic circuit 10 in Fig. 8, but is interconnected differently to other circuit elements and comprises an additional NAND gate 34. The NAND gate 34 receives the masking pulse from the GD terminal of the pulse generator 30 and the historical dot signal from the Q2 terminal of the latch 28. The NAND gate 14 receives the masking pulse from the GC terminal of the pulse generator 30 and the historical dot signal from the Q3 terminal of the latch 28. The NAND gate 16 receives the masking pulse from the GB terminal of the pulse generator 30 and the historical dot signal from the Q4 terminal of the latch 28. The AND gate 18 receives the drive pulse from the GA terminal of the pulse generator 30, the dot printing signal from the Ql terminal of the latch 28, and the outputs of the NAND gates 14, 16, and 34. Fig. 15 illustrates the operation of this historical control circuit of Fig. 14. The drive pulse GA is timed to start just after the latch signal. The masking pulse GD starts together with the drive pulse GA, and is consecutively followed by the masking pulses GC and GB. In the L-L-L-H pattern, all three masking pulses are disabled by the NAND gates 14, 16, and 34, so the drive signal comprises a single pulse having the same duration as the drive pulse GA. In the H-L-L-H pattern the NAND gate 16 enables the masking pulse from the GB terminal, thus masking an intermediate interval of the drive signal so that the drive signal is divided into two separate pulses. As was shown in Fig. 1, the most intense heating occurs at the beginning of a pulse. The drive signal for the H-L-L-H pattern includes two such periods of intense heating, so although it feeds less total current than the drive signal for the L-L-L-H pattern, this current is able to produce substantially the same total amount of heat. This feature overcomes the problem noted in Fig. 13 of patterns with identical point values occurring on different levels. From Figs. 13 and 15 it can also be seen that when patterns on the same level have different point values, for patterns with lower point values the drive signal is generally divided into more separate pulses, thus generating more heat. Consider, for example, the three patterns on level two: the drive signals for H-L-L-H and L-H-L-H, which have point values of 1,0 and 1,5, both comprise two separate pulses; the drive signal for L-L-H-H, which has a point value of 2,0, comprises only one pulse. Accordingly, although all three patterns generate the same total current, the L-L-H-H pattern produces less heat than the other two patterns. A similar condition obtains on level three. The drive signals for H-H-L-H and H-L-H-H, which have point values of 2,5, both comprise two separate pulses. The drive signal for L-H-H-H, which has a point value of 3,O, comprises only one pulse. As on level two, the pattern with the highest point value generates less heat than the other two patterns. The concept can be applied to larger numbers of historical dots. Fig. 16 shows the sixteen patterns of four historical dots and lists their levels and point values. In this case the L-L-L-L-H pattern on level one has the same point value (1,0) as the H-L-L-L-H and L-H-L-L-H patterns on level two, and the L-L-L-H-H pattern on level two has the same point value (2,0) as the H-H-L-L-H, H-L-H-L-H, and H-L-L-H-H patterns on level three. Fig. 17 shows another circuit, which is not part of the invention, that controls drive current according to four historical dots. The resistive heating element 2 and the driver circuit 4 are identical to the corresponding elements in the Fig. 14. The latch 36 is similar to the latch 28 in Fig. 14 but has an additional Q5 terminal for output of a fourth historical dot signal, indicating whether the fourth dot preceding the present dot was or was not printed. The pulse generator 38 is similar to the pulse generator 30 in Fig. 14 but has an additional terminal GE for output of a fourth masking pulse. The logic circuit 40 is similar to the logic circuit 32 in Fig. 14, but comprises an additional NAND gate 42 that receives the masking pulse from the GE terminal of the pulse generator 38 and the historical dot signal from the Q2 terminal of the latch 28. The NAND gates 34, 14 and 16 respectively input the GD, GC, and GB masking pulses from the pulse generator 38 and the Q3, Q4, and Q5 historical dot signals from the latch 36. Fig. 18 illustrates the operation of this historical control circuit. The drive pulse GA is timed to start just after the latch signal. The masking pulse GE starts together with the drive pulse GA, and is consecutively followed by the masking pulses GD, GC, and GB. In the L-L-L-L-H pattern on level one, all four masking pulses are disabled by the NAND gates 14, 16, 34, and 42, so the drive signal comprises a single pulse having the same duration as the drive pulse GA. In the H-L-L-L-H and L-H-L-L-H patterns on level two, which have the same point value, the drive signal is divided into two separate pulses, providing substantially the same amount of heat as for the L-L-L-L-H pattern but with less total current. Similarly, the drive signal for the L-L-L-H-H pattern on level two comprises a single pulse. The drive signals for the H-H-L-L-H, H-L-H-L-H, and H-L-L-H-H patterns on level three, which have the same point value, deliver less total current but divide the current into two or three pulses, thus driving the resistive heating element 2 more effectively. Once again, patterns on different levels that have the same point values produce substantially equal amounts of heat. Among patterns on the same level, this historical control circuit also tends to produce less heat for patterns with higher point values. On level two, for example, the least heat is produced (in a single pulse) by the L-L-L-H-H pattern, which has the highest point value of 2,0. On level three, the least heat is produced (again in a single pulse) by the L-L-H-H-H pattern, which has the highest point value of 3.0. On level four, the least heat is produced (yet again in a single pulse) by the L-H-H-H-H pattern, which has the highest point value of 4,0. Referring to Fig. 19, historical control according to a further embodiment is made by adding the strobe circuit and the pulse replacing circuit of the Fig. 7 to the historical control circuit of Fig. 18. The resistive heating element 2, the driver circuit 4, the latch 36, the pulse generator 38, and the logic circuit 40 in Fig. 19 are identical to those in Fig. 18, except that the AND gate 18 now has six inputs instead of five. The strobe circuit 20 and the pulse replacing circuit 22 in Fig. 19 are identical to those in Fig. 7 except that the NOR gate 24 has three inputs, connected to the Q2, Q3, and Q4 terminals of the latch 36. The output of the OR gate 26 is the sixth input to the AND gate 18. Operation of this historical is entirely analogous to the operation of the historical control circuits in Figs. 7 and 18, so a detailed description will be omitted. The historical control circuit in Fig. 19 replaces the second drive pulse generated by the strobe circuit 20 with the longer first drive pulse from the GA terminal when the three preceding dots were not printed, i.e. when Q2, Q3, and Q4 are all inactive. This is not a restriction, however; by modifying the number of inputs to the NOR gate 24 it is possible to make a pulse replacement depend on all four preceding dots not being printed, or on only the two most recent dots not being printed. The historical control schemes, which are not part of the invention, illustrated in Figs. 14 to 18 can be modified by masking or unmasking specific intervals for specific patterns. Examples will be shown in Figs. 20 to 25. Fig. 20 illustrates a non-inventive circuit which controls drive current according to three historical dots. The resistive heating element 2, the driver circuit 4, the latch 28, the pulse generator 30, and the logic circuit 32 are identical to the corresponding elements in Fig. 14 and are interconnected in the same way except that the NAND gate 16 is coupled to the latch 28 through an unmasking circuit 44. The unmasking circuit 44 comprises a NOR gate 46, an inverter 48, and an AND gate 50. The NOR gate 46 is coupled to the Q2 and Q3 terminals of the latch 28 and generates a signal that is inactive when either the Q2 or Q3 historical dot signal is active. The inverter 48 inverts this signal and feeds it to the AND gate 50. The AND gate 50 also receives the Q4 historical dot signal from the latch 28. The output of the AND gate 50 is fed to the NAND gate 16. The function of the unmasking circuit 44 is to disable the Q4 historical dot signal when the Q2 and Q3 historical dot signals are both inactive. Referring to Fig. 21, this circuit operates like Fig. 15 except in the H-L-L-H pattern. In that pattern, since the Q2 and Q3 historical dot signals are both inactive, the output of the unmasking circuit 44 is inactive, disabling the GB masking pulse. The interval indicated by the dotted line, which was masked in Fig. 15, is therefore unmasked. The drive signal for the H-L-L-H pattern is identical to the drive signal for the L-L-L-H pattern, which is desirable since both patterns have the same point value in Fig. 13. Fig. 22 illustrates another circuit, which is not part of the invention, that is identical to Fig. 20 except that the unmasking circuit 44 has been replaced by a mask augmenting circuit 52. The mask augmenting circuit 52 comprises an inverter 54, an AND gate 56, and an OR gate 58. The inverter 54 inverts the Q3 historical dot signal. The AND gate 56 ANDs the output of the inverter 54 with the Q2 historical dot signal. The output of the AND gate 56 and the Q4 historical dot signal are sent to the OR gate 58, and the output of the OR gate 58 is sent to the NAND gate 16. The function of the mask augmenting circuit 52 is to enable the GB masking pulse not only when the Q4 historical dot signal is active, but also when the Q2 historical dot signal is active and the Q3 and Q4 historical dot signals are inactive. Referring to Fig. 23, this circuit operates like Fig. 15 except in the L-L-H-H pattern. In that pattern, since the Q2 historical dot signal is active and the Q3 and Q4 historical dot signals are inactive, the output of the mask augmenting circuit 52 is active, enabling the GB masking pulse. The interval indicated by the dotted line, which was not masked in Fig. 15, is now masked, reducing the heat produced for the L-L-H-H pattern. This is desirable because the L-L-H-H pattern has the highest point value on level two in Fig. 13. Fig. 24 illustrates another circuit, not part of the invention, which controls drive current according to four historical dots. The resistive heating element 2, the driver circuit 4, the latch 36, the pulse generator 38, and the logic circuit 40 are identical to the corresponding elements in Fig. 17 and are inter-connected in the same way except that the NAND gate 16 is coupled to the latch 36 through a mask augmenting circuit 60. The mask augmenting circuit 60 comprises a pair of inverters 62 and 64, a three-input AND gate 66, and an OR gate 68. The inverters 62 and 64 invert the Q3 and Q4 historical dot signals. The AND gate 66 ANDs the outputs of the inverters 62 and 64 with the Q2 historical dot signal. The output of the AND gate 66 and the Q5 historical dot signal are sent to the OR gate 68, and the output of the OR gate 68 is sent to the NAND gate 16. The function of the mask augmenting circuit 60 is to enable the GB masking pulse not only when the Q5 historical dot signal is active, but also when the Q2 historical dot signal is active and the Q3, Q4, and Q5 historical dot signals are inactive. Referring to Fig. 25, another non-inventive circuit operates exactly like Fig. 17 except in the L-L-L-H-H pattern. In that pattern, since the Q2 historical dot signal is active while Q3, Q4, and Q5 are inactive, the output of the mask augmenting circuit 60 is active, enabling the GB masking pulse. The interval indicated by the dotted line, which was not masked in Fig. 18, is now masked, reducing the heat produced for the L-L-L-H-H pattern. This is desirable because the L-L-L-H-H pattern has the highest point value on level two in Fig. 16.

Claims: An historical control circuit for a thermal line printer, comprising: a resistive heating element (2); a driver means (4) coupled to feed current to the resistive heating element (2) responsive to a drive signal; latch means (6) for generating a dot printing signal (Q1) and at least two historical dot signals (Q2, Q3), said signals indicating printing of a dot by the resistive heating element (2) for at least three consecutive line positions; pulse generating means (8) for generating a first drive pulse (GA) and at least two masking pulses (GB, GC, GD, GE) representing time intervals within the first drive pulse (GA); strobe means (20) for generating a second drive pulse, shorter than the first drive pulse (GA); logic means (10) coupled to gate the second drive pulse by the dot printing signal (Q1) and to mask intervals of the second drive pulse defined by the masking pulses when corresponding historical dot signals (Q2, Q3) are active, thus generating the drive signal, pulse replacing means (22) coupled to replace the second shorter drive pulse with the first drive pulse (GA) when a predetermined number of most recent historical dot signals (Q2, Q3) are all inactive. The circuit of Claim 1, wherein the latch means (6) generates two or four historical dot signals (Q2, Q3, Q4, Q5). The circuit of Claim 1 or 2, wherein the predetermined number is two or three. The circuit of any of Claims 1 to 3, wherein the logic means (10) comprises: at least two first gate means (14, 16; 34, 42) for gating the masking pulses (GB, GC, GD, GE) with the historical dot signals (Q2, Q3); and second gate means (18) for receiving as inputs the dot printing signal (Q1), the first drive pulse (GA), the second drive pulse, and outputs of the first gate means (14, 16; 34, 42), whereby the drive signal is generated when the inputs are all active. The circuit of Claim 4, wherein the first gate means are NAND gates (14, 16; 34, 42) and the second gate means is an AND gate (18). The circuit of any of Claims 1 to 5, wherein the pulse replacing means (22) comprises: third gate means (24) coupled to receive the predetermined number of most recent historical dot signals (Q2, Q3) and generate a replace signal that is active when the predetermined number of most recent historical dot signals are all inactive; and fourth gate means (26) coupled to make the second drive pulse active whenever the replace signal is active. The circuit of Claim 6, wherein the third gate means is a NOR gate (24) and the fourth gate means is an OR gate (26).

Inventors: ENDO TAKAFUMI, ENDO, TAKAFUMI, ENDO, TAKAFUMI, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1992
Main classification: B41J2
IPC codes: H04N1, B41J2