Decision-directed digital phase locked loop

Abstract: A decision-directed phase-locked loop for not synchronizing with opposite phases where the proper data of a PRS channel reproduced signal do not exist. The loop comprises a digital loop filter (20), a ternary level predicting portion (40), a phase modification signal generating portion (70) and an instantaneous phase detecting portion (10). The phase value of a future data existing point is first obtained on the basis of the phase value of the current data existing point in a reproduced signal output from the digital loop filter (20). The ternary level predicting portion (70) predicts future data of the reproduced signal based on the phase value of the future data existing point and on future sampled values of the reproduced signal. Given the predicted future data, the phase modification signal generating portion (70) checks to see if the current zero cross point of the reproduced signal is a data existing point. If the current zero cross point is found to be a data existing point, the digital loop filter (20) modifies its output phase value using the instantaneous phase value supplied by the instantaneous phase detecting portion (10).

Description: Field of the Invention: The present invention relates to a phase-locked loop circuit in accordance with the precharacterizing part of claim 1. Such a phase-locked loop circuit is known from US-A-490 6 941. Description of the Prior Art: Fig. 29 is a view of a typical reproduced signal from a partial response channel (PRS) (1, -1) for magnetic recording; Fig. 30 is a view of a typical reproduced signal from a PRS (1, 0, -1) channel for magnetic recording; Fig. 31 is a view of a typical eye pattern of the reproduces signal from the PRS (1, -1) channel; and Fig. 32 is a view of a typical eye pattern of the reproduced signal from the PRS (1, 0, -1) channel. In Figs. 29 and 30, each cross (+) symbol indicates a point where data, i.e., a zero-degree phase. On the PRS (1, 0, -1) and PRS (1, -1) channels for magnetic recording, data exist in zero-degree phases as a ternary level (1,0 or -1) each. Where the channel characteristic is properly equalized, signal waveform values converge on one of the three level (1, 0 or -1) in a zero-degree phase. Thus the optimum way to detect timing information from this waveform is to detect the phase of zero cross points. However, as evident from Figs. 29 through 32, zero cross points exist near phases other than the zero-degree phase (i.e., between zero-degree phases) on the PRS (1, 0, -1) and PRS (1, -1) channels. Take, for example, a clock reproduction circuit such as the one in Fig. 33. The circuit of Fig. 33 comprises a voltage comparator 401 that compares an input signal with a reference voltage, a bidirectional monostable multivibrator circuit 402 located on the output side of the comparator 401, and a phase-locked loop (PLL) circuit 403 of known construction which, located on the output side of the circuit 402, includes a phase comparator 405, a loop filter 406 and a VCO 407. With the clock reproduction circuit of Fig. 33, assume that an attempt is made to compare an input signal with the reference voltage to detect a zero cross phase from the comparison and to input the resulting phase to the PLL circuit for phase synchronization. In that case, as shown in Fig. 34, the monostable multivibrator circuit 402 outputs pulses incorrectly at 180-degree phases. As a result, phase synchronization is disturbed by the zero cross phase information from opposite phases, or the attempt to establish phase synchronization fails in trying to synchronize with negative phases upon the start of the synchronizing operation. According to US-A-4 906 941 from which the precharacterizing part of claim 1 is derived a digital phase locked loop circuit samples the reproduced analogue signal of a digital signal at a sampling frequency larger than the bit rate of the digital signal, and arithmetically operates by using data at a plurality of successive sampling points, an average phase of the reproduced signal in the range from a point where the reproduces signal crosses a reference level to a predetermined sampling point, and makes the phase locked loop control of the reproduced signal by using the operated average phase. This known digital phase locked loop circuit is operable at the sampling frequency twice or more the frequency determined by the delay time of the phase locked loop. Therefore it is suited for high speed digital magnetic recording/ reproducing apparatuses such as digital VTRs (video tape recorders). EP-A-316 459 discloses an apparatus and a method for fast acquisition of the sample timing phase in systems using partial response signalling. Thereby the signal at the output of a receive filter is sampled at the signalling rate for further processing by a Viterbi decoder. In the receiver, a timing recovering scheme adjusts the phase of the sampling clock so that the received signal is sampled at appropriate instants of time. For fast initial acquisition of the timing phase, a preamble receiving the user data is transmitted and a special timing procedure is employed. SUMMARY OF THE INVENTION: It is an object of the present invention to provide a phase-locked loop circuit for preventing the synchronization with opposite phases where data of a reproduces signal from a PRS channel do not exist. In carrying out the invention and according to one aspect thereof, there is provided a decision-directed digital phase-locked loop circuit comprising: (a) instantaneous phase detecting means for obtaining the instantaneous phase value of a digital sample value relative to a zero cross point of a reproduced signal of a partial response channel based on a plurality of sampled values of said reproduced signal; (b) a digital loop filter for cyclically calculating and outputting a phase value of a sample point of said reproduced signal and modifying said calculation in response to an instantaneous phase digital value obtained by said instantaneous phase detecting means; characterized by (c) phase value predicting means for obtaining the phase value of a future sample point based on the phase value, output by said digital loop filter, at the current sample point of said reproduced signal; (d) data predicting means for predicting future data of said reproduced signal based on the phase value of said future sample point obtained by said phase value predicting means as well as on future sampled values of a predetermined pattern of said reproduced signal; and (e) phase modification control means for determining, based on the future data predicted by said data predicting means, whether the current zero cross point of said reproduced signal is a point where valid data exist, and for allowing said digital loop filter to modify the output phase value thereof using said instantaneous phase value if said current zero cross point is found to be a point where valid data exist. (claim 1) Depending claims 2 to 7 are respectively specifying further developments thereof. In operation, the phase value of a future sample point is first obtained on the basis of the phase value of the current sample point in the reproduced signal output from the digital loop filter. Future data of the reproduced signal are predicted based on the phase value of the future sample point and on future sampled values of the reproduced signal. Given the predicted future data, a check is made to see if the current zero cross point of the reproduced signal is a sample point where valid data exist. If the current zero cross point is found to be a sample point where valid data exist, the digital loop filter modifies its output phase value using the instantaneous phase value of the zero cross point. This prevents phase synchronization in opposite phases where no valid data exist and permits synchronism only with phases where valid data exist. These and other objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a block diagram of a phase-locked loop circuit practiced as one preferred embodiment of the invention; Fig. 2 is a block diagram of a digital magnetic disc recording/reproducing apparatus to which the invention is illustratively applied; Fig. 3 is a block diagram showing a typical construction of the data detection circuit 205 in Fig. 2; Fig. 4 is a view of a typical isolated waveform on the PRS (1, 0, -1) channel after equalization; Fig. 5 is a view showing a typical spectrum of the isolated waveform on the PRS (1, 0, -1) channel after equalization; Fig. 6 is a view describing some aspects of the operating principles of the instantaneous phase detecting portion 10 in Fig. 1; Fig. 7 is a partial view-showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 8 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 9 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 10 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 11 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 12 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 13 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 14 is another partial view showing typical contents of the ROM table 12 in the instantaneous phase detecting portion 10 of Fig. 1; Fig. 15 is a view depicting the principles of computations for the ternary level-predicting portion 40 of Fig. 1 to predict future data; Fig. 16 is a view showing ternary level prediction determining rules in effect when both sampled values S k+2 and S k+3 are greater than a threshold value +A th ; Fig. 17 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 falls between the threshold value -A th and a threshold value +A th , with the sampled value S k+3 greater than the threshold value +A th ; Fig. 18 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is greater than the threshold value +A th , with the sampled value S k+3 falling between the threshold values -A th and +A th ; Fig. 19 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 falls between the threshold values -A th and +A th and the sampled value S k+3 falls also therebetween; Fig. 20 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is smaller than the threshold value -A th , with the sampled value S k+3 falling between the threshold values -A th and +A th ; Fig. 21 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 falls between the threshold values -A th and +A th , with the sampled value S k+3 smaller than the threshold value -A th ; Fig. 22 is a view showing ternary level prediction determining rules in effect when the sampled values S k+2 and S k+3 are both smaller than the threshold value -A th ; Fig. 23 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is smaller than the threshold value -A th and the sampled value S k+3 greater than the threshold value +A th ; Fig. 24 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is greater than the threshold value +A th and the sampled value S k+3 smaller than the threshold value -A th ; Fig. 25 is a view showing a typical sector construction of a magnetic disc as well as a repetitive pattern obtained from the preamble zone of each sector; Fig. 26 is a view of waveforms representing signals output by various parts of the embodiment of Fig. 1 as it operates; Fig. 27 is a view of waveforms representing signals output by various parts of the embodiment of Fig. 1 in synchronism establishing mode; Fig. 28 is a view of waveforms representing signals output by various parts of the embodiment of Fig. 1 in decision-directed processing mode; Fig. 29 is a view of a typical waveform representing a reproduced signal from the PRS (1, -1) channel; Fig. 30 is a view of a typical waveform representing a reproduced signal from the PRS (1, 0, -1) channel; Fig. 31 is a view of a typical eye pattern waveform representing a reproduced signal from the PRS (1, -1) channel; Fig. 32 is a view of a typical eye pattern waveform representing a reproduced signal from the PRS (1, 0, -1) channel; Fig. 33 is a block diagram of a typical prior art clock reproduction circuit; and Fig. 34 is a view of waveforms representing signals output by various parts of the prior art clock reproduction circuit of Fig. 33. DESCRIPTION OF THE PREFERRED EMBODIMENT: Fig. 1 is a block diagram of a phase-locked loop circuit practiced as one preferred embodiment of the invention. Preparatory to describing the embodiment, a digital magnetic disc recording/reproducing apparatus to which the invention typically applies will be explained. Fig. 2 is a block diagram of a digital magnetic disc recording/reproducing apparatus to which the invention applies, the diagram emphasizing the flow of data throughout the apparatus. In Fig. 2, a host computer 100 records data to a hard disk drive (HDD) subsystem 200 as follows: The host computer 100 first sends data through a bus interface to a controller 201 in the HDD subsystem 200. The controller 201 puts the received data into a format suitable for recording on a magnetic disc. The controller 201 then modulates the formatted data in a way compatible with a magnetic recording/reproduction channel and sends the data to a recording amplifier 202. The recording amplifier 202 causes recording currents to flow to the magnetic recording head inside a head disc assembly 203 for recording the data. The head disc assembly 203 is a mechanical block comprising a magnetic disc on which to record data, recording and reproduction heads, a head positioning mechanism, and a spindle motor. Data are reproduced as follows: In the head disc assembly 203, recorded magnetic patterns are read from the magnetic disc by the magnetic reproduction head. The data thus retrieved are amplified by a reproduction amplifier 204 as a reproduced signal. The reproduced signal is converted to digital data by a data detection circuit 205. The controller 201 subjects the digital data to channel demodulation and unformatting processes before sending the data to the host computer 100 through the bus interface. The present invention is applicable in particular to the data detection circuit 205 in the magnetic recording/reproducing apparatus of Fig. 2. The primary objective for the digital magnetic recording/reproducing apparatus to utilize the PRS (1, 0, -1) channel is this: On the magnetic recording/reproduction channel which is a band limiting channel, band utilization is maximized so that data are recorded and reproduced as fast as possible in the same bandwidth. (From another point of view, this means enhancement of the linear recording density in the longitudinal direction on the recording medium.) The PRS (1, 0, -1) channel makes positive use of inter-symbol interference (i.e., interference between isolated reproduced waveforms) that occurs on a band limiting channel. Suppose that isolated waveforms (i.e., reproduced signals of isolated magnetic inversion from recording medium) are equalized into the form shown in Fig. 4. In this case, the waveform passes points 0, ..., 0, 0, 1, 1, 0, 0, ..., 0 at channel bit intervals of T ch . The frequency spectrum of this waveform is as depicted in Fig.5, with the zero point occurring at a frequency of 1/T ch . Clock information is detected from the observation of random data recording and reproducing waveforms generally by one of two major methods: (1) by detecting peak points-(for magnetic disc units that operate on peak detection principles); or (2) by detecting zero cross points. Method (1) above is not usable with the PRS (1, 0, -1) channel because peaks are not acute enough, as shown in the eye pattern of Fig. 32. Where channel equalization is adequate, zero cross points neatly occur in zero-degree phases. Unfortunately, zero cross points can also occur at 180-degree phases. Not all zero cross points may be used for clock phase detection. The data detection circuit 205, to which the invention applies, illustratively comprises as shown in Fig. 3 an analog AGC amplifier 310 that outputs a signal at a constant envelope level on receiving the output of the reproduction amplifier 204, an A/D converter 311 that converts the output signal of the amplifier 310 to a digital signal, a transversal type equalizer (FIR filter) 312 that equalizes the output signal of the converter 311, a clock reproduction PLL and data detector 313 that detects zero-degree phase clock pulses from the output of the equalizer 312 to output zero-degree phase data according to the invention, a sampled value interpolator 314 that interpolates zero-degree phase sampled values on receiving the output of the equalizer 312 and the output of the detector 313, and a Viterbi decoder 315 that subjects the output of the interpolator 314 to Viterbi decoding. In the magnetic disc apparatus, the reproduction level from the magnetic head varies depending on the present radius of the track to be reproduced. Where a number of disc surfaces and magnetic heads are varied in combination, such combinations change the reproduction level. However, for the data detection circuit 205 to provide its predetermined performance requires that the envelope level of the reproduced signal from the channel be substantially constant. This requirement must be met for the following reasons: (1) Within the data detection circuit 205, data are represented by the fixed-point representation system to enable high-speed digital signal processing. In order for each internal word length to be utilized effectively, the level fluctuation should preferably be minimal. (2) Ternary data detection is carried out through level comparison for decision-directed processing, as will be described later. It follows that any fluctuation in the signal level is undesirable. It is for these reasons that the analog AGC amplifier 310 is provided to keep substantially constant the envelope level of the reproduced signal from the channel. The A/D converter 311 samples the analog reproduced signal from the AGC amplifier 310 at a sampling frequency of f s that is a constant multiple of the channel bit rate. The sampled signal is quantized into a predetermined signal word length. Because high-speed operation is required, the converter 311 is typically implemented using a flash A/D converter. In this embodiment, the sampling frequency f s is twice the channel bit rate, which is the simplest possible arrangement. The equalizer 312 controls the inter-symbol interference stemming from the band limiting characteristic and other aspects of the magnetic recording channel so as to fit the channel characteristic correctly to the PRS (1, 0, -1) channel. For example, the equalizer 312 is implemented using a transversal type linear equalizer composed of digital signal processing circuits. The zero-degree phase sampled value interpolator 314 calculates sampled values at zero-degree phase points where data exist based on the output phase from the clock reproduction PLL and data detector 313 according to the invention. The Viterbi decoder 315 outputs a correct data sequence in accordance with the sequence of the sampled values. How the preferred embodiment of the invention works will now be described with reference to Fig. 1. The description of the workings will start at an instantaneous phase detecting portion 10. The detecting portion 10 detects instantaneous phases on the same principles as those disclosed in Japanese Patent Laid-Open No. 59-92410. As its input values, the detecting portion 10 receives two sampled values S k+1 and Sk. The sampled value S k+1 is a value given at a time t = (k + 1)T s , i.e., when a sampled value of S k+3 of a reproduced signal from the PRS channel is delayed two sampling periods by pipeline registers 2 and 4; the sampled value Sk is given at time t = kTch, i.e., when the sampled value S k+3 of the PRS channel reproduced signal is delayed three sampling periods by pipeline registers 2, 4 and 6. A ROM table 12 of the instantaneous phase detecting portion 10 outputs an instantaneous phase of A P k+1 based on the two continuous signal sampled values S k+1 and Sk sampled at a fixed clock rate in asynchronism with the input signal data. The instantaneous phase Δ P k+1 is a time period ranging from the point in time t = (k + 1)T s at which the signal sampled value S K+1 exists back to the signal waveform zero cross point (zero-degree phase candidate) within the (k + 1)th time slit. The values are in units of quantized phases. The instantaneous phase A P k+1 represents the distance between the zero-degree phase (having a phase value of zero) and the time (k + 1)Ts; it also stands for the phase value of the point in time t = (k + 1)T s . With this embodiment, a phase of 360 degrees corresponds to a digital value of 2 NPLL . The time T s for a single time slot corresponds to a phase of 180 degrees, or to 2 NPLL-1 if counted in units of quantized phases. The instantaneous phase Δ P k+1 is obtained from Expression (1) below on the assumption that the signal waveform may be linearly approximated between the two continuous signal sampled values S k+1 and S k (see Fig. 6): Δ P k+1 = 2 N PLL-1 S k+1 S k+1 -S k where, 2 NPLL-1 is the quantized phase count for one sampling period. In the case of S k+1 = S k , the denominator can become 0. In fact, because no zero cross point occurs and because PLL phase update is not performed, there is no need to calculate Δ P k . The ROM table 12 receives as its address input the sampled values S K+1 and S k and outputs the instantaneous phase Δ P k+1 accordingly. Figs. 7 through 14 are views showing typical contents of the ROM table 12 in effect when input signals are four bits long each (i.e., data in twos complements are regarded as absolute binary addresses) and zero cross phase detected output data are four bits long as well (in absolute binary representation). The instantaneous phase is input to a loop filter (digital signal processing PLL) 20 as phase data Δ P k of, say, 4 NPLL bits. That is, with the embodiment of Fig. 1, the delay in the operation time or in the access time of the ROM table 12 is compensated in the following manner to permit high bit rate operations: First the instantaneous phase Δ P k+1 is obtained from the ROM table 12. Then one pipeline register 14 is inserted in the flow to produce a delay of one sampling period. The result is output as the phase data Δ P k . Although the embodiment of Fig. 1 acquires the instantaneous phase Δ P k+1 from the ROM table 12, the embodiment may alternatively execute Expression (1) using a subtracter and divider arrangement in order to find the phase. The digital loop filter 20 will now be described. The filter 20 is at least a primary phase synchronizing loop that updates the internal phase data P k based on the instantaneous phase data Δ P k so as to follow zero-degree phases. Phase modification is available in each time slot. If a correct zero cross point of a zero-degree phase does not exist in a given time slot ((k - 1)T < t < kT), no phase modification should be carried out. In that case, phase updating is performed according to Expressions (2) and (3) below using a phase modification control signal "modify_Pk" coming from a phase modification control signal generating portion 70. This embodiment utilizes a primary loop. The expressions are as follows: if (modify_Pk = 0), then no phase modification is made; (PLL running by itself) P k = P k-1 + 2 N PLL-1 else if (modify_Pk = 1), then phase modification is made; P k = P k-1 + 2 N PLL-1 + α (ΔP k -(P k-1 + 2 N PLL-1 )) The internal phase data are supplemented by 2 NPLL-1 when no phase modification is made according to Expression (2) above. This is done because, with no phase modification performed, the phase still needs to be rotated by 180 degrees due to the presence of one zero-degree phase for every two time slots on average. When phase modification is carried out according to Expression (3), the difference is obtained between the instantaneous input phase A P k and the PLL internal phase self-running value (P k-1 + 2 NPLL-1 ). The amount of phase modification is acquired by multiplying that difference by a modification coefficient of α. In Expressions (2) and (3), each phase data word length is NPLL bits, and add and subtract operations are the modulo arithmetic with 2 NPLL taken as modulus. As indicated by Expression (4) below, the instantaneous phase Δ P k takes on only a positive value: 0 ≤ ΔP k ≤ 2 N PLL-1 The PLL internal phase P k also takes on a positive value only, as indicated by Expression (5): 0 ≤ P k < 2 N PLL-1 The amount of phase modification α (Δ P k - (P k-1 + 2 NPLL-1 )) is twos complement data that may be either positive or negative. In the loop filter 20 of Fig. 1, the PLL internal phase P k is retained in a phase register 26 as data of, say, 4 NPLL bits. A constant generator 28 generates a constant of 2 NPLL-1 . An adder 27 is a modulo (2 NPLL ) adder that receives the output P k-1 of the phase register 26 and the output 2 NPLL-1 of the constant generator 28 so as to execute (P k-1 + 2 NPLL-1 ). A subtracter 21 calculates the difference between the input instantaneous phase Δ P k and the output (P k-1 + 2 NPLL-1 ) of the adder 27. The output of the subtracter 21 is supplied to one of two input terminals 22A of a switch 22. The other input terminal 22B is fed with the output of a constant generator 23. In this embodiment, the constant generator 23 generates 0. The switch 22 is operated in accordance with the phase modification control signal "modify_Pk." When the signal "modify_Pk" is 1, the switch 22 is operated to connect the terminal 22A; when the signal is 0, the switch 22 is operated to connect the terminal 22B. A modification coefficient generator 29 generates the modification coefficient α . With this embodiment, the modification coefficient α is set to 0.125. A multiplier 24 multiplies the output of the switch 22 by the modification coefficient α . The subtracter 21, switch 22 and multiplier 24 determine the amount of PLL internal phase modification. The amount of phase modification thus determined is added by an adder 25 to the PLL internal phase (P k-1 + 2 NPLL-1 ) for phase modification. A zero cross detecting portion 30 will now be described. The first requirement to be met for PLL internal phase modification is that a signal wave zero cross point must exist in a given time slot so that an instantaneous phase may be measured. The zero cross detecting portion 30 first receives continuous two signal samples S k+1 and S k from the pipeline registers 4 and 6, respectively. The two signal samples are compared by comparators 31 and 32 with the output of a constant generator 33. The compare operation yields the MSB's (sign bits) of the two signal samples S k+1 and Sk expressed in twos complement data. These MSB's are subjected to an exclusive-OR operation by an exclusive-OR gate 34 to check for the presence of a zero cross point. The result is output as a zero cross signal "zero_cross_k." To compensate for the effects of the delay due to the exclusive-OR gate 34, the embodiment of Fig. 1 first detects beforehand a signal "zero_cross - k+1" which occurs one time slot later. The detected signal is then delayed by a pipeline register 35 to provide the zero cross signal "zero_cross_k." The PRS (1, 0, -1) reproduced signal waveform results in zero cross points in zero-degree phases only when the ternary data sequence is ..., 1, 0, -1, ..., etc., or ..., -1, 0, 1, ..., etc. Thus it is unacceptable to obtain phase data from each and every zero cross point; new instantaneous phase data must be obtained selectively. This requires the so-called decision-directed processing. The processing involves having a ternary level predicting portion 40 carry out simple ternary level detection, the result of this presumptive data detection being used to detect the instantaneous phase selectively. Decision-directed processing requires three data items: a future data item d k+2 of one time slot later, the current data item d k of the current time slot, and a preceding data item d k-2 of one time slot earlier. However, it should be noted that prior to the update of the time slot k , the PLL knows only the phase P k-1 ; it does not know that zero-degree phase in the (k + 2)th slot which is needed to detect the future data d k+2 . This is the reason why P k+3 is necessary. The predicted value P p(k+3) in the future zero-degree phase is obtained from the PLL internal phase P k-1 using Expression (6) below: P p(k+3) ≈ P k-1 +4 (2 N PLL-1 ) = P k-1 where, the second term in Expression (6) is zero because the add operation is carried out with modulo (2 NPLL ), with the result that the expression is simplified as shown on the second line. That is, if the phase fluctuation of the input signal is small enough, the phase of four time slots later is predicted using Expression (6). In the embodiment of Fig. 1, the output P k-1 of the phase register 26 is supplied as the predicted value P p(k+3) of the future zero-degree phase to the ternary level predicting portion 40. Using the predicted phase P p(k+3) , the ternary level predicting portion 40 performs ternary level determination on the following principles for presumptive detection of the future data d k+3 : Suppose it is known by the PLL that a zero-degree phase exists in the (k + 3)th time slot. (In fact, regardless of the presence or absence of the zero-degree phase, data are detected in all time slots for selective processing (see Expression (11)) based on the valid signal to be described later.) On this assumption, two cases are conceivable: (A) If the input signal samples S k+2 and S k+3 at both ends of the current time slot exist on the same side of a threshold value, the input signal level S 0(k+3) at the zero-degree phase existing point, i.e., the data existing point also exists on the same side. (B) If one input signal sample S k+2 exists on one side of the threshold value and the other input signal sample S k+3 exists on the other side, primary linear interpolation is performed to calculate the signal waveform cross phase with respect to the threshold value in the current time slot (i.e., distance from t = (k + 3)T s back to the signal waveform cross point). The signal waveform cross phase is Δ P+ (k+3) if the threshold value is positive, or Δ P- (k+3) if the threshold value is negative. This phase value is compared with the predicted phase P p(k+3) (i.e., distance from the point in time t = (k + 3)T s back to the zero-degree phase predicted point in the current time slot). The result of the compare operation is used to determine on which side of the threshold value the signal S 0(k+3) of the zero-degree phase predicted point exists. The determination is based on a simple comparison of levels as indicated by Expression (7) below: if (+ A th ≤ S o(k+3) )then d k+3 = +1 elseif (- A th ≤ S o(k+3) <+A th )then d k+3 = 0 elseif( S o(k+3) < - A th )then d k+3 = - 1 The calculation of the signal waveform cross phase relying on primary linear interpolation utilizes Expressions (8) and (9) below. The calculation is based on the same principles as those of the instantaneous phase calculation described earlier. ΔP +(k+3) = 2 N PLL-1 S k+3 - A th S k+3 - S k+2 ΔP -(k+3) = 2 N PLL-1 S k+3 + A th S k+3 - S k+2 . where, A th is an absolute threshold value for ternary level comparison. The principles of the computations above are illustrated in Fig. 15. Fig. 16 is a view showing ternary level prediction determining rules in effect when both sampled values S k+2 and S k+3 are greater than a threshold value +A th . -Fig. 17 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 falls between the threshold value -A th and a threshold value +A th , with the sampled value S k+3 greater than the threshold value +A th . Fig. 18 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is greater than the threshold value +A th , with the sampled value S k+3 falling between the threshold values -A th and +A th . Fig. 19 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 falls between the threshold values -A th and +A th and the sampled value S k+3 falls also therebetween. Fig. 20 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is smaller than the threshold value -A th , with the sampled value S k+3 falling between the threshold values -A th and +A th . Fig. 21 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 falls between the threshold values -A th and +A th , with the sampled value S k+3 smaller than the threshold value -A th . Fig. 22 is a view showing ternary level prediction determining rules in effect when the sampled values S k+2 and S k+3 are both smaller than the threshold value -A th . Fig. 23 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is smaller than the threshold value -A th and the sampled value S k+3 greater than the threshold value +A th . Fig. 24 is a view showing ternary level prediction determining rules in effect when the sampled value S k+2 is greater than the threshold value +A th and the sampled value S k+3 smaller than the threshold value -A th . A valid signal generating portion 50 will now be described. The sampling rate of the input signal to the valid signal generating portion 50 is twice the channel bit rate. On average, one data item exists for two time slots. Although presumptive data detection is performed by the ternary level predicting portion 40 for all time slots, valid data are output only every two time slots on average. Thus it is necessary to generate and output a valid signal showing in which time slot valid data exist, i.e., in which time slot a zero-degree phase exists. The valid signal V k is generated according to the rules of Expression (10) below using the PLL internal phase P k : If (P k-1 > P k ), then data are valid (zero-degree phase present in slot); V k = 1 else if (P k-1 ≦ P k ), then data are not valid (zero-degree phase absent in slot); V k = 0 where, P k is the phase at the sampling time t = kT s (end time of the k-th time slot). The phase value at the zero-degree phase time is 0. Each time slot is divided in virtual terms into 2 NPLL-1 quantized phases. Over time, each quantized phase value is incremented with modulo (2 NPLL ). When N PLL = 4, the transition of the quantized phase in the k-th slot occurs as follows: 13, 14, 15, 0, 1, 2, 3, 4, 5 In this case, a zero-degree phase exists in the time slot. The phase value 13 of P k-1 is incremented to reach 0 (where zero-degree phase exists). Then the value is incremented further to reach P k = 5. Thus the relation P k-1 > P k holds. Conversely, in the case where no zero-degree phase exists in the time slot, the transition of the quantized phase occurs as follows: 5, 6, 7, 8, 9, 10, 11, 12, 13 In this case, each quantized phase value is simply incremented and the relation P k-1 > P k does not hold. The phase value 0 does not exist in the time slot, and the data detected in this slot are not valid. In the valid signal generating portion 50 of the embodiment in Fig. 1, a digital comparator compares the output P k of the adder 25 in the loop filter 20 with the output P k-1 of the phase register 26. The result is needed to execute the compare operation using Expression (10) above. A mode switching control signal generating portion 60 will now be described. The generating portion 60 generates a mode switching control signal for selecting either synchronism establishing mode or decision-directed processing mode. Decision-directed processing involves predicting future zero-degree phases on the assumption that the past phase data held by the PLL are correct (i.e., the PLL is correctly locked to the zero-degree phase). Thus if it is desired to synchronize in phase with a sequence of input signals, a certain degree of synchronism at the beginning of the signal sequence is essential for subsequent decision-directed processing algorithms to work properly. For the above reason, a preamble (a simple repetitive signal pattern portion for establishing synchronism) is attached to the beginning of the input signal sequence. With decision-directed processing not employed, all instantaneous phases are regarded as the zero-degree phase each to permit phase synchronization. The simple repetitive signal pattern for establishing synchronism is provided preferably by reproducing a signal recorded in the preamble zone of each magnetic disc sector. Fig. 25 is a view showing a typical sector construction of a magnetic disc as well as a repetitive pattern obtained from the preamble zone of each sector. In Fig. 25, a track 331 of the magnetic disc 330 is divided into a plurality of sectors 332. Each sector 332 contains a preamble zone 333, a data zone 334 and a gap 335. The preamble recorded in the zone 333 is a pattern repeated at intervals of 6T ch . Where the reproduced signal on the PRS (1, 0, -1) channel is detected for ternary data, the pattern is ..., 1, 0, -1, -1, 0, 1, 1, 0, - 1,-1, 0, 1, 1, ... where, every zero cross point has a zero-degree phase. In the case of decision-directed processing according to the invention, correct synchronization with the zero-degree phase is achieved. Phase synchronism based on the preamble scheme is accomplished in two modes: synchronism establishing mode and decision-directed processing mode. These modes are switched from one to the other. In synchronism establishing mode, the PLL internal phase is modified using the instantaneous phase data at every zero cross point without recourse to decision-directed processing. Upon elapse of a predetermined period of time from the beginning of the sector, the other mode is selected. It is assumed that the starting time at the beginning of the sector is known by suitable means separately provided in the magnetic disc unit. (For example, in a magnetic disc unit operating on the prior art sector servo principle, the servo circuit thereof furnishes a signal indicating the approximate position of the beginning of the sector.) Alternatively, decision-directed processing mode may be selected after a predetermined zero cross count is reached. The signal from the preamble zone is kept reproduced for some time even after decision-directed processing mode is selected. The PLL in the embodiment of Fig. 1 maintains synchronism even as it detects data and performs decision-directed processing given the preamble pattern. With the preamble zone terminated in the sector, phase synchronization based on decision-directed processing is maintained over the data zone in which the phase continues to the preamble pattern. A phase modification control signal generating portion 70 will now be described. The signal generating portion 70 comprises a combinational logic circuit or a ROM table arrangement that performs operations equivalent to those of the logic circuit. On receiving the detected zero cross output from the detecting portion 30 and the valid signal from the valid signal generating portion 50, the phase modification control signal generating portion 70 generates a phase modification control signal "modify_Pk." More specifically, the ternary data d k+3 detected by the ternary level predicting portion 40 are represented as a two-bit twos complement word. This word is delayed through a shift register made of 6 pipeline registers 41, 42, 43, 44, 45 and 46 to become data d k+3 , d k+2 , d k+1 , d k , d k-1 , d k-2 and d k-3 for input to the phase modification control signal generating portion 70. The signal generating portion 70 then generates the phase modification control signal "modify_Pk" based on the above data, on the detected zero cross output of the detecting portion 30, on the valid signal from the valid signal generating portion 50 and on the mode switching control signal from the signal generating portion 60. Care should be exercised to ensure causality for the valid signal. The phase control signal "modify_Pk" output by the phase modification control signal generating portion 70 controls PLL phase modification and affects the internal phase P k . Because the valid signal is generated by a comparator 51 (a combinational logic circuit with no data stored therein) that receives the internal phase P k as one of its inputs, feeding the output V k of the comparator 51 unchanged to the portion 70 would disturb causality and lead to an unpredictable state. To prevent this, the output V k is delayed by a D flip-flop circuit 52 yielding V k-1 . The output V k-1 of the D flip-flop circuit 52 is inverted by an inverter 53 providing V pk , a predicted value of V k . Where phase synchronism is correct, valid and invalid states are alternated from one time slot to another. Thus the above-described process of one-step linear prediction almost always provides the correct valid signal. The basic operations of decision-directed processing mode involve applying the instantaneous phase value A Pk obtained from a zero cross point to the phase modification of the PLL when the transition of the ternary data is predicted to occur in the order of -1, 0, +1, or in the order of +1, 0, -1. In practice, if a jitter-plagued signal is input, the result of presumptive detection of the ternary data may not be 0 in the time slot where a zero cross point exists. A discrepancy between the instantaneous phase and the result of four-step linear phase prediction for presumptive determination can be such that the two values may switch their places chronologically relative to each other. Thus under the rules for generating the phase modification control signal "modify_Pk," decision-directed processing mode is divided into three sub-modes as shown in Expressions (11) and (12) that follow. In Expression (12), AND stands for a logicaL multiply operation and OR for a logical add operation. if (Preamble = 1) then synchronism establishing mode is selected (phase modification at every zero-cross point); modify_Pk = Zero_cross_k else if (Preamble = 0) then decision-directed processing mode is selected; modify_Pk = (Zero_cross_k)AND(valid sequence) In decision-directed processing mode, the phase modification control signal "modify_Pk" = 1. The phase of the PLL, i.e., the loop filter 20 is modified in any one of the following cases: (1) The case where a zero cross point exists in the current k-th time slot, where the time slot is valid (i.e., zero-degree phase present), and where the transition of the ternary data sequence (d k-2 , d k , d k+2 ) is predicted to occur in the order of -1, 0, +1, or in the order of +1, 0, -1. (2) The case where a zero cross point exists in the current k-th time slot and where the above-mentioned transition occurs with the (k - 1)th time slot (i.e., the immediately preceding time slot) located in the middle. In this case, V k-1 is used as the valid signal. Alternatively, Vk may be inverted for use as the valid signal. (3) The case where a zero cross point exists in the current k-th time slot and where the above-mentioned transition occurs with the (k + 1)th time slot (i.e., the immediately following time slot) located in the middle. Although this case would require V k+1 as the valid signal, V k+1 is replaced by V k that is inverted for two-step linear prediction from V k-1 . The rules given by Expressions (11) and (12) are readily implemented using a combinational logic gate circuit, a PLD or a ROM table lookup arrangement. Thus the phase modification control signal generating portion 70 is practiced with ease by use of any of these means. In decision-directed processing mode, the signal generating portion 70 generates the phase modification control signal "modify_Pk" based on the valid signal v pk from one-step future prediction and on t-he data detected in the phase P p(k+3) from four-step future prediction. This means that the signal "modify_Pk" could be generated because of a prediction error. However, the probability of such error incidence is negligible. Even if the phase is modified so as to follow the instantaneous phase at incorrect zero cross points, the PLL internal phase is not much disturbed because the modification coefficient α is sufficiently small (about 0 < α ≦ 0.5 in general). In that case, the subsequent correct instantaneous phase is soon followed. Described below is how the embodiment of Fig. 1 works on the time base with reference to Figs. 26 through 28. Fig. 26 is a view of waveforms showing 512 samples of signals output by various parts of the embodiment. Each of the signals sampled in Fig. 26 has the following meaning: (a) Input signal S k This signal has a waveform produced by first having an A/D converter sample the output waveform of an electromagnetic conversion system made of a head mechanism and recording medium, and then by equalizing the sampled waveform through a digital equalizer to be compatible with the PRS (1, 0, -1) channel. The input signal S k is expressed in four-bit twos complement notation and is an integer that falls within a range of -8 ≦ S k ≦ 7. About 100 wave samples at the beginning correspond to the preamble zone. This is a repetitive pattern repeated at intervals of 6 T ch , with 12 samples making up one interval. The preamble zone is followed by the data zone. (b) Instantaneous phase Δ P k This signal is output by the instantaneous phase detecting portion 10. According to Expression (4), the signal is an integer that falls within a range of 0 ≦ Δ P k ≦ 8. In Fig. 26, the peak of each triangular pulse wave represents a sampled value (the same also holds for the other signals). (c) Zero cross signal "zero_cross_k" This signal is the output of the zero cross detecting portion 30. The signal takes a value of either 1 or 0. (d) Phase modification control signal "modify_Pk" This signal is the output of the phase modification control signal generating portion 70. The signal also takes a value of either 1 or 0. (e) Detected result of ternary level d k This signal is the detected result of the ternary level predicting portion 40 and is delayed by registers 41, 42 and 43. The signal is twos complement data that take one of three values: -1, _0 or +1. In Fig. 26, the value -1 is represented as -2. (f) Valid signal V k This signal is the output of the valid signal generating portion 50. A value of 1 (peak of a triangular pulse wave) stands for a valid state and a 0 for an invalid state. (g) PLL internal phase P k This signal is the modified phase value in effect at the time k. At that time, the value is input to the phase register 26 of the PLL, i.e., the loop filter 20. The overall workings of the embodiment of Fig. 1 will be first described with reference to Fig. 26. At the beginning of the input signal S k , the phase-locked loop circuit, i.e., the decision-directed DPLL in Fig. 1 operates in synchronism establishing mode up to the 50th sample in the preamble zone. Thereafter, the mode switching control signal generating portion 60 replaces synchronism establishing mode with decision-directed processing mode. How the embodiment works in decision-directed processing mode will now be described. Fig. 27 is a view showing enlarged waveforms of 30 samples taken from what is depicted in Fig. 26 with respect to the workings of the embodiment in synchronism establishing mode. In Fig. 27, the initial value of the PLL phase P k is P 0 = 8 at the time of k = 0. This is where the initial phase modification takes place. Until k = 8, P k takes on values of 8, 0, 8, 0, 8, 0, etc. That is, the PLL runs by itself. When k = 8, S 7 = 2 and S 8 = -1 in the input signal S k . With a zero cross point present, the signal "zero_cross_8" = 1. At the same time, the instantaneous phase detecting portion 10 calculates the instantaneous phase Δ P 8 and inputs the phase to the loop filter 20. In turn, the loop filter 20 modifies the internal phase from P 6 = 8 to P 8 = 7 according to Expression (3). No zero cross point exists at times of k = 9, 10, 11, 12 or 13, and thus no phase modification occurs. At the time of k = 14, a zero cross point is again present, and the instantaneous phase Δ P 14 = 3 is input to the loop filter 20 accordingly. This modifies the input phase to P 14 = 6. Because the modification coefficient is small (i.e., α = 0.125) in this example, internal phase modification occurs slowly. The phase modification is carried out at times of k = 8, 14, 20, 26, 32, 38, 44, 50, etc. Every time the phase modification is performed, the internal phase value P k of the DPLL is modified so as to approach the instantaneous phase value Δ P k . When k = 32, the two phase values become the same and synchronism is established. The synchronism establishing operation up to this point has been performed in synchronism establishing mode in which all instantaneous phase values are input. After this, the steady state of established synchronism continues from the time k = 33 to k = 50. As shown in Fig. 26, the predicted results of ternary levels remain regularly repetitive during this period, occurring as 0, +1, +1, 0, -1, -1, 0, etc. The data for decision-directed processing are also detected correctly. The valid signal V k also repeats the pattern of ..., 0, 1, ... per sample. The workings of the embodiment in decision-directed processing mode will now be described. After k = 50, the mode switching control signal generating portion 60 selects decision-directed processing mode. Since synchronism has now been established, the ternary level predicting portion 40 correctly performs presumptive data detection. As a result, all zero cross points between k = 50 and k = 100 entail the transition in the order of -1, 0, +1, or in the order of +1, 0, -1. The output signal "modify _Pk" of the phase modification control signal generating portion 70 coincides with the zero cross signal "zero_cross_k." What follows is a description of the decision-directed processing in the data zone. In the example of Fig. 26, the signal S k remains 0 between k = 100 and k = 111. Thus no zero cross point exists and the DPLL runs by itself. After k = 112, data are recorded. Phase modification is carried out while checks are being made to see if the current zero cross point is of zero-degree phase. Fig. 28 is a view of enlarged waveforms in effect between k = 100 and k = 150. In Fig. 28, a zero cross point exists at the time of k = 116. A look at the predicted ternary data d k indicates that d 114 = +1, d 116 = 0 and d 118 = -1. (The data starting from the valid signal V k up to an even-numbered point in time are valid; the data detected at an odd-numbered point in time have no meaning.) Thus the zero cross point has a zero-degree phase, and the instantaneous phase value Δ P 116 = 2 at that point is used for phase modification. At k = 120 where the next zero cross point exists, the sequence of the predicted ternary data is d k = -1, d k = 0, d k = 0; this means that the requirements for the zero-degree phase are not met. Thus "modify_P120" = 0 and no phase modification takes place. Likewise the requirements for the zero-degree phase are not met at k = 130 and k = 134, with no phase modification carried out. From the time of k = 240 onward, the signal waveform takes a pattern with a 4 T ch cycle in which zero cross points occur only in 180-degree phases. Although the zero cross signal "zero_cross_k" often takes the value 1, none of the requirements for decision-directed processing is met. Thus the signal "modify_Pk" = 0 and no phase modification is performed. Although the above-described embodiment applies to the setup with the PRS (1, 0, -1) channel, the embodiment is not limitative of the invention. The embodiment also applies to PRS (1, -1) channel applications. As described, in the decision-directed phase-locked loop embodying the invention, the phase value of a future data existing point is first obtained on the basis of the phase value of the current data existing point in the reproduced signal output from the digital loop filter. Future data of the reproduced signal are predicted based on the phase value of the future data existing point and on future sampled values of the reproduced signal. Given the predicted future data, a check is made to see if the current zero cross point of the reproduced signal is a data existing point. If the current zero cross point is found to be a data existing point, the digital loop filter modifies its output phase value using the instantaneous phase value of the zero cross point. This scheme prevents phase synchronization in opposite phases where data do not exist and permits synchronism only with phases where data exist. It follows that jitters do not increase in data-existing phases upon input of an opposite instantaneous phase to the phase-locked loop circuit being synchronized. As a secondary benefit, reproduced signal data may be detected. Because all functional blocks in the data detection including the phase-locked loop circuit can be implemented using digital circuits that operate in synchronism at a fixed clock rate, the data detection circuit, ECC decoder, controller and other related parts may be readily built in the same LSI. This makes the whole product smaller in size and less expensive to build, with its LSI design and testing procedures significantly simplified. With no externally attached analog parts required, the product may be shipped unadjusted from the factory. The product also proves to be much less vulnerable to aged deterioration.

Claims: A decision-directed digital phase-locked loop circuit comprising: (a) instantaneous phase detecting means (10) for obtaining the instantaneous phase value (ΔP k ) of a digital sample value (S k ) relative to a zero cross point of a reproduced signal of a partial response channel based on a plurality of sampled values (S k , S k+1 ) of said reproduced signal; (b) a digital loop filter (20) for cyclically calculating and outputting a phase value (P k ) of a sample point (k) of said reproduced signal and modifying said calculation in response to an instantaneous phase digital value (ΔP k ) obtained by said instantaneous phase detecting means; characterized by (c) phase value predicting means for obtaining the phase value (P P(k+3) ) of a future sample point (k+3) based on the phase value (P k-1 ), output by said digital loop filter, at the current sample point (k-1) of said reproduced signal; (d) data predicting means (40) for predicting future data (d k+3 ) of said reproduced signal based on the phase value (P P(k+3) ) of said future sample point (k+3) obtained by said phase value predicting means as well as on future sampled values (S k+3 , S k+2 ) of a predetermined pattern of said reproduced signal; and (e) phase modification control means for determining, based on the future data predicted by said data predicting means, whether the current zero cross point of said reproduced signal is a point where valid data exist, and for allowing said digital loop filter to modify the output phase value thereof using said instantaneous phase value (ΔP k ) if said current zero cross point is found to be a point where valid data exist. A decision-directed digital phase-locked loop circuit according to claim 1, further comprising valid signal generating means (50) for outputting to said phase modification control means a valid signal (V pk ) when the current phase value (P k ) is smaller than a preceding phase value (P k-1 ), said valid signal indicating that the sample point of said reproduced signal exists in the current sampling time slot; wherein said phase modification control means allows said digital loop filter (20) to modify the output phase value thereof using said instantaneous phase value only when said phase modification control means receives said valid signal from said valid signal generating means. A decision-directed digital phase-locked loop circuit according to claim 1, wherein said reproduced signal is obtained by having magnetic patterns recorded on a magnetic disc read by a reproduction head. A decision-directed digital phase-locked loop circuit according to claim 1, wherein said reproduced signal comes from a partial response (1, 0, -1) channel. A decision-directed digital phase-locked loop circuit according to claim 1, wherein said reproduced signal comes from a partial response (1, -1) channel. A decision-directed digital phase-locked loop circuit according to claim 1, further comprising: initial pattern supplying means for supplying said instantaneous phase detecting means (10) with a predetermined repetitive signal pattern of said partial response channel during initialization; and mode switching control means (60) for causing said phase modification control means to switch said digital loop filter (20) between control modes so that said digital loop filter will modify the output phase value thereof using said instantaneous phase value at all zero cross points of said repetitive signal pattern. A decision-directed digital phase-locked loop circuit according to claim 6, wherein said initial pattern supplying means generates said predetermined repetitive signal pattern based on the signal recorded in a preamble zone of a magnetic disc sector.

Inventors: YADA HIROAKI, YADA, HIROAKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: G11B20
IPC codes: H03M5, H04L7, H03L7, G11B20