Process for checking the memories of a programmed micro-computer, by means of a micro-programme incorporated in the micro-computer itself

Abstract: The invention relates to a process for checking, reading or writing, memories (12-15) of a programmed micro-computer (10), essentially comprising the following steps: to select a pre-selected logic space in a memory to be checked, to trigger the process of addressing micro-instructions of a suitable micro-programme related to a pre-selected checking procedure, so as to cause its execution by means of a pre-established number of clock strokes, to repeat in a loop, according to an incremental sequence, the execution of said micro-instructions of the micro-programme.

Description: The present invention relates to a process for checking the memories of a programmed micro-computer, optimized as regards life and efficiency. In the production of micro-computers the finished products are subjected to testing operations, in order to check on their functionality. Generally micro-computers have memories within them of not inconsiderable size, and considering that the checking time depends, in addition to the size of the memory, also on the type of memory to be checked, and that a minimum of three readings is required for a ROM (READ ONLY MEMORY) and a maximum of sixteen readings for an EPROM (ERASABLE READ ONLY MEMORY), it can be seen that checking operations involve problems of time and cost, especially because they are executed on very expensive machines. With the current checking devices and procedures, based on programmes formed by instructions, that require a discrete time for the process of reading any information contained in the memory, testing times are very long and involve substantial increases in production costs. IRE WESCON CONVENTION RECORD, vol. 34, Nov. 1990, North Hollywood, USA, p. 175-178, GALLAKOTA et al.:" Testing of the i486 microprocessor" discloses a built-in self test on a microprocessor wherein microcode controls the testing of a cache. EP-A-0 315 275 discloses testing of a microcomputer memory using scan patch circuitry for addressing the memory and for data input/output. The object of the present invention is a process for checking the memories of a micro-computer, that allows an improvement in the analysis of said memories, at the same time minimizing checking times, so as to reduce production costs. According to this object a process has been developed for checking the memories of a programmed micro-computer, the micro-computer comprising: read only memories and read-and-write memories, divided into logic spaces suitable for containing information related to programmes and data, a group of input and output gates, a register file, a central micro-processor unit (CPU) comprising in turn a control memory containing micro-programmes constituted by micro-instructions, a pre-processor suitable for decoding instruction codes and for defining the addresses of the input points of the micro-programmes related to the instructions, a circuit for decoding said addresses of the input points of the micro-programmes, a pointer capable of addressing said micro-instructions of said micro-programmes, two scanning cell chains suitable for being triggered by means of pre-established operating signals and capable of providing control signals of said logic spaces of said memories and of said micro-programmes, a decoding unit capable of transforming into operational signals said micro-instructions of the micro-programmes contained in said control memory, an arithmetic-logic unit containing an indicator register, a programme counter and incrementer, capable of controlling the process of addressing the information contained in said read-only and read-and-write memories, a circuit capable of providing the address of each pre-selected register of said register file, the above process being characterized in that it comprises the following steps: to trigger said scanning cell chains by means of pre-established operating signals to generate control signals indicative of the pre-selected logic space of one of said memories to be checked, according to a pre-selected checking procedure that can be executed by means of micro-instructions of a suitable micro-programme stored in said control memory, to select, through said scanning cell chains, said pre-selected logic space to be checked, to initialize, through said scanning cell chains, said programme counter and incrementer, to define the starting point of said pre-selected logic space to be checked, to select, through said scanning cell chains, one of the registers of said file and one of said gates, as an output gate, on which to send all information taken from said logic space, to trigger, through said scanning cell chains, said control memory, said pre-processor, said decoding unit and said pointer for addressing said micro-instructions of the micro-programme related to said pre-selected checking procedure, in order that it be executed by means of a pre-established number of clock strokes, to send to said selected register of said register file and to said output gate an information taken from said pre-selected logic space, to repeat in a loop, according to an incremental sequence, the execution of said micro-instructions of the micro-programme so as to send in succession to said selected register of said register file and to said output gate all the information contained in said pre-selected logic space, and to reset the micro-controller through a special signal to return it to normal operating conditions. According to a preferred embodiment, said micro-programme suitable for executing a pre-selected checking procedure is a micro-programme formed by groups of micro-instructions for executing a procedure for reading said memories. According to another preferred embodiment, said micro-programme suitable for executing a pre-selected checking procedure is a micro-programme formed by groups of micro-instructions to execute a process of writing during the testing step, of said memories. With the checking process according to the invention, based on micro-programmes and on an infinite loop micro-procedure, it is possible to proceed to an incremental reading, or writing, of the memories of a micro-controller, analysing all the information contained in them, in a very short time. The process according to the invention is particularly advantageous because it is based on micro-programmes incorporated in the micro-computer and of a general-purpose type, that may be used on any micro-computer of the same family without any changes and with no specific adaptations. Features and advantages of the invention shall now be illustrated with reference to a preferred embodiment, represented as non-limiting examples in the enclosed drawing, wherein: the only figure illustrates, with a block diagramme, a micro-processor that incorporates micro-programmes suitable for executing the checking process according to the invention. There is indicated in the figure as a whole with 10 a micro-controller comprising a central micro-processor unit (CPU), indicated as a whole with 11, a reading and writing memory (RAM) 12, an electrically-erasable programmable read-only memory (EEPROM) 13, an erasable programmable read-only memory (EPROM) 14, a read-only memory (ROM) 15, a group of input and output gates 16, a register file 17, a bus 18 operationally connected to the memmories 12-15 and to the central micro-processor unit 11, and a bus 19 operationally connected to the same central micro-processor unit, to the group of input and output gates 16 and to the register file 17. The central micro-processor unit 11 in turn comprises a read-only control memory (CROM) indicated with 20, a pre-processor indicated with 21, a decoding circuit indicated with 22, a pointer indicated with 23, two scanning cell chains indicated with 24 and 25, a decoding unit indicated with 26, an arithmetic-logic unit (ALU) 27 containing an indicator register (flag), a programme counter and incrementer indicated with 28, a circuit for the process of addressing the registers of the file 17, indicated with 29, all connected operationally together. The control memory 20 is suitable for containing micro-programmes constituted by micro-instructions, which, according to the invention, are micro-programmes formed by micro-instructions suitable for executing the checking procedures, such as the process of reading of memories 12-15, and the process of writing during the testing step of memories 14 and 15. The pre-processor 21 contains registers of instructions with the addresses of the input points of said micro-programmes, and the decoding circuit 22 executes the decoding of said addresses of the input points of the same micro-programmes; the pointer 23 is capable of addressing said micro-instructions of said micro-programmes. The two scanning cell chains 24 and 25 are suitable for being triggered by means of pre-established operating signals, that are introduced into the micro-processor 11 through a reset gate of the group 16, and are capable of supplying the control signals of the logic spaces of said read-only, and read-and-write, memories and of said micro-programmes. The decoding unit 26 is capable of transforming into operational signals said micro-instructions of the micro-programmes contained in the control memory 20. The arithmetic-logic unit 27 contains an indicator register (flag), suitable for identifying the logic space selected by one of said memories 12-15. The programme counter and incrementer 28 is capable of controlling the process of addressing the information contained in said read-only and read-and-write memories. As has already been said, the control memory 20 contains micro-programmes suitable for executing procedures for checking, reading or writing the memories. The micro-programme for executing the procedure for reading is formed by the following sequence of micro-instructions: a first micro-instruction suitable for starting the reading operation: u1) START READ (next u2), a second micro-instruction to prepare the process of addressing the subsequent information to be read, in a buffer register (master latch) of the selected memory: u2) INC+ ->PC & LIP, R* (next u3), a third micro-instruction suitable for writing the information read in a pre-selected register of the file 17 and in a pre-selected gate of the group 16, and to recharge the incrementer 28 with the address of the subsequent information to be read: u3) MEM -> DWR PC -> INC SET INC (next u1). The micro-programme for executing the procedure for writing information identical with pre-selected addresses is formed by the following sequence of micro-instructions: a first micro-instruction suitable for starting the operation of writing an information identical with the low part of an address: u1) START WRITE PC1 ->LIP, RO (next 2), a second micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory: u2) INC+ ->PC & LIP, R* (next u3), a third micro-instruction suitable for recharging the incrementer 28 with the address of the subsequent information to be written: PC ->INC SET INC (next u1). The micro-programme for executing the matrix-type writing procedure of information identical with that contained in two pre-selected registers (AD and AB) of the group 16, is formed by the following sequence of micro-instructions: a first micro-instruction suitable for starting the operation of writing an information identical with that contained in the first pre-selected register (AD): u1) START WRITE AD ->LIP, RO (next 2), a second micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory: u2) INC+ ->PC & LIP, R* (next u3), a third micro-instruction suitable for recharging the incrementer 28 with the address of the subsequent information to be written: PC ->INC SET INC (next u4), a fourth micro-instruction suitable for starting the operation of writing an information identical with that contained in the second pre-selected register (AB): u4) START WRITE AB ->LIP, RO (next u5), a fifth micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory: u5) INC+ ->PC & LIP, R* (next u6), a sixth micro-instruction suitable for recharging the incrementer 28 with the address of the subsequent information to be written: PC ->INC SET INC (next u1). To execute the process of checking the memories 12-15, by means of the reading procedure or by means of the reading and writing procedure, pre-established operating signals are introduced through said reset gate of the group 16; these operating signals, that, for example, consist of two pre-selected voltage levels, 7.5 volts and 5 volts, sent in a given sequence, generate control signals that interrupt the normal operation of the micro-controller and trigger the scanning cell chains 24 and 25; these, with a "scan path" procedure, described in the Italian patent application No. 21820 A/90 (IT-B-1246301), in the name of the same Applicant, select the pre-selected logic space of one of the memories 12-15 to be checked, containing either programme information or data information; the same scanning cell chains select the starting point of the same logic space, set the programme counter 28 with the information identifying the same starting point, and selects one of the gates of the group 16, configuring it as the output gate of the information taken from the selected logic space, so that these are transferred into a pre-selected register of the file 17 and at the same time on said output gate. The same scanning cell chains 24 and 25 trigger the address of the input point of one of the micro-programmes for checking, reading or writing, stored in the control memory 20, through the pre-processor 21, the decoding unit 22 and the pointer 23. Control of the reading and writing micro-programmes is executed through the number of clock strokes necessary for the entire operation to be completed, taking into account that each set of micro-instructions of the same micro-programmes requires one clock stroke and that three clock strokes are necessary for reading an information, while from three to six clock strokes are necessary for writing an information. The checking process is executed with an infinite-loop micro-procedure, which in the minimum access time for internal memories, three clock strokes, executes an incremental reading, or writing, with the information returned on the selected output gate of the group 16. To exit from the checking procedure reset the micro-controller 10. The checking process described, based on micro-programmes and on an infinite-loop micro-procedure, allows the execution of the reading and writing process of the memories of a micro-controller, in a complete manner, analysing all the information contained in them, with a substantial time saving over the usual procedures, based on programmes formed by instructions, that, for the process of reading an information contained in the memory, typically require ten clock strokes. Another advantage of the proposed procedure is that of being based on micro-programmes incorporated in the micro-computer and of the general-purpose type, that may be used on any micro-computer without any changes and with no specific adaptations.

Claims: Process for checking the memories of a programmed micro-computer (10), the micro-computer (10) comprising: read only memories and read-and-write memories (12, 13, 14, 15), divided into logic spaces suitable for containing information related to programmes and data, a group of input and output gates (16), a register file (17), a central micro-processor unit (CPU) (11) comprising in turn a control memory (20) containing micro-programmes constituted by micro-instructions, a pre-processor (21) suitable for decoding instruction codes and for defining the addresses of the input points of the micro-programmes related to the instructions, a circuit (22) for decoding said addresses of the input points of the micro-programmes, a pointer (23) capable of addressing said micro-instructions of said micro-programmes, two scanning cell chains (24, 25) suitable for being triggered by means of pre-established operating signals and capable of providing control signals of said logic spaces of said memories (12-15) and of said micro-programmes, a decoding unit (26) capable of transforming into operational signals said micro-instructions of the micro-programmes contained in said control memory, an arithmetic-logic unit (27) containing an indicator register, a programme counter and incrementer (28) capable of controlling the process of addressing the information contained in said read-only and read-and-write memories, a circuit (29) capable of providing the address of each pre-selected register of said register file, the above process being characterized in that it comprises the following steps: to trigger said scanning cell chains (24, 25) by means of pre-established operating signals to generate control signals indicative of the pre-selected logic space of one of said memories (12-15) to be checked, according to a pre-selected checking procedure that can be executed by means of micro-instructions of a suitable micro-programme stored in said control memory (20), to select, through said scanning cell chains (24, 25), said pre-selected logic space to be checked, to initialize, through said scanning cell chains, (24, 25), said programme counter and incrementer (28), to define the starting point of said pre-selected logic space to be checked, to select, through said scanning cell chains (24, 25), one of the registers of said file (17) and one of said gates (16), as an output gate, on which to send all information taken from said logic space, to trigger, through said scanning cell chains (24, 25), said control memory (20), said pre-processor (21), said decoding unit (22) and said pointer (23) for addressing said micro-instructions of the micro-programme related to said pre-selected checking procedure, in order that it be executed by means of a pre-established number of clock strokes, to send to said selected register of said register file (17) and to said output gate (16), an information taken from said pre-selected logic space, to repeat in a loop, according to an incremental sequence, the execution of said micro-instructions of the micro-programme so as to send in succession to said selected register of said register file (17) and to said output gate all the information contained in said pre-selected logic space, and to reset the micro-computer (10) through a special signal to return it to normal operating conditions. Process according to claim 1, characterised in that said micro-programme suitable for executing a pre-selected checking procedure is a micro-programme formed by a sequence of micro-instructions for executing a procedure for reading said memories (12, 13, 14, 15). Process according to claim 1, characterised in that said micro-programme suitable for executing a pre-selected checking procedure is a micro-programme formed by a sequence of micro-instructions for executing a process of writing during the testing step, of pre-established information in said memories (12, 13). Process according to claim 2, characterised in that said micro-programme for executing the procedure for reading is formed by the following sequence of micro-instructions: a first micro-instruction suitable for starting the reading operation, a second micro-instruction to prepare the process of addressing the subsequent information to be read, in a buffer register (master latch) of the selected memory (14, 15), a third micro-instruction suitable for writing the information read in a pre-selected register of said register file (17) and in the pre-selected gate of said output gates (16), and to recharge said programme counter and incrementer (28) with the address of the subsequent information to be read. Process according to claim 3, characterised in that said micro-programme for executing the procedure for writing, particularly in the case of information identical with pre-selected addresses, is formed by the following sequence of micro-instructions: a first micro-instruction suitable for starting the operation of writing an information identical with the low part of an address, a second micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory (12, 13), a third micro-instruction suitable for recharging said incrementer (28) with the address of the subsequent information to be written. Process according to claim 3, characterised in that said micro-programme for executing the writing procedure, particularly matrix-type writing of information identical with that contained in two pre-selected registers (AD and AB) of said output gates (16), is formed by the following sequence of micro-instructions: a first micro-instruction suitable for starting the operation of writing an information identical with that contained in the first pre-selected register (AD), a second micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory (12, 13), a third micro-instruction suitable for recharging said programme counter and incrementer (28) with the address of the subsequent information to be written, a fourth micro-instruction suitable for starting the operation of writing an information identical with that contained in the second pre-selected register (AB), a fifth micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory (12, 13), a sixth micro-instruction suitable for recharging said programme counter and incrementer (28) with the address of the subsequent information to be written.

Inventors: SCARRA FLAVIO, SCARRA, FLAVIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: G11C29
IPC codes: G06F11, G11C29, G06F15