Method of forming silicide in integrated circuit manufacture

Abstract: Electrical discontinuities in a silicide formed on a patterned surface are prevented by forming metal fillets(e.g.11) in the recesses of the patterned polysilicon(e.g.7) covered surface, and then depositing a metal layer(e.g.9) and reacting with silicon(e.g.7) to form the silicide. The fillet(e.g.11) provides extra metal at a place where there is typically a deficiency in conventional deposition techniques.

Description: Technical Field This invention relates to a method of semiconductor integrated circuit manufacturing in which a metallic silicide is formed. Background of the Invention Semiconductor integrated circuits typically have thousands of devices, such as field effect transistors with source/drain regions and a gate electrode, which must be electrically contacted. The transistors are frequently contacted through openings or windows in a patterned dielectric which expose at least portions of the source/drain regions or gate electrode. Additionally, electrical connections between devices must be made, e.g., from the gate of one transistor to the source/drain region of another transistor or between source/drain regions of different nearby transistors. These connections are frequently referred to as local interconnects and often run over intervening features such as runners. The local interconnects, which may be formed of polysilicon or titanium nitride (TiN), are electrically isolated from the underlying features by a dielectric layer. The metal of choice for many integrated circuit applications has been aluminum. This metal is relatively easy to deposit and then pattern by etching, and has a relatively high electrical conductivity. However, aluminum exhibits drawbacks at submicron dimensions for local interconnects. Typically, processes that use local interconnects subject devices to temperatures greater than 800°C after the local interconnect has been formed. This temperature makes it virtually impossible to use aluminum as a local interconnect. Further, aluminum interconnects are prone to failure because of, e.g., electromigration. Accordingly, alternatives to aluminum have been sought. One extensively investigated alternative to aluminum is formed by the group of metallic silicides such as titanium or tantalum silicide. The silicon to metal ratio of deposited silicides is very hard to control and makes deposited silicides unsuitable for manufacture. Additionally, deposited silicides are not self-aligned. Alternatively, silicides are frequently formed by depositing a metal layer on silicon and heating the two materials so that they react to form the desired silicide. The reaction rate between many metals and silicon is reasonably fast and controlled at silicide formation temperatures. These temperatures are compatible with the integrated circuit processing sequence. Unreacted metal, if any, may be removed after heating is completed. This process is conceptually simple but requires appropriate amounts of metal and silicon so that a silicide is formed everywhere. Silicides are frequently used to increase the conductivity of polysilicon features, such as runners or local interconnects, because the silicide has a higher conductivity than does the polysilicon. However, problems may arise in the implementation of the silicide forming, i.e., siliciding, process described. This is especially true when silicided local interconnects are formed over relatively closely spaced features. For example, a layer of silicide forming metal such as titanium amy be deposited after polysilicon has been deposited and patterned to form conductive features. However, sputtered titanium does not deposit conformally on the polysilicon and the titanium thins at the bottom edges of the region between the features due to shadowing. The lack of metal in this area results in very little silicide formation at the bottom edges. Agglomeration of thin silicide at the bottom edges of runners can lead to undesirably high resistances or, in the worst case, an open circuit. The properties of titanium silicides are discussed in the literature. See, for example, Applied Physics Letters, 48 , pp. 1591-1593, June 9, 1986 and Journal of Applied Physics, 57, pp.5240-5245, June 15, 1985. United States Patent 4,507,853 to McDavid teaches a metallization process for integrated circuits, wherein to reduce metal feature size, the metal layer must be thinned to the point that topological irregularities cause thickness irregularities, especially in openings (contacts) formed through insulator layers. These insulator layers may be as thick as or thicker than the metal layer. While these thickness irregularities could be avoided by thickening the metal layer, a thicker metal layer requires an undesirable increase in feature size. Thus, to enhance metal thickness at the contact and still avoid thickening the metal layer, McDavid uses a three-step, two-metal process. Firstly, a metal layer is deposited on the surface of the semiconductor water. Second, the metal layer is selectively removed, by an anistropic etch. The anisotropic etch selectively removes horizontal portions of the metal layer, leaving segments in the contact, along the contact's sidewall. Then, third, a second metal layer is deposited on the surface, forming the final metal layer. This resulting metal layer is "patterned to create contacts and interconnections". It is critical. in order to minimize feature size, that the final metal layer be no thicker than necessary. Summary of the Invention A method of integrated circuit manufacture is described as outlined in claim 1. In one exemplary embodiment. the conducting compound comprises a silicide. In a preferred embodiment. the patterned surface comprises polysilicon runners, i.e., the features are runners. In yet another embodiment. a dielectric layer is deposited and patterned to form openings which expose selected portions of the substrate before the polysilicon is deposited. Brief Description of the Drawing FIGs. 1-4 are sectional views of a portion of an integrated circuit at several stages during fabrication according to an embodiment of this invention. For reasons of clarity. the elements depicted are not shown to scale. Detailed Description A particular embodiment of the invention will be discussed by reference to FIGs. 1-4. Other embodiments will be evident to those skilled in the art. FIG. 1 is a sectional view of a portion of an integrated circuit at an early stage of fabrication according to this invention. Depicted are substrate 1, features 3, dielectric layer 5, and polysilicon layer 7. The term substrate is used to mean any material which lies beneath and supports another material and may be silicon, polysilicon, etc. The features have conductive layers 31 sidewalls 33, and top layer 35. The dielectric layer 5 has been patterned to form openings 37 which expose selected portions 39 of the substrate such as source/drain regions of field-effect transistors. The polysilicon layer may comprise runners which are formed by depositing a polysilicon layer and then patterning the polysilicon. As depicted, the polysilicon layer 7 extends between openings 37. Those skilled in the art will readily select appropriate deposition and patterning techniques for the polysilicon and also fabricate the features on the substrate. A conducting compound forming metal layer 9 is typically deposited by a technique such as sputtering. An exemplary metal is titanium. The metal does not deposit conformally and the layer has a nonuniform thickness. As can be seen in FIG. 2, the layer 9 is thinner at the bottom edges of the recess between the features. The scarcity of metal in the recesses will lead to insufficient conducting compound formation in those regions and may even cause electrical discontinuities. An anisotropic etchback is now performed. The greater effective thickness of the metal at the edges of the features results in fillets 11 being left in the recesses at the bottom edges between the runners. The resulting structure is depicted in FIG. 3. An appropriate etchback technique will be readily selected by those skilled in the art. It is emphasized that all required of the etchback is that metal fillets remain in the recesses after the etchback has been completed. A second layer 13 of a conducting compound forming metal is now deposited by, e.g., sputtering. The structure is depicted in FIG. 4. The fillets insure that there is adequate metal for conducting compound formation present in the recesses between the features. A standard heating step is now performed to react the metal and the polysilicon to form the desired conducting compound which is a silicide in the embodiment. After completion of this reaction, unreacted metal is removed. Appropriate removal techniques will be readily selected. Standard processing techniques are now used to finish fabrication of the integrated circuiL These techniques are well known and further description is not required to understand this invention. Variations of the embodiment described will be readily thought of by those skilled in the art. For example, silicide forming metals other than titanium may be used. Additionally, the features may be field-oxide regions of gate structures. Other variations will be readily thought of by those skilled in the art.

Claims: A method of integrated circuit manufacture comprising: forming a plurality of spaced-apart features (3) having recesses therebetween on a substrate (1), said substrate (1) and said features (3) having surfaces, depositing a layer of polysilicon (7) and a first layer (9) of a conducting compound forming metal on said surfaces, said first layer being deposited non-conformably etching said first layer (9) to leave metal fillets in said recesses (11); depositing a second layer (13) of conducting compound forming metal; and forming a conducting compound by heating. A method as recited in claim I in which said conducting compound comprises a silicide. A method as recited in claim 2 comprising the further step of depositing a dielectric layer (5) on said features (3) and said substrate (1). A method as recited in claim 3 comprising the further step of patterning said dielectric layer (5) prior to said polysilicon (7) deposition to expose selected portions of the substrate (1). A method as recited in claim 4 in which said exposed portions comprise silicon. A method as recited in claim 3 in which said features (3) comprise a plurality of silicon runners.

Inventors: MANOCHA AJIT, MERCHANT SAILESH MANSINH, SINGH RANBIR, MANOCHA, AJIT, MERCHANT, SAILESH MANSINH, SINGH, RANBIR
Applicants: AT & T CORP, AT&T CORP.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L23