Sram cell and structure with polycrystalline p-channel load devices

Abstract: A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit having an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. A contact layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices. A second insulating layer is formed over the integrated circuit having an opening exposing a portion of the contact layer. A first conductive layer is formed over the integrated circuit, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A gate oxide layer is formed over the first gate electrode and a portion of the second gate electrode of the first and second P-channel devices. A second conductive layer is formed over the integrated circuit, patterned and etched to define a source/drain and channel region of the first gate electrode of the first P-channel device and covering a portion of the second gate electrode of the second P-channel device.

Description: The present invention relates generally to semiconductor integrated circuit processing, and more specifically to a SRAM cell and structure with polycrystalline p-channel load device without series diodes. CMOS static random access memories (SRAM) are increasingly used in the semiconductor industry due to their combination of speed, low power and no requirement for refresh. Information can be written into and read out of a SRAM cell faster than with a DRAM cell because the transistors of the SRAM cell can be switched faster than capacitors can be charged and drained. The trade-off, however, to achieve greater speed and less volatility is that the SRAM cell is less dense requiring more space. The basic SRAM cell can be formed using cross-coupled CMOS inverters having 2 each N-channel and P-channel transistors. The cell is accessed by, typically, 2 N-channel control gates for a standard SRAM cell and 4 control gates for 2-port memory devices. To conserve physical layout space, the P-channel transistors are often replaced with resistive loads. Use of the P-channel transistors as the load for the SRAM cell, however, results in the cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the P-channel transistors provide a higher drive current than high resistance devices. Also, use of P-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating P-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs. A disadvantage of using polycrystalline P-channel load transistors arises where ohmic contact is required between the interconnection of P-channel and N-channel transistors. Ohmic contact between interconnect layers is desirable because no P-N junction is formed. A P-N junction is formed, however, where polycrystalline interconnect lines having different conductivity types make contact. A similar junction can be formed when polycrystalline silicon lines having the same conductivity type, but very different doping levels (such as N -- to N+ ) make contact. In the prior art, as shown in Figures 1 and 2, for example, where P-channel transistors are used as the load devices, a junction diode will be formed at the location where a polycrystalline P-channel transistor contacts a N-channel transistor. As shown in Figure 1, if the polycrystalline P-channel transistor T1 has a gate electrode made of a N-type conductivity polycrystalline silicon, a P-N junction or junction diode will be formed between the P+ source/drain region of the P-channel transistor and its N+ gate which connects to the source/drain region of the N-channel transistor T3. As shown in Figure 2, if the conductivity type of the gate of the P-channel transistor is P-type, a junction diode will be formed between the P-channel gate electrode of T1 and the N+ source/drain region of the N-channel transistor T4. It would be desirable to use P-channel transistors as the load devices in an SRAM cell while preventing a junction diode from forming between P-channel and N-channel transistors. It would be desirable to use a conductive material as an interconnect at the shared contact areas between the P- and N-channel devices to prevent a junction diode from forming. 'A 25 µm 2 New Poly-Si PMOS Load (PPL) SRAM Cell having excellent soft error immunity' in 'The Electron Device Meeting', December 1988, San Francisco pages 48-51, discloses the formation of a conductive interconnect over an N-type source/drain region to electrically connect it to an overlying P-type third polysilicon layer via an N-type second polysilicon layer. EP-A-0173245 discloses the use of a metal, for example tungsten, or a metal silicide for ohmically contacting high resistance polycrystalline silicon to low resistance single crystal silicon and for preventing the diffusion of impurities from the silicon into the polysilicon. Neither of these references disclose arrangements for avoidance of diode formation. EP-A-0297350 discloses the method of silicidation at a via opening to short out a P+/N+ diode. It is an object of the present invention to provide a method and structure for the formation of a semiconductor device which may reduce the problem of diode formation at an interlayer connection. Therefore, according to the present invention, a method is provided for producing a semiconductor device structure with polycrystalline p-channel load devices of an integrated circuit comprising the steps of: providing a first n-channel field effect device; providing a first insulating layer disposed over the n-channel field effect device with an opening to expose an underlying conductive structure comprising at least a portion of a n-type source/drain region of said n-channel field effect device; providing a contact layer over the exposed underlying conductive structure defining a portion of a shared contact region, said contact layer making electrical contact with said source/drain region of said n-channel field effect device; providing a first p-type polysilicon layer comprising a first gate electrode of a first p-channel field effect device disposed over a portion of the first insulating layer; providing a first gate oxide layer; and providing a second polysilicon layer, comprising the source/drain region and channel region of the first p-channel field effect device, disposed over the first gate electrode of the first p-channel field effect device and the contact layer, said source/drain region of said p-channel device having p-type conductivity, characterised in that said first p-type polysilicon layer also comprises a region in contact with said contact layer, said gate oxide layer being disposed over the first gate electrode of the first p-channel field effect device and said region of said first p-type polysilicon layer in contact with said contact layer, and in that the source/drain region of the p-channel device makes electrical contact with the underlying conductive structure through said region of said first p-type polysilicon layer and said contact layer and wherein said contact layer is formed frommaterials selected from the group comprising metal; metal silicide; n-type polysilicon overlaid with a metal silicide; and silicide overlaid with p-type polysilicon. According to another aspect of the present invention there is provided a structure consisting of a portion of a semiconductor integrated circuit comprising: a first n-channel field effect device; a first insulating layer disposed over the n-channel field effect device with an opening to expose an underlying conductive structure comprising at least a portion of the n-type source/drain region of said n-channel field effect device; a contact layer over the exposed underlying conductive structure defining a portion of a shared contact region, said contact layer making electrical contact with said source/drain region of said n-channel field effect device; a first p-type polysilicon layer comprising a first gate electrode of a first p-channel field effect device disposed over a portion of the first insulating layer; a first gate oxide layer; and a second polysilicon layer, comprising the source/drain region and channel region of the first p-channel field effect device, disposed over the first gate electrode of the first p-channel field effect device and the contact layer, said source/drain region of said p-channel device having p-type conductivity, characterised in that said first p-type polysilicon layer also comprises a region in contact with said contact layer, said gate oxide layer being disposed over the first gate electrode of the first p-channel field effect device and said region of said first p-type polysilicon layer in contact with said contact layer, and in that the source/drain region of the p-channel device makes electrical contact with the underlying conductive structure through said region of said first p-type polysilicon layer and said contact layer, and wherein said contact layer is formed from material selected from the group comprising: metal; metal silicide; n-type polysilicon overlaid with a metal silicide; and silicide overlaid with p-type polysilicon. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figures 1-2 illustrate a schematic representation of the SRAM prior art circuit. Figures 3, 4, 4a, 5, 5a, 6 and 6a illustrate alternative preferred methods for fabricating a semiconductor device structure, according to the present invention. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. Referring to Figure 3, an integrated circuit device is to be formed in a silicon substrate 10. Selected regions of the substrate 10 are oxidized to form a field oxide insulating region 12. A first N-channel field effect device 14 having a gate oxide layer 16, a first gate electrode 18, sidewall oxide spacers 20 and source/drain regions 22, 24 are manufactured by methods known in the art. Gate electrode 18 is generally formed from a first polycrystalline silicon layer, such as commonly used to form gate electrodes or field effect devices. A second N-channel field effect device 26 is formed by methods known in the art having a gate oxide layer 28 and a second gate electrode 30. As with the first N-channel field effect device 14, the second N-channel field effect device 26 is generally formed from a first polycrystalline silicon layer. The source/drain region 22 of device 14 and the gate electrode 30 form the interconnected conductive structures of the N-channel devices. Referring to Figures 4 and 4a, a first oxide insulating layer 34 is formed over the integrated circuit by known methods. Insulating layer 34 is patterned and etched to expose a portion of the underlying conductive structure source/drain region 22 of device 14. A portion of the second gate electrode 30 of the second N-channel device 26 may also be exposed during the patterning and etching steps. Source/drain region 22 and gate electrode 30 of the first and second N-channel field effect devices respectively are typically implanted with a N+ type dopant such as arsenic or phosphorus. Device fabrication up to this stage utilizes conventional process steps well known in the art. Historically, the SRAM cell is built with all N-channel and P-channel field effect devices or transistors being formed in the substrate. In order to increase packing density while maintaining better electrical characteristics using P-channel transistors as load devices, the P-channel transistors in the present invention are stacked above the N-channel transistors. Referring to Figure 4, a metal containing layer 36 is deposited over the surface of the integrated circuit. Layer 36 is preferably a refractory metal or a refractory metal silicide such as tantalum or tantalum silicide respectively. Metal layer 36 is deposited by sputtering. The metal containing layer 36 is then patterned and etched by methods known in the art to form a shared contact region disposed over the exposed portions of source/drain region 22. Layer 36 will also be disposed over a portion of gate electrode 30 if gate 30 was exposed during the patterning and etching process of the first insulating layer 34. In the alternative embodiment shown in Figure 4a, an interconnect layer 35 containing a doped polysilicon layer 36 and a barrier layer 37 is formed over the surface of the integrated circuit. Polysilicon layer 36 is first deposited, then barrier layer 37 is deposited. The interconnect layer 35 is then patterned and etched by methods known in the art to form a shared contact region disposed over the exposed portions of source/drain region 22. Layer 35 will also be disposed over a portion of gate electrode 30 if gate 30 was exposed during the patterning and etching process of the first insulating layer 34. Polysilicon layer 36 is implanted with a N-type dopant. Barrier layer 37 is preferably a silicide. Referring to Figures 5 and 5a, a second oxide insulating layer 38 may be formed over the integrated circuit, if necessary. Insulating layer 38, if formed, is then patterned and etched by methods known in the art to expose a portion of the metal containing layer 36. A first conductive layer is then deposited over the integrated circuit. The first conductive layer is then patterned and etched to define a first gate electrode 42 of a first P-channel field effect device. Alternatively, a second gate electrode 40 of a second P-channel field effect device may also be defined from the first conductive layer. The first conductive layer is typically a doped polysilicon. Thus, gate electrode 40 and gate electrode 42, if formed, are typically implanted with a P+ type dopant such as boron or boron diflouride. In the embodiment shown in Figure 5, if gate electrode 40 is formed, metal container layer 36 is now a shared contact between gate electrode 40 of the second P-channel device and the source/drain region 22 of the first N-channel device. Metal containing layer 36 will also connect gate 30 of the second N-channel device to source/drain region 22 and gate electrode 40 if a portion of gate 30 was exposed. If gate 30 is not connected to metal layer 36, it will connect to source/drain region 22 elsewhere (not shown). In the alternative embodiment shown in Figure 5a, if gate electrode 40 is formed, interconnect layer 35 is now a shared contact between gate electrode 40 of the second P-channel device and the source/drain region 22 of the first N-channel device. Interconnect layer 35 will also connect gate 30 of the second N-channel device to source/drain region 22 and gate electrode 40 if a portion of gate 30 was exposed. If gate 30 is not connected to the interconnect layer 35, it will connect to source/drain region 22 elsewhere (not shown). Polysilicon layer 36 may be implanted alternatively with a P-type dopant. In this case, polysilicon layer 36 will be disposed over the barrier layer 37 to form the shared contact. Referring to Figures 6 and 6a, a gate oxide layer 44 is grown over the first gate electrode 42 of the first P-channel device and over the second gate electrode 40 of the second P-channel device, if formed. If the second gate electrode 40 is formed, the gate oxide layer 44 will be etched to expose a portion of the second gate 40. A second conductive layer 46 is deposited over the integrated circuit and patterned and etched to form a source/drain and channel region of the first gate electrode 42 of the first P-channel field effect device. The second conductive layer will be disposed over the gate oxide covering gate 42 and the exposed portion of gate 40 if gate 40 is formed. The second conductive layer 46 is typically a doped polysilicon layer, lightly implanted with a N-type dopant in the channel region directly over gate 42 and heavily implanted with a P+ type dopant such as boron in the source/drain region. Referring to Figure 6, if gate electrode 40 is formed, metal containing layer 36 is now a shared contact between gate electrode 40 of the second P-channel device, the source/drain region 22 of the first N-channel device and the source/drain and channel region 46 of the gate electrode 42. If gate electrode 40 is not formed on top of metal containing layer 36 as shown, it will be connected to layer 36 elsewhere such as beside layer 36 coming out from the plane of the drawing as shown in Figure 5 and 6 or it will be connected to layer 36 via layer 46. Metal containing layer 36 will also connect gate 30 of the second N-channel device to source/drain region 22 and gate electrode 40 if a portion of gate 30 was exposed. The metal containing layer is then a shared contact between two N-channel and two P-channel field effect devices in a six transistor SRAM cell. The shared contact is now connecting materials having different conductivity types. Connecting P-channel and N-channel field effect devices together requires connecting materials of different conductivity types, typically resulting in the formation of P-N junctions. Using a metal or a metal silicide interconnect layer as a shared contact between N-channel and P-channel transistors will prevent a P-N junction from forming. If no P-N junction is formed, the series diodes, as depicted in the prior art Figures 1 and 2, will not form and a good ohmic contact will be made between these devices. Referring to the alternative embodiment of Figure 6a, if gate electrode 40 is formed, the interconnect layer 35 is now a shared contact between gate electrode 40 of the second P-channel device, the source/drain region 22 of the first N-channel device and the source/drain and channel region 46 of the gate electrode 42. If the gate electrode 40 is not formed on top of the interconnect layer 35 as shown, it will be connected to layer 35 elsewhere such as beside layer 35 coming out from the plane of the drawing as shown in Figures 5a and 6a or it will be connected to layer 35 via layer 46. The interconnect layer 35 will also connect gate 30 of the second N-channel device to source/drain region 22 and gate electrode 40 if a portion of gate 30 was exposed. The interconnect layer is then a shared contact between two N-channel and two P-channel field effect devices in a six transistor SRAM cell. The shared contact is now connecting materials having different conductivity types. Connecting P-channel and N-channel field effect devices together requires connecting materials of different conductivity types, typically resulting in the formation of P-N junctions. Using a doped polysilicon layer with a barrier layer such as a refractory metal silicide as an interconnect layer or a shared contact between N-channel and P-channel transistors will prevent a P-N junction from forming. With the barrier layer disposed between the different polysilicon having different conductivity types, no P-N junction is formed and the series diodes, as depicted in the prior art Figures 1 and 2, will not form. A good ohmic contact will thus be made between these devices. While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made within the scope of the claims.

Claims: A method of producing a semiconductor device structure with polycrystalline p-channel load devices of an integrated circuit comprising the steps of: providing a first n-channel field effect device (14); providing a first insulating layer (34) disposed over the n-channel field effect device with an opening to expose an underlying conductive structure comprising at least a portion of a n-type source/drain region of said n-channel field effect device; providing a contact layer (35;36) over the exposed underlying conductive structure defining a portion of a shared contact region, said contact layer making electrical contact with said source/drain region (22) of said n-channel field effect device; providing a first p-type polysilicon layer (40,42) comprising a first gate electrode (42) of a first p-channel field effect device disposed over a portion of the first insulating layer (34); providing a first gate oxide layer (44); and providing a second polysilicon layer (46), comprising the source/drain region and channel region of the first p-channel field effect device, disposed over the first gate electrode (42) of the first p-channel field effect device and the contact layer (35;36), said source/drain region of said p-channel device having p-type conductivity, characterised in that : said first p-type polysilicon layer (40,42) also comprises a region (40) in contact with said contact layer (35;36), said gate oxide layer (44) being disposed over the first gate electrode (42) of the first p-channel field effect device and said region (40) of said first p-type polysilicon layer in contact with said contact layer (35;36), and in that the source/drain region of the p-channel device makes electrical contact with the underlying conductive structure through said region (40) of said first p-type polysilicon layer and said contact layer (35;36) and wherein said contact layer is formed from materials selected from the group comprising metal; metal silicide; n-type polysilicon overlaid with a metal silicide; and silicide overlaid with p-type polysilicon. The method of claim 1, further comprising, before the step of forming the first insulating layer (34) over a substrate (10), the steps of: forming a field oxide region (12) over a portion of the substrate; forming source/drain regions in the substrate; forming the first gate electrode (18) of said first n-channel field effect device (14) over the substrate and forming a second gate electrode (30) of a second n-channel field effect device (26) over a portion of the field oxide region (12) and the substrate (10); whereby the underlying conductive structure is formed from a portion of the source/drain region (22) of the first n-channel field effect device and a portion of the second gate electrode (30) of the second n-channel field effect device. The method of any preceding claim further comprising, after the step of providing the contact layer (35,36), the steps of: forming a second insulating layer (38) over the integrated circuit; and patterning and etching the second insulating layer (38) to expose a portion of the contact layer (35,36), wherein at the same time as the first p-type polysilicon layer is patterned and etched to define the first gate electrode (42) of the first p-channel field effect device, the first p-type polysilicon layer is also patterned and etched to define a second gate electrode (40) of a second p-channel field effect device. The method of claim 3, further comprising the step of: forming the gate oxide layer (44) over the second gate electrode of the second p-channel field effect device at the same time the gate oxide layer (44) is formed over the first gate electrode (42) of the first p-channel device. The method of any preceding claim when dependent upon claim 3 wherein the first p-type polysilicon layer (40,42) and the portion of the second polysilicon layer (46) in contact therewith are doped with a P+ type dopant. The method of any preceding claim when dependent upon claim 2 wherein the source/drain region of the first n-channel field effect device and the second gate electrode of the second n-channel field effect device are doped with a N+ type dopant. The method of any preceding claim wherein the metal material of the contact layer (36) is refractory metal. The method of any preceding claim wherein the metal silicide of the contact layer is refractory metal silicide. The method of any preceding claim wherein, in the contact layer, the silicide layer formed in combination with the doped polysilicon layer is a refractory metal silicide. The method of any preceding claim wherein said step of forming said contact layer comprises sputter depositing metal. A structure consisting of a portion of a semiconductor integrated circuit comprising: a first n-channel field effect device (14); a first insulating layer (34) disposed over the n-channel field effect device with an opening to expose an underlying conductive structure comprising at least a portion of the n-type source/drain region of said n-channel field effect device; a contact layer (35;36) over the exposed underlying conductive structure defining a portion of a shared contact region, said contact layer making electrical contact with said source/drain region (22) of said n-channel field effect device; a first p-type polysilicon layer (40;42) comprising a first gate electrode (42) of a first p-channel field effect device disposed over a portion of the first insulating layer (34); a first gate oxide layer (44); and a second polysilicon layer (46), comprising the source/drain region and channel region of the first p-channel field effect device, disposed over the first gate electrode (42) of the first p-channel field effect device and the contact layer (35;36), said source/drain region of said p-channel device having p-type conductivity, characterised in that : said first p-type polysilicon layer (40,42) also comprises a region (40) in contact with said contact layer (35;36), said gate oxide layer (44) being disposed over the first gate electrode (42) of the first p-channel field effect device and said region (40) of said first p-type polysilicon layer in contact with said contact layer (35;36); and in that the source/drain region of the p-channel device makes electrical contact with the underlying conductive structure through said region (40) of said first p-type polysilicon layer and said contact layer (35;36), and wherein said contact layer is formed from material selected from the group comprising: metal; metal silicide; n-type polysilicon overlaid with a metal silicide; and silicide overlaid with p-type polysilicon. The structure of claim 11 wherein the underlying conductive structure is the source/drain region (22) of the first n-channel field effect device and a second gate electrode (30) of a second n-channel field effect device, and wherein said source/drain region is in the substrate and the second gate electrode is disposed over a field oxide region and the substrate. The structure of claim 12, wherein the source/drain region (22) of the first n-channel field effect device and the second gate electrode (30) of the second n-channel field effect device are doped with a N+ type dopant. The structure of any one of claims 11 to 13, further comprising: a second insulating layer (38), disposed over the contact layer (35,36) and the first insulating layer (34), having an opening exposing a portion of the contact layer (35,36); the region (40) of said first p-type polysilicon layer comprising a second gate electrode of a second p-channel field effect device formed from a p-type doped second polysilicon layer, disposed over the contact layer (35,36) and a portion of the second insulating layer (38). The structure of any one of claims 11 to 14, wherein the metal contact layer is a refractory metal layer. The structure of any one of claims 11 to 15, wherein the metal silicide contact layer is a refractory metal silicide. The structure of claim 14, wherein the second polysilicon layer (46) and a portion of the first p-type polysilicon layer (40,42) are in physical contact and are P+ type doped.

Inventors: BRYANT FRANK R, CHAN TSUI C, JORGENSON LISA K, BRYANT, FRANK R., CHAN, TSUI C., JORGENSON, LISA K.
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L27