Stacked chip assembly and manufacturing method therefor

Abstract: Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating and assembling integrated circuit or memory chips on a circuit substrate or printed wiring board and, more particularly, for stacking such chips into a contacting layered stack, such that their planes lie parallel to and in contact with the plane of the circuit substrate or printed wiring board, and to the parallelly stacked chip assembly manufactured by the method. 2. Description of Related Art and Other Considerations Conventionally, integrated circuit and memory chips are mounted singly in a hermetic package, and the package leads are interconnected to a substrate or a printed circuit board. Alternately, the chips are mounted onto a circuit board in a hermetic hybrid package whose external leads are interconnected to the printed wiring board. When space and volume are at a premium, use of such conventional mounting arrangements results in a less than optimal overall circuit density and a lower circuit speed. Specifically, presently used mounting arrangements consume relatively large amounts of space and volume, and thus lessen circuit density. Further, the relatively large spacing between the chips lowers circuit speed and increases capacitances, thereby causing slower signal propagation through the circuit. These problems have been recognized in the packaging technology, as exemplified by US-A-4,525,921 and US-A-4,764,846. There, chips are stacked at right angles to the substrate and interconnected with edge metalizing circuitry. On one edge or face of the stack, the circuit lines terminate at metal bumps which are used to interconnect the stack directly to a substrate and its corresponding pattern of circuit pads. The chips are thus oriented so that their planes lie normal to the plane of the substrate. The aim of these patents is to achieve a high density in the stack. However, as disclosed, for example, in US-A-4,764,846, to enable the mounting of its individual chips and their carriers to a stack-carrying substrate, the leads from the chips must be extended to a single side, which consumes a relatively large area, thereby militating against the desired aim of high density. It is also possible further to increase density by lapping material from the back side of the wafer prior to its being diced into thinned chips. This thinning is expensive, and adds to the cost of the stack. The bump mounting method of the stack is also costly, and its use in producing reliable connections is uncertain for use in such environments as airborne systems. WO-A-9 100 683 discloses a parallely stacked chip assembly and a method for manufacturing the same, wherein said assembly comprises oversized chips, each chip having a size that is larger than the individual wafer circuit which it incorporates and thus overlapping adjacent circuits on the wafer from which the chip is diced from, wherein said chips comprise rerouted leads on top of passivation, and wherein the stacked arrangement of upper and lower chips are electrically interconnected to a base. IBM Technical Disclosure Bulletin, vol. 32, no. 38, 1989, pages 410-411, "Process for producing lateral chip connector", discloses a parallely stacked chip assembly and a method for manufacturing the same, wherein the stacked arrangement of chips are electrically interconnected to a base. Patent Abstracts of Japan, vol. 9, no. 291 (E-359), 19th November 1985, & JP-A-60 130 854 disclose an assembly of integrated circuit chips assembled parallely on a base and being electrically interconnected to said base. In Proceedings of the 8th IEEE International Electronic Manufacturing Technology Symposium, 1990, N.Y., USA, pages 82-91; C. Val: "The 3D interconnection - an enhanced densification approach with bare chips", there are disclosed parallely stacked chips on a substrate wherein the stacked arrangement of the chips are electrically interconnected to the substrate. In EP-A-0 383 296 there are disclosed parallely stacked chips on a substrate wherein the stacked arrangement of the chips are electrically interconnected to the substrate by ribbon leads. SUMMARY OF THE INVENTION Claims 1, 9 and 11 of the present invention provide for a still higher density over such above described conventional methods by stacking two or more integrated circuit or memory chips on a circuit substrate or printed wiring board in such a manner that the planes of the chips are parallelly, rather than normally, oriented to the substrate or wiring board. The chips can be interconnected as desired, not only from one edge, but also about their entire periphery and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit, that is, each wafer portion which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits. Several advantages are derived from this arrangement. As compared to conventional designs, overall circuit density is further increased by holding the space and volume used to a minimum, by a factor, for example, of about five times over that disclosed in above discussed patent 4,764,846. Because the spacing between the chips is minimized, circuit speed is increased and line impedance and capacitance is correspondingly lowered, thereby permitting higher signal propagation rates through the circuit. The cost of fabrication is lowered and the use of bump mounting is avoided, thus resulting in reliable interconnections. Thermal dissipation is improved. Special hermetic packaging may be avoided, if desired. Other aims and advantages, as well as a more complete understanding of the present invention, will appear from the following explanation of exemplary embodiments and the accompanying drawings thereof. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow diagram of a typical fabrication and assembly procedure for producing products encompassed by the present invention; FIG. 2 is a representation of a typical full wafer which is modified to show a commencing step in the fabrication and assembly procedure of the present invention, using good circuits, designated "G", for incorporation into each chip whose size is greater than the good circuit which it incorporates; FIG. 3 illustrates one embodiment of the present invention comprising a stacked chip assembly before being mounted on a circuit substrate; and Fig. 4 depicts an example not forming part of the invention but being useful for understanding the principles of the invention. FIGS.5-7 depict other embodiments of the present invention, showing alternate construction methods which have been devised to meet special requirements for mounting memory and other chips on a circuit substrate or a printed wiring board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is first made to FIGS. 1 and 2, the former defining a flow diagram of the fabrication and assembly procedure of the present invention, and specifically to the steps designated by indicia 12 and 14. There, indicium 12 represents the method step where a set of dielectric masks is designed to define electrical connections based upon a desired electronic function or functions, and indicium 14 indicates the step in which a wafer 16 (see also FIG. 2) is tested by conventional methods to identify the locations on the wafer of good circuits 18 (also designated in FIG. 2 by indicium "G") and bad circuits 20. It is typical to dot the wafer where bad circuits are found, rather than to mark the good circuits with a "G" designation. In conformance with the present invention, a dicing scheme is defined for wafer 16 (step 22, FIG. 1), and defines locations 24 of oversized chips 25 which are to be diced from the wafer, as shown in FIG. 2. Dicing occurs preferably in two steps. First, the wafer is sawed, e.g., horizontally as shown by dashed lines 27, in such a manner as to avoid slicing through any oversized chip 25, and thus to separate the wafer into rows of chips 25, such as illustrated in FIG. 2. Then, each row is further sawed at a normal, i.e., vertically to the previously made horizontal saw lines 27, to form individual oversized chips 25. In the dicing scheme of step 22 (FIG. 1), wherever possible to maximize use of the wafer material, locations 24 are selected to overlie bad circuits but, if necessary or unavoidable, over good circuits. As an important step in the present invention (step 26 of FIG. 1), the good circuits are masked to protect their input/output pads and wafer 16 is passivated with an impervious, inorganic coating to provide the necessary hermeticity of the chip circuitry. After further appropriate masking, dielectric material is applied to the wafer (step 28 of FIG. 1). This dielectric material may comprise a thin overcoat of organic resin. A pattern of input/output relocation metal is then applied to the wafer to define leads 32, and thus to extend input/output pads 34 of each chip shown in FIG. 2. The performance of this step is noted in step 30 of FIG. 1. At this point, the processing of the wafer varies, depending upon whether the chips, which are to be diced from the wafer comprise lower or topmost chips. This variation in processing, as denoted in FIG. 1, is represented as diverging processing steps for lower chips 36 and topmost chips 38. Those chips 38, which are intended to function as top chips, require two additional processing steps 40 and 42. As depicted in step 40, ribbon bondable metal is applied to peripheral pads 34 (FIG. 2) and, as instructed in step 42, these pads are masked. If desired, wire leads may be used in place of ribbon leads, although the latter is preferred. As required by respective steps 46 and 48 for the lower and the top chips, the wafer is passivated, followed by a dicing of the wafer into lower and topmost chips. As set forth in step 52, for each electric device, the lower chips and the topmost chip are stacked and bonded together into one of the assemblies illustrated in FIGS. 3-7. For only the embodiment disclosed in FIG. 3, the three steps identified in FIG. 1 by indicia 54, 56 and 58 and bracketed by indicium 60 are practiced to produce an assembly 62. In step 58, for example, as it is understood in the art, the term "clear" refers to the step of removing passivation from interconnection pads, if the entire wafer has been passivated in step 46 prior to its being diced, and the term "metalize" refers to the application of suitable metallurgy to facilitate ribbon bonding, if necessary. Here, assembly 62 comprises a top chip 64 and lower chips 66 of equal planar dimensions. Top chip 64 comprises one of chips 25 shown in FIG. 2 which has been processed according to steps 38, 40, 42, 46 and 50 of FIG. 1 so that it includes leads 32' and terminal pads 34'. Lower chips 66, like top chip 64, comprise several of chips 25 of FIG. 2 which have been processed according to steps 36, 46 and 48 of FIG. 1 so that they include leads (not shown, but like leads 32 terminating in pads 34). All of chips 64 and 66, after having been stacked and bonded together as subassembly 62, are ground at their respective edges 68 and on all sides on which connections are to be made, in order to ensure that all pads (e.g., pads 34' of topmost chip 64 and like pads on lower chips 66) are exposed and made flush in the planes of their respective sides, in accordance with step 54 of FIG. 1. Because it is desirable to increase the amount of metal of the exposed pads on lower chips 66, metalization 69 is added to these exposed pads. Interconnects 70 are then formed by conventional metalization techniques between or among selected pads (e.g., pads 34') and metalization 69 and, further, top pads 34' are metalized or cleared, as required by the electrical function, pursuant to steps 56 and 58. Stacked and bonded subassembly 62 is then mounted on and affixed to a base 72, having pads 74, as required by step 76, and ribbon leads 78 are bonded respectively to pads 34' and to pads 74, as represented by step 80, to form an assembly 82. Assembly 82 is then electrically tested according to step 84 to determine if its electrical function operates as intended. Should the test prove successful, assembly 82 is then mounted on and ribbon bonded to a fineline or other appropriate circuit board in accordance with steps 86 and 88. If the test is not successful, assembly 82 is returned for further processing or discarded, as appropriate. Successfully tested constructions are then encapsulated, if needed, as noted by step 90. Assemblies 92, 94, 96 and 98, respectively shown in FIGS. 4-7, assembly 92 not forming part of the invention but being useful for understanding the invention, are also processed in accordance with the steps depicted in FIG. 1, except for steps 54, 56 and 58 thereof. In the method for fabricating assembly 92 of FIG. 4, a substrate circuit 100 is provided with sufficient pads 102 to permit direct connection to the circuit of individual chips 104 which are stacked upon one another. No connections are made between the chips, but the chips can use selected pads in common on the substrate circuit. This technique permits a more conventional assembly to be made using existing processes, and does not require the development of new technologies or interconnecting chips on their vertical edges as shown in FIG. 3. As disclosed with respect to assembly 94 of FIG. 5, in those cases where it is desirable to mount a chip 106 in very close proximity to another chip 108, one expedient method is to mount chip 106 atop chip 108, and to interconnect upper chip 106 directly to lower chip 108 without the necessity of interconnections being made to a substrate as an intermediary circuit path. To accomplish this, it is necessary that upper chip 106 be smaller than lower chip 108, so as to provide room for pads on the lower chip to accommodate interconnecting wires or ribbons 110 from the upper chip. Assembly 94 is then mounted and electrically coupled to a substrate (not shown) by groups of ribbon leads 112. As illustrated in FIG. 6, it is possible also to mount several chips in a stack 114, like chips 104 shown in FIG. 4, where a group of upper chips 116 are smaller than chip 118 below, to permit accommodation of interconnecting pads on the lowest chip for all of the uppermost chips. The lowest chip has pads at its periphery to permit its connection by ribbon leads 120 to a substrate (not shown). Yet another method is shown in FIG. 7 where an upper chip 122 is flip-chip mounted with bump pads 124 to a lower chip 126. Here, the matched coefficient of thermal expansion of silicon on silicon can be used to advantage.

Claims: A method for manufacture of a stacked chip assembly by fabricating, assembling and interconnecting at least two integrated circuit or memory chips in a stacked upper (38; 64; 104; 106; 116) and lower (36; 66; 104; 108; 118) chip arrangement (62) to a circuit substrate or printed wiring board support (100) in such a manner that the planes of the chips are parallelly oriented to the substrate or wiring board, comprising the steps of: testing (14) a full wafer (16) for determining operable (18) and inoperable (20) circuits therein; providing (22) a dicing scheme for defining oversized chips (25) in which each wafer portion (24) which is selected to be formed into a chip (25) has a size that is larger than the individual circuit (18) which it incorporates, thus overlapping adjacent circuits (18; 20), and for positioning individual ones of said chips on selected ones of the operable circuits, thus overlapping said chips onto ones of the circuits adjacent the selected circuits, in preparation for dicing the wafer into the upper (38; 64; 104; 106; 116) and lower (36; 66; 104; 108; 118) chips; applying (28) a dielectric layer mask to the wafer in accordance with circuit designs defining the constituent parts of the stacked chip assembly; applying (30) input/output relocation metal to portions of the wafer exposed through the mask; for the top chip (38; 64; 104; 106; 116), applying (40) ribbon bondable metal to peripheral pads (34; 34') on the wafer, and masking (42) the pads; passivating (46) the wafer; dicing (48) the wafer into the upper (38; 64; 104; 106; 116) and lower (36; 66; 104; 108; 118) chips; assembling and bonding (52) the chips, one atop and in contact with an adjacent chip, into a layered stack (62; 64, 66; 104; 106, 108; 116, 118) of chips; mounting (76) the stack (62; 64, 66; 104; 106, 108; 116, 118) on a base (72); electrically bonding (80) the stack to the base by ribbon leads; electrically testing (84) the stacked and bonded chips; mounting (86) the stacked assembly (82; 92; 94; 96) to the support; electrically bonding (88) the stacked assembly (82; 92; 94; 96) to the support by ribbon leads ; and encapsulating (90) the stacked and bonded chips (62; 64, 66; 104; 106, 108; 116, 118), base (72) and support (100) assembly. A method according to claim 1 further including the steps (60), intermediate said steps of assembling and bonding (52) the chips (36; 38; 64; 66; 104; 106; 108; 116; 118) into the stack (62; 64, 66; 104; 106, 108; 116, 118) and of mounting (76) the stack (62; 64, 66; 104; 106, 108; 116, 118) on the base (72), of: grinding (54) edges (68) of the chips to expose electrical contact points (34); metallizing (56) the edges at selected ones of the contact points (34); metallizing (58) selected ones of the pads (34') on the uppermost chip (38; 64; 104; 106; 116); and performing said stack to base electrically bonding step (80) by bonding ribbon leads (78; 112; 120) from the metallized edges and pads to designated contact areas on the base (72). A method according to claim 1 further comprising the step of positioning contacts (34; 34') fully about the periphery of each of the chips (36; 38; 64; 66; 104; 106; 108; 116; 118). A method according to claim 1 in which the stacked chips (62; 64, 66; 104) have equal dimensions, further comprising the steps of electrically interconnecting the chips (64, 66; 104) at their edges and electrically interconnecting the uppermost chip (64; 104) and the base (72). A method according to claim 1 in which the stacked chips (62; 64, 66; 104) have equal dimensions, further comprising the step of electrically interconnecting the chips (64, 66; 104) to the base (72). A method according to claim 1 in which the stacked chips (106, 108; 116, 118) have unequal dimensions, further comprising the steps of stacking at least one of those chips (106; 116) having lesser dimensions atop at least another of those chips (108; 118) having relatively larger dimensions, and electrically interconnecting the chips successively to the lower chip and therefrom to the base. A method according to claim 1 further comprising the step of forming interconnections (70; 110) among the chips (36; 38; 64; 66; 104; 106; 108; 116; 118) prior to said chip to base interconnecting step (80). A method according to claim 7 wherein said chip to base interconnecting step (80) comprises the step of forming connections (78) from an uppermost one (64; 104) of the chips to the base (72). An assembly of chips comprising at least two integrated circuit chips stacked one (106; 114; 116) atop the other (108; 116; 118), assembled parallelly on a circuit substrate (100) and electrically interconnected to said substrate, each of said chips being of a size such that it comprises an operable individual circuit (18) and adjacent circuits (18; 20) to said operable one, characterized in that said chips (106; 108; 114; 116; 118) are interconnected by ribbon leads (112; 120) to said circuit substrate (100), and said stacked chips (106; 108; 114; 116; 118) have unequal dimensions, with at least one (106; 116) of those chips having lesser dimensions (106; 114; 116) being stacked atop at least another (108; 118) of those chips having relatively larger dimensions (108; 118), and further comprising ribbon leads between successive ones of said upper chips to said lower chips and thence to said substrate. An assembly according to claim 9 further comprising ribbon leads extending from an uppermost one (106; 114) of said chips to said circuit substrate (100). A method for manufacture of a stacked chip assembly by fabricating, assembling and interconnecting two integrated circuit or memory chips in a stacked upper (38; 122) and lower (36; 126) chip arrangement to a circuit substrate (100) or printed wiring board support in such a manner that the planes of the chips are parallelly oriented to the substrate or wiring board, comprising the steps of: testing (14) a full wafer (16) for determining operable (18) and inoperable (20) circuits therein; providing (22) a dicing scheme for defining oversized chips (25) in which each wafer portion (24) which is selected to be formed into a chip (25) has a size that is larger than the individual circuit (18) which it incorporates, thus overlapping adjacent circuits (18; 20), and for positioning individual ones of said chips on selected ones of the operable circuits, thus overlapping said chips onto ones of the circuits adjacent the selected circuits, in preparation for dicing the wafer into the upper (38; 122) and lower (36; 126) chips; applying (28) a dielectric layer mask to the wafer in accordance with circuit designs defining the constituent parts of the stacked chip assembly; applying (30) input/output relocation metal to portions of the wafer exposed through the mask; for the chip (126) to be the second chip from the top of a stack of chips, applying (40) ribbon bondable metal to peripheral pads (34; 34') on the wafer, and masking (42) the pads; passivating (46) the wafer; dicing (48) the wafer into the upper (38; 122) and lower (36; 126) chips; said upper chips being smaller than said lower chips; assembling and bonding (52) the chips, one atop and in contact with an adjacent chip, into a layered stack (122, 126) of chips, the topmost chip (122) of the stack of chips being flip-chip mounted with bump pads (124) to the chip (126) second from the top of the stack; mounting (76) the stack (122, 126) on a base (72); electrically bonding (80) the stack to the base by ribbon leads; electrically testing (84) the stacked and bonded chips; mounting (86) the stacked assembly (98) to the support; electrically bonding (88) the stacked assembly (98) to the support by ribbon leads; and encapsulating (90) the stacked and bonded chips (122, 126), base (72) and support (100) assembly.

Inventors: COCHRAN RICHARD K, GATES LOUIS E JR, COCHRAN, RICHARD K., GATES, LOUIS E. JR.
Applicants: RAYTHEON CO, RAYTHEON COMPANY
Application year: 1992
Main classification: H01L25
IPC codes: H01L25, H01L23, H01L27, H01L21