Optoelectronic integrated circuit

Abstract: By this invention an optoelectronic integrated circuit comprising a plurality of channels each including an optical receiving device (PD 1 ; ... PD n ) for converting a received optical signal to an electrical signal and an amplifier for amplifying an output signal of the optical receiving device (PD 1 ; ... PD n ) is disclosed, wherein the channels are integrated on the same semiconductor substrate, the preamplifier at least includes an amplification stage (Q 11 , R 12 ; ... Q n1 , R n2 ) for amplifying an output signal of the optical receiving device. An emitter follower stage is for lowering an output impedance of the channels. A first electric power source wiring for supplying an electric power source (V C2 ) to the respective amplification stages (Q 11 , R 12 ; ... Q n1 , R n2 ) is electrically separated from a second electric power source wiring for supplying an electric power (V C1 ) on the other stages including the emitter follower (Q 13 , R 14 ; ... Q n3 , R n4 ).

Description: Background of the Invention This invention relates to an optoelectronic integrated circuit device for use in optical receiving units or others of receivers for the optical fiber communication. A conventional optoelectronic integrated circuit device (hereinafter called OEIC array) for use in optical receiving units or others for the optical fiber communication is disclosed in " High-speed eight-channel optoelectronic integrated receiver arrays comprising GaInAs PIN PDs and AlInAs/GaInAs HEMTs", Optical Fiber Communication Conference, Tuesday, February 19, 1991, Lecture No. Tub2. Its schematic circuit diagram is shown in FIG. 1. This OEIC array 40 is provided by monolithically integrated eight channels of an optical receiving circuit. Each channel includes photodiodes PD (PD 1 ∼ PD 8 ), and AMPs provided by resistors, high electron mobility transistors or others for converting a received optical signal to an electric signal. In such conventional OEIC array 40, the electric power source nodes (contacts) 41 of the respective preamplifiers AMP are connected to one another and have the same potential. Because of such circuitry, it is a problem that crosstalks, i.e., leakage of a signal inputted to one channel to other channels, has a level as high as about -30 dB. A cause for such crosstalks is considered to be as follows. That is, condensers C 1 and C 2 are inserted in circuits inside and outside the OEIC array 40 for the reduction of an impedance of the AC current component, and all the electric power source circuits are grounded through the condensers C 1 , C 2 . On the other hand, an electric source power supply terminal 42 is usually supplied with a current from an electric power source 43 through a limited length of an electric power source wiring 44. This electric power source wiring 44 has an inductance L as a distributed constant. This inductance L and the condenser C 2 resonate at a specific frequency, and at this frequency an impedance between the electric source power supply terminal 42 and the ground becomes infinite. When a signal is inputted to one channel, an output voltage corresponding to the signal is generated at the output terminal 45, and a signal current is supplied to a load 46. This signal current is supplied by the electric power source 43. At the time of the supply of the signal current from the electric power source 43, a voltage equal to a product of the impedance between the electric source power supply terminal 42 and the ground, and a value of a current flowing there is generated in the electric source power supply terminal 42. Accordingly, at the above-described resonance frequency the impedance between the electric power source supply terminal 42 and the ground is infinite, and a very large voltage deflection corresponding to the inputted signal current occurs. Generally the preamplifier AMP has a deflected output voltage corresponding to a deflection of an electric power source voltage. Consequently at this resonance frequency, an electric signal inputted to one channel causes a large source voltage deflection and causes deflections of output voltages of all the other channels through the common electric power source wiring. This is a cause for the occurrence of crosstalks. A circuit corresponding to the OEIC array 40 in FIG. 1 is shown in FIG. 2. In this OEIC array, eight channels are monolithically integrated. The first channel of the eight channels includes a PIN photodiode PD 1 , resistors R 11 ∼ R 14 , and high electron mobility transistors (HEMTs) Q 11 ∼ Q 15 . The transistor Q 11 and the resistor R 12 constitute an amplification stage. The transistors Q 12 ∼ Q 15 , and the resistors R 13 , R 14 constitute a two-stage source follower. In FIG. 2 the third to the sixth channels have the same structure as the first channel, and they are not shown. Another example of the conventional OEIC arrays of this kind is disclosed in " Monolithic Integration of an InP/InGaAs Four-Channel Transimpedance Optical Receiver Array ", Electronics Letters, vol. 26, pp. 1833 ∼ 1834, October 1990. FIG. 3 schematically shows its circuit diagram. In this OEIC array, four channels constituting the optical receiver are monolithically integrated. A first one of the four channels comprises a PIN photodiode PD 1 , and an input resistor R f1 , junction transistors Q 11 ∼ Q 19 , and a level shift diode LSD 1 . The transistors Q 11 ∼ Q 13 constitute an amplifying stage for amplifying an electric signal photo-electrically converted by the photodiode PD 1 . The transistors Q 14 , Q 15 , and the diode LSD 1 constitute a level shifting stage for shifting a d.c. voltage of an amplified signal outputted by the amplifying stage. The transistors Q 16 ∼ Q 19 constitute a source follower stage for securing a fan out of an optical receiver output 0/P 1 . The second, the third and the fourth channels have the same circuitry as the first channel, and the second and the third channels are not shown. In a conventional OEIC array of FIG. 3, the amplification stages and the level shift stages of the respective preamplifiers are supplied with an electric source power V DD1 through an electric power source wiring which is common to the respective channels. The source follower stages are supplied with an electric power source V DD2 through a different electric power source wiring which is common to the respective channels. In a conventional OEIC array of FIG. 2, all the stages of the respective preamplifiers are supplied with an electric source power V DD through an electric power source wiring which is common to the respective channels. In the conventional OEIC arrays of these structures, large modulated currents are caused by input signals in the level shift stages and the source follower stages as will be described below. Consequently in the electric power sources for these stages large source voltage deflections are caused by the modulated currents. Such source voltage deflections affect the common electric power sources of the respective channels connected to these stages. That is, a source voltage deflection caused by an input signal in one channel affects the power sources of the other channels, and causes voltage deflections in the output terminals of the other channels. Consequently crosstalks take place among the channels. As a result, the problem that the crosstalks deteriorate minimum sensitivities of the optical receiving circuits of the respective channels occurs. Major causes for such crosstalks are as follows. With respect to the OEIC array of FIG. 2 using HEMTs, explanation will be made as follows with reference to FIG. 4. Here it is assumed, for example, that an optical signal inputted to the first channel is converted to an electrical signal by a photodiode PD 1 , and a modulated current ΔI ml is caused by an input signal when the electric signal is amplified by the preamplifier consisting of an amplification stage and a follower stage. 90% of a modulated current ΔI ml is generated in the source follower state. This modulated current ΔI ml flows through the wiring of a resistor R p to thereby generate a voltage deflection ΔV D . This wiring resistor R p is equivalently shown at the electric power source terminal V DD for supplying an electric source power commonly to the respective preamplifiers. The above-described modulated current ΔI ml flows through this wiring resistor and generates a voltage deflection ΔV D (=ΔI ml xR p ) . This voltage deflection ΔV D is source voltage deflections of the preamplifiers of the other channels as it is. Generally when a source voltage is deflected, an output voltage of the preamplifier is deflected. Accordingly, when an optical signal is inputted to one channel, source voltages of the preamplifiers of the other channels are deflected, and the deflected source voltages deflect output voltage of the other channels with a result of occurrences of crosstalks. In the OEIC array of FIG. 3 using junction transistors, modulated currents are generated due to input signals. 90% of a modulated current is generated in the level shift stage or the source follower stage. The amplification stage and the level shift stage of each preamplifier are supplied with a source voltage V DD1 through the common electric power source wiring. Consequently, when a modulated current occurs in the level shift stage of one preamplifier, a voltage deflection ΔV D is generated in the common electric power source wiring as described above. This voltage deflection ΔV D deflects source voltages of the preamplifiers of the other channels through the common power source wiring, and deflects output voltages. That is, an optical signal inputted to one channel deflects output voltages of the other channels, and crosstalks take place. The reason for output voltages being deflected when source voltages of the preamplifiers are deflected is as follows. That is, as shown in FIG. 4, each preamplifier includes an amplification stage, a level shift stage, a source follower stage. Output voltages of the level shift stage and of the source follower stage are not substantially deflected. But an output voltage of the amplification stage is deflected in a range from 50% to 100% and is sensitive to the voltage deflections. Accordingly, when a voltage deflection due to a source voltage deflection takes place in an output of the amplifier of one channel, this voltage deflection directly affects the source follower stages and the level shift stages. That is, when a source voltage of a preamplifier is deflected, output voltages are adversely deflected. Because of crosstalks due to this cause, as described above, a minimum receiver sensitivity of the optical receiving circuit of each channel is deteriorated. The above-described modulated current ΔI ml is bypassed to the ground by a condenser monolithically integrated on the same semiconductor chip. But the bypass condenser integrated on the semiconductor chip can only have a limited capacity, and it is impossible to give the condenser a sufficiently large capacity. Accordingly all of a generated modulated current cannot be bypassed, and only a part of the current can be bypassed. Consequently a residual modulated current which has not been able to be removed is a cause for the occurrence of the above-described crosstalks. On the other hand, it makes a size of the semiconductor chip impractically extremely large to increase a capacity of the condenser so as to remove all of a modulated current. Summary of the Invention An object of this invention is to provide an optoelectronic integrated circuit device which can decrease such crosstalks among channels, or can eliminate such crosstalks among channels. This invention according to a first aspect is an optoelectronic integrated circuit comprising a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an amplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, the preamplifier at least including an amplification stage for amplifying an output signal of the optical receiving device, and an emitter follower stage for lowering an output impedance of the channels, and a first electric power source wiring for supplying an electric source power to the respective amplification stages being electrically separated from a second electric power source wiring for supplying an electric source power to other stages including the emitter follower. According to this aspect of the invention, the electric source power supply to the amplification stages of the respective preamplifiers, which are sensitive to the voltage deflection is made independently from the electric source power supply to stages of the respective preamplifiers other than the amplification stages, such as the emitter followers. Consequently if a modulated current is generated, due to an optical signal inputted to one channel, in the emitter follower stage or others thereof, and a voltage deflection takes place in the electric power source for the emitter followers and so on, power source voltages of the amplification stages of the other channels, which are sensitive to the voltage deflection, are not deflected. Consequently output voltages of the other channels are not deflected even if an optical signal is inputted to one channel, and no crosstalks occur. This invention according to a second aspect is an optoelectronic integrated circuit comprising a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an preamplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, the amplifier at least including an amplification stage for amplifying an output signal of the optical receiving device of the preamplifier, and a source follower stage for lowering an output impedance of the channels, and a first electric power source wiring for supplying an electric source power to the respective amplification stages being electrically separated from a second electric power source wiring for supplying an electric source power to other stages including the source follower stage. According to this aspect of the invention, the electric source power supply to the amplification stages of the respective amplifiers, which are sensitive to the voltage deflection, is made independently from the electric source power supply to stages of the respective amplifiers other than the amplification stages, such as the source followers. Consequently power source voltages of the amplification stages of the other channels, which are sensitive to the voltage deflection, are not deflected due to the same principle as in the above-described second structure. This invention according to a third aspect is an optoelectronic integrated circuit comprising a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an amplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, the respective amplifiers being supplied with an electric source power through electric power source terminals provided independent from each other for the respective channels. According to this aspect of the invention, the respective channels have their own electric power source terminals separated from each other for operating the amplifiers. Each amplifier is supplied with an electric source power independently. Consequently, it does not happen that an electric source power deflection in one channel causes source power deflections in the other channels, resultantly causing crosstalks. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only. Brief Description of the Drawings FIG. 1 is a general circuit diagram of the conventional optoelectronic integrated circuit array; FIG. 2 is a schematic circuit diagram of a first conventional OEIC array; FIG. 3 is a schematic circuit diagram of a second conventional OEIC array; FIG. 4 is a circuit diagram explaining a principle of the occurrence of crosstalks in the second conventional OEIC array; FIG. 9 is a circuit diagram of the OEIC array according to a first embodiment of this invention: FIG. 10 is a circuit diagram of the OEIC array according to a second embodiment of this invention; FIG. 11 is a circuit diagram of the OEIC array according to a third embodiment of this invention; and FIG. 12 is a circuit diagram of one modification of the embodiment of FIG. 11. Description of the Preferred Embodiments Embodiments of this invention will be explained with reference to the drawings attached hereto. FIG. 9 is a circuit diagram of the OEIC array according to a first embodiment of this invention. The OEIC array according to this embodiment is not specifically limited in a number of channels but usually have 4 ∼ 12 channels depending on applications. In FIG. 9, the first channel and a final n-th channel (n=4∼12) are shown, and the second to the (n-1)-th channels are not shown. These channels are monolithically integrated on one and the same semiconductor chip. In the 0.8 µm-wavelength band optical communication, this semiconductor substrate is formed of GaAs. This substrate is formed of InP for the 1.3 µm- and 1.55 µm-wavelength band optical communication. The respective channels have the same structure and circuit operation as the first channel, whose structure will be explained below. The first channel comprises a photodiode PD 1 , resistors R 11 ∼ R 14 , and bipolar transistors Q 11 ∼ Q 13 . The photodiode PD 1 is an MSM (metal semiconductor metal) or a PIN photodiode. The bipolar transistors Q 11 ∼ Q 13 are hetero junction bipolar transistors (HBTs) of InP/GaInAs hetero junction or AlGaAs/GaAs hetero junction. The combination of a PIN photodiode, and HBTs of InP/GaInAs formed on an InP semiconductor substrate is the best in terms of the operational performance. The photodiode PD 1 and a resistor R 11 constitute an optical detection stage. The transistor Q 11 , and the resistor R 12 constitute an amplification stage for amplifying an input signal detected by the optical detection stage. The transistor Q 12 , and the resistor R 13 constitute a level shift stage, and the transistor Q 13 and transistor R 14 constitute an emitter follower stage. In such structure, an optical signal detected by the photodiode PD 1 is converted to a photocurrent, and this photocurrent is converted to a voltage signal by the resistor R 11 . This voltage signal is supplied to the base of the transistor Q 11 , whose load is the resistor R 12 , to be amplified by a set times here. The amplified input signal has a direct current level shifted by a next level shift stage. Its shift amount is substantially determined by a resistance value of the resistor R 13 . Finally an output impedance of the amplifier is decreased by the emitter follower, and a fan out of a receiver output signal O/P 1 is secured. In this embodiment, the level shift stages and the emitter follower stages of the respective amplifiers except the amplification stages thereof are commonly supplied with an electric source power V C1 , and the amplification stages of the respective amplifiers are commonly supplied with an electric source power V C2 . That is, the electric power source wiring for supplying the source power V C2 to the amplification stages is electrically separated from the electric power source wiring for supplying the source power V C1 to the other stages other than the amplification stages. Accordingly the electric source power supply to the amplification stages of the respective amplifiers, which are sensitive to voltage deflections is made independently from the electric source power supply to the level shift stages and the emitter follower stages of the respective amplifiers. Consequently an optical signal inputted to one channel does not deflect output voltages of the other channels. That is, even when the above-described modulated current ΔI m is generated in the level shift stage or the emitter follower stage of one amplifier, a voltage deflection ΔV D caused by this modulated current does not affect the amplification stages of the other amplifiers. Consequently the electric source power supply to the amplification stages of the respective amplifiers is stable, and noise signal components are not unintentionally increased on the respective amplification stages. Correct optical communication can be performed. FIG. 10 is a circuit diagram of the OEIC array according to a second embodiment of this invention. Different from the second embodiment of FIG. 9, the OEIC array according to this embodiment uses FET transistors. The first channel comprises a photodiode PD 1 , resistors R 11 ∼ R 12 , field effect transistors 5FETs Q 11 ∼ Q 15 , and level shift diodes D 11 ∼ D 13 . The photodiode PD 1 is an MSM or a PIN photodiode. The FETs Q 11 ∼ Q 15 are junction FETs, HEMTs, MOSFETs, MESFETs or others. The combination of a PIN photodiode, and HEMTs formed on an InP semiconductor substrate is the best in terms of the operational performance. The photodiode PD 1 and a resistor R 11 constitute an optical detection stage. The FET Q 11 , and the resistor R 12 constitute an amplification stage for amplifying an input signal detected by the optical detection stage. The FETs Q 12 , Q 13 , and the diodes D 11 ∼ D 13 constitute a level shift stage, and the FETs Q 14 , Q 15 constitute a source follower stage. In this embodiment, the level shift stages and the source follower stages of the respective amplifiers except the amplification stages thereof are commonly supplied with an electric source power V D1 , and the amplification stages of the respective amplifiers are commonly supplied with an electric source power V D2 . Accordingly the electric source power supply to the amplification stages of the respective amplifiers, which are sensitive to voltage deflections is made independently from the electric source power supply to the level shift stages and the source follower stages of the respective amplifiers. Consequently, even when the above-described modulated current ΔI m is generated in the level shift stage or the source follower stage of one amplifier, a voltage deflection ΔV D caused by this modulated current does not affect the amplification stages of the other amplifiers. The circuits according to the first and the second embodiments can suppress the crosstalk from about -30 dB of the conventional structures to below -40 dB. In the parallel optical fiber communication, the deterioration of a minimum receiver sensitivity due to crosstalks can be decreased. As described above, according to the first and the second embodiments, the electric source power supply to the amplification stages of the respective amplifiers, which are sensitive to voltage deflections, is made independently from the electric source power supply to the other stages of the respective amplifiers other than the amplification stages. Consequently an optical signal inputted to one channel does not cause the deflection of output voltages of the other channels, and no crosstalk does not occur. Thus, the OEIC array according to this invention can effectively prevent the deterioration of a minimum receiver sensitivity due to occurrences of crosstalks. FIG. 11 is a circuit diagram of the OEIC array according to a third embodiment of this invention. In FIG. 11, the first channel and a final n-th channel (n=4∼12) are shown, and the second to the (n-1)th channels are not shown. These channels are monolithically integrated on one and the same semiconductor chip. In the 0.8 µm-wavelength band optical communication, this semiconductor substrate is formed of GaAs. This substrate is formed of InP for the 1.3 µm- and 1.55 µm-wavelength band optical communication. The first channel comprises a photodiode PD 1 , resistors R 11 , R 12 , transistors Q 11 ∼ Q 15 , and level shift diodes D 11 ∼ D 13 . The photodiode PD 1 is an MSM or a PIN photodiode. The transistors Q 11 ∼ Q 15 are junction field effect transistors (FETs), HEMTs, MISFETs, MESFETs or others. It is the best combination in the operational performance to form a PIN photodiode and HEMTs on an InP semiconductor substrate. The photodiode PD 1 and a resistor R 11 constitute an optical detection stage. The transistor Q 11 , and the resistor R 12 constitute an amplification stage for amplifying an input signal detected by the optical detection stage. The transistors Q 12 , Q 13 , and the diodes D 11 ∼ D 13 constitute a level shift stage, and the transistors Q 14 , Q 15 constitute a source follower stage. In this embodiment, each channel, which comprises an amplifying stage, a level shift stage, and source follower stage, is provided with electric source terminals. That is, the first channel is provided with electric power source terminals V D1 , V Sl , and the n-th channel is provided with electric power source terminals V Dn , V Sn . Accordingly, in the case that the OEIC array according to this embodiment in which the respective amplifiers are not connected to one another on the same chip is mounted on a hybrid substrate, bypass condensers having a sufficiently large capacity can be connected to the respective amplifiers. That is, power source wirings are led out from the power source terminals V Dn , V Sn to connect on the hybrid substrate each amplifier to the associated large-capacity bypass condenser. The source wirings of each channel are connected to a common electric power source by way of the associated condenser. In this wiring arrangement, each amplifier is supplied with an electric source power through the associated large-capacity bypass condenser. Consequently, in a case that the above-described modulated current ΔI m is generated in one channel, this modulated current is bypassed by the associated large-capacity condenser with the amplifier. Accordingly noises generated in one channel do not affect the other channels, and substantially no crosstalks occur among the channels. This embodiment can suppress the crosstalk of conventionally about -30 dB to below-40dB. In the parallel optical fiber communication, the deterioration of the minimum receiver sensitivity can be reduced. In a case that it is not a hybrid substrate that the OEIC array according to this invention is mounted on, it is possible to separately supply an electric source power to the respective amplifiers. Consequently, it does not happen in the OEIC array according to this invention that, as does in the conventional OEICs, a modulated current generated in the amplifier of one channel extends to the other channels through the power source wiring which is common with the respective channels. The supply of a source power to the respective amplifiers simply through their associated power source terminals V Dn , V Sn can sufficiently reduce crosstalks among the channels. In this case as well the same advantageous effect as in the above-described embodiment can be produced, but a generated modulated current cannot be sufficiently bypassed. FIG. 12 shows the same circuit as that of FIG. 11 except that the FET transistors of latter are replaced by hetero junction bipolar transistors. A photodiode PD1 and a resistor R 11 constitute a optical detection stage; a transistor Q 11 and a resistor R 12 constitute an amplification stage; a transistor Q 12 and a resistor R 13 constitute a level shift stage; and a transistor Q 14 and a resistor R 14 constitute an emitter follower stage. As described above, according to the fourth embodiment, electric power source terminals for operating each amplifier are provided on its associated channel. Consequently an electric source power can be separately supplied to the respective amplifiers. Thus an OEIC array which has succeeded in effectively minimizing the deterioration of the receiver sensitivity caused by crosstalks among the respective channels can be provided. From the invention thus described, it will be obvious that the invention may be varied in many ways.

Claims: An optoelectronic integrated circuit comprising: a plurality of channels each including an optical receiving device (PD 1 ; ... PD n ) for converting a received optical signal to an electric signal, and an amplifier (Q 11 - Q 15 , R 12 , D 11 - D 13 ; ... Q n1 - Q n5 , R n2 , D n1 - D n3 ; or Q 11 , Q 12 , Q 14 , R 12 - R 14 ; ... Q n1 , Q n2 , Q n4 , R n2 - R n4 ) for amplifying an output signal of the optical receiving device; the channels being integrated on the same semiconductor substrate; characterized in that the respective amplifiers are supplied with an electric source power through electric power source terminals (V D1 , V S1 ; ... V Dn , V Sn ; or V C1 , V Θ1 ; ... V Cn , V Θn ) provided independent from each other for the respective channels. An optoelectronic integrated circuit according to claim 1, wherein each of the amplifiers includes an amplification stage (Q 11 , R 12 ; ... Q n1 , R n2 ) for amplifying an output of the optical receiving device (PD 1 ; ... PD n ), a level shift stage (Q 12 , Q 13 , D 11 - D 13 ; ... Q n2 , Q n3 , D n1 - D n3 ) for shifting a direct current level of an output of the amplification stage, and a source follower stage (Q 14 , Q 15 ; ... Q n4 , Q n5 ) for lowering an output impedance of the amplifier. An optoelectronic integrated circuit according to claim 1, wherein each of the amplifiers includes an amplification stage (Q 11 , R 12 ; ... Q n1 , R n2 ) for amplifying an output of the optical receiving device, a level shift stage (Q 12 , R 13 ; ... Q n2 , R n3 ) for shifting a direct current level of an output of the amplification stage, and an emitter follower stage (Q 14 , R 14 ; ... Q n4 , R n4 ) for lowering an output impedance of the amplifier. An optoelectronic integrated circuit according to any of claims 1 to 3, wherein the respective electric power source terminals (V D1 , V S1 ; ... V Dn , V Sn ; or V C1 , V Θ1 ; ... V Cn , V Θn ) are provided on the semiconductor substrate, and the respective electric power source terminals are connected by a wiring to terminals of electric power sources provided independent from each other for the respective channels. An optoelectronic integrated circuit according to claim 1, wherein the semiconductor substrate is an InP substrate; the optical receiving device is a PIN photodiode; and the amplifier includes high electron mobility transistors.

Inventors: SASAKI GORO, SASAKI, GORO, Sasaki, Goro, Yokohama Works of
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES, LIMITED
Application year: 1992
Main classification: H04B10
IPC codes: H04B10