Automatic speed detection for full-duplex modems

Abstract: Method and apparatus for determining occurrence of an S1 modem identification sequence is disclosed. An S1 sequence is found to exist when the sum of conjugate complex multiplication of signal sample amplitudes taken at an interval T/2 result in a negative scalar value for an arbitrary number of sequential occurrences. Complex samples taken from incoming baseband waveform at twice the modulation rate are interleaved in pairs of two with two even numbered samples and two odd numbered samples being considered separately by first performing complex multiplication followed by scalar multiplication of an output of the complex multiplication and an output of the previous complex multiplication delayed by one modulation interval T. The separate results from the sets of pairs of signal samples are summed to form a scalar whose value when consistently less than 0 indicates the presence of an S1 modem identification sequence in accordance with the CCITT S1 recommendation.

Description: Field of the Invention This invention relates generally to modems, data sets, line adapters and the like where analog modulated waveforms are to be transmitted from a sender to a receiver. More particularly, it relates specifically to automode sensing of modem speeds in accordance with the recommended CCITT modem identification signal sequence called "S1". Prior Art Automode sensing is employed in modems built according to the CCITT V.22 and V.22bis standards to enable the modems to sense and properly distinguish between the V.22, 1200bps modems and the V.22bis which may be 1200 or 2400 bps modems. The distinction is based upon sending and receiving during the start-up phase of a short, modulated signal sequence having a standard pattern called the "S1" sequence. The S1 sequence, when received and recognized by an answering V.22bis modem, indicates that the calling mode has V.22bis capabilities i.e., it is capable of sending and receiving at 2400 bit per second. The answering modem receiving the S1 sequence acknowledges the reception of an S1 sequence by also sending such a sequence; when such a sequence is properly received and detected by the calling modem, both modems can declare a V.22bis connection to exist and further start-up sequences may be exchanged to achieve full duplex transmission at the common data rate of 2400 bits per second. Failure of either modem in its mutual exchange of S1 sequences leads to an assumption by both that at least one of the modems is a V.22 capable modem, in which case, the start-up sequences proceed to achieve full duplex transmission at the common data rate of 1200 bps. If the optimum sampling phase and carrier phase are known in advance, an S1 sequence can quickly be recognized by classical symbol detection methods in the receiving modems. Observance of the S1 sequence based upon the detection of alternating signs in the imaginary part of the complex signals x k is the distinctive feature acknowledged in the prior art as recognition of the reception of an S1 sequence. This technique, however, requires careful adjustment of the sampling phase τ and the carrier phase , respectively. Such values are normally not conveniently available at startup because the calling modem begins transmission of its S1 sequence abruptly and without a preamble. The receiving or answering modem must then acquire proper sample phase timing τand carrier phase synchronization  very quickly if the S1 sequence is to be recognized by the classical symbol detection method. This proves to be very difficult in practice and often results in marginal detection performance. This in turn leads to a significant number of potential 2400 bps connections being missed. The same situation exists for calling modems which cannot establish timing phase and carrier phase synchronization from the startup signals received from the answering modem prior to an S1 sequence. Objects of the Invention In light of the foregoing known difficulties with the prior art, it is therefore an object of this invention to provide an improved S1 sequence detection method which does not require synchronization of the sending and receiving modem's sampling phases and carrier phases. It is a further object of this invention to provide a new and improved S1 sequence detection method for use in full duplex modems. Summary of Invention The S1 sequence in the CCITT V.22bis modem standard consists of a four phase shift keyed signal having alternating phase shifts of plus or minus 90 degrees transmitted at the modulation rate of 1 divided by T. In accordance with the present invention, the S1 complex sequence signal is amplitude sampled at twice per modulation interval T to obtain four complex values x k equal to x 2n-0 , x 2n-1 , x 2n-2 and x 2n-3 , respectively. The samples are interleaved with the two even numbered samples being considered together and the two odd numbered samples being considered together, by performing a complex multiplication of the paired samples followed by scalar multiplication between the imaginary part from the complex multiplied samples and the time delayed result of the previous similar complex multiplication where, the time delay is equal to 1 modulation interval T. The same operations are conducted for the two odd numbered samples and the result of its scalar multiplication is added with the result of the first scalar multiplication in a summing operation. It has been discovered that when the sign of the resultant sum is negative i.e. where the sum is less than zero continuously for successive sets of samples, that an S1 sequence exists. In order to verify the occurrence of the S1 sequence, an arbitrary count of sequential findings of the value of the sum being less than zero is made. When the count validity threshold is reached, the S1 signal is viewed as valid and detected. Counting and the summing operations continue until a non-negative value for the sum is found, thereby detecting the end of the S1 sequence. Brief Description of Drawings The foregoing and yet other objects that have not been specifically enumerated are met in a preferred embodiment of the invention in which Figure 1 illustrates the four phase shift keyed symbol transmissions base in a polar coordinate diagram illustrating symbols ABC and D. Figure 2 illustrates a modulated complex base band S1 sequence as it would be seen over a continuous time on an oscilloscope at a receiver receiving an S1 baseband sequence with an arbitrary phase angle phi. Figure 3a illustrates the results of sampling an S1 sequence at a receiver to measure instantaneous amplitudes at four sampling times at T/2 intervals relative to an arbitrary clock, τ, and carrier phases  in the complex number domain to obtain x 2n-0 , x 2n-1 , X 2n-2 , x 2n-3 sample sequences. Figure 3b illustrates the result of similar sampling in the complex domain by complex baseband sampling known in the art and at a different arbitrary clock phase τ when both Figures 3a and 3b have the same arbitrary carrier phase . Figure 4 illustrates a preferred embodiment of the circuitry for combining complex samples and calculating the results which lead to detection of an S1 sequence in accordance with the invention. Figure 5 illustrates schematically the timing and placement of the complex samples in the real and imaginary domains as utilized in the preferred embodiment of the invention. Figure 6 illustrates schematically the complex sampler used to provide the sample stream for use in the preferred embodiment of Figure 4. Detailed Description of Preferred Embodiment This invention eliminates the prior requirement for synchronization of the carrier phase and sampling phase between sending and receiving modems prior to accurate detection of an S1 identification signal sequence. It has been found that certain mathematical combinations of the complex signal samples lead to a correlation that uniquely identifies an S1 sequence if the signal samples are spaced at the modulation interval, T. It has been found that two sets of T-spaced, "interlaced" (that is time alternated samples as shall appear herein) samples may be used to form sample sets which are processed at each modulation interval to yield imaginary components. The imaginary components are then combined to form a sum or metric which is invariant to either sampling or carrier phase differences. Further filtering of this metric, via appropriate low pass filters combined with counting of sequential occurrences of a sum correlation in comparison with a threshold count for detection, completes the process of S1 signal detection. In the absence of transmission distortion and noise, the CCITT S1 signal set when complex sampled at a rate T/2 yields complex sampled signal samples of the form: In equation 1, τ and  may be arbitrary sampling timing phases and carrier phases, respectively. To detect an S1 sequence in accordance with the invention, the following algorithms must be performed: u n = v cos,n v cos,n -1 + v sin,n v sin,n -1 = [-1], The values given in the brackets on the right-hand sides of equations 2, 3 and 4 are valid when the incoming signal x k is an S1 signal. It may be seen that the negative value assumed by the sum in equation 4, u n does not depend upon the sampling phase and carrier phase since those terms drop out in the sum which is formed. If noise or random data are received, the sum u n will fluctuate randomly about 0, but if an S1 sequence is being sent, the sum u n will always be negative. Similarly, if an unmodulated carrier signal is received, u n vanishes in the mean and random noise would prevail. Hence, a true detection may be obtained by observing that the metric u n is less than 0 during a specified number of consecutive modulation intervals. Any arbitrary number may be chosen, but a suitable criterion for a reception of an S1 sequence has been found by experimentation to be a sequential count of 32 consecutive occurrences of the metric u n less than 0. Greater robustness against noise or jitter can be achieved by applying the filtering function ξ to the metric u n as shown by equation 6: u n = (1-ε) u n -1 + ε( v cos,n v cos,n -1 + v sin,n v sin,n -1 ), 0<ε<1. Either an actual analog hardware filter may be built with the filtering coefficient ξ lying in the range of 0 to 1 as shown by equation 6, or a digitally implemented algorithm for filtering may be employed. The preferred embodiment of circuitry for performing the algorithm in equations 2 through 5 is shown in Figure 4. Turning to Figure 4, an incoming analog waveform signal at the receiving point is complex sampled by the sampler 12 which may be simply an analog to digital converters strobed at equal to or more than the Nyquist sampling rate. The S1 processing rate selected is, as discussed earlier, twice the modulation rate, or, an interval of T/2. After appropriate filtering and demodulation, consecutive baseband samples are repetitively made and fed into the inputs of the complex multipliers 1 and 2, respectively. Beginning at any arbitrary point, an incoming signal will be sampled to result in a sample x 2n , a succeeding sample x 2n-1 , another sample x 2n-2 and a fourth sample x 2n-3 . Each group of four consecutive samples is handled in the complex multipliers 1 and 2 with the even numbered and the odd numbered samples being taken together. Thus the input into the complex multiplier 1, for example comprises a signal x 2n and the next even numbered sample x 2n-2 (conjugated) which is displaced in time by T. The inputs to the complex multiplier 2 are, likewise, the complex sample x 2n-1 and x 2n-3 (conjugated). The even numbered samples and the odd numbered samples at the sampling rate T/2 thus comprise the separate inputs to the different complex multipliers 1 and 2 as shown in Figure 4. The complex sample signals have the form as shown above in equation 1. The two sets of complex samples represent an arbitrary clock time and its displacement by T/2. The output from the complex multipliers 1 and 2 in Figure 4 are the starting point for the calculations for the equations 2 and 3 for calculating the imaginary component v cos,n of and v sin,n , respectively. This fact is indicated in Figure 4 by the numeral 2(Im) (for "imaginary") after the output of the complex multiplier 1 and the numeral 3(Im) after the output of the complex multiplier 2. Each of these results is inputted to a time delay circuit 3 or 4, respectively, where a 1 modulation period time delay T is introduced prior to feeding the time delayed calculated imaginary value and the current imaginary value directly to the scalar multiplier 5 as shown in Figure 4, or for the other two complex and conjugate complex samples x 2n-1 and x 2n-3 , to the scalar multiplier 6 as shown. The results are summed together in the adder 7 whose output is the metric u n as shown by equation 4. A decision/comparator circuit 8 receives the input which is the sum. The decision circuit compares the value u n to 0 to determine if a negative value is present. If a negative value is present, the "yes" output increments the S1 counter 9 by one and if a non negative result occurs in comparator 8, the "no" output resets counter 9 to zero. The contents of counter 9 are continuously monitored by comparator 10 having an arbitrary threshold value for detection of a valid S1 sequence. It has been found that a threshold of 32 is an appropriate level for comparison. When 32 consecutive occurrences of the metric u n being less than 0 have been counted in counter 9, the comparator 10 will indicate and latch the detection of an S1 sequence, but will otherwise indicate "not S1" as shown. AND gate 11 receives the S1 detected input and the u n non negative input to logically indicate the end of the S1 sequence, AND gate 11 is conditioned because negative value u n have been found in sufficient number to indicate the presence of an S1 signal, and then comparator 8 will later indicate the occurrence of a non-negative value for u n . Figure 6 shows a typical modem front end for producing a complex baseband signal sample sequence as specified for input to the S1 detector. Analog Low Pass Filter (LPF) receives a real analog line signal at its input and provides a controlled spectrum version of this analog signal to A/D convertor 15 Spectrum control reduces sampling foldover interference at the convertor output. The A/D convertor samples the anti-alias filter output periodically at a uniform rate, typically greater than the minimum rate specified by sampling theory, (i.e. Nyquist rate). Digitally quantized signal values from the A/D convertor 15 are fed identically to a "Hilbert" filter-pair 16 which have further identical band-control responses but differing phase responses to yield a complex sampled signal pair at the input to a demodulator 17. Demodulator 17 receives a second complex carrier input sequence from 19 and performs a vector rotation of the signal by the given carrier angle-demodulation. Original "passband" samples are thus converted to complex baseband samples. Sequences of these baseband samples are buffered in 18 under control of-a rate selector input to yield T/2 spaced complex baseband signal samples as required by the S1 detector, Figure 4. Complex samples from sampler 12 are illustrated in Figure 5 schematically to show their placement as sample set 1 and sample set 2, etc. which would continue indefinitely. It may be seen that the numbering of the samples and their use in the circuitry for both the real and imaginary components are shifted by a time period delay T. Thus, after establishing an incoming signal, the first two samples will provide first inputs to the complex multipliers 1 and 2 and the next two samples will provide second inputs to the two complex multipliers, the outputs of which will be delayed by a period T for scalar multiplication in the multipliers 5 and 6 of Figure 4. It may thus be seen that incoming samples will be sequentially taken, but that a new calculation will occur only after two new samples-have been obtained while the two earliest obtained samples will no longer be utilized when fifth and sixth samples, respectively, have been received etc. It may be observed that the embodiment shown in Figure 4 may be easily realized in the hardware as shown or may be implemented as a program in a simple computer, provided appropriate account is kept of the fact that some of the sample values represent imaginary numbers. In equations 2 and 3, x 2n-2 and x 2n-3 are conjugate complex samples and are indicated by the asterisk over the x as is also shown in the legend to the drawing Figure 4. Returning to Figure 4, the logical flow is given for performing the algorithm as described by equations 2 through 5 above. As shown in Figure 4, four complex data samples are processed at each T time interval from x n-0 to x n-3 which is shown schematically in Figure 5. Figure 5 is for two adjacent T time intervals. These four samples constitute two interlaced sample pairs in which successive complex sample values are taken at sampling times spaced T/2 intervals apart. Each T interval, therefor, will contain two new complex samples. When two new complex signal samples are received, all of the samples are indexed so that the two oldest samples are replaced. The pairs of samples are for two different clock or sample sets as indicated by Figure 5. The conjugate multiplications indicated are performed in the multiplier blocks 1 and 2 in Figure 4 to rotate the more recently received complex samples through the polar angles of the previous T-spaced samples. As expected, an imaginary result for such differential rotation during the S1 sequence will have alternating mathematical signs. These imaginary components as shown by equations 2 and 3, respectively, will satisfy a particular condition when the S1 alternating ABAB symbol set is received. Each imaginary component will be multiplied by the previous imaginary component delayed by one modulation period T from the same source i.e. the delay will occur in the blocks 3 and 4 in Figure 4 and the multiplication in blocks 5 and 6 to obtain the scalar of the multiplication of the imaginary component by the previous delayed imaginary component. The expected value for the product of the multiplication during the alternating S1 sequence ABAB is either minus 1 or 0, depending upon the specific arbitrary clock position at which the samples are chosen. One may note that there are two like channels for this calculation in Figure 4 comprising blocks 1, 3 and 5 in one channel and blocks 2, 4 and 6 in the other. The channels differ in their clock positions as shown by the sample index used at their inputs. Therefore the output of blocks 5 and 6 will generate an expected sequence of -1, -1... from one of the blocks and 0, 0 from the other or vice versa; or both blocks may have an output of -0.5. Block 7 combines the results of the two scalar multiplications to form the sum u n of equation 4. This is a linear addition operation to form at its output a sequence of approximately -1, -1... so long as an S1 sequence is present. By maintaining a running count of the occurrence u n less than 0 and testing it against an appropriate threshold count, a valid S1 sequence may be detected. At each interval T, the output of block 7 is tested for a negative value in block 8. And if a negative value is found, the running count in counter 9 is incremented by 1, while otherwise the count is reset to 0. When an arbitrary number of consecutive negative values has been found, for example 32 T interval results being less than 0, one may accept the fact that an S1 occurrence is indicated. Any other non S1 valid sequence or noise interference will cause the output of block 7 to violate the expected test value of less than 0 and will cause the running count to reset to 0, thereby keeping the S1 count in counter 9 below the threshold value. The end of the valid S1 sequence is also easily detected and the precise end of the S1 signal is needed for other events in most modems. Block 11 in Figure 4 logically combines the latched valid decision from block 10 that an S1 sequence is detected with the running decision of the value sequence from block 7 and searches for any violation of the 1, -1 ... pattern i.e., if a value greater than 0 or 0 is found, this marks the S1 sequence end and it is so indicated. Implementation of a software program for implementing the algorithm for forming the sum of equation 4 by first calculating the results of equations 2 and 3 from inputted samples having the form as shown in equation 1 are self-evident and need no further description. Having thus described our invention with reference to a preferred embodiment, what is set forth in the claims which follows is included by way of example only and not by way of limitation wherefore what is claimed is:

Claims: A method of detecting a received CCITT S1 standard modem identification signal sequence, comprising steps of: complex sampling the amplitude of received baseband signals at a rate of twice the carrier modulation rate τ to yield four consecutive samples x 2n-0 , x 2n-1 , x 2n-2 , and x 2n-3 of the form: where τ and  may be any arbitrary values of the sampling phase and carrier phase, respectively; and forming the sum u n in accordance with u n = v cos,n v cos,n -1 + v sin,n v sin,n -1 = [-1], where v cos,n is and v sin,n is and; counting an arbitrary number of consecutive occurrences of the value of said sum u n being less than 0 as indicative of reception of said signal sequence. A method as described in Claim 1 wherein: said sampling further includes the step of forming interlaced sample value pairs from each group of four consecutive samples x n by choosing the two even numbered samples x 2n-0 and x 2n-2 and the two odd numbered samples, x 2n-1 and x 2n-3 for use in said sum forming step. A method as described in Claim 1 or Claim 2 wherein: said forming of said sum u n further includes filtering said sum against random noise and distortion by multiplying said sum u n by a filtering function of the form u n = (1-ε) u n -1 + ε( v cos,n v cos,n -1 + v sin,n v sin,n -1 ), 0<ε<1. where ξ is greater than 0 and less than 1. A method as described in Claim 1 or Claim 2 wherein: said sampling is continued after an indication of said sequence being received has occurred until a violation of said sum u n less than 0 is found, whereupon an end to said sequence is indicated. A method as described in Claim 3 wherein: said sampling is continued after an indication of said sequence being received has occurred until a violation of said sum u n less than 0 is found, whereupon an end to said sequence is indicated. A modem apparatus having signal reception and complex sampling means and means for detecting receipt of a modem identification signal of the form S1 in accordance with the CCITT recommendation, characterized in that it comprises : first multiplication means (1, 2) connected to receive complex baseband signal samples from said sampling means, said first multiplication means forming the complex products of alternate consecutive ones of said complex samples; time delay means (3, 4) connected to said first multiplier means for delaying transmission of said complex products by one modulation interval, T; second multiplication means (5,6) connected to receive both the output of said first multiplier and the output of said time delay means, said second multiplication means forming the scalar product thereof; and summing means (7) connected to said second multiplier means and receiving the result therefrom to form the sum of said scalar product therefrom; first comparison means (8) connected to said summing means for determining whether said sum is a negative value; counting means (9) connected to said first comparison means for counting consecutive instances of said comparison being negative; and second comparison means (10) connected to said counting means for comparing said count therefrom to an arbitrary value to indicate the presence of a modem identification sequence.

Inventors: MURRAY JACK THOMAS, UNGERBOECK GOTTFRIED, WARE MALCOLM SCOTT, MURRAY, JACK THOMAS, UNGERBOECK, GOTTFRIED, WARE, MALCOLM SCOTT
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1992
Main classification: H04L27
IPC codes: H04L27