Apparatus for interpolating scanning lines of TV signal in a TV receiver

Abstract: An apparatus for interpolating scanning lines of a TV signal in a TV, comprising a scanning line interpolator for discriminating vertical, horizontal and diagonal edge patterns of a received video signal of the TV signal and extracting a signal for interpolation from the video signal using vertical, 45° and 135° diagonal average values, a first time compressor for compressing the time of the interpolation signal from the scanning line interpolator, a second time compressor for compressing the time of the video signal, and a switch for selectively and in turn outputting output signals from the first and second time compressors. The scanning line interpolator includes a one line memory for delaying the received video signal by one line, first to fourth horizontal comparizon circuits, a diagonal/vertical sum signal output circuit for outputting first and second diagonal sum signals and a vertical sum signal, and an interpolation signal output circuit for selecting one of the first and second diagonal sum signals and the vertical sum signal from the diagonal/vertical sum signal output circuit in response to control signals from first and second control signal generating circuits, the selected signal having the smallest difference, averaging the selected signal and outputting the averaged signal as the interpolation signal.

Description: Field of the Invention The present invention relates in general to doubling the number of scanning lines of a television signal in a television (TV) of the interlaced scanning type, and more particularly to an apparatus for interpolating scanning lines of a TV signal in a TV, which is useful in removing step edges of a video which has a diagonal variation in the case of using conventional line repetition and vertical average methods. Generally, in a TV of the interlaced scanning type, a line structure, a line flicker, a vertical resolution insufficiency and etc. are generated as picture quality degradation elements due to the interlaced scanning. For this reason, for the purpose of solutions to these problems, there has conventionally been employed a method of scanning an interpolation scanning line between scanning lines to double the number of the scanning lines. The conventional method of doubling the number of the scanning lines includes an intra-field interpolation method which is classified into a line repetition method of performing the interpolation using the previous scanning line as the interpolation scanning line and a vertical average method of performing the interpolation by averaging the upper and lower scanning lines with respect to a scanning line to be interpolated, and an inter-field interpolation method of interpolating a scanning line of the previous field as the interpolation scanning line. Referring to Figs. 1A to 1D, there are shown block diagrams and views illustrating the conventional intra-field interpolation method, respectively. Fig. 1A is a block diagram of an intra-field interpolator using the line repetition and Fig. 1B is a view illustrating the intra-field interpolation method using the line repetition. In Fig. 1A, the intra-field interpolator comprises a one line memory 1 for delaying a received video signal Yin of a television signal by one line, a first time compressor 2 for compressing the time of an output signal from the one line memory 1 by 2 to 1, a second time compressor 3 for compressing the time of the video signal Yin by 2 to 1, and a switch SW1 for selectively outputting one of output signals from the first and second time compressors 2 and 3. Fig. 1C is a block diagram of an intra-field interpolator using the vertical average and Fig. 1D is a view illustrating the intra-field interpolation method using the vertical average. In Fig. 1C, the intra-field interpolator comprises a one line memory 4 for delaying a received video signal Yin of a television signal by one line, an adder 5 for adding an output signal from the one line memory 4 to the video signal Yin, a 1/2 amplifier 6 for amplifying an output signal from the adder 5 by a 1/2 level, a first time compressor 7 for compressing the time of an output signal from the 1/2 amplifier 6 by 2 to 1, a second time compressor 8 for compressing the time of the video signal Yin by 2 to 1, and a switch SW2 for selectively outputting one of output signals from the first and second time compressors 7 and 8. Referring to Figs. 2A and 2B, there are shown a block diagram and a view illustrating the conventional inter-field interpolation method, respectively. Fig. 2A is a block diagram of an inter-field interpolator and Fig. 28 is a view illustrating the inter-field interpolation method. In Fig. 2A, the inter-field interpolator comprises a one field memory 9 for delaying a received video signal Yin of a television signal by one field, a first time compressor 10 for compressing the time of an output signal from the one field memory 9 by 2 to 1, a second time compressor 11 for compressing the time of the video signal Yin by 2 to 1, and a switch SW3 for selectively outputting one of output signals from the first and second time compressors 10 and 11. The operations of the constructions in Figs. 1A, 1C and 2A will hereinafter be described with reference to Figs. 1B, 1D and 2B, respectively. In Fig. 1B, a scanning line i to be interpolated is substituted by the previous line. Namely, the time of the video signal Yin delayed by the one line memory 1 is compressed by 2 to 1 by the first time compressor 2 and the time of the original video signal Yin is compressed by 2 to 1 by the second time compressor 3. As a result, the first switch SW1 selects the output signal from the first time compressor 2 with respect to the scanning line to be interpolated and selects the output signal from the second time compressor 3 with respect to the original scanning line. At this time, a switching clock of the first switch SW1 is half a period of one scanning line of the inputted signal. In Fig. 1D, the scanning line i to be interpolated is substituted by averaging the upper and lower scanning lines a and b about the scanning line i in the field. Namely, the video signal Yin delayed by the one line memory 4 is added to the original video signal Yin by the adder 5 and then amplified by the 1/2 amplifier 6. The time of the output signal from the 1/2 amplifier 6 is compressed by 2 to 1 by the first time compressor 7 and the time of the original video signal Yin is compressed by 2 to 1 by the second time compressor 8. As a result, in a similar manner to that mentioned above with reference to Fig. 1A, the switch SW2 selects the output signal from the first time compressor 7 with respect to the scanning line to be interpolated and selects the output signal from the second time compressor 8 with respect to the original scanning line. In Fig. 2B, the scanning line i to be interpolated is substituted by a scanning line of the previous field. Namely, the time of the video signal Yin delayed by the one field memory 9 is compressed by 2 to 1 by the first time compressor 10 and the time of the original video signal Yin is compressed by 2 to 1 by the second time compressor 11. As a result, the third switch SW3 selects the output signal from the first time compressor 10 with respect to the scanning line to be interpolated and selects the output signal from the second time compressor 11 with respect to the original scanning line. However, the above-mentioned conventional interpolation methods have disadvantages as shown in Figs. 3B to 3D. Fig. 3A is a waveform diagram illustrating a motion of the original video in one field. The reference numeral a represents a still video, the reference numeral b represents the video moved by one sample to the right, the reference numeral c represents the video moved by one sample upward and the reference numeral d represents the video moved by one sample diagonally. Fig. 3B is a waveform diagram illustrating the interpolation result which is obtained by utilizing the line repetition. From Fig. 3B, it can be seen that many step edges appear at the still video and the video of slow motion. Fig. 3C is a waveform diagram illustrating the interpolation result which is obtained by utilizing the line average or the vertical average. It can be seen from Fig. 3C that blurred edge portions appear at the still video and the video of slow motion. Fig. 3D is a waveform diagram illustrating the interpolation result which is obtained by utilizing the inter-field interpolation. Herein, the interpolation is accurately performed at the still video, but inaccurately at the moved video. Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an apparatus for interpolating scanning lines of a TV signal in a TV, which is capable of removing step edges of an interpolated video by interpolating the scanning lines utilizing diagonal and vertical averages on the basis of control signals which are different according to edge patterns of a video signal of the interlaced scanning type. Document US-A-4 985 764 discloses an apparatus for generating an interpolation signal for a television signal according to the preamble of claim 1. However, document US-A-4 985 764 does not disclose such control signals. In accordance with the present invention, the above and other objects can be accomplished by a provision of an apparatus for interpolating scanning lines of a video signal in a television receiver according to the characterizing portion of claim 1. According to another aspect of the invention, there is provided an apparatus for interpolating scanning lines of a video signal in a television receiver according to claim 4. Other features are recited in the subclaims. The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1D are block diagrams and views illustrating a conventional intra-field interpolation method, respectively, wherein: Fig. 1A is a block diagram of an intra-field interpolator using a line repetition; Fig. 1B is a view illustrating the intra-field interpolation method using the line repetition; Fig. 1C is a block diagram of an intra-field interpolator using a vertical average; and Fig. 1D is a view illustrating the intra-field interpolation method using the vertical average; Figs. 2A and 2B are a block diagram and a view illustrating a conventional inter-field interpolation method, respectively, wherein: Fig. 2A is a block diagram of an inter-field interpolator; and Fig. 2B is a view illustrating the inter-field interpolation method; Fig. 3A is a waveform diagram illustrating a motion of the original video in one field; Fig. 3B is a waveform diagram illustrating the interpolation result which is obtained by utilizing the line repetition; Fig. 3C is a waveform diagram illustrating the interpolation result which is obtained by utilizing the vertical average; Fig. 3D is a waveform diagram illustrating the interpolation result which is obtained by utilizing the inter-field interpolation; Fig. 4 is a block diagram of an apparatus for interpolating scanning lines of a TV signal in a TV in accordance with the present invention; Fig. 5 is a detailed block diagram of a scanning line interpolator in the apparatus in Fig. 4 in accordance with an embodiment of the present invention; Fig. 6 is a detailed block diagram of the scanning line interpolator in the apparatus in Fig. 4 in accordance with an alternative embodiment of the present invention; Figs. 7A to 7F show characteristics of control signals which are different according to edge patterns in accordance with the present invention; and Fig. 8 is a view illustrating a proposed interpolation method on a two-dimensional area in accordance with the present invention. Referring to Fig. 4, there is shown a block diagram of an apparatus for interpolating scanning lines of a TV signal in a TV in accordance with the present invention. As shown in this figure, the scanning line interpolating apparatus of the present invention comprises a scanning line interpolator 21 for extracting a signal for interpolation from a received video signal Vi of the television signal, a first time compressor 22 for compressing the time of the interpolation signal from the scanning line interpolator 21 by 2 to 1, a second time compressor 23 for compressing the time of the video signal Vi by 2 to 1, and a switch 21 for selectively and in turn outputting output signals from the first and second time compressors 22 and 23. Referring to Fig. 5, there is shown a detailed block diagram of the scanning line interpolator 21 in the apparatus in Fig. 4 in accordance with an embodiment of the present invention. As shown in this drawing, the scanning line interpolator 21 includes a one line memory 32 for delaying the received video signal Vi by one line, a first horizontal comparison circuit 110 for delaying the received video signal Vi by one sample, detecting a difference signal between the video signal Vi and the one sample-delayed video signal, taking the absolute value of the detected difference and comparing the absolute value with a predetermined reference value T1, a second horizontal comparison circuit 120 for delaying the one sample-delayed video signal from the first horizontal comparison circuit 110 by one sample, detecting a difference signal between the one sample-delayed video signal and the two-sample-delayed video signal, taking the absolute value of the detected difference and comparing the absolute value with a predetermined reference value T2, a third horizontal comparison circuit 130 for delaying the one line-delayed video signal from the one line memory 32 by one sample, detecting a difference signal between the one line-delayed video signal and the one line-delayed and then one sample-delayed video signal, taking the absolute value of the detected difference and comparing the absolute value with a predetermined reference value T3, and a fourth horizontal comparison circuit 140 for delaying the one line-delayed and then one sample-delayed video signal from the third horizontal comparison circuit 130 by one sample, detecting a difference signal between the one line-delayed and then one sample-delayed video signal and the one line-delayed and then two-sample-delayed video signal, taking the absolute value of the detected difference and comparing the absolute value with a predetermined reference value T4. The scanning line interpolator 21 also comprises a diagonal/vertical sum signal output circuit 150 for summing the received video signal Vi and the one line-delayed and then two- sample-delayed video signal from the fourth horizontal comparison circuit 140 to output a first diagonal sum signal L, summing the two-sample-delayed video signal from the second horizontal comparison circuit 120 and the one line-delayed video signal from the one line memory 32 to output a second diagonal sum signal N and summing the one sample-delayed video signal from the first horizontal comparison circuit 110 and the one line-delayed and then one sample-delayed video signal from the third horizontal comparison circuit 130 to output a vertical sum signal M, a first control signal generating circuit 160 for adding the horizontal difference signals from the first to fourth horizontal comparison circuits 110-140, detecting a vertical difference signal between the one sample-delayed video signal from the first horizontal comparison circuit 110 and the one line-delayed and then one sample-delayed video signal from the third horizontal comparison circuit 130 and exclusive-ORing the added signal and the vertical difference signal to generate a control signal, a second control signal generating circuit 170 for generating a control signal in response to control signals from the first to fourth horizontal comparison circuits 110-140, and an interpolation signal output circuit 180 for selecting one of the first and second diagonal sum signals L and N and the vertical sum signal M from the diagonal/vertical sum signal output circuit 150 in response to the control signals from the first and second control signal generating circuits 160 and 170, the selected signal having the smallest difference, amplifying the selected signal by a factor 1/2 and outputting the amplified signal as the interpolation signal. The first to fourth horizontal comparison circuits 110140 each includes a one sample memory for delaying a signal inputted therein by one sample, a subtracter for subtracting the output signal from the one sample memory from the signal inputted in the one sample memory, an absolute value generator for taking the absolute value of the output signal from the subtracter and a comparator for comparing the output signal from the absolute value generator with a predetermined reference value. The second control signal generating circuit 170 includes a bit adder 49 for adding the control signals D10-D13 from the first to fourth horizontal comparison circuits 110-140, inverters I1 and I2 for inverting the most significant 2 bits of the output signal from the bit adder 49, respectively, and an AND gate AND1 for ANDing output signals from the inverter gates I1 and I2 and the least significant bit of the output signal from the bit adder 49 and outputting the ANDed signal as the control signal. Referring to Fig. 6, there is shown a detailed block diagram of the scanning line interpolator 21 in the apparatus in Fig. 4 in accordance with an alternative embodiment of the present invention. As shown in this figure, the scanning line interpolator 21 includes first to fourth horizontal comparison circuits 210-240, a diagonal vertical sum signal output circuit 250, a first control signal generating circuit 260, a second control signal generating circuit 270, a weight generating circuit 280 for generating a weight signal in response to a control signal from the second control signal generating circuit 270, a diagonal interpolation signal generating circuit 290 for selecting one of first and second diagonal sum signals L and N from the diagonal/vertical sum signal output circuit 250 in response to a control signal from the first control signal generating circuit 260, the selected signal having a smaller diagonal difference, and amplifying the selected signal by a gain based on the weight signal from the weight generating circuit 280, and an interpolation signal output circuit 300 for amplifying a vertical sum signal M from the diagonal/vertical sum signal output circuit 250 by the gain based on the weight signal from the weight generating circuit 280, summing the amplified vertical sum signal M and the diagonal interpolation signal from the diagonal interpolation signal generating circuit 290, amplifying the summed signal by a factor 1/2 and outputting the amplified signal as the interpolation signal. Herein, the constructions of the first to fourth horizontal comparison circuits 210-240, the diagonal/vertical sum signal output circuit 250, the first control signal generating circuit 260 and the second control signal generating circuit 270 are the same as those in Fig. 5 and a description thereof will thus be omitted. The weight generating circuit 280 is a typical IIR filter and includes a subtracter 281 for obtaining a difference between an input signal Xn and an output signal from the weight generating circuit 280 delayed by one sample, a K amplifier 282 for amplifying an output signal from the subtracter 281 by a predetermined factor K, an adder 283 for adding the output signal from the K amplifier 282 to the output signal from the weight generating circuit 280 delayed by one sample and outputting the added signal as the weight signal, and a one sample memory 284 for delaying the output signal from the adder 283 by one sample and feeding back the one sample-delayed signal to the subtracter 281 and the adder 283. The weight generating circuit will hereinafter be referred to as the IIR filter. The operation of the scanning line interpolating apparatus with the above-mentioned construction in accordance with the present invention will hereinafter be described in detail with reference to Figs. 4 through 8. The video signal Vi or luminance and chrominance signals separated from the received TV signal is applied to the scanning line interpolator 21 with the construction in Fig. 5 or 6. The scanning line interpolator 21 extracts the interpolation signal from the received video signal Vi and outputs it to the first time compressor 22. The video signal Vi is also applied to the second time compressor 23. The first and second time compressors 22 and 23 perform the time compression with respect to the inputted signals. The switch SW21 selects the output signal from the second time compressor 23 with respect to the original position and selects the output signal from the first time compressor 22 with respect to the position to be interpolated. At this time, a switching clock of the switch SW21 is T H /2 (T H : about 63.5 µs in a NTSC system). In Fig. 5, the video signal Vi of the interlaced scanning type is summed up to the signal delayed by the one line memory 32 and the third and fourth sample memories 33 and 34, thereby resulting in production of the sum signal L of 135° . diagonal components. The signal delayed by the first one sample memory 30 is summed up to the signal delayed by the one line memory 32 and the third one sample memory 33, thereby resulting in production of the sum signal M of vertical components. The signal delayed by the first and second one sample memories 28 and 29 is summed up to the signal delayed by the one line memory 32, thereby resulting in production of the sum signal N of 45° diagonal components. In the first to fourth horizontal comparison circuits 110-140, the output signals from the first to fourth subtracters 30, 31, 35 and 36 are applied to the first to fourth comparators 45-48 through the first to fourth absolute value generators 41-44, respectively. As a result, the first to fourth comparators 45-48 output the control signals D10-D13 based on the edge patterns as shown in Figs. 7A to 7F, respectively. In the second control signal generating circuit 170, the control signals D10-D13 from the first to fourth horizontal comparison circuits 110-140 are added in the bit adder 49. The inverters I1 and I2 invert the most significant 2 bits of the output signal from the bit adder 49, respectively, and the AND gate AND1 ANDs the output signals from the inverter gates I1 and I2 and the least significant bit of the output signal from the bit adder 49. At this time, when the edge pattern is a diagonal pattern (45° or 135°), the output from the AND gate AND1 is high. When the edge pattern is a horizontal or vertical pattern, the output from the AND gate AND1 is low. The difference signals from the first to fourth subtracters 30, 31, 35 and 36 are added in the adder 50, which outputs the added signal as a sign bit (1 bit). The exclusive-OR gate EX-OR1 exclusive-ORs the sign bit from the adder 50 and a sign bit Ho of the vertical difference signal. If the sign bits are the same, the edge pattern is 45° edge. As a result, the output from the exclusive-OR gate EX-OR1 is low. If the sign bits are not the same, the edge pattern is 135° edge. As a result, the output from the exclusive-OR gate EX-OR1 is high. The output signal from the AND gate AND1 and the output signal from the exclusive-OR gate EX-OR1 are used as the most and least significant bits MSB and LSB of the multiplexer 51, respectively. When the output signals from the AND gate AND1 and the exclusive-OR gate EX-OR1 as control signals all are high, the multiplexer 51 outputs the 135° diagonal component sum signal L. When the output signals from the AND gate AND1 and the exclusive-OR gate EX-OR1 as control signals are low and low or low and high, the multiplexer 51 outputs the vertical component sum signal M. Also, the multiplexer 51 outputs the 45° diagonal component sum signal N when the output signals from the AND gate AND1 and the exclusive-OR gate EX-OR1 are high and low. The output signal from multiplexer 51 is amplified by 1/2 in the 1/2 amplifier 52. In result, the output signal from the 1/2 amplifier 52 is the interpolation signal. On the other hand, in Fig. 6, there are generated the 135° diagonal component sum signal L, the vertical component sum signal M, the 45° diagonal component sum signal N, the edge pattern control signals D10-D13 and the vertical control signal Ho. The output signal from the exclusive-OR gate EX-OR2 is a control signal for discriminating whether the diagonal edge pattern is 45° or 135°. In response to the control signal from the exclusive-OR gate EX-OR2, the multiplexer 76 outputs the 135° diagonal component sum signal L or the 45° diagonal component sum signal N. The output signal from the AND gate AND2 in the second control signal generating circuit 270 is a control signal for discrimination of the diagonal edge pattern and is applied to the IIR filter 280, which maintains a consistency of the control signal for discrimination of the edge pattern. The IIR filter 280 acts to maintain a consistency of the control signal for discrimination of the edge pattern to prevent a considerable picture quality degradation due to a discrimination error. Assuming that the input of the IIR filter 280 is Ci(n), the output thereof can be expressed by the following equation: Co(n) = K.Ci(n) + (1-K).Co(n-1) The frequency response of the IIR filter 280 can be expressed by the following equation: H(e jW ) = K/[1_(1-K)e -jW ] From the above equation, it can be seen that the output signal is sensitive to the input signal as the K value becomes large. The output signal Co(n) from the IIR filter 280 is multiplied by the diagonal component sum output from the multiplexer 76 in the first variable amplifier 77. On the other hand, in the second variable amplifier 78, the value of Co(n) is multiplied by the vertical component sum signal M. The output signals from the first and second variable amplifiers 77 and 78 are added in the adder 79 and then amplified by 1/2 in the 1/2 amplifier 80. In result, the output signal from the 1/2 amplifier 80 is the interpolation signal. Figs. 7A to 7F show characteristics of the control signals which are different according to the edge patterns in accordance with the present invention and Fig. 8 is a view illustrating a proposed interpolation method on a two-dimensional area in accordance with the present invention. The control signals can be expressed as follows: D10 = a-b, [X -1 (n-1) - X -1 (n)], D11 = b-c, [X -1 (n) - X -1 (n+1)], D12 = d-e, [X +1 (n-1)- X +1 (n)], D13 = e-f, [X +1 (n) -X +1 (n+1)], and Ho = b-e, [X -1 (n)- X +1 (n)] Assuming that the sample to be interpolated is i, the above control signals can be changed according to the edge patterns as follows. Namely, as shown in Figs. 7A to 7D, in the case of a diagonal edge which is varied diagonally, only one of the control signals D10-D13 exceeds a predetermined threshold voltage. In the case of a 135° edge (\), the sum of the control signals D10-D13 and the control signal Ho are exclusive-ORed into 1. In the case of a 45° edge (/), the sum of the control signals D10-D13 and the control signal Ho are exclusive-ORed into 0. Also in the case of a vertical edge (|) as shown in Fig. 7E, the control signal Ho does not exceed the predetermined threshold and, therefore, the number of the control signals D10-D13 exceeding the predetermined threshold voltage is 0 or two or more. In the case of a horizontal edge (-) as shown in Fig. 7F, the control signal Ho exceeds the predetermined threshold voltage and the number of the control signals D10-D13 exceeding the predetermined threshold voltage is 0. Accordingly, the interpolation value applied to the sample to be interpolated on the two-dimensional area as shown in Fig. 8 is L[= 1/2(a + f)] in the case of the 135° edge (\) and N[= 1/2(c + d)] in the case of the 45° edge (/). Also in the case other than the 45° or 135° edge, a vertical average M[1/2(b +e)] is used as the interpolation value. As hereinbefore described, according to the present invention, there is provided the apparatus for interpolating the scanning lines of the TV signal in the TV, which is capable of removing the step edges of the interpolated video by interpolating the scanning lines utilizing the diagonal and vertical averages on the basis of the control signals which are different according to the horizontal, vertical and diagonal edge patterns of the video signal of the interlaced scanning type.

Claims: An apparatus for interpolating scanning lines of a video signal in a television receiver, comprising scanning line interpolating means (21) for discriminating vertical, horizontal and diagonal edge patterns of a received video signal (Vi) and extracting an interpolation signal from the video signal using vertical, 45° and 135° diagonal average values, characterized in that it further comprises : first time compressing means (22) for compressing the time of the interpolation signal from said scanning line interpolating means (21) ; second time compressing means (23) for compressing the time of the video signal ; and switching means (SW21) for selectively and in turn outputting output signals from said first and second time compressing means (22, 23), and in that said scanning line interpolating means (21) include : a one line memory (32) for delaying the received video signal (Vi) by one line ; first horizontal comparison means (110) for delaying the received video signal (Vi) by one sample, detecting a first horizontal difference signal between the received video signal (Vi) and the one sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T1) and outputting a first control signal (D10) in accordance with said comparison ; second horizontal comparison means (120) for delaying the one sampled-delayed video signal from said first horizontal comparison means (110) by one sample, detecting a second horizontal difference signal between the one sample-delayed video signal and the two-sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T2), and outputting a second control signal (D11) in accordance with said comparison ; third horizontal comparison means (130 ) for delaying the one line-delayed video signal from said one line memory (32) by one sample, detecting a third horizontal difference signal between the one line-delayed video signal and the one line-delayed and then one sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T3), and outputting a third control signal (D12) in accordance with said comparison ; fourth horizontal comparison means (140) for delaying the one line-delayed and then one sample-delayed video signal from said third horizontal comparison means (130) by one sample, detecting a fourth horizontal difference signal between the one line-delayed and then one sample-delayed video signal and the one line-delayed and then two-sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T4), and outputting a fourth control signal (D13) in accordance with said comparison ; diagonal/vertical sum signal output means (150) for summing the received video signal (Vi) and the one line-delayed and then two-sample-delayed video signal from said fourth horizontal comparison means (140) to output a first diagonal sum signal (L), summing the two-sample-delayed video signal from said second horizontal comparison means (120) and the one line-delayed video signal from said one line memory (32) to output a second diagonal sum signal (N) and summing the one sample-delayed video signal from said first horizontal comparison means (110) and the one line-delayed and then one sample-delayed video signal from said third horizontal comparison means (130) to output a vertical sum signal (M); first control signal generating means (160) for adding the first through fourth horizontal difference signals from said first to fourth horizontal comparison means (110, 120, 130, 140) to obtain an added signal as a sign bit, obtaining a vertical difference signal between the one sample-delayed video signal from said first horizontal comparison means (110) and the one line-delayed and then one sample-delayed video signal from said third horizontal comparison means (130) and generating a control signal in response to the added signal and the vertical difference signal by exclusiveORing the sign bit from the added signal and the sign bit of the vertical difference signal ; second control signal generating means (170) for adding the first through fourth control signals (D10, D11, D12, D13) from said first to fourth horizontal comparison means (110, 120, 130, 140), inverting the most significant 2 bits of the added signal and generating a control signal in response to the inverted most significant 2 bits of the added signal and the least significant bit of the added signal ; and interpolation signal output means (180) for selecting one of the first and second diagonal sum signals (L,N) and the vertical sum signal (M) from said diagonal/vertical sum signal output means (150) in response to the control signals from said first and second control signal generating means (160,170), amplifying the selected signal by a factor 1/2 and outputting the amplified signal as the interpolation signal (Vout). An apparatus for interpolating scanning lines of a video signal,as set forth in Claim 1, wherein said first to fourth horizontal comparison means (110, 120, 130, 140) each includes: a one sample memory (28, 29, 33, 34) for delaying a signal inputted therein by one sample; a subtracter (30, 31, 35, 36) for subtracting the output signal from said one sample memory (28, 29, 33, 34) from the signal inputted in said one sample memory; an absolute value generator (41, 42, 43, 44) for taking the absolute value of the output signal from said subtracter (30, 31, 35, 36); and a comparator (45, 46, 47, 48) for comparing the output signal from said absolute value generator (41, 42, 43, 44) with a predetermined reference value (T1, T2, T3, T4). An apparatus for interpolating scanning lines of a video signal, as set forth in Claims 1 or claim 2, wherein said second control signal generating means (170) includes: a bit adder (49) for adding the control signals from said first to fourth horizontal comparison means (110,120,130,140); inverter gates (I1, I2) for inverting the most significant 2 bits of the output signal from said bit adder (49), respectively; and an AND gate (AND1) for ANDing output signals from said inverter gates (I1, I2) and the least significant bit of the output signal from said bit adder (49) and outputting the ANDed signal as the control signal. An apparatus for interpolating scanning lines of a video signal in a television receiver, comprising scanning line interpolating means (21) for discriminating vertical, horizontal and diagonal edge patterns of a received video signal (Vi) and extracting an interpolation signal from the video signal using vertical, 45° and 135° diagonal average values, characterized in that it further comprises : first time compressing means (22) for compressing the time of the interpolation signal from said scanning line interpolating means (21) ; second time compressing means (23) for compressing the time of the video signal ; and switching means (SW21) for selectively and in turn outputting output signals from said first and second time compressing means (22, 23), and in that said scanning line interpolating means (21) include : a one line memory (56) for delaying the received video signal by one line ; first horizontal comparison means (210) for delaying the received video signal (Vi) by one sample, detecting a first horizontal difference signal between the received video signal (Vi) and the one sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T1), and outputting a first control signal (D10) in accordance with said comparison ; second horizontal comparison means (220) for delaying the one sample-delayed video signal from said first horizontal comparison means (210) by one sample, detecting a second horizontal difference signal between the one sample-delayed video signal and the two-sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T2), and outputting a second control signal (D11) in accordance with said comparison; third horizontal comparison means (230) for delaying the one line-delayed video signal from said one line memory (56) by one sample, detecting a third horizontal difference signal between the one line-delayed video signal and the one line-delayed and then one sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T3), and outputting a third control signal (D12) in accordance with said comparison; fourth horizontal comparison means (240) for delaying the one line-delayed and then one sample-delayed video signal from said third horizontal comparison means (230) by one sample, detecting a fourth horizontal difference signal between the one line-delayed and then one sample-delayed video signal and the one line-delayed two-sample-delayed video signal, taking the absolute value of the detected difference, comparing the absolute value with a predetermined reference value (T4), and outputting a fourth control signal (D13) in accordance with said comparison; diagonal/vertical sum signal output means (250) for summing the received video signal(Vi) and the one line-delayed and then and then two- sample-delayed video signal from said fourth horizontal comparison means (240) to output a first diagonal sum signal (L), summing the two-sample-delayed video signal from said second horizontal comparison means (220) and the one line-delayed video signal from said one line memory (56) to output a second diagonal sum signal (N) and summing the one sample-delayed video signal from said first horizontal comparison means (210) and the one line-delayed and then one sample-delayed video signal from said third horizontal comparison means (230) to output a vertical sum signal (M); first control signal generating means (260) for adding the first through fourth horizontal difference signals from said first to fourth horizontal comparison means (210, 220, 230, 240) to obtain an added signal as a sign bit obtaining a vertical difference signal between the one sample-delayed video signal from said first horizontal comparison means (210) and the one line-delayed and then one sample-delayed video signal from said third horizontal comparison means (230) and generating a control signal in response to the added signal and the vertical difference signal by exclusive-ORing the sign bit from the added signal and the sign bit of the vertical difference signal; second control signal generating means (270) for adding the first through fourth control signals (D10, D11, D12, D13) from said first to fourth horizontal comparison means (210, 220, 230, 240), inverting the most significant 2 bits of the added signal and generating a control signal in response to the inverted most significant 2 bits of the added signal and the least significant bit of the added signal; weight generating means (280) for generating a weight signal (Co(n)) in response to the control signal from said second control signal generating means (270); diagonal interpolation signal generating means (290) for selecting one of the first and second diagonal sum signals (L, N) from said diagonal/vertical sum signal output means (250) in response to the control signal from said first control signal generating means (260), amplifying the selected signal by a gain based on the weight signal (Co(n)) from said weight generating means (280), and outputting the amplified selected signal as a diagonal interpolation signal; and interpolation signal output means (300) for amplifying the vertical sum signal (M) from said diagonal/vertical sum signal output means (250) by the gain based on the weight signal (Co(n)) from said weight generating means (280), summing the amplified vertical sum signal and the diagonal interpolation signal from said diagonal interpolation signal generating means (290), amplifying the summed signal by a factor 1/2 and outputting the amplified signal as the interpolation signal (Vout). An apparatus for interpolating scanning lines of a video signal, as set forth in Claim 4, wherein said first to fourth horizontal comparison means (210, 220, 230, 240) each includes: a one sample memory (52, 53, 57, 58) for delaying a signal inputted therein by one sample; a subtracter (54, 55, 59, 60) for subtracting the output signal from said one sample memory (52, 53, 57, 58) from the signal inputted in said one sample memory; an absolute value generator (65, 66, 67, 68) for taking the absolute value of the output signal from said subtracter (54, 55, 59, 60); and a comparator (69, 70, 71, 72) for comparing the output signal from said absolute value generator (65, 66, 67, 68) with a predetermined reference value (T1, T2, T3, T4). An apparatus for interpolating scanning lines of a video signal, as set forth in claim 4 or claim 5, wherein said second control signal generating means (270) includes: a bit adder (73) for adding the control signals from said first to fourth horizontal comparison means (210, 220, 230, 240); inverter gates (I3, I4) for inverting the most significant 2 bits of the output signal from said bit adder (73), respectively; and an AND gate (AND2) for ANDing output signals from said inverter gates (I3, I4) and the least significant bit of the output signal from said bit adder (73) and outputting the ANDed signal as the control signal. An apparatus for interpolating scanning lines of a video signal, as set forth in any one of Claims 4-6, wherein said weight generating means (280) includes: a subtracter (281) for obtaining a difference signal between an input signal (Ci(n)) and an output signal from said weight generating means (280) delayed by one sample; a K amplifier (282) for amplifying the output signal from said subtracter (281) by a predetermined factor (K); an adder (283) for adding the output signal from said K amplifier (282) to the output signal from said weight generating means (280) delayed by one sample and outputting the added signal as the weight signal (Co(n)); and a one sample memory (284) for delaying the output signal from said adder (283) by one sample and feeding back the one sample-delayed signal to said subtracter (281) and said adder (283).

Inventors: HONG SUNG HOON, HONG, SUNG HOON
Applicants: LG ELECTRONICS INC, LG ELECTRONICS INC.
Application year: 1992
Main classification: H04N5
IPC codes: H04N7, H04N5