Process for flip-chip connection of a semiconductor chip

Abstract: A process for flip-chip connection comprises the steps of forming a plurality of spacer bumps 9 on the periphery of the semiconductor chip 6, forming a plurality of solder bumps 5 on the main chip surface, providing a cutting groove 10 between the solder bumps 5 and the spacer 9, aligning the solder bumps 5 on the semiconductor chip with the corresponding solder bumps on the circuit board 7, heating the assembly in order to merge the mating solder bumps 5 and thus to form the flip-chip connection, and breaking away the outer peripheral portion of the semiconductor chip 6 along the cutting groove 10 thereby removing the spacer bumps 9.

Description: The present invention relates generally to a process for flip-chip connection of a semiconductor chip. According to the progress of information-processing technology, semiconductor devices that form the major part of information-processing equipment are subjected to ever-increasing demands for greater capacity, LSI and VLSI chips being currently in use. As is well known, these integrated circuit elements have a large number of unit transistors arranged in an array on a semiconductor chip having an area of several mm 2 . When a circuit connection is effected by wire bonding, the back side of the semiconductor chip is initially bonded on a circuit board by a eutectic alloy or solder or an adhesive. Then electrode terminals (pads) provided on the circumference of the chip are wire-bonded to corresponding electrode terminals (pads) provided on the circuit board for establishing electrical connection to conductors on the circuit board. However, the extremely high density of modern devices means that such wire-bonding methods are not applicable for a large-capacity element, such as an LSI chip. For large-capacity elements it is typical to employ a flip-chip connection method, in which solder bumps are arranged in matrix form on one surface of the semiconductor chip. Upon being mounted on the circuit board, the surface side of the semiconductor chip is mated or aligned with the surface of the circuit board so that the solder bumps on the semiconductor chip come into contact with solder bumps on the circuit board; the bumps are then soldered to each other. Employing this method, since the semiconductor elements can be directly mounted on the circuit board, signal transmission paths can be significantly shortened. This contributes to the reduction of transmission loss of the signal transmitted through the signal transmission paths. In practice, solder bumps having configurations identical to those of the solder bumps on the semiconductor elements are formed on the circuit board, such as those made of ceramic, at positions exactly corresponding to those on the semiconductor elements. The semiconductor element is mounted on the circuit board by mating respective solder bumps thereof with the solder bumps on the circuit board. Thereafter, a heat higher than the melting point of the bumps is applied so as to melt the solder bumps for welding respectively mating bumps. Most of the current semiconductor integrated circuits are formed of silicon (Si). On the other hand, most of the currently available circuit boards are formed of alumina ceramics or glass ceramics. As set forth above, large capacity elements, such as LSI, VLSI or so forth are frequently mounted on the circuit board by flip-chip connection. The inventors have proposed in Japanese Patent Application No. 2-118388 (JP-A- 4-14834), which has been commonly assigned to the assignee of the present invention, a method for forming a plurality of solder bumps on the semiconductor chip or the circuit board with high positioning precision. Using the solder bumps formed by the proposed method, flip-chip connections can be effected in a practical and efficient manner. A brief discussion of the conventional method will be provided. At first, as shown in Fig. 2, a metal mask is fitted on a transparent substrate 1 that has high thermal resistance but cannot be connected by soldering, such as a glass plate or a transparent quartz plate. At this position, a solder is deposited by vacuum disposition to form solder projections 2 (Fig. 2A). On the other hand, a substrate 3,which may be a semiconductor chip or a circuit board or both, is preliminarily formed with pads of gold (Au)and so forth, equal in size to solder bumps formed at positions forming the solder bumps, by way of vacuum desposition and so forth. The substrate 3 to be processed is heated at a temperature higher than or equal to the melting point of the solder. The solder projections 2 on the transparent substrate 1 are then positioned and aligned with respective corresponding pads 4 arranged in matrix form, and the solder projections 2 and the pads 4 are mated with each other (Fig. 2B). Since the solder forming the solder projections 2 have low adhering ability to the transparent substrate 1 and have high adhering ability to the pads 4, the solder projections 2 are transferred to the pads 4 to form the solder bumps 5 (Fig. 2C). A feature of this forming method is that, even when a slight offset is present between the pads 4 on the substrate 3 to be processed and the solder projection 2 on the transparent substrate 1, the hemisphere solder bumps 5 can be formed on the pads by self-alignment. Next, the solder bumps 5 thus formed on the semiconductor chip 6 are positioned in alignment with the corresponding solder bumps 5 on the circuit board 7 and then mated with the latter (Fig. 2D). By heating the circuit board 7 to a temperature higher than or equal to the melting point of the solder, the mating solder bumps 5 are melted and are welded to each other. The welded solder is cask-shaped (Fig. 2E). However, in such a connection method, stress due to the difference in thermal expansion coefficients between the semiconductor chip 6 and the circuit board 7 can concentrate at the junction between the barrelshaped solder and the substrate and thereby lower reliability. To avoid this problem, various methods of forming the solder mass into a configuration with an intermediate waist portion, i.e. a reduced-diameter middle portion, have been proposed. In one of the proposed methods, spacers are mounted on the circuit board so as to provide a clearance between the semiconductor chip and the circuit board. However, this method encounters a problem in that it is difficult to maintain sufficient space to insert the spacer because of the small area of the semiconductor chip. Also, it is difficult to maintain the height of the spacer constant. In view of the above, this method is not practical and results in low workability. Also, there has been proposed another method, in which the semiconductor chip is drawn up after connection to form the waist portion. However, this method is not practical and it lowers the reliability of the products. Therefore, it is an object of the present invention to provide a flip-chip connecting process that enables the formation of solder, for connecting a semiconductor chip and a circuit board, into a configuration having an intermediate waist portion. According to the invention, a flip-chip connection process for a semiconductor chip, in which solder bumps formed on the semiconductor chip in a matrix arrangement are mated with solder bumps formed on a circuit board for flip-chip connection, comprises the steps of: forming a plurality of spacer bumps on the semiconductor chip or the substrate in the vicinity of the periphery of the chip; providing a weakened portion between the plurality of solder bumps and the spacer bumps before the chip and substrate are aligned; aligning the solder bumps on the semiconductor chip with the corresponding solder bumps on the substrate; heating the assembly so as to cause the solder bumps to merge, the spacer bumps holding the chip and the substrate at a predetermined spacing with the height of the spacer bumps being selected so as to form a smaller-diameter waist portion at the intermediate portion of the merged solder bumps; and breaking away the peripheral portion of the semiconductor chip along the weakened portion after the flip-chip connection is made, in order to remove the spacer bumps. Preferably, the step of forming the stud bumps is performed by wire-bonding a wire on each pad once or, if necessary, several times in succession and subsequently crushing the bonded wire to the desired height to give the correct spacing of chip and substrate. The spacer bumps or studs should have a melting point higher than that of the solder and may conveniently be made of aluminium or gold. They are preferably formed on the chip and are removed with the peripheral chip portion, but they could conceivably be formed on the substrate instead. Japanese Unexamined Patent Publication (Kokai) No. 4-22130 discloses a flip-chip connection method in which stud bumps are formed on the periphery of a semiconductor chip on which solder bumps are formed. However, this reference does not disclose the provision of solder bumps on the substrate on which the chip is mounted, in addition to the provision of the solder bumps on the chip. Also, this reference does not disclose the removal of the stud bumps after completion of the flip-chip connection. EP-A1-0147576 (IBM) likewise describes a process of bonding a semiconductor chip to a substrate using nickel spacer spheres; however, these spheres remain in place once soldering is completed. JP-A-59-155162 may also be consulted as showing guide bumps for flip-chip bonding. Each of the stud bumps may be formed higher than the individual solder bumps but shorter than the total height of the mating solder bumps. In practice, the height of the stud bump is selected so as to form a smaller diameter waist portion at the intermediate portion of the integrated (merged) solder bumps. The step of forming the stud bump may be effected by wire bonding and cutting or breaking a wire in one step to a predetermined cut length by a wire bonder and then crushing the predetermined cut length of wire into a length corresponding to the desired height of the stud bump and with a tip end plane surface. Reference may be made in this context to GB-A-2095473. Alternatively, it is possible to carry out the wire bonding and cutting to a length shorter than the predetermined cut length and to repeat this step until the length of the cut wire attains the predetermined cut length. As can be appreciated herefrom, with the present invention, stud bumps of suitable height may be provided on the outer periphery of the semiconductor chip for maintaining the most suitable spacing during flip-chip connection between the solder bumps on the semiconductor chip and the solder bumps on the circuit board. The stud bumps can be removed together with the peripheral portion of the semiconductor chip after completion of connection. By this method, the waist portion can be assuredly formed on the integrated solder to avoid concentration of stress at the junction between the solder and the substrates. The stud bumps can be easily formed by a conventional wire-bonding process using gold (Au) or aluminium (Al) wire. The bonded wire is crushed or compressed to provide a stud bump sufficient in height to allow the solder bumps to merge while maintaining a smaller diameter waist portion at an intermediate position. The present invention will be understood more fully from the detailed description given below by way of example of one embodiment with reference to the accompanying drawings, in which: Figs. 1A to 1E are sections showing process steps of a flip-chip connection method in accordance with the present invention; and Figs. 2A to 2E, as discussed above, are sections showing process steps in the conventional flip-chip connection method. Initially, on a substrate surface of a semiconductor chip, on which an integrated circuit, such as LSI and so forth, are formed, pads 4 for forming solder bumps 5 and stud bumps 9 thereon are disposed by way of vacuum deposition of gold (Au) and so forth. Ideally, the pads 4 for forming the stud or spacer bumps 9 are formed at four corners of the semiconductor chip 6. However, it is possible to arrange the pads 4 for forming the stud bumps in the vicinity of the peripheral edges to form an equilateral triangle. On the pads 4 for the stud bumps, Au wires or aluminium(Al) wires are bonded by means of a wire bonder. Then, the bonded wire is cut or torn off by the wire bonder at a predetermined length (approximately 70 µm) appropriate for forming the stud bumps to form the stud bumps 9 (Fig. 1A). Then, by means of a dicing-saw, dicing lines 10 are formed to define the outer peripheral portion including the stud bumps 9. Also, in a manner similar to that of the prior art discussed with respect to Fig. 2, the solder bumps 5 are formed on the pads 4 at the inside of the dicing lines 10. At the same time, the stud bumps 9 are crushed into a predetermined height (Fig. 1B). Thereafter, the solder bumps 5 on the semiconductor chip 6 are positioned in alignment with those on the circuit board 7 (Fig. 1C) substantially in the same manner as those in the prior art. At this time, the stud bumps 9 having predetermined heights serve as spacers for maintaining a predetermined distance between the semiconductor chip 6 and circuit board 7 (Fig. 1D). The distance to be maintained between the semiconductor chip 6 and the circuit board 7 is selected so that the solder bumps of the semiconductor chip 6 and the circuit board 7 may form a configuration with the waist portion at the intermediate position. Thereafter, the mating solder bumps 5 are melted by heating the circuit board 7 for welding. At this time, since the stud bumps 9 maintain sufficient clearance between the semiconductor chip 6 and the circuit board 7 as set forth above, the melted solder cannot be crushed to the extent that it forms a cask-shaped configuration but allows for a smaller-diameter waist portion at the intermediate position thereof (Fig. 1D). Thereafter, the semiconductor substrate is broken away at the dicing lines 10 so as to remove the outer circumferential portion together with the stud bumps 9. By this method, the flip chip connection with the solder configuration having an intermediate waist can be easily formed with satisfactory accuracy using a relatively simple method. It should be appreciated that the size of the solder bumps is variable depending upon the size and rating of the semiconductor chip. Therefore, the height of the stud bumps is variable depending upon the size of the solder bumps. In this case, if a higher stud bump is required, since the height of the stud bump at one wire bonding operation after crushing is approximately 70 µm, the wire bonding process is repeated in order to obtain a sufficient height. The stud bump thus formed with a sufficient height is then crushed with an appropriate jig into the predetermined stud bump height. The process of the present invention can provide advantages over the process as disclosed in the hereinbefore-mentioned Japanese Unexamined Patent Publication (Kokai) No. 4-22130, in that since the solder bumps on the semiconductor chip and on the circuit board are mated upon connection so as to be bonded with each other, good wettability between the bonded bumps is attained, and in addition, since the stud bumps are removed after completion of the flip chip connection, additional elements such as condensers or capacitors, resistors and the like can also be mounted. A plurality of pads 4 were formed on the surface of a semiconductor chip formed of silicon (Si) and on the surface of a circuit board formed of ceramic or glass ceramic by vacuum deposition and photolithographic technology. Each pad 4 was formed into a circular configuration with an 80 µm diameter. The pads 4 were arranged in the matrix array with a center-to-center pitch of 150 µm. In addition, on the four corners of the semiconductor chip, the pads 4 for the stud bumps were formed. The pads 4 on the four corners were given the same diameters as those of the other pads. Here, the vacuum deposition layer forming each pad 4 had a three-layer construction of Au/Pt/Ti from the lower side at the bottom layer of Ti. The thickness of the respective layers was 1000Å (100nm). Next, by means of the dicing saw, dicing lines 10 extending along the circumferential edge of the semiconductor chip were formed. The depth of the dicing line was 350 µm while the thickness of the semiconductor chip substrate was 500 µm. On the pads 4 for the stud bumps on four corners, Au wires with a 35 µm diameter were wire bonded. The Au wires were then cut or torn at a height of 70 µm. The wire was then crushed to a height of 60 µm so as to have a plane tip end surface. On the other hand, employing the conventional bump transfer method, the solder bumps 5 with a height of 40 µm were formed on the semiconductor chip and the circuit board. Then, flux was applied on the semiconductor chip surface and the circuit board surface. Thereafter, the semiconductor chip and the circuit board were mutually positioned and mated with respective corresponding solder bumps 5, and heated for soldering together. After connecting, a flux washing was performed. The circumferential portions of the semiconductor chip were broken away at the dicing lines 10, together with the stud bumps. As a result, a 60 µm solder connection with a smaller diameter waist portion could be obtained. A plurality of pads 4 were formed on the surface of a semiconductor chip formed of silicon (Si) and on the surface of a circuit board formed of glass ceramic by vacuum deposition and photolithographic technology. Each pad 4 was formed into a circular configuration with a 200 µm diameter. The pads 4 were arranged in the matrix array with a center-to-center pitch of 400 µm. In addition, on the four corners of the semiconductor chip, the pads 4 for the stud bumps were formed. The pads 4 on the four corners were given the same diameters as those of the other pads. Here, the vacuum deposition layer forming each pad 4 had a three-layer construction of Au/Pt/Ti from the lower side at the bottom layer of Ti. The thickness of respective layers was 1000Å. Next, by means of the dicing saw, dicing lines 10 extending along the circumferential edge of the semiconductor chip were formed. The depth of the dicing line was 350 µm while the thickness of the semiconductor chip substrate was 500 µm. On the pads 4 for the stud bumps on four corners, Au wires with a 35 µm diameter were wire bonded. The Au wires were then cut at a height of 70 µm. This process was repeated sequentially five times. The resultant wire was then crushed to a weight of 200 µm with a plane tip end surface. On the other hand, employing the conventional bump transfer method, the solder bumps 5 with a 120 µm height were formed on the semiconductor chip and the circuit board. Then, flux was applied on the semiconductor chip surface and the circuit board surface. Thereafter, the semiconductor chip and the circuit board were mutually positioned and mated with respective corresponding solder bumps 5, and heated for soldering together. After connecting, a flux washing was performed. The circumferential portions of the semiconductor chip were broken away at the dicing lines 10, together with the stud bumps. As a result, the solder connection with a height of 200 µm and with a smaller diameter waist portion could be obtained. As can be appreciated, with the present invention, the solder connection with a solder configuration having an intermediate waist portion can be easily obtained through a relatively simple process. This contributes significantly to the improvement in reliability of the semiconductor device. It will be understood that while the invention is particularly applicable to semiconductor devices, it can also be used for other solid-state devices such as piezoelectric components.

Claims: A process of forming the flip-chip connection of a semiconductor chip, in which solder bumps (5) formed on the semiconductor chip (6) are mated with solder bumps formed on a substrate (7) for flip-chip connection; the process comprising the steps of: forming a plurality of spacer bumps (9) on the semiconductor chip (6) or the substrate (7) in the vicinity of the periphery of the chip; providing a weakened portion (10) between the plurality of solder bumps (5) and the spacer bumps (9) before the chip and substrate are aligned; aligning the solder bumps on the semiconductor chip with the corresponding solder bumps on the substrate (7); heating the assembly so as to cause the solder bumps to merge (11), the spacer bumps (9) holding the chip (6) and the substrate (7) at a predetermined spacing with the height of the spacer bumps (9) being selected so as to form a smaller-diameter waist portion at the intermediate portion of the merged solder bumps (11); and breaking away the peripheral portion of the semiconductor chip along the weakened portion after the flip-chip connection is made, in order to remove the spacer bumps (9). A process as set forth in claim 1, wherein each spacer bump (9) is formed with a height greater than the height of the individual solder bumps (5) but less than the sum of the heights of the corresponding pairs of solder bumps. A process as set forth in claim 1 or 2, wherein the step of forming the spacer bumps (9) is performed by bonding a wire onto each bump location, breaking off the wire and subsequently crushing the wire to a height corresponding to the predetermined spacing. A process as set forth in claim 3, wherein each wire is cut to a predetermined length and then the wire ends are crushed to a length corresponding to the desired height of the spacer bump in such a way as to form a plane end surface. A process as set forth in claim 4, wherein several wire bonding and cutting steps are performed sequentially until the cut wire attains the said predetermined length. A process as set forth in any preceding claim, wherein the spacer bumps are made of aluminium or gold. A process as set forth in any preceding claim, wherein the weakened portion (10) is a groove cut into the chip (6).

Inventors: HASHIMOTO KAORU, KARASAWA KAZUAKI, NAKANISHI TERU, OCHIAI MASAYUKI, HASHIMOTO, KAORU, KARASAWA, KAZUAKI, NAKANISHI, TERU, OCHIAI, MASAYUKI, HASHIMOTO, KAORU, FUJITSU LIMITED, KARASAWA, KAZUAKI, FUJITSU LIMITED, NAKANISHI, TERU, FUJITSU LIMITED, OCHIAI, MASAYUKI, FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H01L21
IPC codes: H05K3, H01L21