A diagonal propagation digital multiplier

Abstract: A diagonal propagation, digital multiplier of a kind adapted to multiply a first factor (x(n)) by a second (M), with said factors being each expressed as a binary number, characterized in that it comprises: a non-volatile memory (3) having a plurality of cells (5) each with one digit of a factor (M) stored therein; a plurality of computation blocks (I,II,....,VIII) cascade connected together, each block being also connected to a corresponding cell (5) in the memory (3); computation means (6) in each of the blocks for performing a binary sum of the first factor (x(n)) plus one digit of the second factor (M); and memory elements (L) in each of the blocks for storing therein the result of the calculation and making it available as pseudo-carryover to the next block.

Description: This invention relates to a diagonal propagation, digital multiplier of a type intended for multiplying a first factor (x(n)) by a second factor (M), with either factors being expressed by a binary number. The field of application of the invention is related, in particular but not solely, to digital FIR (Finite Impulse Response) filters and reference will be made, throughout this description, to that field of application for convenience of illustration. As is known, digital filters are devices designed to convert a sampled signal x(n) being input thereto into another sampled signal y(n) having predetermined frequency response characteristics. A sampled signal is, of course, a digital signal encoded as a binary number of N digits or bits on which the filter accuracy or resolution is dependent. The prior art teaches filters in integrated circuit form which comprise digital multipliers and adders so arranged as to have, produced for each input, an output y(n) given by the sum of the present and past input samples as multiplied each by a respective coefficient d(i), to be obtained from the filter pulse response. For example, a typical filter of conventional construction uses a chain of N-1 adders, each provided with first and second inputs, and an output. The output of each one adder is connected to the first input of the next, through a delay block (T), and the second input of each adder is connected to the output of a corresponding digital multiplier (X). The various coefficients d(i) of response to the filter pulse are associated directly with the multipliers (X). According to the prior art, the multipliers have been embodied by circuit structures which are quite complex and sluggish in the processing run. Structures of that kind are described, for instance, in Joseph Cavanagh, "Digital Computer Arithmetics", McGraw-Hill, pages 137 - 235. A structure of a digital multiplier of known type is also disclosed in the U.S. patent No. 4,189,767 to Ahuja. This document discloses a pipelined multiplier specifically designed for an address translator of a memory system. One input of such a multiplier is the multiplicand which includes n parallel bit level signals, each individually applied to one of inputs (Y 1 -Y n ) of the multiplier. The other basic input of the multiplier includes X 1 -X n parallel bit signals from an external input register. All the inputs are gated into a storing register via a clocking arrangement. Each of the basic cells in the first row of the multiplier also has a sum and carry input and produces two outputs for the next successive storing register. The carry conductors run vertically while the sum conductors run diagonally. The initial input to each of these conductors is a "0" level signal. In such a configuration, known as a pipelined carry save multiplier, the first n+2 rows perform the multiplication function exclusive of the carrying function. The remaining storing registers provide the carry function in accordance with the general pipeline operation. This document doesn't suggest the use of such a multiplier in a digital filter and, moreover, it provides a multiplier structure which is not so fast and efficient to be useful in digital filters. The use of a multiplier in a digital filter is suggested in the IEEE Journal of Solid State Circuits, vol. SC-18, No. 3, June 1983, pages 280-285. However, the multiplier structure disclosed therein is very complex and requires a specific design of all components which may not be coupled in a modular way. The sluggishness of prior art multipliers imposes a serious limitation on the implementation of fast digital filters; in fact, the commercially most widely used designs can only perform satisfactorily when operated at a low frequency. Another limitation comes to current designs from the extreme difficulty of implementing so-called adaptive filters, i.e. filters for which the value of one of the multiplicative factors, such as that of the filter coefficients d(i), for example, can be readily changed. The underlying technical problem of this invention is to provide a digital multiplier which has structural and functional features enabling it to operate at a faster rate, and making digital filters of the adaptive type feasible, thereby to overcome the limitations of prior embodiments. The solutive idea on which the invention stands is that of first storing one of the multiplicative factors, and then performing the multiplication on binary numbers using a partial product, called pseudo-carryover, which is the partial result without the rightmost generated bit of a binary sum between an input digital signal x(n) and a coefficient digit b(i), and and a digital word, called pseudo-sum, made by a series of said rightmost generated bits.This solution makes the value of one of the multiplicative factors readily modifiable and minimize the computing time for the multiplication. Based on this idea, the technical problem is solved by a multiplier as indicated above and defined in the characterizing portion of Claim 1. The features and advantages of a digital multiplier according to the invention will become apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a diagramatic view of a digital multiplier embodying this invention; Figure 2 is a diagramatic view of a conventionally accepted digital filter structure; and Figures 3 to 8 are respective diagramatic views of details of the multiplier shown in Figure 1. With reference to the drawing views, generally and schematically shown at 1 is a digital multiplier embodying this invention. The multiplier 1 may be incorporated, for example, into a digital filter 2, shown in Figure 2, which receives as input a given digital code sampled signal x(n), and outputs another sampled signal y(n) having predetermined frequency response characteristics. The filter 2 is a so-called linear FIR (Finite Impulse Response) type, i.e. wherein at each n-th discrete time the input x(n) and output y(n) signals are tied together by the following relation: from which it is evinced that the output sample y(n) is only dependent on the present and past input samples. The coefficients d(i) are a finite number N and can be obtained from the response to the filter pulse. Basically, relation (1) shows that an output sequence y(n) can be obtained from an input sequence x(n) by carrying out a series of products and sums between those samples which represent the system response to the impulse and the input samples as suitably delayed. Accordingly, within the filter 2, each multiplier 1 is arranged to perform multiplication of a first factor, represented by the input signal x(n), by a second factor M, represented by a coefficient d(i). Advantageously, the multiplier 1 of this invention includes a memory 3 wherein the various digits or bits of a i-th coefficient d(i) are stored. The memory 3 is a non-volatile type and implemented preferably as a programmable EPROM memory. However, there would be no objection to the use of some other memory type. In the exemplary embodiment under consideration, the coefficients are coded with eight bits and accordingly, the memory 3 comprises eight cells 5, each containing one digit or bit of a corresponding coefficient d0....d7. As a whole, in the filter 1 there are N memories each having eight bits. The multiplier 1 further comprises a group of N computation blocks, each having a specific circuit structure to be described. In this case, there are eight blocks, and each block has been denoted by a corresponding Roman numeral I, II,....,VIII. The eight cells 5 of memory 3 are arranged correspondingly with the eight blocks I, II,....,VIII, and each cell 5 is connected to its corresponding block to supply it with the value of the bit corresponding to the coefficient stored therein. Also provided is a final block, indicated at 4, which is operative to result the most significant portion of the product operation, while the least significant portion of the product is provided by the eight blocks I, II,....,VIII. Each block includes computing means for performing a binary arithmetics operation, as well as storage elements for storing the operation result therein. Figure 3 shows in detail the structure of the first block I, which comprises a series of inputs a0....a7 in parallel arrangement and adapted to receive the input signal x(n). In the example herein, the input signal x(n) is provided in an eight-bit digital coding, and corresponding with input a0 is the least significant bit in said coding. Each of the aforesaid inputs a0....a7 is led to a corresponding logic gate 6 of the AND type which has two inputs and one output. The second input of each gate 6 is connected to the first cell 5 of the memory 3. The group of gates 6 basically perform a binary product of the coding of x(n) plus the bit b0 of the i-th coefficient. The result of this operation is indicated by the sequence-of binary digits p'1....p'7 and stored in a group 9 of memory cells L, e.g. latches. Each cell L is connected to the output of one of the gates 6 excepting the first, that is, the gate 6 associated with the least significant input a0. Said first gate having in fact its output A free and available as a block I output. Presented on that output A is the least significant digit in the so-called pseudo-sum of input signal x(n) and the bit b0 of the given coefficient d(i). It should be noted, moreover, that a branch off toward a register 10 made up of individual memory cells L is provided from each input a0,....,a7. This register 10 holds the value of the input signal to provide it to the other blocks of multiplier 1, so that on this value further operations may be performed. For this purpose, each cell L of the register 10 is directly connected to an identic and corresponding cell of another register 10 included in the block II. The structure of the second block II is showed more specifically in figure 4 and it is on its turn characterized by a parallel arrangement of logic gates 6. Each gate has a couple of inputs and one output as in the block I. The first input of each gate is connected to a corresponding cell L of the register 10; while the other input of each logic gate is connected to a second cell 5 of the memory 3, in order to receive a digital signal concerning the coefficient digit b1. Advantageously, the block II has also a couple of adders 7 and 8 in cascade connection. More specifically, the adders 7 are of an Half Adder type and are indicated in the drawings with the abbreviation HA; while the adders 8 are Full Adders and are indicated with the abbreviation FA. In the block II couples of Full and/or Half adders are provided with connections to couples of outputs of the gates 6 in order to compute the carryoverof the binary sum between the input signal x(n) plus coefficient digit b1. Of course, the carryover will propagate through a single cell only. All the adders 7 or 8, with the exception of that associated with the most significant binary digit, are input both the output signal from the corresponding gate 6 and the signal contained in the corresponding memory L of group 9 in the preceding block I. Advantageously, the memory cells (latches) L are incorporated to the block II after the adders 7 or 8 in order to store therein the so-called pseudo-carryover associated with the binary sum. In a similar manner to that described in connection with the first block I, also in the second block II the first logic gate 6, i.e. the gate related to the least significant digit of the sum performed in that block, has an output B which is left free in order to provide an output of block II through which the value of the second bit of pseudo-addition of the two multiplicative factors can be derived. As for the remaining blocks of multiplier 1, it matters to observe that the even-numbered blocks IV and VI have identical structures substantially similar to that of the second block II, but with a difference in the arrangement of the HA and FA adders. This different arrangement is made necessary simply by carryover count requirements. Shown in Figure 6 is the structure of such blocks IV and VI of the even order. As for the odd-numbered blocks III, V and VII, these also have the same structure, as shown in Figure 5. They differ from the even order blocks by the provision of single half adders 7 at the outputs of the first and last logic gate 6 in the group of logic gates contained within each block. Commanding separate consideration is the structure of the eighth block shown in Figure 7. This block is connected to the last cell 5 in the memory 3, i.e. the cell containing the most significant bit of the second multiplicative factor composed of the coefficients digits b0,....,b7. The value of the coefficient digit b7 is 0 when the second factor is a positive number. When that factor is instead a negative number expressed as a complement on 2, the logic value of b7 is put equal to 1. Consequently, to perform the binary sum operation in block VIII with due account for any carryover, a branch-off 13 from the last cell 5 is input to a logic gate 11 of the XOR (exclusive OR) type which has another input connected to the output of the last FA adder 8 in the block. The branch-off 13 is also extended to the first adder in block VIII for joint connection with the adder output to a half adder 12 whose output H completes the output group A, B, ...., H of the blocks I, II,....VIII intended to compose the pseudo-sum of the two factors, x(n) and M. Provided at the output of the XOR gate 11 and the last adder HA are respective memory cells L, additional to those provided after the group of adder pairs 8. It should be further noted that the ninth block 4 shown in Figure 8 comprises essentially HA and FA adders, as well as memory cells L for receiving the outputs from block VIII ahead and performing a final sum that yields the result of the multiplication in cooperation with the outputs from A to H of the eight blocks I, II,..., VIII. The operation of the inventive multiplier will be now described with reference to an initial state wherein the input signal x(n) is presented to the inputs a0,....,a7 of block I for multiplication by the series of coefficients digits b0,....,b7 contained in the memory 3. The multiplier 1 operates on a clock pulse, not shown because conventional, and the input signal x(n) is received at every clock pulse. The input signal x(n) is encoded by a binary number which can be expressed mathematically as a sum of powers of 2: x(n) = a 0 + a 1 *2 + a 2 *2 2 + ....+ a N-1 *2 N-1 The input signal x(n) will be assumed to be always positive; this introduces no limitation because, in order to sample the signal, the analog/digital converters ahead of filter 2 generally supply a plus sign signal. The series of coefficients digits b0,....,b7 together represent a binary number which can be expressed as a sum of powers of 2. This second binary number will be denoted hereinafter by M, followed by an indication of its plus or minus (+/-) sign. In one case, we get: M(+) = b 0 + b 1 *2 + b 2 *2 2 +....+ b N-1 *2 N-1 , whereas in the other, M(-) represents a negative number expressed as a 2's complement, namely: M(-) = b 0 + b 1 *2 + b 2 *2 2 + ....+ b N-2 *2 N-2 + (-2 N-1 ). Thus, the multiplier 1 is to address two possible multiplication types, namely: x(n)*M(+) and x(n)*M(-). When both factors are positive and represented by an N-bit coding, their product reduces to performing the binary sum of the first factor plus the second factor as shifted through N-1 positions toward the most significant bits. On the other hand, where the second factor is negative and expressed as a 2's complement, the product of the factors reduces to performing the previous operation and adding its result to the 2's complement of the first factor as shifted through N-1 positions toward the most significant bits. In the first computation block I, the signal X(n) is at once multiplied by coefficient digit b0. This operation is actually performed as a binary sum of the coding of x(n) and the bit of coefficient digit b0. The partial result yielded is stored in the group 9 of memories L placed after the logic gates 6 and constitutes a first, so-called pseudo-carryover. It matters to observe, however, that this partial result also generates the least significant bit of the product, which is made available as pseudo-sum on the output A of block I. The second block II has the input sample x(n) available to it in the register 10 and receives, from the block preceding it. the aforesaid partial result in pseudo-carryover form. The input sample x(n) is applied to the AND gates 6 along with the corresponding coefficient digit bl, and a new product is computed in pseudo-sum form. The carryover propagates through a cell owing to the adders 7 and 8 being arranged in cascaded pairs. The result of this, the second, operation is made available on the output B as the second digit of the multiplicative factor pseudo-sum, as well as in the cells L after the adders, as pseudo-carryover for propagation to the next block. Thus, each block will store the input sample to make it available for the next block, and add the input sample to the partial product from the block ahead. The n-th and eighth blocks will add to the partial product the 2's complement input sample, as computed over nine bits, in the instance of the second factor M being negative. In summary, if the number of bits per word is N, then the product of two words of N bits each is fully defined by a string of 2N bits. Accordingly, each internal number of the multiplier is represented by two strings of bits which constitute the partial products, pseudo-sum and pseudo-carryovers in proper order according to their weights. The actual number resulting from the multiplication is therefore obtained by propagating the pseudo-carryover from one block to the next by addition of the produced logical product. In essence, this means that the words containing the pseudo-sum and the output 14 of the final block 4 are concatenated. The multiplier of this invention has a major advantage in that it reconciles a simple construction with fast multiplicative factor processing capability. Another important advantage of this multiplier resides in the possibility it affords of implementing digital filters of the adaptive type.

Claims: A diagonal propagation digital multiplier of a type intended for multiplying a first factor (x(n)) by a second factor (M), both factors being expressed by a binary number, comprising: a non-volatile programmable memory (3) having a plurality of cells (5) each with one digit of one (M) of said factors stored therein; a plurality of computation blocks (I,II,....,VIII) being cascade connected to one another and each block being connected to a respective corresponding cell (5) of said memory (3); each of said computation blocks (I,II,....,IX) delivering a computation result being a pseudo-carryover comprising sum and carry signals, and a least significant bit signal forming one digit of a pseudo-sum which is available at a free output of said computation block, and each of said computation blocks comprising a computation stage (6) performing the binary product of the first factor (x(n)) and a digit of the second factor (M) stored in the corresponding cell, and performing the sum of said binary product and the pseudo-carryover provided by a preceding computation block by means of binary adders (HA, FA) arranged in pairs and interconnected such that a carry signal is only propagated once within each pair of adders in said computation stage, in order to provide a computation result; a plurality of memory elements (L) in each of said computation blocks for storing the pseudo-carryover portion of said computation result and making it available as pseudo-carryover to the next computation block of said plurality of computation blocks; and a final block (XI) computing the sum and carry signals of the last pseudo-carryover provided by the last computation block (VIII) in order to make the result of the product operation available in explicit form on the output. A multiplier according to Claim 1, characterized in that, with the only exception of the first, second, and last computation blocks, the even-position numbered blocks (IV,VI) have identical structures, and likewise, the odd-position numbered blocks (III,V,VII) have identical structures. A multiplier according to Claim 1, characterized in that the last (VIII) of said blocks includes a logic gate of the exclusive-or (XOR) type having an input connected directly to its corresponding last cell (5) in said memory (3).

Inventors: GOLLA CARLA, SALI MAURO, GOLLA, CARLA, SALI, MAURO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: G06F7
IPC codes: G06F7, G06F17