Forming dielectrics in semiconductor devices

Abstract: A method of forming an inter-metal dielectrics in a semiconductor device includes the steps of sequentially forming first and second insulating layers (25, 27) over a semiconductor substrate with a patterned metal layer 23, etching-back the second insulating layer 27 so as to form second insulating spacers over side walls of the first insulating layer 25, and growing a third insulating layer 29 over the first and second insulating layers 25, 27, the growing speed of the third insulating layer 29 being different over regions of the first insulating layer 25 than over regions of the second insulating layer 27.

Description: The present invention relates to the fabrication of semiconductor devices, and more particularly to forming inter-metal dielectrics in semiconductor devices. Recently, highly integrated semiconductor devices tend to have multiple conductive layers, which intensifies the importance of flatness of insulating layers between metal layers. In order to achieve the flatness of the insulating layers between the multiple metal layers in a semiconductor device, there is generally used a spin-on glass process, an etch-back process, or a resinous insulating process using polyimide. However, these give rise to problems such as voids, cracks, etc. produced in regions between conductive lines during the planarization process, because the conductive lines have increased step differences and the intervals between the conductive lines are of the order of submicrons. There is shown a conventional spin-on glass planarization process in Figures 1A-1D of the accompanying diagrammatic drawings. In this case, the starting material is a semiconductor substrate with lower conductive lines 3. The process for forming transistors, capacitors, etc. is neglected in the drawings. Referring to Figure 1A, a second insulating layer 5 of oxide is deposited over a semiconductor substrate (not shown) with a first insulating layer 1 of BPSG (Boro-Phospho-Silicate Glass) and a first metal layer 3 forming the lower conductive lines. In the step of Figure 1B, a third insulating layer 7 of spin-on glass is applied and subjected to heat treatment. The third insulating layer is usually coated several times to improve step coverage and avoid cracks. In the step of Figure 1C, the spin-on glass layer 7 is etched-back so as to expose the portions of the insulating layer 5 over the first metal layer 3. In the step of Figure 1D, a fourth insulating layer 9 for buffering is finally laid over the substrate completing the planarization of the insulating layer between the lower and upper conductive lines. However, the spin-on glass layer 7 is so weak as to be easily cracked, so that reliability of the semiconductor device can not be assured. EP-A-349070 discloses the steps of sequentially forming first and second insulating layers over a semiconductor substrate having a patterned metal layer, such that portions of the first and second insulating layers are selectively exposed and depositing a third insulating layer over the first and second insulating layers. The surfaces of the second insulating layer are anisotropically etched once deposited to provide a V-shaped groove with gently sloping surfaces 37 between the metallisations. Because the grooves are V-shaped, the subsequently formed insulating layer may be isotropically deposited on the gently sloping surfaces and becasue there are no enclosed angles of greater than 90 degrees on or adjacent the gently sloping surfaces the third insulating layer can be isotropically deposited without forming voids. EP-A-0 411 795 discloses the anisotropic deposition of SiO 2 with different deposition rates on vertical layers than on horizontal ones. Preferred embodiments of the present invention aim to provide an improved method for forming inter-metal dielectrics without voids in a semiconductor device. Another aim is to provide a method for forming inter-metal dielectrics in a semiconductor device, which inter-metal dielectrics have a good resistance against cracking and a good planarization. According to the present invention, there is provided a method of forming an inter-metal dielectric in a semiconductor device, comprising the steps of: sequentially forming first and second insulating layers over a semiconductor substrate having a patterned metal layer, such that portions of said first insulating layer and portions of said second insulating layer are selectively exposed; and depositing a third insulating layer on said exposed portions of said first and second insulating layers, characterised in that the deposition rate of said third insulating layer is different on said exposed portions of said first insulating layer to the rate on said exposed portions of said second insulating layer because the deposition rate of the third layer is a function of the material onto which it is being deposited. Preferably, said exposed portions of said first insulating layer are over respective portions of said patterned metal layer. Preferably, said exposed portions of said first insulating layer are exposed by etching-back said second insulating layer so as to form spacers of said second insulating layer over side walls of said first insulating layer. Preferably, said exposed portions of said first insulating layer are exposed by: applying a sacrificial layer to said second insulating layer; etching-back said sacrificial layer so as to expose said second insulating layer on said patterned metal layer and first insulating layer, thereby leaving sacrificial layer portions between portions of said patterned metal layer; and removing the exposed portions of said second insulating layer by using said remaining sacrificial layer portions as a mask. Preferably, said sacrificial layer comprises a photoresist or spin-on glass layer. A method as above may include the preliminary step of forming said patterned metal layer on said substrate. Preferably, said first insulating layer comprises phospho-silicate glass (PSG), O 3 -tetra- ethyl-ortho-silicate phospho silicate glass (O 3 -TEOS PSG), O 3 -tetra-ethyl-ortho-silicate boro-phospho-silicate glass (O 3 -TEOS BPSG), P-TEOS undoped silicate glass (USG) or TiN. Preferably, said second insulating layer comprises plasma-enhancement silane USG (P-SiH 4 USG) or O 3 -TEOS USG. Preferably, said third insulating layer comprises O 3 -TEOS USG. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 to 4 of the accompanying diagrammatic drawings, in which: Figures 2A to 2C are cross-sectional views for schematically illustrating one example of a method of forming inter-metal dielectrics according to an embodiment of the present invention; Figures 3A to 3D are cross-sectional views for schematically illustrating another example of a method of forming inter-metal dielectrics according to the present invention; and Figures 4A to 4D are cross-sectional views for schematically illustrating a further example of a method of forming inter-metal dielectrics according to a further embodiment of the present invention. Referring to Figures 2A-2C, a first insulating layer 25 of about 1000Å thickness and a second insulating layer 27 of about 1000Å are sequentially formed over a semiconductor substrate (not shown) with an inter-metal dielectric 21 formed of BPSG and a first metal layer 23 forming lower conductive lines, in the step of Figure 2A. The first insulating layer 25 consists of PSG (Phospho-Silicate Glass), O 3 -TEOS PSG (O 3 -Tetra-Ethyl-Ortho-Silicate Phospho-Silicate-Glass), O 3 -TEOS BPSG, or P-TEOS USG (Plasma-enhanced Tetra Ethyl Ortho Silicate Undoped Silicate Glass), and the second insulating layer 27 consists of P-SiH 4 USG (Plasma-enhanced Silane Undoped Silicate Glass) or O 3 -TEOS USG. In the step of Figure 2B, the second insulating layer 27 is etched-back so as to form spacers 27 of the second insulating layer over the side walls of the first insulating layer 25. In the step of Figure 2C, a third insulating layer 29 whose deposition rate depends on the lower layer is laid to about 6000Å thickness over the substrate. The third insulating layer 29 is an oxide layer such as O 3 -TEOS USG whose deposition rate depends on the lower layer and thus is higher in the region over the second insulating spacer 27 than in the region over the first insulating layer 25. As a result there is obtained a flat insulating layer without voids even if the intervals between the conductive lines are narrow and the step differences are greatly increased. Referring to Figures 3A-3D, over a semiconductor substrate (not shown) with an inter-metal dielectric 31 and first metal layer 33 forming lower conductive lines there are sequentially formed first insulating layer 35 of about 1000Å thickness, a second insulating layer 37 consists of about 1000Å thickness and photoresist 39, in the step of Figure 3A. The first insulating layer 35 consists of PSG, O 3 -TEOS PSG, O 3 -TEOS BPSG, or P-TEOS USG, and the second insulating layer 37 consists of P-SiH 4 USG or O 3 -TEOS USG. In the step of Figure 3B, the photoresist 39 is etched-back so as to expose the second insulating layer 37 thereby leaving photoresist portions in the recesses between the first metal layers 33. In the step of Figure 3C, the exposed portions of the second insulating layer 37 are removed by using the remaining photoresist portions as a mask. Then a third insulating layer 41 of O 3 -TEOS USG is formed over the substrate after removing the photoresist 39, in the step of Figure 3D. The deposition rate of the third insulating layer 41 depends on the property of the lower insulating layer. Namely, the deposition rate of the third insulating layer 41 is greater in the region over the second insulating layer 37 than in the region over the first insulating layer 35. As a result the portions of the third insulating layer between the metal layers 33 have a thickness great enough to compensate for the depth of the recesses between the metal layers, thus preferably planarizing the inter-metal dielectric. In this embodiment, a photoresist mask is employed to cause portions of the second insulating layer 37 to remain only in predetermined regions, but a spin-on glass layer may be employed in other embodiments. Referring to Figures 4A-4D, a metal layer 53 forming lower conductive lines and a first insulating layer 55 are sequentially deposited over a semiconductor substrate (not shown) with an inter-metal dielectric 51, in the step of Figure 4A. In this case the thickness of the first insulating layer 55 is about 1000Å. A second insulating layer 57 of about 1000Å thickness is formed over the substrate. The first insulating layer 55 consists of PSG, TiN or P-TEOS USG, and the second insulating layer 57 P-SiH 4 USG or O 3 -TEOS USG. A sacrificial layer 59 formed of photoresist or spin-on glass is applied to the second insulating layer 57. The sacrificial layer is etched-back so as to expose the second insulating layer 57 on the patterned metal layers 53 and first insulating layers 55 with sacrificial layer portions 59 remaining in the recesses between the patterned metal layers 53 in the step of Figure 4B. The exposed portions of the second insulating layer 57 are removed by using the remaining sacrificial layer portions as a mask in the step of Figure 4C. A third insulating layer 61 such as O 3 -TEOS USG whose deposition rate depends on the property of the lower layer 53 is formed over the first and second insulating layers 55, 57 after removing the remaining sacrificial layer portions 59. Namely, the deposition rate of the third insulating layer is greater in the region over the second insulating layer 57 than in the region over the first insulating layer 55. As a result, the portions of the third insulating layer 61 between the metal layers have a thickness great enough to compensate for the depth of the recesses between the metal layers, thus preferably planarizing the inter-metal dielectric. Thus, in the illustrated examples of the present invention, different insulating layers are exposed over different regions of a semiconductor substrate and an insulating layer whose deposition rate depends on the exposed lower layer is deposited, so that it is possible to control the thickness of the inter-metal dielectrics according to the different regions. Hence there are obtained inter-metal dielectrics without voids and a good planarization, which increases the reliability of the semiconductor devices.

Claims: A method of forming an inter-metal dielectric in a semiconductor device, comprising the steps of: sequentially forming first and second insulating layers over a semiconductor substrate having a patterned metal layer, such that portions of said first insulating layer and portions of said second insulating layer are selectively exposed; and depositing a third insulating layer on said exposed portions of said first and second insulating layers, characterised in that the deposition rate of said third insulating layer is different on said exposed portions of said first insulating layer to the rate on said exposed portions of said second insulating layer because the deposition rate of the third layer is a function of the material onto which it is being deposited. A method according to claim 1, wherein said exposed portions of said first insulating layer are over respective portions of said patterned metal layer. A method according to claim 1 or 2, wherein said exposed portions of said first insulating layer are exposed by etching-back said second insulating layer so as to form spacers of said second insulating layer over side walls of said first insulating layer. A method according to any of the preceding claims, wherein said exposed portions of said first insulating layer are exposed by: applying a sacrificial layer to said second insulating layer; etching-back said sacrificial layer so as to expose said second insulating layer on said patterned metal layer and first insulating layer, thereby leaving sacrificial layer portions between portions of said patterned metal layer; and removing the exposed portions of said second insulating layer by using said remaining sacrificial layer portions as a mask. A method according to claim 4, wherein said sacrificial layer comprises a photoresist or spin-on glass layer. A method according to any of the preceding claims, including the preliminary step of forming said patterned metal layer on said substrate. A method according to any of the preceding claims, wherein said first insulating layer comprises phospho-silicate glass (PSG), O 3 -tetra- ethyl-ortho-silicate phospho silicate glass (O 3 -TEOS PSG), O 3 -tetra-ethyl-orthosilicate boro-phospho-silicate glass (O 3 -TEOS BPSG), P-TEOS undoped silicate glass (USG) or TiN. A method according to any of the preceding claims, wherein said second insulating layer comprises plasma-enhancement silane USG (P-SiH 4 USG) or O 3 -TEOS USG. A method according to any of the preceding claims, wherein said third insulating layer comprises O 3 -TEOS USG.

Inventors: CHOI JI-HYUN, KIM CHANG-GYU, CHOI,JI-HYUN, KIM, CHANG-GYU, CHOI,JI-HYUN PROCESS DEVELOPMENT TEAM 2
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO. LTD.
Application year: 1992
Main classification: H01L21
IPC codes: H01L21, H01L23