Counter circuit using Johnson-type counter and applied circuit including the same

Abstract: A counter circuit includes Johnson-type counters (JC₁ ∼ JCm) of m stages, each counter including a plurality of flip-flops (FF₁₁ ∼ FF 1N 1 ,FF₂₁ ∼ FF 2N 2 ,... ..., FF m1 ∼ FF mNm ) connected in a cascade connection, each flip-flop receiving a clock signal (CLK) at a respective clock input end (C). In the constitution, signals at respective output ends (Q) of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends (C) of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of freguency division with high speed, while relatively simplifying the circuit constitution.

Description: The present invention relates to a counter circuit, more particularly, to a counter circuit using a Johnson-type counter and its applications. The counter circuit and its applied circuits according to the present invention can be utilized in various digital applied circuits which frequently need operations for converting a chain of serial data into parallel data of a plurality of bits, or converting parallel data of a plurality of bits into a chain of serial data. With a recent demand for high speed operation in various digital applied circuits or systems, a development of integrated circuits (IC) which can effect a signal processing with high speed has been demanded. To this end, it is necessary to effect respective operations of circuits within the IC with high speed. As an example of a counter circuit using a Johnson-type counter, a 1/N frequency-dividing circuit including a plurality of flip-flops connected in a cascade connection is known. In this constitution, the first stage flip-flop receives a clock signal and the last stage flip-flop outputs a 1/N divided signal. Accordingly, the 1/N divided signal cannot be obtained until the clock signal is applied and then passed through the flip-flops of the plurality of stages. Namely, it takes considerable time corresponding to an operation delay time of the flip-flops to obtain the 1/N divided signal. This is disadvantageous from a viewpoint of the operation speed. Also, since the flip-flops are connected in the cascade connection, a drawback arises in that the ratio of frequency division is fixed depending on the number of use of the flip-flops. As another example of a counter circuit using a Johnson-type counter, a divided signal generating circuit effecting a logical-OR operation is known. In this case, each signal input to the OR logic portion needs an input amplitude of a predetermined level. Where the input amplitude is increased, however, a problem occurs in that the operation delay time of each flip-flop is prolonged. This leads to a lowering in a maximum operation frequency of the Johnson-type counter and thus is not preferable. Note, the problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention. According to one aspect of the present invention, there is provided a counter circuit including: Johnsontype counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end, wherein signals at respective output ends of all flip-flops in a (K-1)th stage counter are simultaneously input to each clock input end of all flip-flops in each counter of a kth stage and more, via respective OR gates. Also, according to another aspect of the present invention, there is provided a counter circuit including: Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection; and (m-l) logic gates connected between each stage of the Johnson-type counters, wherein a clock signal is simultaneously input to respective clock input ends of flip-flops in a first stage counter; a logic sum of the clock signal and signals at respective output ends of flip-flops in the first stage counter is generated by a first logic gate and output as a first signal; the first signal is simultaneously input to respective clock input ends of flip-flops in a second stage counter; a logic sum of the first signal and signals at respective output ends of flip-flops in the second stage counter is generated by a second logic gate and output as a second signal; and, hereinafter in the like manner, a (m-l)-th signal is simultaneously input to respective clock input ends of flip-flops in a m-th stage counter. The present invention provides a counter circuit which can obtain a signal having an arbitrary ratio of frequency division with high speed, while relatively simplifying the circuit constitution. The present invention also provides a counter circuit using a Johnson-type counter which can heighten a maximum operation frequency thereof and thus realize a high speed operation thereof. Some examples of the present invention will be described hereinafter in detail by way of preferred embodiments and contrasted with known circuits with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a constitution of a prior art 1/16 frequency-dividing circuit; Fig. 2 is a timing chart representing the operation of the circuit of Fig. 1; Fig. 3 is a circuit diagram showing a constitution of another prior art 1/16 frequency-dividing circuit; Fig. 4 is a timing chart representing the operation of the circuit of Fig. 3; Fig. 5 is a circuit diagram showing a constitution of a prior art divided signal generating circuit; Fig. 6 is a timing chart representing the operation of the circuit of Fig. 5; Fig. 7 is a circuit diagram showing a constitution of a prior art 16-bit data demultiplexer circuit; Fig. 8 is a timing chart representing the operation of the circuit of Fig. 7; Fig. 9 is a circuit diagram showing a constitution of a prior art 16-bit data multiplexer circuit; Fig. 10 is a timing chart representing the operation of the circuit of Fig. 9; Fig. 11 is a circuit diagram showing a fundamental constitution of the counter circuit according to a first aspect of the present invention; Fig. 12 is a circuit diagram showing a fundamental constitution of the divided signal generating circuit according to a second aspect of the present invention; Fig. 13 is a circuit diagram showing a fundamental constitution of the counter circuit according to a third aspect of the present invention; Fig. 14 is a circuit diagram showing a fundamental constitution of the divided signal generating circuit according to a fourth aspect of the present invention; Fig. 15 is a block diagram showing a fundamental constitution of the data converting circuit according to a fifth aspect of the present invention; Fig. 16 is a block diagram showing a fundamental constitution of the data converting circuit according to a sixth aspect of the present invention; Fig. 17 is a circuit diagram showing a fundamental constitution of a counter circuit; Fig. 18 is a timing chart representing the operation of the circuit of Fig. 17; Fig. 19 is a circuit diagram showing a constitution of the 1/16 frequency-dividing circuit according to an embodiment corresponding to the first aspect of the present invention; Fig. 20 is a timing chart representing the operation of the circuit of Fig. 19; Fig. 21 is a circuit diagram showing a constitution of the divided signal generating circuit according to an embodiment corresponding to the second aspect of the present invention; Fig. 22 is a timing chart representing the operation of the circuit of Fig. 21; Fig. 23 is a circuit diagram showing a constitution of the 1/16 frequency-dividing circuit according to an embodiment corresponding to the third aspect of the present invention; Fig. 24 is a timing chart representing the operation of the circuit of Fig. 23; Fig. 25 is a circuit diagram showing a constitution of the divided signal generating circuit according to an embodiment corresponding to the fourth aspect of the present invention; Fig. 26 is a timing chart representing the operation of the circuit of Fig. 25; Fig. 27 is a circuit diagram showing a constitution of the 16-bit data demultiplexer circuit according to an embodiment corresponding to the fifth aspect of the present invention; Fig. 28 is a timing chart representing the operation of the circuit of Fig. 27; Fig. 29 is a circuit diagram showing a constitution of the 16-bit data multiplexer circuit according to an embodiment corresponding to the sixth aspect of the present invention; Fig. 30 is a timing chart representing the operation of the circuit of Fig. 29; Fig. 31 is a circuit diagram showing a constitution of the divided signal generating circuit according to an embodiment of the present invention utilizing the counter circuit of Figure 17; Fig. 32 is a timing chart representing the operation of the circuit of Fig. 31; Fig. 33 is a circuit diagram showing a constitution of the divided signal generating circuit according to another embodiment of the present invention utilizing the counter circuit of Figure 17; Fig. 34 is a timing chart representing the operation of the circuit of Fig. 33; Fig. 35 is a circuit diagram showing a constitution of the 16-bit data demultiplexer circuit as an application example of the circuit of Fig. 31; and Fig. 36 is a circuit diagram showing a constitution of the 16-bit data multiplexer circuit as another application example of the circuit of Fig. 31. Throughout the description, identical references used in connection with the drawings indicate like constituent elements and thus the repetition of explanation thereof is omitted. First, for a better understanding of the preferred embodiments of the present invention, the related prior art will be explained with reference to Figs. 1 to 10. Figure 1 illustrates a constitution of a prior art 1/16 frequency-dividing circuit, and Fig. 2 shows a timing chart representing the operation thereof. The circuit of Fig. 1 includes four flip-flops FF1 to FF4. The first stage flip-flop FF1 receives a clock signal CLK at a clock input end C and, hereinafter in the like manner, the following stage flip-flop receives a signal from an output end Q of the preceding stage flip-flop at the clock input end C. Finally, the last stage flip-flop FF4 outputs a 1/16 divided signal from the output end Q. Accordingly, as shown in the timing chart of Fig. 2, time taken until the 1/16 divided signal is obtained from a point of time of the application of the clock signal CLK is t 4F corresponding to an operation delay time of the flip-flops of four stages. Figure 3 illustrates a constitution of another prior art 1/16 frequency-dividing circuit, and Fig. 4 shows a timing chart representing the operation thereof. The circuit of Fig. 3 has a form of a Johnson-type counter including eight flip-flops FF1 to FF8 connected in a cascade connection. Each flip-flop simultaneously receives a clock signal CLK at a respective clock input end C and the last stage flip-flop FF8 outputs a 1/16 divided signal from the output end Q. According to the constitution, as shown in the timing chart of Fig. 4, time taken until the 1/16 divided signal is obtained from a point of time of the application of the clock signal CLK is no more than t F corresponding to an operation delay time of the flip-flop of one stage. On the other hand, the number of flip-flops used in the constitution is no less than eight. Figure 5 illustrates a constitution of a prior art divided signal generating circuit, and Fig. 6 shows a timing chart representing the operation thereof. The illustrated circuit 10b includes a logical OR gate LG in addition to the 1/16 frequency-dividing circuit of Fig. 3. The OR gate LG generates a logic sum of the clock signal CLK and signals at respective output ends Q of all of the flip-flops FF1 to FF8 and outputs a result thereof as a data load pulse DLP. According to the constitution, as shown in the timing chart of Fig. 6, time taken until the data load pulse DLP is obtained from a point of time of the application of the clock signal CLK is no more than t G corresponding to an operation delay time of the gate of one stage. On the other hand, the number of flip-flops used in the constitution is no less than eight. Figure 7 illustrates a constitution of a prior art 16-bit data demultiplexer circuit, and Fig. 8 shows a timing chart representing the operation thereof. The illustrated circuit includes the divided signal generating circuit 10b of Fig. 5, a delay circuit DLY for generating a delayed clock signal DCLK in response to the clock signal CLK, a serial/parallel converting circuit having sixteen flip-flops FF 101 to FF 1 16 connected in a cascade connection, and a latch circuit having sixteen flip-flops FF 201 to FF 2 16 , each flip-flop responsive to the data load pulse DLP output from the divided signal generating circuit 10b, latching respective outputs of the serial/parallel converting circuit and outputting the latched data as parallel data OUT16 to OUT1. The delay circuit DLY has the function of delaying the clock signal CLK by a predetermined delay time corresponding to the number of stage of gates and outputting the delayed clock signal DCLK. Also, the divided signal generating circuit 10b has the function of outputting the data load pulse DLP at an appropriate timing after data is set in the flip-flops FF 201 to FF 2 16 of the latch circuit. Namely, the serial/parallel converting circuit sequentially inputs a chain of serial data D in response to the delayed clock signal DCLK, and outputs the parallel data OUT16 to OUT1 in response to the data load pulse DLP and holds the parallel data until a next 16-bit data is input thereto. An example of the art is disclosed, for example, in Japanese unexamined patent publication No.3-22712. Figure 9 illustrates a constitution of a prior art 16-bit data multiplexer circuit, and Fig. 10 shows a timing chart representing the operation thereof. The illustrated circuit includes the divided signal generating circuit 10b of Fig. 5, a delay circuit DLY for generating a delayed clock signal DCLK in response to the clock signal CLK, and a parallel/serial converting circuit having sixteen selectors SEL 01 to SEL 1 6 and sixteen flip-flops FF 3 01 to FF 316 connected sequentially and alternately to one another. The delay circuit DLY has the function of delaying the clock signal CLK by a predetermined delay time corresponding to the number of stage of gates and outputting the delayed clock signal DCLK. Also, the divided signal generating circuit 10b has the function of outputting the data load pulse DLP when a new 16-bit data is taken into the parallel/serial converting circuit by the selectors SEL 01 to SEL 16 . Namely, the parallel/serial converting circuit inputs a 16-bit data by means of the selectors SEL 01 to SEL 1 6 in response to the data load pulse DLP and then, in response to the delayed clock signal DCLK, outputs the 16-bit parallel data as a chain of serial data OUT, bit by bit. According to the prior art constitution of Fig. 1, the 1/16 divided signal cannot be obtained until the clock signal CLK is applied to the first stage flip-flop FF1 and then passed through the flip-flops of four stages (FF1 to FF4). Namely, it takes the time t 4F corresponding to the operation delay time of the flip-flops of four stages to obtain the 1/16 divided signal. This is disadvantageous from a viewpoint of the operation speed. Also, since the flip-flops are connected in the cascade connection, a problem occurs in that the ratio of frequency division is fixed depending on the number of use of the flip-flops. This lays a restriction on the utilization or application of the frequency-dividing circuit due to the frequency being fixed, and thus is not preferable. Although the prior art constitution of Fig. 3 has an advantage in that it is possible to obtain the 1/16 divided signal with higher speed than in the circuit constitution of Fig. 1, it poses a problem in that the circuit constitution relatively becomes complicated because the number of use of the flip-flops is more than that in Fig. 1. Furthermore, the like problems are present in the prior art divided signal generating circuit 10b of Fig. 5 which uses the counter circuit (1/16 frequency-dividing circuit) containing the above problems, the prior art data demultiplexer circuit of Fig. 7 using the divided signal generating circuit 10b, and the prior art data multiplexer circuit of Fig. 9 using the divided signal generating circuit 10b. Also, according to the prior art constitution using a Johnson-type counter effecting a logical OR operation as shown in Fig. 5, respective signals input to the OR logic portion (OR gate LG), i.e., the clock signal CLK and the signals at the respective output ends Q of the flip-flops FF1 to FF8, need an input amplitude of level so sufficient as to be compared with a reference level within the OR gate LG. In this case, the operation delay time of each flip-flop depends upon a magnitude of the input amplitude. Therefore, a problem occurs in that the operation delay time of each flip-flop is prolonged where the input amplitude is increased. As a result, a maximum operation frequency of the Johnsontype counter is lowered and thus an operation speed of the entire circuit is decreased. Figure 11 illustrates a fundamental constitution of the counter circuit according to a first aspect of the present invention. The illustrated circuit includes Johnson-type counters JC 1 ∼ JCm of m stages, each counter including a plurality of flip-flops FF 11 ∼ FF 1N 1 ,FF 21 ∼ FF 2N 2 ,... ...,FF m1 ∼ FF mNm connected in a cascade connection, each flip-flop receiving a clock signal CLK at a respective clock input end C, wherein signals at respective output ends Q of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends C of flip-flops in each counter of a k-th stage and more. Figure 12 illustrates a fundamental constitution of the divided signal generating circuit according to a second aspect of the present invention. The illustrated circuit includes the counter circuit shown in Fig. 11, and a logic gate LG which generates a logic sum of the clock signal and signals at respective output ends of all of the flip-flops in the counter circuit and outputs a result thereof as a m-th signal. Figure 13 illustrates a fundamental constitution of the counter circuit according to a third aspect of the present invention. The illustrated circuit includes Johnson-type counters JCC 1 ∼ JCCm of m stages, each counter including a plurality of flip-flops FF 11 ∼ FF 1N 1 , FF 21 ∼ FF 2N 2 ,... ... FF m1 ∼ FF mNm connected in a cascade connection, and (m-1) logic gates LG 1 ∼ LG m-1 connected between each stage of the Johnson-type counters, wherein a clock signal CLK is simultaneously input to respective clock input ends C of flip-flops in a first stage counter JCC 1 ; a logic sum of the clock signal and signals at respective output ends Q of flip-flops in the first stage counter is generated by a first logic gate LG 1 and output as a first signal S 1 ; the first signal is simultaneously input to respective clock input ends C of flip-flops in a second stage counter JCC 2 ; a logic sum of the first signal and signals at respective output ends Q of flip-flops in the second stage counter is generated by a second logic gate LG 2 and output as a second signal S 2 ; and, hereinafter in the like manner, a (m-1)-th signal S m-1 is simultaneously input to respective clock input ends C of flip-flops in a m-th stage counter JCCm. Figure 14 illustrates a fundamental constitution of the divided signal generating circuit according to a fourth aspect of the present invention. The illustrated circuit includes the counter circuit shown in Fig. 13, and a logic gate LGm which generates a logic sum of the (m-1)-th signal and signals at respective output ends of flip-flops in the m-th stage counter and outputs a result thereof as a m-th signal Sm (DLP). Figure 15 illustrates a fundamental constitution of the data converting circuit according to a fifth aspect of the present invention. The illustrated circuit includes the divided signal generating circuit 10 (20) shown in Fig. 12 or Fig. 14, a unit 11 for inputting a serial data SD in response to the clock signal CLK and converting the serial data into a parallel data PD of a plurality of bits, and a unit 12 for latching and outputting the parallel data in response to the m-th signal DLP output from the divided signal generating circuit. Figure 16 illustrates a fundamental constitution of the data converting circuit according to a sixth aspect of the present invention. The illustrated circuit includes the divided signal generating circuit 10 (20) shown in Fig. 12 or Fig. 14, and a unit 13 for inputting a parallel data PD of a plurality of bits in response to the m-th signal DLP output from the divided signal generating circuit and converting the parallel data into a serial data SD in response to the clock signal CLK, to thereby output the converted serial data. Figure 17 illustrates a fundamental constitution of a counter circuit. The illustrated circuit includes a Johnson-type counter JC including a plurality of flip-flops FF 1 ∼ FFn connected in a cascade connection, each flip-flop simultaneously receiving a clock signal CLK at a respective clock input end C, and a gate unit GT for generating a logic sum of the clock signal and signals at respective output ends Q, QX of the flip-flops in the counter. The Johnson-type counter includes a buffer unit G 0 , G 1 ∼Gn for regulating respective timings at which the clock signal and the signals at the respective output ends of each flip-flop are input to the gate unit, non-inverting and inverting outputs of a last stage flip-flop FFn being input to data inverting and data non-inverting input ends of a first stage flip-flop FF 1 , respectively, and operation amplitude levels of respective differential signal outputs of the flip-flops being set to be smaller than those of other circuits. According to the first aspect (Fig. 11) and the third aspect (Fig. 13) of the present invention, the ratio of frequency division is expressed as follows: 1 / {2 · (N 1 )} × 1 / {2 ·(N 2 )} × 1 / {2 · (N 3 )} × ··· ··· ··· ··· × 1 / {2 · (Nm)} Note, reference Nm denotes the number of flip-flops in the m-th stage counter JCm (JCCm), where m indicates an integer more than two (m ≧ 2). As is obvious from the formula (1), it is possible to arbitrarily set the division ratio by suitably selecting the number N 1 , N 2 , ··· ···, Nm of flip-flops in the respective stage counters. An example of selection of the division ratio is shown in Table below. DIV. RATIO N 1 N 2 N 3 N 4 1/2 1 1/4 2 1/6 3 1/8 2 1 : 1/16 2 2 : 1/24 3 2 : 1/32 2 2 1 : 1/64 2 2 2 : 1/128 2 2 2 1 : 1/256 2 2 2 2 Also, according to the second aspect (Fig. 12) and the fourth aspect (Fig. 14) of the present invention, it is possible to output a clock signal (pulse) one time in one period or cycle of an output signal having the division ratio expressed by the formula (1). Also, according to the fifth aspect (Fig. 15) and the sixth aspect (Fig. 16) of the present invention, it is possible to obtain the effects dependent on the second aspect or the fourth aspect. In the counting circuit of Figure 17, since the operation amplitude level of respective differential signal outputs of the flip-flops FF 1 to FFn constituting the Johnson-type counter JC is set to be smaller than that of other circuits, it is possible to quickly change a level of the output of each flip-flop, from "L" level to "H" level, or from "H" level to "L" level. Namely, it is possible to reduce the operation delay time of each flip-flop and thus heighten a maximum operation frequency of the Johnson-type counter JC. This contributes to a high speed operation of the entire counter circuit. In this connection, buffer gates G 0 and G 1 ∼ Gn are provided for regulating respective timings at which the clock signal CLK and the signals at the respective output ends of each flip-flop are input to the gate means (OR gate GT). Each buffer gate G 1 , G 2 ,... ... , Gn receives a differential signal of small amplitude from the corresponding flip-flop, and amplifies the differential signal up to an amplitude level which is necessary and sufficient for the logic operation in the OR gate GT. On the other hand, the buffer gate G 0 functions as a gate for phase regulation. The operation of the counter circuit of Fig. 17 will now be explained with reference to the timing chart of Fig. 18. In Fig. 18, reference T denotes a period of the clock signal CLK; reference t F an operation delay time of the flip-flop of one stage; reference t G1 an operation delay time of each buffer gate G 0 ∼ Gn; and reference t G2 an operation delay time of the OR gate GT. First, it is assumed that respective non-inverting outputs "Q" (inverting outputs "QX") of each flip-flop FF 1 to FFn are all in "L" level ("H" level) in the initial state. In this state, when the first clock signal CLK(1) is applied, the non-inverting output Q of the first stage flip-flop FF 1 is made "H" level by the inverting output QX of the last stage flip-flop FFn. The change of the level is transmitted through the buffer gate G 1 . Accordingly, the timing at which the output P 1 of the gate G 1 is made "H" level is after a lapse of the delay time of (t F + t G1 ) from the rise edge of the input clock signal CLK. In the like manner, when the non-inverting output Q of the flip-flop FF 1 is made "L" level, the output P 1 of the gate G 1 is made "L" level after a lapse of the delay time of (t F + t G1 ) from the rise edge of the (n+1)-th clock signal CLK(n+1). At the point of time of the application of the first clock signal CLK(1), respective non-inverting outputs Q of other flip-flops FF 2 to FFn still remain "L" level. At the point of time after the application of the first clock signal CLK(1), however, the non-inverting output Q of the second stage flip-flop FF 2 is made "H" level upon receipt of the second clock signal CLK(2). Hereinafter in the like manner, the non-inverting output Q of the last stage flip-flop FFn remains "L" level until the application of the (n-1)-th clock signal CLK(n-1) and, when the n-th clock signal CLK(n) is applied, the output Q of the flip-flop FFn is made "H" level after a lapse of the delay time of (t F + t G1 ). Also, when the 2n-th clock signal CLK(2n) is applied, the output Q of the flip-flop FFn is made "L" level after a lapse of the delay time of (t F + t G1 ). As a result, the outputs Q of each flip-flop FF 1 to FFn are all brought to "L" level (initial state). Thus, the outputs Q of all of the flip-flops are brought to "L" level every time the clock signal CLK is input 2n times. At this time, the edge of the clock signal CLK passing through the buffer gate G 0 becomes effective, and thus the OR gate GT outputs a pulse as shown by reference t x in Fig. 18. In this case, as a condition based on which the OR gate GT can output a pulse having rise and fall edges, it is necessary for the pulse width t x to have a margin. To this end, it is necessary to make the fall timing of the output of the OR gate GT (i.e., the fall timing of the input signal thereof) quicker. The fall timing is determined by a condition 1 ○ after a lapse of the operation delay time t G1 of the buffer gate G 0 from the fall edge of the clock signal CLK passing through the gate G 0 , or a condition 2 ○ after a lapse of the operation delay times t F and t G1 of the flip-flop FFn and the buffer gate Gn from the rise edge of the clock signal CLK. With an increase in the frequency of the clock signal CLK, however, the fall edge of the output of the OR gate GT is determined by the condition 2 ○. The pulse width t x of the output of the OR gate GT is expressed as follows: t x = (T + t G1 + t G2 ) - (t F + t G1 + t G2 ) = T - t F Assuming that the operation delay time t F of the flip-flop is a specific value, the shorter the period T of the clock signal CLK becomes, the less the margin of the pulse width t x becomes. Where the time t x has little margin, a problem occurs in that the edge of the clock signal CLK becomes ineffective and thus it becomes impossible to output a desired pulse signal at the output of the OR gate GT. From the above, it is appreciated that it is possible to give a sufficient margin to the pulse width t x by reducing the operation delay time t F of each flip-flop FF 1 to FFn. Even if the frequency of the clock signal CLK is increased, the output of the OR gate GT can be output without error. To reduce the operation delay time of each flip-flop, the operation amplitude level of the differential signal output of each flip-flop is selected to be smaller than that of other circuits. By the feature, it is possible to increase the operation speed of each flip-flop and thus heighten the maximum operation frequency of the counter. Next, the preferred embodiments of the present invention will be explained with reference to Figs. 19 to 36. Figure 19 illustrates a constitution of the 1/16 frequency-dividing circuit according to an embodiment corresponding to the first aspect of the present invention, and Fig. 20 shows a timing chart representing the operation thereof. The circuit of Fig. 19 includes Johnson-type counters JC 1 and JC 2 of two stages. The number of stage of the connection of flip-flops in the first stage counter JC 1 is two (FF 11 , FF 12 ), and that in the second stage counter JC 2 is also two (FF 21 , FF 22 ). This corresponds to N 1 = N 2 = 2 in the aforementioned Table. Signals at respective output ends Q of the flip-flops FF 11 , FF 1 2 in the first stage counter JC 1 are input via OR gates G 2 1 and G 2 2 in the second stage counter JC 2 to respective clock input ends C of the flip-flops FF 21 , FF 2 2 in the counter JC 2 . Also, a clock signal CLK is input to the respective clock input ends C of the flip-flops FF 11 , FF 1 2 in the first stage counter JC 1 , and input via the OR gates G 21 , G 2 2 in the second stage counter JC 2 to the respective clock input ends C of the flip-flops FF 21 , FF 22 . Finally, the flip-flops FF 21 , FF 22 in the second stage counter JC 2 output a 1/16 divided signal from the respective output ends Q. In Fig. 20, reference t F denotes an operation delay time of the flip-flop of one stage. According to the constitution of the present embodiment, as shown in the timing chart of Fig. 20, time taken until the 1/16 divided signal is obtained from a point of time of the application of the clock signal CLK is no more than t F corresponding to the operation delay time of the flip-flop of one stage (FF 1 1 or FF 12 ). Contrary to this, according to the prior art (see Figs. 1 and 2), the 1/16 divided signal cannot be obtained until the clock signal CLK is applied to the first stage flip-flop FF1 and then passed through the flip-flops of four stages (FF1 to FF4). Namely, it is possible to reduce the whole operation delay time required for obtaining the 1/16 divided signal, while using flip-flops of the same number (i.e., four) as that in the prior art (see Fig. 1). This contributes to a high speed operation of the entire circuit. Also, since the number of flip-flops used for obtaining the 1/16 divided signal is no more than four, it is possible to relatively simplify the circuit constitution, as compared with the prior art. Figure 21 illustrates a constitution of the divided signal generating circuit according to an embodiment corresponding to the second aspect of the present invention, and Fig. 22 shows a timing chart representing the operation thereof. The divided signal generating circuit 10a of the present embodiment utilizes the output of the 1/16 frequency-dividing circuit of Fig. 19. Namely, the circuit 10a includes an OR gate LG which generates a logic sum of the clock signal CLK and the signals at the respective output ends Q of all of the flip-flops FF 11 , FF 12 , FF 21 and FF 2 2 and outputs a result thereof as a data load pulse signal DLP. In Fig. 22, reference t F denotes the operation delay time of the flip-flop of one stage, and reference t G denotes an operation delay time of the gate of one stage. According to the constitution of the present embodiment, as shown in the timing chart of Fig. 22, it is possible to output a clock signal (data load pulse DLP) one time in one period or cycle of the 1/16 divided signal obtained from the 1/16 frequency-dividing circuit of Fig. 19. Figure 23 illustrates a constitution of the 1/16 frequency-dividing circuit according to an embodiment corresponding to the third aspect of the present invention, and Fig. 24 shows a timing chart representing the operation thereof. The circuit of Fig. 23 includes Johnson-type counters JCC 1 and JCC 2 of two stages and an OR gate LG 1 connected between each counter. The number of stage of the connection of flip-flops in the first stage counter JCC 1 is two (FF 11 , FF 12 ), and that in the second stage counter JCC 2 is also two (FF 21 , FF 22 ). Signals at respective output ends Q of the flip-flops FF 11 , FF 1 2 in the first stage counter JCC 1 are input to the OR gate LG 1 . Also, a clock signal CLK is input to the OR gate LG 1 and respective clock input ends C of the flip-flops FF 11 , FF 1 2 in the first stage counter JCC 1 . Also, an output of the OR gate LG 1 (first signal S 1 ) is input to respective clock input ends C of the flip-flops FF 21 , FF 22 in the second stage counter JCC 2 . Finally, the flip-flops FF 21 , FF 2 2 in the second stage counter JCC 2 output a 1/16 divided signal from the respective output ends Q. In Fig. 24, reference t F denotes the operation delay time of the flip-flop of one stage, and reference t G denotes the operation delay time of the gate of one stage. According to the constitution of the present embodiment, as shown in the timing chart of Fig. 24, time taken until the 1/16 divided signal is obtained from a point of time of the application of the clock signal CLK is no more than (t F + t G ) corresponding to the operation delay times of the flip-flop of one stage and the gate of one stage (LG 1 ). Contrary to this, according to the prior art (see Figs. 1 and 2), the 1/16 divided signal cannot be obtained until the clock signal CLK is passed through the flip-flops of four stages. Namely, it is possible to relatively reduce the whole operation delay time required for obtaining the 1/16 divided signal, while using flip-flops of the same number (i.e., four) as that in the prior art (see Fig. 1). Also, since the 1/16 divided signal can be obtained using no more than four flip-flops and one logic gate, it is possible to relatively simplify the circuit constitution, as compared with the prior art. Figure 25 illustrates a constitution of the divided signal generating circuit according to an embodiment corresponding to the fourth aspect of the present invention, and Fig. 26 shows a timing chart representing the operation thereof. The divided signal generating circuit 20a of the present embodiment utilizes the output of the 1/16 frequency-dividing circuit of Fig. 23. Namely, the circuit 20a includes an OR gate LG 2 which generates a logic sum of the first signal S 1 (output of the OR gate LG 1 ) and the signals at the respective output ends Q of the flip-flops FF 21 , FF 2 2 in the second stage counter JCC 2 and outputs a result thereof as a second signal S 2 (data load pulse DLP). In Fig. 26, reference t F denotes the operation delay time of the flip-flop of one stage, and reference t G denotes the operation delay time of the gate of one stage. According to the constitution of the present embodiment, as shown in the timing chart of Fig. 26, it is possible to output a clock signal (data load pulse DLP) one time in one period or cycle of the 1/16 divided signal obtained from the 1/16 frequency-dividing circuit of Fig. 23. Figure 27 illustrates a constitution of the 16-bit data demultiplexer circuit according to an embodiment corresponding to the fifth aspect of the present invention, and Fig. 28 shows a timing chart representing the operation thereof. The circuit constitution of Fig. 27 is different from that of Fig. 7 (prior art) in that the divided signal generating circuit 10a (see Fig. 21) is provided in place of the prior art divided signal generating circuit 10b (see Fig. 5). Other constitution is the same as that of Fig. 7 and thus the explanation thereof is omitted. The circuit of the present embodiment can produce effects dependent on the embodiments of Figs. 19 and 21. Figure 29 illustrates a constitution of the 16-bit data multiplexer circuit according to an embodiment corresponding to the sixth aspect of the present invention, and Fig. 30 shows a timing chart representing the operation thereof. The circuit constitution of Fig. 29 is different from that of Fig. 9 (prior art) in that the divided signal generating circuit 10a (see Fig. 21) is provided in place of the prior art divided signal generating circuit 10b (see Fig. 5). Other constitution is the same as that of Fig. 9 and thus the explanation thereof is omitted. In this embodiment as well, it is possible to obtain effects dependent on the embodiments of Figs. 19 and 21. Although, in each embodiment, the 1/16 divided signal is obtained using the Johnson-type counters JC 1 , JC 2 (JCC 1 , JCC 2 ) ) of two stages each having two flip-flops, the ratio of frequency division is not restrictive to 1/16. As is obvious from the gist of the present invention, it is possible to arbitrarily select the division ratio by suitably selecting the number of stages of the Johnson-type counter or the number of flip-flops in each counter. Figure 31 illustrates a constitution of the divided signal generating circuit according to an embodiment of the present invention, utilizing the counting circuit of Figure 17, and Fig. 32 shows a timing chart representing the operation thereof. The divided signal generating circuit 10a' of the present embodiment is different from the divided signal generating circuit 10a shown in Fig. 21 in that the Johnson-type counter JC (see Fig. 17) is provided in place of the Johnson-type counter JC 1 . Other constitution is the same as that of Fig. 21 and thus the explanation thereof is omitted. According to the present embodiment, it is possible to increase the operation speed of each flip-flop FF 11 , FF 1 2 in the first stage counter JC, as explained in connection with Figs. 17 and 18. As a result, it is possible to reduce the operation delay time of each flip-flop FF 11 , FF 1 2 and thus heighten a maximum operation frequency of the Johnson-type counter JC. This contributes to a high speed operation of the entire circuit. In Fig. 32, reference t G denotes an operation delay time of each gate of one stage, reference t F1 denotes an operation delay time of each flip-flop of one stage in the first stage counter JC, and reference t F2 denotes an operation delay time of each flip-flop of one stage in the second stage counter JC 2 . The operation of the present circuit is easily deduced from the explanation described in connection with Fig. 18 and thus the explanation thereof is omitted. Figure 33 illustrates a constitution of the divided signal generating circuit according to another embodiment of the present invention, utilizing the counter circuit of Figure 17, and Fig. 34 shows a timing chart representing the operation thereof. The divided signal generating circuit 20a' of the present embodiment is different from the divided signal generating circuit 20a shown in Fig. 25 in that the Johnson-type counter JC (see Fig. 17) is provided in place of the Johnson-type counter JCC 1 . Other constitution is the same as that of Fig. 25 and the operation and effects of the entire circuit are easily deduced from the explanation described in connection with Figs. 17 and 18, and thus the explanations thereof are omitted. Figures 35 and 36 illustrate constitutions of the 16-bit data demultiplexer circuit and the 16-bit data multiplexer circuit, respectively, as application examples of the divided signal generating circuit 10a' of Fig. 31. Respective circuits are different from the corresponding circuits shown in Figs. 27 and 29 in that the divided signal generating circuit 10a' (see Fig. 31) is provided in place of the divided signal generating circuit 10a. Other constitutions are the same as those of Figs. 27 and 29 and the operation and effects of the entire circuit are easily deduced from the explanation described in connection with Figs. 17 and 18, and thus the explanations thereof are omitted.

Claims: A counter circuit comprising: Johnson-type counters (JC,∼JCm) of m stages, each counter including a plurality of flip-flops (FF 11 ∼FF 21 ∼FF 2N2 , ... ... FF m1 ∼FF mNm ) connected in a cascade connection, each flip-flop receiving a clock signal (CLK) at a respective clock input end (C), wherein signals at respective output ends (Q) of all flip-flops in a (k-l)-th stage counter are simultaneously input to each clock input end (C) of all flip-flops in each counter of a k-th stage and more, via respective OR gates. A counter circuit as set forth in claim 1, wherein each counter of a second stage and more comprises a gate means (G 21 , G 22 ) for simultaneously receiving the clock signal and the signals from the respective output ends of flip-flops in each counter of the preceding stage or stages. A divided signal generating circuit comprising: a counter circuit according to claim 1 or claim 2, and a logic gate (LG) which generates a logic sum of the clock signal and signals at respective output ends of all of the flip-flops in the counter circuit and outputs a result thereof as a m-th signal (DLP). A data converting circuit comprising: a divided signal generating circuit (10, 20) according to claim 3, means (11) for inputting a serial data (SD) in response to the clock signal (CLK) and converting the serial data into a parallel data (PD) of a plurality of bits; and means (12) for latching and outputting the parallel data in response to the m-th signal (DLP) output from the divided signal generating circuit. A data converting circuit comprising: a divided signal generating circuit (10, 20) according to claim 3, and means (13) for inputting a parallel data (PD) of a plurality of bits in response to the m-th signal (DLP) output from the divided signal generating circuit and converting the parallel data into a serial data (SD) in response to the clock signal (CLK), to thereby output the converted serial data. A divided signal generating circuit comprising: a counter circuit according to claim 1 or claim 2, and a first stage Johnson-type counter (JC) including a buffer means (G 0 , G 1 , G 2 ) for regulating respective timings at which the clock signal and signals at respective output ends of each flip-flop in the self counter are input to respective clock input ends of flip-flops in each counter of a second stage and more, non-inverting and inverting outputs of a last stage flip-flop (FF 12 ) being input to data inverting and data non-inverting input ends of a first stage flipflop (FF 11 ), respectively, and operation amplitude levels of respective differential signal outputs of the flip-flops in the self counter being set to be smaller than those of other circuits. A divided signal generating circuit as set forth in claim 6, further comprising a logic gate (LG) which generates a logic sum of the clock signal and signals at respective output ends of all of the flipflops in the counter circuit and outputs a result thereof as a m-th signal (DLP). A divided signal generating circuit as set forth in claim 7, wherein the buffer means comprises means (G 0 ) for phase regulation and means (G 1 , G 2 ) for receiving respective differential signals of small amplitude from each flip-flop and amplifying the differential signals up to an amplitude level which is necessary and sufficient for the logic operation in the gate means. A data demultiplexer circuit comprising: a divided signal generating circuit (10a') according to claim 7 or claim 8; means (FF 101 ∼FF 116 ) for inputting a serial data (SD) in response to the clock signal (CLK, DCLK) and converting the serial data into a parallel data (OUT16∼OUTl) of a plurality of bits; and means (FF 201 ∼FF 216 ) for latching and outputting the parallel data in response to the m-th signal (DLP) output from the divided signal generating circuit. A data multiplexer circuit comprising: a divided signal generating circuit (10a') according to claim 7 or claim 8; ;and means (SEL 01 ∼SEL 16 , FF 301 ∼FF 316 ) for inputting a parallel data (D16∼D1) of a plurality of bits in resp#nse to the m-th signal (DLP) output from the divided signal generating circuit and converting the parallel data into a serial data (OUT) in response to the clock signal (CLK, DCLK), to thereby output the converted serial data. A counter circuit comprising: Johnson-type counters (JCC 1 ∼JCCm) of m stages, each counter including a plurality of flipflops (FF 11 ∼FF 21 ∼FF 2N2 , ... ... FF m1 ∼FF mNm ) connected in a cascade connection; and (m-l) logic gates (LG 1 ∼LG m-1 ) connected between each stage of the Johnson-type counters, wherein a clock signal (CLK) is simultaneously input to respective clock input ends (C) of flip-flops in a first stage counter (JCC 1 ); a logic sum of the clock signal and signals at respective output ends (Q) of flip-flops in the first stage counter is generated by a first logic gate (LG 1 ) and output as a first signal (S 1 ); the first signal is simultaneously input to respective clock input ends (C) of flip-flops in a second stage counter (JCC 2 ); a logic sum of the first signal and signals at respective output ends (Q) of flip-flops in the second stage counter is generated by a second logic gate (LG 2 ) and output as a second signal (S 2 ); and, hereinafter in the like manner, a (m-l)-th signal (S m-1 ) is simultaneously input to respective clock input ends (C) of flip-flops in a m-th stage counter (JCCm). A divided signal generating circuit comprising: a counter circuit according to claim 11; and a logic gate (LGm) which generates a logic sum of the (m-l)-th signal and signals at respective output ends of flip-flops in the m-th stage counter and outputs a result thereof as a m-th signal (Sm, DLP). A data converting circuit comprising a divided signal generating circuit (10, 20) according to claim 12; and means (11) for inputting a serial data (SD) in response to the clock signal (CLK) and converting the serial data into a parallel data (PD) of a plurality of bits; and means (12) for latching and outputting the parallel data in response to the m-th signal (DLP) output from the divided signal generating circuit. A data converting circuit comprising: a divided signal generating circuit (10, 20) according to claim 12; and means (13) for inputting a parallel data (PD) of a plurality of bits in response to the m-th signal (DLP) output from the divided signal generating circuit and converting the parallel data into a seria] data (SD) in response to the clock signal (CLK), tO thereby output the converted serial data. A divided signal generating circuit comprising: a counter circuit according to claim 11; a first stage Johnson-type counter (JC) including a buffer means (G 0 , G 1 , G 2 ) for regulating respective timings at which the clock signal and signals at respective output ends of each flip-flop in the self counter are input to the first logic gate, non-inverting and inverting outputs of a last stage flip-flop (FF 12 ) being input to data inverting and data non-inverting input ends of a first stage flip-flop (FF 11 ), respectively, and operation amplitude levels of respective differential signal outputs of the flipflops in the self counter being set to be smaller than those of other circuits. A divided signal generating circuit as set forth in claim 15, further comprising a logic gate (LG, ) which generates a logic sum of the (m-l)-th signal and signals at respective output ends of flip-flops in the m-th stage counter and outputs a result thereof as a m-th signal (DLP). A divided signal generating circuit as set forth in claim 16, wherein the buffer means comprises means (G 0 ) for phase regulation and means (G 1 ,G 2 ) for receiving respective differential signals of small amplitude from each flip-flop and amplifying the differential signals up to an amplitude level which is necessary and sufficient for the logic operation in the gate means. A data demultiplexer circuit comprising a divided signal generating circuit according to claim 16; means (FF 101 ∼FF 116 ) for inputting a serial data (SD) in response to the clock signal (CLK, DCLK) and convertihg the serial data into a parallel data (OUT16--OUTl) of a plurality of bits; and means (FF 201 ∼FF 216 ) for latching and outputting the parallel data in response to the m-th signal (DLP) output from the divided signal generating circuit. A data multiplexer circuit comprising: a divided signal generating circuit according to claim 16; and means (SEL 01 ∼SEL 16 , FF 301 ∼FF 316 ) for inputting a parallel data (D16∼Dl) of a plurality of bits in response to the m-th signal (DLP) output from the divided signal generating circuit and converting the parallel data into a serial data (OUT) in response to the clock signal (CLK, DCLK), to thereby output the converted serial data.

Inventors: NOMURA KATSUMOBU, SHIOTSU SHINICHI, TAMAMURA MASAYA, NOMURA, KATSUMOBU, SHIOTSU, SHINICHI, TAMAMURA, MASAYA, Nomura, Katsumobu, c/o Fujitsu Limited, Shiotsu, Shinichi, c/o Fujitsu Limited, Tamamura, Masaya, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: H03K23
IPC codes: H03M9, H03K23