Method of programming flash EEPROM cell arrays

Abstract: An improved method of programming EEPROM cells in a memory array, wherein a cell page can be programmed and erased without disturbing other cell pages in the array, and further, an individual cell can be reprogrammed without disturbing other cells in the array. The user can selectively erase and program cells in the array by controlling the operating conditions of the word lines, bit lines, and Vss lines coupled to those cells according to the method of the present invention.

Description: This invention relates generally to flash EEPROM cells, and more particularly to a method of programming EEPROM cells. Erasable read-only memory cells, widely known as EPROMs, are a versatile type of nonvolatile semiconductor memory. A typical N-channel EPROM cell is composed of an N-channel silicon-gate storage transistor which uses a floating first layer polysilicon gate (floating gate), which is directly accessed via a second stacked polysilicon gate (control gate), to trap and store electrons for extremely long periods of time. The N-channel EPROM cell is considered to be in a programmed state when the floating gate has a net negative charge due to the presence of "hot electrons" injected from the drain. When the cell is in a programmed state, the electrons on the floating gate keep the N-channel transistor in a logical off state. Conversely, the cell is considered to be in an erased state when there are no electrons on the floating gate and thus no net negative charge on the gate. To erase the cell, the energy of the electrons stored on the floating gate is raised until the electrons can "tunnel" through the tunnel dielectric from the gate to the source, a phenomenon commonly known as Fowler-Nordheim tunnelling. When the cell is erased, the N-channel transistor is in a logical on state. Note that N-channel EPROMs are preferred over P-channel EPROMs due to the programmability and speed advantages of N-channel EPROMs. EPROMs are conventionally UV-erasable. That is, to erase the cell, relatively high-intensity ultraviolet light is used to excite floating gate electrons and cause them to move off the gate. There are a number of disadvantages with UV-erasable EPROMs. For example, such cells require the use of costly clear quartz windows to allow for UV irradiation of the floating gates. Additionally, the entire array of exposed EPROM cells is erased, even when it is desired to erase only a few cells. To overcome shortcomings such as these, flash electrically erasable read-only memory, widely known as flash EEPROMs, were developed. Flash EEPROMs typically use Fowler-Nordheim tunnelling, as opposed to hot-electron injection, for cell programming as well as for cell erase. A voltage signal, usually less than 25 volts, is applied to the control gate, which is capacitively coupled to the floating gate, while the drain is held either at ground potential or at a voltage less than that applied to the control gate, and the source is held at ground potential. Under such conditions, Fowler-Nordheim tunnelling occurs, in which electrons from the drain, tunnel through a thin layer of SiO 2 (tunnel dielectric) to the floating gate. An important difference between EEPROMs and EPROMs is in the way in which the cells are erased, or more specifically, the way in which the floating gate electrons are removed. Unlike UV-erasable EPROMs, a conventional EEPROM cell electrically induces Fowler-Nordheim electron tunnelling to erase the floating polysilicon gate. A voltage signal, typically less than 25 volts, is applied to the cell drain while the control gate is held at ground potential and the source is left at a floating, or unspecified, voltage potential. As a result, the electrons stored on the floating gate will tunnel through the tunnel dielectric to the source. An advantage of electrical erase over UV erase is that electrical erase can allow for selective erasure of cells in an array, as opposed to erasure of all cells in an array. A conventional EEPROM cell contains an additional "select" gate to control erasure of that cell. By providing a byte-decode transistor for each EEPROM cell in a memory array to control its select gate, selective erase of individual cells or bits in the array can be achieved as opposed to full-array erase in the case of UV-erasable EPROM memory arrays. Although selective erase can thus be achieved, the additional select gate, for example, causes an EEPROM cell to be somewhat larger than an EPROM cell. An alternative type of EEPROM cell known as the flash EEPROM cell does not contain an additional select gate and thus is smaller than a conventional EEPROM cell. However, a memory array of flash EEPROM cells typically cannot be selectively erased due to the absence of select gates. Like an EPROM cell array, all the cells in a flash EEPROM cell array are erased even when not all of the cells in the array need to be erased. Moreover, flash EEPROMs often are more prone to program disturb problems than are conventional EEPROMs due to their different array architecture and absence of byte selection circuitry. Memory arrays using flash EEPROMs often employ a "chip-mode" program cycle. First, all the cells in the array are programmed (logic off state). Second, all the cells in the array are erased (logic on state). Lastly, individual cells in the array are selectively programmed, while other cells remain in the erased state. Note that all the cells in the memory array are programmed first before they are erased in order to avoid "over-erasing". For an over-erased cell, unselected cells can become leaky leading to incorrect sensing of a selected bit on the same bit line and it will also be difficult to program the bit again. Chip mode programming suffers from the disadvantage that every time a single cell (data bit) needs to be programmed, the whole chip must undergo the above-described cycle. Accordingly, all the cells must go through at least one program and erase cycle. As a result, some cells are unnecessarily cycled, i . e . programmed and erased, leading to unnecessary and premature wearout. Additionally, the average programming time can be unnecessarily long. US-A-4 949 309 discloses an array of floating gate transistors which are connected in such a way that a subset of the array of transistors can be erased without affecting the state of the other floating gate transistors within the array, or, in the alternative, the entire array of floating gate transistors can be erased simultaneously. EP-A-182 198 discloses a single transistor electrically programmable device arranged in an array in which an entire column of bytes can be selected for erasure. In view of the foregoing, it is a general objective of the present invention to provide an improved method for selective erase of flash EEPROM cells. We will describe an improved method for programming a memory array of flash EEPROM cells, which allows for reduced cycling, and thus longer endurance of a typical cell in a memory array, and reduced average programming time. More particularly, the page mode programming method of the present invention can be implemented by preventing erasure of cells that are to be left undisturbed by raising the voltage level at their associated control/floating gates so as to oppose and cancel the field caused by the application of a voltage signal to the associated sources during erase. We will describe a method for selectively programming flash EEPROM cells in a memory array, in order to achieve greater programming efficiency and to prolong the endurance of flash EEPROM cells in a memory array by permitting selective erase of cells in the array. The present invention provides a method for programming a flash EEPROM containing an array of flash EEPROM cells including at least one respective V ss line, a plurality of bit lines (BL0..BLn), and a plurality of word lines (WL0...WLn), the array being organized into a plurality of respective pages, each respective page including a plurality of cells all of which have a source coupled to a V ss line, and a gate coupled to the same word line, the drain of the cells of a respective page being coupled to respective bit lines, the method characterised by: programming all of the cells of at least one respective page; erasing all of the cells of said at least one respective page only by inhibiting erasure of the cells of other pages; and subsequently selectively programming individual cells of said at least one respective page. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of this invention will be better understood by referring to the following description given with reference to the accompanying drawings in which like reference numbers refer to like parts, and in which: Figure 1 is a diagram illustrating a portion of a n X n memory array of flash EEPROM cells in accordance with the present invention; Figure 2 shows a cross-sectional diagram of an earlier EEPROM cell; and Figure 3 shows a cross-sectional diagram of a split-gate EEPROM cell in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention offers an improved method of programming flash EEPROM cells in a memory array, wherein a single cell can be programmed without erasing all the cells in the array. The page mode programming method of the present invention utilizes selective erase of cells, as opposed to full-array erase used in chip mode programming, resulting in greater programming efficiency, faster programming time, and longer endurance of cells. Figure 1 illustrates a portion of an n X n memory array 10 of flash EEPROM cells for implementation of the present invention. A typical cell 12 includes a control/floating gate 14 attached to a word line (WLO), a drain 16 attached to a bit line (BLO), and a source 18 attached to a Vss line. Cells in the array are arranged in "pages". A page is defined as a series of cells with source terminals coupled to a common Vss line and with control gates coupled to a common word line. For example, cells with control gates attached to WLO and sources attached to a common Vss line comprise a page of memory cells, two of which (cells 12 and 20) are shown in Figure 1. In the preferred embodiment, eight such cells comprise a byte of memory. Each cell in a page has a different bit line (BLO-BLn) attached to its drain. To erase cells in the memory array 10 according to the well-known chip mode programming method, a voltage Vpp is applied via the line labeled Vss to the sources of all the cells, the bit lines are left floating, and word lines are all held at ground potential. The entire memory array is erased as a result of this chip mode method. However, according to the page mode method of the present invention, selective erase of cell pages can be accomplished by supplying a voltage near Vpp to the word lines of those pages which are to be left undisturbed. That is, the erase procedure will be canceled in those pages whose word lines are at Vpp instead of ground potential. A detailed description of the operation of the page mode method of the present invention follows. In the page mode program cycle, only the cells of the memory array to undergo the cycle are programmed to the logic off state by tying their sources via the line labeled Vss to ground potential, applying Vpp to the control/floating gates via the word lines, and holding the bit lines high at some voltage between Vpp (12 volts) and Vcc (5 volts) to induce hot electron injection into the dielectric from the drain. Note that not all the cells of the memory array need to be initially programmed as is the case in the chip mode cycle, because not all the cells are erased using the page mode. Once the initial programming is complete, the erase procedure is performed. However, unlike the chip mode erase stage, only selected cell pages are erased to the logic on state in the page mode erase stage. Erase is accomplished by applying Vpp to the sources via the line labeled Vss, the drains left at a floating potential, and tying the control/floating gates to ground potential via the word lines. Selective erase is achieved by holding the word lines of those cell pages to be left undisturbed, that is not erased, at a voltage near Vpp, instead of at ground potential, to cancel and oppose the erase process in those cell pages. Finally, selective programming is performed to complete the cycle by programming only those cells whose bit lines are high, which entails applying a voltage potential between Vcc and Vpp to the drains of the cells to be programmed in order to induce electron tunnelling. For example, if the user wants to selectively program the cell 12 corresponding to bit 00, without unnecessarily erasing all the cells first, the procedure illustrated in the following Table can be employed. First, during the initial programming stage, WLO is held at Vpp to program all the cells of page 0, the page which contains cell 00 while the other word lines, line V ss and WL1-WLn are held at ground potential. Next, only the cells attached to WLO are erased by tying WL0 to ground and holding WL1 through WLn near potential Vpp to cancel the erase in those cell pages. Line V ss is held at V pp. Finally, cell 12 can be exclusively programmed by holding BLO high, holding WL0 at Vpp, holding line Vss at ground, and tying all other bit lines and word lines to ground potential. It will be appreciated that other cells of the array can be programmed using similar procedures. Details of the implementation of the circuitry used to inhibit erasure by holding word lines high is provided in our US Patent US-A-5 126 808, filed October 23, 1989, entitled FLASH EEPROM ARRAY WITH PAGED ERASED ARCHITECTURE. Figure 2 shows a cross-sectional profile drawing of an earlier EEPROM cell 20, with a uniform tunnel dielectric 22 of approximately 100 Å (10 nm), which can be programmed according to the method of the present invention. The floating gate 24 is separated from the control gate 26 by an interpoly dielectric 28. The method of the present invention also can be applied to a split-gate cell 30 such as shown in Figure 3, wherein a gate dielectric 32 (dielectric on the drain side of the cell) is thicker than on the source side, i . e . the tunnel dielectric 34. The gate dielectric 32 is approximately 200 Å (20nm) thick, and the thickness of the tunnel dielectric is approximately 100 Å (10nm). For further details of the split-gate flash EEPROM cell, reference our U.S. Patent 4,958,321, issued September 18, 1990, entitled ONE TRANSISTOR FLASH EPROM CELL invented by Chi Chang. A major advantage of the split-gate cell is that it reduces program disturb. Program disturb, in which the drain voltage induces an unwanted electric field across the tunnel dielectric (i.e. between the drain and the floating gate) during long program-select periods, may result in memory loss (i.e., electron loss from the floating gate) in certain cells. The thicker dielectric on the drain side of the cell reduces such charge leakage from the floating gate to the drain. Additionally, the thinner dielectric on the source side of the cell still allows for easy electron tunnelling from the floating gate to the source. Therefore, the described arrangement of the present invention provides an improved method of programming flash EEPROM cells in a memory array by page mode programming. The method provides much of the program selectability advantage of conventional EEPROM cells and the size advantage of flash EEPROM cells. Thus, the arrangement allows for more efficient cell-to-cell programming and reduced cell wearout. While the present invention has been described with reference to specific embodiments, the description is illustrative and is not intended to limit the invention. Various modifications to the described method may be employed by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims: A method for programming a flash EEPROM containing an array of flash EEPROM cells including at least one respective V ss line, a plurality of bit lines (BL0..BLn), and a plurality of word lines (WL0...WLn), the array being organized into a plurality of respective pages, each respective page including a plurality of cells all of which have a source coupled to a V ss line, and a gate coupled to the same word line, the drain of the cells of a respective page being coupled to respective bit lines, the method characterised by: programming all of the cells of at least one respective page; erasing all of the cells of said at least one respective page only by inhibiting erasure of the cells of other pages; and subsequently selectively programming individual cells of said at least one respective page. The method of claim 1, wherein said first step of programming includes programming cells of multiple pages; wherein said step of erasing includes erasing the cells of the same multiple respective pages; and wherein said step of selectively programming includes programming individual cells of the same multiple respective pages. The method of claim 2 wherein said step of inhibiting includes inhibiting erasure of cells in all pages other than said multiple respective pages. The method of claim 1 wherein said first step of programming includes the steps of: holding the Vss line at ground potential; holding the word line which is connected to the gates of all of the cells of the respective page at a voltage Vpp; and holding the bit lines of said individual cells to be programmed at a high voltage level. The method as in claim 1 wherein said step of erasing includes the further steps of: holding the Vss line at voltage potential Vpp; holding the word line which is connected to the gates of all of the cells of the respective page at ground potential; and holding the bit lines of said individual cells to be programmed at a floating voltage potential. The method of claim 3 wherein said step of inhibiting erase includes the step of: holding the word lines of pages other than the selected at a voltage near Vpp. The method of claim 1 wherein said step of selectively programming includes the steps of: holding the word line of cells to be programmed at a voltage Vpp; and holding the bit lines of at least one of the cells to be programmed at a high voltage level.

Inventors: RADDY NADER, RADDY, NADER
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1992
Main classification: G11C16
IPC codes: G11C17, G11C16