Apparatus for adaptively tuning to a received periodic signal

Abstract: An apparatus for adaptively tuning to a received periodic signal. The apparatus preferably employs digital signal processing techniques for algorithmic generation of a sinusoidal estimated output signal, determines the difference between the estimated output signal and the received signal, and generates an error signal based upon the difference between the estimated output signal and the received signal. The error signal is applied to vary at least one factor of the algorithmic determination of the estimated output signal appropriately to reduce the error between the estimated output signal and the received signal.

Description: The present invention is directed to an apparatus which will adaptively tune to a received periodic signal and, in one embodiment, will identify the frequency of the received signal to a user. Adaptive tuning to a received periodic signal is useful in a variety of situations, such as identifying frequency of a fire control or a search radar of a weapon system, tuning to a homing beacon or other similar navigational device, or, generally, tuning to or identifying any periodic signal of unknown frequency with speed and precision. Prior art devices for identifying and tuning to an unidentified (i.e., the frequency is unknown) received signal involved filtering the received signal through an array of high Q filters, and establishing a frequency range within which the received frequency is propagated by noting which of the high Q filters in the array passes the received signal. In order to provide a high degree of accuracy in ascertaining the frequency of the received signal, such prior art circuits must necessarily have a large number of high Q filters in the filter array. A greater number of filters reduces the interval between detectable frequencies and, therefore, increased the accuracy by which the received frequency can be determined. Thus, such prior art devices necessarily require that some estimation of the frequency of the received signal be known in advance in order that the frequency range detectable by the filter array can be assured to include the frequency expected to be received. In order to search a very wide frequency spectrum, it is sometimes required that a plurality of prior art devices be employed, with each device addressing a different range of frequencies. The prior art devices thus described are slow to operate, require foreknowledge of the range within which the anticipated frequency of the received signal will fall, and require the use of analog devices, such as high Q filters, which are known by those skilled in the art to be less stable than digital circuit elements, especially when subjected to variations of ambient temperature. It is desirable that an apparatus be provided for detection of frequency of a received signal which is stable in operation in a variety of environments, which is capable of accurate determination of the frequency of the received signal, and which is capable of ascertaining the frequency of the received signal speedily. GB-A-2100537 discloses a digital signal processing apparatus according to the preamble of claim 1. According to the present invention such apparatus is characterized in that the twice-delayed signal received by the first summing circuit is weighted by multiplying the twice-delayed signal by a second weight factor from a second weight factor source; wherein the estimated output signal generated by the first summing circuit is substantially the sum of the weighted once-delayed output signal and the weighted twice-delayed signal, the error signal being operatively supplied to the first weight factor source and to the second weight factor source, the first weight factor source and the second weight factor source being responsive to the error signal to alter the first weight factor and the second weight factor appropriately to change the weighted once-delayed output signal and the weighted twice-delayed output signal to reduce the difference between the input signal and the estimated output signal. Accordingly there is described an apparatus for adaptively tuning to a received periodic signal which employs digital signaling processing and is stable in a variety of operating environments. The apparatus is inexpensive to construct and ascertains the frequency of a received signal both speedily and with a high degree of accuracy. In the accompanying drawings, by way of example only: Fig. 1 is a schematic diagram of one embodiment of the present invention. Fig. 2 is a schematic diagram of an alternative embodiment of the present invention configured to accommodate noise. As disclosed in our US Patent 4,839,842 to Pyi and Asghar, a periodic waveform may be represented by the expression: cos (m+1) Δ = 2 cos (m) Δ cos Δ - cos (m-1) Δ; where Δ = 2πfT f = signal frequency T = sampling interval Given that the sampling interval T is equal to one over f s (f s equals sampling frequency), the value of Δ may be rewritten as: Δ= 2π f f s For simplicity of expression, Eqn. [1] can be rewritten as: x n+1 = 2 cos Δ x n - x n-1 ; where x n = cos(n)Δ For any given signal frequency, f, the quantity 2 cos Δ is a constant, K. Thus, Eqn. [2] can be expressed as: x n+1 = Kx n - x n-1 ; K = 2 cos Δ The relationship expressed in Eqn. [3] may be advantageously employed in an apparatus for adaptively tuning to a received periodic signal as illustrated in Fig. 1. In Fig. 1, an adaptive tuning apparatus 10 is illustrated having a first delay circuit 12 receiving an incoming signal x n+1 at an input 14. First delay circuit 12 delays incoming signal x n+1 by one clock period and generates a once-delayed signal, x n , at an output 16. Once-delayed signal, x n , is provided to an input 18 of a second delay circuit 20 and to an input 22 of a multiplier circuit 24. Multiplier circuit 24 also receives a multiplier, K, at a multiplier input 26 from a multiplier source 28. Multiplier circuit 24 provides a multiplier output signal, Kx n , at an output 30. Second delay circuit 20 delays once-delayed signal x n one clock period and generates a twice-delayed signal, x n-1 , at an output 32. A first summing circuit 34 receives multiplier output signal Kx n at an input 36, receives twice-delayed signal x n-1 at a negative input terminal 38, and generates an output signal at an output 40. The output signal generated at output 40 is an estimated signal, est. x n+1 , which comprises the difference between multiplier output signal Kx n , less twice-delayed signal x n-1 . A second summing circuit 42 receives estimated signal est. x n+1 at a negative input terminal 46, receives received signal x n+1 at an input 44, and generates an output signal at an output 48. The output signal generated at output 48 is an error signal ε which comprises the difference between received signal x n+1 , less estimated signal est. x n+1 . Error signal ε is applied to an input 50 of multiplier source 28. Multiplier source 28 responds to error signal ε to alter multiplier K provided to multiplier input 26 appropriately to reduce error signal ε. When error signal ε equals zero, estimated signal est. x n+1 equals received signal x n+1 , and adaptive tuning apparatus 10 has successfully tuned to received signal x n+1 . When error signal ε equals zero, it is possible to ascertain the frequency of received signal x n+1 by recalling Eqn. [4] above, so that for the frequency at which error signal ε equals zero, K = 2 cos Θ where  identifies the target frequency, f t (that is, the frequency of received signal X n+1 ). Thus, since: = 2π f t f s and since f s , the sampling frequency, is known, then f t can be readily determined by the expression: f t = f s arcos ( K 2 ) 2π Adaptive tuning apparatus 10 also may include a logic module 54 which receives an input signal from multiplier source 28 at an input 56. The input received from multiplier source 28 at input 56 comprises the value of K generated by multiplier source 28 when error signal ε equals zero. In the embodiment of the present invention illustrated in Fig. 1, it is contemplated that logic module 54 will contain a stored arccosine table in appropriate detail to identify, with the accuracy desired, the arccosine of the quantity: K 2 Further, logic module 54 stores the value f s of the sampling frequency and the value π to enable calculation of f t , the target frequency, according to Eqn. [7] above. Fig. 2 is a schematic diagram of an alternate embodiment of the present invention configured to accommodate noise. Eqn. [3], discussed in connection with the preferred embodiment of the present invention illustrated in Fig. 1, may be rewritten to account for white Gaussian noise in the form: x(n)=Wx(n-1)-x(n-2) W= 2cos2π f ( n ) f s , where f(n) equals a time varying frequency of the received sinusoidal signal and f s equals sampling frequency. Referring to Fig. 2, an apparatus 100 is illustrated having a first delay circuit 102 and a second delay circuit 104. An input signal, x(n), is received by apparatus 100 at an input 106 to first delay circuit 102. First delay circuit 102 delays input signal x(n) one clock period and generates at an output 108 a once-delayed signal x(n-1); x(n-1) is substantially input signal x(n) delayed one clock period. Second delay circuit 104 receives once-delayed signal x(n-1) at an input 110 and delays once-delayed signal x(n-1) by one further clock period, generating at a twice-delayed signal x(n-2) at an output 112. Once-delayed signal x(n-1) is also applied to a multiplier 114 at an input 116. A first weighted factor source 118 provides a first weighted factor, W1(n), to an input 120 of multiplier 114. Multiplier 114 generates at an output 122 a weighted once-delayed signal which is substantially the product of once-delayed signal x(n-1) and first weighted factor Wl(n). This weighted once-delayed signal is applied to an input 124 of a summing node 126. Twice-delayed signal x(n-2) is applied to an input 128 of a multiplier 130. Multiplier 130 also receives at an input 132 a second weighted factor, W2(n), from a second weighted factor source 134. Summing node 126 produces at an output 136 an estimation of input signal x(n), x and(n), estimated input signal x and(n) is applied to an input 138 of a summing node 140. Also received by summing node 140 at an input 142 is input signal x(n). Summing node 140 produces at an output 144 an error signal ε. First weighted factor source 118 and second weighted factor source 134 are responsive to error signal ε to vary first weighted factor Wl(n) and second weighted factor W2(n) appropriately to reduce error signal ε. That is, W1(n) and W2(n) are appropriately varied to reduce the difference between input signal x(n) and estimated input signal x and(n). As may be seen from inspection of Fig. 2: x (n)=W1(n-1)x(n-1)+W2(n-1)x(n-2) Both weighted factors W1(n), W2(n) are adaptive and are preferably determined by a least mean square algorithm, so that: W1(n)=W1(n-1)+µε(n)x(n-1) W2(n)=W2(n-1)+µε(n)x(n-2) Thus, from Fig. 2 and Eqn. [9]: ε(n)=x(n)- x (n)=x(n)-W1(n-1)x(n-1)-W2(n-1)x(n-2) If the input signal x(n) is a pure sine wave, then, from Eqn. [8], W1(n) would converge to a value W defined by the expression: W= 2cos2π f ( n ) f s , and W2 would have a value of -1. However, one realistically should expect to receive a sine wave accompanied by a noise factor. Such a real world situation may be generally expressed by: x(n)=x s (n)+N(n) x s (n) = signal term N(n) = noise term In the presence of white Gaussian noise, the inventors have found that the first weighted factor Wl(n) does not provide an accurate frequency estimation. Thus, second weighted factor W2(n) is employed to estimate noise energy. A correction is then made to first weighted factor W1(n) to obtain an accurate frequency reading. Further considering Eqn. [10]: W1(n)=W1(n-1)+µε(n)x(n-1) µ = gain factor However, W1(n-1)=W1(n-2)+µε(n-1)x(n-2) Thus, W1(n)=W1(n-2)+µ[ε(n)x(n-1)+ε(n-1)x(n-2) Repetitive substitution yields an expansion of Eqn. [14c]: W1(m)=W1(m)+µ[ε(n)x(n-1)+ε(n-1)x(n-2)+...+ε(m+1)x(m)] Therefore: When the system embodied in the apparatus 100 is in steady state, ε(n) is in the presence of noise, a small signal moving randomly about zero. In such a steady state, the weighting functions W1(n) and W2(n) may be defined as: W1(n)=W1*+δW1(n) W2(n)=W2*+δW2(n) Comparing Eqn. [16] with Eqn. [15], and noting a correspondence between the second terms of each of Eqns. [15] and [16], one may note: If µ→0, then |δW1(n)|<<1 and |δW2(n)|<<1 Thus, substituting Eqn. [12] into Eqn. [15] yields: Substituting Eqns. [13] and [16] into Eqn. [18] yields: From Eqn. [8], we know that (recall that W2*=-1, in steady state; the case assumed in connection with Eqn. [8]): x s (k)-W1*x s (k-1)-W2*x s (k-2)=0 Thus, Eqn. [19] reduces to: Assuming that noise N(k) is independent of signal x s (k), as is the case with white Gaussian noise (that is, N(k) is an uncorrelated signal), then: E{N(k)}=0 (mean of N(k)=0) E{N(k)N(k+n)}=0, when n=0 Therefore: That is, in general: Expanding Eqn. [21] yields: By Eqn. [23] and Eqn. [24], we know that all terms underlined in Eqn. 25 equal zero, so: Recall that when |µ|<<1, |δW1(k)|<<1 and |δW2(k)|<<1, so: Therefore, Observing that W1(n)≅W1* when n→∞, Eqn. [28] may be expressed: W1 *≅ W1 ( m )-µ W1 * R N (0) Applying a similar derivation to Eqn. [11] yields: W2*≅W2(m)+µR N (0) µR N (0)=W2*-W2(m) Substituting Eqn. [31] in Eqn. [29] yields: W1*≅W1(m)-W1*[W2*-W2(m)] W1 * =W1 ( m ) - 2cos 2π f 0 f s [ W2 * -W2 ( m )] W1 * =W1 ( m )+2cos 2π f 0 f s [1+ W2 ( m )] Given the cosine function, generally, one can make the following approximations: Substituting Eqn. [35] in Eqn. [34] yields: As previously mentioned, the quantity f s / f 0 must be greater than two to satisfy the requirements of Nyquist sampling theory. Thus, if W1 ( m )≅2cos 2π f 0 f s , then Eqn. [36] may be represented as: Thus, given the theoretical background provided by Eqns. [8] through [37], the operation of apparatus 100 illustrated in Fig. 2 may be further explained in that apparatus 100 includes a frequency identification circuit 150. Frequency identification circuit 150 comprises a summing node 152 which receives second weighted factor W2 from second weighted factor source 134 at an input 154. Summing node 152 also receives at a second input 156 the steady state value of W2*(=-1). Since input 156 is an inverting input, summing node 152 produces at its output 158 a signal representing the quantity [1+W2(n)], which signal is received at an input 162 of a multiplier 160. The quantity W1(n) is applied to an input 164 of a threshold circuit 166. Threshold circuit 166 is preferably designed to substantially implement the approximations represented by Eqn. [37] above, so that the signal, "A", provided by threshold circuit 166 at its output 168 is variable, as indicated in the table associated with Fig. 2, according to the value of signal W1(n) received at input 164. The output signal provided by threshold circuit 166 is applied to an input 170 of multiplier 160 so that multiplier 160 provides at its output 172 a signal "B". Signal "B" varies as indicated in the table associated with Fig. 2, depending upon the value of W1(n) received at input 164 of threshold circuit 166. Signal "B" is applied to an input 174 of a summing node 176; the signal W1(n) is provided to a second input 178 of summing node 176 from first weighted factor source 118, and summing node 176 provides at its output 180 the value W1*. Thus signal W1* is calculated by frequency identification circuit 150 in accordance with Eqn. [37] above. The value provided at output 180 of summing node 176 uniquely identifies the frequency of the sinusoidal signal, x s (n), received at input 106 of delay circuit 102 through a look-up table or similar arrangement in a logic circuit (not shown in Fig. 2). In such manner, a second weighted factor, W2(n), is employed to estimate noise energy in the received signal x(n) and second weighted factor W2(n) is employed to apply a correction to first weighted factor Wl(n) in order to accurately reflect an index uniquely identifying the sinusoidal wave form x s (n) contained within the received signal x n , which is received in the form of Eqn. [13], i.e., x n =x s (n)+N(n)

Claims: A digital signal processing apparatus for adaptively tuning to a received periodic signal, said received signal being a component of an input signal, said input signal including at least some white Gaussian noise; the apparatus comprising: a first delay circuit (102), said first delay circuit receiving said input signal and generating a once-delayed signal, said once-delayed signal being substantially said input signal delayed one clock period; a second delay circuit (104), said second delay circuit receiving said once-delayed signal from said first delay circuit (102) and generating a twice-delayed signal, said twice-delayed signal being substantially said input signal delayed two said clock periods; a first multiplying circuit (114), said first multiplying circuit receiving said once-delayed signal from said first delay circuit (102) and receiving a first weight factor from a first weight factor source (118), said first multiplying circuit generating a weighted once-delayed output signal, said weighted once-delayed output signal being substantially said once-delayed signal multiplied by said first weight factor; a first summing circuit (126), said first summing circuit receiving said weighted once-delayed output signal and receiving said twice-delayed signal, said first summing circuit generating an estimated output signal, and a second summing circuit (140), said second summing circuit receiving said input signal and receiving said estimated output signal, said second summing circuit generating an error signal, said error signal being representative of the difference between said input signal and said estimated output signal; characterised in that the apparatus further comprises a second multiplying circuit (130), said second multiplying circuit receiving said twice-delayed signal from said second delay circuit and receiving a second weight factor from a second weight factor source (134), said second multiplying circuit generating a weighted twice-delayed output signal, said weighted twice-delayed output signal being substantially said twice-delayed signal multiplied by said second weight factor; wherein the estimated output signal generated by the first summing circuit (126) is substantially the sum of the weighted once-delayed output signal and the weighted twice-delayed signal, the error signal being operatively supplied to said first weight factor source (118) and to said second weight factor source (134), said first weight factor source and said second weight factor source being responsive to said error signal to alter said first weight factor and said second weight factor appropriately to change said weighted once-delayed output signal and said weighted twice-delayed output signal to reduce said difference between said input signal and said estimated output signal. A digital signal processing apparatus according to claim 1 wherein the apparatus further comprises frequency identification means (54) for identifying the frequency of said received signal; said frequency identification means receiving said first weight factor from said first weight factor source as a first input, and receiving said second weight factor from said second weight factor source as a second input, said frequency identification means algorithmically calculating a frequency index from said first input and said second input, said frequency index uniquely identifying said frequency of said received signal. Apparatus according to claim 1 or claim 2 in which the first weight factor and/or the second weight factor are set to an initial first weight factor and/or an initital second weight factor, respectively, to establish the estimated signal at a predetermined initial estimation of the received signal.

Inventors: ASGHAR SAFDAR M, ZHOU YAN, ASGHAR, SAFDAR M., ZHOU, YAN
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1992
Main classification: H04Q1
IPC codes: G01R23, H04Q1, H03H17, H03J3