Bias voltage generation circuit of ECL level for decreasing power consumption thereof

Abstract: A bias voltage generation circuit comprises a bias voltage generation portion (BVG) having a bias control node (N₁), a first switching unit (T₁), and a second switching unit (MT, MTP). The bias voltage generation portion (BVG) is used to generate a bias voltage (Vcs) of a predetermined potential and supply the bias voltage (Vcs) to an ECL circuit during an operation period (t₀), and the first switching unit (T₁) is used to drop the bias voltage (Vcs) during a standby period (t₁) in response to a bias voltage control signal (PS). The second switching unit (MT, MTP) is used to switch OFF during the standby period (t₁) to cut off a current flow through the bias control node (N₁) and switch ON during the operation period (t₀) to supply a current through the bias control node (N₁) in response to the bias voltage control signal (PS). Consequently, current flow during the standby period (t₁) can be reduced, and power consumption of the bias voltage generation circuit during the standby period (t₁) is minimal.

Description: The present invention relates to a bias voltage generation circuit, more particularly, to a bias voltage generation circuit of an emitter coupled logic (ECL) level. Conventionally, high-speed LSIs are constituted by emitter coupled logic (ECL) circuits, but the ECL circuits require large amounts of power. In recent years, high-speed LSIs of low power consumption have been required to realize a battery backup system, and various techniques have been developed and proposed to meet the requirement. Note, one effective technique applying to ECL circuits is to provide a standby state by lowering the bias voltage of the ECL circuits during a non-operation period, thereby saving on total power consumption during operation and non-operation periods. This technique externally controls the bias voltage of the ECL circuits generated by a bias voltage generation circuit. Further, the bias voltage generation circuit is also required to be of low power consumption by itself. USA Patent No. 4 639 661 discloses an ECL circuit having such a standby state. Two switching networks are used to enable the device to respond to a power-down signal. JP-A-197987 uses a discharging circuit to reduce the bias current during a standby state. JP-A-6442918 discloses a method of reducing power consumption in a differential amplifier circuit by supplementing a base current of an output bipolar transistor via a FET. An object of the present invention is to provide a bias voltage generation circuit having small consumption power during a standby period. Namely, an object of the present invention is to reduce current flow to a negligible amount (less than about 10 microamperes: µ A) during a standby period. According to the present invention, there is provided a bias voltage generation circuit supplied with a bias voltage control signal, the circuit including a first power supply line, a second power supply line, and a bias voltage generation portion having a bias control node, the bias voltage generation portion being connected between said first power supply line and said second power supply line, and comprising an output transistor for generating at its output a bias voltage of a predetermined potential based on the voltage at the bias control node and supplying said bias voltage to a circuit during an operation period, said bias voltage generation circuit comprising a voltage regulation and compensation feedback circuit connected between the output of said output transistor and said bias control node; a first switching means, connected between said bias control node of said bias voltage generation portion and said second power supply line, for switching ON during a standby period to lower said bias voltage and switching OFF during said operation period based on the bias voltage control signal and a second switching means, connected between said bias control node and said first power supply line, for switching OFF during said standby period to cause an impedance between said first power supply line and said bias control node to be relatively high and switching ON during said operation period to cause the impedance between said first power supply line and said bias control node to be relatively low based on said bias voltage control signal to set the bias control voltage. The first switching unit may be constituted by a PNP-type bipolar transistor having base, collector and emitter electrodes, the base electrode receiving the bias voltage control signal, the collector electrode being connected to the second power supply line, and the emitter electrode being connected to the bias control node. The second switching unit may be constituted by an N-type MIS transistor, a gate electrode of the N-type MIS transistor receiving the bias voltage control signal. The second switching unit may be constituted by a P-type MIS transistor, a gate electrode of the P-type MIS transistor receiving an inverted signal of the bias voltage control signal through an inverter. The ON-resistance value of the MIS transistor may correspond to a resistance value determined by the bias voltage generation portion. The MIS transistor may be constituted as a long-gate MIS transistor. The bias voltage generation portion may include a compensation bipolar transistor, connected to the second power supply line and a resistor (R 2 ) connected between the bias control node and the compensation bipolar transistor, for compensating the bias voltage at the predetermined potential. The second switching unit may be switched OFF during the standby period to cut off the current flowing through the compensation bipolar transistor. The bias voltage generation circuit may further comprise a resistor connected between the first power supply line and the bias control node in series to the second switching unit, the resistance value of the resistor corresponding to a resistance value determined by the bias voltage generation portion, the second switching unit being mainly used for a switching purpose, and the resistor being mainly used for providing a required resistance value. The bias voltage generation circuit may further comprise a pull-up resistor having a high resistance value, connected between the first power supply line and the bias control node. The first power supply line may be a high-potential power supply line, and the second power supply line may be a low-potential power supply line. The bias voltage generated by the bias voltage generation circuit may be supplied to an emitter coupled logic circuit during the operation period. The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: Figure 1 is a circuit diagram showing an example of a bias voltage generation circuit according to the related art (JP-A-63 278 416); Figure 2 is a circuit diagram showing a first embodiment of a bias voltage generation circuit according to the present invention; Figure 3 is a circuit diagram showing an ECL circuit to which the bias voltage generation circuit of the present invention is applicable; Figure 4 is a block diagram showing an example of radio telephone equipment using the bias voltage generation circuit of the present invention; Figure 5 is a circuit block diagram showing the prescaler shown in Fig. 4; Figures 6A to 6C are timing charts for explaining an operation of the prescaler of Fig. 5; Figure 7 is a circuit diagram showing a second embodiment of the bias voltage generation circuit according to the present invention; and Figure 8 is a circuit diagram showing a third embodiment of the bias voltage generation circuit according to the present invention. For a better understanding of the preferred embodiments, the problems of the related art will be explained, with reference to Fig. 1. Figure 1 shows an example of a bias voltage generation circuit according to the related art. As shown in Fig. 1, the bias voltage generation circuit comprises a PNP-type bipolar transistor T 1 0 1 , a plurality of NPN-type bipolar transistors T 1 0 2 to T 1 0 9 , and a plurality of resistors R 1 0 1 to R 1 0 8 . The transistor T 1 0 1 has a base electrode connected to a bias voltage control signal input terminal (PS), an emitter electrode, which is a node n 1 and generally called as VRCM, connected to a high-potential power source (first power supply line) V C C through the resistor R 1 0 1 , and a collector electrode connected to a low-potential power source (second power supply line) V E E . The transistor T 1 0 2 has a collector electrode connected, through the resistor R 1 0 2 , to the emitter electrode (node n 1 ) of the transistor T 1 0 1 as well as to the base electrodes of the transistors T 1 0 3 and T 1 0 8 , an emitter electrode connected to the low-potential power source V E E , and a base electrode connected to the collector electrodes of the transistors T 1 0 4 , T 1 0 5 , and T 1 0 6 as well as to the low-potential power source V E E through the resistor R 1 0 3 . The transistor T 1 0 3 has a collector electrode connected to the high-potential power source V C C , and an emitter electrode connected to the base electrode of the transistor T 1 0 2 through the resistor R 1 0 4 . The base electrodes of the transistors T 1 0 4 , T 1 0 5 , and T 1 0 6 are connected to one another and commonly to the collector and base electrodes of the transistor T 1 0 9 through the resistor R 1 0 6 , and the emitter electrodes thereof are connected to one another and to the low-potential power source V E E through the resistor R 1 0 5 . The collector electrode of the transistor T 1 0 7 is connected to its base electrode as well as to the high-potential power source V C C through the resistor R 1 0 7 , and the emitter electrode thereof is connected to the collector electrode of the transistor T 1 0 8 . The emitter electrode of the transistor T 1 0 8 is connected to a bias voltage output terminal Vcs as well as to the collector electrode of the transistor T 1 0 9 through the resistor R 1 0 8 . The emitter electrode of the transistor T 1 0 9 is connected to the low-potential power source V E E . Note, the transistors T 1 0 4 , T 1 0 5 , T 1 0 6 , and T 1 0 9 are the same size, and these transistors (T 1 0 4 , T 1 0 5 , T 1 0 6 ; T 1 0 9 ) are used to compensate for the temperature dependency thereof. Further, the transistor T 1 0 2 is used to compensate for the bias voltage Vcs at the predetermined potential (-4.0, or 1.2 volts). In addition, as shown in Fig. 1, a bias voltage generation portion BVG' is constituted by the bipolar transistors T 1 0 2 to T 1 0 9 , and the resistors R 1 0 1 to R 1 0 8 . In the above bias voltage generation circuit shown in Fig. 1, for example, a potential of the high-potential power source V C C is defined to be 0 (or 5.2) volts, a potential of the low-potential power source V E E is defined to be -5.2 (or 0) volts, and the bias voltage Vcs is defined to be -4.0 (or 1.2) volts. Further, for example, each resistance value of the resistor R 1 0 1 and the resistor R 1 0 5 is defined to be 20 kΩ. In the bias voltage generation circuit of Fig. 1. the bias voltage control signal PS supplied to the bias voltage control signal input terminal (PS) is dropped during a standby period (corresponding to a period t 1 shown in Fig. 6B) to turn ON the PNP-type bipolar transistor T 1 0 1 . Therefore, a level at the node n 1 (VRCM) is dropped to decrease an output voltage (bias voltage) Vsc. As a result, power consumption of an ECL circuit to which the bias voltage is supplied is reduced during the standby period. As described above, the bias voltage generation circuit shown in Fig. 1 turns ON the transistor T 1 0 1 during a standby period to drop a level at the node n 1 , thereby dropping the output voltage Vcs. The resistance value of the resistor R 1 0 1 must not be too high because it supplies a collector current to the transistor T 1 0 2 during operation. This means that a current flowing to the resistor R 1 0 1 (which is defined to be about several tens kiloohms) may remain as an emitter current to the transistor T 1 0 1 during a standby period. The current flowing to the resistor R 1 0 1 is, for example, about 100 µ A, although it depends on a circuit constant. This will be a big problem to be solved, in particular, for radio telephone equipment using a battery backup system. Below, the preferred embodiments of a bias voltage generation circuit according to the present invention will be explained, with reference to the accompanying drawings. Figure 2 is a circuit diagram showing a first embodiment of a bias voltage generation circuit according to the present invention. As shown in Fig. 2, the bias voltage generation circuit of the first embodiment comprises an N-type MIS transistor MT, a PNP-type bipolar transistor T 1 , a plurality of NPN-type bipolar transistors T 2 to T 9 , and a plurality of resistors R 1 to R 8 . The transistor T 1 has a base, collector and emitter electrodes. The base electrode of the transistor T 1 is connected to a bias voltage control signal input terminal (PS) as well as to the gate electrode of the MIS transistor MT, the emitter electrode thereof, which is a node n 1 and generally called as VRCM, is connected to the drain electrode of the transistor MT, and the collector electrode thereof is connected to a low-potential power source (second power supply line) V E E . The source electrode of the transistor MT is connected to a high-potential power source (first power supply line) V C C . The collector electrode of the transistor T 2 is connected to the emitter electrode (node N 1 ) of the transistor T 1 through the resistor R 2 . The node N 1 (VRCM) is connected to the high-potential power source V C C through the resistor R 1 as well as to the base electrodes of the transistors T 3 and T 8 . The emitter electrode of the transistor T 2 is connected to the low-potential power source V E E , and the base electrode thereof is connected to the collector electrodes of the transistors T 4 , T 5 , and T 6 as well as to the low-potential power source V E E through the resistor R 3 . The collector electrode of the transistor T 3 is connected to the high-potential power source V C C , and the emitter electrode thereof is connected to the base electrode of the transistor T 2 through the resistor R 4 . The base electrodes of the transistors T 4 , T 5 , and T 6 are connected to one another and commonly to the collector and base electrodes of the transistor T 9 through the resistor R 6 , and the emitter electrodes thereof are connected to one another and to the low-potential power source V E E through the resistor R 5 . The collector electrode of the transistor T 7 is connected to its base electrode as well as to the high-potential power source V C C through the resistor R 7 , and the emitter electrode thereof is connected to the collector electrode of the transistor T 8 . The emitter electrode of the transistor T 8 is connected to the bias voltage output terminal (Vcs) as well as to the collector electrode of the transistor T 9 through the resistor R 8 . The emitter electrode of the transistor T 9 is connected to the low-potential power source V E E . Note, the transistors T 4 , T 5 , T 6 , and T 9 are the same size, and these transistors (T 4 , T 5 , T 6 ; T 9 ) are used to compensate for the temperature dependency thereof. Further, the transistor T 2 is used to compensate for the bias voltage Vcs at the predetermined potential (-4.0, or 1.2 volts). Namely, the transistor T 2 compensates for temperature dependency of the bias voltage Vcs. Further, as shown in Fig. 2, a bias voltage generation portion BVG is constituted by the bipolar transistors T 2 to T 9 , and the resistors R 2 to R 8 . In the above bias voltage generation circuit shown in Fig. 2, for example, a potential of the high-potential power source V C C is defined to be 0 (or 5.2) volts, a potential of the low-potential power source V E E is defined to be -5.2 (or 0) volts, and the bias voltage Vcs is defined to be -4.0 (or 1.2) volts. Further, for example, the resistance value of the resistor R 5 is defined to be 20 kΩ , and the ON-resistance value of the MIS transistor MT is defined to be 20 kΩ . Note, the ON-resistance value of the MIS transistor MT corresponds to that of the resistor R 1 0 1 shown in Fig. 1, Next, the operation of the bias voltage generation circuit of Fig. 2 will be explained. During a standby period (corresponding to a period t 1 shown in Fig. 6B) of the bias voltage generation circuit of this embodiment shown in Fig. 2, the bias voltage control signal PS supplied to the bias voltage control signal input terminal (PS) is dropped to turn ON the PNP-type bipolar transistor T 1 . Therefore, a level at the node N 1 falls to set the output voltage (bias voltage) Vcs to a low potential. Note, at this time, the bias voltage control signal PS is also supplied to the gate of the N-type MIS transistor MT, so that the transistor MT is turned OFF by the bias voltage control signal PS. Consequently, almost no current flows through the turned OFF transistor MT and the node N 1 during the standby period. In this way, power consumption of an ECL circuit to which the bias voltage is supplied is saved during the standby period. Further, power consumption of the bias voltage generation circuit is also reduced by cutting OFF the current flowing through the MIS transistor MT and the node N 1 . During an operation period (corresponding to a period t 0 shown in Fig. 6B) in which the bias voltage generation circuit of this embodiment generates a bias voltage of predetermined level, the bias voltage control signal PS supplied to the gate of the N-type MIS transistor MT rises to turn ON the transistor MT. Because of the ON-resistance (for example, several tens kiloohms) of the transistor MT, the transistor functions similar to the resistor R 1 0 1 of Fig. 1. Namely, during operation, the ON-resistance of the transistor MT works to supply a collector current to the bipolar transistor T 2 for providing the bias voltage Vcs of predetermined potential. According to the bias voltage generation circuit of Fig. 2, the gate length of the N-type MIS transistor MT is long enough to provide the ON-resistance of, for example, several kiloohms. The resistor R 1 of Fig. 2 is a pull-up resistor, which supplies a very weak collector current to the transistor T 1 . The resistor R 1 may have a high resistance value of about several megaohms. Accordingly, a current of several microamperes will flow through the pull-up resistor R 1 , which causes no problem with power consumption in actual use. Figure 3 is a circuit diagram showing an ECL circuit to which the bias voltage generation circuit of the present invention is applicable, and the ECL circuit is a basic one. As shown in Fig. 3, the ECL circuit comprises transistors T 3 1 to T 3 7 and resistors R 3 1 to R 3 5 . The output (bias voltage) Vcs of the bias voltage generation circuit of the invention is supplied to various ECL circuits. As shown in Fig. 3, for example, the bias voltage Vcs is applied to base electrodes of the transistors T 3 5 , T 3 6 , and T 3 7 of the ECL circuit, and during a standby period, the bias voltage generation circuit drops the bias voltage Vcs to reduce power consumption in the ECL circuit. Note, the bias voltage generation circuit is applicable for providing a bias voltage to the basic ECL circuit of Fig. 3 as well as other circuits. Figure 4 is a block diagram showing an example of radio telephone equipment using the bias voltage generation circuit of the present invention. As shown in Fig. 4, the radio telephone equipment, which is generally provided with a battery backup system, comprises a microprocessor unit (MPU) 1, a PLL control circuit 2, a prescaler 3, a phase comparator 4, a charge pump circuit 5, a low pass filter (LPF) 7, a voltage controlled oscillator (VCO) 6, and a crystal oscillator 11. Note, as shown in Fig. 4, the bias voltage generation circuit of the present invention is included in the prescaler 3, and a power save signal (bias voltage control signal) PS is supplied to the bias voltage generation circuit. Further, as shown in Fig. 4, a radio frequency RF (RF o u t , RF i n ) generated by the VCO 6 is returned to the PLL control circuit 2 through the prescaler 3. Figure 5 is a circuit block diagram showing the prescaler shown in Fig. 4. As shown in Fig. 5, the prescaler 3 comprises a bias voltage generation circuit 30, four T-type flip-flops 31 to 34, and inverters 35 and 36. Note, the flip-flops 31 to 34 are connected in series, the radio frequency RF i n output from the VCO 6 is supplied to the flip-flop 31, and the signal f o u t output from the flip-flop 34 is supplied to the PLL control circuit 2. Further, the flip-flops 31 to 34 are constituted by ECL circuits to realize a high-speed operation. The power save signal (bias voltage control signal) PS output from the MPU 1 is supplied to the bias voltage generation circuit 30 through the inverters 35 and 36, and the bias voltage Vcs output from the bias voltage generation circuit 30 is applied to the flip-flops 31 to 34. Note, the bias voltage generation circuit 30 is not only applied to the prescaler 3 of the radio telephone equipment, but the bias voltage generation circuit 30 can also be applied to various ECL circuits. Figures 6A to 6C are timing charts for explaining an operation of the prescaler of Fig. 5. As shown in Fig. 6A, the power save signal (bias voltage control signal) PS is changed to a high level during 100 milliseconds (msec.) by 1 second (sec.). Namely, one period of the power save signal PS is determined to be 1 sec., and the power save signal PS is at a high level during 100 msec. and at a low level during 900 msec. in each period thereof. In Fig. 6B, a reference t 0 denotes an operation period corresponding to the period that the power save signal PS is at a high level, and a reference t 1 denotes a standby period corresponding to the period that the power save signal PS is at a low level. Further, a reference P 0 1 denotes a timing of starting the operation of the prescaler 3, and a reference P 0 2 denotes a timing of stopping the operation of the prescaler 3. Namely, as shown in Figs. 2, 6A to 6C, during the standby period t 1 , the power save signal PS is dropped to turn ON the PNP-type bipolar transistor T 1 , and a level at the node N 1 falls to set the output voltage (bias voltage) Vcs to a low potential (-5.2, or 0 volts). Note, at this time, the power save signal PS is also supplied to the gate of the N-type MIS transistor MT, so that the transistor MT is turned OFF by the power save signal PS. Consequently, as shown in Fig. 6C, almost no current CC 1 (2 ∼ 5 µ A) is used by the prescaler 3 during the standby period t 1 . On the other hand, during an operation period t 0 , the power save signal PS rises to turn OFF the PNP-type bipolar transistor T 1 , and a bias voltage Vcs is returned to a predetermined level (-4.0, or 1.2 volts). Further, the N-type MIS transistor MT is turned ON, and the ON-resistance of the transistor MT is provided between the high-potential power source V C C and the node N 1 , so that a collector current of the bipolar transistor T 2 for providing the bias voltage Vcs of predetermined potential starts to flow. Consequently, as shown in Fig. 6C, a current CC 0 (several tens mA) is used by the prescaler 3 during the operation period t 0 . Note, in Fig. 6C, a reference CC 0 1 denotes a consumption current of the related art prescaler using the bias voltage generation circuit shown in Fig. 1 during the standby period t 1 . Therefore, by applying the bias voltage generation circuit of the present invention, the consumption current of the prescaler 3 can be reduced from the current CC 0 1 (several hundreds µ A) to the current CC 1 (2 ∼ 5 µ A), during the standby period t 1 . Figure 7 is a circuit diagram showing a second embodiment of the bias voltage generation circuit according to the present invention. By comparing the bias voltage generation circuit shown in Fig. 7 with that shown in Fig. 2, the bias voltage generation circuit shown in Fig. 7 further comprises a resistor R 0 . The resistor R 0 is connected between the N-type MIS transistor MT and the node N 1 . Note, other parts of this second embodiment are the same as those of the first embodiment of the bias voltage generation circuit shown in Fig. 2. Note, the ON-resistance of a standard N-type MIS transistor is small, for example, several ohms. Accordingly, the transistor MT is used mainly for switching purposes, and the resistor R 0 mainly determines a resistance value (for example, several tens kiloohms) while the transistor MT is being ON. In Fig. 7, the resistor R 0 is disposed between the drain of the transistor MT and the node N 1 , but the resistor R 0 may be disposed between the high-potential power source V CC and the source of the transistor MT. For example, the ON-resistance value of the transistor MT is determined to be 1 kΩ (or 100 Ω), and the resistance value of the resistor R 0 is determined to be 19 kΩ (or 19.9 k Ω). In this case, when fluctuating the resistance value of the ON-resistance value of the transistor MT, the total resistance value is mainly due to that of the resistor R 0 , and thus the manufacturing variation of the transistor MT does not influence to the bias voltage Vcs. Further, as shown in Fig. 7, in this second embodiment, the pull-up resistor R 1 is connected parallel with the series-connected MIS transistor MT and resistor R 0 . Figure 8 is a circuit diagram showing a third embodiment of the bias voltage generation circuit according to the present invention. As shown in Fig. 8, a P-type MIS transistor MTP can be used instead of the N-type MIS transistor MT of Fig. 7. The gate of the P-type MIS transistor MTP receives an inverted signal of the bias voltage control signal PS through an inverter INV. As described above, in a bias voltage generation circuit according to the present invention, a bias voltage generation circuit generates a bias voltage Vcs of predetermined potential during an operation period and drops the bias voltage during a standby period in response to a bias voltage control signal PS to save power consumption of the ECL circuit to which the bias voltage is supplied. The bias voltage generation circuit comprises a MIS transistor MT (MTP) to be switched ON and OFF in response to the bias voltage control signal. The MIS transistor MT (MTP) is switched OFF during the standby period to cut off current flow and ON during the operation period to supply a current to a bipolar transistor T 2 for providing the bias voltage of the predetermined potential. In the bias voltage generation circuit of the present invention, the MIS transistor MT (MTP) is switched ON and OFF in response to the bias voltage control signal PS. During a standby period, the MIS transistor MT (MTP) is turned OFF to cut off a current, and during an operation period, the MIS transistor MT (MTP) is turned ON to supply a current to the bipolar transistor T 2 for providing the bias voltage of the predetermined potential. As explained above, the bias voltage generation circuits according to the embodiments can reduce a current in the bias voltage generation circuits themselves during a standby period. In particular, the embodiments realize an elongated use with low power consumption required for battery driven communications equipment, etc. Namely, in accordance with a bias voltage generation circuit of the present invention, the bias voltage generation circuit comprises a MIS transistor to be switched ON and OFF in response to a bias voltage control signal, and current flow is reduced to a negligible amount (less than about 10 µ A) during a standby period.

Claims: A bias voltage generation circuit supplied with a bias voltage control signal (PS), the circuit including a first power supply line (V CC ), a second power supply line (V EE ), and a bias voltage generation portion (BVG) having a bias control node (N 1 ), the bias voltage generation portion being connected between said first power supply line (V CC ) and said second power supply line (V EE ), and comprising an output transistor (T8) for generating at its output a bias voltage (Vcs) of a predetermined potential based on the voltage (VRCM) at the bias control node (N 1 ) and supplying said bias voltage to a circuit during an operation period (t 0 ), said bias voltage generation circuit comprising: a voltage regulation and compensation feedback circuit connected between the output of said output transistor (T8) and said bias control node (N 1 ) ; a first switching means (T 1 ), connected between said bias control node (N 1 ) of said bias voltage generation portion (BVG) and said second power supply line (V EE ), for switching ON during a standby period (t 1 ) to lower said bias voltage (Vcs) and switching OFF during said operation period (t 0 ) based on the bias voltage control signal (PS); and a second switching means (MT, MTP; R 1 ), connected between said bias control node (N 1 ) and said first power supply line (V CC ), for switching OFF during said standby period (t 1 ) to cause an impedance between said first power supply line (V CC ) and said bias control node (N 1 ) to be relatively high and switching ON during said operation period (t 0 ) to cause the impedance between said first power supply line (V CC ) and said bias control node (N 1 ) to be relatively low based on said bias voltage control signal (PS) to set the bias control voltage (VRCM) . A bias voltage generation circuit according to claim 1, wherein said first switching means (T 1 ) is constituted by a PNP-type bipolar transistor having base, collector and emitter electrodes, said base electrode receiving said bias voltage control signal (PS), said collector electrode being connected to said second power supply line (V EE ), and said emitter electrode being connected to said bias control node (N 1 ). A bias voltage generation circuit according to claim 1 or claim 2, wherein said second switching means (MT) is constituted by an N-type MIS transistor, a gate electrode of said N-type MIS transistor (MT) receiving said bias voltage control signal (PS). A bias voltage generation circuit according to claim 1 or claim 2, wherein said second switching means (MTP) is constituted by a P-type MIS transistor, a gate electrode of said P-type MIS transistor (MTP) receiving an inverted signal of said bias voltage control signal (PS) through an inverter (INV). A bias voltage generation circuit according to claim 3 or 4, wherein the ON-resistance value of said MIS transistor (MT, MTP) corresponds to a resistance value determined by said bias voltage generation portion (BVG). A bias voltage generation circuit according to claim 3, 4 or 5, wherein said MIS transistor (MT, MTP) is constituted as a long-gate MIS transistor. A bias voltage generation circuit according to any one of the preceding claims, wherein said bias voltage generation portion (BVG) includes a compensation bipolar transistor (T 2 ), connected to said second power supply line (V EE ) and a resistor (R 2 ) connected between said bias control node (N 1 ) and said compensation bipolar transistor (T 2 ). A bias voltage generation circuit according to any one of claims 3 to 7, wherein said second switchinq means (MT, MTP) is switched OFF during said standby period (t 1 ) to cut off the current flowing through said compensation bipolar transistor (T 2 ). A bias voltage generation circuit according to any one of the preceding claims, wherein said bias voltage generation circuit further comprises a resistor (R 0 ) connected between said first power supply line (V cc ) and said bias control node (N 1 ) in series to said second switching means (MT, MTP), the resistance value of said resistor (R 0 ) corresponding to a resistance value determined by said bias voltage generation portion (BVG), said second switching means (MT, MTP) being used mainly for a switching purpose, and said resistor (R 0 ) being used mainly for providing a required resistance value. A bias voltage generation circuit according to any one of the preceding claims, wherein said bias voltage generation circuit further comprises a pull-up resistor (R 1 ) having a high resistance value, connected between said first power supply line (V CC ) and said bias control node (N 1 ). A bias voltage generation circuit according to any one of the preceding claims, wherein said first power supply line (V CC ) is a high-potential power supply line, and said second power supply line (V EE ) is a low-potential power supply line. A bias voltage generation circuit according to any one of the preceding claims, wherein said bias voltage (Vcs) generated by said bias voltage generation circuit is supplied to an emitter coupled logic circuit during said operation period (t 0 ).

Inventors: AISAKA TETSUYA, NONAKA KAZUYUKI, AISAKA, TETSUYA, NONAKA, KAZUYUKI, Aisaka, Tetsuya, c/o Fujitsu VLSI Limited, NONAKA, KAZUYUKI, C/O FUJITSU VLSI LIMITED
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1992
Main classification: H03K19
IPC codes: H03K19, G05F3