Tunneling transistor

Abstract: A tunneling transistor comprising an emitter layer (7), a barrier layer (6) having a conduction band higher in energy than a conduction band of said emitter layer (7) and a valence band lower in energy than a valence band of said emitter layer (7), and further having a thickness with which electrons can substantially tunnel the barrier layer (6), a collector layer (4) having a conduction band lower in energy than the valence band of said emitter layer (7) and a conductivity type opposite to said emitter layer (7), and further having a thickness with which quantum levels are substantially formed, a gate layer (2) having a conduction band higher in energy than the conduction band of said layer and a valence band of said emitter layer (7), and further having a thickness with which the probability of electron tunneling is substantially greatly reduced, said layers been laminated in this order, and electrodes (5,8) which form ohmic junctions on said emitter layer and said collector layer and an electrode (3) which forms a Schottky junction on said gate layer.

Description: The present invention relates to a tunneling transistor capable of controlling negative resistance characteristics. Prior practice of negative resistance devices through tunneling includes a resonant hot electron transistor (RHET) and a resonant tunneling bipolar transistor (RBT), those transistors being constructed through combination of a resonant tunneling structure with a heterojunction bipolar transistor or a field effect transistor. These transistors are successful in the construction of Ex-NOR gates, multiple-state holding gates, latch circuits and NOR circuits with a reduced number of constituent transistors compared with prior art transistors, and hence attract many interests with the expectation of application to functional devices. These devices are described, for example, in Electron Devices, Vol. 36, p 2065, 1989, F. Capasso, et al. In the resonant tunneling effect, there is taken as a tunnel barrier the size of a discontinuity of conduction band energy in a semiconductor heterojunction, i.e., a difference between electron affinities between constituting semiconductors, so that the height of the tunnel barrier is not increased and the resonant tunneling effect is severely affected by a current (an excess current) based upon electrons going over the barrier by thermal excitation at room temperature. The foregoing prior art tunneling transistors are therefore unlikely to be operational at room temperature. Applied Physics Letters, Vol. 47, No. 8, October 1985, pp. 888-890 (Bonnefoi et al.) discloses an unipolar inverted base-collector tunnel transistor. IBM Technical Disclosure Bulletin, Vol. 31, No. 7, December 1988, pp. 20-21 shows a semiconductor tunneling hetero structure comprising an InAs layer and a GaSb layer separated by a barrier layer. US-A-4 538 165 discloses a field effect transistor using InAs, GaSb and AlSb. It is an object of the invention to provide a tunneling transistor capable of operating at room temperature by reducing the excess current in the tunneling transistor and increasing the tunnel current. This object is achieved by a tunneling transistor as defined in claims 1 and 2, respectively; claim 3 defines a further development of the invention. In accordance with the present invention, for ensuring the decrease of the excess current and the increase of the tunnel current, there is used interband tunneling between the valence band and the conduction band of the constituent semiconductors instead of tunneling between conduction bands of a constituent semiconductor. In the tunneling transistor of the present invention, differential negative resistance is produced in the current-voltage characteristic which resistance is controllable by the gate electrode. The present invention manifests the following advantages: Use of the resonant tunneling between the energy bands instead of the prior art resonant tunneling between the conduction bands ensures an increase of tunnel current density and suppression of the excess current, and permits room temperature operation. Compared with the prior art AlGaAs devices the transistor according to the present invention can suppress to 1/6∼1/8 the excess current at predetermined current density and 77K operation temperature. The above and in any other advantages, features and additional objects of the present invention will become manifest to those versed in the art upon making reference to the following detailed description and accompanying drawings in which preferred structural embodiments incorporating the principles of the present invention are shown by way of illustrative example. FIG. 1 is a sectional view illustrating a first embodiment of the present invention; FIG. 2 is a view illustrating a band structure of the first embodiment; FIG. 3 is a view illustrating a current-voltage characteristic of the first embodiment; FIG. 4 is a view illustrating a band structure of a second embodiment of the present invention; FIG. 5 is a view illustrating a band structure of a third embodiment of the present invention; and FIG. 6 is a view illustrating a band structure of a fourth embodiment of the present invention. In the following there will be described the present invention with reference to the attached drawings each illustrating some preferred and concrete examples of the present invention. Referring to FIGS. 1 and 2, there are illustrated respectively an arrangement of a first concrete example of the present invention in the form of a cross section, and an energy band structure in the arrangement of FIG. 1. As illustrated in FIG. 1, an AlSb barrier layer 2 which is a second semiconductor is provided on an InAs substrate 1 of a transistor, and a gate electrode 3 is formed on the top surface of the barrier layer 2 on one side of the same and, on the other hand, an InAs collector layer 4 is formed on the top surface of the barrier layer 2 on the other side of the same. On the top surface of the collector layer 4 on one side of the same an AlSb barrier layer 6 is disposed, while on the top surface of the same on the other side of the same a collector electrode 5 is disposed to form an ohmic junction with the collector layer 4. On the top surface of the AlSb barrier layer 6 there is provided a GaSb emitter layer 7. On the top surface of the emitter layer 7 an emitter electrode 8 is disposed to form an ohmic junction with the emitter layer 7. As illustrated in FIG. 2, the valence band of the GaSb emitter layer 7 is located above the conduction band of the InAs collector layer 4 by about 150 meV, and interband tunneling is provided through the AlSb barrier layer 6. Quantum levels are formed in the InAs collector layer 4 disposed between the AlSb barrier layer 2 and the AlSb barrier layer 6, so that only electrons in the GaSb valence band having energy resonating those energy levels tunnel toward the InAs collector layer 4 to produce a collector current. With the thickness of an InAs quantum well assumed to be 10 nm (100 Å), a first quantum level E 0 is formed substantially above an InAs conduction band edge by about 80 meV and below a GaSb. valence band edge by about 70 meV. The quantum levels in the InAs collector layer 4 can be varied by gate Voltage applied to the gate electrode 3 located opposite to the GaAs emitter layer 7, with respect to the collector layer 4 whereby negative resistance characteristics of the embodiment can be controlled. With the gate electrode 3 supplied with negative voltage, negative voltage is applied to the InAs quantum well and a current is produced in a resonant manner when the quantum level is coincident with the Fermi level of the GaSb emitter. With the applied negative voltage increased further, the quantum level is shifted to be located in a GaSb gap. Hereby, the current is decreased to produce the negative resistance characteristics. Referring to FIG. 3, there is illustrated a collector current-voltage characteristic for varieties of the quantum levels. For constants used, the thickness of the AlSb barrier layer 6 is assumed to be 2 nm (20Å) and the Fermi level in thermal equilibrium is assumed to be located above the InAs conduction band by 75 meV. Referring to FIG. 4, there is illustrated an energy band structure of a second preferred embodiment. The identical operation to that of the transistor of the first embodiment is exhibited by reversing the polarity of the applied voltage. The present embodiment offers a complementary device to the first embodiment of FIG. 1. Referring to FIG. 5, there is illustrated an energy band structure of a third preferred embodiment. Although in FIG. 1 the collector electrode forms its contact on the quantum well layer, in the present embodiment a double barrier quantum well layer is inserted between an emitter and a collector to permit a collector layer to be made thicker. Formation of the collector electrode can thus be facilitated compared with the first arrangement. Referring further to FIG. 6, there is illustrated a fourth preferred embodiment of the present invention. Identical operation to the transistor of FIG. 5 is demonstrated by reversing the polarity of the applied voltage. The present embodiment offers a complementary device to the device of FIG. 5. According to the present invention, as described above, use is made of the interband tunneling instead of the prior art resonant tunneling between the conduction bands, whereby the tunnel current density is increased with the excess current being suppressed to permit the transistor of the present invention to be operational at room temperature. Compared with the prior art AlGaAs device, the transistor of the present invention suppresses the excess current to 1/6∼1/8 with the assumption of the current density to be constant and operation temperature to be 77K.

Claims: A tunneling transistor comprising: an emitter layer (7) made of a first semiconductor material having a conduction band and a valence band, said emitter layer having a first conductivity type; a barrier layer (6) made of a second semiconductor material having a conduction band and a valence band, the bottom of the conduction band of said second semiconductor material being higher in energy than the bottom of the conduction band of said first semiconductor material, and the top of the valence band of said second semiconductor layer being lower in energy than the top of the valence band of said first semiconductor material, said barrier layer having such a thickness that electrons can tunnel through said barrier layer; a collector layer (4) made of a third semiconductor material having a conduction band and a valence band, the bottom of the conduction band of said third semiconductor material being lower in energy than the top of the valence band of said first semiconductor material, and the top of the valence band of said third semiconductor material being higher in energy than the top of the valence band of said second semiconductor material, said collector layer having a conductivity type opposite to that of said emitter layer and such a thickness that quantum levels are formed in said collector layer; a gate layer (2) made of a semiconductor material having a conduction band and a valence band, a bottom of the conduction band of said semiconductor material of said gate layer being higher in energy than the bottom of the conduction band of said first semiconductor material, and a top of the valence band of said semiconductor material of said gate layer being lower in energy than the top of the valence band of said third semiconductor material, said gate layer having such a thickness that the probability of electron tunneling through said gate layer is greatly reduced; said layers being laminated in this order; electrodes (8, 5) which form ohmic contacts on said emitter layer and said collector layer, respectively; and an electrode (3) which forms a Schottky contact on said gate layer. A tunneling transistor comprising: an emitter layer made of a first semiconductor material having a conduction band and a valence band, said emitter layer having a first conductivity type; a barrier layer made of a second semiconductor material having a conduction band and a valence band, the bottom of the conduction band of said second semiconductor material being higher in energy than the bottom of the conduction band of said first semiconductor material, and the top of the valence band of said second semiconductor layer being lower in energy than the top of the valence band of said first semiconductor material, said barrier layer having such a thickness that electrons can tunnel through said barrier layer; a collector layer made of a third semiconductor material having a conduction band and a valence band, the top of the valence band of said third semiconductor material being higher in energy than the bottom of the conduction band of said first semiconductor material, and the bottom of the conduction band of said third semiconductor material being lower in energy than the bottom of the conduction band of said second semiconductor material, said collector layer having a conductivity type opposite to that of said emitter layer and such a thickness that quantum levels are formed in said collector layer; a gate layer made of a semiconductor material having a conduction band and a valence band, a top of the valence band of said semiconductor material of said gate layer being lower in energy than the top of the valence band of said first semiconductor material, and a bottom of the conduction band of said semiconductor material of said gate layer being higher in energy than the bottom of the conduction band of said third semiconductor material, said gate layer having such a thickness that the probability of electron tunneling through said gate layer is greatly reduced; said layers being laminated in this order; electrodes which form ohmic contacts on said emitter layer and said collector layer, respectively; and an electrode which forms a Schottky contact on said gate layer. A tunneling transistor according to claim 1 or 2 characterised in that a further barrier layer made of said second semiconductor material is disposed within said collector layer between said barrier layer and said gate layer, whereby a double barrier quantum well structure is formed by said barrier layer, said further barrier layer and the portion of said collector layer located therebetween, said quantum levels being formed in said portion of said collector layer.

Inventors: UEMURA TETSUYA, UEMURA, TETSUYA
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01L29
IPC codes: H01L29, H01L21