Process for manufacturing DC superconducting quantum interference device

Abstract: To reduce the number of steps of manufacturing a DC superconducting quantum interference device (as will be shortly referred to as "DC-SQUID"), which is to be applied to a highly sensitive electromagnetic sensor, an ammeter, a displacement meter a high-frequency signal amplifier or the like, thereby to improve the production yield. At the time of manufacturing the DC-SQUID, the number of masks is reduced to reduce the number of total steps by simultaneously performing the steps of fabricating an input coil 3 and a feedback coil 2 and the step of fabricating an counter electrode 13 of the components including a pick-up coil 1, the feedback coil 2, the input coil 3, a Josephson junction 10, a washer coil 11 and the counter electrode.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a DC superconducting quantum interference device (which will be shortly referred to as "DC-SQUID"), which is applied to a highly sensitive magnetic sensor, an ammeter, a displacement meter, a high-frequency signal amplifier or the like. 2. Description of the Prior Art The steps of the prior art are shown in sections in Figs. 2(a) to 2(e). These steps manufacture a SQUID integrated with a pick-up coil and begin fabricating a pick-up coil 1, a feedback coil 2 and an input coil 3 before the remaining steps. The individual steps will be briefly described in the following. Fig. 2(a) shows a step at which the surface is flattened with the first insulating film 4 after the pick-up coil 1, the feedback coil 2 and the input coil 3 are formed of a superconducting film. This superconducting film is formed by depositing Nb by a sputtering, and the first insulating film 4 is flattened by applying SOG after SiO 2 has been deposited by a plasma CVD. Fig. 2(b) shows a step at which a resistance film 5 for shunting or damping the SQUID is set to a designed value by a second insulating film 6 after it has been deposited. The resistance film 5 is made of Pd, and the second insulating film 6 is formed by evaporating MgO together. Figs. 2(c) and 2(d) show steps at which a Josephson junction 10 and a washer coil 11 are fabricated. The Josephson junction 10 is deposited a Nb/Al-oxide/Nb structure by a sputtering. The washer coil 11 is formed of a lower electrode 7 of the Josephson junction 10. Fig. 2(e) shows a step at which an opposed electrode 13 of a superconducting film is formed after a third insulating film 12 has been deposited. The third insulating film 12 and the counter electrode 13 are deposited together, respectively, by evaporating SiO and Pbln. According to the steps of Fig. 2, the pick-up coil 1, the feedback coil 2 and the input coil 3 are fabricated before the remaining steps so that the number of masks for patterning the deposited films by a photolithography increases. Since the number of steps increases, the time for the manufacture is elongated to reduce the production yield of the element. SUMMARY OF THE INVENTION It is an object of the present invention to provide a reduced steps and improved yield process for manufacturing highly sensitive magnetic field detector. The feedback coil and the input coil can be isotropically etched to have a tapered pattern thereby to eliminate the flattening step by the SOG. In order to achieve the object of the invention a method according to claim 1 is employed. Claim 2 relates to a preferred embodiment of the invention. Since the number of masks is reduced by the above-specified process, the number of steps can be reduced to manufacture a magnetic field detector having improved production yield and characteristics. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1(a) to 1(d) are sectional views showing the steps of a first embodiment of the present invention. Figs. 2(a) to 2(e) are sectional views showing the steps of the prior art. Fig. 3 is a top plan view showing the first embodiment of the present invention. Figs. 4(a) to 4(d) are sectional views showing the steps of a second embodiment of the present invention. Fig. 5 is a top plan view showing the second embodiment of the present invention. Figs. 6(a) to 6(d) are sectional views showing the steps of a third embodiment of the present invention. Figs. 7(a) to 7(d) are sectional views showing the steps of a fourth embodiment of the present invention. Fig. 8 is a top plan view of a DC-SQUID having double-washer coils connected in series. Fig. 9 is a top plan view of a DC-SQUID having double-washer coils connected in parallel. Fig. 10 is a top plan view showing a gradiometer DC-SQUID. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in the following in connection with the embodiments thereof with reference to the accompanying drawings. Fig. 3 is a top plan view showing a first embodiment of the present invention. Figs. 1(a) to 1(d) are sections taken along line A - A' of Fig. 3 and showing the steps. The manufacture process will be described with reference to Figs. 1(a) to 1(d). Fig 1(a) shows a step at which a resistance film 5 for shunting or damping a DC-SQUID is insulated by a second insulating film 6 to have a designed resistance after it has been deposited. The resistance film 5 can be made of a metal such as Mo, MoN, Pd, Au, Cu, A l or Pd, any of which can be deposited by a sputtering or evaporation. Here, the Mo is deposited to athickness of 100 nm by magnetron sputtering and is patterned to a designed size by a photolithographic step. The second insulating film 6 can be made of SiO 2 , SiO, Si or MgO. Any of these materials can be deposited by the sputtering, evaporation or CVD. The deposited film is set to be 1.5 to 2 times as thick as the resistance film 5 so as to insulate the resistance film 5 completely. Here, the SiO 2 is deposited to 150 to 200 nm by magnetron sputtering and is enabled to contact with the resistance film 5 by the photolithographic step. Both the wet and dry etching methods can be used for etching the SiO 2 . The wet etching is exemplified by a method using a mixture of hydrofluoric acid. The dry etching is exemplified by a reactive ion etching (i.e., RIE) using a mixture of CF 4 or CHF 3 and oxygen. Here, the SiO 2 is etched by the RIE using the mixture of CHF 3 and oxygen. Fig. 1(b) shows a step for fabricating a Josephson junction 10, at which a lower electrode 7, a barrier layer 8 and an upper electrode 9 are deposited and at which the upper electrode 9 and the barrier layer 8 are etched by the photolithography. The Josephson junction 10 can be exemplified not only by the Nb/A l -oxide structure but also by a variety of structures of NbN/MgO/NbN, Nb/Si/Nb, Nb/Nb-oxed/Nb. Here, the Nb/A l -oxide/Nb structure is deposited by the sputtering. Examples of the deposition are as follows. An argon gas is introduced into a reaction chamber, which is evacuated to a high vacuum of 10 -5 Pa or less, and the Nb film of the lower electrode 7 is deposited under a pressure of 0.2 to 4 Pa by the DC magnetron sputtering. The film is set to be about 1.5 to 2 times as thick as the second insulating film 6 and is deposited to 200 to 300 nm. Then, the introduction of the argon gas is interrupted, and the reaction chamber is evacuated to a high vacuum of 10 -5 Pa or less. After this, the argon gas is introduced so that the Al is deposited to 1 to 20 nm under a pressure of 0.2 to 4 Pa by the DC magnetron sputtering. Here arises no problem unless the evacuation to a high vacuum is elaborately performed before the sputtering of the A l . The reaction chamber is evacuated to a high vacuum of 10 -5 Pa or less, and an oxygen gas or a mixture of oxygen and argon is introduced to adjust the pressure to the set level. Then, the A l surface is oxidized to form the barrier layer 8 of A l Ox/A l . The reaction chamber is evacuated to a high vacuum of 10 -5 Pa or less, and the upper electrode 9 is deposited to 100 to 300 nm under the aforementioned Nb depositing condition. Next, the upper electrode 9 and the barrier layer 8 are etching at the photolithographic step to form the Josephson junction 10. The etching method used is generally the dry etching method using a plasma. The Nb of the upper electrode 9 is subjected to the reactive ion etching (i.e., RIE) using CF 4 or a mixture of CF 4 and oxygen. The A l of the barrier layer 8 is removed by either the wet etching method using an acid or the RIE using an Ar gas. Here, the barrier layer 8 need not be etched. Fig. 1(c) shows a step, at which a detection coil 1, a feedback modulation coil 2 and an input coil 3 are formed by patterning the superconducting film deposited as the lower electrode 7 of the Josephson junction 10 by the photolithography. The etching method used is generally the dry etching method using plasma. The Nb of the lower electrode 7 is subjected to the plasma etching or reactive ion etching (i.e., RIE) using a mixture of CF 4 and oxygen. Here, the etching is so different from that of the aforementioned upper electrode 9 that the isotropic etching is effected by increasing the amount of oxygen and that the resist film in the peripheral of the pattern is etched with the oxygen into a tapered shape. The etching can be specifically exemplified by using the plasma etching apparatus with a gas, which is prepared by adding 10 % of oxygen to the CF 4 , under a pressure of 133 Pa and with a power of 50 W. Fig. 1(d) shows a step, at which: a third insulating film 12 or an inter-layer insulating film is deposited; a contact hole is then formed by the photolithography; and a superconducting film is then deposited to form a washer coil 11 and an electrode 13 by the photolithography. The third insulating film 12 can be deposited by a method similar to that of the second insulating film 6. Here, the SiO 2 is deposited to 300 to 500 nm by magnetron sputtering, and the contact hole is formed by the photolithography. The etching of the SiO 2 is performed by the RIE like the second insulating film 6. The superconducting film is exemplified by the Nb, NbN, Pb-In or Pn-ln-Au which is deposited by the sputtering or evaporation. Here, the Nb film is deposited to 400 to 600 nm by the DC magnetron sputtering like the electrode of the Josephson junction. Before, the deposition, the substrate is inversely sputtered with the Ar gas so as to form the superconducting contact. After this, the washer coil 11, the counter electrode 13 and other wiring portions are formed by the photolithography. The etching is exemplified by the plasma etching like the aforementioned lower electrode 7. Fig. 5 is a top plan view showing a second embodiment of the present invention, from which the pick-up coil 1 is omitted. Fig. 4 is a section taken along line A - A' of Fig. 5. This method fabricates the counter electrode 13 simultaneously with the pick-up coil 1, the feedback coil 2 and the input coil 3, and the methods of fabricating the individual layers are similar to those of the first embodiment. Fig. 6 presents sections showing the steps of a third embodiment. This manufacture process is different from the foregoing two embodiments in the method of forming the Josephson junction 10 such that the upper electrode 9 is formed after the etching has been performed beforehand up to the lower electrode 7. (Figs. 6(b) and 6 (c)) At this step, the second insulating film 6 has to be left unetched at the time of etching the upper electrode 9. In case the second insulating film used is made of SiO 2 , SiO or Si, its surface is covered with A l , and oxide film of A l or MgO so that it may not be etched. Fig. 6 corresponds to the first embodiment of Fig. 1 but can also be applied to the second embodiment if the pick-up coil 1, the feedback coil 2 and the input coil 3 are fabricated at steps similar to those of the second embodiment. Fig. 7 presents sections showing the steps of a fourth embodiment. This embodiment is a process for self-aligning the third insulating film 12 at a lift-off step. Specifically, the upper electrode 9 is etched by the RIE by using a photoresist as a mask, and the SiO is deposited by the evaporation and lifted off. Since the fourth embodiment is dispensed with the photolithography step for forming the contact hole in the third insulating film, the number of masks is further reduced to provide a manufacture process having less steps. Although the several embodiments have been described, a number of other manufacture processes can be achieved by interchanging the order of the individual layers. For example, the last layer need not be tapered but may be patterned at the lift-off step. The resistance film 5 is fabricated at first but may be fabricated after the Josephson junction 10 has been fabricated. The foregoing embodiments are exemplified by the DC-SQUID made of the single washer coil. If two washer coils are used, the magnetic field, which might otherwise go directly into them, can be canceled to detect the magnetic field in higher sensitivity with the detection coil. In the aforementioned individual embodiments of the DC-SQUID manufacturing steps, the DC-SQUID can have two washer coils. Fig. 8 is a top plan view showing the DC-SQUID in which the washer coils are connected in series. Fig. 9 is a top plan view showing a DC-SQUID, in which washer coils are connected in parallel. Moreover, a DC-SQUID of the gradiometer type for detecting a magnetic field gradient can also be manufactured, as shown in top plan view in Fig. 10. The components are a first-order differential type detection coil 1 and a DC-SQUID body 15, which is of the double-washer type of Fig. 8 or 9. According to the present invention, it is possible to manufacture the DC-SQUID with a reduced number of masks and at a reduced number of steps and to manufacture a magnetic field detection circuit which has improved production yield and reproductivity.

Claims: A process for manufacturing a DC superconducting quantum interference device having a pick-up coil (1) for detecting a magnetic field to produce a signal current, an input coil (3) superconductively coupled to said pick-up coil (1) through two input terminals, a feedback coil (2) for transmitting a signal coming from an external control system, a washer coil (11) magnetically coupled to said input coil (3) and said feedback coil (2) for constituting a superconducting ring, and a Josephson junction (10) connecting a counter electrode (13) and said washer coil (11) and sandwiching a barrier layer between a lower electrode (7) and an upper electrode (9) for converting said signal current into a voltage characterized in that the process includes the steps of fabricating either said Josephson junction (10) simultaneously with fabricating the input coil (3) and said feedback coil (2) whereby said pick-up coil (1), said feedback coil (2) and said input coil (3) are formed by patterning a super conducting film deposited as the lower electrode (7) of said Josephson junction (10) by photolithography, or fabricating said counter electrode (13) directly adjacent to the upper elctrode (9) of the Josephson junction simultaneously with fabricating said input coil (3) and said feedback coil (2), whereby said pick-up coil (1), said feedback coil (2) and said input coil (3) are formed by patterning a super conducting film deposited as the counter-electrode (3) by photolithography. The process according to claim 1, wherein at least one of said input coil (1), said feedback coil (2) and said washer coil (11) is formed by an isotropic etching to have a tapered section.

Inventors: CHIBA NORIO, CHINONE KAZUO, SHIMIZU NOBUHIRO, CHIBA, NORIO, CHINONE, KAZUO, SHIMIZU, NOBUHIRO, CHIBA, NORIO, C/O SEIKO INSTRUMENTS INC., Chinone, Kazuo, c/o Seiko Instruments Inc., Shimizu, Nobuhiro, c/o Seiko Instruments Inc.
Applicants: SEIKO INSTR INC, SEIKO INSTRUMENTS INC.
Application year: 1992
Main classification: H01L39
IPC codes: H01L39, G01R33