ARBITRARY WAVEFORM GENERATOR ARCHITECTURE

Abstract: A method of direct digital synthesis of linear frequency modulated wave forms comprising the steps of: at a given regular time, adding a fixed frequency increment word (1) to a frequency control value stored in a first register (4) to produce a lineally increasing frequency control word; adding the frequency control word stored in the first register (4) to a second register (8) to form a quadratically increasing phase word; converting the quadratically increasing phase word to an amplitude value using a lookup table stored in a memory means (9) to produce a lineally increasing frequency, and periodically resetting the frequency control word to produce a frequency sawtooth. Also a device for implementing the method being an arbitrary waveform generator comprising a pluraality of accumulators (4+5, 7+8), a memory means (9), a convertor means (10) and a clock means (6).

Description: ARBITRARY WAVEFORM GENERATOR ARCHITECTURE BACKGROUND OF THE INVENTION This invention relates to a method of digitally generating linear frequency modulated continuous wave (FMCW) waveforms at high frequency for use in such applications as high-frequency radar systems. In its most general sense the invention can be applied to any system requiring virtually any waveform. In this discussion its application in HF radar systems will be used as an example. Signal sources used in HF radar systems require very high dynamic range, low phase noise and amplitude accuracy over a wide frequency band. In many applications they also require fast frequency switching and known phase characteristics. Typical signal sources use one of two methods to generate these signals - phase locked loop synthesis or direct digital synthesis. Phase locked loop methods, in their most simple form, suffer from poor phase noise and/or poor frequency resolution (a relative large step between permissible frequencies). Frequency switching time can also be rather poor (long). Direct digital synthesis methods are usually based on phase accumulator techniques or memory look-up techniques. These techniques allow for both low phase noise and narrow frequency resolution. However, the phase accumulator design is optimised for the generation of a fixed frequency tone and the memory lookup technique suffers from large computational overheads as all data points must be calculated in advance. This invention combines and extends the phase accumulator technique to provide a device which can generate arbitrary or pseudo-arbitrary waveforms. This is particularly important in a real-time system. The invention described here may be used as a pseudo-ar f " trary waveform generator with high capability and low computational overhead. A common waveform used in HF radar systems is the linear frequency modulated continuous wave (FMCW) waveform, where the frequency is swept linearly up or down over a programmable frequency span in a programmable ' time interval, in order to generate these signals from conventional signal sources it is necessary to approximate the desired waveform by a series of short fixed-frequency steps. This invention can produce true linear FMCW waveforms. The technique may be further extended to produce more complex waveforms of higher order, or these waveforms may be approximated by a piecewise linear approximation. This approximation, being a second order approximation, is inherently more accurate than the first order approximation of conventional phase accumulator techniques. The continuous time equation for a single cycle of a sawtooth waveform (linear FMCW ramp) is given by : where T = the period of the waveform ω 0 = 2πf 0 the starting frequency of the ramp G& 1 = 2πfϊ the ending frequency of the ramp. Converting this equation to an equivalent discrete time equation with sampling period t s and adding the constraint that there are an integer number (N) of samples in a ramp period, reveals that it can be written more simply as : f(n) = SIN[n(a + bn)] where a = ω 0 .t s This analysis leads to the discovery that a discrete digital synthesis ramp generator may be implemented with two levels of accumulation and a sinusoidal look-up ROM if the two phase registers are loaded with the initial values a + b and 2b respectively. The technique of cascading accumulators can be extended to allow the generation of higher order waveforms. In fact any waveform s(t) = SIN(φ(t)) where φ(t) = ao+a-it + a2t 2 + ... +a n t n can be generated with n cascaded accumulators. By including a cosine lookup ROM as well as a sine lookup ROM any waveform s(t) = eiΦtø can be generated. Note also that the lookup ROM is not constrained to sinusoidal waveforms, but can be used to map any periodic function. In practice implementing further stages of accumulation becomes difficult due to a need for greater arithmetic precision in the early stages of accumulation, and to account for propagation delays through the accumulator chain. The design presented here approximates higher order waveforms by a piecewise linear approximation. SUMMARY OF THE INVENTION According to perhaps one form of this invention there is proposed an arbitrary waveform generator comprising : a plurality of accumulators each adapted to produce an output value from one or more input values; one or more memory means adapted to map the output of one or more accumulators to an amplitude value; a converter means adapted to convert the amplitude value from digital form to analogue form; and a control means adapted to synchronise the operation of the waveform generator. In preference the input values are In preference the converter means is a digital to analogue converter that converts a digital signal from the digital section of the generator to an analogue signal. In preference the memory means is an addressable solid state memory device such as a read only memory device containing a look-up table for mapping a linear variation in phase to a sinusoidal variation in amplitude. Alternatively, the memory means could be an EPROM, Beta card, DRAM or other similar memory device. The memory device look-up table may contain other periodic functions. In preference the control means is a microprocessor incorporating a clock means which is a high purity oscillator. In order to interface to the very complex waveform scheduling requirements of on operational OTHR radar control system a high performance microprocessor is required. In preference there is provided a filter means which filters the output of the digital to analogue converter. In practice this is a low pass filter. In a further form of this invention there is proposed a method of direct digital synthesis of linear frequency modulated waveforms comprising the steps of : at a given regular time, adding a fixed frequency increment word to a frequency control value stored in a first register to produce a linearly increasing frequency control word; adding the frequency control word stored in the first register to a second register to form a quadratically increasing phase word; converting the quadratically increasing phase word to an amplitude value using a look-up table stored in a memory means to produce a linearly increasing frequency; and periodically resetting the frequency control word to produce a frequency sawtooth. In preference the amplitude value is converted from a digital value to an analogue value using a digital to analogue converter. In preference there is provided a filter means after the digital to analogue converter and in preference this is a low pass filter. In preference there is provided a clock means to provide the given regular time and control the periodic resetting. DESCRIPTION OF THE PREFERRED EMBODIMENT For a better understanding of this invention a preferred embodiment will now be described with reference to the attached drawing in which : FIG 1 is a schematic of an arbitrary waveform generator consisting of two phase accumulator stages. Phase accumulator signal synthesis is a digital technique whereby a fixed phase increment is added to a value stored in a phase register, giving rise to a linearly varying phase. As the instantaneous frequency is defined to be the time derivative of the phase, the phase accumulator thus generates a fixed frequency signal. This signal is mapped to an amplitude by a sinusoidal lookup table, which may then be converted to an analogue form by a digital- to-analogue converter. Referring in detail to the figure, the inputs to the generator are a frequency increment word 1 , an initial frequency 2 and an initial phase 3. The frequency register 4 is incremented in an adder 5 by the value of the increment word 1 on each reference clock pulse of a clock 6, giving a linear frequency progression. The linearly changing frequency output from the frequency register 4 is added in adder 7 to the phase register 8 on each clock pulse to produce a quadratic phase progression which is mapped by the ROM 9 to produce a linearly increasing frequency ramp. By resetting the control values at regular intervals the output becomes a repetitive frequency sawtooth. A digital to analogue converter 10 converts the digital signal 11 to analogue form which is subsequently passed through a low-pass filter T2 to produce the desired output. Each ramp can be completely defined by four parameters or control values : initial phase, initial frequency, frequency increment word and duration of ramp. Any of the first three parameters may be unused (taking the final value of the previous ramp), which allows for greater flexibility in waveform generation and reduces some computational overhead. A logical extension of this technique is to implement more stages of accumulation to generate polynomials of higher order, allowing even more complex waveforms to be generated directly. However, current technology imposes restrictions on the capability of such higher-order polynomials, such that it is presently more appropriate to generate these higher-order polynomials in a piecewise linear approximation using short linear FMCW ramps. The method of controlling this dual phase accumulator allows independent setting of the initial phase, initial frequency, and frequency deviation rate. It also allows pseudo-arbitrary waveforms to be generated relatively simply by means of piecewise linear approximation with short time intervals (possibly as short as 10-20 microseconds). This is a very powerful method of generating pseudo-arbitrary waveforms, as the length of the waveform sequence is dependent only on the storage requirements for the waveform definition, rather than on the storage requirements for the entire sequence (as in the memory lookup method of arbitrary waveform synthesis). It also allows real¬ time generation of data points, avoiding the long overheads of memory lookup techniques. The waveform generator may be configured to either repetitively generate the same ramp or produce a series of independent ramps. Pseudo-arbitrary waveforms can be generated by a piecewise linear approximation of ramps to the desired waveform instead of using a multiple accumulator architecture of higher order. As each ramp segment is defined by four parameters only it is possible to reduce the minimum ramp duration to the time required to transfer these four parameters to the appropriate registers. With current high performance microprocessors a minimum step size of 10 to 20 microseconds is a physically achievable value that will provide a good approximation to most desired waveforms. The pseudo-arbitrary waveform is implemented as a series of short frequency ramps approximating the desired waveform. The total number of ramp segments that can be put in a sequence has yet to be determined, but will number in the thousands and will be limited only by parameter storage requirements. The speed of programming and implementing these ramps as well as the maximum number of ramps is determined only by the speed and storage capabilities of the controlling microprocessor. This is a very powerful method of producing pseudo-arbitrary waveforms and allows very complex waveforms of long duration to be generated relatively simply without recourse to multiple accumulator architectures. The invention offers a number of advantages. The output frequency can be changed very rapidly without impacting on the quality of the output signal. The non-pipelined nature of the design allows the output frequency to change within a single sampling clock period. Furthermore, any changes in frequency are controlled to provide non-discontinuous changes in phase and frequency unless discontinuity is desired, in which case the discontinuity is known and can thus be controlled. In the same manner as a single phase accumulator is optimised for a fixed frequency tone, the dual accumulator is optimised for quadratic phase generation (i.e. linear FMCW). The addition of further stages of phase accumulation provide a method for optimised generation of higher order waveforms. Being all digital the phase and amplitude are controlled at all times. This has particular importance in radar systems where a coherent detection process is implemented. Coherent detection requires a known, repeatable phase progression and phase errors translate directly to errors in detection.

Claims: CLAIMS 1. An arbitrary waveform generator comprising : a plurality of accumulators each adapted to produce an output value from one or more input values; one or more memory means adapted to map the output of one or more accumulators to an amplitude value; a converter means adapted to convert the amplitude value from digital form to analogue form; and a control means adapted to synchronise the operation of the plurality of accumulators, the one or more memory means and the converter means. 2. The arbitrary waveform generator of claim 1 further comprising a plurality of input registers adapted to store the input values. 3. The arbitrary waveform generator of claim 1 in which each accumulator comprises an adder means adapted to add two input values to produce an output value and a register means adapted to store said output value. 4. The arbitrary waveform generator of claim 3 in which one of the input values is the previous value stored in the register means. 5. The arbitrary waveform generator of claim 1 in which the memory means is addressable solid state memory. 6. The arbitrary waveform generator of claim 1 in which the memory means contains a look-up table for mapping the accumulator output to the amplitude value. 7. The arbitrary waveform generator of claim 1 in which the converter means is a digital to analogue conversion device. 8. The arbitrary waveform generator of claim 1 in which the control means is a microprocessor means adapted to provide a clock reference signal to which the waveform generator is synchronised. 9. The arbitrary waveform generator of claim 1 in which the control means comprises a microprocessor means, reference clock means and synchronising signal means working in cooperation to synchronise the operation of the waveform generator. 10. The arbitrary waveform generator of claim 1 further comprising a filter means adapted to filter the output of the converter means. 11. An arbitrary digital waveform generator comprising : a plurality of accumulators each adapted to produce an output value from one or more input values; one or more memory means adapted to map the output of one or more accumulators to an amplitude value; and a control means adapted to synchronise the operation of the plurality of accumulators and the one or more memory means. 12. The arbitrary waveform generator of claim 11 in which each accumulator comprises an adder means adapted to add two input values to produce an output value and a register means adapted to store said output value. 13. The arbitrary waveform generator of claim 12 in which one of the input values is the previous value stored in the register means. 14. The arbitrary wavet.. m generator of claim 11 in which the memory means contains a look-up table for mapping the accumulator output to the amplitude value. 15. An arbitrary waveform generator for generating a linear frequency ramp comprising : first and second accumulators each adapted to produce an output value from two input values wherein one of the input values to the first accumulator is a frequency increment word id the output of the first accumulator is the input to the second accumulator; a memory means adapted to map the output of the second accumulator to a sinusoidally varying amplitude value; and a control means adapted to synchronise the operation of the plurality of accumulators, the one or more memory means and the converter means. 16. The arbitrary waveform generator of claim 15 further including a converter means adapted to convert the amplitude value from digital form to analogue form. 17. The arbitrary waveform generator of claim 15 in which each accumulator comprises an adder means adapted to add the two input values to produce the output value and a register means adapted to store said output value and further characterised in that the value stored in the register means is one of the inputs to the adder means. 18. An arbitrary waveform generator for generating a linear frequency modulated continuous wave waveform comprising : a control means incorporating a reference clock; a first accumulator adapted to produce a linear frequency progression by incrementing a frequency register by the value of a frequency increment word once every reference clock cycle; a second accumulator adapted to produce a quadratic phase progression by adding the linear frequency progression to a phase register once every clock cycle; and a memory means adapted to produce a linearly increasing frequency ramp from the quadratic phase progression by mapping from a sinusoidal look-up table. 19. The arbitrary waveform generator of claim 18 further including a digital to analogue converter adapted to convert the linearly increasing frequency ramp from digital form to analogue form. 20. The arbitrary waveform generator of claim 18 in which the linearly increasing frequency ramp is defined by : the frequency increment word; an initial frequency value stored in the frequency register prior to a first clock cycle; an initial phase value stored in the phase register prior to the first clock cycle; and a duration of the ramp being the number of clock cycles for which increments occur. 21. A method of direct digital synthesis of linear frequency modulated waveforms comprising the steps of : at a given regular time, adding a fixed frequency increment word to a frequency control value stored in a first register to produce a linearly increasing frequency control word; adding the frequency control word stored in the first register to a second register to form a quadratically increasing phase word; converting the quadratically increasing phase word to an amplitude value using a look-up table stored in a memory means to produce a linearly increasing frequency; and periodically resetting the frequency control word to produce a frequency sawtooth. 22. The method of claim 21 further including the step of converting the amplitude value from digital form to analogue form in a converter means. 23. The method of claim 21 further including the step of filtering the output of the converter means. 24. The method of claim 21 in which the look-up table is a sinusoidal look-up table. 25. The method of claim 21 wherein the given regular time is provided by a reference clock means. 26. An arbitrary waveform generator as herein described with reference to the attached figure.

Inventors: DURBRIDGE LYNDON JOHN, DURBRIDGE, LYNDON, JOHN
Applicants: COMMW OF AUSTRALIA, THE COMMONWEALTH OF AUSTRALIA
Application year: 1992
Main classification: H03K4
IPC codes: G01S7, G01S13, G06F1, H03B28