Electrostatic discharge protective device having a reduced current leakage

Abstract: In an anti-ESD protective structure, especially designed for pins destined to reach below ground and/or above supply voltages, includes a pair of Zener diodes or lateral NPN structures with a resistive connection between base and emitter, connected in opposition among each other between the pin to be protected and a grounded substrate of the integrated circuit. An amplifying effect on the leakage current which is drawn/injected through the pin by the protective structure caused by the triggering of an intrinsic parasitic transistor is effectively eliminated by connecting a biasing element, such as a forward biased junction, between the node of interconnection between the two Zener orlateral NPN structures and a node of the integrated circuit biased with a voltage sufficiently high as to ensure, under any condition, a reverse biasing of the base-emitter junction of the parasitic transistor.

Description: BACKGROUND OF THE INVENTION Integrated circuits are often provided with protective integrated structures against electrical discharges of electrostatic origin which may hit an external pin of the integrated circuit. The basic principle of operation of an electrostatic discharge (ESD) protective device consists in limiting to an established maximum tolerable value, dictated by the particular fabrication process, voltage spikes which may occur on the pins of the integrated circuit, in order to prevent breakdown of integrated structures which are connected to the respective pins, and which because of their intrinsic characteristics are often unable to tolerate voltage spikes greater than a certain amplitude. The amplitude of voltage spikes of an electrostatic origin may easily reach several KV with a maximum energy associated therewith on the order of several mjoule, e.g. according to the so-called "Human Body Model". In view of the fact that the rise time of these spikes is typically a few nanoseconds (ns), the reaction time of the protection structure must be extremely fast. Commonly the integrated structures used for implementing an ESD protection are constituted by Zener diodes, SCR, and lateral NPN structures with a resistive connection between base and emitter. A prior art integrated structure of this latter type, as depicted in Fig. 1, has the configuration of a lateral NPN transistor wherein its base region is connected to its emitter region through a resistive path. The structure may be considered a diode constituted by the base/collector junction, which exhibits a voltage/current characteristic having a well defined zone showing a negative slope in the first quadrant. Other equivalent electrical schemes of the prior art integrated structure of Fig. 1 are shown in figures 2A and 2B for simplicity's sake or the prior art integrated structure of Fig. 1 may be symbolically indicated by means of a diode symbol inscribed in a circle together with an asterisk, as depicted in Fig. 2C. Commonly in literature, this prior art discharge structure is referred to simply as "lateral NPN", with the understanding that the NPN structure includes a resistive connection between the base and emitter regions, when configured for use as an ESD protection device. In addition, some pins of integrated circuits (e.g. an input pin) must be capable of operating with negative voltages with respect to ground (i.e., below ground), and/or with voltages higher than the supply voltage, as it is well known to a person skilled in the art. An ESD protection device may be implemented also for these pins; a prior art such device is symbolically shown in Fig. 3. In such prior art devices, the ESD protection device is implemented by utilizing two Zener diodes, Z1 and Z2, or two lateral NPNs with a resistive connection between base and emitter, connected in series and in opposition with each other between the (input) pin to be protected and a substrate of the integrated circuit connected to ground. This type of prior art integrated protection structure has several drawbacks tied to the triggering of an intrinsic parasitic transistor which makes the structure unusable in integrated circuits wherein a very small current absorption of the ESD protection structure must be ensured; for example, in the case of an input pin of an operational amplifier. Figures 4 and 5 show schematically a prior art integrated protection structure realized in an integrated circuit having typical junction-isolation architecture and comprising a p-type semiconducting substrate and an n-type epitaxial layer, wherein the various devices are formed within regions of the n- type epitaxial layer laterally defined by p+ isolation diffusions. Both in Fig. 4 and in Fig. 5, a PNP parasitic transistor (PNPparas.), intrinsic to the integrated protection structure Z2. In this case, the base current of the parasitic transistor is constituted by the leakage current (Ileak) of the diffusions which realize the two Zener diodes, Z1 and Z2, beside the intrinsic leakage current of the Z2 diode and the total current drawn by the ESD protection structure through the protected pin. This total current is given by the following relation: I tot = I leaktot x G where G is the current gain of the parasitic transistor, which is intrinsic to the integrated ESD protection structure. As a consequence the current which is drawn (or injected) through the relative pin of the integrated circuit, the current represents an intrinsic leakage current amplified by the parasitic transistor and, therefore, may reach untolerable levels for many applications. A parasitic PNP transistor is also present also within the integrated structure of a lateral NPN and is provided with a resistive connection between base and emitter, which is usable in place of a Zener structure as a discharge element, as symbolically shown in Fig. 1. The document FR-A-2,590,726 discloses an output half-bridge stage employing a pair of reverse biased diodes connected between the output node and the supply rails, respectively, for providing a recirculation path for the discharge current of an inductive external load driven by the stage. The document US-A-4,302,792 discloses an arrangement employing a pair of complementary transistors, biased by sources of reference voltages for protecting a circuit node from an electrostatic discharge and establishing a voltage bias of the node. A biasing resistance is connected between the node and a bias voltage source for biasing the base of a transistor connected to said node. SUMMARY OF THE INVENTION Accordingly a general object of the present invention is to provide a circuit arrangement which may be easily realized, and which practically nullifies the amplifying effect of an intrinsic parasitic transistor on the intrinsic leakage current of a particular ESD protection structure. Another object of the present invention is to provide a protective structure usable with specific types of pins of an integrated circuit when a low current leakage must be ensured. An integrated structure according to the present invention is defined in claim 1. A method of protecting integrated components according to the present invention is defined in claim 6. These objects and other advantages of the present invention are achieved by employing a biasing element, connected between a connection node between two discharge elements of the ESD protection structures (such as two Zener diodes in opposition with each other or between two lateral NPN structures with a resistive connection between base and emitter, and which coincides with a base region of an intrinsic parasitic transistor), and a circuit node which is maintained at a certain voltage Vx having a value which satisfies the following condition: Vx-Vfd > Vin(+) max where Vfd represents a voltage drop through said biasing element and Vin(+)max represents the maximum design voltage (positive with respect to ground) which the protected pin will reach during a normal operation of the circuit, in order to reverse bias the base-emitter junction of the parasitic transistor, thus nullifying its amplifying effect upon the total leakage current of the integrated anti ESD protection structure. The biasing element may be constituted by a forward biased diode or a functionally equivalent structure such as, for example, a Zener junction or a lateral NPN structure with a resistive connection between base and emitter. BRIEF DESCRIPTION OF THE DRAWINGS As described above, Figures 1, 2A, 2B and 2C, show a prior art integrated discharge structure used for implementing ESD protection, consisting of a lateral NPN transistor with a resistive connection between base and emitter. Figures 3, 4 and 5 schematically depict prior art ESD protection structures for a pin of an integrated circuit. Figure 6 shows an embodiment of the improved integrated ESD protective structure of the present invention. Figure 7 is a partial illustration of an integrated circuit, e.g. an operational amplifier, provided with a protective device of the invention, specifically applied to two input pins of the integrated circuit. Figure 8 is a partial illustration of an integrated circuit similar to the one depicted in Fig. 7, wherein the anti ESD protective device of the invention is realized by employing lateral NPN transistors with a resistive connection between base and emitter in place of Zener diodes. DETAILED DESCRIPTION With reference to the circuit shown in Fig. 6, an anti ESD protective integrated device of the invention comprises a forward biased diode D1, functionally connected to a node at Vx potential, and capable of inversely biasing the base-emitter junction of a parasitic PNP transistor (PNPparas.) (symbolically depicted by means of phantom lines) of the integrated protective structure. The structure includes two Zener Z1 and Z2, used, in conjunction with diode D 1 , to nullify the amplifying effect on the leakage current by the intrinsic parasitic PNP transistor. Such a nullifying effect is achieved by connecting the biasing diode D1 to a voltage Vx having a level which will satisfy the above-indicated condition (1). In the specific embodiment depicted in Fig. 4 as it relates to an input pin of a functional circuit, because under normal operation conditions of the integrated circuit the Zener diode Z2 must be prevented from going into breakdown when the applied voltage on the input pin Vin drops to the maximum negative design value with respect to ground, the Vx voltage may advantageously have a value which also satisfies the following condition: Vbz1 > | Vin(-) | + (Vx-Vfd) where Vbz1 is the voltage drop across the Zener Z1. These considerations remain valid also when in place of the Zener diodes, lateral NPN structures with a resistive connection between base and emitter are used. The current which is eventually absorbed/injected through the protected pin by the ESD protection structure of the invention will remain purely an intrinsic leakage current without being subject to any amplifying effect because of the triggering of an intrinsic parasitic transistor. The anti ESD protection structures as may be applied to the pins of an integrated operational amplifier are schematically shown in Fig. 7. In the application shown, the pins protected by means of the improved structure of the present invention are the two input pins: In(-) and In(+). In the embodiment of Fig. 7, the biasing element is the Zener diode Z8 which performs the same function of the diode D1 of the circuit depicted in Fig. 6. The voltage node VDD to which the biasing diode Z8 is connected, coincides, in the embodiment of Fig. 7, with the node Vx of Fig. 6. This arrangement is possible whenever the contemplated maximum design voltage for the two input pins is lower than VDD-Vfd. As should be evident to one skilled in the art, the particular configuration of the ESD protective structure will protect all the pins from positive and negative discharges as well as from discharges among different pins, as contemplated by widely applied standard specifications. Of course the Zener diodes of the protection structure of Fig. 7 may be replaced by lateral NPN structures with a resistive connection between base and emitter, as symbolically shown in Fig. 8. Only the supply pin (VDD) remains protected by means of a Zener diode Z1. In this embodiment the biasing function performed by the diode D1 of Fig. 6 is performed by the lateral NPN S5.

Claims: An integrated structure for protecting integrated components that are connected to a pin of an integrated circuit which may be hit by an electrostatic discharge, the structure comprising: an integrated pair of discharging elements (Z1, Z2) connected in series and in opposition to one another between said pin and a node at ground potential, each pair being composed of two Zener diodes or two diode-configured lateral NPN transistors; a biasing element (D1), which comprises a forward biased junction, connected between the intermediate connection node between said counteropposed discharging elements (Z1, Z2) and a supply voltage node (Vx), voltage supply means to apply a supply voltage at said supply voltage node such that said supply voltage is greater than the maximum design voltage reached by the pin under normal operating conditions, incremented by the voltage drop across said biasing element. An integrated structure as recited in claim 1, wherein each discharging element (Z1, Z2) is a lateral NPN structure having a resistive connection between a base region and emitter region thereof. An integrated structure as recited in claim 1, wherein said biasing element (D1) is a diode. An integrated structure as recited in claim 1, wherein said biasing element (D1) is a Zener diode. An integrated structure as recited in claim 1, wherein said biasing element (D1) is a lateral NPN structure having a resistive connection between a base region and an emitter region thereof. A method of protecting integrated components that are connected to a pin of an integrated circuit which may be hit by an electrostatic discharge by employing an integrated protection structure as defined in any one of the preceding claims, wherein the voltage (Vx) of the supply node is greater than the maximum voltage that is reached by the protected pin under normal operating conditions , incremented by the voltage drop of said biasing element. The method of claim 6, wherein the supply voltage (Vx) satisfies the following condition: Vbz1 > | Vin(-) | + (Vx - Vfd) wherein Vbz1 is a voltage drop across a first Zener diode or lateral NPN structure with a resistive connection between a base region and an emitter region thereof, constituting a first discharging element (Z1), of said pair (Z1, Z2) of discharging elements of said protective structure and being connected to said pin, Vin(-) is the maximum negative design voltage with respect to ground that the voltage on the pin may reach under normal operating conditions and Vfd is a voltage drop across said biasing element. The method of claim 6, wherein the supply voltage (Vx) satisfies the following condition: Vx - Vfd > Vin(+) max wherein Vfd is a voltage drop across said biasing element and Vin(+) max is the maximum positive design voltage with respect to ground that the voltage on the pin may reach under normal operating conditions.

Inventors: CANCLINI ATHOS, MORELLI MARCO, PELLEGRINI FRANCO, CANCLINI, ATHOS, MORELLI, MARCO, PELLEGRINI, FRANCO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1992
Main classification: H01L27
IPC codes: H01L29, H01L21, H01L27, H03K17, H03K19