Improved performance lateral double-diffused MOS transistor and method of fabrication thereof

Abstract: A transistor has a JFET gate region (24) of a first conductivity type formed at the face of a semiconductor layer (10) to laterally and downwardly surround a drift region (26) of a second conductivity type. A thick insulator region (42) is formed on a portion of the drift region at the face. A IGFET body (30) of the first conductivity type is formed at the face to be adjacent the JFET gate region (24). This body (30) spaces a source region (34) of the second conductivity type from the drift region (26). A drain region (60) is formed at the face to be of the second conductivity type and to adjoin the drift region (26), and to be spaced from the IGFET body. A conductive gate (52) extends over the face between the source region (34) and the thick insulator region (42), with a thin gate insulator (50) spacing the gate (52) from the IGFET body (30). The enhanced doping concentration of the JFET gate region (24) with respect to the semiconductor layer (10) allows the dopant concentration of the drift region (26) to likewise be increased, thereby allowing RESURF conditions to be met at the rated voltage and with a lower r ds (on).

Description: TECHNICAL FIELD OF THE INVENTION This invention relates in general to electronic power devices, and more particularly to a device according to the preamble of claim 1 which is known from Patent Abstracts of Japan Vol. 14, 312 and corresponding JP-A-2 102 575 and a method for its fabrication. In IEDM Meeting 1983, pages 95-98, H. Itoh et al., "Extremely High Efficient UHF Power MOSFET For Handy Transmitter", it is disclosed that the doping concentration of a P-substrate is lower than that of a P-Well formed therein so as to reduce the output capacitance. BACKGROUND OF THE INVENTION Lateral double-diffused insulated gate field effect transistors (sometimes known as LDMOS transistors) are the power devices of choice for integration into very large scale integrated circuit (VLSI) logic processes. The on-resistance per unit area (r ds (on)) is the figure of merit for a high voltage power device. Reduced surface field (RESURF) power transistors were introduced by J.A. Appels and H.M.J. Vaes in "High Voltage Thin Layer Devices (Research Devices)", IDEM Tech. Dig. 1979, pp. 238-241. A RESURF LDMOS device will have, given a (P) type semiconductor substrate, an N-type drift region that surrounds an (N+) drain. Relatively thick LOCOS oxide is grown on a portion of the drift region. A relatively deep (P) type implant is used to make the body of the insulated gate field-effect transistor (IGFET), which spaces the drift region from a source region. A (P+) back gate connection is formed within the (P) body implant region. A conductive gate is formed over and insulated from the IGFET body to extend from the source region over the body to the lateral margin of the LOCOS oxide, and preferably extends onto a portion of this thicker oxide. The drift region has a donor dopant concentration N D1 , which is designed to fully deplete with the JFET action from the (P-) substrate gate at the rated voltage. However, the JFET gate dopant concentration is optimized for use of the substrate for other VLSI devices, and is suboptimal for a high voltage power device. A need therefore exists to develop an LDMOS transistor having a low r ds (on) that is yet compatible with VLSI logic processes. SUMMARY OF THE INVENTION According to the present invention the device of the initially defined type further comprises the characterizing features of claim 1. Furthermore, according to this invention there is provided the fabricating method defined in claim 13. Preferred embodiments are listed in the respective dependent claims. An important technical advantage ofthe invention in its provision of the region with dopant concentration that is enhanced over that of the semiconductor layer and over the body. Due to the more highly doped region, the drift region doping can also be increased while still meeting the RESURF conditions. This will lower the drift region resistance, leading to a lower r ds (on) for the device. A further technical advantage of the invention is its compatibility with a VLSI logic process in which other, lower-power devices are made simultaneously in the same chip. Only one additional mask is needed to fabricate this device in addition to the others normally encountered in a VLSI logic process. BRIEF DESCRIPTION OF THE DRAWINGS Further aspects of the invention and their advantages will be discerned by referring to the following detailed description in conjunction with the drawings, in which like parts are identified with like characters and in which: FIGURES 1-5 are highly magnified schematic sectional views of a mirror pair of LDMOS transistors according to the invention, showing successive stages in their fabrication; and FIGURE 6 is a perspective view of a portion of one such LDMOS transistor. DETAILED DESCRIPTION OF THE INVENTION Referring first to FIGURE 1, a (P-) semiconductor substrate is indicated generally at 10. Layer 10 may be an epitaxial layer having a resistance in the range of 25 to 33 ohm-cm. A sacrificial layer 12 of oxide is grown on a face 14 of the semiconductor layer 10. Layer 12 may be approximately 400 Angstroms thick. A layer 16 of photoresist is deposited on the oxide 12 and is developed to define a first implantation area indicated generally at 18. The developed photoresist layer 16 is used as a mask for two implants of different conductivity types. First, a (P) type dopant such as boron is implanted into area 18 at an implantation energy of approximately 100 KeV. The dose may be in the range of 5 x 10 12 atoms/cm 2 to 2 x 10 13 atoms/cm 2 . This creates a (P) region 20. Using the same mask, a second implant is performed, this time using an (N) type dopant having a substantially lower diffusivity than the (P) type dopant employed. In the preferred embodiment, arsenic is used with an implantation energy of approximately 80 KeV and a dose in the range of 5 x 10 12 to 2 x 10 13 atoms/cm 2 . This creates an (N) type region 22 that is shallower than the (P) region 20. The region 20 will have a dopant concentration which is substantially higher than the background dopant concentration of the (P-) semiconductor layer 10. Referring next to FIGURE 2, the photoresist layer 16 is stripped and the implants 20 and 22 are driven in to produce a (P) JFET gate region 24 and an (N) drift region 26. The diffusion drive-in may take place, for example, at 1200°C for approximately 700 minutes. The higher diffusivity of the (P) type dopant causes the dopant to diffuse outwardly at a faster rate than the arsenic atoms used to create the drift region 26. This in turn results in the JFET gate region 24 laterally and downwardly enclosing the (N) drift region 26. Referring next to FIGURE 3, the results of a second set of implantations are shown. A second layer of photoresist (not shown) is deposited and developed to leave open second implantation areas (not shown). A second set of implants is then performed, each using the second developed photoresist mask. A first of these implants is with a high diffusivity, (P) dopant such as boron. The dose should fall within the range of 1.5 x 10 13 atoms/cm 2 to 1.5 x 10 14 atoms/cm 2 , and is preferably about 5 x 10 13 atoms/cm 2 . The implantation energy may be approximately 100 KeV. Second, a relatively low-diffusivity (N) type dopant such as arsenic is implanted. The dose for this species can range from 3 x 10 13 through 2 x 10 14 and is preferably about 1 x 10 14 atoms/cm 2 . A preferred implantation energy is 120 KeV. Next, a drive-in step is performed, such as one at approximately 1100°C for 500 minutes. This will produce insulated gate field effect transistor (IGFET) bodys 30 and 32 as respectively surrounding source regions 34 and 36. The IGFET bodys 30 and 32 intentionally overlap the JFET gate region 24. The top of the IGFET region 30 will serve as the channel region of a field effect transistor to be fabricated between source region 34 and the drift region 26, while the top of the IGFET body 32 likewise serves as the channel region for a field effect transistor to be formed between the drift region 26 and source region 36. After these diffusion drive-ins, a pad oxide layer (not shown) is grown on the surface 14 of the semiconductor layer 10 and a nitride layer is subsequently deposited to together form a hard mask 40. Mask 40 is patterned and etched to leave windows 41 for the subsequent LOCOS thick oxide growth process step to be described immediately below. Turning to FIGURE 4, LOCOS oxide islands 42 and 44 are grown under an oxygen atmosphere to a preferred thickness of about 7600 Angstroms. Each of the LOCOS oxide islands 42 and 44 has "bird's beak" lateral margins 46 which are near the lateral margins 48 of the drift region 26. Next, a gate oxide layer 50 is grown on the surface 14 of the semiconductor layer to a total thickness of approximately 500 Angstroms under an oxygen/steam atmosphere. After this, approximately 4500 Angstroms of polycrystalline silicon (poly) is deposited on the surface of the semiconductor wafer, heavily doped with a dopant such as POCl 3 at a dose of approximately 10 21 atoms/cm 2 , patterned and etched to form conductive poly gates 52 and 54. Poly gate 52 extends from a point near the lateral margin of the source region 34, over the IGFET body 30, across a near area of the drift region 26, and preferably up onto a portion of the LOCOS oxide region 42. Poly gate 54 is disposed similarly in mirror image. The remaining important steps in the fabrication process are illustrated in FIGURE 5. An (N+) source/drain implant is performed as partially self-aligned to lateral edges 56 and 58, respectively, of the poly gates 52 and 54. A developed photoresist layer 59 (see FIGURE 4) is used to define the opposing lateral margins of the implant. This first (N+) source/drain implant is performed, for example, with phosphorus, at an energy of approximately 80 KeV and a dose of approximately 4 x 10 14 cm -2 . This implant enhances the dopant concentration in source regions 34 and 36, and creates the drain region 60, which is self-aligned to LOCOS islands 42 and 44. This first source/drain implant is immediately followed with a second source/drain implant with, for example, arsenic at an implantation energy of approximately 120 KeV and a dose of 5 x 10 15 atoms/cm 2 . This will create particularly heavily doped (N+) regions 62 and 64, and will enhance the dopant concentration of the drain 60. Regions 62 and 34 form a graded-junction source region, as do regions 36 and 64 correspondingly. Next, a (P) implant area is defined using photoresist, and an implant of a (P) type dopant, as for example boron, is performed to create (P+) back gate connection regions 70 and 72. The back gate connection regions may be formed, for example, with boron at an implantation energy of about 25 KeV and a dose of about 2 x 10 15 atoms/cm 2 . These back gate connection regions 70 and 72 are implanted within the respective IGFET bodys 30 and 32, and preferably are adjacent to their respective source regions 62 and 64. This is to make efficacious a common metal contact (not shown) to both the source region 62 and the back gate connection 70, on the one hand, and to the source region 64 and the back gate connection 72 on the other. Further steps are necessary to complete the device. These include the deposition of approximately 4000 Angstroms of undoped oxide and approximately 7000 Angstroms of borophosphosilicate glass (BPSG) (not shown). A contact photoresist layer (not shown) is then deposited and developed. Appropriate contacts are etched to expose at least portions of back gate connection regions 70 and 72, source regions 62 and 64, and drain region 60. The exposed contact areas are silicided by depositing platinum, which will create a thin layer 74 of platinum silicide. Excess platinum is then removed. This is followed by the deposition of a relatively refractory metal such as a titanium-tungsten alloy. The first level of metallization is completed using aluminum, to complete contacts 78, 80 and 82. FIGURE 6 is a highly magnified, schematic perspective view of the left one-half of the pair of devices shown in FIGURE 5. The completed lateral double-diffused "metal/oxide/semiconductor" (LDMOS) power transistor indicated generally at 90 may take any of several forms. The indicated structures may be elongated indefinitely in parallel to direction 92 to create a series of elongate stripes, as current-carrying characteristics require. Also, as is partially shown in conjunction with FIGURES 1-5, the transistor 90 may be replicated about planes 94 and 96, and repeated in this manner as many times as is desired. With multiple sources and drains, drain region 60 would alternate with source region 34. Only one such alternation is shown in conjunction with FIGURES 1-5, which shows a common drain region 60 provided for the source regions 34 and 36. The basic structure of transistor 90 may also have curved components (not shown) such that an essentially circular structure may be fabricated; curved components (not shown) can also close off and join together appropriate ones of the "stripes" at either end of an elongated structure. Silicon has a breakdown voltage characteristic of approximately 30 volts per micron. For a structure designed to have a breakdown voltage (BV) of approximately 90 volts, the length, in a direction perpendicular to direction 92, of the drift region 26 from a lateral margin 98 of the LOCOS oxide 42 to the lateral margin 100 of the drain 60 should be approximately 3.5 microns. This distance may be reduced for devices needing lower breakdown voltages. The distance between points 98 and 100 directly affect the on-resistance, r ds (on). It is desirable to increase the dopant of drift region 26 to lower the on-resistance as much as possible. On the other hand, the breakdown voltage of the part will depend in part on the relationship of the dopant concentration N d of the drift region 26 and the dopant concentration of N a of the JFET gate region 24. As the concentration N a in gate region 24 is increased, the dopant concentration N d in drift region 26 may also be increased while meeting the RESURF conditions. This allows more flexible design, and an optimization of r ds (on) and the breakdown voltage (BV). For a relatively light arsenic dose of region 26, the breakdown voltage is caused by potential crowding near the (N+) drain 60. In this mode, breakdown voltage increases with the arsenic implant dose. With higher arsenic implant doses, a bulk breakdown is observed. This is the preferred mode of operation since the device 90 will then exhibit the highest possible breakdown voltage and the bulk breakdown gives the device 90 more rugged characteristics. However further increases in the arsenic implant dose result in lower breakdown voltage due to the high electric fields under the gate electrode 52. After a point, this lowering in breakdown voltage outweighs the incremental improvement in r ds (on). LDMOS devices 90 suitable for automotive applications were fabricated in a one micron CMOS process. The smallest call scale pitch (between planes 94 and 96) was 10.7 microns. The measured r ds (on) of 1.38 milliohms-cm 2 at a V gs of 15 volts with a breakdown voltage of 80 volts represents the best performance reported to date for a lateral device in this voltage range. In summary, an improved performance LDMOS power transistor has been shown and described. The addition of an enhanced-dopant concentration JFET gate region allows the dopant concentration of the drift region to be increased, thereby reducing r ds (on), important in the characterization of the performance of the device. Nonetheless, this device may be fabricated such that it is compatible with the VLSI logic process at a minimal extra cost and only one additional mask.

Claims: A device having a large breakdown voltage and adaptable to carry a large amount of current, and formed at a face of a semiconductor layer (10) doped to have a first conductivity type, said device comprising: a drift region (26) of a second conductivity type opposite that of said first conductivity type; a thick insulator region (42) formed at said face on said drift region (26); a body (30) of said first conductivity type; a source region (34) formed at said face to be of said second conductivity type and formed to be laterally within said body (30) and spaced from said drift region (26); a drain region (60) formed to be of said second conductivity type and adjoining said drift region (26) and spaced from said body (30); a back gate connection region (70) formed to be of said first conductivity type and adjoining said body (30); and a conductive gate (52) extending over said face between said source region (34) and said thick insulator region (42), a thin gate insulator (50) spacing said gate (52) from said body (30); characterized by a region (24) of said first conductivity type formed in said semiconductor layer (10), said region (24) having a dopant concentration substantially higher than the dopant concentration of said semiconductor layer (10); said body (30) being formed at said face adjacent said region (24), said drift region (26) being formed at said face to be laterally within said region (24), the peak dopant concentration of said region (24) being in the range of 3 to 5 x 10 15 acceptors per cubic centimetre, and the peak dopant concentration of said drift region (26) being in the range of 3 to 5 x 10 16 donors per cubic centimetre. The device of claim 1, wherein said conductive gate (52) further extends over at least a portion of said thick insulator region (42). The device of claim 1 of claim 2, wherein said back gate connection region (70) is formed at said face to adjoin said source region (34), a common conductive contact (78) made to said source region (34) and said back gate connection region (70). The device of any of claims 1 to 3, wherein said drift region (26) has a lateral margin adjacent said body (30), said thin gate insulator terminating (50) at said thick insulator region (42); and a length of said drift region (26) between the termination of said thin gate insulator (50) and said drain region (60) being approximately 3.5 microns. The device of claim 4, wherein said thick insulator region (42) has at least one bird's beak lateral margin near the lateral margin of said drift region (26); said body (30) adjoins said region (24) and said lateral margin of said drift region (26); and said conductive gate (52) further extends over at least a portion of said thick insulator region (42). The device of any of claims 1 to 5, wherein said first conductivity type is (P). The device of any preceding claim, wherein said drift region (26) laterally and downwardly encloses said drain region (60). The device of any preceding claim, wherein said semiconductor layer (10) comprises silicon. The device of any preceding claim, wherein said thick insulator region (42) comprises oxide. The device of any preceding claim in the form of a lateral double-diffused transistor. The device of any preceding claim, wherein said source region (34) has first and second subregions, said first subregion laterally and downwardly enclosing said second subregion and having less dopant concentration of said second conductivity type than said second subregion. A device according to any preceding claim, wherein the body (30) is a IGFET body. A method of fabricating a device at a face of a semiconductor layer (10) having a first conductivity type, comprising the steps of: forming a first mask (16) on the face to define a first implant area (18); using the first mask (16), selectively implanting a dopant of the second conductivity type into the first implant area (18); using the first mask (16), selectively implanting a dopant of the first conductivity type into the first implant area (18), the dopant of the first conductivity type having substantially higher diffusivity in the semiconductor layer (10) than the dopant of the second conductivity type; driving in the dopants to create a drift region (26) of the second conductivity type and a region (24) of the first conductivity type laterally and downwardly surrounding the drift region (26); forming a second mask on the face to define a second implant area; using the second mask, selectively implanting a dopant of the second conductivity type into the second implant area; using the second mask, selectively implanting a dopant of the first conductivity type into the second implant area, the dopant of the first conductivity type having substantially higher diffusivity in the semiconductor layer than the dopant of the second conductivity type; driving in the dopants to create a source region (34) of the second conductivity type and a body (30) of the first conductivity type laterally and downwardly surrounding the source region (34), at least a portion of the body (30) spacing the source region (34) from the drift region (26); forming at least one thick insulator layer (42) on a portion of the drift region (26) near a boundary thereof with the body (30); forming a gate insulator (50) on the body (30) and to extend on the face from the source region (34) at least to the thick insulator layer (42); forming a conductive gate (52) at least on the gate insulator (50); and forming a drain region (60) of the second conductivity type and to be spaced from the body (30) by the drift region (50), the peak dopant concentration of said region (24) being in the range of 3 to 5 x 10 15 acceptors per cubic centimetre, and the peak dopant concentration of said drift region (26) being in the range of 3 to 5 x 10 16 donors per cubic centimetre. The method of claim 13 further comprising the steps of: forming the body (30) to laterally and downwardly surround the source region (34) and to overlap the region (24); and forming a back gate connection region (70) at the face to be of the first conductivity type and to adjoin the body (30). The method of claim 13 and 14 further comprising the steps of: using an edge of the conductive gate (52) to partially self-align the implant, implanting additional dopant of the second conductivity type into the source region (34) in order to create a graded junction.

Inventors: MALHI SATWINDER, NG WAI TUNG, MALHI, SATWINDER, NG, WAI TUNG
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1992
Main classification: H01L29
IPC codes: H01L29