CCD linear image sensor

Abstract: A CCD linear image sensor comprises an array of linearly arranged photosensor cells, and a pair of CCD shift registers arranged at both sides of the array of linearly arranged photosensor cells. Each of the pair of CCD shift registers are coupled in parallel to the linearly arranged photosensor cell array so as to read out signal charges from predetermined photosensor cells of the linearly arranged photosensor cell array and to transfer the read-out signal charge serially in the CCD shifter register. An output end of each of the pair of CCD shift registers is branched into a pair of CCD shift register transfer paths. An output circuit connected to an output terminal of each of the branched CCD shift register transfer paths.

Description: Background of the Invention Field of the invention The present invention relates to a CCD image sensor including CCD shift registers, and more specifically to a structure for outputting at a high speed a transferred charge from a pair of CCD shift registers arranged at both sides of an array of linearly arranged photosensor cells, respectively. Description of related art CCD shift registers are now widely used in an image sensor, a delay line, etc. In particular, the image sensor has been contrived to assume a so called two-line type in which a CCD shift register to be arranged along one array of linearly arranged photosensors are divided into a pair of CCD shift registers arranged in parallel to and at both sides of the linearly arranged photosensor array, in order to elevate the operation speed (for example, U. S. Patent 4,712,137). One typical two-line type of image sensor of the prior art includes first and second arrays of linearly arranged photosensor cells formed in a semiconductor substrate of one conduction type and shielded from each other by a photo shield located between the two arrays of linearly arranged photosensor cells. At an outside of the first array of linearly arranged photosensor cells, a first transfer gate array is provided in parallel to the first array of linearly arranged photosensor cells. At an outside of the first transfer gate array, first and second CCD shift registers are arranged in parallel to each other and to the first transfer gate array, so that odd-numbered cells of the first linearly arranged photosensor array are read out through the first transfer gate array to the first CCD shift registers and even-numbered cells of the first linearly arranged photosensor array are read out through the first transfer gate array to the second CCD shift registers. Each of the first and second CCD shift registers has a serial output connected to an output buffer, so that an output of the two output buffers will be combined at an external device. With this arrangement, signal charges stored in the first linearly arranged photosensor array can be read out at a high speed, since the signal charges stored in the first linearly arranged photosensor array are alternately distributed into the two CCD shift registers and then transferred through the two CCD shift registers. Accordingly, the read-out speed become a double of that obtained when only one CCD shift register is provided to one linearly arranged photosensor array. Similarly, at an outside of the second array of linearly arranged photosensor cells, a second transfer gate array is provided in parallel to the second array of linearly arranged photosensor cells. At an outside of the second transfer gate array, third and fourth CCD shift registers are arranged in parallel to each other and to the second transfer gate array, so that odd-numbered cells of the second linearly arranged photosensor array are read out through the second transfer gate array to the third CCD shift registers and even-numbered cells of the second linearly arranged photosensor array are read out through the second transfer gate array to the fourth CCD shift registers. Each of the third and fourth CCD shift registers has a serial output connected to an output buffer. In the above mentioned arrangement, the first linearly arranged photosensor array and the second linearly arranged photosensor array are staggered by a half bit or a half of photosensor cell. Therefore, if the two linearly arranged photosensor arrays are read out in the order of a first cell of the first linearly arranged photosensor array, a first cell of the second linearly arranged photosensor array, a second cell of the first linearly arranged photosensor array, a second cell of the second linearly arranged photosensor array, etc, and if the outputs of the two linearly arranged photosensor arrays are combined to one output, a considerably high degree of resolution of image can be read out at a high speed. In the above mentioned high-speed high-resolution image sensor, in order to transfer the signal charge to an outside CCD shift register of the first and second CCD shift registers and an outside shift register of the third and fourth CCD shift registers, the signal charges must be passed through an inside CCD shift register of each pair of CCD shift registers. When the signal charges are passed through the inside CCD shift register, a portion of the signal charges remains in the inside CCD shift register, and therefore, the transfer efficiency lowers. In addition, the remaining signal charge is mixed into the signal charge to be transferred in the inside CCD shift register. EP-A-0282150 discloses a CCD linear image sensor according to the pre-characterizing part of claim 1. This device utilizes the so called "narrow channel effect" in order to bend the transfer direction by 90°. On the other hand, US-A-4,811,068 discloses a CCD linear image device wherein signal charges flow from two directions to one single transfer channel or vice versa with no drop in the transfer speed. This device was intended to shorten the gate length in the transfer direction without decreasing the amount of signal charges being handled. Summary of the Invention Accordingly, it is an object of the present invention to provide a CCD linear image sensor which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a CCD linear image sensor which does not have a problem in which a portion of a signal charge to be serially transferred through a first CCD shift register remains in a second CCD shift register, and the signal charge remaining in the second CCD shift register is mixed into the signal charge to be transferred in the second CCD shift register. Another object of the present invention is to provide a CCD linear image sensor which can realize the branching without droping the transfer speed in the branch section. According to the invention these objects are achieved by a CCD linear image sensor according to claim 1. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a partially broken, diagrammatic plan view of a CCD image sensor; Figure 2 is a timing chart of clocks used for driving the CCD image sensor shown in Figure 1; Figure 3 is a detailed plan view of a transfer path branch section of the CCD image sensor shown in Figure 1; Figures 4A and 4B are potential diagrams of two sections in Figure 3; and Figure 5 is a detailed plan view of a transfer path branch section of an embodiment of the CCD image sensor in accordance with the present invention. Description of the Preferred embodiments Referring to Figure 1, there is shown a partially broken, diagrammatic plan view of a CCD image sensor outside the present invention. The shown CCD image sensor includes an array 15 of photosensor cells (PD1, PD2, PD3, PD4, PD5, • • •) formed in a semiconductor substrate of one conduction type. A pair of transfer gates 13 are formed at both sides of the photosensor cell array 15 and coupled in parallel to odd-numbered cells (PD1, PD3, PD5, • • •) and even-numbered cells (PD2, PD4, • • •) of the photosensor cell array 15, respectively. The pair of transfer gates 13 are driven with a transfer clock  TG . A pair of CCD shift registers 12 and 14 are formed at an outside of each of the transfer gates 13 and coupled in parallel to the corresponding transfer gate, so that signal charges accumulated in the odd-numbered cells (PD1, PD3, PD5, • • •) of the photosensor cell array 15 are in parallel transferred to the CCD shift register 12 under control of the transfer gate 13, and that signal charges accumulated in the even-numbered cells (PD2, PD4, • • •) of the photosensor cell array 15 are in parallel transferred to the CCD shift register 14 under control of the transfer gate 13. The CCD shift registers 12 and 14 are driven with two-phase clocks  1 and  2 so as to serially transfer the received signal charges. The CCD shift register 12 is branched at its output end portion into two CCD shifter registers 12a and 12b. Similarly, the CCD shift register 14 is branched at its output end portion into two CCD shifter registers 14a and 14b. These branched CCD shift registers 12a, 12b, 14a and 14b are with two-phase clocks  3 and  4 so as to serially transfer the received signal charges. Output terminals of the branched CCD shift registers 12a, 12b, 14a and 14b are connected to four output buffers 17, respectively, which in turn have their output terminal connected to output terminals V O1 , V O2 , V O3 and V O4 , respectively. With this arrangement, a signal charge of each photosensor cell can be transferred to the corresponding CCD shift register through only one transfer stage. Therefore, the problem of the prior art in which a not-transferred signal charge remains in another CCD shifter register is solved On the other hand, since four output terminals are provided, it is possible to read the signal charges at a high speed. Referring to Figure 3, there is shown a detailed plan view of a transfer path branch section in which one CCD shift register is branched into two CCD shift registers. Also referring to Figures 4A and 4B, there are shown potential diagrams along the lines A1-B1-C1 and A1-B1-D1 in Figure 3. In addition, Figure 2 shows a timing chart of the transfer clocks  1 ,  2 ,  3 , and  4 used for driving the CCD image sensor shown in Figure 1. As shown in Figure 3, each transfer electrode of the two-phase driven CCD shift register is composed of one storage electrode 20a, 21a, 22a, 23a, • • • and one barrier electrode 20b, 21b, 22b, 23b, • • •. The substrate 1 includes a CCD transfer channel 23 formed in a surface of the substrate under the transfer electrodes applied with the clocks  1,  2 ,  3 , and  4 . This CCD transfer channel 23 is formed of an impurity layer of the conduction type opposite to that of the substrate 1. The CCD transfer channel 23 has impurity regions 24 of the same conduction type as that of the substrate 1. The impurity regions 24 are formed under a portion of the barrier electrode which does not overlap the storage electrode. Thus, a buried channel type two-phase driven CCD shift register is constituted. Here, for simplification of description, assume that the substrate I and the impurity regions 24 are of a P-type, and the impurity layer 23 is of an N-type. As shown in the timing chart of Figure 2, only the clock  2 is at a high level at the time t 1 . Therefore, as shown in Figure 4, a signal charge Q 1 exists under the storage electrode 20a applied with the clock  2 . At the time t 2 , since only the clock  1 is brought to the high level and the clock  2 is brought to a low level, the signal charge Q 1 is caused to move under the storage electrode 21 a applied with the clock  1 . At the time t 3 , the clock  3 is brought to a high level, but the signal charge Q 1 under the storage electrode 21a is maintained as it is. At the time t 4 , the clock  1 is brought to a low level and the clock  3 is maintained at a high level, so that the signal charge Q 1 is caused to move under the storage electrode 23a applied with the clock  3 . Here, attention should be paid to an inlet of the CCD shift register 12b located adjacent to the storage electrode 21a. Since the clock  4 applied to the barrier electrode 22b is at a low level, the barrier electrode 22b functions as a barrier as shown in Figure 4B. Therefore, the signal charge Q 1 does not flow into the storage electrode 22a, and flows into only the storage electrode 23a. A signal charge Q 2 transferred in the CCD shift register 12 next to the signal charge Q 1 is caused to move under the storage electrode 21a at the time t 7 . At the time t 7 , the clock  3 is at a low level contrary to the time t 4 , and therefore, the barrier electrode 23b functions as a barrier as shown in Figure 4A. On the other hand, since the clock  4 is at a high level, the barrier electrode 22b functions as a transfer electrode so that the signal charge Q2 is caused to move under the storage electrode 22a. As mentioned above, the signal charges transferred in the CCD shift register 12 are alternately transferred to the CCD shift registers 12a and 12b by applying the clocks as shown in Figure 2. Similarly to the CCD shift register as mentioned above, signal charges transferred in the CCD shift register 14 are alternately transferred to the CCD shift registers 14a and 14b As mentioned above, the signal charge transferred in one CCD shift register can be distributed into two CCD shift registers. Here, a shape of the storage electrode 21a shown in Figure 3 for distributing the signal charge into the two CCD shift registers is important. Now, the shape of the storage electrode 21a will be described. In the potential diagram of Figure 4, when the signal charge flows from under the storage electrode 21a to under the storage electrode 23a at the time t 4 , a signal charge existing at a location "E" in Figure 3 must move a long distance as shown by an arrow F. For this reason, a time necessary for this movement becomes long. Specifically discussing this problem by assuming that the CCD shift register has a channel width of 30µm and the required movement distance is about 30µm, the time constant τ of the movement of the signal charge due to heat diffusion is as follows: τ = 4L 2 π 2 D ≃ 540 (n sec) where L is the movement distance; D is diffusion coefficient of electric charge and D=6.75cm 2 /cm in the case of electrons. The above equation is shown in page 73 of "Fundamental and Application of Charge Transfer Devices CCD, BBD" published from Kindai Kagaku-sha of Japan. With no modification, a maximum driving frequency of the disclosed charge transfer device is limited in this charge distribution section 16 In order to overcome this problem, the storage electrode 21a of this CCD image sensor is brought into the shape near to a triangle so that a channel direction length L E of the location "E" of the storage electrode 21a is shorter than a channel direction length LB of a portion of the storage electrode 21a near to a center line A1-B1 of the CCD shift register. With this difference in the channel direction length of the storage electrode 21a, a potential difference is created by a so called narrow channel effect. Specifically discussing by assuming L E = 3µm and L B = 6µm, the potential difference of about 1V is introduced between the location "E" and the location having the channel direction length L B . By this potential difference, an electric field is generated from the location "E" toward the barrier electrode 23b. A time τ E of the electric charge due to this electric field becomes as follows, assuming that the mobility µ of electron is 1000cm 2 /V-sec, the movement distance L is 30µm and the potential difference ΔV is 1V. τ E = L µ • ν L ≃ 9(n·sec) Namely, the time τ E is remarkably smaller than the constant τ of movement due to only heat diffusion. Thus, by causing the storage electrode 21a to have the shape having a channel direction length increasing from opposite side edges of the channel toward a center portion of the channel, the drop of the transfer speed in the signal charge distribution section 16 can be prevented. Referring to Figure 5, there is shown the signal charge distribution section of an embodiment of the CCD linear image sensor in accordance with the present invention. The shape of a storage electrode 31a for distributing a signal charge transferred in a CCD shift register composed of storage electrodes 30a and barrier electrodes 30b, into a CCD shift register composed of storage electrodes 33a and barrier electrodes 33b and a CCD shift register composed of storage electrodes 32a and barrier electrodes 32b, is further advanced in comparison with the branch section shown in Figure 3. In order to increase the speed of the charge transfer to the storage electrodes 33a and 32a, the channel direction length of the storage electrode 31a is further shortened in comparison with the branch section shown in Figure 3. In addition, the channel width of portion of the storage electrode 31a adjacent to the barrier electrodes 33b and 32b is widened so that the signal charge can be smoothly moved. An electric charge existing at a location "G" in Figure 5 is most apart from the barrier electrode 33b. A channel width under a portion around the location "G" is shorter than the other portion of the channel, so that an electric field is generated from the location "G" toward a center of the storage electrode 31a in order to increase the transfer speed. The invention has thus been shown and described with reference to the specific embodiment. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claim.

Claims: A CCD linear image sensor comprising an array (15) of linearly arranged photosensor cells (PD1, PD2, PD3, PD4, PD5), a first and a second CCD shift register (12 and 14) arranged at a first and a second side of said array of linearly arranged photosensor cells, respectively, each of said CCD shift registers being coupled in parallel to said array of linearly arranged photosensor cells so as to read out signal charges from predetermined photosensor cells of said array of linearly arranged photosensor cells and to transfer the read out signal charges serially in the CCD shift register, respective branch means (16) coupled to an output end of each of said CCD shift registers so as to branch said output end of the respective CCD shift register into a pair of branched CCD shift register paths (12a and 12b or 14a and 14b), and output circuits (17), respectively, connected to each output terminal of each of said branched CCD shift register paths, each of said pair of branched CCD shift register paths (12a and 12b, 14a and 14b) being so driven that signal charges transferred in the corresponding CCD shift register are alternately transferred either through one branched CCD shift register path (12a or 12b; 14a or 14b) or through the other branched CCD shift register path (12a or 12b; 14a or 14b), characterized in that each branch means has a storage electrode (31a) located at a location where said output end of said respective CCD shift register (12 or 14) is branched into said corresponding pair of branched CCD shift register paths (12a and 12b or 14a and 14b), and said storage electrode (31a) of said branch means has its width which is greatest at its beginning and continually decreases toward its end, and a channel under said storage electrode (31a) has its width which is reduced under a barrier electrode (31b) at said output end of said respective CCD shift register (12 or 14) and has a minimum width before said beginning of said storage electrode (31a) and which further increases whereas the width of said storage electrode (31a) decreases, and then the channel under said storage electrode (31a) merges into the respective channels of said corresponding pair of branched shift register paths (12a and 12b or 14a and 14b), so that an electric field is generated from said respective CCD shift register (12 or 14) towards said corresponding pair of branched CCD shift register paths (12a and 12b or 14a and 14b).

Inventors: MIWADA KAZUO, MIWADA, KAZUO
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1992
Main classification: H01L27
IPC codes: H01L29, H04N5, H01L27, H04N1, H01L21