Method of manufacturing semiconductor device

Abstract: According to this invention, an isolation trench is formed in a semiconductor substrate. A first insulating film is formed on a surface of the semiconductor substrate and an inner surface of the trench. A silicon oxide film containing phosphorus and boron is buried in the trench in which the first insulating film is formed. A second insulating film pattern having a width larger than that of the trench is formed on the trench and a peripheral portion of the trench. The second insulating film pattern prevents out-diffusion phosphorus and boron in the silicon oxide film. The first insulating film which is not covered with the second insulating film pattern is removed to form a first insulating film pattern. The surface of the semiconductor substrate which is not covered with the first and second insulating film patterns is thermally oxidized.

Description: Specification Background of the Invention The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor substrate in which a silicon oxide film containing phosphorus and boron is buried in a trench used for isolating elements from each other formed on the same substrate. In a semiconductor integrated circuit (to be referred to as an LSI hereinafter), a technique for electrically isolating elements from each other formed on the same substrate is necessary. A typical isolation technique is shown in Figs. 10 to 12. Fig. 10 shows a p-n isolating method using a p-n junction obtained by forming an n-type semiconductor element region 511a and a p-type semiconductor region 512 on a p-type semiconductor region 516 of a semiconductor substrate 501a. Fig. 11 shows a LOCOS isolating method for a thick SiO 2 film 513 for isolating an n-type semiconductor region 511b on the p-type semiconductor region 516 of a semiconductor substrate 501b. Fig. 12 shows a trench isolating method for forming a deep trench 512, reaching the p-type semiconductor region 516, for isolating an n-type semiconductor element region 511c on the p-type semiconductor region 516 of a semiconductor substrate 501c. In recent years, in order to obtain the high integration density and high-speed operation of an LSI, the trench isolating method having the smallest area for isolation has been popularly used. In the trench isolation method, as shown in Fig. 12, an insulating film 514 is formed on the inner surface of a trench 512, and a polysilicon film 515 having a thermal expansion coefficient close to that of a silicon substrate is generally buried in the trench 512 in which the insulating film 514 is formed. In reply to a demand of a further high-speed operation of an LSI, a method of decreasing a capacitance between elements by replacing a material buried in the trench 512 with an insulator having a low dielectric constant has been examined. First, as an insulator to be buried in the trench 512, a silicon dioxide film having a low dielectric constant and good step coverage and formed by low-pressure CVD (Chemical Vapor Deposition) is considered. However, the shape of the film, like an SiO 2 film 8 shown in Fig. 13, is affected by the shape of a trench 2, thereby forming a depression 7 in the SiO 2 film 8 at the upper portion of the trench 2. Therefore, when the SiO 2 film 8 is etched by a depth corresponding to the thickness thereof to remove a part of the SiO 2 film 8 out of the trench 2, the SiO 2 film 8 left in the trench 2 is not suitable for the material to be buried in the trench 2 because the SiO 2 film 8 has a deep depression 7a in the trench 2 like an SiO 2 film 8a shown in Fig. 14. For this reason, the concept of reflowing (remelting) is used. A silicon oxide film (borophosphosilicate glass; BPSG) is formed in the trench 2 by low-pressure CVD. This silicon oxide film contains boron and phosphorus, has a low dielectric constant, good step coverage, a reflow property better than that of an SiO 2 film doped with no impurity, and a small stress, and does not easily generate stress in the substrate. In this case, as will be described later, as shown in Fig. 16, a BPSG film 5 has a depression 7 at the upper portion of the trench 2 immediately after the BPSG film 5 is formed. However, when the BPSG film 5 is reflowed at a temperature of 900°C to 1,000°C, the surface of the BPSG film 5 is smoothed as shown in Fig. 17. Therefore, when the BPSG film 5 is etched by a depth corresponding to the thickness thereof at the flat portion, a BPSG film 5b having a flat upper portion which is suitable for the material to be buried in the trench 2 is formed in the trench 2. A conventional method of manufacturing a semiconductor device using a BPSG-buried trench will be described below with reference to the accompanying drawings. Figs. 15 to 21 are sectional views showing the main steps in manufacturing a semiconductor device by a conventional manufacturing method. As shown in Fig. 15, a trench 2 having a width of about 0.6 to 1.0 µm and a depth of 4 to 6 µm is formed in a semiconductor device 1, and an SiO 2 film 3 and an Si 3 N 4 film 4 are sequentially formed on the surface of the semiconductor substrate 1 and the inner surface of the trench 2. The Si 3 N 4 film 4 serves as a stopper for preventing phosphorus and boron in a BPSG film buried in the trench 2 (to be described later) from being diffused in the semiconductor substrate 1 when a barrier film and the BPSG film are etched. The thickness of the Si 3 N 4 film 4 is about 50 to 150 nm (nanometer). Furthermore, the SiO 2 film 3 is used for preventing a stress generated when the Si 3 N 4 film 4 is brought into direct contact with the semiconductor substrate 1 and has a thickness of about 30 to 200 nm. As shown in Fig. 16, a BPSG film 5 having a phosphorus concentration of 2 to 6 mol% and a boron concentration of 8 to 12 mol% is formed on the Si 3 N 4 film 4 by low-pressure CVD to sufficiently bury the trench 2 and to have a thickness t1 which is 1/2 or more a width t2 of the trench 2 (t1 ≥ t2/2). At this time, the BPSG film 5 has a depression 7 at the upper portion of the trench 2. The BPSG film 5 is reflowed by annealing at a temperature of 900°C to 1,000°C to smooth the surface of the BPSG film 5, thereby obtaining a BPSG film 5a shown in Fig. 17. The BPSG film 5a is etched using an etching liquid containing hydrofluoric acid by a depth corresponding to the thickness of the BPSG film 5a at a flat portion thereof to leave a BPSG film 5b in the trench 2 as shown in Fig. 18, so that the upper end of the BPSG film 5b has the same level as that of the surface of the semiconductor substrate 1. An unnecessary part of the Si 3 N 4 film 4 on the surface of the semiconductor substrate 1 is etched using phosphoric acid heated at a temperature of 140 to 160°C to expose the SiO 2 film on the surface of the semiconductor substrate 1, and an Si 3 N 4 film 4a is left in the trench 2 as shown in Fig. 19. At this time, since the SiO 2 film 3 exposed on the semiconductor substrate 1 is exposed to the phosphoric acid used for etching the Si 3 N 4 film 4, the SiO 2 film 3 has poor thickness controllability and poor film quality, and the SiO 2 film 3 cannot be used as a substrate protecting film for ion implantation or a gate oxide film of a MOS transistor. Therefore, the SiO 2 film 3 must be reformed. As shown in Fig. 20, the SiO 2 film 3a is left in the trench 2, and the SiO 2 film 3 on the surface of the semiconductor substrate 1 is partially etched by an etching liquid containing hydrofluoric acid. As shown in Fig. 21, the exposed surface of the semiconductor substrate 1 is thermally oxidized to form an SiO 2 film 30. The SiO 2 film 30 has a thickness required in the next step. Subsequently, elements are formed on the semiconductor substrate 1 by a normal process. As described above, the BPSG film 5b having a dielectric constant lower than that of polysilicon is buried in the trench 2 for isolation, thereby manufacturing an LSI having a decreased capacitance between the elements. In the conventional manufacturing method, since annealing at a temperature of 850°C to 1,100°C is performed while the surface of the semiconductor substrate and the BPSG film in the trench are exposed as shown in Fig. 14, phosphorus and boron in the BPSG film are diffused out as indicated by arrows in Figs. 22 and 23, thereby forming an impurity diffusion region 9 in the semiconductor substrate 1 around the trench. Even when annealing (thermal oxidation) is performed at a temperature of 1,000°C for 30 minutes, the impurity diffusion region 9 has a width of 0.5 µm or more on each side of the trench. Even when micropatterning is performed to obtain a trench having a width of 0.8 µm, when the SiO 2 film formed on the inner wall of the trench extends to the semiconductor substrate 1 to have a width of 0.1 µm, and an impurity diffusion region formed by diffusion from the BPSG 5b has a width of 0.5 µm on each side of the trench. In this case, an isolation region has the width of 2.0 µm as shown in Fig. 9A, and the high integration density of an large scale integration cannot be easily obtained. L.K. White et al, in a paper referenced "Extended Abstracts Vol. 93/2 1990 pages 406 to 407, addresses this problem of undesired contamination of the semiconductor substrate by boron and phosphorous. The method that is taught involves sequential deposition of a silicon oxide cap and a BPSG layer on both the buried BPSG layer and substrate upper surface, followed by etchback of both these layers. However, a result of oxidising the substrate surface is that crystal defects are induced in the substrate. European patent publication EP-A-0482591 relates to isolation regions between elements and describes a semiconductor having an element isolation region including a LOCOS type field oxide film formed in a surface of a silicon substrate and a U-trench isolation region provided in the silicon substrate. JP 2015650 describes a method of manufacturing a semiconductor device in which a trench is lined with a silicon nitride film prior to filling the trench with a BPSG film. The BPSG film is covered with a second silicon nitride film. Summary of the Invention It is an object of the present invention to provide a method of manufacturing a semiconductor device for preventing formation of an unnecessary impurity diffusion region in a semiconductor substrate around an isolation trench. It is another object of the present invention to provide a method of manufacturing a semiconductor device in which an area required for isolation is decreased to obtain a high integration density of a semiconductor integrated circuit. It is still another object of the present invention to provide a method of manufacturing a semiconductor device capable of obtaining a high-speed operation of a semiconductor integrated circuit. According to the present invention, there is provided a method according to Claim 1. Brief Description of the Drawings Figures 1 to 4 are sectional views showing the main steps in manufacturing a semiconductor device; Figures 5 to 8 are sectional views showing the main steps in manufacturing a semiconductor device according to an embodiment of the present invention; Figures 9A and 9B are views showing comparison between a conventional technique and the present invention; Figures 10 to 12 are views showing a typical isolation technique; Figures 13 to 14 are sectional views showing a semiconductor device in which a silicon oxide film free from phosphorus is buried in a trench; Figs. 15 to 21 are sectional views showing the main steps in manufacturing a semiconductor device according to a conventional method of manufacturing a semiconductor device; and Figs. 22 and 23 are views showing problems in the conventional method of manufacturing a semiconductor device. Description of the Preferred Embodiment The present invention will be described below with reference to the accompanying drawings. Figs. 1 to 4 show the main steps in manufacturing a semiconductor device.The step in Fig. 1 corresponding to Fig. 19 is obtained according to the same method as that of the prior art. In Fig. 1, an SiO 2 film 103 and an Si 3 N 4 film 104 are sequentially formed on the surface of the semiconductor substrate 101 having a trench 102 and on the inner surface of the trench 102, and a BPSG film 105 is buried in the trench 102. As shown in Fig. 2, An Si 3 N 4 film 106 having a thickness of 25 nm or more is formed by low-pressure CVD on the upper surface of the semiconductor substrate 101, i.e., the entire surface of the SiO 2 film 103 and the BPSG film 105. The Si 3 N 4 film 106 is used to prevent phosphorus and boron atoms in the BPSG film 105 from diffusion out when the surface of the semiconductor substrate is thermally oxidized to be described later. As shown in Fig. 3, the Si 3 N 4 film 106 is partially etched by a normal photolithographic technique to leave an Si 3 N 4 film 106a having a width larger than that of the trench 102 on the upper portion of the trench 102. In addition, the SiO 2 film 103 is partially etched to leave an SiO 2 film 103a having a width almost equal to that of the Si 3 N 4 film 106a. The Si 3 N 4 film 106 is etched using a photoresist as a mask by dry etching such as RIE (Reactive Ion Etching) to obtain high dimensional accuracy. The SiO 2 film 103 is etched by wet etching using an etching liquid containing hydrofluoric acid to prevent the semiconductor substrate 101 from damage. In this method, in consideration of overetching and side etching of the Si 3 N 4 film 104 and the SiO 2 film 103 and positioning accuracy of an exposure device used in a lithographic technique, the width of the Si 3 N 4 film 106a is larger than that of the trench 102 by 0.1 µm to 0.3 µm on each side. The exposed surface of the semiconductor substrate 101 is thermally oxidized to form an SiO 2 film 107 as shown in Fig. 4. The SiO 2 film 107 has a thickness required by the subsequent processes. Subsequently, elements are formed on the semiconductor substrate 101 by normal processes. As described above, since the BPSG film 105 is covered with the Si 3 N 4 film 106a when the semiconductor substrate is thermally oxidized, phosphorus or boron ion atoms in the BPSG film 105 are not diffused out, and an LSI can be manufactured without forming an impurity diffusion region around the trench. An embodiment of the present invention will be described below with reference to the accompanying drawings. Figs. 5 to 8 show the main steps in manufacturing a semiconductor device according to the embodiment of the present invention. The step in Fig. 5 corresponding to Fig. 18 is obtained according to the same method as that of the prior art. In Fig. 5, an SiO 2 film 203 and an Si 3 N 4 film 204 are sequentially formed on a semiconductor substrate 201 and in a trench 202 formed in the semiconductor substrate 201, and a BPSG film 205 is buried in the trench 102. Unlike the previously described method, as shown in Fig. 6, the Si 3 N 4 film 204 is not removed, and an Si 3 N 4 film 206 is formed on the Si 3 N 4 film 204 and the BPSG film 205. The Si 3 N 4 film 206 has a thickness of 25 nm or more as the Si 3 N 4 film in the first embodiment (Fig. 3). The Si 3 N 4 film 206 is etched by a normal photolithographic technique to leave the Si 3 N 4 film 206 having a width larger than that of the trench 202, and the Si 3 N 4 film 204 and the SiO 2 film 203 are etched to form Si 3 N 4 films 206a and 204a and an SiO 2 film 203a. The exposed surface of the semiconductor substrate 201 is thermally oxidized to form an SiO 2 film 207 as shown in Fig. 8. The SiO 2 film 207 has a thickness required by the subsequent processes. Subsequently, elements are formed on the semiconductor substrate 201 by normal processes. According to this embodiment, unlike the previously mentioned method, the step of etching the Si 3 N 4 film 204 in Figs. 18 and 19 can be omitted, and the depression in the trench caused by overetching the Si 3 N 4 film 204 can be prevented. As described above, according to the manufacturing method of the present invention, in a semiconductor device in which a BPSG film having a low dielectric constant and contributing to the high-speed operation of an LSI is buried in a trench used for isolation, when the surface of a semiconductor substrate is to be thermally oxidized, the BPSG film in the trench is covered with the Si 3 N 4 film, and diffusion of phosphorus and boron atoms from the BPSG film to form an impurity diffusion region around the trench can be prevented. Therefore, assume that the trench used for isolation has a width of 0.8 µm, that an oxide film formed in the trench extends to the semiconductor substrate side to have a width of 0.1 µm on each side of the trench, and that the width of a diffusion region formed by diffusion from the BPSG film in a conventional method is set to be 0.5 µm on each side of the trench. In this case, as shown in Fig. 9A, an isolation region R requires a width of 2 µm in the conventional method. According to the present invention, however, as shown in Fig. 9B, when the width of the Si 3 N 4 film covering the BPSG film is set to be larger than that of the trench by 0.2 µm on each side of the trench, the width of the isolation region R can be advantageously decreased by 30%, i.e., 1.4 µm.

Claims: A method of manufacturing a semiconductor device, comprising the steps of: forming an isolation trench (202) in a semiconductor substrate (201) ; forming a first insulating film (203) on a surface of said semiconductor substrate and an inner surface of said trench; forming a second insulating film on said first insulating film; burying a silicon oxide film (205) containing phosphorus and boron in said trench in which said first and second insulating films are formed; forming on said trench and said second insulating film surrounding said trench a third insulating film formed of the same material as said second insulating film (206a); etching said second and third insulating films to have a width larger than that of said trench, said films extending from said trench over an adjacent portion of the substrate surrounding said trench, the second and third insulating films preventing out-diffusion of phosphorus and boron from said silicon oxide film; removing said first insulating film which is not covered with said etched second and third insulating films to form a first insulating film pattern (203a); and thermally oxidising the surface of said semiconductor substrate which is not covered with said first to third insulating films. A method according to Claim 1, wherein said second and third insulating films consist of silicon nitride.

Inventors: NISHIO NOBUYA, NISHIO, NOBUYA, Nishio, Nobuya, c/o NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H01L21
IPC codes: H01L21