Amplifying circuit

Abstract: At the time of driving no load, a non-inverted input of a differential amplifier is switched from an output terminal to a reference voltage source. Thus, a constant current source circuit consisting of the reference voltage source, the differential amplifier, and an output stage transistor is provided to control an idling current flowing through output stage transistors to an appropriate level.

Description: This invention relates to an amplifying circuit, and more particularly to an amplifying circuit for driving a load of a low impedance. One type of a conventional amplifying circuit for driving a low impedance load is described in a report titled "MOS Operational Amplifier Design - A Tutorial Overview" of "IEEE Journal of Solid-State Circuit, Vol. SC-17, No.6, December 1982". The conventional amplifying circuit comprises two differential amplifiers each amplifying a difference between one input signal and a signal fed-back from an output terminal, and two output stage transistors having sources connected to a power supply and ground, respectively, to be driven by the differential amplifiers. The conventional amplifying circuit has an advantage in that a range of an output voltage can be wide as compared to an amplifying circuit using a source follower circuit at an output stage. However, the conventional amplifying circuit has a disadvantage in that an idling current flowing through the output stage transistors is largely fluctuated, when the two differential amplifiers are supplied with an input offset voltage. For the purpose of overcoming this disadvantage, the other type of a conventional amplifying circuit is proposed as described in a report titled "A 1.544 Mb/s CMOS Line Driver for 22.8 Ohm Load" of "IEEE Journal of Solid-State Circuits, Vol. SC-25, No.3, June, 1990". In this conventional amplifying circuit, an idling current flowing through output stage transistors is controlled to be increased or decreased by two negative feed-back amplifiers which are connected to outputs of two differential amplifiers, respectively. However, this conventional amplifying circuit has disadvantages in that it is difficult to control the idling current with a predetermined precision, because the idling current is determined at the time of no load by amplification factors of the differential and negative feedback amplifiers and an input offset voltage of the differential amplifier, and in that the design is difficult on some points as described later. Features of arrangements illustrating the invention and to be described below include an amplifying circuit in which the fluctuation of an idling current flowing through output stage transistors is minimised, the idling current is well controlled at the time of no load in order to decrease current consumption and to avoid the output transistors being cut-off, and which can be designed with comparative ease. In one arrangement to be described below, an amplifying circuit includes:- a first differential amplifier having its inverting input connected to an input terminal and a non-inverting input connected to an output terminal; a first output stage transistor having its gate connected to an output of the first differential amplifier, its source connected to a power supply, and its drain connected to the output terminal; a second differential amplifier having its inverting input connected to the input terminal and its non-inverting input connected to the output terminal; a second output stage transistor having its gate connected to an output of the differential amplifier, its source connected to ground, and its drain connected to the output terminal; first switching means for switching the non-inverting input of the first differential amplifier from the output terminal to a reference voltage source; and second switching means for switching the inverting input of the first differential amplifier from the input terminal to the output of the first differential amplifier. The following description and drawings disclose previously proposed arrangements, as well as, by means of examples, the invention which is characterised in the appended claims, whose terms determine the extent of the protection conferred hereby. In the drawings:- Fig. 1 is a circuit diagram of a first conventional amplifying circuit; Fig. 2 is a circuit diagram of a second conventional amplifying circuit; Fig. 3 is a circuit diagram explaining principle of an amplifying circuit of a first preferred embodiment according to the invention; Figs. 4A and 4B are circuit diagrams of an amplifying circuit of the first preferred embodiment; Fig. 5 is a circuit diagram explaining principle of an amplifying circuit of a second preferred embodiment according to the invention; and Fig. 6 is a circuit diagram of an amplifying circuit of the second preferred embodiment. Before explaining an amplifying circuit of a first preferred embodiment according to the invention, the aforementioned first and second conventional amplifying circuit will be explained in Figs. 1 and 2. Fig. 1 shows the first conventional amplifying circuit which comprises differential amplifiers A1 and A2, and output stage transistors Q1 and Q2. In this amplifying circuit, inverted terminals of the amplifying circuits A1 and A2 are connected to an input terminal IN, non-inverted terminals thereof are connected to an output terminals OUT, and outputs thereof are connected to gates of the transistors Q1 and Q2, respectively. Drains of the transistors Q1 and Q2 are connected to the output terminal which is a common point connected to the non-inverted terminals of the differential amplifiers A1 and A2, a source of the transistor Q1 is connected to a power supply, and a source of the transistor Q2 is connected to ground. In this amplifying circuit, the output stage transistors Q1 and Q2 are driven by the differential amplifiers A1 and A2. As described before, a range of an output voltage obtained at the output terminal OUT can be wide as compared to an amplifying circuit utilizing a source follower circuit for an output stage. For this reason, the first conventional amplifying circuit is widely used. In the first conventional amplifying circuit, however, an idling current flowing through the output stage transistors Q1 and Q2 is largely fluctuated, when an input offset voltage is applied to the differential amplifiers A1 and A2. If it is assumed that a positive input offset voltage is applied to the differential amplifier A1, and a negative input offset voltage is applied to the differential amplifier A2, respectively, under the condition that a polarity of the input offset voltage is determined on the basis of the non-inverted input, an output signal of the differential amplifier A1 swings in the direction of the ground potential, while an output signal of the differential amplifier A2 swings in the direction of the power supply voltage. As a result, the idling current is largely increased to increase the consumption of current. On the other hand, if it is assumed that a negative input offset voltage is applied to the differential amplifier A1, and a positive input offset voltage is applied to the differential amplifier A2, the direction of the swing is reverse in the output signals of the differential amplifiers A1 and A2 to that of the swing as explained in the former assumption of the input offset voltage, so that the idling current is largely decreased, thereby cutting the output stage transistors Q1 and Q2 off in an extreme case. In order to overcome this disadvantage, the aforementioned second conventional amplifying circuit is proposed as shown in Fig. 2. Fig. 2 shows circuit portions corresponding to the differential amplifier A1 and the transistor Q1 of Fig. 1, respectively. In this amplifying circuit, a differential amplifier A11 is composed of transistors Q8 to Q15 including a current source IB, and a differential amplifier A12 is composed of transistors Q3 to Q6. An output of the differential amplifier A11 is connected to an output stage transistor Q1 which is connected to an output terminal OUT, and to the transistor Q3 of the differential amplifier A12. Additionally, a transistor Q7 is provided to be connected at a gate to a node of drains of the transistors Q5 and Q6 by a switch SW1. In the second conventional amplifying circuit, a difference is made in the differential amplifier A12 between a gate to source voltage of the output stage transistors Q1 and a gate to source voltage of the transistor Q12 through which a current equal to a current flowing through the transistor Q8 flows. As a result of this comparison, an output signal X is applied through the switch SW1 to the transistor Q7, in which the output signal X is amplified to be negatively fed back to a gate of the transistor Q3. That is, an idling current which is caused to flow through the output stage transistor Q1 by an input offset voltage applied to the differential amplifier A11 is compensated by the negative feed-back amplifier A12 composed of the transistors Q3 to Q7. At the time of no load (no signal), the switch SW1 is turned on, so that the idling current flowing through the transistor Q1 is controlled. On the other hand, the switch SW1 is turned off at the time of driving a load, so that no control of the idling current is carried out. At the load driving state, a current supplied to a load flows through the output stage transistor Q1 to generate a large gate to source voltage of this transistor Q1. In such a case, if the switch SW1 is turned on, the negative feed-back amplifier A12 tends to stop the operation of the output stage transistor Q1 for driving a load. This is reason why the switch SW1 is turned off at the time of driving a load. In the second conventional amplifying circuit, however, the idling current is determined at the time of no load by amplification factors of the differential amplifier A11 and the negative feed-back amplifier A12 and an input offset voltage of the differential amplifier A11, so that it is difficult to control the idling current with a predetermined precision due to the presence of plural control parameters. In addition, two negative feed-back paths consisting of a first feed-back path from the output stage transistor Q1 to the differential amplifier A11 and a second feedback path locally established from the transistor Q7 to the output stage transistor Q1 are provided therein, so that it is difficult to deal with design requirements such as the distribution of amplification factors of the amplifiers A11 and A12, the compensation of phases, the systematic generation of an input offset voltage, etc. Next, an amplifying circuit of a first preferred embodiment according to the invention will be explained in Figs. 3 and 4. Fig. 3 shows the principle of the amplifying circuit, wherein like parts are indicated by like reference numerals as used in Fig. 1. In this amplifying circuit, a switch SW1 having terminals a, b and c, and d, e and f is provided on the input side of the differential amplifier A1, wherein the terminals a and d are connected to the non-inverted input and the inverted input of the differential amplifier A1, respectively, the terminal b is connected to the output terminal OUT, the terminal c is connected to a reference voltage VR, the terminal e is connected to the input terminal IN, and the terminal f is connected to an output of the differential amplifier A1. At the time of driving a load, the terminals a and d are turned on the terminals b and d, respectively, so that operation is carried out in the same manner as in Fig. 1. At the time of no load, the terminals a and b are turned on the terminals c and f, respectively. Consequently, a feed-back circuit including the differential amplifier A1 becomes a voltage follower having an input of the reference voltage VR, so that the output stage transistor Q1 is applied at the gate with the reference voltage VR to function as a constant current source. For this structure, an idling current flowing through the output stage transistors Q1 and Q2 is arbitrarily controlled in its value with a predetermined precision by a value of the reference voltage VR. Fig. 4A shows a portion of the amplifying circuit of Fig. 3 excluding the differential amplifier A2 and the output stage transistor Q2, wherein the switch SW1 is shown as including switches SW1-1 and SW1-2 linked to each other to be turned in the ON and OFF manner. In operation of driving a load, the switch SW1-1 is turned off, and the switch SW1-2 is turned on, so that a differential amplifier composed of transistors Q5 to Q16 and the output stage transistor Q1 only operate. In this state, the output stage transistor Q1 functions as a power transistor for driving a load. In operation of driving no load, the switch 1-1 is turned on, and the switch 1-2 is turned off. In this no load mode, a circuit composed of transistors Q1 to Q4 and Q7 to Q17 operate, wherein a voltage follower having the output stage transistor Q1 applied at the gate with the reference voltage VR is formed. In this circuit, the output stage transistor Q1 functions as a constant current source. Here, if it is assumed that a ratio of sizes between the transistors Q1 and Q17 is "n", a current of "n x IR" flows through the output stage transistor Q1, where "IR" is a reference current, as shown in Fig. 4A. At this time, a voltage of the output terminal OUT is equal to a voltage applied to the input terminal IN in cooperation with the differential amplifier A2 and the output stage transistor Q2 as explained in Fig. 3. In the circuit of Fig. 4A, a current flowing through the output stage transistors Q1 and Q2 (Fig. 3) is precisely controlled at the time of no load, so that the increase of a current consumption and the cut-off of the output stage transistors are avoided. Further, there is no existence of a local feed-back circuit, although it is formed in the aforementioned conventional amplifying circuit. Accordingly, amplification factors and phase compensation are easily determined in designing an amplifying circuit of the invention, because the circuit design can be carried out separately between the ON states of the switches SW1-1 and SW1-2. The transistor Q17, the reference current IR, and the reference voltage VR of Fig. 4A may be explained as shown in Fig. 4B. Fig. 5 shows an amplifying circuit of a second preferred embodiment according to the invention, wherein the output stage transistor Q is N type, and the output stage transistor Q2 is P type, although the output stage transistors Q1 and Q2 are P type and N type, respectively, in the first preferred embodiment. Fig. 6 shows a portion of the amplifying circuit of the second preferred embodiment excluding the differential amplifier A2 and the output stage transistor Q2 as shown in Fig. 5, wherein like parts are indicated by like reference numerals as used in Fig. 4A. Although the invention has been illustrated with reference to a specific embodiment, as an example, it will be understood that variations and modifications thereof, as well as other embodiments, may be made within the scope of the appended claims.

Claims: An amplifying circuit, including a first differential amplifier (A1) having its inverting input (d) connected to an input terminal (IN) and its non-inverting input (a) ccnnected to an output terminal (OUT), a first output stage transistor (Q1) having its gate connected to the output of the first differential amplifier (A1), its source connected to a power supply, and its drain connected to the output terminal (OUT), a second differential amplifier (A2) having its inverting input connected to the input terminal (IN) and its non-inverting input connected to the output terminal (OUT), a second output stage transistor (Q2) having its gate connected to the output of the second differential amplifier (A2), its source connected to ground, and its drain connected to the output terminal (OUT), characterised in that there are provided first switching means (b,c) for switching the non-inverting input of one of the first and second differential amplifiers (A1, A2) from the output terminal (OUT) to a reference voltage source (VR), and second switching means (e,f) for switching the inverting input of the one of the first and second differential amplifiers (A1,A2) from the input terminal (IN) to the output of the one of the first and second differential amplifiers (A1,A2). An amplifying circuit as claimed in claim 1, wherein the first and second switching means (b,c) (e,f) switch the connections of the non-inverting and inverting inputs of the first differential amplifier (A1) to the reference voltage source (VR) and the output of the first differential amplifier (A1), respectively, at a time when the circuit is not driving a load. An amplifying circuit, as claimed in either claim 1 or claim 2, wherein the first output stage transistor (Q1) is of P channel type, and the second output stage transistor (Q2) is of N channel type.

Inventors: FUJII TAKASHI, FUJII, TAKASHI, FUJII, TAKASHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1992
Main classification: H03F1
IPC codes: H03F3, H03F1