FLASH MEMORY IMPROVED IN ERASING CHARACTERISTIC, AND CIRCUIT THEREFOR

Abstract: A flash memory improved in its erasing operation by shortening its erasing time, wherein, when data is written prior to erasing, by selecting a plurality of lines of at least either of word lines and bit lines simultaneously, data is written into a plurality of transistors in concurrence.

Description: The present invention relates to a so-called flash memory or a nonvolatile semiconductor memory from which existent information can be electrically erased concurrently or block by block. In particular, this invention is concerned with improvements in erasing a flash memory and improvements in the associated circuitry. In recent years, a variety of semiconductor memories such as an electrically erasable programmable read only memory (EEPROM), which can be rewritten by electrically erasing data stored therein, have been developed in the field of nonvolatile memories. The semiconductor memories are nonvolatile memories which are made rewritable by electrically erasing specified data previously written therein. As for this kind of nonvolatile memory, in consideration of the use as a substitute for a magnetic storage or the like, efforts have been made to increase the capacity and decrease the cost. For use in a portable information processing terminal or the like, however, it is required to lower the voltage requirements. Known semiconductor memories, which are nonvolatile memories that are made rewritable by erasing specified data previously written therein, include an erasable programmable read only memory (EPROM) and the EEPROM. The EPROM has the advantage of a small cell size. However, data erasing is a nuisance because ultraviolet light must be used to erase data. As for the EEPROM, data erasing is easy to do because data can be erased electrically. However, the cell size in the EEPROM is larger than that in the EPROM, which makes it difficult to increase the capacity of an EEPROM. As a semiconductor memory having the advantages of the foregoing memories, for example, what is referred to as a flash memory has been developed. The term "flash memory" will be adopted in the succeeding description. The nonvolatile semiconductor memory has an overall configuration, for example, as that shown in Fig. 1. In Fig. 1, N cell blocks 11 1 to 11 N (for example, eight blocks) each having multiple transistor cells are arranged in a row. The cell blocks 11 1 to 11 N are provided with bit line select circuits 12 1 to 12 N and sense amplifiers/sense buffers 13 1 to 13 N respectively. A row address signal is supplied from a row address buffer to each of the cell blocks 11 1 to 11 N via a row decoder 15. A column address signal is supplied from a column address buffer 16 to each of the bit line select circuits 12 1 to 12 N via a column address decoder 17. A voltage V S sent from a source power supply circuit 18 is applied to each of source electrodes of the transistor cells of the cell blocks 11 1 to 11 N . Fig. 2 shows the cell block 11, one of the cell blocks in the aforesaid nonvolatile semiconductor memory, and its peripheral circuitry. In Fig. 2, components identical to those in Fig. 1 bear the same reference numerals, of which a description will be omitted. In Fig. 2, the bit line select circuit 12 comprises n-channel MOS field-effect transistors Q1 to Qn. Column address signals Y1 to Yn are fed from the column decoder 17 to the gates of the transistors Q1 to Qn. The cell block 11 comprises a total of n by n field-effect transistors Q11 to Qnn having floating gates and control gates. The gates of n transistors Qil to Qin (where, i = 1, 2, etc., and n) arranged in tandem are provided with row address signals Xi sent from the row decoder 15 via word lines. The drains of the n transistors Qli to Qni arranged in tandem are connected to the drains of the transistors Qi in the bit line select circuit 12 via bit lines. Voltage from the source power circuit 18 is applied to each of the sources of the transistors Qll to Qnn. A cell amplifier 13a and a write buffer 13b are connected to each of the sources of the transistors Q1 to Qn. In the foregoing semiconductor memory, when row addresses Xi and column addresses Yj are selected for writing, data read from the write buffer 13 are written in the transistors Qij of the cell blocks 11 1 to 11 N . Writing is performed simultaneously on one bit per each of the cell blocks 11 1 to 11 N or a total of N bits designated with the row addresses and column addresses. Data erasing is performed concurrently on all transistors in the cell blocks 11 1 to 11 N . In a flash memory, information is retained depending on the presence or absence of a charge in a memory cell. Fig. 3 shows an example of a structure of a memory cell. As shown in Fig. 3, a gate has a two-layered structure consisting of a control gate (CG) 25 and a floating gate (FG) 24. The control gate 25 is connected to a word line WLi and a drain (D) 23 is connected to a bit line BLi. Reference numeral 26 denotes a tunneling oxide film. The flash memory is broadly divided into two types which may be referred to as NOR and NAND types. These types differ from each other in a method of writing, reading, or erasing information into or from a memory cell. Taking the NOR type flash memory as an example, writing, reading, or erasing information into or from a memory cell will be described below. When information is to be written in a memory cell having the aforesaid structure, as shown in Fig. 4, the word line WLi is set to Vpp (approx. 12 V), the bit line BLi is set to approx. 6 V, and the source S is set to 0 V. High voltage is then applied to the control gate CG and drain D. Current then flows into the memory cell. Part of the electrons flowing through the memory cell are accelerated due to the high electric field in the vicinity of the drain D, gain energy, and then go beyond the energy barrier of an insulating film of the floating gate. The electrons are finally injected into the floating gate FG. The floating gate FG is not electrically coupled with other circuits, so it therefore can retain charges on a semi-permanent basis. When information is to be read from a memory cell, as shown in Fig. 5, the word line WLi is set to Vcc (about 5 V), the bit line BLi is set to about 1 V, and the source S is set to 0 V. The memory cell is then selected by specifying the word line WLi and bit line BLi. The threshold value of the cell transistor varies depending on the charges retained in the floating gate FG. Current flowing through the selected memory cell varies depending on the information stored therein. The information therefore can be read out by detecting and amplifying the current. The voltage levels of the control gate CG, drain D, source S, and substrate PS in the aforesaid operative states are set to the values listed in Table 1. Voltages in modes in a prior art CG D S PS Reading Vcc to 1 V 0 V 0 V Writing Vpp to 6 V 0 V 0 V Erasing 0 V Float Vpp 0 V When information is to be erased from a memory cell, as shown in Fig. 6, the word line WLi is set to about 0 V and the bit line BLi is opened. In this state, the drain D is opened, about 0 volt is applied to the control gate CG, and a high voltage of about 12 volts is applied to the source S. Since a high voltage is applied to the source S, deep diffusion is required in order to increase the resistivity of the diffused layer in the source. This hinders reduction in cell area. For partial erasing (i.e. erasing of only some, rather than all, of the cells at a time), it is required that different parts of the Vss line connected to the sources must have different voltages. This leads to a need to effect disconnection of the different parts or an increased number of drive circuits. Eventually, chip size increases. A solution to the above problem is to apply a negative voltage to the word line WLi. To be more specific, as shown in Fig. 7, a negative voltage (about - 10 V) is applied to the control gate CG and Vcc (about 5 V) is applied to the source S (predetermined erasure portion). The drain D is opened. Erasing is then executed. In this case, since a low voltage is applied to the source S, the resistivity of the source need not be intensified. This contributes to reduction in cell size. Partial erasing is enabled by selectively applying negative voltage to just the required control gates CG. The aforesaid erasing method is a source erasing method in which charges in the floating gate FG are routed to the source. A channel erasing method is also available, wherein charges in the floating gate are routed to a channel; that is, a substrate (channel-containing portion). Even in this method, negative voltage is applied to the control gate. The channel erasing method is sometimes employed for the aforesaid NAND-type flash memory. Figs. 8 to 11 show the states of a memory cell with voltage applied according to various erasing methods. In Figs. 8 to 11, the memory cell is an n-channel transistor. Fig. 8 shows a state in which positive voltage is applied according to a channel erasing method. The drain D and source S are opened, and the control gate CG is set to 0 V. The high voltage Vpp is applied to the P well (predetermined erasure portion) equivalent to a channel (channel-containing portion). In channel erasing, a triple-well structure shown in Fig. 8 is adopted because positive bias is applied to the channel. Fig. 9 shows a state in which a positive voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to 0 V. The high voltage Vpp is applied to the source (predetermined erasure portion) S. The substrate is opened or set to 0 V. Fig. 10 shows a state in which a negative voltage is applied according to the channel erasing method. The drain D and source S are opened, and the control gate CG is set to a negative voltage V BB . A positive voltage Vcc is applied to the p well (predetermined erasure portion) equivalent to a channel (channel-containing portion). V BB - Vcc is applied between the control gate CG and channel. Fig. 11 shows a state in which negative voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to the negative voltage V BB . The source (predetermined erasure portion) S is set to the positive voltage Vcc. This erasing method is used, for example, in the flash memory device disclosed in US 5077691. That device may be considered to include a plurality of flash memory cells, each including a transistor having a source region, a drain region, a floating gate, a control gate, and a channel-containing portion in which a channel between the said source and drain regions of the transistor is formed when the device is in use, the said channel-containing portion being formed in a substrate of the device or in a well within the said substrate; negative-voltage source means for outputting a first potential that is negative relative to a second potential; and erase means connected to the said negative-voltage source means and operable, during a memory cell erase operation, to cause the said first potential to be applied to the said control gate of each cell to be erased whilst the said second potential is applied to a predetermined erasure portion of each such cell so that charges stored in the floating gate of the cell are removed therefrom to the said erasure portion, the said erasure portion being the said channel-containing portion or the said source region of the cell. In this device, the first (control-gate) potential is a relatively high negative voltage (-12V to -17V) and the second (source-region) potential is a relatively low positive voltage (+0.5V to +5V), and the substrate potential is ground potential (0V). This enables a relatively large potential difference to be created between the control gate and the source region whilst keeping the source-to-substrate reverse voltage at +5V or less. Incidentally, EP-A-0209912 discloses an EEPROM device having an NMOS transistor formed in a p-well in an n-type substrate. The device uses a low positive voltage (supply voltage Vcc≈5V) and a large negative voltage (-Vpp≈-12V) to achieve writing and erasing. In the erasing operation, -Vpp is applied to the gate electrode and Vcc is applied to the well. This means that the substrate potential can be fixed to a comparatively low potential, e.g. about +5V, so that a p-channel MOSFET formed on the n-type substrate can operate with ordinary signal levels. This makes it possible for the peripheral circuits of the NMOS transistor to be constructed using CMOS circuitry. Whichever method is adopted for erasing a flash memory (channel erasing or source erasing), voltage applied between the control gate CG and channel or source S (predetermined erasure portion) greatly affects the erasing. For stable erasing, the voltage to be applied between the control gate and the channel or source must be held constant irrespective of the fluctuation in external power supply. A memory for a portable device is one of currently conceivable application fields for a flash memory. This kind of portable equipment use batteries as a power supply. When employed for portable equipment, a flash memory is therefore subjected to a voltage fluctuation in an external power supply. Under these circumstances, there is an increasing demand for an erasing method for a flash memory that permits stable erasing irrelevant of a fluctuations in an external power supply, and for a flash memory that can be erased according to the erasing method. Accordingly, it is desirable to enable stable erasing for a specified period of time. A semiconductor memory device embodying a first aspect of the present invention is characterised by voltage control means connected operatively with the said control gate and the said erasure portion of each cell to be erased during such an erase operation, for maintaining a substantially-constant preselected potential difference between the applied first and second potentials during the said erase operation. According to a second aspect of the present invention there is provided an erasure method, for use in a semiconductor memory device that comprises a plurality of flash memory cells, each including a transistor having a source region, a drain region, a floating gate, a control gate, and a channel-containing portion in which a channel between the said source and drain regions of the transistor is formed when the device is in use, the said channel-containing portion being formed in a substrate of the device, or in a well within the said substrate, in which method: during a memory cell erase operation a first potential is applied to the control gate of each cell to be erased whilst a second potential is applied to a predetermined erasure portion of the cell, the erasure portion being the said channel-containing portion or the said source region of the cell, and the first potential being negative relative to the second potential so that charges stored in the floating gate of the cell are removed therefrom to the erasure portion; characterised in that during the said erase operation a substantially-constant preselected potential difference is maintained between the applied first and second potentials. In such a flash memory, and such an erasure method, the voltage between a control gate and a channel or source is held constant all the time, so errors in erasing time will be diminished. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 shows an overall configuration of a flash memory in which embodiments of the present invention can be implemented; Fig. 2 is a circuit diagram showing a major section of Fig. 1; Fig. 3 shows a structure of a memory cell; Figs. 4 to 7 are explanatory diagrams for methods of reading, writing, and erasing a flash memory; Fig. 4 shows the conditions for writing; Fig. 5 shows the conditions for reading; Fig. 6 shows the conditions for erasing; Fig. 7 shows the conditions for erasing based on negative-voltage application; Fig. 8 is an explanatory diagram for channel erasing based on high-voltage application; Fig. 9 is an explanatory diagram for source erasing based on high-voltage application; Fig. 10 is an explanatory diagram for channel erasing based on negative-voltage application; Fig. 11 is an explanatory diagram for source erasing based on negative-voltage application; Fig. 12 shows a structure of a transistor cell; Fig. 13 is an explanatory diagram for excessive erasing; Fig. 14 shows a circuitry of the first embodiment; Fig. 15 shows a circuitry of the second embodiment; Fig. 16 shows a circuitry of the third embodiment; Fig. 17 shows a circuitry of the fourth embodiment; Fig. 18 shows a circuitry of the fifth embodiment; and Fig. 19 shows a circuitry of the sixth embodiment; Prior to the embodiments, pre-erase writing will be described. Fig. 12 shows a structure of a memory cell shown in Fig. 3 in more detail. A transistor serving as the memory cell has, as shown in Fig. 12, a structure in which n-type diffusion regions 32 and 33 are formed in a p-type substrate 31 with a certain space between them. A floating gate (FG) 34 and a control gate (CG) 35 are formed above the p-type substrate 31, and coated with an oxide film 36. The n-type diffusion regions 32 and 33 are coupled with a source electrode 37 and a drain electrode 39 respectively. The control gate 35 is coupled with a gate electrode 38. An insulating film for isolating between the floating gate (FG) and control gate (CG) in the stacked gate type memory cell transistor may be an oxide film or oxide nitride film. However, an ONO film; that is, a three-layered structure of an oxide film over a nitride film over an oxide film is preferred in an effort to prevent a time-sequential leakage of charges from the floating gate (FG). Using the same process for producing the insulating film between gate electrodes, an insulating film for a gate in a single gate-type transistor which is used in any region of peripheral circuits may be produced. In this case, the gate insulating film for the single gate-type transistor formed in a region of peripheral circuits may be the ONO film or oxide nitride film. The gate insulating films for transistors other than memory cell transistors are not necessarily oxide films. Writing in a memory cell is achieved by injecting electrons into the floating gate (FG) 34, whereby "0" will be written. Erasing is achieved by removing electrons from the floating gate (FG) 34, whereby "1" will be written. When a source erasing method based on high-voltage application is performed to erase the transistor cell (to write "1"), as described previously, high voltage is applied to the source electrode 37, zero volt is applied to the gate electrode 38, and the drain electrode 39 is opened. The electrons retained in the floating gate 34 are thus removed. When "0" has been written in the transistor cell; that is, when electrons have been retained in the floating gate 34, the threshold Vth for the cell decreases over the course of an erasing period or time T in accordance with a curve I shown in Fig. 13 to become lower than a threshold level for identifying data "1". In contrast, when "1" has been written in the transistor cell; that is, when no electrons have been retained in the floating gate 34, since the threshold level is low, as the threshold of the cell decreases as indicated with II in Fig. 13 due to the erasing, the threshold level becomes 0 at a time before the end of the erasing period T. Thus, during the above erasing, too many electrons are removed from transistor cells in which "1s" have previously been written. Those transistor cells consequently enter a Normally On state. In order to prevent the foregoing excessive erasing, it is necessary for a flash memory, in which cells are NORed, to write data "0" in each of the transistor cells in all cell blocks before concurrent erasing is performed. Writing data "0" is performed on all transistor cells, wherein the data values written in the transistor cells are not checked. Specifically, a source voltage Vs for the source electrode 37 in the transistor cell shown in Fig. 12 is set to 0 V, a gate voltage Vg for the gate electrode 38 is set to a high voltage, and a drain voltage V D for the drain electrode 39 is set to a high voltage. High-energy electrons developed by applying high voltage between the source and drain then reach the floating gate 84 through the oxide film 36. Data "0" is thus written in the transistor cell. Fig. 14 shows a configuration of the first embodiment, including a memory cell, a row decoder for feeding an access signal to a word line connected to a control gate CG of the memory cell, and a circuit for applying a negative voltage. In Fig. 14 reference numeral 81 denotes a negative voltage charge pump circuit; 82 denotes a negative voltage bias circuit; 83 denotes a decoder; 80 denotes a cell transistor; 85 and 86 denote MOS diode arrays (voltage control elements) each consisting of n-channel enhancement field-effect transistors 85 1 to 85 N or 86 1 to 86 M ; n1 and n2 denote nodes; 84 denotes a NOR gate; WL denotes a word line; D denotes a drain; S denotes a source; BG denotes a well contact; CG denotes a control gate; FG denotes a floating gate; CLK denotes a clock signal; ES denotes an erase select signal; Vpp denotes an external supply voltage; and Vss denotes a ground voltage. For reading, the erase select signal ES is held low and the clock signal CLK is held high. In this state, the decoder 83 outputs a high signal when the word line WL is selected and a low signal when the word line WL is unselected. When the word line WL is low (unselected), the NCR gate 84 is responsive to the clock signal CLK, the clock signal CLK is, however, held high. The negative voltage bias circuit 82 therefore does not operate. A negative voltage V BB generated by the negative voltage charge pump circuit 81 will therefore not be applied to the word line WL. For erasing, the erase select signal ES is driven high and the clock signal CLk is supplied. In this state, the decoder 83 outputs a low signal when the word line WL is selected and a high signal when the word line WL is unselected. When the word line WL is low, the NOR gate 84 is responsive to the clock signal CLK and the negative bias circuit 82 operates. The negative voltage V BB generated by the negative voltage charge pump circuit 81 is then applied to the word line WL. In the meantime, the drain D and source S of the memory cell 80 are open, and the voltage Vpp is applied to the well contact BG. When data has been written in the memory cell 80, electrons are passed through the floating gate FG to the channel due to the tunnel effect. Erasing is thus carried out. The nodes n1 and n2 are clamped at a specified voltage by the MOS diode arrays that are the transistor arrays 85 and 86. As mentioned above, in this embodiment, it is the row decoder 83 that applies the high voltage Vpp and positive voltage Vcc to a selected word line WL during writing or reading and applies a zero voltage Vss to unselected word lines WL. Negative voltage is applied by the negative voltage charge pump circuit 81. The control for applying negative voltage to a selected word line alone is extended by the row decoder 83. The row decoder 83 has a logic reversing function for providing an output whose logic is reversed between erasing and reading or erasing. The negative voltage charge pump circuit 81 generates and outputs a negative voltage during normal operation or negative voltage application. The output voltage is restricted to a specified value by the transistor arrays connected between the negative voltage charge pump circuit 81 and the high voltage source Vpp. The negative voltage bias circuit 82 will be described later. The detailed description is omitted here therefore. In response to receipt of the clock signal CLK via gate 84, the output voltage of the negative voltage charge pump circuit 81 is placed on a word line. The effect of a decrease of Vpp by an amount a (in V) will be discussed next The potential difference between Vpp and nl is held at Vpp - V BB by the MOS diode array 85 that is a transistor array. If Vpp decreases by the amount a, the n1 voltage becomes: V BB - a The voltage between the control gate CG and channel in tne memory cell 80 is is held at: Vpp - VBB Next, the effect of an increase of Vpp by an amount a (in V) will be discussed. If Vpp increases by the amount a, the n1 voltage becomes: V BB + a The voltage between the control gate CG and channel in the memory cell 80 is then held at: Vpp - VBB As mentioned above, even if the external voltage Vpp varies, the voltage between the control gate CG and channel is held constant all the time, so stable erasing characteristics are ensured. In the foregoing first embodiment, the output voltage of the negative voltage charge pump circuit 81 is restricted to a specified value relative to the high voltage source Vpp, which is applied to the p well, by the transistor array. A voltage that is constant relative to Vpp can thus be applied. In contrast, in the second embodiment to be described next, a negative voltage V BB applied to the control gate CG and a positive voltage Vpp applied to the p well are restricted relative to a ground (zero) voltage Vss. The potential difference between the negative voltage and positive voltage is thus held constant. Fig. 15 shows a configuration of the second embodiment. What differs from the circuitry in Fig. 14 is that the output of an inverter 98 for generating voltage to be applied to the p well is restricted by a transistor array (MOS diode array) 97 and held constant relative to a ground voltage Vss, and that the output of a negative voltage charge pump circuit 91 is restricted by a transistor array (MOS diode array) 95 and held constant relative to the ground voltage Vss. The effect of a fluctuation in Vpp will now be discussed. The voltage between n3 and Vss is held constant by the transistor array 95, and the voltage between a well contact BG and Vss is held constant by the transistor array 97. Vss denotes a ground voltage, which therefore will not be affected by a fluctuation in Vpp. Irrespective of the fluctuation in Vpp, a voltage that is constant relative to Vss is always supplied to a control gate CG and the well contact BG. The voltage between the control gate CG and channel is always held constant. Despite a fluctuation in external voltage Vpp, the voltage between the control gate CG and channel is held constant. Stable erasing characteristics are ensured. Fig. 16 shows the third embodiment of a channel erasing method. In Fig. 16 reference numeral 101 denotes a negative voltage charge pump circuit; 102 denotes a negative voltage bias circuit; 103 denotes a decoder; 107, 109, and 111 denote inverters; 100 denotes a cell transistor; 105, 106, 108, and 110 are n-channel enhancement field-effect transistor arrays; n6 to n10 denote nodes; WL denotes a word line; D denotes a drain; S denotes a source; BG denotes a well contact; CLK1 to CLK3 denote clock signals; ES denotes an erase select signal; /ES denotes an erase power switching signal; Vpp denotes an external supply voltage; and Vss denotes a ground voltage. Next, the operations of the foregoing circuitry will be described. For reading, the erase select signal ES is held low, the erase power switching signal /ES is held high, and the clock signals CLK1 to CLK3 are held high. The well contact BG is biased with Vss by the inverter 111. The decoder 103 outputs a high signal when the word line WL is selected, and a low signal when the word line WL is unselected. When WL is low, the NOR gate 104 is responsive to the clock signal CLK1. The clock signal CLK1 is held high. The negative voltage bias circuit 102 therefore does not operate. Since the clock signals CLK2 and CLK3 are also held high, the negative voltage charge pump circuit 101 does not generate V BB . Negative voltage is therefore not applied to WL. For erasing, the erase select signal ES is driven high and the erase power switching signal /ES is driven low. Clock signals are fed to the clocks CLK1 to CLK3. The clock signals CLK2 and CLK3 are mutually 180° out of phase. The decoder 103 outputs a low signal when the word line WL is selected, and a high signal when the word line WL is unselected. When WL is low, the NOR gate 104 is responsive to the clock signal CLK1. The negative voltage bias circuit 102 operates and applies V BB generated by the negative voltage charge pump circuit 101 to the word line WL. At this time, the source S and drain D of the cell transistor 100 are open and the well contact BG is provided with high voltage by the inverter 111. If data has been written in the cell transistor 100, electrons are passed through the control gate CG to the channel due to the tunnel effect. Erasing is thus achieved. The n6 to n10 and well contact BG are clamped at certain voltages with Vss as a reference voltage by the transistor arrays 105, 106, 108, and 110. The effect of fluctuation in Vpp will now be discussed. The value of a voltage V BB generated by the negative voltage charge pump circuit 101 is determined by the amplitude of a signal fed to the negative voltage charge pump circuit 101, the coupling coefficient, and the threshold voltage of a transistor. What is critical about a product is the amplitude of an input signal. In this embodiment, however, since the input terminals n8 and n9 of the negative voltage charge pump circuit 101 are clamped at constant voltages with Vss as a reference voltage, the input terminals n8 and n9 are free from the influence of a fluctuation in Vpp. The output voltage V BB of the negative voltage charge pump circuit 101 is held constant irrespective of the fluctuation in Vpp. The voltage applied to the well contact BG is also clamped with Vss as a reference voltage, which therefore is constant irrespective of the fluctuation in Vpp. Even if Vpp fluctuates, the voltage between the control gate CG and channel is held constant. As mentioned above, even if the external voltage Vpp fluctuates, the voltage between the control gate CG and channel is held constant, so stable erasing characteristics are ensured. The aforesaid embodiments provide channel erasing methods in which the voltage applied between a control gate and a channel is held constant in order to ensure stable erasing. Even in source erasing, stable erasing is assured by restricting applied voltage in the same manner. Figs. 17 to 19 show the fourth to sixth embodiments permitting stable source erasing. Unlike the channel erasing circuitry shown in Figs. 14 to 16, voltage to be applied to a p well is applied to a source S. As described previously, in a flash memory embodying the present invention, a simple row decoder applies negative voltage for erasing. The circuitry is therefore downsized and high integration is realized. Furthermore, stable erasing contributes to an improvement in reliability. Flash memories are expected to substitute for magnetic storages. For use in portable equipment on behalf of magnetic storages, in particular, the properties of flash memories; that is, small size and light weight will prove very helpful. For actual use in portable equipment in place of magnetic storage, the flash memory must further be innovated to achieve downsizing, an increase in operational speed, reduction in power consumption, and decrease in voltage requirements. Embodiments of the present invention provide innovative flash memory and solve some of the problems obstructing the widespread use of the flash memory.

Claims: A semiconductor memory device including: a plurality of flash memory cells (80; 90; 100; 120; 130; 140), each including a transistor having a source region (S), a drain region (D), a floating gate (FG), a control gate (CG), and a channel-containing portion (p-well; p-sub) in which a channel between the said source and drain regions (S, D) of the transistor is formed when the device is in use, the said channel-containing portion being formed in a substrate (p-sub) of the device or in a well (p-well) within the said substrate; negative-voltage source means (81; 91; 101; 121; 131; 141) for outputting a first potential (V BB ) that is negative relative to a second potential (Vpp); and erase means (82 to 84; 92 to 94, 98; 102, 103, 111; 122 to 124; 132 to 134, 138; 142 to 144, 151) connected to the said negative-voltage source means and operable, during a memory cell erase operation, to cause the said first potential (Vase) to be applied to the said control gate (CG) of each cell to be erased whilst the said second potential (Vpp) is applied to a predetermined erasure portion (p-well; S) of each such cell so that charges stored in the floating gate of the cell are removed therefrom to the said erasure portion, the said erasure portion being the said channel-containing portion (p-well; p-sub) or the said source region (S) of the cell; characterised by: voltage control means (85, 86; 95 to 97; 105, 106, 108, 110; 125, 126; 135 to 137; 145, 146, 148, 150), connected operatively with the said control gate (CG) and the said erasure portion (p-well; p-sub; S) of each cell to be erased during such an erase operation, for maintaining a substantially-constant preselected potential difference (V BB -Vpp) between the applied first and second potentials during the said erase operation. A device as claimed in claim 1, wherein the said erase means are operable to set the said second potential to a positive supply potential (Vcc) of the device during the said erase operation, and the said first potential is negative with respect to a ground potential (Vss) of the device. A device as claimed in claim 1, wherein the said erase means are operable to set the said second potential to a high positive potential (Vpp) of the device during the said erase operation, and the said first potential is a ground potential (Vss) of the device. A device as claimed in claim 1, 2 or 3, wherein the said erasure portion is the said channel-containing portion (p-well; p-sub), and the said erase means are operable in the said erase operation to set the said source and drain regions (S, D) of each cell to be erased to an open-circuit condition. A device as claimed in claim 1, 2 or 3, wherein the said erasure portion is the said source region (S), and the said erase means are operable in the said erase operation to set the said drain region (D) of each cell to be erased to an open-circuit condition. A device as claimed in any preceding claim, wherein the said negative-voltage source means include charge pump means (81; 91; 101; 121; 131; 141) connected for deriving the said first potential from a power supply potential (Vpp) of the device. A device as claimed in any preceding claim, wherein the said voltage control means include a voltage control element (85; 125; 135) having a first node connected operatively to a first connection line (WL) of the device by which the said first potential (V BB ) is applied to the said control gate (CG) during the said erase operation, and also having a second node connected operatively to a second connection line (BG) of the device by which the said second potential (Vpp) is applied to the said predetermined erasure portion during the said erase operation. A device as claimed in any one of claims 1 to 6, wherein the said voltage control means include: a first voltage control element (95; 107, 108; 146, 148) having a first node connected operatively to a first connection line (WL) of the device by which the said first potential (V BB ) is applied to the said control gate during the said erase operation, and also having a second node connected to a reference potential line (Vss) of the device; and a second voltage control element (97; 110; 137; 150) having a first node connected operatively to a second connection line of the device by which the said second potential (Vpp) is applied to the said predetermined erasure portion during the said erase operation, and also having a second node connected to the said reference potential line (Vss). A device as claimed in claim 7 or 8 when read as appended to claim 6, wherein the voltage control element (85; 95; 125; 135) that is connected operatively to the first connection line (WL) is connected on an output side of the charge pump means (81; 91; 121; 131). A device as claimed in claim 7 or 8 when read as appended to claim 6, wherein the voltage control element (106, 108; 146, 148) that is connected operatively to the first connection line (WL) is connected on an input side of the charge pump means (101; 141). A device as claimed in any one of claims 7 to 10, wherein the or each said voltage control element serves to prevent a potential difference between its said first and second nodes from exceeding a predetermined value. A device as claimed in any one of claims 7 to 11, wherein the or each said voltage control element comprises an MOS diode array. A device as claimed in claim 12, wherein the said MOS diode array of the or each said voltage control element is formed by a plurality of n-type MOS enhancement type transistors connected in series between the said first and second nodes of the element concerned. An erasure method, for use in a semiconductor memory device that comprises a plurality of flash memory cells (80; 90; 100; 120; 130; 140), each including a transistor having a source region (S), a drain region (D), a floating gate (FG), a control gate (CG), and a channel-containing portion in which a channel between the said source and drain regions (S, D) of the transistor is formed when the device is in use, the said channel-containing portion being formed in a substrate (p-sub) of the device, or in a well (p-well) within the said substrate, in which method: during a memory cell erase operation a first potential (V BB ) is applied to the control gate (CG) of each cell to be erased whilst a second potential (Vpp) is applied to a predetermined erasure portion (p-well; p-sub; S) of the cell, the erasure portion being the said channel-containing portion or the said source region of the cell, and the first potential being negative relative to the second potential so that charges stored in the floating gate of the cell are removed therefrom to the erasure portion; characterised in that during the said erase operation a substantially-constant preselected potential difference (V BB -Vpp) is maintained between the applied first and second potentials. A method as claimed in claim 14, wherein the said first potential (V BB ) is negative with respect to a ground potential (Vss) of the device and the said second potential is a positive supply voltage (Vcc) of the device during the said erase operation. A method as claimed in claim 14, wherein the said first potential is a ground potential (Vss) of the device and the said second potential is a high positive potential (Vpp) of the device during the said erase operation. A method as claimed in claim 14, 15 or 16, wherein the said erasure portion is the said channel-containing portion (p-well; p-sub), and in the erase operation the source and drain regions (S, D) of each cell to be erased are set to an open-circuit condition. A method as claimed in claim 14, 15 or 16, wherein the said erasure portion is the said source region (S), and in the erase operation the said drain region (D) of each cell to be erased is set to an open-circuit condition.

Inventors: AKAOGI TAKAO, HAGIWARA RYOJI, ITANO KIYOSHI, KASA YASUSHI, KAWAMURA SHOUICHI, KAWASHIMA HIROMI, OGAWA YASUSHIGE, TAKEGUCHI TETSUJI, AKAOGI, TAKAO, HAGIWARA, RYOJI, ITANO, KIYOSHI, KASA, YASUSHI, KAWAMURA, SHOUICHI, KAWASHIMA, HIROMI, OGAWA, YASUSHIGE, TAKEGUCHI, TETSUJI, AKAOGI, TAKAO FUJITSU LIMITED 1015, KAMIKODANAKA, HAGIWARA, RYOJI FUJITSU LIMITED, ITANO, KIYOSHI FUJITSU LIMITED 1015, KAMIKODANAKA, KASA, YASUSHI FUJITSU LIMITED 1015, KAMIKODANAKA, KAWAMURA, SHOUICHI FUJITSU LIMITED, KAWASHIMA, HIROMI FUJITSU LIMITED, OGAWA, YASUSHIGE FUJITSU VLSI LIMITED, TAKEGUCHI, TETSUJI FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1992
Main classification: G11C16
IPC codes: G05F3, H03K3, G11C16, H03K19, G11C29