Semiconductor device for improving high-frequency characteristics and avoiding chip cracking

Abstract: A semiconductor device comprises a plurality of gate electrodes (14), drain electrodes (5), and source electrodes (11), axi-symmetrically formed on opposite sides of a gate pad (12) and drain pad (4). Two source pads (9, 10) are arranged at the ends of these electrodes, to which the source electrodes are connected, so that a gate width (WW) can be shortened. Therefore, an output power, gain, etc., can be increased, and the high-frequency characteristics can be improved. Further, when arranging a plurality of semiconductor devices in parallel, the semiconductor chip can be formed in the shape of a square, i.e., the aspect ratio thereof can be reduced, therefore, cracks in the semiconductor chip (semiconductor device) can be avoided.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, more particularly, to a semiconductor device having a plurality of high-output power semiconductor transistors. 2. Description of the Related Art Recently, digital communication systems such as mobile communication systems using satellite and quadrature amplitude modulation (QAM) communication networks have been rapidly developed, and these communication systems require high-power microwave semiconductor devices constituted by arranging a plurality of high-frequency high-output power transistors, accordingly, to meet this requirement, for example, metal semiconductor field effect transistors (MESFETs), metal insulator semiconductor field effect transistors (MISFETs), and high electron mobility transistors (HEMTs) have been studied and developed. In a high-power microwave amplifier using the above semiconductor devices, which are used, for example, to amplify signals of microwave band (1 GHz to 20 GHz) for transfer to a communication satellite, the semiconductor device (semiconductor chip) is positioned between an input matching circuit and an output matching circuit, and these input and output matching circuits are used for impedance matching at the input and output sides of the semiconductor chip (semiconductor device). Further, the input side electrodes of the semiconductor chip are connected to electrodes of the input matching circuit by bonding wires, and the output side electrodes of the semiconductor chip are connected to electrodes of the output matching circuit by bonding wires. When producing (assembling) the microwave amplifier, the semiconductor chip is directly disposed at a position between the input matching circuit and the output matching circuit in a package, and the semiconductor chip is then fixed to the surface of the package by heating and melting gold-tin alloy and by carrying out a scrub process, i.e., a process of scrubbing the semiconductor chip on the surface of the package. Note, the semiconductor chip (semiconductor device) is made thin, e.g., 30 µm or 100 µm, to effectively radiate the heat self-produced by the chip, because a high-power microwave semiconductor chip produces a large amount of heat. Further, the semiconductor chip for a high-power microwave semiconductor device is made, for example, of a compound semiconductor material (Gallium Arsenide: GaAs, and the like), which is more delicate than a silicon (Si) semiconductor chip, and thus may be broken during the scrub process and the like. Recently, semiconductor devices comprising a plurality of source electrodes, drain electrodes, and gate electrodes have been studied and developed. For example, in such a semiconductor device, the source electrodes and the drain electrode are formed into an interdigital shape (comb-like shape), the source and drain electrodes are alternated and spaced apart from one another, and the gate electrodes are formed in a comb like manner between the source electrodes and drain electrodes. In this semiconductor device, when the output power of the semiconductor device must be increased, a unit gate width must be widened, or a total length of the gate widths must be made larger. Accordingly, to enlarge the total gate width, the semiconductor device (semiconductor chip) is comprised of a plurality of transistor cells (semiconductor device) arranged in parallel. Note, when the unit gate width is widened, to thereby realize a high-frequency high-output power semiconductor device, electric power supplied to ends of the source electrodes and drain electrodes is not uniformly transmitted to the other ends of the electrodes due to the gate width, and further, an uneven phase rotation may occur, and an output power of the semiconductor device may be lowered. Furthermore, when the number of transistor cells is increased and the cells are arranged in parallel, the shape of the semiconductor chip (semiconductor device) is a rectangle having one side much longer than the other. Namely, the semiconductor device must be made long and thin, and thus the semiconductor device may be broken during the scrub process and the like. These problems of the prior art will be explained hereafter in detail. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device by which the high-frequency characteristics thereof are improved and in which chip cracking easily caused. This object is achieved by the features of claim 1. FR-A-2 369 689 discloses a transistor with gate electrodes are provided on upper and lower portions of the drain electrode, or divided into two units, and thus two gate wirings must be provided. EP-A-0 015 072 discloses a transistor having a part of the source electrode inserted into the drain and gate electrodes. The first electrodes may extend in two opposite directions from a first conductive pad, and two of a second conductive pads may be provided. A plurality of the semiconductor devices may be arranged in parallel, to constitute a semiconductor chip. Further, the semiconductor device may be formed in the shape of a square. The first electrodes may extend in three directions from the first conductive pad, and three of the second conductive pads are provided. The first electrodes may also extend in four directions from the first conductive pad, and four of the second conductive pads may be provided. A plurality of the semiconductor devices may be arranged to constitute a semiconductor chip having the shape of a square. The semiconductor device may include a plurality of transistors, the first electrodes are drain electrodes, the second electrodes are source electrodes, and the third electrodes are gate electrodes of the transistors. The semiconductor device may amplify signals of microwave band. Further, according to the present invention, there is also provided a microwave amplifier including a semiconductor device as claimed for amplifying signals, an input matching circuit, connected to the semiconductor device, for carrying out an impedance matching at an input side of the semiconductor device; and an output matching circuit, connected to the semiconductor device, for carrying out an impedance matching at an output side of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: Figure 1 is a plan view showing an example of a semiconductor device according to the prior art; Figure 2 is a plan view showing another example of a semiconductor device according to the prior art; Figure 3 is a characteristic view showing a relationship between a unit gate width and an output voltage drop; Figure 4 is a plan view showing a first embodiment of a semiconductor device according to the present invention; Figures 5A to 5C are partial enlarged sectional views showing examples of the semiconductor device shown in Fig. 4; Figure 6 is a partial enlarged perspective view showing the semiconductor device shown in Fig. 4; Figure 7 is a plan view showing a second embodiment of a semiconductor device according to the present invention; Figure 8 is a plan view showing a part of a microwave amplifier using the second embodiment shown in Fig. 7; Figure 9 is a plan view showing a third embodiment of a semiconductor device according to the present invention; and Figure 10 is a plan view showing a fourth embodiment of a semiconductor device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS For a better understanding of the preferred embodiments, the problems of the prior art will be explained with reference to Figs. 1 to 3. Figure 1 shows an example of a semiconductor device according to the prior art, more particularly, Fig. 1 shows an example of the structure of a high-output MESFET of the prior art. As shown in Fig. 1, the semiconductor device (MESFET) comprises two pads aa and bb, a plurality of source electrodes ss, drain electrodes dd, and gate electrodes gg. The source electrodes ss are connected to the pad aa, and the drain electrodes dd are connected to the pad bb, positioned at opposite side of the pad aa. Namely, as shown in Fig. 1, the source electrodes ss and the drain electrode dd are formed in the shape of a comb (interdigital shape), the source and drain electrodes ss, dd are alternated and spaced apart from one another on an n-GaAs substrate cc, and the source and drain electrodes ss, dd are connected with an n-GaAs substrate cc by an ohmic contact. Further, the gate electrodes gg are formed in the shape of a comb between the source electrodes ss and drain electrodes dd, and the gate electrode gg are connected to the n-GaAs substrate cc by a Schottky contact. Note, in the semiconductor device shown in Fig. 1, when the output power of the semiconductor device must be increased, a unit gate width WW must be widened. Namely, when increasing an output power of the semiconductor device, a total length of the gate widths (total gate width) must be lengthened. Figure 2 shows another example of a semiconductor device according to the prior art. As shown in Fig. 2, when arranging a plurality of transistor cells TT in parallel, the total gate width becomes long, and thus an output power of the semiconductor device becomes large. Note, each of the transistor cells TT corresponds to the semiconductor device shown in Fig. 1. Note, when the number of the transistor cells TT is increased, or when the number of electrodes gg, ss, and dd is increased, a length of a gate bus line corresponding to a length LL of the semiconductor device (semiconductor chip) must be enlarged. Namely, when the numbers of the transistor cells TT is increased and the cell are arranged in parallel, the shape of the semiconductor chip (semiconductor device) is a rectangle having one side (LL) much longer than the other. Therefore, the semiconductor device must be made long and thin, and is made, for example, of a compound semiconductor material (GaAs, and the like), and thus the semiconductor device may be broken during the scrub process and the like. Further, the high-frequency characteristics of the semiconductor device (transistor) may deteriorated by an uneven phase rotation. Figure 3 is a characteristic view showing a relationship between a unit gate width and an output voltage drop. As shown in Fig. 3, the output voltage of the semiconductor device is lowered in accordance with an enlarging of the unit gate width WW, or an enlarging of the total gate width of the semiconductor device. Namely, when the unit gate width WW is widened, to thereby realize a high-frequency high-output power semiconductor device, electric power supplied to ends of the source electrodes ss and drain electrodes dd is not uniformly transmitted to the other ends of the electrodes, due to the gate width WW. Further, an uneven phase rotation may occur, and an output power of the semiconductor device may be lowered. Preferred embodiments of a semiconductor device according to the present invention will be now explained, with reference to the accompanying drawings. Figure 4 shows a first embodiment of a semiconductor device according to the present invention, Figs. 5A to 5C are partial enlarged sectional views showing examples of the semiconductor device shown in Fig. 4, and Fig. 6 is a partial enlarged perspective view showing the semiconductor device shown in Fig. 4. In Fig. 4, reference numeral 1 denotes an n-GaAs (n-type Gallium Arsenide) layer formed on an i-GaAs (intrinsic Gallium Arsenide) substrate 2, and an insulation film 3, on which a conductivity drain pad 4 is formed, is formed on the n-GaAs layer 1. A plurality of drain electrodes 5 are formed at regular intervals on each side of the pad 4, in the shape of comb (interdigital shape), and are in an ohmic contact with the n-GaAs layer 1. As shown in Fig. 6, a part of each drain electrode 5 close to the drain pad 4 is lifted from the n-GaAs layer 1 to form a parabolic air bridge 6. As shown in Fig. 4, insulation films 7 and 8 are formed on the n-GaAs layer 1 adjacent to ends of the drain electrodes 5 having an opposite orientation, and conductive first and second source pads 9 and 10 are formed on the insulation films 7 and 8, respectively. The edges of the source pads 9, 10 are connected to source electrodes 11 disposed at regular intervals along the drain electrodes 5. The source electrodes 11 are in ohmic contact with the n-GaAs layer 1. Further, reference numeral 12 denotes a conductive gate pad arranged on the insulation film 3 exposed through an opening 4a of the drain pad 4. Opposite sides of the gate pad 12 are connected to gate lead electrodes 13, respectively, arranged below the air bridges 6, and each of the gate lead electrodes 13 is connected to a plurality of gate electrodes 14 in Schottky contact with the n-GaAs layer 1. The gate electrodes 14 are arranged between and spaced apart from the source electrodes 11 and drain electrodes 5. As shown in Fig. 4, a width WW of the gate electrodes 14 is set such that an output voltage drop due to an uneven phase rotation is minimized when a high-frequency signal voltage is applied to the gate electrodes 14. Namely, by comparing the semiconductor device shown in Fig. 4 with that shown in Fig. 1, the length of the unit gate width WW of the semiconductor device of Fig. 4 can be made a half of that of Fig. 1, when a total length of the gate widths (total gate width) of each of the semiconductor device are made equal. Therefore, the high-frequency characteristics of the semiconductor device can be improved, and chip cracking in the semiconductor device is not easily caused. Figures 5A to 5C show a metal semiconductor field effect transistor (MESFET), a metal insulator semiconductor field effect transistors (MISFET), and a high electron mobility transistors (HEMT), respectively. As shown in Fig. 5A, in the MESFET, the gate electrode 14 is directly formed on the n-GaAs layer 1, and further, reference numeral 15 denotes a depletion layer to be produced in the n-GaAs layer 1 when a voltage is applied to the gate electrodes 14. As shown in Figs. 5B to 5C, in the MISFET and HEMT, references 1BB and 1CC denote n-GaAs layers corresponding to the layer 1 shown in Fig. 5A, 2BB and 2CC denote i-GaAs substrates corresponding to the substrate 1 of Fig. 5A, 5BB and 5CC denote drain electrodes corresponding to the drain electrode 11 of Fig. 5A, 11BB and 11CC denote source electrodes corresponding to the source electrode 11 of Fig. 5A, and 14BB and 14CC denote gate electrodes corresponding to the gate electrode 14 of Fig. 5A. Note, as shown in Fig. 5B, in the MISFET, an insulation layer 16BB is provided between the gate electrode 14BB and the n-GaAs layer 1BB. Further, as shown in Fig. 5C, in the MISFET, the gate electrode 14CC is directly formed on the n-GaAs layer 1CC. Next, the operation of this embodiment will be explained. The gate electrodes 14 (14BB, 14CC), drain electrodes 5 (5BB, 5CC), and source electrodes 11 (11bb, 11CC) are axi-symmetrically formed on opposite sides of the gate pad 12 and drain pad 4, the two source pads 9 and 10 are arranged at the ends of these electrodes, and the source electrodes 11 are connected to the pads 9 and 10. Since the gate width WW is set to prevent a voltage drop due to an uneven phase rotation, the electric power is uniformly delivered to all of the source electrodes 11 and drain electrodes 5, to thereby prevent a drop in the output voltage. Further, the drain electrodes 5, etc., are formed on the opposite sides of the pads 4 and 12, and thereby, at the number of gate electrodes 14, drain electrodes 5, and source electrodes 11 is greater than the number of electrodes of the prior art semiconductor device (with reference to Fig. 1) having the electrodes formed on only one side of a pad. Therefore, in the semiconductor device of the present embodiment, the currents flowing in the electrodes 14, 5, and 11 can be increased. Consequently, according to the semiconductor device of the present embodiment, the influence of uneven phase rotation in the transistor (semiconductor device) can be reduced. Figure 7 shows a second embodiment of a semiconductor device according to the present invention. As shown in Fig. 7, in the semiconductor device of the second embodiment, a plurality of the semiconductor devices shown in Fig. 4 are arranged in parallel; this corresponds to the device shown in Fig. 2 of the prior art. By comparing the semiconductor device (semiconductor chip) shown in Fig. 7 with that shown in Fig. 2, when a total length of the gate widths (total gate with) of the semiconductor device of Fig. 7 is the same as that of Fig. 2, a length LL of the semiconductor device (semiconductor chip), or a gate bus line of the semiconductor device of the present invention shown in Fig. 7, is a half of that shown in Fig. 2. Therefore, the shape of the semiconductor device can be made a rectangle having one side (LL) not much larger than the other, i.e., the shape of the semiconductor device can be made approximately a square, and thus the semiconductor device is not easily broken during the scrub process and the like. Namely, when the length LL of the semiconductor device of the semiconductor device of Fig. 7 is the same as that of Fig. 2, the total gate width of the semiconductor device of Fig. 7 can be made double that of Fig. 2. Further, when the length LL of the semiconductor device of the semiconductor device of Fig. 7 is the same as that of Fig. 2, and further, when the total gate widths thereof are made the same, a unit gate width WW of the semiconductor device shown in Fig. 7 can be made a half of that shown in Fig. 2, and therefore, the high-frequency characteristics of the semiconductor device (transistor) are not deteriorated by an uneven phase rotation. As described above, when a plurality of the semiconductor device (elements) of Fig. 4 are arranged as shown in Fig. 7, the length LL of the semiconductor device thereof can be shortened, or can be made a half of the length of the conventional semiconductor device shown in Fig.2, whereby the electric power is uniformly distributed and the influence of the phase rotation can be reduced. Therefore, according to the present embodiment, the output power, gain, etc., of a high-frequency high-output power transistor can be increased, i.e., high-frequency characteristics of the semiconductor device can be improved. Further, according to the present embodiment, the aspect ratio of the semiconductor chip (semiconductor device) can be reduced, and thus cracks in the semiconductor device can be avoided. Figure 8 shows a part of a microwave amplifier using the second embodiment shown in Fig. 7. In Fig. 8, reference numeral 200 denotes a microwave amplifier, 100 denotes a high-power compound semiconductor device (semiconductor chip) corresponding to that shown in Fig. 7, 101 denotes an input matching circuit for carrying out an impedance matching at an input side of the semiconductor device 100, and 102 denotes an output matching circuit for carrying out an impedance matching at an output side of the semiconductor device 100. Note, the microwave amplifier 200 having an output power of, for example, 4 watts or 8 watts, is used to amplify signals of the microwave band (1 GHz to 20 GHz) for transfer to a communication satellite. As shown in Fig. 8, the semiconductor device 100 is positioned between the input matching circuit 101 and the output matching circuit 102, input side electrodes (gate electrodes) of the semiconductor device 100 are connected to an electrode 113 of the input matching circuit 101 by a plurality of bonding wires 114, and output side electrodes (drain electrodes) of the semiconductor device 100 are connected to an electrode 123 of the output matching circuit 102 by a plurality of bonding wires. Note, as shown in Fig. 8, the input matching circuit 101 comprises a substrate 111 made of aluminum oxide (Al 2 O 3 : alumina), a metallic pattern portion 112 and the electrode 113, and similarly, the output matching circuit 102 comprises a substrate 121 made of aluminum oxide (Al 2 O 3 ), a metallic pattern portion 122 and the electrode 123. Further, the semiconductor device 100 is formed on a metallic portion 132, and the electrodes 113 and 123 are formed on aluminum oxide portions 131 and 133. When producing (assembling) the microwave amplifier 200, the semiconductor device 100 is disposed on the metallic portion 132 between the input matching circuit 101 and the output matching circuit 102 in a package (not shown), and then the semiconductor device 100 is fixed to the surface of the package by heating and melting gold-tin alloy, and by carrying out a scrub process. Note, the metallic pattern portions 112 and 122 are formed to carry out a fine control of the impedance matching at the input and output sides of the amplifier circuit 200. In the above description, the high-power microwave semiconductor device 100 is formed thinly (for example, 30 µm or 100 µm) to effectively radiate the heat produced thereby, because the semiconductor device 100 consumes a large amount of power, and thus produces a large amount of heat. Note, the semiconductor device 100 used for a high-power microwave amplifier 200 (for example, made of Gallium Arsenide (GaAs)) is more delicate than that of silicon (Si), but the semiconductor device 100 can be formed as a square, and thus the semiconductor device 100 is not easily broken during the scrub process and the like. Figures 9 and 10 show third and fourth embodiments of a semiconductor device according to the present invention. As shown in Figs. 9 and 10, in the third and fourth embodiments of the semiconductor device of the present invention, the gate electrodes, source electrodes, and drain electrodes are axi-symmetrically arranged around the drain pad. Namely, as shown in Fig. 9, in the third embodiment it is possible to arrange the electrodes in three directions orthogonal to one another, and to lay out a plurality of these arrangements. In Fig. 9, reference numeral 20 denotes a gate pad, 21 a drain pad, and 22 to 24 are source pads. Further, as shown in Fig. 10, in the fourth embodiment, it is also possible to arrange the electrodes in four directions orthogonal to one another, and to lay out a plurality of these arrangements. In Fig. 10, reference numeral 30 denotes a gate pad, 31 a drain pad, and 32 to 25 are source pads. Note, the semiconductor devices 110 and 120 shown in Figs. 9 and 10 can be also applied to a microwave amplifier, the explanations of which are the same as given above with reference to Fig. 8. Namely, in the third embodiment 110 of the semiconductor device shown in Fig. 9, the drain electrodes (5) extend in three directions from the drain pad 21. Note, three source pads (22, 23, 24) are provided in accordance with the three directions in which the drain electrodes are extended. Similarly, in the fourth embodiment 120 of the semiconductor device shown in Fig. 10, the drain electrodes (5) extend in four directions from the drain pad 31. Note, four source pads (32, 33, 34, 35) are provided in accordance with the four directions in which the drain electrodes are extended. Note, the semiconductor device of the third and fourth embodiments can be arranged to constitute a semiconductor chip having the shape of a square, whereby cracks in the semiconductor device can be avoided. As described above, these embodiments prevent an output voltage drop due to a phase rotation, provide a higher output, further reduce an aspect ratio of the device, and suppress chip cracking. Note, although not shown in Figs. 9 and 10, each of the pads shown in Figs. 9 and 10 is connected to electrodes, similar to the arrangement shown in Fig. 4. In the above description, the embodiments of the semiconductor device can use various types of transistors, such as MESFETs, MISFETs, HEMTs, and the like. Further, the present invention also can be applied for improving the characteristics of high power amplification vertical junction FETs formed on a silicon substrate, and of other high-output power transistors, by forming gate, source, and drain electrodes in two to four directions around a pad, as explained above. As described above, according to the present invention, when a plurality of the semiconductor device are arranged, the length LL of the semiconductor device thereof can be shortened, so that electric power is uniformly distributed and the influence of a phase rotation can be reduced. Therefore, the output power, gain, etc., of a high-frequency high-output power transistor can be increased, i.e., the high-frequency characteristics of the semiconductor device can be improved. Further, according to the present invention, the aspect ratio of the semiconductor chip (semiconductor device) can be reduced, and thus cracks in the semiconductor device can be avoided. Many widely differing embodiments of the present invention may be constructed without departing from the scope of the present invention, and it should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims: A semiconductor device for amplifying signals having at least one transistor, said transistor comprising: a semiconductor layer (1; 1BB; 1CC); a first conductive pad (4; 21; 31) formed on said semiconductor layer (1; 1BB, 1CC); a plurality of first groups of first electrodes (5; 5BB, 5CC) connected to said first conductive pad (4; 21; 31), each first group comprising plural first electrodes arranged in a comb-shape, the plurality of first groups extending from said first conductive pad in a plurality of respective and different directions; a plurality of second conductive pads (9, 10; 22, 23, 24; 32, 33, 34, 35) formed on said semiconductor layer (1; 1BB, 1CC) respectively corresponding to the plurality of first groups of first electrodes and formed adjacent to the free ends of said first electrodes (5, 5BB, 5CC) of said respectively corresponding first groups; a plurality of second groups of second electrodes (11, 11BB, 11CC) respectively associated with said plurality of second pads and the respectively corresponding plurality of first groups of first electrodes, each second group comprising plural second electrodes extending from the corresponding second conductive pad (9, 10; 22, 23, 24; 32, 33, 34, 35) arranged in a comb-shape interdigitated with the corresponding first electrodes (5; 5BB, 5CC); a third conductive pad (12; 20; 30) formed in an inner region of said first conductive pad (4; 21; 31), and electrically isolated from said first conductive pad (4; 21; 31); and a plurality of third groups of third electrodes (14; 14BB, 14CC) connected to said third conductive pad (12; 20; 30), and formed on said semiconductor layer (1; 1BB, 1CC) and respectively corresponding to the plurality of first and second groups of first and second electrodes, each third group comprising plural third electrodes, the third electrodes of each third group being disposed within the space between respective, adjacent first electrodes (5; 5BB, 5CC) and second electrodes (11, 11BB, 11CC) of the corresponding and respectively associated first and second groups thereof. A semiconductor device as claimed in claim 1, wherein said first electrodes (5; 5BB, 5CC) extend in two opposite directions from said first conductive pad (4), and two of said second conductive pads (9, 10) are provided. A semiconductor device as claimed in claim 1 or 2, wherein a plurality of said transistors are arranged in parallel, to constitute a semiconductor device (100). A semiconductor device as claimed in any of claims 1 to 3, wherein said semiconductor device (100; 110; 120) is formed in the shape of a square. A semiconductor device as claimed in any of claims 1, 3 or 4, wherein said first electrodes (5; 5BB, 5CC) extend in three directions from said first conductive pad (21), and three of said second conductive pads (22, 23, 24) are provided. A semiconductor device as claimed in any of claims 1, 3 or 4, wherein said first electrodes (5; 5BB, 5CC) extend in four directions from said first conductive pad (31), and four of said second conductive pads (32, 33, 34, 35) are provided. A semiconductor device as claimed in claim 5 or 6, wherein a plurality of said transistors are arranged to constitute a semiconductor chip (110; 120) having the shape of a square. A semiconductor device as claimed in claim any one of the preceding claims, wherein said semiconductor device includes a plurality of said transistors, said first electrodes (5; 5BB; 5CC) are drain electrodes, said second electrodes (11; 11BB; 11CC) are source electrodes, and said third electrodes (14; 14BB, 14CC) are gate electrodes of said transistors. A semiconductor device as claimed in any one of the preceding claims, wherein said semiconductor device (100, 110, 120) is applied to a microwave amplifier including an input matching circuit (101), connected to said semiconductor device (100, 110, 120), for carrying out an impedance matching at an input side of said semiconductor device (100, 110, 120); and an output matching circuit (102), connected to said semiconductor device (100, 110, 120), for carrying out an impedance matching at an output side of said semiconductor device (100, 110, 120).

Inventors: AOKI YOSHIO, KOJIMA MASAKAZU, SANO SEIGO, AOKI, YOSHIO, KOJIMA, MASAKAZU, SANO, SEIGO, Aoki, Yoshio, c/o Fujitsu Limited, Kojima, Masakazu, c/o Fujitsu Limited, Sano, Seigo, c/o Fujitsu Yamanashi Electronics
Applicants: FUJITSU LTD, FUJITSU YAMANASHI ELECTRONIC, FUJITSU LIMITED, FUJITSU YAMANASHI ELECTRONICS LIMITED
Application year: 1992
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L23