Photo-electric converter

Abstract: A photo-electric converter comprises a plurality of sensor columns; a reference voltage control circuit for correcting a difference between outputs of the sensor columns; a control block including a plurality of comparators for discriminating the output voltages of photo-sensing elements of the sensor columns and an accumulation time control circuit connected to the comparators, wherein switching element is adapted to be driven by the output of the control block to make the output accumulation time to be correlated to the output voltages of the photosensing elements. The reference voltage control circuit controls a comparison reference voltage applied to the comparators of the control block to cause the sensor columns to produce outputs of the same level.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric converter which varies an accumulation time as an illumination of an object changes so that an output voltage in a predetermined range is always produced. Related Background Art Since the illumination of the object varies in a wide range such as 10 -3 to 10 3 luxes, a sufficient dynamic range of the output voltage in a prior art photo-electric converter used for AF (auto-focusing) means of a camera cannot be attained by setting a fixed accumulation time. Thus, the accumulation time is varied with the change of the illumination of the object and the output voltage is amplified in accordance with the accumulation time to attain a so-called AGC (auto-gain control) so that the output voltage within a predetermined range is produced without regard to the illumination of the object. In such a contrast control type photo-electric converter, a control method for detecting the illumination of the object on real-time basis and terminating the accumulation when a predetermined input level is reached is disclosed in Japanese Laid-Open Patent Application JP-A-61-167916. An improvement over the above control method in which maximum and minimum values of the illumination are detected on real-time basis, the accumulation time is changed in accordance with a difference between the maximum and the minimum, that is, a contrast of the object, and the output voltage is amplified in accordance with the contrast, is disclosed in Japanese Laid-Open Patent Application JP-A-1-222583. In the disclosed construction, a constant contrast component can always be taken out without regard to the condition of the object so that a control system which is strong to a low contrast can be attained. Fig. 1 shows a circuit block diagram of a configuration of a photo-electric conversion sensor unit and a control unit of a prior art contrast control type photo-electric converter. Numerals 401 - 401n denote NPN transistors which function as photo-sensing elements, numerals 402 - 402n denote switching transistors for resetting base electrodes of the NPN transistors 401 - 401n, numerals 403 - 403n denote switching transistors for resetting emitter electrodes of the transistors 401 - 401n, numerals 404 - 404n denote capacitors for storing output voltages of the transistors 401 - 401n, numerals 405 - 405n denote switching transistors for transferring the outputs of the transistors 401 - 401n which function as the photo-sensing elements to the capacitors 404 - 404n for controlling the accumulation time, numerals 406 - 406n denote switching transistors for reading out the voltages stored in the capacitors 404 - 404n, numeral 408 denotes a common output line to which the outputs are read, and numeral 409 denotes a stray capacitance of the common output line 408. Numeral 410 denotes a shift register for scanning bits, numeral 411 denotes an output buffer, numeral 412 denotes an amplifier for real-time monitoring a maximum value of the outputs of the photo-sensing transistors, numeral 413 denotes an amplifier for real-time monitoring a minimum value of the outputs of the photo-sensing transistors 401 - 401n, numeral 414 denotes an output buffer, numeral 415 denotes a differential amplifier, numerals 416, 417 and 418 denote resistors for producing desired voltages, numerals 419, 420 and 421 denote comparators, numeral 422 denotes a control circuit which receives the outputs of the comparators 419, 420 and 422 to drive the switching transistors 405 - 405n for controlling the accmulation time, numeral 423 denotes a reference voltage terminal for determining a comparison reference voltage of the comparators, numeral 424 denotes a photoelectric conversion sensor output terminal, numeral 425 denotes an accumulation time control pulse output terminal, numeral 426 denotes a sensor collector power supply terminal, numeral 427 denotes a control terminal for the switching transistors 402 - 402n, numeral 428 denotes a base reset terminal for the switching transistors 402 - 402n, numeral 429 denotes a control terminal for the switching transistors 403 - 403n, and numeral 430 denotes an emitter reset power supply terminal for the switching transistors 403 - 403n. Fig. 2 shows a timing chart of a photo-sensor reset period and an accumulation time in the prior art configuration. When pulses are applied to the terminals 425, 427 and 429, the output of the differential amplifier 415 gradually rises on real time basis from the start of accumulation in accordance with the contrast of the object, as shown in Fig. 2. Reference voltages of the comparators 419, 420 and 421 for comparing the outputs are referred to as A, B and C, and the prior art control method is explained below. Fig. 3 illustrates the control of the output voltage versus the accumulation time for explaining an operation of the prior art photo-electric converter. The output of the differential amplifier 415 shown in Fig. 1, that is, the output of the real time contrast monitor rises with the accumulation time. A time point T B is set in the accumulation time period and following five controls are conducted. 1 ○ When the output exceeds the level A before the accumulation time T B , the accumulation is terminated at that time point t 1 . 2 ○ When the output exceeds the level B at the time point T B , the accumulation is continued until the output reaches the level A, when the accumulation is terminated at that time point t 2 . 3 ○ When the output exceeds the level C at the time point T B , the accumulation is continued until the output reaches the level B, when the accumulation is terminated at that time point t 3 . 4 ○ When the output is below the level C at the time point T B , the accumulation is continued until the output reaches the level C, when the accumulation is terminated at that time point t 4 . 5 ○ When the output does not reach the level C before a preset maximum accumulation time T MAX , the accumulation is terminated at the time point T MAX . The output of the photo-electric conversion sensor is multiplied by the gain corresponding to the level A, B or C so that proper AGC is attained and the output in the predetermined range is attained without regard to the contrast of the object. The outputs of the transistors 401 - 401n which function as the photo-sensors are temporarily transferred to the accumulation capacitors 404 - 404n through the transistors 405 - 405n at the end of accumulation. Then, the shift register 410 is serially scanned to read out the content thereof to the common line 408 through the transistors 406 - 406n. The output V out in given by V out = V E · C T / (C T + C H ) where C T is the capacitance of the accumulation capacitor 404, C H is the stray capacitance 409 of the common line 408 and V E is a voltage at C T . Main components of C H are a drain capacitance of the transistor 406, a wiring capacitance of the common line 408 and an input capacitance of the output buffer 411. A gain determined by the level of the comparator is multiplied to V out in a succeeding stage processing circuit. However, in a recent AF system, a plurality of columns of photo-sensing elements are formed in one chip, different numbers of pixels are used, or different orientations are used in order to enhance the functions. Where a plurality of sensor columns each including a plurality of photo-sensing elements are arranged and the numbers of pixels of the sensor columns are different from each other, the numbers of reading switching transistors 406 are different from each other in the prior art configuration. As a result, the capacitances C H of the stray capacitors 409 are different from sensor column to sensor column. Where the photo-sensing elements are not arranged in one direction, the wiring lengths of the column line 408 are different from sensor column to sensor column. This also causes different values of C H . The fact that the values of C H are different from sensor column to sensor column means that the output voltages from the respective sensor columns are different. This causes non-uniformity in sensitivity. If the AGC is applied to such a plurality of sensor columns by the same comparator level, the non-uniformity in the sensitivity due to the different in C H is directly amplified. SUMMARY OF THE INVENTION The present invention provides photoelectric conversion apparatus as set out in claim 1. Optional features are set out in the remaining claims. An embodiment of the photoelectric convertor of the present invention comprises a plurality of sensor columns, reference voltage control means for correcting a difference between the outputs of the sensor columns, and a control block including (i) a plurality of comparators for discriminating output voltages of a plurality of photo-sensing elements of the sensor columns and (ii) an accumulation time control circuit connected to the comparators. An accumulation time controlling switching element is driven by the output of the control block to make the output accumulation time to be correlated to the output voltage of the photo-sensing element. The reference voltage control means controls comparison reference voltages applied to the comparators of the control blocks so that the respective sensor columns produce the outputs of the same level. In the embodiment, the output voltages of the photo-sensing elements of the sensor columns are discriminated by the comparators of the control block and applied to the accumulation time control circuit, and the output from the accumulation time control circuit drives the accumulation time control switching elements to make the output accumulation time to be correlated to the outputs of the photo-sensing elements. The reference voltage control means also controls the comparison reference voltages applied to the comparators of the control blocks so that the difference between the outputs of the sensor columns is corrected and the outputs of the same level are produced from the plurality of sensors. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art circuit block diagram, Fig. 2 shows a timing chart in the prior art, Fig. 3 illustrates control in the prior art, Fig. 4 shows a circuit block diagram of one embodiment of the present invention, Fig. 5 illustrates control in the embodiment, Fig. 6 illustrates control in the embodiment, and Fig. 7 shows a control block diagram of another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the photo-electric converter of the present invention is now explained. Fig. 4 shows a circuit block diagram of the present embodiment. Numerals 101 - 101n and 201 - 201m denote NPN transistors which function as photo-sensing elements, numerals 102 - 102n and 202 - 202m denote switching transistors for resetting base electrodes of the photo-sensing transistors, numerals 103 - 103n and 203 - 203m denote switching transistors for resetting emitter electrodes of the photo-sensing transistors, numerals 104 - 104n and 204 - 204m denote accumulation capacitors for accumulating the output voltages of the photo-sensing transistors, numerals 105 - 105n and 205 - 205m denote accumulation time controlling switching transistors for controlling the accumulation times of the accumulation capacitors and transferring the outputs of the photo-sensing elements to the accumulation capacitors, numerals 106 - 106n and 206 - 206m denote switching transistors for reading the voltages accumulated in the accumulation capacitors, numerals 108 and 208 denote common output lines to which the outputs are read, numerals 109 and 209 denote stray capacitances of the common output lines 108 and 208, and numerals 110 and 210 denote shift registers for scanning bits. Numerals 111 and 211 denote output buffers, numerals 112 - 112n and 212 - 212m denote amplifiers for real-time monitoring a maximum value of the outputs of 101 - 101n and 201 - 201m, numerals 113 - 113n and 213 - 213m denote amplifiers for real time monitoring a minimum value of the outputs of the photo-sensing transistors 101 - 101n and 201 - 201m, numerals 114 and 214 denote output buffers, numerals 115 and 215 denote differential amplifiers, A1 denotes a control block 1, A2 denotes a control block 2, numerals 115, 117, 118, 216, 217 and 218 denote resistors for supplying desired comparison reference voltages to the succeeding stage comparators, numerals 150 and 151 denote reference voltage controlling resistors for controlling the comparison reference voltages of the comparators, which function as reference voltage control means for correcting the difference between the outputs of the sensor columns, numerals 119, 120 and 121 denote comparators of the control block 1, numerals 219, 220 and 221 denote comparators of the control block 2, numerals 122 and 222 denote accumulation time control circuits which receive the outputs of the comparators to drive the accumulation time controlling switching transistors 105 - 105n and 205 - 205m, and numeral 123 denotes a reference voltage terminal for generating the comparison reference voltage of the comparator. Numerals 124 and 224 denote photo-electric conversion sensor output terminals, numerals 125 and 225 denote accumulation time control pulse output terminals, numeral 126 denotes a sensor collector power supply terminal, numeral 127 denotes a control terminal for the switching transistors 102 - 102n and 202 - 202m, numeral 128 denotes a base reset power supply terminal, numeral 129 denotes a control terminal for the switching transistors 103 - 103n and 203 - 203m, and numeral 130 denotes an emitter reset power supply terminal. The two sensor columns of the circuit configuration shown in Fig. 4 are formed on one chip to form a photo-electric converter. An operation of the present embodiment is now explained. The NPN transistor 101 which functions as a photo-sensing element transfers a voltage corresponding to an illumination of an object to the accumulation capacitors 104 - 104n and 204 - 204m. The photo-sensing transistors 101 - 101n and 201 - 201m form first sensor and second sensor which are separate photo-sensors, and the numbers n and m of the photo-sensing elements may be equal to or different from each other. The orientations of the sensor columns may be same or different. The output control between the sensor columns is now explained. The stray capacitance 109 of the common read line 108 of the first sensor column is represented by C H1 , the stray capacitance of the common read line 208 of the second sensor column is represented by C H2 and the capacitance of the accumulation capacitors 104 and 204 is represented by C T . The output voltage of the photosensing element of the first sensor column, that is, the voltage stored in the accumulation capacitor is represented by V E1 and the output voltage of the photosensing element of the second sensor column, that is, the voltage stored in the accumulation capacitor is represented by V E2 . Thus, voltages V out1 and V out2 at the output terminals 124 and 224 of the sensor columns are represented by V out1 =V E1 · C T / (C T + C H1 ) V out2 =V E2 · C T / (C T + C H2 ) Since V E1 and V E2 are controlled to appropriate preset values by comparing the outputs of the real time contrast monitors 115 and 215 with the comparison reference voltages by the comparators in the control block 1 and the control block 2 shown in Fig. 4, there is a difference between V out1 and V out2 due to the difference between C H1 and C H2 if V E1 = V E2 . Since C H1 and C H2 are determined by the numbers of pixels and the wiring lengths in the respective sensor columns, it has been impossible in the prior art to perfectly match them. Accordingly, in the system in which V E1 and V E2 are determined by the same comparator configuration, it is not possible to make the outputs V out1 and V out2 equal. In the embodiment of the present invention, the comparison reference voltages of the comparators of the control block 1 and the control block 2 are made different from each other based on C H1 and C H2 which are previously determined by calculation so that V E1 and V E2 which cause V out1 = V out2 are obtained. Specifically, a tailoring resistor 150 is added on the resistors 116 - 118 of the control block 1 and a reference voltage tailoring resistor 151 is added on the resistors 216 - 218 to set the comparison reference voltages to be applied to the comparators such that they meet the above condition. Namely, the relation of V out1 = V out2 is attained by selecting R1 and R2 to meet a relation of C T · R 2 /(C T + C H1 ) = C T · R 1 / (C T + C H2 ) where R1 is the resistance of the reference voltage tailoring resistor 150 of the control block 1 and R2 is the resistance of the reference voltage tailoring resistor 151 of the control block 2. Figs. 5 and 6 explain the control. When C H1 > C H2 , C T /(C T + C H1 ) < C T /(G + C H2 ) is met. Thus, if V E1 = V E2 , then V out1 < V out2 . Accordingly, the reference voltage tailoring resistors of the control block 1 and the control block 2 are selected to meet a relation of R1 < R2 to make the comparison reference voltages to meet a relation of A1 > A2, and the accumulation times t 1 and t 2 which produce V E1 and V E2 to meet the relation of V out1 = V out2 are selected. In this manner, the output levels from the plurality of sensor columns are made equal. Fig. 7 shows a control block diagram of another embodiment of the present invention. The reference voltage tailoring resistors R1 and R2 in Fig. 6 are eliminated and reference voltage generators 401 and 402, a control block 1 and a control block 2 are added as the reference voltage control means so that reference voltages having adjusted for the difference between the stray capacitances C H1 and C H2 of the common read line is internally generated without being externally supplied. Other configuration is identical to that of the previous embodiment. The present embodiment offers the same advantages as those of the previous embodiment and eliminates the necessity for externally supplying the reference voltage. In the present embodiment, two sensor columns are used. Where more than two sensor columns are used, the same advantages may be attained by correcting the comparison reference voltages in the same manner. While the control blocks and the sensor columns are on the same chip in the embodiment, they may be on different chips to attain the same advantages. In accordance with the present embodiment, the output voltages of the photo-sensing elements of the sensor columns are discriminated by the comparators of the control blocks and applied to the accumulation time control circuit, and the accumulation time controlling switching elements are driven by the output from the accumulation time control circuit to make the output accumulation times to be correlated to the outputs of the photo-sensing elements. Thus, the present embodiment can be applied to a low contrast object. The reference voltage control means controls the comparison reference voltages applied to the comparators of the control blocks to correct the difference between the outputs of the sensor columns. Accordingly, the photo-electric converter of the present embodiment can produce the outputs of the same level from the sensors without regard to the difference in the characteristics of the sensor columns such as the difference in the numbers of photo-sensing elements, the difference in wiring lengths and the difference in the orientations of the sensor columns.

Claims: Photoelectric conversion apparatus comprising: at least first and second arrays of photoelectric conversion cells (101;201); and control means (A1,A2), the first and second arrays of photoelectric conversion cells having respective readout circuits (106 to 111; 206 to 211) with different properties from each other causing an effect on signal levels so that the same signal level output from respective cells of the first and second arrays results in different signal levels output from the respective readout circuits of the first and second arrays, and the control means being arranged to generate or receive first and second reference signals corresponding to the respective different properties of the readout circuits of the first and second arrays, and controlling the accumulation times of the cells of the arrays in accordance with the reference signals so as to compensate for the said effect on signal levels of the said different properties of the respective readout circuits. Apparatus as claimed in claim 1 in which the said different properties of the respective readout circuits (106 to 111; 206 to 211) comprise different capacitances. Apparatus as claimed in claim 1 or claim 2 in which the first and second arrays comprises capacitor means (104;204) between the photoelectric conversion cells (101;201) and the readout circuits (106 to 111; 206 to 211). Apparatus as claimed in claim 3 in which the readout circuits comprises respective output lines (108;208) and switching transistors (106;206) between the output lines and the capacitor means (104;204). Apparatus as claimed in any one of the preceding claims in which the control means comprises comparator means (119,120,121;219,220,221) for comparing the signal level output by the cells of the respective arrays with respective comparison levels obtained from the respective reference signals, and the control means controls the accumulation times of the cells of the arrays in accordance with the comparison results. Apparatus as claimed in claim 5 in which the control means comprises resistor means (150;151) for receiving a common reference signal and deriving the first and second reference signals therefrom. Apparatus as claimed in claim 5 in which the control means comprises voltage source means (401;402) for generating the first and second reference signals. Apparatus as claimed in any one of claims 5 to 7 in which the control means comprises resistor means (116,117,118;216,217,218) for generating a plurality of comparison levels from the reference signals. Apparatus as claimed in any one of the preceding claims in which the first and second arrays are formed on a common substrate.

Inventors: FURUKAWA TATSUO, FURUKAWA, TATSUO, FURUKAWA, TATSUO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1992
Main classification: H04N3
IPC codes: H04N5, G03B13, H04N3, G02B7