Arbiter with a uniformly partitioned architecture

Abstract: A multiple-input arbiter first mutually correlates groups of input signals for identifying a particular group, which includes at least one input signal that is a candidate for gaining the overall priority. Thereupon the priority winner is determined in that particular group. Such a hierarchical processing lends itself to an architecture wherein the processing in groups is implemented by cascaded levels of uniform logic blocks. The decomposition in uniform logic blocks considerably simplifies the design of arbiters that process large numbers of input signals.

Description: The invention relates to an arbiter comprising: an input for receiving a plurality of input signals; mutual exclusion means for determining relative priorities between input signals within all possible respective pairs of input signals; prioritizing means for assigning priority to a particular input signal (S 1 , S 2 ,..) on the basis of the relative priorities. An arbiter is a well known interface circuit that controls a communication protocol on the basis of assigning priority to a particular input signal selected from a plurality of input signals in order to determine a processing sequence for the input signals. The priority assignment may be based on temporal aspects of the signal, e.g., the order of arrivals at the arbiter's inputs. Assigning a priority to the particular input signal is then to be understood as selecting the particular input signal on the basis of its temporal characteristics with respect to the temporal characteristics of the other input signals, e.g., the particular input signal is the first to have arrived and determines the further processing. Typically, arbiters are used for controlling the communication between transmitting stations and receiving stations interconnected via a bus system. U.S. Patent 4,835,422 issued to Dike et al., discusses an electronic arbiter circuit with an input section that provides relative priority signals upon receiving a plurality of input signals. Each respective relative priority signal specifies which one of a respective pair of input signals has gained priority over the other input signal. The relative priority signals associated with all pairs of input signals are supplied to a decode logic circuit. The decode logic circuit operates on the relative priority signals in order to furnish output signals specifying an absolute priority of a particular one of the input signals. That is, the output signals indicate which one of the input signals is considered to have gained priority over all other input signals. In addition, the decode logic circuit takes care of priority conflicts that may occur at the level of the relative priority signals. A priority conflict is an event wherein, for example, three or more input signals arrive substantially simultaneously within the resolution of the electronics and the delay paths involved. Such an event gives rise to inconsistencies. For example, the relative priority signals may indicate that the respective input signals at first, second and third input terminals respectively gained priority over the input signals at the second, third and first input terminals. Assuming that one of these input signals indeed was the first to arrive overall, such a cyclic relationship does not give an unambiguous absolute priority winner. The decode logic circuit is designed to resolve the conflict by selecting in a predetermined manner one of the input signals, which was involved in causing the conflict, as the absolute priority winner. The design of the decode logic circuit for conventional arbiters rapidly becomes increasingly complicated when the number of input signals is raised. This is due, among other things, to the growing number of logic combinations of the input signals that should be taken into account when anticipating all priority conflicts possible. From US 4,395,753 and from the IBM technical disclosure bulletin Vol. 27, No.10B (March 1985) pages 5978 to 5981 it has been known to use a hierarchical architecture to solve complexity problems in an arbiter. However, these solutions require a predetermined ranking of the priorities of the input signals and are therefore less fair than a solution based on relative priorities. These publications provide no suggestion how a hierarchical scheme can be applied to relative priorities. It is an object of the invention to provide an arbiter which uses relative priorities and has a simpler design than the known arbiters, and that therefore is simpler to fabricate. It is a further object to provide a general concept for the architecture of multiple-input arbiters which use relative priorities. The arbiter according to the invention is characterized in that the prioritizing means comprise correlating means for determining further relative priorities between groups of input signals within at least one respective pair of groups, on the basis of the relative priorities; assigning means for assigning priority to a specific group on the basis of the further relative priorities and for assigning priority to the particular input signal from the specific group on the basis of the relative priorities of the input signals in the specific group. The arbiter in the invention first mutually correlates groups of input signals for identifying the particular group, which includes at least one input signal that is a candidate for gaining the overall priority. Thereupon, the priority winner is determined in that particular group. It is explained below that such a hierarchical architecture, wherein the decode logic circuitry is distributed, considerably simplifies the logic structure of the arbiter. The hierarchical architecture is preferably implemented with a plurality of uniform and simple decode logic blocks. BRIEF DESCRIPTION OF THE DRAWING The invention will be explained below by way of example and with reference to the accompanying drawing in which: Fig. 1 shows a block diagram of an arbiter according to the invention, Fig. 2 shows an example of a basic decode logic block, defined below as a "4-block", for an arbiter of the invention, and Fig. 3 shows a detailed example of an 8-input arbiter in accordance with the invention. DETAILED DESCRIPTION DEFINITIONS The following notation is used in the explanation below. The indication "S p " is shorthand for an input signal identified by subscript number "p". The expression "p/q" stands for: input signal S p has gained priority over input signal S q . The representation "p/{k, l, m}" indicates the logic relationship: p/k AND p/l AND p/m. That is, S p has gained priority over the set of input signals S k , S l and S m . Similarly, "{p, q}/{k, l, m}" stands for: p/{k, l, m, q} OR q/{k, l, m, p}. That is, either S p has gained priority over S q , S k , S l and S m , or S q has gained priority over S p , S k , S l and S m . An N-block is defined as a function that operates on signals: 1/2, 1/3, ..., 1/N, 2/1, 2/3, ..., 2/N, ..., (N-2)/(N-1), (N-2)/N, (N-1)/N, and that supplies output signals: 1/{2, 3, ..., N}, 2/{1, 3, ..., N}, ..., N/{1, 2, ..., (N-1)}. In other words, an N-block is a function that operates on information that specifies the mutual relative priority in pairs of signals, and furnishes information regarding a unique priority winner among the signals. An implementation of an N-block is the basic building block for the decode circuitry in the arbiter of the invention. The architecture of an arbiter according to the invention is based on a decomposition of the input signals by distributing the input signals over sub-sets of equal size with the size of the sets doubling (and therefore the number of sets being halved) at each successive level in the decomposition. At the intermediate decomposition levels, the priority relations on the sets are decoded in a way similar to the way wherein the priority relations on the input signals themselves are decoded at the first level. This hierarchical decomposition is explained below. ANALYSIS As an example, assume that among a set of sixteen input signals S 1 -S 16 to be processed by a 16-input arbiter, the input signal S 5 is the overall priority winner. In accordance with above definitions, the expression: i) 5/{1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16} is valid, and is equivalent to: ii) {1, 2, 3, 4, 5, 6, 7, 8}/{9, 10, 11, 12, 13, 14, 15, 16} AND {5, 6, 7, 8}/{1, 2, 3, 4} AND {5, 6}/{7, 8} AND 5/6. It is explained below how the terms in expression ii) are generated by starting out with the mutual priority signals of the form p/q. The mutual priority signals p/q are created by applying the input signals S 1 -S N in pairs to mutual exclusion elements. A number of N input signals requires N 2 /2 mutual exclusion elements. An example of such a mutual exclusion element for a electronic arbiter is described in US Patent 4,835,422 mentioned above. For the sake of brevity, only one of the signal paths is explored. The signal processing involved in the other signal paths is similar to the one reviewed below. First of all, mutual priority signals are generated that subsequently are processed in groups by a 4-block in a first level of 4-blocks operating in parallel. For instance, tracing the mutual priority signals: iii) 5/6; 6/5; 5/7; 7/5; 5/8; 8/5; 6/7; 7/6; 6/8; 8/6; 7/8 and 8/7, results into: iv) 5/{6, 7, 8}; 6/{5, 7, 8}; 71{5, 6, 8} and 8/{5, 6, 7} For each 4-block, the associated results are supplied in pairs to two OR gates. For the results under iv) the following contributions are furnished at the outputs of the OR gates: v) 5/{6, 7, 8} OR 6/{5, 7, 8} = {5, 6}/{7, 8}, and vi) 7/{5, 6, 8} OR 8/{5, 6, 7} = {7, 8}/{5, 6}. Among the output signals of the OR gates, associated with the other 4-blocks in the first level, the following contributions are also provided that all have originated in a similar way: vii) {7, 8}/{9, 10}; {9, 10}/{7, 8}; {5, 6}/{9, 10}; {9, 10}/{5, 6}; {7, 8}/{11, 12}; {11, 12}/{7, 8}; {5, 6}/{11, 12}; {11, 12}/{5, 6}; {9, 10}/{11, 12}; and{11, 12}/{9, 10}. Together with {5, 6}/{7, 8} and {7, 8}/{5, 6}, the contributions under vii) are supplied to a further 4-block at a second level. The following four combinations appear at the further 4-block's output: viii) {5, 6}/{7, 8, 9, 10, 11, 12} {7, 8}/{5, 6, 9, 10, 11,12} {9, 10}/{5, 6, 7, 8, 11, 12} {11, 12}/{5, 6, 7, 8, 9, 10} Supplying pairs of the combinations under viii) to a pair of OR gates gives the following entities: ix) {5, 6}/{7, 8, 9, 10, 11, 12} OR {7, 8}/{5, 6, 9, 10, 11, 12} = {5, 6, 7, 8}/{9, 10, 11, 12}, and x) {9, 10}/{5, 6, 7, 8, 11, 12} OR {11, 12}/{5, 6, 7, 8, 9, 10} = {9, 10, 11, 12}/{5, 6, 7, 8}. Likewise, other 4-blocks in the second level and the associated OR gates give rise to other entities: xi) {1, 2, 3, 4}/{5, 6, 7, 8} {5, 6, 7, 8}/{1, 2, 3, 4} {1, 2, 3, 4}/{9, 10, 11, 12} {9, 10, 11, 12}/{1, 2, 3, 4} {1, 2, 3, 4}/{13, 14, 15, 16} {13, 14, 15, 16}/{1, 2, 3, 4} {5, 6, 7, 8}/{13, 14, 15, 16} {13, 14, 15, 16}/{5, 6, 7, 8} The twelve entities under ix), x) and xi) are supplied to a particular 4-block in a third level of parallel operating 4-blocks, thereby giving rise to the compositions: xii) {1, 2, 3, 4}/{5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16} {5, 6, 7, 8}/{1, 2, 3, 4, 9, 10, 11, 12, 13, 14, 15, 16} {9, 10, 11, 12}/{1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15, 16} {13, 14, 15, 16}/{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12} In turn, the compositions under xii) are combined in OR gates, resulting in the following compounds: xiii) {1, 2, 3, 4}/{5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16} OR {5, 6, 7, 8}/{1, 2, 3, 4, 9, 10, 11, 12, 13, 14, 15, 16} = {1, 2, 3, 4, 5, 6, 7, 8}/{9, 10, 11, 12, 13, 14, 15, 16}, and xiv) {9, 10, 11, 12}/{1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15, 16} OR {13, 14, 15, 16}/{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12} = {9, 10, 11, 12, 13, 14, 15, 16}/{1, 2, 3, 4, 5, 6, 7, 8}. At this point referring to expressions v), xi) and xiii), it has been shown that all terms of expression ii) have been generated using successive levels of functionally uniform 4-blocks and OR gates. Combining the individual terms by means of logic AND gates eventually produces output signal i), indicating that input signal S 5 is the unique overall priority winner. Note that the construction of the information items to be combined in order to select a unique overall priority winner can be simplified further. The last layer of OR gates used for creating the compounds under xiii) and xiv) is actually not necessary. It is readily seen that expression i): i) 5/{1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16} is equivalent to: xv) {5, 6, 7, 8}/{1, 2, 3, 4, 9, 10, 11, 12, 13, 14, 15, 16} AND (5, 6}/{7, 8} AND 5/6. Note that the operation of a 4-block is uniform regardless of its position relative to other 4-blocks in the signal path. Accordingly, an arbiter in the invention is preferably implemented using functionally and even physically uniform N-blocks and uniform OR gates. Such an N-block preferably is optimized regarding speed or power consumption. BLOCK DIAGRAM Fig. 1 illustrates the general concept of the preferred embodiment of an arbiter in the invention. The block diagram of Fig. 1 shows the arbiter with a section 10 having a plurality of mutual exclusion elements and with a signal path comprising correlating units, such as 20, 30 and 40, interconnected by means of layers of OR gates arranged in parallel, such as layer 50 and 60. The correlation units 20, 30 and 40 are distributed along the signal path and largely function as the decode logic block in the prior art mentioned above. Correlating units 20 and 30 each include a parallel arrangement of N-blocks (not shown), whereas correlating unit 40 has a single N-block (not shown). The input of each correlating unit 20, 30 and 40, and the output of correlating unit 40 are coupled to an arrangement of AND gates 70. Operation of the arbiter is discussed by way of example with reference to the analysis above for the processing of sixteen input signals S 1 -S 16 . For this example, the N-blocks specified above are considered to be 4-blocks. A number of one hundred and twenty-eight mutual exclusion elements 10 receive input signals S 1 -S 16 and provide two-hundred-and-fifty-six output signals of the form p/q as under iii) above. These output signals are supplied to both AND gate arrangement 70 and first correlating unit 20 that comprises_twenty-eight 4-blocks (not shown) operating in parallel. A first one of these 4-blocks deals with input signal group 1-2-3-4, a second one with 1-2-5-6, a third one with 1-2-7-8, etc. First correlating unit 20 creates output results of the form p/{q, r, s}, plus permutations, as under iv). These results are transferred to a arrangement 50 of fifty-six 2-input OR gates operating in parallel in order to create contributions of the form {p, q}/{r, s} as under v)-vii) above. The contributions obtained are supplied to AND gate arrangement 70 and to second correlating unit 30 that comprises six 4-blocks operating in parallel in order to generate combinations of the form {p, q}/{r, s, t, u, v, w} as under viii). The combinations are then supplied to a OR gate arrangement 60 having twelve 2-input OR gates (not shown) arranged in parallel. OR gate arrangement 60 produces entities of the form {p, q, r, s}/{t, u, v, w} as under ix)-xi). The entities are routed to AND gate arrangement 70 and to correlating unit 40 that comprises a single 4-block. Correlating unit 40 creates compositions of the form {p, q, r, s}/{a, b, c, d, e, f, g, h, i, j, k, l} as under xii). These compositions are supplied to AND gate arrangement 70. AND gate arrangement 70 performs the logic calculations as under xv) in order to furnish output signals at output 80 that unambiguously specify the overall priority winner. 4-BLOCK Fig. 2 shows a example of a 4-block for use in the decode logic circuit of an arbiter in the invention. Such a 4-block is substantially known from Fig. 9 of US Patent 4,835,422, cited above and incorporated herein by way of reference. The 4-block is designed to embody an encoding pattern that activates one and only one of the outputs G 1 , G 2 , G 3 and G 4 at a time. DETAILED 8-INPUT ARBITER Fig. 3 shows a 8-input arbiter in accordance with the invention for the processing of input signals S 1 -S 8 . The arbiter comprises a set 110 of twenty-eight mutual exclusion elements for generating fifty-six mutual priority signals for all possible paired combinations of input signals having the form p/q and q/p (p and q have the values 1, 2, ..., 8 in this example). The mutual priority signals are supplied to a first correlating unit 120 and to an AND gate arrangement 180. First correlating unit 120 comprises six 4-blocks arranged in parallel. Each respective 4-block processes the twelve mutual priority signals associated with a respective quadruplet of input signals, as is indicated in each 4-block. For instance, 4-block "1-2-7-8" handles the mutual priority signals corresponding to the quadruplet of input signals S 1 , S 2 , S 7 and S 8 . The four output signals of each 4-block indicate which one of the input signals in the associated quadruplet is a relative priority winner within the collection. These output signals then are supplied to an arrangement 150 that comprises twelve 2-input OR gates, two per 4-block. Each OR gate creates a further output signal of the form {p, q}/{r, s}, as is indicated for each individual OR gate shown. The OR gates' twelve further output signals are supplied to a correlation unit 140. Correlation unit 140 comprises a single 4-block for providing four output signals of the form {p, q}/{r, s, t, u, v, w} that are supplied to an AND gate arrangement 180. AND gate arrangement 180 logically combines the output signals p/q of section 110 and the output signals {p, q}/{r, s, t, u, v, w} of correlating unit 140 in order to generate output signals C 1 -C 8 that specify unambiguously the overall priority winner. The example analyzed above relates to an arbiter for processing a number N of input signals that equals a power of 2. An arbiter in accordance with the invention for the processing of N input signals, N not being a power of 2, is created as follows. First, consider a arbiter of the invention for handling N' input signals, N' being the smallest power of 2 that is larger than N. This arbiter has (N'-N) inputs that are never activated. These redundant inputs are represented by constants throughout the arbiter's network. That is, the network includes logic gates whose outputs do not change as a consequence of the redundant, stationary inputs. Preferably, the network is pruned by removing these stationary logic gates from the network. In a IC embodiment, for instance, the pruning saves chip area and reduces power consumption. However, the inputs of the other, dynamic logic gates, which were connected to the outputs of the stationary logic gates, are to be provided with the appropriate logic constant. In a IC this is done by, e.g., tying the relevant gate input to a constant voltage. Alternatively, these specified dynamic logic gates are replaced by simpler logic gates that have less inputs and less components. This latter solution saves additional substrate area and reduces power consumption further. Note that, instead of the OR gates and AND gates, NOR gates and NAND gates can be used, respectively, depending on the chosen polarity of the logic involved. Above diagrams therefore are to be interpreted functionally.

Claims: An arbiter comprising: an input for receiving a plurality of input signals (S 1 , S 2 ,..); mutual exclusion means (10, 110) for determining relative priorities between input signals within all possible respective pairs of input signals (S 1 , S 2 ,..); prioritizing means (20, 50, 30, 60, 40, 80, 120, 150, 140, 180) for assigning priority to a particular input signal (S 1 , S 2 ,..) on the basis of the relative priorities; characterized in that the prioritizing means comprise correlating means (20, 50, 30, 60, 120, 150) for determining further relative priorities between groups of input signals within at least one respective pair of groups (12/34, 12/56, 12/78, 34/56, 34/78, 56/78), on the basis of the relative priorities; assigning means (80, 180) for assigning priority to a specific group (12, 34, 56, 78) on the basis of the further relative priorities and for assigning priority to the particular input signal (S 1 , S 2 ,..) from the specific group (12, 34, 56, 78) on the basis of the relative priorities of the input signals in the specific group. The arbiter of claim 1 wherein the prioritizing means (20, 50, 30, 60, 40, 80, 120, 150, 140, 180) hierarchically decompose a group (12345678) containing all the plurality of input signals into groups (1234, 5678, 12, 34, 56, 78) of decreasing size, the correlating means (20, 50, 30, 60, 120, 150) determining further relative priorities between groups within pairs (1234/5678, 12/34, 12/56, 12/78, 34/56, 34/78, 56/78) of groups of equal size, the assigning means (80, 180) hierarchically assigning priority to respective specific groups (1234, 5678, 12, 34, 56, 78), each among groups of equal size and on the basis of the relative priorities of these groups of equal size, the assigning means assigning priority to the particular input signal (S 1 , S 2 ,..) which is in each of the groups (1234, 5678, 12, 34, 56, 78) of decreasing size that is assigned priority by the assigning means. The arbiter of claim 1 or 2 wherein the correlating means comprise a plurality of decode logic blocks (4) each assigned to a respective set of input signals (S 1 , S 2 ,..) or groups (12, 34, 56, 78) of equal size, each decode logic block (4) having inputs for receiving decode input signals representing relative priorities (1/2, 1/3 ...) or further relative priorities (12/34, 12/56,) between all pairs in the respective set, each decode logic block (4) producing logic block output signals (1/{234}, 2/{134}.., 12/345678, ..) indicative of a single one of the input signals or groups of the respective set gaining priority over the other input signals or the other groups of the respective set; an arrangement of logic gates (150) having gate inputs connected to the decode logic blocks (4) for logically combining the logic block output signals (1/{234}, 2/{134},..) into a gate output signal (12/34) specifying which one of two mutually complementary subsets of the respective set has relative priority over the other, a subset having relative priority when it contains the single one of the input signals or groups that has gained priority. The arbiter of Claim 3 wherein the logic operation of each logic gate (150) includes an OR operation. The arbiter of Claim 3 wherein the assigning means comprise an arrangement of further logic gates (180), each further logic gate receiving a respective one of the logic block output signals (12/345678, .. ) of a logic block (4) assigned to a respective set of input signals (12345678), and a relative priority signal (1/2, 3/4, 5/6, 7/8). The arbiter of Claim 5 wherein the logic operation of each further logic gate (180) includes an AND operation. The arbiter of Claim 3, wherein all the decode logic blocks (4) are functionally identical. The arbiter of Claim 7, wherein each of the decode logic blocks is functionally equivalent to a circuit comprising three respective AND gates that have a respective AND output coupled to a respective input of a 3-input OR gate. The arbiter of claim 1 embodied in an integrated circuit device. The arbiter of Claim 3 wherein the decode logic blocks each comprise at least part of an integrated circuit device.

Inventors: DIKE CHARLES E, DIKE, CHARLES, Dike, Charles, c/o Internationaal Octrooibureau BV
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1992
Main classification: G06F13
IPC codes: G06F9, G06F13