Charge transfer device

Abstract: In a CCD element, the influence of a parasitic capacitance existing between a floating diffusion region and a reset gate section of an output section is suppressed to increase sensitivity. In a CCD element in which a floating diffusion region (7) is connected to the final stage of a charge transfer register (1) having a CCD structure through a horizontal output gate section (5) and a reset gate section (11) is disposed between the floating diffusion region (7) and a reset drain region (10), an output gate pulse ( HOG ) having an anti-phase of a reset pulse (RG) applied to the reset gate section (11) is applied to the horizontal output gate section (5). Further, an output waveform in a signal period in a CCD linear sensor can be made flat and a signal level difference between odd-numbered and even-numbered pixels can be improved. In a CCD linear sensor comprising a photo sensing region formed of a plurality of photo sensing elements (pixels), first and second horizontal transfer registers disposed at both sides of the photo sensing region through read-out gate sections, a floating diffusion region for alternately detecting signal charges transferred thereto from the first and second horizontal transfer registers as output signals and a reset gate section, a transfer section of the final stage portion of the first and second horizontal transfer registers is separated and phases of drive pulses (H₁'), (H₂') applied to the transfer section of the final stage portion are shifted from those of drive pulses (H₁), (H₂) applied to the preceding transfer section, whereby a noise component (36) is superimposed upon the output waveform of ON period (T R ) of the reset gate section.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to CCD (charge coupled device) linear sensor, CCD imaging devices such as a CCD linear sensor and CCD elements such as other devices utilizing CCDs or the like. Description of the Prior Art: FIG. 1 of the accompanying drawings shows a structure of a final stage portion of a horizontal transfer register of a conventional CCD imaging device and an output section thereof. Referring to FIG. 1, a horizontal transfer register 1 has a plurality of arrays of transfer sections 4 each composed of transfer electrodes, i.e., a storage electrode 3S and a transfer electrode 3T formed on a major surface of a semiconductor substrate 2 via an insulating layer, and transfers signal charges in the horizontal direction by means of two-phase drive pulses H 1 and H 2 (see FIGS. 2A and 2B). The transfer section 4 at the final stage of the horizontal transfer register 1 is connected to a floating diffusion region 7 via a horizontal output gate section 5 to which there is applied a fixed gate voltage V HOG . The signal charge from the horizontal transfer register 1 is transferred to the floating diffusion region 7, in which it is converted in the form of charge to voltage and then output from an output amplifier 8. In an output section 9, a reset gate section 11 to which a reset pulse RG (see FIG, 2C) is applied is formed between the floating diffusion region 7 and a reset drain region 10 in order to drain out the signal charge transferred to the floating diffusion region 7 to the reset drain region 10 to which there is applied a predetermined voltage V RD (see FIG. 2D). In the output section  of FIG. 1, as shown by a waveform of a potential on the floating diffusion region 7 in FIG. 2D, wnen the reset gate section 11 is turned on (when the reset pulse RG is high in level), a potential V FD of the floating diffusion region 7 becomes equal to a potential V RD of the reset drain region 10 (V FD = V RD ). However, a parasitic capacitance C 1 exists between the floating diffusion region 7 and the reset gate section 11 so that, after the reset gate section 11 is turned off, the potential V FD of the floating diffusion region 7 does not equal to the potential V RD of the reset drain region 10 due to a capacitive coupling of the parasitic capacitance C1 and becomes lower than the potential V RD (V FD < V RD ). Considering this phenomenon from a waveform of a CCD output shown in FIG. 2E, after the reset gate section 11 is turned off, the CCD output becomes a potential (i.e., field-through potential) b which is lower than a reference potential (i.e., reset potential) a . A difference between the reference potential a and the field-through potential b is rendered a so-called coupling amount A 1 which is caused by the parasitic capacitance C 1 . It is desirable that the parasitic capacitance C 1 is reduced in proportional to a capacity associated with the floating diffusion region 7 as the CCD imaging device is increased in sensitivity. More specifically, if the parasitic capacitance C 1 is not reduced, then the coupling amount A 1 is relatively increased, resulting in a dynamic range of a signal component being reduced. As shown in a diagram of potentials in FIG. 3, the potential in the floating diffusion region 7 after the reset gate section 11 is turned off is lowered (shown by a solid line) from the potential V RD (shown by a dashed line) of the reset drain region 10. As a result, signal charges are difficult to be transferred to the floating diffusion region 7 and the amount of signal charges to be transferred is reduced. A potential difference B 1 in FIG. 3 corresponds to the coupling amount A 1 in the waveform of the CCD output. Furthermore, in order to obtain a higher resolution, a CCD linear sensor is arranged such that signal charges of odd-numbered photo sensing elements (pixels) and even-numbered photo sensing elements (pixels) are transferred to two charge transfer registers in a divided fashion and then output from the final stage in the mixed form. As shown in FIG. 4, first and second horizontal transfer registers 24 and 25 each being formed of a CCD are disposed on respective sides of a photo sensing region 21 having an array composed of a plurality of photo sensing elements (pixels) S (S 1 , S 2 , S 3 , ...) through read-out gate sections 22 and 23. Signal charges of the odd-numbered photo sensing elements S 1 , S 3 , S 5 , ..., are read out to the first horizontal transfer register 24 and signal charges of the even-numbered photo sensing elements S 2 , S 4 , S 6 , ... are read out to the second horizontal transfer register 25. Then, signal charges are transferred in one direction by two-phase drive pulses H 1 , H 2 and H 1 ', H 2 ' shown in FIGS. 5A and 5B, respectively. Transfer sections HR 1 , HR 2 of the final stages are applied with independent drive pulses H 1 ', H 2 ' which are synchronized with the drive pulses H 1 , H 2 supplied to preceding transfer sections HR 1 , HR 2 . The transfer sections HR 1 , HR 2 provided at the final stages of the first and second horizontal transfer registers 24, 25 are connected to a common floating diffusion region 27 via a common horizontal output gate section 26 to which there is applied a gate voltage V HOG . Then, signal charges read out from the even-numbered and even-numbered photo sensing elements and transferced by the first and second horizontal transfer registers 24, 25 are added together by the floating diffusion region 27, that is, the odd-numbered and even-numbered signal charges are alternately transferred to the common floating diffusion region 27, in which they are converted in the form of charge to voltage and then signals corresponding to odd-numbered and even-numbered pixels are sequentially and alternately output from an output amplifier 28 as shown by a waveform of a CCD output in FIG. 5D. In this output section, the signal charges transferred to the floating diffusion region 27 are discharged to a reset drain region 30 through a reset gate section 29 by a reset pulse RG which is supplied thereto and whose frequency is twice as high as those of the two-phase drive pulses H 1 , H 2 and H 1 ', H 2 ' as shown in FIG. 5C. In the CCD linear sensor, large capacitances of the first and second transfer sections HR 1 , HR 2 in the horizontal transfer registers 24, 25 are driven by the drive pulses H 1 , H 2 so that noise components caused by such capacitances are superimposed upon the output signal. Consequently, the waveform of the CCD output during the signal period, for example, is fluctuated. Further, when signal charges are read out by the two horizontal transfer registers 24 and 25, a difference known as "DC level difference" occurs between the signal level of the odd-numbered pixel (photo sensing element) and that of the even-numbered pixel (photo sensing element). In the output section, the floating diffusion region 27 is formed within a well region and the well region is interconnected to the ground. In that event, the capacitance of the transfer sections HR 1 , HR 2 is large so that, when the horizontal transfer registers 24, 25 are driven by the two-phase drive pulses H 1 , H 2 , a well region potential (so-called reference potential) Vo is momentarily fluctuated at negative-going edges t 1 , t 2 , t 3 , ... of the drive pulse H 1 or H 2 which transfers the signal charges to the floating diffusion region 27 as shown in Fig. 5, to thereby produce a fluctuated component 15. Consequently, a noise component 16 is superimposed upon the output signal on the basis of this fluctuated component 15. Thus, the waveform during the signal period is not flat. Further, since the capacitance of the first transfer section HR 1 is different from that of the second transfer section HR 2 , the noise component 16 is changed, thereby resulting in a difference (so-called DC level difference) being produced in the signal level of the odd-numbered pixel and that of the even-numbered pixel. This signal level difference becomes conspicuous because the resolution of the CCD linear sensor is increased more and more. Therefore, each of the pixels must be corrected, which is very cumbersome in the prior art. Prior art document EP-A-0 140 292 discloses a solid-state image sensor which has an electrically floating carrier detecting electrode formed on a substrate, into which the signal carriers are transmitted, a sense amplifier circuit detecting the variation in a voltage of the electrode at the time of transferring the carriers, and a resetting electrode for resetting the potential of the electrode to a predetermined potential at every read-out period of the picture element section. A circuit arrangement for removing noise has two switches which switch to alternatively become conductive in response to control pulse signals. The first switch becomes conductive during a first period within one picture element period. During the first period the CCD output signal contains an effective image signal component. The second switch becomes conductive during a second period during which the CCD output signal contains a reset noise component, thereby forcibly fixing the level of the reset noise signal to a DC reference potential so that reset noise can be removed. OBJECTS AND SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved CCD imaging device in which the aforesaid shortcomings and disadvantages encountered with the prior art can be eliminated. More specifically, it is an object of the present invention to provide a CCD imaging device in which a coupling amount caused by a capacitance between a reset gate section and a floating diffusion region can be reduced. Another object of the present invention is to provide a CCD imaging device which can be improved in sensitivity. A further object of the present invention is to provide a CCD imaging device in which a waveform in a signal period can be made flat. Yet a further object of the present invention is to provide a CCD imaging device in which a difference between signal levels of pixels can be improved. Still a further object of the present invention is to provide a CCD imaging device which can produce image quality of high resolution without correcting a black signal. To solve this object the present invention provides a charge transfer device as specified in claim 1. Said charge transfer device is driven in accordance with the method specified in claim 5. A charge transfer device formed on a semiconductor substrate is comprised of a charge detecting section including an electrically floating diffusion region, a floating diffusion amplifier connected to the floating diffusion region, and a transistor responsive to a reset pulse voltage signal for resetting the floating diffusion region to a predetermined potential, the transistor comprising the floating diffusion region, a drain diffusion region formed in the substrate, a gate electrode connected to a source of the pule voltage signal, and a channel formed on the substrate, the channel extending between the floating diffusion region and the drain diffusion region, and charge transfer section for transferring charges to the charge detecting section, a the charge transfer section including a channel formed on the substrate, a plurality of gate electrodes insulated from the channel, and an output gate electrode formed on an end of the charge transfer section, the plurality of gate electrodes being responsive to a driving pulse voltage signal, wherein the driving pulse voltage signal having a specific phase so that a noise generated by a voltage shift of the driving pulse voltage signal overlaps on an output signal corresponding to a reset period. A solid state linear imaging device formed on a semiconductor substrate is comprised of a plurality of photo sensing elements receiving a light and producing a charge signal corresponding to the amount of light, and a charge transfer section for receiving the charge signal from the photo sensing elements and transferring the charge signal to a charge detecting section, the charge detecting section including an electrically floating diffusion region, a floating diffusion amplifier connected to the floating diffusion region, and a transistor responsive to a reset pulse voltage signal for resetting the floating diffusion region to a predetermined potential, the transistor comprising the floating diffusion region, a drain diffusion region formed in the substrate, a gate electrode connected to a source of the pulse voltage signal, and a channel formed on the substrate, the channel extending between the floating diffusion region and the drain diffusion region, the charge transfer section including a channel formed on the substrate, a plurality of gate electrodes insulated from the channel, and an output gate electrode formed on an end of the charge transfer section, the plurality of gate electrodes being responsive to a driving pulse voltage signal, and the driving pulse voltage signal having a specific phase so that a noise generated by a voltage shift of the driving pulse voltage signal overlaps on an output signal corresponding to a reset period. A charge transfer device formed on a semiconductor body comprises of a charge detecting section including an electrically floating diffusion region, a floating diffusion amplifier connected to the floating diffusion region and a transistor responsive to a reset pulse voltage signal for resetting the floating diffusion region to a predetermined potential, the transistor comprising the floating diffusion region, a drain diffusion region formed in a substrate, a gate electrode connected to a source of the reset pulse voltage signal, and a channel formed on the substrate, the channel extending between the floating diffusion region and the drain diffusion region; and a charge transfer section for transferring charges to a charge detecting section, the charge transfer section including a channel formed on the substrate, a plurality of gate electrodes insulated from the channel, and an output gate electrode formed on an end of the charge transfer section, the gate electrodes consisting of a first portion responsive to a first driving pulse voltage signal and a second portion responsive to a second driving pulse voltage signal, the second portion being adjacent to the output gate electrode, wherein the first driving pulse voltage signal has a specific phase so that a noise generated by a voltage shift of the first driving pulse voltage signal overlaps on an output corresponding to a reset period. A solid state linear imaging device formed on a semiconductor substrate comprises a plurality of photo sensing elements receiving a light and producing a charge signal corresponding to the amount of light, and a charge transfer section for receiving the charge signal from the photo sensing elements and transferring the charge signal to a charge detecting section, the charge detecting section including an electrically floating diffusion region, a floating diffusion amplifier connected to the floating diffusion region, and a transistor responsive to a reset pulse voltage signal for resetting the floating diffusion region to a predetermined potential, the transistor comprising the floating diffusion region, a drain diffusion region formed in the substrate, a gate electrode connected to a source of the reset pulse voltage signal, and a channel formed on the substrate, the channel extending between the floating diffusion region and the drain diffusion region, the charge transfer section including a channel formed on the substrate, a plurality of gate electrodes insulated from the channel, and an output gate electrode formed on an end of the charge transfer section, the gate electrodes consisting of a first portion responsive to a first driving pulse voltage signal and a second portion responsive to a second driving pulse voltage signal, the second portion being adjacent to the output gate electrode, wherein the first driving pulse voltage signal has a specific phase so that a noise generated by a voltage shift of the first driving pulse voltage signal overlaps on an output signal corresponding to a reset period. A charge transfer device formed on a semiconductor body comprises a charge detecting section including an electrically floating diffusion region, a floating diffusion amplifier connected to the floating diffusion region and a transistor responsive to a reset pulse voltage signal for resetting the floating diffusion region to a predetermined potential, the transistor comprising the floating diffusion region, a drain diffusion region formed in a substrate, a gate electrode connected to a source of the pulse voltage signal, and a channel formed on the substrate, the channel extending between the floating diffusion region and the drain diffusion region, and a charge transfer section for transferring charges to a charge detecting section, the charge transfer section including a channel formed on the substrate, a plurality of gate electrodes insulated from the channel, and an output gate electrode formed on an end of the charge transfer section, the output gate electrode being responsive to an output gate pulse voltage signal, and the output gate pulse voltage signal having an anti-phase of the reset pulse voltage signal. The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof to be read in conjunction with the accompanying drawings, in which like reference numerals are used to identify the same or similar parts in the several views. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a fragmentary side view of a structure of a main portion of a CCD imaging device according to the prior art; FIGS. 2A through 2E are respectively diagrams showing waveforms of pulses applied to the CCD imaging device and waveform of an output from the CCD imaging device according to the prior art; FIG. 3 is a diagram of potential developed in the output section according to the prior art; FIG. 4 is a fragmentary plan view of a structure of a CCD linear sensor according to the prior art; FIGS. 5A through 5E are respectively diagrams of waveforms of pulses supplied, a waveform of a CCD output or the like according to the prior-art CCD linear sensor; FIG. 6 is a fragmentary side view of a structure of a final stage of a horizontal transfer register and an output section of a CCD imaging device useful for the understanding of the present invention; FIGS. 7A through 7E are respectively diagrams of waveforms of pulses applied and a waveform of a CCD output of the CCD imaging device shown in FIG. 6; FIGS. 8A through 8D are respectively diagrams of potentials developed in the horizontal charge transfer section and, to which references will be made in explaining charge transfer operation; FIG. 9 is a fragmentary plan view of a structure of a CCD imaging device according to an embodiment of the present invention; FIGS. 10A through 10E are respectively diagrams of waveforms of drive pulses, a reset pulse and a CCD output according to the embodiment of the present invention; and FIG. 11 is a block diagram showing a circuit configuration which generates pulses to be supplied according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the accompanying drawings. FIG. 6 of the accompanying drawings show a structure of a final stage of a horizontal transfer register and an output section of a CCD imaging device. In FIG. 6, elements and parts identical to those of FIG. 1 are marked with the same references and therefore need not be described in detail. Similarly to FIG. 1, this CCD imaging device comprises a horizontal transfer register 1 of CCD structure each having an array of a plurality of transfer sections 4 each of which has a storage electrode 3S and a transfer electrode 3T formed on a major surface of a semiconductor substrate 2 via an insulating layer (not shown) to sequentially transfer signal charges in the horizontal direction by the two-phase drive pulses H 1 , H 2 , a horizontal output gate section 5 connected to the final transfer section 4 of the horizontal transfer register 1, a floating diffusion region 7, an output amplifier 8 connected to the floating diffusion region 7, a reset drain region 10 and a reset gate section 11 which discharges signal charges transferred to the floating diffusion region 7 to the reset drain region 10, as shown in FIG. 6. The predetermined voltage V RD is applied to the reset drain region 10 and the reset pulse RG is applied to the reset gate section 11, respectively. As shown in FIG. 6 and FIGS. 7A to 7B, an output gate pulse  HOG having an anti-phase of that of the reset pulse  RG is applied to the horizontal output gate section 5 instead of the conventional fixed potential. Because the parasitic capacitance C 1 exists between the floating diffusion region 7 and the reset gate section 11 and a parasitic capacitance C2 also exists between the floating diffusion region 7 and the horizontal output gate section 5, the output gate pulse  HOG having the anti-phase of that of the reset pulse RG is applied to the horizontal output gate section 5, thereby suppressing a potential from being lowered in the floating diffusion region 7 after the reset gate 11 is turned off. Hence, the coupling amount A 2 in the so-called CCD output waveform can be suppressed. More specifically, when the reset gate section 11 is turned on by the application of the high level (e.g., 5V) of the reset pulse RG thereto, a potential V FD of the floating diffusion region 7 becomes equal to a potential V RD of the reset drain region 10. At that time, the low level (e.g., 0V) of the output gate pulse  HOG is applied to the horizontal output gate section 5. Then, although the potential V FD of the floating diffusion region 7 after the reset gate section 11 is turned off by the application of the low level (e.g., 0V) of the reset pulse RG is lowered by the capacitive coupling of the parasitic capacitance C 1 , the high level (e.g., 5v) of the output gate pulse  HOG is simultaneously applied to the horizontal gate section 5 so that the potential of the floating diffusion region 7 is increased by the capacitive coupling of the parasitic capacitance C 2 . Consequently, the potential in the floating diffusion region 7 after the reset gate section 11 is turned off can be suppressed from being lowered, which can reduce the coupling amount A2 in the waveform of the CCD output shown in FIG. 7E. If the parasitic capacitance C 1 and the parasitic capacitance C 2 are exactly the same value (C 1 = C 2 ) and the phase of the reset pulse RG and that of the output gate pulse  HOG are exactly opposite to each other, then the coupling amount in FIG. 7E is reduced to zero and a CCD output waveform P 1 is presented as shown by a broken line in FIG. 7E. Further, the coupling amount can be reduced if the parasitic capacitance C 1 and the parasitic capacitance C 2 are not equal. If an inequality of C 1 > C 2 , for example, is satisfied, then a CCD output waveform P 2 shown by a solid line in the coupling amount A 2 in FIG. 7E is presented. In this case, an inequality of C 1 > C 2 might be satisfied. P 3 in FIG. 7E represents a conventional CCD output waveform obtained in FIG. 1 for comparison. While the amplitudes of the output gate pulse  HOG and the reset pulse RG are made equal as described above, the present CCD imaging device is not limited thereto and the coupling amount A 2 can be suppressed more by changing the amplitude of the output gate pulse  HOG . Transfer of signal charges will be described with reference to applied pulse waveforms of FIGS. 7A to 7D and a diagram of potentials of FIG. 8. The two-phase drive pulses H 1 and H 2 are applied to the transfer section 4 of the horizontal transfer register 1, the output gate pulse  HOG is applied to the horizontal output gate section 5 and the reset pulse RG is applied to the reset gate section 11 at timings shown in FIGS. 7A through 7D, respectively. At timing point t 11 in which the reset gate section 11 is turned on, potentials in the respective sections are set in the states shown in FIG. 8A, whereby a signal charge e 1 in the floating diffusion region 7 is discharged to the reset drain region 10 and the next signal charge e 2 is transferred to the portion beneath the storage electrode 3S of the final transfer section 4. At timing point t 12 at which the reset gate section 11 is turned off, the drive pulse H 1 is high in level and the output gate pulse  HOG goes to high level so that the potential state shown in FIG. 8B is presented. Thus, the signal charge e 2 remains in the portion beneath the storage electrode 3S of the final transfer section 4. In the next timing point t 13 , the drive pulse H 1 goes to low level, bringing about the potential state shown in FIG. 8C. Then, the signal charge e 2 of the transfer section 4 is transferred to the floating diffusion region 7 and the signal component is output from the output amplifier 8. In the next timing point t 14 , the drive pulse H 1 goes to high level, thereby presenting the potential state shown in FIG. 8D. Therefore, the next signal charge e 3 is transferred to the portion beneath the storage electrode 3S of the final transfer section 4. In this fashion, signal charges are sequentially transferred to the floating diffusion region 7 and then output from the output amplifier 8. According to the above CCD imaging device, the output gate pulse  HOG having an anti-phase of the reset pulse RG is applied to the succeeding horizontal output gate section 5 of the horizontal transfer register 1, whereby the influence of the parasitic capacitance C 1 between the reset gate section 1 and the floating diffusion region 7 can be reduced and the coupling can be reduced. Consequently, the amount of charges processed by the floating diffusion region 7 can be avoided from being reduced by the coupling amount increased by the increase of sensitivity of the CCD imaging devices such as CCD area sensor, CCD linear sensor or the like. Also, the amount of charges transferred to the floating diffusion region 7 can be avoided from being reduced. According to the above CCD imaging device, the influence of the parasitic capacitance between the floating diffusion region and the reset gate section can be suppressed and the coupling amount between the reference potential and the field-through potential in the output can be reduced, thereby keeping sufficient amount of charges processed by the floating diffusion region. Therefore, the sensitivity of the CCD imaging devices such as CCD area sensor, CCD linear sensor or the like can be improved. A CCD imaging device according to an embodiment of the present invention will be described below in detail with reference to FIG. 9 through FIGS. 10A to 10E. Also in this embodiment, the CCD imaging device is applied to the CCL linear sensor. In FIG. 9, like parts corresponding to those of FIG. 4 are marked with the same references and therefore need not be described in detail. FIG. 9 of the accompanying drawings shows a fragmentary plan view of a structure of the CCD imaging device according to the embodiment of the present invention. As shown in FIG. 9, a photo sensing region 21 has an array of a plurality of photo sensing elements S (S 1 , S 2 , S 3 ...) arranged in one direction, and first and second horizontal transfer registers 24 and 25 of CCD structure are disposed on both sides of the photo sensing region 21 through read-out gate sections 22, 23 in parallel to the photo sensing region 21. Each of the first and second horizontal transfer registers 24 and 25 has an array of a plurality of transfer sections HR (HR 1 , HR 2 ) each having a transfer electrode composed of a set of storage electrode and transfer electrode, though not shown. One drive pulse H 1 of the two-phase drive pulses is applied to the transfer electrode of every other one first transfer section HR 1 and the other drive pulse H 2 is applied to the transfer electrode of remaining every other one second transfer section HR 2 . The first transfer sections HR 1 of the first horizontal transfer register 24 are formed in association with the odd-numbered photo sensing elements S 1 , S 3 , S 5 , ..., for example, and the first transfer sections HR 1 of the second horizontal transfer register 25 are formed in association with the even-numbered photo sensing elements S 2 , S 4 , S 6 , ..., for example. Final terminals of the first and second horizontal transfer registers 24 and 25 are connected to a common detecting section, i.e., floating diffusion region 27 through a common horizontal output gate section 26 to which the gate voltage V HOG is applied. An output amplifier 28 is connected to the diffusion floating region 27. A reset gate section 29 to which the reset pulse RG is applied is formed between the floating diffusion region 27 and a reset drain region 30. According to this CCD linear sensor, similarly as described above, signal charges of the odd-numbered photo sensing elements S 1 , S 3 , S 5 , ..., read out to the first horizontal transfer register 24 and signal charges of the even-numbered photo sensing elements S 2 , S 4 , S 6 , ... are read out to the second horizontal transfer register 25. Then, the signal charges thus read out are transferred through the first and second horizontal transfer registers 24, 25 in one direction and mixed together by the floating diffusion region 27 through a horizontal output gate section 26, i.e., odd-numbered and even-numbered signal charges are alternately transferred to the floating diffusion region 27. Then, the signal charges are converted by the floating diffusion region 27 in the form of charge to voltage and signals corresponding to the odd-numbered and even-numbered pixels are alternately output through an output amplifier 28. According to the embodiment of the present invention, the final transfer section of the first and second horizontal transfer registers 24, 25, e.g., a transfer region 32 of final bit or a plurality of bits including the final bit is separated from the first and second horizontal transfer registers 24 and 25. Then, a drive pulse H 1 ' (see FIG. 10B) is applied to the first transfer section HR 1 of the final transfer region 32 and a drive pulse H 2 ' (see FIG. 10B) is applied to the second transfer section HR 2 , respectively. Further, a drive pules H 1 (see FIG. 10A) is applied to the first transfer sections HR 1 of a transfer region 33 which precedes the final stage portion of the first and second horizontal transfer registers 24, 25 and a drive pulse H 2 (see FIG. 10A) is applied to the second transfer sections HR2 in the transfer region 33, respectively. The reset pulse RG (see FIG. 10) having frequency twice those of the drive pulses H 1 , H 1 ', H 2 , H 2 ' is supplied to the reset gate section 29 similarly as described before. When the transfer region 33 having large capacitance is driven, the phases of the drive pulses H 1 , H 2 applied to the preceding transfer region 33 are shifted by Δt from those of the drive pulses H 1 ', H 2 ' such that negative-going edge t 1 or t 2 , ... of the drive pulse H1 or H2 which transfers signal charges to the succeeding transfer section HR fall within the high level period of the reset pulse RG (so-called ON period of the reset gate section 29). According to the above structure, since the phases of the drive pulse H 1 , H 2 applied to the preceding transfer region 33 are shifted by Δt from those of the drive pulses H 1 ', H 2 ' applied to the final transfer region 32 so that the negative-going edges of the drive pulses H 1 , H 2 which transfer signal charges to the next stage fall within the high level period of the reset pulse RG (so-called ON period of the reset gate section 29), a noise component 36 based on a fluctuated component 35 (see FIG. 10E) of the reference potential Vo of the well region is superimposed upon an output waveform in an ON period T R of the reset gate section 29 and can be prevented from being superimposed upon an output waveform, i.e., signal waveform of a signal period T S . Therefore, the output waveform in the signal period T S can be made flat. Further, a difference between the signal level of the odd-numbered pixel and that of the even-numbered signal level can be eliminated and the image quality of high resolution can be obtained without correcting a black signal of each pixel. An example of a circuit configuration which can shift phases between the above-mentioned drive pulses H 1 ', H 2 ' and H 1 , H 2 will be described in greater detail with reference to FIG. 11. In the case of the CCD linear sensor whose timing system is formed as an IC-chip, as shown in FIG. 11 of the accompanying drawings, the clock pulses H1', H2' for final stage and the reset pulse RG generated from a timing generator 41 are supplied to a driver circuit 42 as is. Also, a delay circuit 43 is connected to external control terminals a 1 to a n and the delay circuit 43 delays the clock pulses H 1 ', H 2 ' from the timing generator 41 to provide clock pulses H 1 , H 2 which are phase-shifted by At from the clock pulse H 1 ', H 2 '. These clock pulses H 1 , H 2 are supplied to a driver circuit 44. Since the delay amount Δt of the delay circuit 43 is changed with available frequencies, the delay amount Δt can be changed by switching voltages applied to the external control terminals a 1 to a n in a digital fashion. The phases between the drive pulses H 1 ', H 2 ' and drive pulses H 1 , H 2 are shifted as described above, whereby the influence of the transfer capacitance in the transfer region 33 in the CCD linear sensor can be reduced and the output waveform in the signal period can be made flat. Also, a difference of signal levels between the pixels can be improved. While the signal charges of the first and second horizontal transfer register 24, 25 are alternately transferred to and mixed together by the floating diffusion region 27 as described above, the present invention is not limited thereto and the following variant is also possible. That is, a transfer section of several bits which are driven by two-phase drive pulses is disposed at the front stage of the floating diffusion region 27, whereby signal charges from the first and second horizontal transfer registers 24, 25 are alternately transferred to this transfer section of several bits and mixed together. In this case, before the odd-numbered and even-numbered signal charges are added by the above transfer section, the final transfer region 32 of a plurality of bits in the first and second horizontal transfer registers 24, 25 is separated from the preceding transfer region 33 and supplied with the drive pulses H 1 ', H 2 ' and H 1 , H 2 in the above-mentioned phase-relation. Furthermore, while the present invention is applied to the CCD linear sensor having the first and second horizontal transfer registers 24, 25 as described above, the present invention is not limited thereto and the present invention can be applied to a CCD area image sensor in which signal charges of one line are read out by a plurality of horizontal transfer registers. According to the CCD imaging device of the present invention, the output waveform in the signal period can be made flat and a difference between the pixels, i.e., the signal level corresponding to the odd-numbered pixel and the signal level corresponding to the even-numbered pixel can be improved. Thus, the image quality of high resolution can be obtained without correcting the black signal. Having described a preferred embodiment of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications could be effected therein by one skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims: A charge transfer device formed on a semiconductor body comprising: a charge detecting section including an electrically floating diffusion region (7; 27), an output amplifier (8; 28) connected to said floating diffusion region (7; 27) and a transistor responsive to a reset pulse voltage signal ( RG ) for resetting said floating diffusion region (7; 27) to a predetermined potential, said transistor comprising said floating diffusion region (7; 27), a reset drain region (10; 30) formed in a substrate (2), a gate electrode (11; 29) connected to a source of said reset pulse voltage signal ( RG ), and a channel formed on said substrate (2), said channel extending between said floating diffusion region (7; 27) and said reset drain region (10; 30); charge transfer means for transferring charges to said charge detecting section, said charge transfer means including a channel formed on said substrate, a plurality of gate electrodes insulated from said channel, and an output gate electrode formed on an end of said charge transfer means; and a timing generator (41) for generating a driving pulse voltage signal (H' 1 ; H' 2 ) ; characterized in that said charge transfer device further comprises a delay circuit (43) connected to said timing generator (41) for delaying said driving pulse voltage signal (H' 1 ; H' 2 ) from said timing generator (41) to provide a further driving pulse voltage signal (H 1 ; H 2 ) which is phase shifted by At from the driving pulse voltage signal (H' 1 ; H' 2 ); said gate electrodes consist of a first portion (33) responsive to said further driving pulse voltage signal (H 1 ; H 2 ) and a second portion (32) responsive to said driving pulse voltage signal (H' 1 ; H' 2 ), said second portion (32) being adjacent to said output gate electrode, wherein said further driving pulse voltage signal (H 1 ; H 2 ) has a specific phase so that the negative going edges (t 1 , t 2 ) of said further driving pulse voltage signal (H 1 ; H 2 ) fall within a high level period of said reset pulse voltage signal ( RG ). The charge transfer device according to claim 1, wherein said transistor is active in a voltage shift period of said further driving pulse voltage signal (H 1 ; H 2 ). The charge transfer device according to claim 1, wherein said reset pulse voltage signal ( RG ) is high in level in a voltage shift period of said further driving pulse voltage signal (H 1 ; H 2 ). A solid state linear imaging device comprising: a plurality of photo sensing elements (S) receiving light and producing a charge signal corresponding to the amount of light; and a charge transfer device according to any of the preceding claims for receiving said charge signal from said photo sensing elements. A method for driving a charge transfer device of any of the claims 1 to 3, said method comprising the step of generating a driving pulse voltage signal (H' 1 ; H' 2 ) in a timing generator (41) and being characterized in that said driving pulse voltage signal (H' 1 ; H' 2 ) from said timing generator (41) is delayed to provide a further driving pulse voltage signal (H 1 ; H 2 ) which is phase shifted by Δt from the driving pulse voltage signal (H' 1 ; H' 2 ); said further driving pulse voltage signal (H 1 ; H 2 ) is applied to a first portion (33) of said gate electrodes and said driving pulse voltage signal (H' 1 ; H' 2 ) is applied to a second portion (32) of said gate electrodes, said second portion (32) being adjacent to said output gate electrode, said further driving pulse voltage signal (H 1 ; H 2 ) having a specific phase so that the negative going edges (t 1 , t 2 ) of said further driving pulse voltage signal (H 1 ; H 2 ) fall within a high level period of said reset pulse voltage signal (# RG ). The method according to claim 5, wherein said transistor is activated in a voltage shift period of said further driving pulse voltage signal (H 1 ; H 2 ). The method according to claim 5, wherein said reset pulse voltage signal ( RG ) is high in level in a voltage shift period of said further driving pulse voltage signal (H 1 ; H 2 ).

Inventors: HIRAMA MASAHIDE SONY CORPORATI, HIRAMA, MASAHIDE, SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H04N3
IPC codes: H01L27, H04N5, H04N3