Semiconductor device with low resistance contact and method of manufacturing the same

Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer (17) of a second conductivity type on a semiconductor substrate (1) of a first conductivity type, forming a transition metal compound layer (21) containing a constituent element of the semiconductor substrate on the impurity diffusion layer (17), and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere. A semiconductor device includes a semiconductor substrate (1) of a first conductivity type, an impurity diffusion layer (17) of a second conductivity type formed in the semiconductor substrate (1) of the first conductivity type, and a conductive metal compound layer formed on the impurity diffusion layer (17), wherein the conductive metal compound layer consists of at least a transition metal, a semiconductor element, and an impurity element of the second conductivity type which is an impurity element of the second conductivity type, and the impurity element of the second conductivity in the conductive metal compound layer is uniformly distributed.

Description: The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a shallow impurity layer. In recent years, electric circuits consisting of a large number of transistors and resistors are arranged in the main portion of a computer or communication equipment, and a large scale integrated circuit (LSI) obtained by integrating the large number of transistors and resistors in one chip is frequently used as the electric circuit. The improvement of the performance of one LSI is important to design high-performance equipment. Since this improvement can be achieved by increasing a degree of integration of, e.g., an LSI, a field effect transistor (FET) must be micropatterned. For this purpose, when the length of each gate of the FET is decreased, source and drain regions must be shallow. For example, low-acceleration ion implantation is popularly used for forming these regions. In this method, shallow source and drain regions each having a depth of about 0.1 µm can be formed, and a micro-patterned FET having high performance can be formed. However, an impurity layer formed by only the ion implantation has a high resistance, i.e., a sheet resistance of 100 Ω/□ or more. In order to increase the speed of the FET, the sheet resistance of the impurity layer must be decreased to cause a drain current to properly flow. when the diameter of a contact hole is decreased, Si contained in an Aℓ-Si-Cu alloy used as an electrode wiring material is precipitated in the contact hole to cause an increase in contact resistivity. In order to solve the above two problems, a method of metallizing a part of the impurity layer or the inside of the contact hole is considered. For example, a method called salicide is used. According to this method, after a field oxide film 83 is formed on a (100) Si substrate 81, a gate oxide film 85, a gate electrode 87, and a gate side-wall insulating film 89 (thickness of about 150 nm) are formed on the field oxide film 83. An impurity diffusion layer 91 is formed in the surface of the Si substrate 81 by well-known ion implantation, and a titanium (Ti) film 93 is deposited on the entire surface of the resultant structure to have a thickness of 40 nm. As shown in Fig. 1B, the surface of the Si substrate 81 is heated by lamp annealing, a silicide film, i.e., a titanium silicide (TiSi 2 ) film 9, is formed in the surface layer of the impurity diffusion layer 91. As shown in Fig. 1C, after the non-reacted Ti film 93 is removed by etching, an insulating film 97 is formed. Finally, contact holes are formed in the insulating film 97, and electrode wiring layers 99 are formed, thereby obtaining an FET. According to this method, the TiSi 2 film 95 having a thickness of 80 nm can be formed, and the sheet resistance can be decreased to about 2 to 3 Ω/□. However, recent extensive studies have pointed out the following problems of a method of this type. The depth of a diffusion layer must be set to be 0.1 µm or less to form an FET having a gate length of 0.3 µm or less. Boron (B) used for forming a p + -type diffusion layer has a diffusion coefficient smaller than that of arsenic (As) used for forming an n + -type diffusion layer. For this reason, in order to form such a shallow p + -type diffusion layer by using B, annealing must be performed at a low temperature of about 850°C. when the TiSi 2 film 95 is formed by the above method, however, B ions in a high-concentration region formed on the surface of the Si substrate are consumed for forming the TiSi 2 film 95. It is found that the B concentration of a TiSi 2 /Si interface is considerably decreased. For example, when the p + -type diffusion layer is formed by annealing at 850°C using ion implantation of BF 2 , the B concentration of the TiSi 2 /Si interface is a low value, i.e., 3 x 10 19 cm -3 or less. On the other hand, high-temperature annealing in a POCℓ 3 gas atmosphere at 850°C for 60 minutes may be performed to improve the reliability of the element after the TiSi 2 film is formed. However, in this case, the B concentration of the TiSi 2 /Si interface is further decreased. As a result, the contact resistivity of the electrode wiring layer to the p + -type diffusion layer is very large value, i.e., 1 × 10 14 Ω·cm 2 or more, ohmic and electric connection cannot be obtained between the p + -type diffusion layer and the electrode wiring layer. As a countermeasure against the above problem, the following attempt is made. That is, after the TiSi 2 film 95 is formed, B or BF 2 ions are implanted near the TiSi 2 /Si interface from the upper surface of the TiSi 2 film 95, and the resultant structure is annealed in a nitrogen atmosphere to increase the B concentration of the TiSi 2 /Si interface. However, B ions must be implanted at a high acceleration voltage of 30 kev or more to use this method, and a p + -type diffusion layer is deeply formed under the TiSi 2 film 95. For this reason, the method cannot be applied to a micropatterned device requiring a shallow junction, and Ti ions in the TiSi 2 film 95 are knocked in the Si substrate 81 by performing the ion implantation at a high acceleration voltage, i.e., a knock-on phenomenon occurs. Therefore, defects are formed in the diffusion layer and junction leakage is increased, resulting in inconvenience. When a wiring layer obtained by stacking a metal compound layer such as a TiSi 2 layer on a polysilicon layer containing an impurity such as B is to be formed, since the impurity is consumed, the wiring resistance of the polysilicon layer is increased. On the other hand, the salicide method is also applied to a complementary MOS (CMOS)-FET. That is, in this case, the complementary CMOS-FET is manufactured by the step shown in Fig. 12 except for formation of p + and n + -type impurity diffusion layers in the surface layer of the Si substrate 81. In this case, since the contact resistivity of the electrode wiring layer to the p + -type diffusion layer has a very large value, i.e., 1 × 10 -4 Ω·cm 2 or more, ohmic and electric connection cannot be obtained between the p + -type diffusion layer and the electrode wiring layer. In order to solve this problem, the following semiconductor device is proposed. In this semiconductor device, metal silicide films of different types are formed on the p + -type diffusion layer and the n + -type diffusion layer of the CMOS-FET, respectively. For example, a platinum silicide film is formed on the p + -type diffusion layer and a Ti silicide film is formed on the n + -type diffusion layer. However, since the number of steps in manufacturing the semiconductor device is very large, an inexpensive high-performance CMOS-FET cannot be obtained. As described above, when the shallow p + -type diffusion layer having a thickness of 0.1 µm or less is formed, in a conventional salicide method, an impurity concentration of the interface between a TiSi 2 film and a P + - type diffusion layer is decreased in proportion to an increase in time for high-temperature annealing. For this reason, a contact resistivity is increased, and it is difficult to properly perform electric connection between the p + -type diffusion layer and an electrode wiring layer. In addition, when an impurity is doped in the interface between the p + -type diffusion layer and the Si substrate by ion implantation, the following new problems are posed. That is, the depth of junction is increased, and at the same time, junction leakage is increased. In addition, the resistance is disadvantageously increased by consuming an impurity even in a stacked wiring layer consisting of a polysilicon film and a TiSi 2 film. Deposition of a phosphorus-doped molybdenum silicide film on a semiconductor substrate by d-c magnetron co-sputtering of Si and Mo targets is disclosed in an article in the Journal of Electrochemical Society: Solid-State Science and Technology, vol. 128, no. 11 (Nov. 1981), Manchester, New Hampshire, US, pages 2402 to 2410; S. Inoue et al.: "Phosphorus-Doped Molybdenum Silicide Films for LSI Applications". A transition metal silicide layer formed on a doped silicon substrate, and doped with impurities by ion implantation is known from EP-A2-0431721 . The present invention has been made in consideration of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device having high reliability, which is not degraded by junction leakage or the like, and a sufficiently low resistance of a contact between an electrode wiring layer and a shallow diffusion layer. Furthermore, it is another object of the present invention to provide a semiconductor device capable of obtaining both low-resistance p + - type and n + -type contacts which are stable after high-temperature annealing is performed. According to the first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an impurity diffusion layer of a second conductivity type on a silicon substrate of a first conductivity type; and forming a transition metal silicide layer on said impurity diffusion layer doped with an impurity of the second conductivity type wherein the method further comprises doping the impurity of the second conductivity type in the transition metal silicide layer by annealing in a reducing atmosphere containing said impurity after forming the transition metal silicide layer. According to the second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an impurity diffusion layer of a second conductivity type on a silicon substrate of a first conductivity type; and forming a thin film including a transition metal on said impurity diffusion layer, wherein the method further comprises: annealing said silicon substrate having said thin film thereon in an atmosphere containing an impurity element of the second conductivity type to cause the transition metal to selectively react with said silicon and to simultaneously dope the impurity element of the second conductivity type in a transition metal silicide layer formed by the reaction between the transition metal and the silicon substrate. According to the third aspect of the present invention, there is provided a semiconductor device comprising: a silicon substrate of a first conductivity type; an impurity diffusion layer of a second conductivity type formed in said silicon substrate of the first conductivity type; and a titanium silicide layer formed on said impurity diffusion layer containing titanium, silicon and boron, characterised in that a boron concentration of said titanium silicide layer is 2 x 10 20 cm -3 or more. Figs. 1A to 1C are sectional views showing the steps in manufacturing an FET in a conventional method; Figs. 2A to 2C are sectional views showing the first half of the steps in manufacturing an FET according to a first embodiment of the present invention; Figs. 3A and 3B are sectional views showing the second half of the steps in manufacturing the FET according to the first embodiment of the present invention; Fig. 4 is a graph showing a relationship between the depth of a substrate and a B concentration in the first embodiment of the present invention; Figs. 5A to 5C are sectional views showing the steps in manufacturing an FET according to a second embodiment of the present invention; Figs. 6A to 6C are sectional views showing the steps in manufacturing an FET according to a third embodiment of the present invention; Fig. 7 is a graph showing a relationship between the depth of a substrate and a B concentration in the third embodiment of the present invention; Figs. 8A to 8C are sectional views showing the steps in manufacturing an FET according to a fourth embodiment of the present invention; Figs. 9A to 9C are sectional views showing the steps in manufacturing a CMOS-FET according to a fifth embodiment of the present invention; Fig. 10 is a graph showing a result obtained by performing an SIMS analysis to a metal compound film formed on a p + -type diffusion layer; Fig. 11 is a graph showing a relationship between a B concentration in an Si surface layer and a B concentration in a metal compound formed in the fifth embodiment of the present invention; and Fig. 12 is a sectional view showing a step in manufacturing a CMOS-FET according to a sixth embodiment of the present invention. In the first and second embodiments of the present invention, TiSi 2 and ZrSi 2 are used as metal compounds containing constituent elements of a semiconductor substrate. The step of doping an impurity, i.e., the step of thermally diffusing the impurity preferably includes the step of thermally diffusing an impurity of a second conductivity type in a layer consisting of the metal compound and the step of thermally diffusing the impurity from the metal compound layer to the substrate. The step of thermally diffusing the impurity of the second conductivity type in the metal compound layer is preferably performed by a vapour-phase diffusion or a solid-phase diffusion from a metal impurity film. The solid-phase diffusion is performed by forming a thin film containing the impurity of the second conductivity type on the metal compound layer and diffusing the impurity of the second conductivity type in the metal compound layer. Alternatively, the solid-phase diffusion is performed by diffusing the impurity of the second conductivity type in the metal compound layer while the impurity of the second conductivity type is deposited on the metal compound layer. As a reducing atmosphere in which the above diffusion is performed, an atmosphere added with hydrogen or carbon monoxide is used. In this case, after the annealing is performed in the reducing atmosphere, it is more preferable that the impurity is thermally diffused in an oxygen atmosphere from the metal compound layer to an impurity diffusion layer. According to the third embodiment of the present invention, Ti, V, W, Mo, Ta, Co, or the like can be used as a transition metal. As a method of forming a thin film consisting of the transition metal, sputtering, CVD, beam evaporation, or the like can be used. The annealing for causing the transition metal to react with the impurity element of the second conductivity type is preferably performed at a temperature of 600 to 850°C. The annealing is not promoted at a temperature of less than 600°C. However, when the temperature is higher than 850°C, heat resistance is degraded. According to the third embodiment of the present invention, an impurity concentration of the conductive metal compound layer as a whole is not less than 2 × 10 20 cm -3 , and the ratio in a peak concentration near an interface between the conductive metal compound layer and the semiconductor substrate and a minimum concentration in the conductive metal compound layer is less than 10 1 . According to this embodiment of the present invention, since the impurity of the second conductivity type is thermally diffused in the impurity diffusion layer, the present invention is free from an increase in depth of the layer, defects of the layer, and any damage to the substrate compared with use of ion implantation. According to the first embodiment of the present invention, since a high-concentration impurity is doped in a metal compound layer and annealed in a reducing atmosphere, the metal compound and the impurity are prevented from being combined with and dissociated from each other, thereby uniformly distributing the impurity in the metal compound layer. Therefore, the impurity in the metal compound layer can be supplied to the interface between the metal compound layer and the impurity diffusion layer, the impurity concentration of the interface can be kept to be sufficiently high. According to the second embodiment of the present invention, when an impurity is to be doped from a gas containing the impurity of the second conductivity type in a metal compound layer, since the impurity is uniformly distributed in the metal compound layer without being combined with the metal compound, the same effect as described above can be obtained. According to the third embodiment of the present invention, since an impurity is not diffused outward from an interface between an Si substrate and a metal wiring layer formed on a shallow junction after high-temperature annealing is performed, an increase in contact resistance is prevented. According to the fourth embodiment of the present invention, according to forming a TiSi 2 -B film obtained by uniformly containing high-concentration B atoms in a p + -type Si substrate, Ti-B bonding is saturated, and extraction of B atoms from the substrate is prevented. For this reason, the B concentration of the interface is not decreased, and a thermally stable low-resistance contact can be formed. According to the fifth embodiment of the present invention, a conductive metal compound layer further contains an element such as C, N, or O, having a bonding energy to a transition metal higher than those to the transition metal and Si. For this reason, in a complementary MOS semiconductor device, an impurity element such as B is not diffused in an impurity diffusion layer such as an n + -type Si layer by a concentration gradient, thereby obtaining a stable contact. As described above, according to the present invention, a shallow high-concentration impurity layer or the like can be formed not to cause degradation of the impurity layer, and a contact resistance between an electrode wiring layer and the impurity layer can be sufficiently decreased. Examples of the present invention will be described below with reference to the accompanying drawings. Example 1 Figs. 2A to 3B are sectional views showing the steps in manufacturing an FET according to a first embodiment of the present invention. As shown in Fig. 2A, a field oxide film 3 having a thickness of 800 nm was formed by a burying method on an n-type Si substrate having a (100) plane as a major surface. After a gate oxide film 5 having a thickness of about 10 nm, an impurity-doped polysilicon layer 7 having a thickness of 150 nm, a tungsten silicide (WSi 2 ) layer 9 having a thickness of 150 nm, and a CVD-SiO 2 film 11 were sequentially deposited in an element forming region surrounded by the oxide film 3, the stacked films were etched to have a gate shape, thereby forming a gate electrode. As shown in Fig. 2B, after a CVD-SiO 2 film having a thickness of about 150 nm and serving as an SiO 2 spacer 13 was deposited on the entire surface of the resultant structure, the CVD-SiO 2 film was anisotropically etched to form the SiO 2 spacer 13 on the side wall of the gate electrode. After a thin SiO 2 film 15 having a thickness of about 10 nm was formed on an exposed Si surface, BF 2 + ions were implanted in the SiO 2 film 15 at an acceleration voltage of 35 keV and a dose of 5 × 10 15 cm- 2 . Thereafter, the Si substrate 1 was annealed in an N 2 atmosphere at 850°C for one hour to form a shallow p + -type impurity diffusion layer 17 having a thickness of about 0.1 µm. As shown in Fig. 2C, the Si substrate 1 was set in an HF vapor to remove the thin SiO 2 film 15 from the p + -type impurity diffusion layer 17, and immediately, the Si substrate was set in a vacuum device. In this manner, a spontaneous oxide film on the Si surface could be prevented from growing. The pressure of the vacuum device was decreased to a very high vacuum of 1.33×10 -6 Pa (10 -8 Torr) or less, and Ti atoms were deposited by sputtering to form a Ti film 19 having a thickness of about 40 nm. Thereafter, a TiSi 2 layer 21 having a thickness of about 80 nm was selectively formed on the exposed Si surface of the resultant structure by annealing the resultant structure in an N 2 atmosphere at 600°C for 15 minutes. The TiSi 2 film formed at this time had a C49 phase. As shown in Fig. 3A, the resultant structure was etched in a solution having a ratio of H 2 SO 4 : H 2 O 5 = 5 : 1 to remove the non-reacted Ti film 19 deposited on the field oxide film 3 and the SiO 2 spacer 13. Thereafter, the Si substrate 1 was annealed in an N 2 atmosphere at 900°C for 30 seconds to change the phase of the TiSi 2 layer 21 into a C54 phase having a low sheet resistance. In this stage, the B concentration of the interface between the TiSi 2 layer 21 and the p + -type impurity diffusion layer 17 was measured. It was found that the value was very low, i.e., 3 × 10 19 cm -3 . At this time, when a contact resistivity was measured, the value was very high, i.e., 1 × 10 -4 Ω·cm 2 or more. In the stage, ohmic and electronic connection between the p + -type impurity diffusion layer 17 and the electrode wiring layer could not be obtained. This Si substrate 1 was set in a cold-wall chamber and annealed in a gas mixture atmosphere of Ar gas, H 2 gas, and B 2 H 6 gas at 600°C for 20 minutes. This annealing is called the first annealing step. At this time, the pressure of the chamber was set to be about 66.6 Pa (0.5 Torr), the flow rate of the H 2 gas was set to be 2,000 sccm, and the flow rate of the B 2 H 6 gas was set to be 50 sccm. In addition, the Ar gas was used as a carrier gas (as in the subsequent examples). The gas mixture was switched to a gas mixture consisting of Ar gas, O 2 gas, and B 2 H 6 gas, and the Si substrate 1 was annealed at 800°C for 10 minutes. This annealing is called the second annealing step. At this time, a pressure was set to be about 66.6 Pa (0.5 Torr), and the flow rates of the O 2 gas and the B 2 H 6 gas were set to be 5 sccm and 10 sccm, respectively. As shown in Fig. 3B, after stacked films having a thickness of 0.7 µm and consisting of a BPSG film 25 and a CVD-SiO 2 film 23 serving as an insulating interlayer were deposited on the entire surface of the resultant structure, the resultant structure was lamp-annealed in an N 2 atmosphere at the atmospheric pressure and 1,000°C for 10 seconds. This annealing is called the third annealing step. Finally, contact holes were formed, and an electrode wiring layer having stacked films consisting of a selective CVD-W film 27, a TiN film 29, and an Aℓ-Si alloy film 31 was formed in each contact hole, thereby obtaining an FET. At this time, when the B concentration of the interface between the p + -type impurity diffusion layer 17 and the TiSi 2 layer 21 was measured in detail, although the value was increased to 1 × 10 20 cm -3 , the depth of the p + -type impurity diffusion layer 17 was 10 nm or less. In the FET formed by the above method, when a contact resistivity between the TiSi 2 layer 21 and the p + -type impurity diffusion layer 17 was measured, the value was 23 Ω per contact area of 1 µm 2 , and a perfect ohmic contact could be obtained. In addition, the junction leakage of the FET was equal to that of an FET in which no silicide film was formed. In Example 1, a reason for preferably self-aligning the TiSi 2 layer 21 will be described below with reference to Fig. 4. Fig. 4 shows B concentration distributions in the method of Example 1 and in a conventional method. This graph shows the result obtained by analysis by using an SIMS method. Before the TiSi 2 layer 21 is formed, the p + -type impurity diffusion layer 17 having a high B concentration, i.e., a peak B concentration of 5 × 10 20 cm -3 , is formed in the Si substrate 1. However, the Si substrate 1 is etched in accordance with formation of the TiSi 2 layer 21, B atoms of the high concentration region are doped in the TiSi 2 layer 21. The B atoms doped in the TiSi 2 layer 21 are greatly diffused outward in accordance with the movement of the interface between the TiSi 2 layer 21 and the Si substrate 1, and some of the B atoms are bonded to Ti atoms to produce stable TiB 2 , thereby doping the B atoms in the TiSi 2 layer 21. As a result, as shown in Fig. 4, the final B concentration of the interface between the TiSi 2 layer 21 and the Si substrate 1 is decreased to a small value almost determined by the diffusion profile of initial B atoms and an amount of etched Si. Since the method up to this stage is the same as a method of forming a conventional silicide film, a sufficiently low contact resistivity is not obtained yet. In Example 1, in addition to the above steps, the first annealing step in a B 2 H 6 atmosphere was added. As shown in Fig. 4, when this step was used, B2H6 gas could be uniformly diffused in a high concentration in the TiSi 2 layer 21. In this first annealing step, since decomposition of the B 2 H 6 gas could be suppressed by adding H 2 gas, B atoms were not precipitated but could be uniformly diffused. At this time, the B concentration in the TiSi 2 layer 21 was measured to be about 8 × 10 20 cm -3 . When O 2 gas was added, and the second annealing step was performed, 3 atoms doped in the TiSi 2 layer 21 were piled up on the interface between the TiSi 2 layer 21 and the Si substrate 1 and on the surface of the TiSi 2 layer 21. In this annealing step, even when annealing was performed in an atmosphere where O 2 gas was not added, the B concentration of the interface was increased. However, the increase in B concentration was considerably increased by adding the O 2 gas because the B atoms in the TiSi 2 layer 21 were dissociated. At this time, since an SiO 2 film was formed on the surface of the TiSi 2 layer 21, the B atoms were prevented from outward diffusion. In addition, the third annealing step was added, the B atoms piled up on the interface between the TiSi 2 layer 21 and the Si substrate 1, as shown in Fig. 4, were diffused in the Si substrate 1, such that the high-concentration p + -type impurity diffusion layer 17 could be formed. As described above, since the B atoms are diffused by all thermal diffusion phenomena, the Si substrate 1 can be prevented from damage, and preferable junction leakage characteristics can be obtained. According to Example 1, nigh-concentration B atoms can be supplied to the interface between the TiSi 2 layer 21 and the Si substrate 1 without damage to the Si substrate 1, and the shallow p + -type impurity diffusion layer 17 which can be in good contact with an electrode wiring layer can be easily formed. Example 2 Figs. 5A to 5C are sectional views showing the steps in manufacturing an FET according to a second embodiment of the present invention. The same reference numerals as in Figs. 2A to 3B denote the same parts of the FET shown in Figs. 5A to 5C, and a description thereof will be omitted. In Example 2, B ions are diffused in a TiSi 2 layer 21 and an interface between the TiSi 2 layer 21 and an Si substrate 1 by solid-phase thermal diffusion in place of vapor-phase thermal diffusion. As shown in Fig. 5A, a gate oxide film 5 and a gate electrode having stacked films consisting of a polycrystalline layer 7, a WSi 2 layer 9, and an SiO 2 film 11 were formed on an element forming region which was formed on the n-type Si substrate 1 having a (100) plane as a major surface and surrounded by a field oxide film 3 having a thickness of 800 nm. Thereafter, a thin SiO 2 film (not shown) having a thickness of 10 nm was formed on the exposed Si surface of the Si substrate 1, and BF 2 + ions were implanted at an acceleration voltage of 35 keV and a dose of 5 × 10 15 cm -2 . The steps up to this are the same as those of Example 1. Lamp annealing was performed in an N 2 atmosphere at 1,050°C for 20 minutes to form a shallow p + -type impurity diffusion layer 17 having a thickness of about 0.1 µm. when a method of forming an impurity diffusion layer using this lamp annealing was performed, a p + /n junction sharper than that obtained by normal furnace annealing could be obtained. As in Example 1, after a thin SiO 2 film was removed, a Ti film having a thickness of 400 nm was deposited, and the TiSi 2 layer 21 was formed using the following double-step annealing. That is, the double-step annealing included the first-step annealing in an N 2 atmosphere at 600°C for 15 minutes, treatments in an H 2 SO 4 solution and an H 2 O 2 solution, and the second-step annealing in an N 2 atmosphere at 900°C for 30 seconds. As shown in Fig. 5B, the Si substrate on which the TiSi 2 layer 21 was formed was set in a cold-wall chamber and annealed in a gas mixture consisting of Ar gas and B 2 H 2 gas at 450°C for 30 minutes. This step is called the first annealing step hereinafter. In this step, a B film 33 having a thickness of about 20 nm could be deposited on the entire surface of the substrate. At this time, the pressure of the chamber was set to be about 0.5 Torr, and the flow rate of the B 2 H 6 gas was set to be 200 sccm. The gas mixture was switched to a gas mixture consisting of H 2 gas and B 2 H 6 gas, and the substrate was annealed at 800°C for 20 minutes. At this time, the flow rates of the H 2 gas and B 2 H 6 gas were set to be 2,000 sccm and 50 sccm, respectively. This step is called the second annealing step hereinafter. After the substrate was annealed in a 10% oxygen atmosphere at 600°C for 5 minutes to change the B film 33 into a B 2 O 3 film, the B 2 O 3 film was removed by water. The second annealing step may be performed as follows. That is, the substrate is annealed in a gas mixture consisting of Ar gas, O 2 gas, and B 2 H 6 gas at 850°C for 20 minutes. At this time, a pressure is set to be 66.65 Pa (0.5 Torr), and the gas flow rates of the Ar, O 2 , and B 2 H 6 are set to be 2,000 sccm, 2 sccm, and 50 sccm, respectively. As shown in Fig. 5C, as in Example 1, after a CVD-SiO 2 film 23 and a BPSG film 25 were sequentially deposited on the substrate, the substrate was lamp-annealed in an N 2 atmosphere at 1,000°C for 10 seconds to increase the concentration of the p + -type impurity diffusion layer 17. Finally, contact holes were formed in source and drain regions, and electrode wiring layers each having stacked films consisting of a W film 27, a TiN film 29, and an Aℓ-Si alloy film 31 were formed in the contact holes, thereby obtaining an FET. The contact resistivity and junction leakage characteristics between the TiSi 2 layer 21 and the p + -type impurity diffusion layer 17 of the FET formed by the above method were measured. As a result, as in Example 1, it was confirmed to obtain preferable results. In Example 2, H may have the following function. That is, when H atoms are bonded to Ti atoms, the Ti atoms are prevented from being bonded to B ions, or the Ti and B atoms are dissociated from each other, thereby uniformly distributing the B atoms in the TiSi 2 layer. For this reason, the B atoms are sufficiently supplied to the interface between the TiSi 2 layer and the diffusion layer, and the above effect can be obtained. In Example 2, the B film 33 is formed by CVD using B 2 H 6 gas. However, even when the B film 33 is formed by physical deposition such as sputtering, the same effect as described above can be obtained. At this time, when a spontaneous oxide film on the interface between the B film 33 and the TiSi 2 layer 21 is removed by Ar reverse sputtering or by F 2 gas, Cℓ 2 gas, or BCℓ 3 gas, doping can be performed with good reproducibility. In addition, when a substrate on which a BN film is deposited in place of the B film 33 is annealed, the same effect as described above can be obtained. The first and second embodiments of the present invention are not limited to Examples 1 and 2. For example, in Examples 1 and 2, after the p + -type impurity diffusion layer 17 is formed on the Si substrate 1, the TiSi 2 layer 21 is formed, and a B concentration is increased. However, so-called post doping may be performed. That is, in the post doping, prior to the formation of the p + -type impurity diffusion layer, the TiSi 2 layer 21 may be formed, and the shallow p + -type impurity diffusion layer 17 may be formed in the same steps as described above. After B ions may be doped in the TiSi 2 layer 21 by ion implantation of BF 2 , the TiSi 2 layer 21 may be annealed in a gas mixture consisting of Ar, H 2 , B 2 H 6 to uniformly diffuse B ions in the TiSi 2 layer 21, and the B ions may be diffused in the substrate by the annealing step serving as a subsequent step as in Examples 1 and 2. In this case, when the range of the doped ions is completely controlled within the TiSi 2 layer 21, damage to the Si substrate can be minimized. In addition, an impurity such as B ions may be doped in the TiSi 2 layer 21 by another method. Example 3 Figs. 6A to 6C are sectional views showing the steps in manufacturing an FET according to a third embodiment of the present invention. As in Example 1, as shown in Fig. 6A, shallow p + -type impurity diffusion layers 17 were formed in an Si substrate 1. Note that annealing was performed in an N 2 atmosphere at 1,000°C for 20 seconds. The Si substrate 1 was set in an HF vapor to remove a thin SiO 2 film 15 from the p + -type impurity diffusion layer 17, and immediately, the Si substrate 1 was set in a vacuum device. In this manner, a spontaneous oxide film on the Si surface could be prevented from growth. The pressure of the vacuum device was decreased to a very high vacuum of 1.33×10 -6 Pa(10 -8 Torr) or less, and a Ti film 40 was formed on the p + -type impurity diffusion layer 17 by sputtering deposition to have a thickness of about 20 nm. The Si substrate 1 was set in a cold-wall chamber and annealed in a gas mixture consisting of Ar gas and B 2 H 6 at 600°C for 20 minutes. At this time, the pressure in the chamber was set to be about 0.5 Torr, and the flow rate of the B 2 H 6 gas was set to be 5 sccm. As a result of the annealing, as shown in Fig. 6B, the Ti film 40 was reacted with the Si substrate 1 to form a TiSi 2 layer 41 having a thickness of about 50 nm. At the same time, high-concentration B atoms were doped in the TiSi 2 layer 41. After a non-reacted Ti film was selectively removed by a solution mixture consisting of H 2 SO 4 and H 2 O 2 , a stacked film having a thickness of 1.0 µm and consisting of a CVD-SiO 2 film 23 serving as an insulating interlayer and the BPSG film 25 was formed on the entire surface of the resultant structure. Thereafter, annealing for reflow and gettering was performed to the Si substrate 1 in a POCℓ 3 atmosphere at an atmospheric pressure and 850°C for 60 minutes. Finally, as shown in Fig. 6C, contact holes were formed on source and drain regions, and an electrode wiring Layers each having a stacked film consisting of a selection CVD-W film 27, a TiN film 29, and an AS-Si alloy film 31 were formed in the contact holes, thereby obtaining an FET. When the contact resistivity between the TiSi 2 layer 41 and the p + -type impurity diffusion layer 17 of the FET formed by the above method was measured, the value was about 20 Ω per a contact area of 1 µm 2 , and a perfect ohmic contact could be obtained. In addition, the junction leakage of the FET was equal to that of an FET in which the TiSi 2 layer 41 was not formed. This mechanism was examined as in Example 1. That is, when the B distribution in the TiSi 2 layer was evaluated by an SIMS method, as shown in Fig. 7, it was confirmed that the B atoms were uniformly distributed in the TiSi 2 layer 41 at a concentration of 1 × 10 21 cm -3 or more. At this time, since the grain size of Ti silicide constituting the TiSi 2 layer 41 was small, i.e., 50 nm or less, B atoms were distributed in TiSi 2 grains at a high concentration, and some of the B atoms were precipitated on the grain boundary to produce TiB 2 . The boron concentration of the p + -type impurity diffusion layer 17 at the interface contacting with the TiSi 2 layer 41 was 1 × 10 20 cm -3 , and it was confirmed that the B concentration was not decreased even when the high-temperature gettering step was performed to the interface. That is, according to the third embodiment of the present invention, when the TiSi 2 layer is to be formed, annealing in an N 2 atmosphere, an Ar atmosphere, and a vacuum atmosphere is not performed, but annealing is performed in a B 2 H 6 gas atmosphere. Therefore, formation of the TiSi 2 substrate and doping of high-concentration B atoms can be simultaneously performed. Since formation energy of a Ti-B bond is generally higher than that of a Ti-Si bond, when a TiSi 2 layer is formed in a conventional technique, B atoms being on a TiSi 2 /p + -type Si interface are actively adsorbed in the TiSi 2 layer. For this reason, a low-resistance contact having thermal stability cannot be formed. However, in Example 3, since high-concentration B atoms are present in the TiSi 2 layer in advance, the B atoms are not adsorbed in the TiSi 2 layer. In addition, rapid diffusion of the B atoms caused by precipitating TiB 2 on Ti-silicide grain boundary is prevented. As a result, the B concentration of the interface of the TiSi 2 layer and the Si substrate is not decreased, and a low-resistance contact having thermal stability can be formed. As a method of doping B atoms in the TiSi 2 layer, ion implantation is used. However, the ion implantation generally has spread approximated by the Gaussian process in an implantation profile of ions. For this reason, it is difficult to uniformly dope B atoms in the direction of depth of the TiSi 2 layer. In addition, when the B concentration near the interface of the TiSi 2 layer and the Si substrate 1 is sufficiently increased, atoms are inevitably deeply doped in the Si substrate. As a result, the thickness of a junction portion is increased. At the same time, defects are formed in the Si substrate to cause the junction leakage. In contrast to this, according to Example 3, since thermal diffusion is used as the method of doping B atoms, the B atoms can be uniformly doped without causing any defect of the Si substrate. In addition, since the formation of the TiSi 2 layer and the doping are simultaneously performed, a decrease in B concentration on the interface can be suppressed during formation of the TiSi 2 layer. As is apparent from the above mechanism, according to this embodiment, as a Ti film has a small thickness, the effect of the present invention is sufficiently enhanced. The thickness of the Ti film is preferably set to be 40 nm or less because, when the thickness of the Ti film excesses 40 nm, the silicide forming reaction and the B atom diffusion process are independently performed on the Ti/Si interface to degrade a doping effect. When the thickness of the Ti film is set to be 40 nm or less, since B atoms easily reach the Ti/Si interface, the silicide formation and doping are simultaneously performed. When the TiSi 2 layer is formed while the thickness of the Ti film is set to be 10 nm or less, an aggregation reaction occurs by annealing at 850°C, and the shape of TiSi 2 layer is changed into an island shape. However, according to the method of Example 3, even when the thickness of the Ti film is set to be 5 nm, since high-concentration B ions are doped in the TiSi 2 layer, no aggregation reaction occurs, thereby obtaining a proper TiSi 2 layer in which the B ions are uniformly doped. According to Example 3, although a gas mixture of consisting of Ar and B 2 H 6 is used as an annealing gas, H 2 gas may be added to the gas mixture. Even when a gas containing a dopant such as BCℓ 3 is used in place of the B 2 H 6 gas, the same effect as described above can be obtained. Example 4 Figs. 8A to 8C are sectional views showing the steps in manufacturing an FET according to a fourth embodiment of the present invention. As in Example 3, as shown in Fig. 8A, shallow p + -type impurity diffusion layers 17 were formed in an Si substrate 1, and a Ti film 40 having a thickness of 20 nm was formed thereon. The Si substrate 1 was set in a cold-wall chamber and annealed in a gas mixture consisting of Ar gas and B 2 H 6 at 850°C for 60 minutes. At this time, the pressure in the chamber was set to be about 66.65 Pa (0.5 Torr), and the flow rate of the B 2 H 6 gas was set to be 10 sccm. As a result of annealing, as shown in Fig. 8B, the Ti film 40 was entirely changed into a TiB 2 film 42. That is, since the Ti film 40 was annealed in the high-concentration B 2 H 6 gas atmosphere at a high temperature, high-concentration B atoms were not doped in the TiSi layer, but the TiB 2 film 42 was formed. As shown in Fig. 8C, after the TiB 2 film 42 was patterned to a predetermined portion by photolithography, as in Example 3, insulating interlayers 23 and 25 were formed, and contact holes were formed. For example, electrode wiring layers each having a stacked film consisting of a selection CVD-W film 27, a TiN film 29, and an Aℓ-Si alloy film 31 were formed, thereby obtaining an FET. When the contact of the FET formed as in Example 3 was evaluated, it was confirmed that low-resistance characteristics having high thermal stability could be obtained as in Example 3. A mechanism for forming the TiB 2 film 42 is considered as follows. That is, at the beginning of a reaction, B atoms are adsorbed to the interface between the Si substrate and the Ti film to form the TiSi 2 layer. However, since the annealing temperature, i.e., 850°C, is higher than that of Example 3, a rate of forming Ti-B bonds is higher than that of Ti-Si bonds, and most of Ti atoms are consumed in production of TiSi 2 . In addition, since the production enthalpy of TiB is larger than that of TiSi 2 , a reaction of TiSi 2 + 2B → TiB 2 + Si is performed at the high temperature. On the other hand, on an insulating film, since Ti ions produce TiB 2 at first, an entirely uniform TiB 2 film is formed. When the TiB 2 layer film is formed, as in Example 3, the Ti atoms bonded to B atoms are not extracted. Therefore, it is regarded that a contact resistance is not increased even in a subsequent high-temperature annealing step. In addition, when the TiB 2 film is formed by the method of Example 4, since the Si surface is brought into contact with Ti atoms at first, a spontaneous oxide film is reduced. For this reason, a proper interface free from variations in washing process performed prior to deposition of Ti can be obtained. The third aspect of the present invention can be achieved by modifying Example 4, as a matter of course. For example, when the annealing time in Example 4 is prolonged, B atoms can be diffused in the Si substrate through the TiB 2 film to form a p + -type junction. In Examples 3 and 4, a method of forming the TiSi 2 layer or the TiB 2 film on the entire surface of a p + -type impurity diffusion layer has been described. However, these films may be applied to the barrier metal forming step of forming a barrier metal film in a contact hole. In this case, when a polysilicon film, a transition metal silicide film such as an NiSi film, a TiSi 2 film, a WSi 2 film, and an MoSi 2 film, or a film consisting of a refractory metal such as W and Ta may be used as a wiring layer, a low-resistance wiring layer which can withstand an annealing step at 600°C or more can be easily obtained, although a conventional Aℓ alloy film cannot withstand the annealing step. For this reason, a device having a three-dimensional stacking structure can be easily formed. As a modification of Example 4, after a Ti film having a thickness of 20 nm is formed by sputtering Ti, a Ti-B alloy which contains B having a concentration higher than that of TiB 2 is deposited by sputtering or CVD to form a 70-nm thick Ti-B alloy film. When the Ti-B alloy film is annealed at 700 to 800°C for 30 to 60 seconds or at 550 to 650°C for 30 minutes, TiSi 2 containing B can be obtained. In Examples 3 and 4, Ti is used as a transition metal, and the Ti is deposited by sputtering. However, another transition metal may be deposited by another thin film deposition. More particularly, in Example 3, a transition metal silicide film doped with high-concentration B atoms can be formed, to obtain a thermally stable contact. In Examples 1 to 4, although use of a p + -type Si substrate has been described, the same technique as described above can be easily applied to an n + -type Si substrate, as a matter of course. For example, although a Ti-B film is formed by using a gas mixture consisting of B 2 H 6 gas and Ar gas in each of Examples 1 to 4, a Ti-As film can be formed on an n + -type Si substrate by using AsH 4 gas in place of the B 2 H 6 gas. In addition, B diffusion using B 2 H 6 has also been described in Examples 1 to 4. However, when B diffusion using BCℓ 3 or an organic boron compound is performed, the same effect as described above can be obtained. Although most of each of source and drain regions is changed into silicide in each of Examples 1 to 4, the method of the present invention can be applied to a small contact hole having a size of 0.5 µm or less formed in an n + - or p + -type impurity diffusion layer. Although a TiSi 2 film is used as silicide in each of Examples 1 to 4, the present invention can be applied to other silicide films such as a CoSi 2 film, an NiSi 2 film, a WSi 2 film, and an MoSi 2 film. Example 5 Figs. 9A to 9C are sectional views showing the steps in manufacturing a CMOS-FET according to a fifth embodiment of the present invention. A field oxide film 52 having a thickness of 800 nm was formed by a burying method on an n-type Si substrate 51 having a (100) plane as a major surface. As and B atoms serving as impurities were doped by high-acceleration ion implantation in element forming regions divided by the filed oxide film 52 to form an n-type well layer 53 and a p-type well layer 54. A gate oxide film 55 having a thickness of 10 nm, a doped polysilicon layer 56 having a thickness of 150 nm, a WSi 2 film 57 having a thickness of 150 nm, and a CVD-SiO 2 film 58 were sequentially formed on the Si substrate 51 in each element forming region. The resultant structure was etched to have a gate shape. A CVD-SiN film having a thickness of 150 nm was formed on the resultant structure, and each side wall of the gate was anisotropically etched to form an SiN film 59. Thereafter, BF 2 + ions were doped in the n-type well layer 53 at an acceleration voltage of 35 keV and a dose of 3 × 10 15 cm -2 , and As + ions were doped in the p-type well layer at an acceleration voltage of 60 keV and a dose of 3 × 10 15 cm -2 . Subsequently, the resultant structure was annealed in an N 2 atmosphere at 1,000°C for 20 seconds to form shallow p + - and n + -type impurity diffusion layers 60 and 61 having a thickness of about 0.1 µm as shown in Fig. 9A. Thereafter, HF processing was performed to the entire surface of the Si substrate, and the Si substrate was washed with distilled water containing an oxygen concentration of 5 ppm or less, and, immediately, the Si substrate was set in a vacuum device. This processing could prevent a spontaneous oxide film from growing on the Si surface. The pressure in the vacuum device was decreased to be 5 × 10 -7 Torr or less, and the Si substrate 51 was heated to 750°C. TiCℓ 4 gas of 10 sccm, SiH 4 gas of 10 sccm, B 2 H 6 gas of 1 sccm, and H 2 gas of 10 sccm were supplied to the vacuum device. At this time, the pressure in this vacuum device was set to be 13.33 Pa(0.1 Torr). As a result, as shown in Fig. 9B, a Ti-Si-B mixture film 62 having a thickness of about 50 nm was selectively formed on each of the p + -type diffusion layers 60 and the n + -type diffusion layers 61 at the same time. A CVD-SiO 2 63 and a PSG film 64 were formed on the entire surface of the resultant structure as an insulating interlayer. At this time, a total thickness of these films was set to be 1.0 µm. Gettering and annealing were performed to the resultant structure in a POCℓ 3 atmosphere at 850°C and an atmospheric pressure for 60 minutes. Thereafter, contact holes were formed in source and drain regions, and electrode wiring layers was formed by forming a selection CVD-W film 65, a TiN film 66, and an Aℓ or Cu film 67 in the contact holes, thereby obtaining a MOS-FET as shown in Fig. 9C. When the Ti-Si-B mixture film 62 was measured by X-ray diffraction, it was confirmed that the film consisted of TiSi 2 , and other Ti compounds were not detected. In addition, when a boron (B) concentration in the Ti-Si-B mixture film 62 was analyzed by an SIMS method, it was confirmed that boron was uniformly distributed in the film at a concentration of about 5 × 10 20 cm -3 . When a Ti-Si-B-C mixture film was formed in place of the Ti-Si-B mixture film, CH 4 gas was supplied to the vacuum device at a flow rate of 0.1 sccm, in addition to the above gas mixture. In this case, as shown in Fig. 10, it was confirmed that carbon was uniformly distributed in the Ti-Si-B-C mixture film at a concentration of about 10 19 cm -3 . In this manner, the Ti-Si-B mixture film was formed by uniformly distributing high-concentration B atoms in an TiSi 2 film, and the Ti-Si-B-C mixture film is formed by uniformly distributing high-concentration B atoms and low-concentration C in a TiSi 2 film. These mixture films are also referred to as TiSi 2 -B films hereinafter. When the B concentration of the p + -type diffusion layer at the interface contacting with the TiSi 2 -B film was measured in detail, the B concentration was 1 to 2 × 10 20 cm -3 , and it was confirmed that the B concentration of the interface was not decreased although the TiSi 2 -B film was subjected to high-temperature gettering. In addition, the state of the interface between the TiSi 2 -B film and the n + -type diffusion layer was examined in detail, and the following was confirmed. That is, B ions were not doped in the n + -type diffusion layer from the TiSi 2 -B film, and an As concentration of the interface was not different from that before the TiSi 2 film was formed. When contact resistivities of the TiSi 2 -B film and the p + -type diffusion layer of the CMOS-FET manufactured as described above were measured, the value was 24 Ω per contact area of 1 µm 2 , and a perfect ohmic contact could be obtained. In addition, the sheet resistance of the p + -type diffusion layer was decreased to 4 Ω/□, and it was conformed that the transistor characteristics Gm was increased by 10% or more compared with the case wherein the TiSi 2 -B film was not formed. In addition, the junction leakage of each of the n + -type diffusion layer and the p + -type diffusion layer was substantially equal to reference junction leakage. The C-doped TiSi 2 -B film was a uniform film which had a uniform concentration distribution even when the film was subjected to annealing at 800 to 900°C. According to the fifth embodiment of the present invention, a mechanism in which a stable contact is obtained even when it is subjected to high-temperature annealing will be described below. In a conventional method of forming a TiSi 2 film containing no boron, a decrease in free energy caused by forming Ti-B compound is larger than a decrease in free energy caused by forming Ti-Si compound. For this reason, B ions present in an Si layer near the interface between the TiSi 2 film and the p + -type Si substrate are actively adsorbed in the TiSi 2 film. Since a probability of bonding Ti atoms and B atoms is increased in proportion to an increase in annealing temperature, the TiSi 2 film is subjected to high-temperature annealing, so that a gettering step or a BPSG reflowing step, or extraction of the B atoms is promoted, and the B concentration of the interface is considerably decreased. As a result, a thermally stable low-resistance contact cannot be formed by a conventional technique. In contrast to this, according to the fifth embodiment of the present invention, since a TiSi 2 -B film uniformly containing high-concentration B atoms is formed on a p + -type Si substrate, saturation of Ti-B, Ti-C bonding prevents the substrate from extraction of B atoms. In addition, since a B concentration in the TiSi 2 -B film is higher than that of the p + -type Si substrate, thermal diffusion of B atoms from the substrate is prevented. As a result, the B concentration of the interface is not decreased, and a thermally stable low-resistance contact can be formed. In this case, since B atoms which can freely move in the TiSi 2 -B film are not present, they are not doped in the Si substrate after annealing is performed. In addition, the electron concentration of the interface between the n + -type diffusion layer an the Si substrate is kept to be stable, and an increase in n + -type contact resistivity is prevented. In this embodiment, when the flow rate of B 2 H 6 gas is controlled, a B concentration in a region having a depth of about 20 nm near the surface of the TiSi 2 -B film can be decreased to the B concentration in the p + -type diffusion layer or less, i.e., 1 × 10 19 cm -3 or less. In this case, after high-temperature annealing is performed for a long time, it is found that a few B ions are extracted from the p + -type diffusion layer, because, when a TiSi 2 -B film having a low B concentration is present near the surface, the B distribution in the film is reformed. Therefore, it is important that B atoms are uniformly distributed in the TiSi 2 -B film. As described above, according to the fifth embodiment of the present invention, it was cleared that uniform distribution of high-concentration B atoms in the film was important. More particularly, when an B concentration was set to be 2 × 10 20 cm -3 or more, more preferably 5 × 10 20 cm -3 or more, an optimal result was obtained. In this case, Fig. 11 shows relationship between the B concentration of the TiSi 2 -B film which is subjected to annealing at 850°C for 60 minutes and the B concentration of the surface of the p + -type Si substrate. As is apparent from Fig. 11, when the B concentration in the TiSi 2 -B film is 2 × 10 20 cm -3 or more, more preferably 5 × 10 20 cm -3 or more, the B concentration in the surface of the Si substrate becomes 10 20 cm -3 . A method according to Example 5 is superior to a method of doping B atoms in a Ti silicide film by ion implantation in the following points. That is, in the ion implantation, since the implantation profile of ions generally has spread approximated by the Gaussian distribution, it is difficult to uniformly dope in the Ti silicide film. Even if B atoms are attempted to be uniformly doped in the Ti silicide film by sequentially changing acceleration voltages, when the B concentration near the interface between the silicide film and the Si substrate is sufficiently high, the B atoms are deeply doped in the Si substrate. As a result, the junction depth is increased, and defects may be formed in the Si substrate, thereby probably causing junction leakage. On the other hand, when B atoms are doped only near the surface of the Ti silicide film, since a sufficient B concentration cannot be assured near the interface, the B atoms are extracted by TiSi 2 after high-temperature annealing is performed, and the conventional problem cannot be solved. In addition, in the ion implantation, since a mask such as a resist must be formed to prevent B ions from being doped in the n + -type diffusion layer, the number of manufacturing steps is increased. Since the Ti silicide film does not have resistance to acid, the resist cannot be completely removed after the ion implantation is performed. For this reason, the Ti silicide film is contaminated by free ions such as sodium ions. In contrast to this, in the method according to Example 5, since B ions can be uniformly distributed in the TiSi 2 film at a high concentration without substantially causing defects in the Si substrate, a decrease in p + -type ion concentration can be perfectly suppressed after high-temperature annealing is performed. In Example 5, the TiSi 2 -B film is selectively formed on only an impurity diffusion layer. However, even if the TiSi 2 -B film is formed on the entire surface of the Si substrate and patterned to form a wiring layer in only a predetermined region, the same effect as described above can be obtained. In this case, prior to film formation in Example 5, after a spontaneous oxide film is removed by annealing in SiH 4 gas at 750 to 800°C, the same film forming gas as described above is supplied, and a uniform TiSi 2 -B film can be formed. In addition, even if BCℓ 3 gas or B(CH 3 ) 3 gas is used in place of the B 2 H 6 gas, the same effect as described above can be obtained. TiCℓ 3 (CH 3 ) gas, Ti+[N(CH 3 ) 2 ] 4 , or the like may be used as the TiCℓ 4 gas. When a uniform TiSi 2 -B film is formed by sputtering using a mixed-metal target such as Ti-Si-B or simultaneous deposition in place of CVD, the same effect as described above can be obtained. In Example 5, since CH 4 gas is used as one of film forming gases, low-concentration C can be distributed in the formed TiSi 2 -B film. For this reason, production of TiB 2 clusters is suppressed, and B ions can be uniformly distributed in the film. In addition, even if N 2 gas or NH 3 gas is added in place of the CH 4 gas, the same effect as described above can be obtained. That is, when an element such as C, N, or O which has the production enthalpy in production of a compound larger than that in production of Tisi 2 and can form a Ti conductive compound having the same conductivity as that of TiB 2 is added, production of TiB 2 clusters can be suppressed. Therefore, the structure of the semiconductor device according to the present invention can be easily stabilized. Various modifications of Example 5 can be effected as a matter of course. For example, Ti is deposited on the entire surface of a substrate by sputtering, and the resultant structure is annealed at 650 to 750°C to form a TiSi 2 film on only an exposed Si portion. Thereafter, B ions can be uniformly distributed in a Ti silicide film by vapor-phase diffusion of B 2 H 6 gas. In addition, although a method of forming the TiSi 2 film on the entire surface of the diffusion layer has been described in this embodiment, as shown in Fig. 12, this technique may be applied to the barrier metal forming step. That is, a TiSi 2 -B film 71 may be formed in a contact hole 70. The case wherein Ti is used has been described in Example 5. However, high-concentration B atoms may be doped in a film by using another transition metal such as zirconium (Zr), vanadium (V), tungsten (W), molybdenum (Mo), tantalum (Ta), or cobalt (Co) to form a so-called transition metal silicide-B film, and a thermally stable contact can be formed on an CMOS-FET. As described above, according to the present invention, since an impurity is supplied from a metal compound layer to a substrate by thermal deposition, a semiconductor device having sufficiently low contact resistance between an electrode wiring layer and a shallow impurity layer can be obtained without any damage to the substrate or the like.

Claims: A method of manufacturing a semiconductor device, comprising the steps of: forming an impurity diffusion layer (17, 60, 61) of a second conductivity type on a silicon substrate (1, 51) of a first conductivity type; and forming a transition metal silicide layer (21, 41, 42, 57, 71) on said impurity diffusion layer (17, 60, 61) doped with an impurity of the second conductivity type, characterised in that: doping the impurity of the second conductivity type in said transition metal silicide layer (21, 41, 42, 57, 71) is carried out by annealing in a reducing atmosphere containing said impurity after forming said transition metal silicide layer. A method according to claim 1, characterised in that the step of doping the impurity of the second conductivity type in said metal silicide layer is performed by vapour-phase diffusion. A method according to claim 1, characterised in that said reducing atmosphere is a hydrogen or carbon monoxide atmosphere. A method according to claim 1, characterised in that the step of doping the impurity of the second conductivity type in said metal silicide layer is performed by solid-phase diffusion. A method according to claim 4, characterised in that the solid-phase diffusion is performed by forming a thin film (33) containing the impurity of the second conductivity type on said metal silicide layer (21, 41) and diffusing the impurity of the second conductivity type in said metal silicide layer (21, 41). A method according to claim 4, characterised in that the solid-phase diffusion is performed by diffusing the impurity of the second conductivity type in said metal silicide layer while the impurity of the second conductivity type is deposited on said metal silicide layer (21, 41). A method according to claim 1, characterised in that a gas mixture including a gas containing the impurity of the second conductivity type and a gas for suppressing decomposition of the gas containing the impurity of the second conductivity is included in said atmosphere containing the impurity element of the second conductivity type. A method according to claim 1, characterised in that the transition metal is at least one member selected from the group consisting of Ti, V, W, Mo, Ta, and Co. A method according to claim 1, characterised in that B is used as the impurity element, and Ti is used as the transition metal. A method of manufacturing a semiconductor device, comprising the steps of: forming an impurity diffusion layer (17, 60, 61) of a second conductivity type on a silicon substrate (1, 51) of a first conductivity type; and forming a thin film (21, 41, 42, 57, 71) including a transition metal on said impurity diffusion layer, and: annealing said silicon substrate (1, 51) having said thin film (21, 41, 42, 57, 71) thereon in an atmosphere containing an impurity element of the second conductivity type to cause the transition metal to react with said silicon and to simultaneously dope the impurity element of the second conductivity type in a transition metal silicide layer formed by the reaction between the transition metal and the silicon substrate. A method according to claim 10, characterised in that a gas mixture including a gas containing the impurity of the second conductivity type and a gas for suppressing decomposition of the gas containing the impurity of the second conductivity is included in said atmosphere containing the impurity element of the second conductivity type. A method according to claim 11, characterised in that the gas mixture includes B 2 H 6 gas and H 2 gas. A method according to claim 10, characterised in that the transition metal is at least one member selected from the group consisting of Ti, V, W, Mo, Ta, and Co. A method according to claim 10, characterised in that B is used as the impurity element, and Ti is used as the transition metal. A semiconductor device comprising: a silicon substrate (1, 51) of a first conductivity type; an impurity diffusion layer (17, 60, 61) of a second conductivity type formed in said silicon substrate (1, 51) of the first conductivity type; and a titanium silicide layer formed on said impurity diffusion layer (21, 41, 42, 57, 71) containing titanium, silicon and boron, characterised in that a boron concentration of said titanium silicide layer (21, 41, 42, 57, 71) is 2 × 10 20 cm -3 or more. A semiconductor device according to claim 15, characterised in that the ratio of the peak concentration near the interface between said titanium silicide layer and said silicon region to the minimum concentration in said titanium silicide layer is less than 10 1 . A semiconductor device according to claim 15, characterised in that said silicon substrate is a complementary MOS substrate, said titanium silicide layer has interfaces contacting a first diffusion layer containing an impurity element of the first conductivity type and a second diffusion layer containing an impurity element of the second conductivity type, and said titanium silicide layer contains boron and an element whose bonding energy to titanium is larger than a bonding energy between titanium and silicon.

Inventors: KUNISHIMA IWAO, SUGURO KYOICHI, KUNISHIMA,IWAO, SUGURO, KYOICHI, Kunishima,Iwao, c/o Intellectual Property Div., Suguro, Kyoichi, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1992
Main classification: H01L21
IPC codes: H01L29, H01L21