Level shifting CMOS integrated circuits

Abstract: The voltage level shifter circuit includes a pair of CMOS invertors (1,2) having inputs and outputs cross connected thereto. One terminal of a pair of power source terminals of each CMOS invertor (1,2) is grounded, and complementary input signals are supplied to the CMOS (1,2) invertors by way of the respective other power source terminal. The voltage level shifter circuit level shifts an input amplitude substantially equal to an input threshold value of transistors to the voltage level of the power source while suppressing the dc consumption current.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a complementary metal oxide semiconductor (CMOS) voltage shifting logic circuit with low direct current power consumption and high speed switching operation. 2. Description of the Prior Art A level shifter circuit is conventionally employed to amplify a signal of a small voltage amplitude such as, for example, an ECL level to effect shifting of a voltage level of the signal to another signal of a greater amplitude. Exemplary ones of conventional level shifter circuits are shown in Figs. 1 and 2. In particular. Fig. 1 shows a conventional level shifter circuit which employs a flip-flop while Fig. 2 shows another conventional level shifter circuit which employs a current mirror. In order to assure a high driving capacity for an output load of each of the level shifter circuits shown in Figs. 1 and 2, the current driving capacity of an element employed must necessarily be high. However, since dc current flows through the level shifter circuits, if the driving capacity is increased, then the dc consumption current is increased. Accordingly, the conventional level shifter circuits have a drawback that the operating speed depends upon a trade-off with the dc consumption current. In the EP-A-0 411 818 a current sensing amplifier for a memory is disclosed, which has two cross-coupled input p-channel transistors, two load transistors connected respectively to the input transistors and a switch element. Output voltages are developed across the load transistors. The amplifier senses differences in currents supplied to the input transistors and drives the output voltages in opposite directions in a sense dependent on the sense of the difference of the currents. SUMMARY OF THE INVENTION It is an object of the present invention to provide a level shifter circuit which is low in dc current and high in operating speed. The invention is defined in claim 1, preferred embodiments are defined in the sub-claims. According to the invention, it is possible to raise the operating speed of the circuit without increasing the size of the input transistors. In the preferred embodiment the transistor connected to the side to which the input signal is supplied has further an increased current driving capacity while the other transistor connected to the power source of the fixed voltage side has a sufficiently low current driving capacity comparing with the transistor on the signal inputting side. Accordingly, the input threshold value of the level shifting circuit is decreased by an amount equal to the input threshold value of the transistor connected to the side to which the input signal is supplied, and consequently. the stable point is moved by a small variation of the input signal. As a result, a small input amplitude is level shifted to a great output amplitude by the level shifter circuits. BRIEF DESCRIPTION OF THE DRAWINGS The invention is described in detail with reference to the accompanying drawings, of which: Fig. 1 is a schematic circuit diagram of an exemplary conventional digital level shifter circuit: Fig. 2 is a schematic circuit diagram of another exemplary conventional digital level shifter circuit: Figs. 3A and 3B are a schematic circuit diagram and a logic diagram, respectively, of a CMOS digital level shifter circuit showing a modification of the circuit disclosed in the EP-A-0 411 818; Figs. 4A and 4B are a logic diagram and a schematic circuit diagram, respectively, of an invertor circuit included in the CMOS digital level shifter circuit shown in Fig. 3A; Fig. 5 is a diagram showing an input-output characteristic of the invertor circuit shown in Fig. 4B; Fig. 6 is a butterfly plot diagram of a latch circuit consisting of a pair of such invertors as shown in Fig. 4B when the input voltage Vin is higher than the sum of voltages VinB and Vthp; Fig. 7 depicts a diagram of an input-output characteristic for explaining the conditions under which the output voltage moves to one stable operating point only; Fig. 8 is a diagram showing voltage waveforms at different locations of the circuit shown in Fig. 3A during operation; and Fig. 9 is a schematic diagram of a BICMOS digital level shifter circuit showing a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to Figs. 3A and 3B, there is shown in schematic diagram and logic diagram, respectively, a level shifter circuit according to the EP-A-0 411 818 to which a modification is applied. As can clearly be seen from Fig. 3A, the level shifter circuit shown includes a flip-flop constituted from a CMOS invertor as a basic circuit. In particular, the level shifter circuit shown includes a first CMOS invertor 1 as a basic CMOS invertor compo ed of an nMOS transistor Tr1 and a pMOS transistor Tr3. Another nMOS transistor Tr7 is interposed between the nMOS transistor Trl and the pMOS transistor Tr3. The level shifter circuit further includes a second CMOS invertor 2 as another basic CMOS invertor composed of an nMOS transistor Tr2 and a pMOS transistor Tr4. Another nMOS transistor Tr8 is interposed between the nMOS transistor Tr2 and the pMOS transistor Tr4. The transistors Tr7 and Tr8 interposed in the CMOS invertors 1 and 2 are provided to limit through current which flows through the invertors 1 and 2, respectively. Meanwhile, MOS transistors having a sufficiently higher driving capacity than the thus interposed transistors Tr7 and Tr8 are used as the transistors Tr1, Tr2 and Tr3, Tr4 constituting the CMOS invertors 1 and 2, respectively. Figs. 4A and 4B show in logic diagram and circuit diagram. respectively, an invertor constituting a flip-flop. and Fig. 5 shows an input-output characteristic of the invertor. The input threshold value of the invertor shown in Figs. 4A and 4B is almost equal to Vin - Vthp, where Vin is an input voltage and Vthp is a voltage Vth of a pMOS transistor. When a flip-flop is constituted using the invertor, the butterfly plot when Vin = VinB is such as shown in a characteristic diagram of Fig. 6. As can apparently be seen from Fig. 6, when Vin = VinB, there are two stable points at which data are latched. However, when the input voltage is equal to Vin = VinB + Vthp + α as shown in a characteristic diagram of Fig. 7, there is only one stable point, to which the output voltage moves. Accordingly, in this instance, the input amplitude Vthp + α is level shifted to the output amplitude Vin. It is to be noted that, when data are to be inverted, the voltage VinB should be set to VinB = Vin + Vthp + α. Fig. 8 shows in waveform diagram a level shifting operation of the level shifter circuit shown in Fig. 3A. Referring to Fig. 8, a characteristic curve (a) indicates Vin while a broken line characteristic curve (b) indicates Vout. Meanwhile, a further characteristic curve (c) shown by an alternate long and short dash line indicates VinB while a still further characteristic curve (d) shown by an alternate long and two short dashes line indicates VoutB. As can apparently be seen from Fig. 8, the level shifter circuit of the present embodiment shifts the level of an input amplitude of 1.4 volts or so to an output amplitude of 5 volts. Since level shifting is performed in such a manner as described above, the level shifter circuit has the following characteristics. In particular, (1) dc consumption current will not flow: (2) an output driving capacity for a next stage can be increased by increasing the current driving capacity of each transistor element, and high speed operation can be achieved without paying attention to dc current: (3) however, an input amplitude higher than Vthp is required and the input sensitivity cannot be set to a value lower than Vthp: and (4) the output amplitude will fully swing from the input voltage levels Vin and VinB to the ground GND. Fig. 9 shows a preferred embodiment of the invention resulting from a modification to the level shifter circuit shown in Figs. 3A and 3B. Referring to Fig. 9, the level shifter circuit according to the invention additionally includes a pair of bipolar transistors Q1 and Q2 provided together with pull-up pMOS transistors Tr5 and Tr6, respectively, to assure an increased output driving capacity. In such a circuit which does not include the bipolar transistors Q1 and Q2 and the pull-up pMOS transitors Tr5 and Tr6 as the circuit shown in Fig. 3, in order to raise the speed of an output pulling up operation, the pMOS transistors Tr3 and Tr4 must be increased considerably in size. However, where such bipolar transistors Q1 and Q2 together with pull-up pMOS transistors Tr5 and Tr6 are additionally provided as in the circuit shown in Fig. 9, a higher speed operation of the pMOS transistors Tr3 and Tr4 can be achieved without increasing the sizes of them. Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the scope of the invention as set forth in the claims.

Claims: A voltage level shifter circuit, comprising: a first IGFET (Tr1) of a first conductivity type having the drain-source path connected between a first output node (VoutB) and a first reference power source; a second IGFET (Tr2) of the first conductivity type having the drain-source path connected between a second output node (Vout) and said first reference power source; a third IGFET (Tr3) of a second conductivity type opposite to the first conductivity type having the drain-source path connected between said first output node (VoutB) and a first input node (VinB); and a fourth IGFET (Tr4) of the second conductivity type having the drain-source path connected between said second output node (Vout) and a second input node (Vin); said second output node (Vout) being connected to the gate electrodes of said first and third IGFETs (Tr1, Tr3) while said first output node (VoutB) is connected to the gate electrodes of said second and fourth IGFETs (Tr2, Tr4); the first and second input nodes (VinB, Vin) constituting the input of the voltage level shifter circuit; and the first and second output nodes (VoutB, Vout) constituting the output of the voltage level shifter circuit, characterized in that said voltage level shifter circuit further comprises a fifth IGFET (Tr5) of which the source is connected to said first input node (VinB) and the gate electrode is connected to the gate electrode of said third IGFET (Tr3), a first bipolar transistor (Q1) of which the base is connected to the drain of said fifth IGFET (Tr5), the emitter is connected to said first output node (VoutB) and the collector is connected to a second power source, a sixth IGFET (Tr6) of which the source is connected to said second input node (Vin) and the gate electrode is connected to the gate electrode of said fourth IGFET (Tr4), and a second bipolar transistor (Q2) of which the base is connected to the drain of said sixth IGFET (Tr6), the emitter is connected to said second output node (Vout), and the collector is connected to said second power source. A voltage level shifter circuit according to claim 1, characterized by first voltage dropping means (Tr7) connected in series to the drain-souce path of said first IGFET (Tr1) between said first output node (VoutB) and said first reference power source; second voltage dropping means (Tr8) connected in series to the drain-source path of said second IGFET (Tr2) between said second output node (Vout) and said first reference power source. A voltage level shifter circuit according to claim 2, wherein said first and second voltage dropping means (Tr7, Tr8) include a seventh and eighth IGFET (Tr7, Tr8) of the first conductivity type having the drain-source path connected in series to the drain-source path of said first and second IGFETs, respectively, a voltage higher than the voltage level of said reference power source being applied to the gate electrodes of said seventh and eighth IGFET (Tr7, Tr8) to keep said seventh and eighth IGFET (Tr7, Tr8) in a conducting state.

Inventors: USUKI HIDEKI, USUKI, HIDEKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1992
Main classification: H03K19
IPC codes: H03K19, H03K3